drivers/net/mlx5/mlx5_flow_aso.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2020 Mellanox Technologies, Ltd
   3  */
   4 #include <mlx5_prm.h>
   5 #include <rte_malloc.h>
   6 #include <rte_cycles.h>
   7 #include <rte_eal_paging.h>
   8
   9 #include <mlx5_malloc.h>
  10 #include <mlx5_common_os.h>
  11 #include <mlx5_common_devx.h>
  12
  13 #include "mlx5.h"
  14 #include "mlx5_flow.h"
  15
  16 /**
  17  * Destroy Completion Queue used for ASO access.
  18  *
  19  * @param[in] cq
  20  *   ASO CQ to destroy.
  21  */
  22 static void
  23 mlx5_aso_cq_destroy(struct mlx5_aso_cq *cq)
  24 {
  25         if (cq->cq_obj.cq)
  26                 mlx5_devx_cq_destroy(&cq->cq_obj);
  27         memset(cq, 0, sizeof(*cq));
  28 }
  29
  30 /**
  31  * Create Completion Queue used for ASO access.
  32  *
  33  * @param[in] ctx
  34  *   Context returned from mlx5 open_device() glue function.
  35  * @param[in/out] cq
  36  *   Pointer to CQ to create.
  37  * @param[in] log_desc_n
  38  *   Log of number of descriptors in queue.
  39  * @param[in] socket
  40  *   Socket to use for allocation.
  41  * @param[in] uar_page_id
  42  *   UAR page ID to use.
  43  *
  44  * @return
  45  *   0 on success, a negative errno value otherwise and rte_errno is set.
  46  */
  47 static int
  48 mlx5_aso_cq_create(void *ctx, struct mlx5_aso_cq *cq, uint16_t log_desc_n,
  49                    int socket, int uar_page_id)
  50 {
  51         struct mlx5_devx_cq_attr attr = {
  52                 .uar_page_id = uar_page_id,
  53         };
  54
  55         cq->log_desc_n = log_desc_n;
  56         cq->cq_ci = 0;
  57         return mlx5_devx_cq_create(ctx, &cq->cq_obj, log_desc_n, &attr, socket);
  58 }
  59
  60 /**
  61  * Free MR resources.
  62  *
  63  * @param[in] mr
  64  *   MR to free.
  65  */
  66 static void
  67 mlx5_aso_devx_dereg_mr(struct mlx5_aso_devx_mr *mr)
  68 {
  69         claim_zero(mlx5_devx_cmd_destroy(mr->mkey));
  70         if (!mr->is_indirect && mr->umem)
  71                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
  72         mlx5_free(mr->buf);
  73         memset(mr, 0, sizeof(*mr));
  74 }
  75
  76 /**
  77  * Register Memory Region.
  78  *
  79  * @param[in] ctx
  80  *   Context returned from mlx5 open_device() glue function.
  81  * @param[in] length
  82  *   Size of MR buffer.
  83  * @param[in/out] mr
  84  *   Pointer to MR to create.
  85  * @param[in] socket
  86  *   Socket to use for allocation.
  87  * @param[in] pdn
  88  *   Protection Domain number to use.
  89  *
  90  * @return
  91  *   0 on success, a negative errno value otherwise and rte_errno is set.
  92  */
  93 static int
  94 mlx5_aso_devx_reg_mr(void *ctx, size_t length, struct mlx5_aso_devx_mr *mr,
  95                      int socket, int pdn)
  96 {
  97         struct mlx5_devx_mkey_attr mkey_attr;
  98
  99         mr->buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, length, 4096,
 100                               socket);
 101         if (!mr->buf) {
 102                 DRV_LOG(ERR, "Failed to create ASO bits mem for MR by Devx.");
 103                 return -1;
 104         }
 105         mr->umem = mlx5_os_umem_reg(ctx, mr->buf, length,
 106                                                  IBV_ACCESS_LOCAL_WRITE);
 107         if (!mr->umem) {
 108                 DRV_LOG(ERR, "Failed to register Umem for MR by Devx.");
 109                 goto error;
 110         }
 111         mkey_attr.addr = (uintptr_t)mr->buf;
 112         mkey_attr.size = length;
 113         mkey_attr.umem_id = mlx5_os_get_umem_id(mr->umem);
 114         mkey_attr.pd = pdn;
 115         mkey_attr.pg_access = 1;
 116         mkey_attr.klm_array = NULL;
 117         mkey_attr.klm_num = 0;
 118         mkey_attr.relaxed_ordering_read = 0;
 119         mkey_attr.relaxed_ordering_write = 0;
 120         mr->mkey = mlx5_devx_cmd_mkey_create(ctx, &mkey_attr);
 121         if (!mr->mkey) {
 122                 DRV_LOG(ERR, "Failed to create direct Mkey.");
 123                 goto error;
 124         }
 125         mr->length = length;
 126         mr->is_indirect = false;
 127         return 0;
 128 error:
 129         if (mr->umem)
 130                 claim_zero(mlx5_glue->devx_umem_dereg(mr->umem));
 131         mlx5_free(mr->buf);
 132         return -1;
 133 }
 134
 135 /**
 136  * Destroy Send Queue used for ASO access.
 137  *
 138  * @param[in] sq
 139  *   ASO SQ to destroy.
 140  */
 141 static void
 142 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq)
 143 {
 144         mlx5_devx_sq_destroy(&sq->sq_obj);
 145         mlx5_aso_cq_destroy(&sq->cq);
 146         memset(sq, 0, sizeof(*sq));
 147 }
 148
 149 /**
 150  * Initialize Send Queue used for ASO access.
 151  *
 152  * @param[in] sq
 153  *   ASO SQ to initialize.
 154  */
 155 static void
 156 mlx5_aso_age_init_sq(struct mlx5_aso_sq *sq)
 157 {
 158         volatile struct mlx5_aso_wqe *restrict wqe;
 159         int i;
 160         int size = 1 << sq->log_desc_n;
 161         uint64_t addr;
 162
 163         /* All the next fields state should stay constant. */
 164         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 165                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 166                                                           (sizeof(*wqe) >> 4));
 167                 wqe->aso_cseg.lkey = rte_cpu_to_be_32(sq->mr.mkey->id);
 168                 addr = (uint64_t)((uint64_t *)sq->mr.buf + i *
 169                                             MLX5_ASO_AGE_ACTIONS_PER_POOL / 64);
 170                 wqe->aso_cseg.va_h = rte_cpu_to_be_32((uint32_t)(addr >> 32));
 171                 wqe->aso_cseg.va_l_r = rte_cpu_to_be_32((uint32_t)addr | 1u);
 172                 wqe->aso_cseg.operand_masks = rte_cpu_to_be_32
 173                         (0u |
 174                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 175                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 176                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 177                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 178                 wqe->aso_cseg.data_mask = RTE_BE64(UINT64_MAX);
 179         }
 180 }
 181
 182 /**
 183  * Initialize Send Queue used for ASO flow meter access.
 184  *
 185  * @param[in] sq
 186  *   ASO SQ to initialize.
 187  */
 188 static void
 189 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq)
 190 {
 191         volatile struct mlx5_aso_wqe *restrict wqe;
 192         int i;
 193         int size = 1 << sq->log_desc_n;
 194         uint32_t idx;
 195
 196         /* All the next fields state should stay constant. */
 197         for (i = 0, wqe = &sq->sq_obj.aso_wqes[0]; i < size; ++i, ++wqe) {
 198                 wqe->general_cseg.sq_ds = rte_cpu_to_be_32((sq->sqn << 8) |
 199                                                           (sizeof(*wqe) >> 4));
 200                 wqe->aso_cseg.operand_masks = RTE_BE32(0u |
 201                          (ASO_OPER_LOGICAL_OR << ASO_CSEG_COND_OPER_OFFSET) |
 202                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_1_OPER_OFFSET) |
 203                          (ASO_OP_ALWAYS_TRUE << ASO_CSEG_COND_0_OPER_OFFSET) |
 204                          (BYTEWISE_64BYTE << ASO_CSEG_DATA_MASK_MODE_OFFSET));
 205                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 206                                                          MLX5_COMP_MODE_OFFSET);
 207                 for (idx = 0; idx < MLX5_ASO_METERS_PER_WQE;
 208                         idx++)
 209                         wqe->aso_dseg.mtrs[idx].v_bo_sc_bbog_mm =
 210                                 RTE_BE32((1 << ASO_DSEG_VALID_OFFSET) |
 211                                 (MLX5_FLOW_COLOR_GREEN << ASO_DSEG_SC_OFFSET));
 212         }
 213 }
 214
 215 /**
 216  * Create Send Queue used for ASO access.
 217  *
 218  * @param[in] ctx
 219  *   Context returned from mlx5 open_device() glue function.
 220  * @param[in/out] sq
 221  *   Pointer to SQ to create.
 222  * @param[in] socket
 223  *   Socket to use for allocation.
 224  * @param[in] uar
 225  *   User Access Region object.
 226  * @param[in] pdn
 227  *   Protection Domain number to use.
 228  * @param[in] log_desc_n
 229  *   Log of number of descriptors in queue.
 230  *
 231  * @return
 232  *   0 on success, a negative errno value otherwise and rte_errno is set.
 233  */
 234 static int
 235 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
 236                    void *uar, uint32_t pdn,  uint16_t log_desc_n,
 237                    uint32_t ts_format)
 238 {
 239         struct mlx5_devx_create_sq_attr attr = {
 240                 .user_index = 0xFFFF,
 241                 .wq_attr = (struct mlx5_devx_wq_attr){
 242                         .pd = pdn,
 243                         .uar_page = mlx5_os_get_devx_uar_page_id(uar),
 244                 },
 245                 .ts_format = mlx5_ts_format_conv(ts_format),
 246         };
 247         struct mlx5_devx_modify_sq_attr modify_attr = {
 248                 .state = MLX5_SQC_STATE_RDY,
 249         };
 250         uint16_t log_wqbb_n;
 251         int ret;
 252
 253         if (mlx5_aso_cq_create(ctx, &sq->cq, log_desc_n, socket,
 254                                mlx5_os_get_devx_uar_page_id(uar)))
 255                 goto error;
 256         sq->log_desc_n = log_desc_n;
 257         attr.cqn = sq->cq.cq_obj.cq->id;
 258         /* for mlx5_aso_wqe that is twice the size of mlx5_wqe */
 259         log_wqbb_n = log_desc_n + 1;
 260         ret = mlx5_devx_sq_create(ctx, &sq->sq_obj, log_wqbb_n, &attr, socket);
 261         if (ret) {
 262                 DRV_LOG(ERR, "Can't create SQ object.");
 263                 rte_errno = ENOMEM;
 264                 goto error;
 265         }
 266         ret = mlx5_devx_cmd_modify_sq(sq->sq_obj.sq, &modify_attr);
 267         if (ret) {
 268                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 269                 rte_errno = ENOMEM;
 270                 goto error;
 271         }
 272         sq->pi = 0;
 273         sq->head = 0;
 274         sq->tail = 0;
 275         sq->sqn = sq->sq_obj.sq->id;
 276         sq->uar_addr = mlx5_os_get_devx_uar_reg_addr(uar);
 277         return 0;
 278 error:
 279         mlx5_aso_destroy_sq(sq);
 280         return -1;
 281 }
 282
 283 /**
 284  * API to create and initialize Send Queue used for ASO access.
 285  *
 286  * @param[in] sh
 287  *   Pointer to shared device context.
 288  *
 289  * @return
 290  *   0 on success, a negative errno value otherwise and rte_errno is set.
 291  */
 292 int
 293 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh,
 294                         enum mlx5_access_aso_opc_mod aso_opc_mod)
 295 {
 296         uint32_t sq_desc_n = 1 << MLX5_ASO_QUEUE_LOG_DESC;
 297
 298         switch (aso_opc_mod) {
 299         case ASO_OPC_MOD_FLOW_HIT:
 300                 if (mlx5_aso_devx_reg_mr(sh->ctx,
 301                         (MLX5_ASO_AGE_ACTIONS_PER_POOL / 8) *
 302                         sq_desc_n, &sh->aso_age_mng->aso_sq.mr, 0, sh->pdn))
 303                         return -1;
 304                 if (mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
 305                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 306                                   sh->sq_ts_format)) {
 307                         mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
 308                         return -1;
 309                 }
 310                 mlx5_aso_age_init_sq(&sh->aso_age_mng->aso_sq);
 311                 break;
 312         case ASO_OPC_MOD_POLICER:
 313                 if (mlx5_aso_sq_create(sh->ctx, &sh->mtrmng->sq, 0,
 314                                   sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
 315                                   sh->sq_ts_format))
 316                         return -1;
 317                 mlx5_aso_mtr_init_sq(&sh->mtrmng->sq);
 318                 break;
 319         default:
 320                 DRV_LOG(ERR, "Unknown ASO operation mode");
 321                 return -1;
 322         }
 323         return 0;
 324 }
 325
 326 /**
 327  * API to destroy Send Queue used for ASO access.
 328  *
 329  * @param[in] sh
 330  *   Pointer to shared device context.
 331  */
 332 void
 333 mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh,
 334                                 enum mlx5_access_aso_opc_mod aso_opc_mod)
 335 {
 336         struct mlx5_aso_sq *sq;
 337
 338         switch (aso_opc_mod) {
 339         case ASO_OPC_MOD_FLOW_HIT:
 340                 mlx5_aso_devx_dereg_mr(&sh->aso_age_mng->aso_sq.mr);
 341                 sq = &sh->aso_age_mng->aso_sq;
 342                 break;
 343         case ASO_OPC_MOD_POLICER:
 344                 sq = &sh->mtrmng->sq;
 345                 break;
 346         default:
 347                 DRV_LOG(ERR, "Unknown ASO operation mode");
 348                 return;
 349         }
 350         mlx5_aso_destroy_sq(sq);
 351 }
 352
 353 /**
 354  * Write a burst of WQEs to ASO SQ.
 355  *
 356  * @param[in] mng
 357  *   ASO management data, contains the SQ.
 358  * @param[in] n
 359  *   Index of the last valid pool.
 360  *
 361  * @return
 362  *   Number of WQEs in burst.
 363  */
 364 static uint16_t
 365 mlx5_aso_sq_enqueue_burst(struct mlx5_aso_age_mng *mng, uint16_t n)
 366 {
 367         volatile struct mlx5_aso_wqe *wqe;
 368         struct mlx5_aso_sq *sq = &mng->aso_sq;
 369         struct mlx5_aso_age_pool *pool;
 370         uint16_t size = 1 << sq->log_desc_n;
 371         uint16_t mask = size - 1;
 372         uint16_t max;
 373         uint16_t start_head = sq->head;
 374
 375         max = RTE_MIN(size - (uint16_t)(sq->head - sq->tail), n - sq->next);
 376         if (unlikely(!max))
 377                 return 0;
 378         sq->elts[start_head & mask].burst_size = max;
 379         do {
 380                 wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 381                 rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 382                 /* Fill next WQE. */
 383                 rte_spinlock_lock(&mng->resize_sl);
 384                 pool = mng->pools[sq->next];
 385                 rte_spinlock_unlock(&mng->resize_sl);
 386                 sq->elts[sq->head & mask].pool = pool;
 387                 wqe->general_cseg.misc =
 388                                 rte_cpu_to_be_32(((struct mlx5_devx_obj *)
 389                                                  (pool->flow_hit_aso_obj))->id);
 390                 wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
 391                                                          MLX5_COMP_MODE_OFFSET);
 392                 wqe->general_cseg.opcode = rte_cpu_to_be_32
 393                                                 (MLX5_OPCODE_ACCESS_ASO |
 394                                                  (ASO_OPC_MOD_FLOW_HIT <<
 395                                                   WQE_CSEG_OPC_MOD_OFFSET) |
 396                                                  (sq->pi <<
 397                                                   WQE_CSEG_WQE_INDEX_OFFSET));
 398                 sq->pi += 2; /* Each WQE contains 2 WQEBB's. */
 399                 sq->head++;
 400                 sq->next++;
 401                 max--;
 402         } while (max);
 403         wqe->general_cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 404                                                          MLX5_COMP_MODE_OFFSET);
 405         rte_io_wmb();
 406         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 407         rte_wmb();
 408         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH.*/
 409         rte_wmb();
 410         return sq->elts[start_head & mask].burst_size;
 411 }
 412
 413 /**
 414  * Debug utility function. Dump contents of error CQE and WQE.
 415  *
 416  * @param[in] cqe
 417  *   Error CQE to dump.
 418  * @param[in] wqe
 419  *   Error WQE to dump.
 420  */
 421 static void
 422 mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe)
 423 {
 424         int i;
 425
 426         DRV_LOG(ERR, "Error cqe:");
 427         for (i = 0; i < 16; i += 4)
 428                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 429                         cqe[i + 2], cqe[i + 3]);
 430         DRV_LOG(ERR, "\nError wqe:");
 431         for (i = 0; i < (int)sizeof(struct mlx5_aso_wqe) / 4; i += 4)
 432                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 433                         wqe[i + 2], wqe[i + 3]);
 434 }
 435
 436 /**
 437  * Handle case of error CQE.
 438  *
 439  * @param[in] sq
 440  *   ASO SQ to use.
 441  */
 442 static void
 443 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq)
 444 {
 445         struct mlx5_aso_cq *cq = &sq->cq;
 446         uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1);
 447         volatile struct mlx5_err_cqe *cqe =
 448                         (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx];
 449
 450         cq->errors++;
 451         idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n);
 452         mlx5_aso_dump_err_objs((volatile uint32_t *)cqe,
 453                                (volatile uint32_t *)&sq->sq_obj.aso_wqes[idx]);
 454 }
 455
 456 /**
 457  * Update ASO objects upon completion.
 458  *
 459  * @param[in] sh
 460  *   Shared device context.
 461  * @param[in] n
 462  *   Number of completed ASO objects.
 463  */
 464 static void
 465 mlx5_aso_age_action_update(struct mlx5_dev_ctx_shared *sh, uint16_t n)
 466 {
 467         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 468         struct mlx5_aso_sq *sq = &mng->aso_sq;
 469         struct mlx5_age_info *age_info;
 470         const uint16_t size = 1 << sq->log_desc_n;
 471         const uint16_t mask = size - 1;
 472         const uint64_t curr = MLX5_CURR_TIME_SEC;
 473         uint16_t expected = AGE_CANDIDATE;
 474         uint16_t i;
 475
 476         for (i = 0; i < n; ++i) {
 477                 uint16_t idx = (sq->tail + i) & mask;
 478                 struct mlx5_aso_age_pool *pool = sq->elts[idx].pool;
 479                 uint64_t diff = curr - pool->time_of_last_age_check;
 480                 uint64_t *addr = sq->mr.buf;
 481                 int j;
 482
 483                 addr += idx * MLX5_ASO_AGE_ACTIONS_PER_POOL / 64;
 484                 pool->time_of_last_age_check = curr;
 485                 for (j = 0; j < MLX5_ASO_AGE_ACTIONS_PER_POOL; j++) {
 486                         struct mlx5_aso_age_action *act = &pool->actions[j];
 487                         struct mlx5_age_param *ap = &act->age_params;
 488                         uint8_t byte;
 489                         uint8_t offset;
 490                         uint8_t *u8addr;
 491                         uint8_t hit;
 492
 493                         if (__atomic_load_n(&ap->state, __ATOMIC_RELAXED) !=
 494                                             AGE_CANDIDATE)
 495                                 continue;
 496                         byte = 63 - (j / 8);
 497                         offset = j % 8;
 498                         u8addr = (uint8_t *)addr;
 499                         hit = (u8addr[byte] >> offset) & 0x1;
 500                         if (hit) {
 501                                 __atomic_store_n(&ap->sec_since_last_hit, 0,
 502                                                  __ATOMIC_RELAXED);
 503                         } else {
 504                                 struct mlx5_priv *priv;
 505
 506                                 __atomic_fetch_add(&ap->sec_since_last_hit,
 507                                                    diff, __ATOMIC_RELAXED);
 508                                 /* If timeout passed add to aged-out list. */
 509                                 if (ap->sec_since_last_hit <= ap->timeout)
 510                                         continue;
 511                                 priv =
 512                                 rte_eth_devices[ap->port_id].data->dev_private;
 513                                 age_info = GET_PORT_AGE_INFO(priv);
 514                                 rte_spinlock_lock(&age_info->aged_sl);
 515                                 if (__atomic_compare_exchange_n(&ap->state,
 516                                                                 &expected,
 517                                                                 AGE_TMOUT,
 518                                                                 false,
 519                                                                __ATOMIC_RELAXED,
 520                                                             __ATOMIC_RELAXED)) {
 521                                         LIST_INSERT_HEAD(&age_info->aged_aso,
 522                                                          act, next);
 523                                         MLX5_AGE_SET(age_info,
 524                                                      MLX5_AGE_EVENT_NEW);
 525                                 }
 526                                 rte_spinlock_unlock(&age_info->aged_sl);
 527                         }
 528                 }
 529         }
 530         mlx5_age_event_prepare(sh);
 531 }
 532
 533 /**
 534  * Handle completions from WQEs sent to ASO SQ.
 535  *
 536  * @param[in] sh
 537  *   Shared device context.
 538  *
 539  * @return
 540  *   Number of CQEs handled.
 541  */
 542 static uint16_t
 543 mlx5_aso_completion_handle(struct mlx5_dev_ctx_shared *sh)
 544 {
 545         struct mlx5_aso_age_mng *mng = sh->aso_age_mng;
 546         struct mlx5_aso_sq *sq = &mng->aso_sq;
 547         struct mlx5_aso_cq *cq = &sq->cq;
 548         volatile struct mlx5_cqe *restrict cqe;
 549         const unsigned int cq_size = 1 << cq->log_desc_n;
 550         const unsigned int mask = cq_size - 1;
 551         uint32_t idx;
 552         uint32_t next_idx = cq->cq_ci & mask;
 553         const uint16_t max = (uint16_t)(sq->head - sq->tail);
 554         uint16_t i = 0;
 555         int ret;
 556         if (unlikely(!max))
 557                 return 0;
 558         do {
 559                 idx = next_idx;
 560                 next_idx = (cq->cq_ci + 1) & mask;
 561                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 562                 cqe = &cq->cq_obj.cqes[idx];
 563                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 564                 /*
 565                  * Be sure owner read is done before any other cookie field or
 566                  * opaque field.
 567                  */
 568                 rte_io_rmb();
 569                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 570                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 571                                 break;
 572                         mlx5_aso_cqe_err_handle(sq);
 573                 } else {
 574                         i += sq->elts[(sq->tail + i) & mask].burst_size;
 575                 }
 576                 cq->cq_ci++;
 577         } while (1);
 578         if (likely(i)) {
 579                 mlx5_aso_age_action_update(sh, i);
 580                 sq->tail += i;
 581                 rte_io_wmb();
 582                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 583         }
 584         return i;
 585 }
 586
 587 /**
 588  * Periodically read CQEs and send WQEs to ASO SQ.
 589  *
 590  * @param[in] arg
 591  *   Shared device context containing the ASO SQ.
 592  */
 593 static void
 594 mlx5_flow_aso_alarm(void *arg)
 595 {
 596         struct mlx5_dev_ctx_shared *sh = arg;
 597         struct mlx5_aso_sq *sq = &sh->aso_age_mng->aso_sq;
 598         uint32_t us = 100u;
 599         uint16_t n;
 600
 601         rte_spinlock_lock(&sh->aso_age_mng->resize_sl);
 602         n = sh->aso_age_mng->next;
 603         rte_spinlock_unlock(&sh->aso_age_mng->resize_sl);
 604         mlx5_aso_completion_handle(sh);
 605         if (sq->next == n) {
 606                 /* End of loop: wait 1 second. */
 607                 us = US_PER_S;
 608                 sq->next = 0;
 609         }
 610         mlx5_aso_sq_enqueue_burst(sh->aso_age_mng, n);
 611         if (rte_eal_alarm_set(us, mlx5_flow_aso_alarm, sh))
 612                 DRV_LOG(ERR, "Cannot reinitialize aso alarm.");
 613 }
 614
 615 /**
 616  * API to start ASO access using ASO SQ.
 617  *
 618  * @param[in] sh
 619  *   Pointer to shared device context.
 620  *
 621  * @return
 622  *   0 on success, a negative errno value otherwise and rte_errno is set.
 623  */
 624 int
 625 mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh)
 626 {
 627         if (rte_eal_alarm_set(US_PER_S, mlx5_flow_aso_alarm, sh)) {
 628                 DRV_LOG(ERR, "Cannot reinitialize ASO age alarm.");
 629                 return -rte_errno;
 630         }
 631         return 0;
 632 }
 633
 634 /**
 635  * API to stop ASO access using ASO SQ.
 636  *
 637  * @param[in] sh
 638  *   Pointer to shared device context.
 639  *
 640  * @return
 641  *   0 on success, a negative errno value otherwise and rte_errno is set.
 642  */
 643 int
 644 mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh)
 645 {
 646         int retries = 1024;
 647
 648         if (!sh->aso_age_mng->aso_sq.sq_obj.sq)
 649                 return -EINVAL;
 650         rte_errno = 0;
 651         while (--retries) {
 652                 rte_eal_alarm_cancel(mlx5_flow_aso_alarm, sh);
 653                 if (rte_errno != EINPROGRESS)
 654                         break;
 655                 rte_pause();
 656         }
 657         return -rte_errno;
 658 }
 659
 660 static uint16_t
 661 mlx5_aso_mtr_sq_enqueue_single(struct mlx5_aso_sq *sq,
 662                 struct mlx5_aso_mtr *aso_mtr)
 663 {
 664         volatile struct mlx5_aso_wqe *wqe = NULL;
 665         struct mlx5_flow_meter_info *fm = NULL;
 666         uint16_t size = 1 << sq->log_desc_n;
 667         uint16_t mask = size - 1;
 668         uint16_t res = size - (uint16_t)(sq->head - sq->tail);
 669         uint32_t dseg_idx = 0;
 670         struct mlx5_aso_mtr_pool *pool = NULL;
 671
 672         if (unlikely(!res)) {
 673                 DRV_LOG(ERR, "Fail: SQ is full and no free WQE to send");
 674                 return 0;
 675         }
 676         wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
 677         rte_prefetch0(&sq->sq_obj.aso_wqes[(sq->head + 1) & mask]);
 678         /* Fill next WQE. */
 679         fm = &aso_mtr->fm;
 680         sq->elts[sq->head & mask].mtr = aso_mtr;
 681         pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
 682                         mtrs[aso_mtr->offset]);
 683         wqe->general_cseg.misc = rte_cpu_to_be_32(pool->devx_obj->id +
 684                         (aso_mtr->offset >> 1));
 685         wqe->general_cseg.opcode = rte_cpu_to_be_32(MLX5_OPCODE_ACCESS_ASO |
 686                         (ASO_OPC_MOD_POLICER <<
 687                         WQE_CSEG_OPC_MOD_OFFSET) |
 688                         sq->pi << WQE_CSEG_WQE_INDEX_OFFSET);
 689         /* There are 2 meters in one ASO cache line. */
 690         dseg_idx = aso_mtr->offset & 0x1;
 691         wqe->aso_cseg.data_mask =
 692                 RTE_BE64(MLX5_IFC_FLOW_METER_PARAM_MASK << (32 * !dseg_idx));
 693         if (fm->is_enable) {
 694                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 695                         fm->profile->srtcm_prm.cbs_cir;
 696                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir =
 697                         fm->profile->srtcm_prm.ebs_eir;
 698         } else {
 699                 wqe->aso_dseg.mtrs[dseg_idx].cbs_cir =
 700                         RTE_BE32(MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL);
 701                 wqe->aso_dseg.mtrs[dseg_idx].ebs_eir = 0;
 702         }
 703         sq->head++;
 704         sq->pi += 2;/* Each WQE contains 2 WQEBB's. */
 705         rte_io_wmb();
 706         sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(sq->pi);
 707         rte_wmb();
 708         *sq->uar_addr = *(volatile uint64_t *)wqe; /* Assume 64 bit ARCH. */
 709         rte_wmb();
 710         return 1;
 711 }
 712
 713 static void
 714 mlx5_aso_mtrs_status_update(struct mlx5_aso_sq *sq, uint16_t aso_mtrs_nums)
 715 {
 716         uint16_t size = 1 << sq->log_desc_n;
 717         uint16_t mask = size - 1;
 718         uint16_t i;
 719         struct mlx5_aso_mtr *aso_mtr = NULL;
 720         uint8_t exp_state = ASO_METER_WAIT;
 721
 722         for (i = 0; i < aso_mtrs_nums; ++i) {
 723                 aso_mtr = sq->elts[(sq->tail + i) & mask].mtr;
 724                 MLX5_ASSERT(aso_mtr);
 725                 (void)__atomic_compare_exchange_n(&aso_mtr->state,
 726                                 &exp_state, ASO_METER_READY,
 727                                 false, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
 728         }
 729 }
 730
 731 static void
 732 mlx5_aso_mtr_completion_handle(struct mlx5_aso_sq *sq)
 733 {
 734         struct mlx5_aso_cq *cq = &sq->cq;
 735         volatile struct mlx5_cqe *restrict cqe;
 736         const unsigned int cq_size = 1 << cq->log_desc_n;
 737         const unsigned int mask = cq_size - 1;
 738         uint32_t idx;
 739         uint32_t next_idx = cq->cq_ci & mask;
 740         const uint16_t max = (uint16_t)(sq->head - sq->tail);
 741         uint16_t n = 0;
 742         int ret;
 743
 744         if (unlikely(!max))
 745                 return;
 746         do {
 747                 idx = next_idx;
 748                 next_idx = (cq->cq_ci + 1) & mask;
 749                 rte_prefetch0(&cq->cq_obj.cqes[next_idx]);
 750                 cqe = &cq->cq_obj.cqes[idx];
 751                 ret = check_cqe(cqe, cq_size, cq->cq_ci);
 752                 /*
 753                  * Be sure owner read is done before any other cookie field or
 754                  * opaque field.
 755                  */
 756                 rte_io_rmb();
 757                 if (ret != MLX5_CQE_STATUS_SW_OWN) {
 758                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 759                                 break;
 760                         mlx5_aso_cqe_err_handle(sq);
 761                 } else {
 762                         n++;
 763                 }
 764                 cq->cq_ci++;
 765         } while (1);
 766         if (likely(n)) {
 767                 mlx5_aso_mtrs_status_update(sq, n);
 768                 sq->tail += n;
 769                 rte_io_wmb();
 770                 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->cq_ci);
 771         }
 772 }
 773
 774 /**
 775  * Update meter parameter by send WQE.
 776  *
 777  * @param[in] dev
 778  *   Pointer to Ethernet device.
 779  * @param[in] priv
 780  *   Pointer to mlx5 private data structure.
 781  * @param[in] fm
 782  *   Pointer to flow meter to be modified.
 783  *
 784  * @return
 785  *   0 on success, a negative errno value otherwise and rte_errno is set.
 786  */
 787 int
 788 mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh,
 789                         struct mlx5_aso_mtr *mtr)
 790 {
 791         struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
 792         uint32_t poll_wqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 793
 794         do {
 795                 mlx5_aso_mtr_completion_handle(sq);
 796                 if (mlx5_aso_mtr_sq_enqueue_single(sq, mtr))
 797                         return 0;
 798                 /* Waiting for wqe resource. */
 799                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 800         } while (--poll_wqe_times);
 801         DRV_LOG(ERR, "Fail to send WQE for ASO meter %d",
 802                         mtr->fm.meter_id);
 803         return -1;
 804 }
 805
 806 /**
 807  * Wait for meter to be ready.
 808  *
 809  * @param[in] dev
 810  *   Pointer to Ethernet device.
 811  * @param[in] priv
 812  *   Pointer to mlx5 private data structure.
 813  * @param[in] fm
 814  *   Pointer to flow meter to be modified.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 int
 820 mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh,
 821                         struct mlx5_aso_mtr *mtr)
 822 {
 823         struct mlx5_aso_sq *sq = &sh->mtrmng->sq;
 824         uint32_t poll_cqe_times = MLX5_MTR_POLL_WQE_CQE_TIMES;
 825
 826         if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 827                                             ASO_METER_READY)
 828                 return 0;
 829         do {
 830                 mlx5_aso_mtr_completion_handle(sq);
 831                 if (__atomic_load_n(&mtr->state, __ATOMIC_RELAXED) ==
 832                                             ASO_METER_READY)
 833                         return 0;
 834                 /* Waiting for CQE ready. */
 835                 rte_delay_us_sleep(MLX5_ASO_WQE_CQE_RESPONSE_DELAY);
 836         } while (--poll_cqe_times);
 837         DRV_LOG(ERR, "Fail to poll CQE ready for ASO meter %d",
 838                         mtr->fm.meter_id);
 839         return -1;
 840 }