1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
53 /* VLAN header definitions */
54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
74 struct mlx5_flow_tbl_resource *tbl);
77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
80 * Initialize flow attributes structure according to flow items' types.
82 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
83 * mode. For tunnel mode, the items to be modified are the outermost ones.
86 * Pointer to item specification.
88 * Pointer to flow attributes structure.
90 * Pointer to the sub flow.
91 * @param[in] tunnel_decap
92 * Whether action is after tunnel decapsulation.
95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
96 struct mlx5_flow *dev_flow, bool tunnel_decap)
98 uint64_t layers = dev_flow->handle->layers;
101 * If layers is already initialized, it means this dev_flow is the
102 * suffix flow, the layers flags is set by the prefix flow. Need to
103 * use the layer flags from prefix flow as the suffix flow may not
104 * have the user defined items as the flow is split.
107 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
109 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
111 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
113 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
118 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
119 uint8_t next_protocol = 0xff;
120 switch (item->type) {
121 case RTE_FLOW_ITEM_TYPE_GRE:
122 case RTE_FLOW_ITEM_TYPE_NVGRE:
123 case RTE_FLOW_ITEM_TYPE_VXLAN:
124 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
125 case RTE_FLOW_ITEM_TYPE_GENEVE:
126 case RTE_FLOW_ITEM_TYPE_MPLS:
130 case RTE_FLOW_ITEM_TYPE_IPV4:
133 if (item->mask != NULL &&
134 ((const struct rte_flow_item_ipv4 *)
135 item->mask)->hdr.next_proto_id)
137 ((const struct rte_flow_item_ipv4 *)
138 (item->spec))->hdr.next_proto_id &
139 ((const struct rte_flow_item_ipv4 *)
140 (item->mask))->hdr.next_proto_id;
141 if ((next_protocol == IPPROTO_IPIP ||
142 next_protocol == IPPROTO_IPV6) && tunnel_decap)
145 case RTE_FLOW_ITEM_TYPE_IPV6:
148 if (item->mask != NULL &&
149 ((const struct rte_flow_item_ipv6 *)
150 item->mask)->hdr.proto)
152 ((const struct rte_flow_item_ipv6 *)
153 (item->spec))->hdr.proto &
154 ((const struct rte_flow_item_ipv6 *)
155 (item->mask))->hdr.proto;
156 if ((next_protocol == IPPROTO_IPIP ||
157 next_protocol == IPPROTO_IPV6) && tunnel_decap)
160 case RTE_FLOW_ITEM_TYPE_UDP:
164 case RTE_FLOW_ITEM_TYPE_TCP:
176 * Convert rte_mtr_color to mlx5 color.
185 rte_col_2_mlx5_col(enum rte_color rcol)
188 case RTE_COLOR_GREEN:
189 return MLX5_FLOW_COLOR_GREEN;
190 case RTE_COLOR_YELLOW:
191 return MLX5_FLOW_COLOR_YELLOW;
193 return MLX5_FLOW_COLOR_RED;
197 return MLX5_FLOW_COLOR_UNDEFINED;
200 struct field_modify_info {
201 uint32_t size; /* Size of field in protocol header, in bytes. */
202 uint32_t offset; /* Offset of field in protocol header, in bytes. */
203 enum mlx5_modification_field id;
206 struct field_modify_info modify_eth[] = {
207 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
208 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
209 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
210 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
214 struct field_modify_info modify_vlan_out_first_vid[] = {
215 /* Size in bits !!! */
216 {12, 0, MLX5_MODI_OUT_FIRST_VID},
220 struct field_modify_info modify_ipv4[] = {
221 {1, 1, MLX5_MODI_OUT_IP_DSCP},
222 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
223 {4, 12, MLX5_MODI_OUT_SIPV4},
224 {4, 16, MLX5_MODI_OUT_DIPV4},
228 struct field_modify_info modify_ipv6[] = {
229 {1, 0, MLX5_MODI_OUT_IP_DSCP},
230 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
231 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
232 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
233 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
234 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
235 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
236 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
237 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
238 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
242 struct field_modify_info modify_udp[] = {
243 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
244 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
248 struct field_modify_info modify_tcp[] = {
249 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
250 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
251 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
252 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
258 uint8_t next_protocol, uint64_t *item_flags,
261 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
262 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
263 if (next_protocol == IPPROTO_IPIP) {
264 *item_flags |= MLX5_FLOW_LAYER_IPIP;
267 if (next_protocol == IPPROTO_IPV6) {
268 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
274 * Acquire the synchronizing object to protect multithreaded access
275 * to shared dv context. Lock occurs only if context is actually
276 * shared, i.e. we have multiport IB device and representors are
280 * Pointer to the rte_eth_dev structure.
283 flow_dv_shared_lock(struct rte_eth_dev *dev)
285 struct mlx5_priv *priv = dev->data->dev_private;
286 struct mlx5_dev_ctx_shared *sh = priv->sh;
288 if (sh->dv_refcnt > 1) {
291 ret = pthread_mutex_lock(&sh->dv_mutex);
298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
300 struct mlx5_priv *priv = dev->data->dev_private;
301 struct mlx5_dev_ctx_shared *sh = priv->sh;
303 if (sh->dv_refcnt > 1) {
306 ret = pthread_mutex_unlock(&sh->dv_mutex);
312 /* Update VLAN's VID/PCP based on input rte_flow_action.
315 * Pointer to struct rte_flow_action.
317 * Pointer to struct rte_vlan_hdr.
320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
321 struct rte_vlan_hdr *vlan)
324 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
326 ((const struct rte_flow_action_of_set_vlan_pcp *)
327 action->conf)->vlan_pcp;
328 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
330 vlan->vlan_tci |= vlan_tci;
331 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
332 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
333 vlan->vlan_tci |= rte_be_to_cpu_16
334 (((const struct rte_flow_action_of_set_vlan_vid *)
335 action->conf)->vlan_vid);
340 * Fetch 1, 2, 3 or 4 byte field from the byte array
341 * and return as unsigned integer in host-endian format.
344 * Pointer to data array.
346 * Size of field to extract.
349 * converted field in host endian format.
351 static inline uint32_t
352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
364 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = (ret << 8) | *(data + sizeof(uint16_t));
368 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
379 * Convert modify-header action to DV specification.
381 * Data length of each action is determined by provided field description
382 * and the item mask. Data bit offset and width of each action is determined
383 * by provided item mask.
386 * Pointer to item specification.
388 * Pointer to field modification information.
389 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
390 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
393 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
394 * Negative offset value sets the same offset as source offset.
395 * size field is ignored, value is taken from source field.
396 * @param[in,out] resource
397 * Pointer to the modify-header resource.
399 * Type of modification.
401 * Pointer to the error structure.
404 * 0 on success, a negative errno value otherwise and rte_errno is set.
407 flow_dv_convert_modify_action(struct rte_flow_item *item,
408 struct field_modify_info *field,
409 struct field_modify_info *dcopy,
410 struct mlx5_flow_dv_modify_hdr_resource *resource,
411 uint32_t type, struct rte_flow_error *error)
413 uint32_t i = resource->actions_num;
414 struct mlx5_modification_cmd *actions = resource->actions;
417 * The item and mask are provided in big-endian format.
418 * The fields should be presented as in big-endian format either.
419 * Mask must be always present, it defines the actual field width.
421 MLX5_ASSERT(item->mask);
422 MLX5_ASSERT(field->size);
429 if (i >= MLX5_MAX_MODIFY_NUM)
430 return rte_flow_error_set(error, EINVAL,
431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
432 "too many items to modify");
433 /* Fetch variable byte size mask from the array. */
434 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
435 field->offset, field->size);
440 /* Deduce actual data width in bits from mask value. */
441 off_b = rte_bsf32(mask);
442 size_b = sizeof(uint32_t) * CHAR_BIT -
443 off_b - __builtin_clz(mask);
445 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
446 actions[i] = (struct mlx5_modification_cmd) {
452 /* Convert entire record to expected big-endian format. */
453 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
454 if (type == MLX5_MODIFICATION_TYPE_COPY) {
456 actions[i].dst_field = dcopy->id;
457 actions[i].dst_offset =
458 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
459 /* Convert entire record to big-endian format. */
460 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
462 MLX5_ASSERT(item->spec);
463 data = flow_dv_fetch_field((const uint8_t *)item->spec +
464 field->offset, field->size);
465 /* Shift out the trailing masked bits from data. */
466 data = (data & mask) >> off_b;
467 actions[i].data1 = rte_cpu_to_be_32(data);
471 } while (field->size);
472 if (resource->actions_num == i)
473 return rte_flow_error_set(error, EINVAL,
474 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
475 "invalid modification flow item");
476 resource->actions_num = i;
481 * Convert modify-header set IPv4 address action to DV specification.
483 * @param[in,out] resource
484 * Pointer to the modify-header resource.
486 * Pointer to action specification.
488 * Pointer to the error structure.
491 * 0 on success, a negative errno value otherwise and rte_errno is set.
494 flow_dv_convert_action_modify_ipv4
495 (struct mlx5_flow_dv_modify_hdr_resource *resource,
496 const struct rte_flow_action *action,
497 struct rte_flow_error *error)
499 const struct rte_flow_action_set_ipv4 *conf =
500 (const struct rte_flow_action_set_ipv4 *)(action->conf);
501 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
502 struct rte_flow_item_ipv4 ipv4;
503 struct rte_flow_item_ipv4 ipv4_mask;
505 memset(&ipv4, 0, sizeof(ipv4));
506 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
507 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
508 ipv4.hdr.src_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
511 ipv4.hdr.dst_addr = conf->ipv4_addr;
512 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
515 item.mask = &ipv4_mask;
516 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
517 MLX5_MODIFICATION_TYPE_SET, error);
521 * Convert modify-header set IPv6 address action to DV specification.
523 * @param[in,out] resource
524 * Pointer to the modify-header resource.
526 * Pointer to action specification.
528 * Pointer to the error structure.
531 * 0 on success, a negative errno value otherwise and rte_errno is set.
534 flow_dv_convert_action_modify_ipv6
535 (struct mlx5_flow_dv_modify_hdr_resource *resource,
536 const struct rte_flow_action *action,
537 struct rte_flow_error *error)
539 const struct rte_flow_action_set_ipv6 *conf =
540 (const struct rte_flow_action_set_ipv6 *)(action->conf);
541 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
542 struct rte_flow_item_ipv6 ipv6;
543 struct rte_flow_item_ipv6 ipv6_mask;
545 memset(&ipv6, 0, sizeof(ipv6));
546 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
547 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
548 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
549 sizeof(ipv6.hdr.src_addr));
550 memcpy(&ipv6_mask.hdr.src_addr,
551 &rte_flow_item_ipv6_mask.hdr.src_addr,
552 sizeof(ipv6.hdr.src_addr));
554 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
555 sizeof(ipv6.hdr.dst_addr));
556 memcpy(&ipv6_mask.hdr.dst_addr,
557 &rte_flow_item_ipv6_mask.hdr.dst_addr,
558 sizeof(ipv6.hdr.dst_addr));
561 item.mask = &ipv6_mask;
562 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
563 MLX5_MODIFICATION_TYPE_SET, error);
567 * Convert modify-header set MAC address action to DV specification.
569 * @param[in,out] resource
570 * Pointer to the modify-header resource.
572 * Pointer to action specification.
574 * Pointer to the error structure.
577 * 0 on success, a negative errno value otherwise and rte_errno is set.
580 flow_dv_convert_action_modify_mac
581 (struct mlx5_flow_dv_modify_hdr_resource *resource,
582 const struct rte_flow_action *action,
583 struct rte_flow_error *error)
585 const struct rte_flow_action_set_mac *conf =
586 (const struct rte_flow_action_set_mac *)(action->conf);
587 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
588 struct rte_flow_item_eth eth;
589 struct rte_flow_item_eth eth_mask;
591 memset(ð, 0, sizeof(eth));
592 memset(ð_mask, 0, sizeof(eth_mask));
593 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
594 memcpy(ð.src.addr_bytes, &conf->mac_addr,
595 sizeof(eth.src.addr_bytes));
596 memcpy(ð_mask.src.addr_bytes,
597 &rte_flow_item_eth_mask.src.addr_bytes,
598 sizeof(eth_mask.src.addr_bytes));
600 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
601 sizeof(eth.dst.addr_bytes));
602 memcpy(ð_mask.dst.addr_bytes,
603 &rte_flow_item_eth_mask.dst.addr_bytes,
604 sizeof(eth_mask.dst.addr_bytes));
607 item.mask = ð_mask;
608 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
609 MLX5_MODIFICATION_TYPE_SET, error);
613 * Convert modify-header set VLAN VID action to DV specification.
615 * @param[in,out] resource
616 * Pointer to the modify-header resource.
618 * Pointer to action specification.
620 * Pointer to the error structure.
623 * 0 on success, a negative errno value otherwise and rte_errno is set.
626 flow_dv_convert_action_modify_vlan_vid
627 (struct mlx5_flow_dv_modify_hdr_resource *resource,
628 const struct rte_flow_action *action,
629 struct rte_flow_error *error)
631 const struct rte_flow_action_of_set_vlan_vid *conf =
632 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
633 int i = resource->actions_num;
634 struct mlx5_modification_cmd *actions = resource->actions;
635 struct field_modify_info *field = modify_vlan_out_first_vid;
637 if (i >= MLX5_MAX_MODIFY_NUM)
638 return rte_flow_error_set(error, EINVAL,
639 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
640 "too many items to modify");
641 actions[i] = (struct mlx5_modification_cmd) {
642 .action_type = MLX5_MODIFICATION_TYPE_SET,
644 .length = field->size,
645 .offset = field->offset,
647 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
648 actions[i].data1 = conf->vlan_vid;
649 actions[i].data1 = actions[i].data1 << 16;
650 resource->actions_num = ++i;
655 * Convert modify-header set TP action to DV specification.
657 * @param[in,out] resource
658 * Pointer to the modify-header resource.
660 * Pointer to action specification.
662 * Pointer to rte_flow_item objects list.
664 * Pointer to flow attributes structure.
665 * @param[in] dev_flow
666 * Pointer to the sub flow.
667 * @param[in] tunnel_decap
668 * Whether action is after tunnel decapsulation.
670 * Pointer to the error structure.
673 * 0 on success, a negative errno value otherwise and rte_errno is set.
676 flow_dv_convert_action_modify_tp
677 (struct mlx5_flow_dv_modify_hdr_resource *resource,
678 const struct rte_flow_action *action,
679 const struct rte_flow_item *items,
680 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
681 bool tunnel_decap, struct rte_flow_error *error)
683 const struct rte_flow_action_set_tp *conf =
684 (const struct rte_flow_action_set_tp *)(action->conf);
685 struct rte_flow_item item;
686 struct rte_flow_item_udp udp;
687 struct rte_flow_item_udp udp_mask;
688 struct rte_flow_item_tcp tcp;
689 struct rte_flow_item_tcp tcp_mask;
690 struct field_modify_info *field;
693 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
695 memset(&udp, 0, sizeof(udp));
696 memset(&udp_mask, 0, sizeof(udp_mask));
697 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
698 udp.hdr.src_port = conf->port;
699 udp_mask.hdr.src_port =
700 rte_flow_item_udp_mask.hdr.src_port;
702 udp.hdr.dst_port = conf->port;
703 udp_mask.hdr.dst_port =
704 rte_flow_item_udp_mask.hdr.dst_port;
706 item.type = RTE_FLOW_ITEM_TYPE_UDP;
708 item.mask = &udp_mask;
711 MLX5_ASSERT(attr->tcp);
712 memset(&tcp, 0, sizeof(tcp));
713 memset(&tcp_mask, 0, sizeof(tcp_mask));
714 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
715 tcp.hdr.src_port = conf->port;
716 tcp_mask.hdr.src_port =
717 rte_flow_item_tcp_mask.hdr.src_port;
719 tcp.hdr.dst_port = conf->port;
720 tcp_mask.hdr.dst_port =
721 rte_flow_item_tcp_mask.hdr.dst_port;
723 item.type = RTE_FLOW_ITEM_TYPE_TCP;
725 item.mask = &tcp_mask;
728 return flow_dv_convert_modify_action(&item, field, NULL, resource,
729 MLX5_MODIFICATION_TYPE_SET, error);
733 * Convert modify-header set TTL action to DV specification.
735 * @param[in,out] resource
736 * Pointer to the modify-header resource.
738 * Pointer to action specification.
740 * Pointer to rte_flow_item objects list.
742 * Pointer to flow attributes structure.
743 * @param[in] dev_flow
744 * Pointer to the sub flow.
745 * @param[in] tunnel_decap
746 * Whether action is after tunnel decapsulation.
748 * Pointer to the error structure.
751 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 flow_dv_convert_action_modify_ttl
755 (struct mlx5_flow_dv_modify_hdr_resource *resource,
756 const struct rte_flow_action *action,
757 const struct rte_flow_item *items,
758 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
759 bool tunnel_decap, struct rte_flow_error *error)
761 const struct rte_flow_action_set_ttl *conf =
762 (const struct rte_flow_action_set_ttl *)(action->conf);
763 struct rte_flow_item item;
764 struct rte_flow_item_ipv4 ipv4;
765 struct rte_flow_item_ipv4 ipv4_mask;
766 struct rte_flow_item_ipv6 ipv6;
767 struct rte_flow_item_ipv6 ipv6_mask;
768 struct field_modify_info *field;
771 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
773 memset(&ipv4, 0, sizeof(ipv4));
774 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
775 ipv4.hdr.time_to_live = conf->ttl_value;
776 ipv4_mask.hdr.time_to_live = 0xFF;
777 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
779 item.mask = &ipv4_mask;
782 MLX5_ASSERT(attr->ipv6);
783 memset(&ipv6, 0, sizeof(ipv6));
784 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
785 ipv6.hdr.hop_limits = conf->ttl_value;
786 ipv6_mask.hdr.hop_limits = 0xFF;
787 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
789 item.mask = &ipv6_mask;
792 return flow_dv_convert_modify_action(&item, field, NULL, resource,
793 MLX5_MODIFICATION_TYPE_SET, error);
797 * Convert modify-header decrement TTL action to DV specification.
799 * @param[in,out] resource
800 * Pointer to the modify-header resource.
802 * Pointer to action specification.
804 * Pointer to rte_flow_item objects list.
806 * Pointer to flow attributes structure.
807 * @param[in] dev_flow
808 * Pointer to the sub flow.
809 * @param[in] tunnel_decap
810 * Whether action is after tunnel decapsulation.
812 * Pointer to the error structure.
815 * 0 on success, a negative errno value otherwise and rte_errno is set.
818 flow_dv_convert_action_modify_dec_ttl
819 (struct mlx5_flow_dv_modify_hdr_resource *resource,
820 const struct rte_flow_item *items,
821 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
822 bool tunnel_decap, struct rte_flow_error *error)
824 struct rte_flow_item item;
825 struct rte_flow_item_ipv4 ipv4;
826 struct rte_flow_item_ipv4 ipv4_mask;
827 struct rte_flow_item_ipv6 ipv6;
828 struct rte_flow_item_ipv6 ipv6_mask;
829 struct field_modify_info *field;
832 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
834 memset(&ipv4, 0, sizeof(ipv4));
835 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
836 ipv4.hdr.time_to_live = 0xFF;
837 ipv4_mask.hdr.time_to_live = 0xFF;
838 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
840 item.mask = &ipv4_mask;
843 MLX5_ASSERT(attr->ipv6);
844 memset(&ipv6, 0, sizeof(ipv6));
845 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
846 ipv6.hdr.hop_limits = 0xFF;
847 ipv6_mask.hdr.hop_limits = 0xFF;
848 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
850 item.mask = &ipv6_mask;
853 return flow_dv_convert_modify_action(&item, field, NULL, resource,
854 MLX5_MODIFICATION_TYPE_ADD, error);
858 * Convert modify-header increment/decrement TCP Sequence number
859 * to DV specification.
861 * @param[in,out] resource
862 * Pointer to the modify-header resource.
864 * Pointer to action specification.
866 * Pointer to the error structure.
869 * 0 on success, a negative errno value otherwise and rte_errno is set.
872 flow_dv_convert_action_modify_tcp_seq
873 (struct mlx5_flow_dv_modify_hdr_resource *resource,
874 const struct rte_flow_action *action,
875 struct rte_flow_error *error)
877 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
878 uint64_t value = rte_be_to_cpu_32(*conf);
879 struct rte_flow_item item;
880 struct rte_flow_item_tcp tcp;
881 struct rte_flow_item_tcp tcp_mask;
883 memset(&tcp, 0, sizeof(tcp));
884 memset(&tcp_mask, 0, sizeof(tcp_mask));
885 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
887 * The HW has no decrement operation, only increment operation.
888 * To simulate decrement X from Y using increment operation
889 * we need to add UINT32_MAX X times to Y.
890 * Each adding of UINT32_MAX decrements Y by 1.
893 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
894 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
895 item.type = RTE_FLOW_ITEM_TYPE_TCP;
897 item.mask = &tcp_mask;
898 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
899 MLX5_MODIFICATION_TYPE_ADD, error);
903 * Convert modify-header increment/decrement TCP Acknowledgment number
904 * to DV specification.
906 * @param[in,out] resource
907 * Pointer to the modify-header resource.
909 * Pointer to action specification.
911 * Pointer to the error structure.
914 * 0 on success, a negative errno value otherwise and rte_errno is set.
917 flow_dv_convert_action_modify_tcp_ack
918 (struct mlx5_flow_dv_modify_hdr_resource *resource,
919 const struct rte_flow_action *action,
920 struct rte_flow_error *error)
922 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
923 uint64_t value = rte_be_to_cpu_32(*conf);
924 struct rte_flow_item item;
925 struct rte_flow_item_tcp tcp;
926 struct rte_flow_item_tcp tcp_mask;
928 memset(&tcp, 0, sizeof(tcp));
929 memset(&tcp_mask, 0, sizeof(tcp_mask));
930 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
932 * The HW has no decrement operation, only increment operation.
933 * To simulate decrement X from Y using increment operation
934 * we need to add UINT32_MAX X times to Y.
935 * Each adding of UINT32_MAX decrements Y by 1.
938 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
939 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
940 item.type = RTE_FLOW_ITEM_TYPE_TCP;
942 item.mask = &tcp_mask;
943 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
944 MLX5_MODIFICATION_TYPE_ADD, error);
947 static enum mlx5_modification_field reg_to_field[] = {
948 [REG_NONE] = MLX5_MODI_OUT_NONE,
949 [REG_A] = MLX5_MODI_META_DATA_REG_A,
950 [REG_B] = MLX5_MODI_META_DATA_REG_B,
951 [REG_C_0] = MLX5_MODI_META_REG_C_0,
952 [REG_C_1] = MLX5_MODI_META_REG_C_1,
953 [REG_C_2] = MLX5_MODI_META_REG_C_2,
954 [REG_C_3] = MLX5_MODI_META_REG_C_3,
955 [REG_C_4] = MLX5_MODI_META_REG_C_4,
956 [REG_C_5] = MLX5_MODI_META_REG_C_5,
957 [REG_C_6] = MLX5_MODI_META_REG_C_6,
958 [REG_C_7] = MLX5_MODI_META_REG_C_7,
962 * Convert register set to DV specification.
964 * @param[in,out] resource
965 * Pointer to the modify-header resource.
967 * Pointer to action specification.
969 * Pointer to the error structure.
972 * 0 on success, a negative errno value otherwise and rte_errno is set.
975 flow_dv_convert_action_set_reg
976 (struct mlx5_flow_dv_modify_hdr_resource *resource,
977 const struct rte_flow_action *action,
978 struct rte_flow_error *error)
980 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
981 struct mlx5_modification_cmd *actions = resource->actions;
982 uint32_t i = resource->actions_num;
984 if (i >= MLX5_MAX_MODIFY_NUM)
985 return rte_flow_error_set(error, EINVAL,
986 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
987 "too many items to modify");
988 MLX5_ASSERT(conf->id != REG_NONE);
989 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
990 actions[i] = (struct mlx5_modification_cmd) {
991 .action_type = MLX5_MODIFICATION_TYPE_SET,
992 .field = reg_to_field[conf->id],
994 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
995 actions[i].data1 = rte_cpu_to_be_32(conf->data);
997 resource->actions_num = i;
1002 * Convert SET_TAG action to DV specification.
1005 * Pointer to the rte_eth_dev structure.
1006 * @param[in,out] resource
1007 * Pointer to the modify-header resource.
1009 * Pointer to action specification.
1011 * Pointer to the error structure.
1014 * 0 on success, a negative errno value otherwise and rte_errno is set.
1017 flow_dv_convert_action_set_tag
1018 (struct rte_eth_dev *dev,
1019 struct mlx5_flow_dv_modify_hdr_resource *resource,
1020 const struct rte_flow_action_set_tag *conf,
1021 struct rte_flow_error *error)
1023 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025 struct rte_flow_item item = {
1029 struct field_modify_info reg_c_x[] = {
1032 enum mlx5_modification_field reg_type;
1035 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038 MLX5_ASSERT(ret != REG_NONE);
1039 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040 reg_type = reg_to_field[ret];
1041 MLX5_ASSERT(reg_type > 0);
1042 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044 MLX5_MODIFICATION_TYPE_SET, error);
1048 * Convert internal COPY_REG action to DV specification.
1051 * Pointer to the rte_eth_dev structure.
1052 * @param[in,out] res
1053 * Pointer to the modify-header resource.
1055 * Pointer to action specification.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064 struct mlx5_flow_dv_modify_hdr_resource *res,
1065 const struct rte_flow_action *action,
1066 struct rte_flow_error *error)
1068 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070 struct rte_flow_item item = {
1074 struct field_modify_info reg_src[] = {
1075 {4, 0, reg_to_field[conf->src]},
1078 struct field_modify_info reg_dst = {
1080 .id = reg_to_field[conf->dst],
1082 /* Adjust reg_c[0] usage according to reported mask. */
1083 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084 struct mlx5_priv *priv = dev->data->dev_private;
1085 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087 MLX5_ASSERT(reg_c0);
1088 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089 if (conf->dst == REG_C_0) {
1090 /* Copy to reg_c[0], within mask only. */
1091 reg_dst.offset = rte_bsf32(reg_c0);
1093 * Mask is ignoring the enianness, because
1094 * there is no conversion in datapath.
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097 /* Copy from destination lower bits to reg_c[0]. */
1098 mask = reg_c0 >> reg_dst.offset;
1100 /* Copy from destination upper bits to reg_c[0]. */
1101 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102 rte_fls_u32(reg_c0));
1105 mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107 /* Copy from reg_c[0] to destination lower bits. */
1110 /* Copy from reg_c[0] to destination upper bits. */
1111 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112 (rte_fls_u32(reg_c0) -
1117 return flow_dv_convert_modify_action(&item,
1118 reg_src, ®_dst, res,
1119 MLX5_MODIFICATION_TYPE_COPY,
1124 * Convert MARK action to DV specification. This routine is used
1125 * in extensive metadata only and requires metadata register to be
1126 * handled. In legacy mode hardware tag resource is engaged.
1129 * Pointer to the rte_eth_dev structure.
1131 * Pointer to MARK action specification.
1132 * @param[in,out] resource
1133 * Pointer to the modify-header resource.
1135 * Pointer to the error structure.
1138 * 0 on success, a negative errno value otherwise and rte_errno is set.
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142 const struct rte_flow_action_mark *conf,
1143 struct mlx5_flow_dv_modify_hdr_resource *resource,
1144 struct rte_flow_error *error)
1146 struct mlx5_priv *priv = dev->data->dev_private;
1147 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148 priv->sh->dv_mark_mask);
1149 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150 struct rte_flow_item item = {
1154 struct field_modify_info reg_c_x[] = {
1155 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1161 return rte_flow_error_set(error, EINVAL,
1162 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1163 NULL, "zero mark action mask");
1164 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167 MLX5_ASSERT(reg > 0);
1168 if (reg == REG_C_0) {
1169 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1170 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1173 mask = rte_cpu_to_be_32(mask) & msk_c0;
1174 mask = rte_cpu_to_be_32(mask << shl_c0);
1176 reg_c_x[0].id = reg_to_field[reg];
1177 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1178 MLX5_MODIFICATION_TYPE_SET, error);
1182 * Get metadata register index for specified steering domain.
1185 * Pointer to the rte_eth_dev structure.
1187 * Attributes of flow to determine steering domain.
1189 * Pointer to the error structure.
1192 * positive index on success, a negative errno value otherwise
1193 * and rte_errno is set.
1195 static enum modify_reg
1196 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1197 const struct rte_flow_attr *attr,
1198 struct rte_flow_error *error)
1201 mlx5_flow_get_reg_id(dev, attr->transfer ?
1205 MLX5_METADATA_RX, 0, error);
1207 return rte_flow_error_set(error,
1208 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1209 NULL, "unavailable "
1210 "metadata register");
1215 * Convert SET_META action to DV specification.
1218 * Pointer to the rte_eth_dev structure.
1219 * @param[in,out] resource
1220 * Pointer to the modify-header resource.
1222 * Attributes of flow that includes this item.
1224 * Pointer to action specification.
1226 * Pointer to the error structure.
1229 * 0 on success, a negative errno value otherwise and rte_errno is set.
1232 flow_dv_convert_action_set_meta
1233 (struct rte_eth_dev *dev,
1234 struct mlx5_flow_dv_modify_hdr_resource *resource,
1235 const struct rte_flow_attr *attr,
1236 const struct rte_flow_action_set_meta *conf,
1237 struct rte_flow_error *error)
1239 uint32_t data = conf->data;
1240 uint32_t mask = conf->mask;
1241 struct rte_flow_item item = {
1245 struct field_modify_info reg_c_x[] = {
1248 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1253 * In datapath code there is no endianness
1254 * coversions for perfromance reasons, all
1255 * pattern conversions are done in rte_flow.
1257 if (reg == REG_C_0) {
1258 struct mlx5_priv *priv = dev->data->dev_private;
1259 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262 MLX5_ASSERT(msk_c0);
1263 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1264 shl_c0 = rte_bsf32(msk_c0);
1266 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1270 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1273 /* The routine expects parameters in memory as big-endian ones. */
1274 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1275 MLX5_MODIFICATION_TYPE_SET, error);
1279 * Convert modify-header set IPv4 DSCP action to DV specification.
1281 * @param[in,out] resource
1282 * Pointer to the modify-header resource.
1284 * Pointer to action specification.
1286 * Pointer to the error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_convert_action_modify_ipv4_dscp
1293 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1294 const struct rte_flow_action *action,
1295 struct rte_flow_error *error)
1297 const struct rte_flow_action_set_dscp *conf =
1298 (const struct rte_flow_action_set_dscp *)(action->conf);
1299 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1300 struct rte_flow_item_ipv4 ipv4;
1301 struct rte_flow_item_ipv4 ipv4_mask;
1303 memset(&ipv4, 0, sizeof(ipv4));
1304 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1305 ipv4.hdr.type_of_service = conf->dscp;
1306 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308 item.mask = &ipv4_mask;
1309 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1310 MLX5_MODIFICATION_TYPE_SET, error);
1314 * Convert modify-header set IPv6 DSCP action to DV specification.
1316 * @param[in,out] resource
1317 * Pointer to the modify-header resource.
1319 * Pointer to action specification.
1321 * Pointer to the error structure.
1324 * 0 on success, a negative errno value otherwise and rte_errno is set.
1327 flow_dv_convert_action_modify_ipv6_dscp
1328 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1329 const struct rte_flow_action *action,
1330 struct rte_flow_error *error)
1332 const struct rte_flow_action_set_dscp *conf =
1333 (const struct rte_flow_action_set_dscp *)(action->conf);
1334 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1335 struct rte_flow_item_ipv6 ipv6;
1336 struct rte_flow_item_ipv6 ipv6_mask;
1338 memset(&ipv6, 0, sizeof(ipv6));
1339 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1342 * rdma-core only accept the DSCP bits byte aligned start from
1343 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1344 * bits in IPv6 case as rdma-core requires byte aligned value.
1346 ipv6.hdr.vtc_flow = conf->dscp;
1347 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349 item.mask = &ipv6_mask;
1350 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1351 MLX5_MODIFICATION_TYPE_SET, error);
1355 * Validate MARK item.
1358 * Pointer to the rte_eth_dev structure.
1360 * Item specification.
1362 * Attributes of flow that includes this item.
1364 * Pointer to error structure.
1367 * 0 on success, a negative errno value otherwise and rte_errno is set.
1370 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1371 const struct rte_flow_item *item,
1372 const struct rte_flow_attr *attr __rte_unused,
1373 struct rte_flow_error *error)
1375 struct mlx5_priv *priv = dev->data->dev_private;
1376 struct mlx5_dev_config *config = &priv->config;
1377 const struct rte_flow_item_mark *spec = item->spec;
1378 const struct rte_flow_item_mark *mask = item->mask;
1379 const struct rte_flow_item_mark nic_mask = {
1380 .id = priv->sh->dv_mark_mask,
1384 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata feature"
1389 if (!mlx5_flow_ext_mreg_supported(dev))
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't supported");
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1397 "extended metadata register"
1398 " isn't available");
1399 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406 "data cannot be empty");
1407 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1408 return rte_flow_error_set(error, EINVAL,
1409 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411 "mark id exceeds the limit");
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1417 "mask cannot be zero");
1419 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1420 (const uint8_t *)&nic_mask,
1421 sizeof(struct rte_flow_item_mark),
1429 * Validate META item.
1432 * Pointer to the rte_eth_dev structure.
1434 * Item specification.
1436 * Attributes of flow that includes this item.
1438 * Pointer to error structure.
1441 * 0 on success, a negative errno value otherwise and rte_errno is set.
1444 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1445 const struct rte_flow_item *item,
1446 const struct rte_flow_attr *attr,
1447 struct rte_flow_error *error)
1449 struct mlx5_priv *priv = dev->data->dev_private;
1450 struct mlx5_dev_config *config = &priv->config;
1451 const struct rte_flow_item_meta *spec = item->spec;
1452 const struct rte_flow_item_meta *mask = item->mask;
1453 struct rte_flow_item_meta nic_mask = {
1460 return rte_flow_error_set(error, EINVAL,
1461 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463 "data cannot be empty");
1464 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1465 if (!mlx5_flow_ext_mreg_supported(dev))
1466 return rte_flow_error_set(error, ENOTSUP,
1467 RTE_FLOW_ERROR_TYPE_ITEM, item,
1468 "extended metadata register"
1469 " isn't supported");
1470 reg = flow_dv_get_metadata_reg(dev, attr, error);
1474 return rte_flow_error_set(error, ENOTSUP,
1475 RTE_FLOW_ERROR_TYPE_ITEM, item,
1479 nic_mask.data = priv->sh->dv_meta_mask;
1480 } else if (attr->transfer) {
1481 return rte_flow_error_set(error, ENOTSUP,
1482 RTE_FLOW_ERROR_TYPE_ITEM, item,
1483 "extended metadata feature "
1484 "should be enabled when "
1485 "meta item is requested "
1486 "with e-switch mode ");
1489 mask = &rte_flow_item_meta_mask;
1491 return rte_flow_error_set(error, EINVAL,
1492 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493 "mask cannot be zero");
1495 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496 (const uint8_t *)&nic_mask,
1497 sizeof(struct rte_flow_item_meta),
1503 * Validate TAG item.
1506 * Pointer to the rte_eth_dev structure.
1508 * Item specification.
1510 * Attributes of flow that includes this item.
1512 * Pointer to error structure.
1515 * 0 on success, a negative errno value otherwise and rte_errno is set.
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519 const struct rte_flow_item *item,
1520 const struct rte_flow_attr *attr __rte_unused,
1521 struct rte_flow_error *error)
1523 const struct rte_flow_item_tag *spec = item->spec;
1524 const struct rte_flow_item_tag *mask = item->mask;
1525 const struct rte_flow_item_tag nic_mask = {
1526 .data = RTE_BE32(UINT32_MAX),
1531 if (!mlx5_flow_ext_mreg_supported(dev))
1532 return rte_flow_error_set(error, ENOTSUP,
1533 RTE_FLOW_ERROR_TYPE_ITEM, item,
1534 "extensive metadata register"
1535 " isn't supported");
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1540 "data cannot be empty");
1542 mask = &rte_flow_item_tag_mask;
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546 "mask cannot be zero");
1548 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549 (const uint8_t *)&nic_mask,
1550 sizeof(struct rte_flow_item_tag),
1554 if (mask->index != 0xff)
1555 return rte_flow_error_set(error, EINVAL,
1556 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557 "partial mask for tag index"
1558 " is not supported");
1559 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1562 MLX5_ASSERT(ret != REG_NONE);
1567 * Validate vport item.
1570 * Pointer to the rte_eth_dev structure.
1572 * Item specification.
1574 * Attributes of flow that includes this item.
1575 * @param[in] item_flags
1576 * Bit-fields that holds the items detected until now.
1578 * Pointer to error structure.
1581 * 0 on success, a negative errno value otherwise and rte_errno is set.
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585 const struct rte_flow_item *item,
1586 const struct rte_flow_attr *attr,
1587 uint64_t item_flags,
1588 struct rte_flow_error *error)
1590 const struct rte_flow_item_port_id *spec = item->spec;
1591 const struct rte_flow_item_port_id *mask = item->mask;
1592 const struct rte_flow_item_port_id switch_mask = {
1595 struct mlx5_priv *esw_priv;
1596 struct mlx5_priv *dev_priv;
1599 if (!attr->transfer)
1600 return rte_flow_error_set(error, EINVAL,
1601 RTE_FLOW_ERROR_TYPE_ITEM,
1603 "match on port id is valid only"
1604 " when transfer flag is enabled");
1605 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606 return rte_flow_error_set(error, ENOTSUP,
1607 RTE_FLOW_ERROR_TYPE_ITEM, item,
1608 "multiple source ports are not"
1611 mask = &switch_mask;
1612 if (mask->id != 0xffffffff)
1613 return rte_flow_error_set(error, ENOTSUP,
1614 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1616 "no support for partial mask on"
1618 ret = mlx5_flow_item_acceptable
1619 (item, (const uint8_t *)mask,
1620 (const uint8_t *)&rte_flow_item_port_id_mask,
1621 sizeof(struct rte_flow_item_port_id),
1627 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631 "failed to obtain E-Switch info for"
1633 dev_priv = mlx5_dev_to_eswitch_info(dev);
1635 return rte_flow_error_set(error, rte_errno,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1638 "failed to obtain E-Switch info");
1639 if (esw_priv->domain_id != dev_priv->domain_id)
1640 return rte_flow_error_set(error, EINVAL,
1641 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642 "cannot match on a port from a"
1643 " different E-Switch");
1648 * Validate VLAN item.
1651 * Item specification.
1652 * @param[in] item_flags
1653 * Bit-fields that holds the items detected until now.
1655 * Ethernet device flow is being created on.
1657 * Pointer to error structure.
1660 * 0 on success, a negative errno value otherwise and rte_errno is set.
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664 uint64_t item_flags,
1665 struct rte_eth_dev *dev,
1666 struct rte_flow_error *error)
1668 const struct rte_flow_item_vlan *mask = item->mask;
1669 const struct rte_flow_item_vlan nic_mask = {
1670 .tci = RTE_BE16(UINT16_MAX),
1671 .inner_type = RTE_BE16(UINT16_MAX),
1673 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1675 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676 MLX5_FLOW_LAYER_INNER_L4) :
1677 (MLX5_FLOW_LAYER_OUTER_L3 |
1678 MLX5_FLOW_LAYER_OUTER_L4);
1679 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680 MLX5_FLOW_LAYER_OUTER_VLAN;
1682 if (item_flags & vlanm)
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM, item,
1685 "multiple VLAN layers not supported");
1686 else if ((item_flags & l34m) != 0)
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM, item,
1689 "VLAN cannot follow L3/L4 layer");
1691 mask = &rte_flow_item_vlan_mask;
1692 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693 (const uint8_t *)&nic_mask,
1694 sizeof(struct rte_flow_item_vlan),
1698 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699 struct mlx5_priv *priv = dev->data->dev_private;
1701 if (priv->vmwa_context) {
1703 * Non-NULL context means we have a virtual machine
1704 * and SR-IOV enabled, we have to create VLAN interface
1705 * to make hypervisor to setup E-Switch vport
1706 * context correctly. We avoid creating the multiple
1707 * VLAN interfaces, so we cannot support VLAN tag mask.
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ITEM,
1712 "VLAN tag mask is not"
1713 " supported in virtual"
1721 * GTP flags are contained in 1 byte of the format:
1722 * -------------------------------------------
1723 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1724 * |-----------------------------------------|
1725 * | value | Version | PT | Res | E | S | PN |
1726 * -------------------------------------------
1728 * Matching is supported only for GTP flags E, S, PN.
1730 #define MLX5_GTP_FLAGS_MASK 0x07
1733 * Validate GTP item.
1736 * Pointer to the rte_eth_dev structure.
1738 * Item specification.
1739 * @param[in] item_flags
1740 * Bit-fields that holds the items detected until now.
1742 * Pointer to error structure.
1745 * 0 on success, a negative errno value otherwise and rte_errno is set.
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749 const struct rte_flow_item *item,
1750 uint64_t item_flags,
1751 struct rte_flow_error *error)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 const struct rte_flow_item_gtp *spec = item->spec;
1755 const struct rte_flow_item_gtp *mask = item->mask;
1756 const struct rte_flow_item_gtp nic_mask = {
1757 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1759 .teid = RTE_BE32(0xffffffff),
1762 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763 return rte_flow_error_set(error, ENOTSUP,
1764 RTE_FLOW_ERROR_TYPE_ITEM, item,
1765 "GTP support is not enabled");
1766 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767 return rte_flow_error_set(error, ENOTSUP,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "multiple tunnel layers not"
1771 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772 return rte_flow_error_set(error, EINVAL,
1773 RTE_FLOW_ERROR_TYPE_ITEM, item,
1774 "no outer UDP layer found");
1776 mask = &rte_flow_item_gtp_mask;
1777 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778 return rte_flow_error_set(error, ENOTSUP,
1779 RTE_FLOW_ERROR_TYPE_ITEM, item,
1780 "Match is supported for GTP"
1782 return mlx5_flow_item_acceptable
1783 (item, (const uint8_t *)mask,
1784 (const uint8_t *)&nic_mask,
1785 sizeof(struct rte_flow_item_gtp),
1790 * Validate the pop VLAN action.
1793 * Pointer to the rte_eth_dev structure.
1794 * @param[in] action_flags
1795 * Holds the actions detected until now.
1797 * Pointer to the pop vlan action.
1798 * @param[in] item_flags
1799 * The items found in this flow rule.
1801 * Pointer to flow attributes.
1803 * Pointer to error structure.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810 uint64_t action_flags,
1811 const struct rte_flow_action *action,
1812 uint64_t item_flags,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct mlx5_priv *priv = dev->data->dev_private;
1820 if (!priv->sh->pop_vlan_action)
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1824 "pop vlan action is not supported");
1826 return rte_flow_error_set(error, ENOTSUP,
1827 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1829 "pop vlan action not supported for "
1831 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ACTION, action,
1834 "no support for multiple VLAN "
1836 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1837 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1838 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1842 "cannot pop vlan after decap without "
1843 "match on inner vlan in the flow");
1844 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1845 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1846 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1850 "cannot pop vlan without a "
1851 "match on (outer) vlan in the flow");
1852 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION, action,
1855 "wrong action order, port_id should "
1856 "be after pop VLAN action");
1857 if (!attr->transfer && priv->representor)
1858 return rte_flow_error_set(error, ENOTSUP,
1859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1860 "pop vlan action for VF representor "
1861 "not supported on NIC table");
1866 * Get VLAN default info from vlan match info.
1869 * the list of item specifications.
1871 * pointer VLAN info to fill to.
1874 * 0 on success, a negative errno value otherwise and rte_errno is set.
1877 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1878 struct rte_vlan_hdr *vlan)
1880 const struct rte_flow_item_vlan nic_mask = {
1881 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1882 MLX5DV_FLOW_VLAN_VID_MASK),
1883 .inner_type = RTE_BE16(0xffff),
1888 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1889 int type = items->type;
1891 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1892 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1895 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1896 const struct rte_flow_item_vlan *vlan_m = items->mask;
1897 const struct rte_flow_item_vlan *vlan_v = items->spec;
1899 /* If VLAN item in pattern doesn't contain data, return here. */
1904 /* Only full match values are accepted */
1905 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1906 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1907 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1909 rte_be_to_cpu_16(vlan_v->tci &
1910 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1912 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1913 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1914 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1916 rte_be_to_cpu_16(vlan_v->tci &
1917 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1919 if (vlan_m->inner_type == nic_mask.inner_type)
1920 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1921 vlan_m->inner_type);
1926 * Validate the push VLAN action.
1929 * Pointer to the rte_eth_dev structure.
1930 * @param[in] action_flags
1931 * Holds the actions detected until now.
1932 * @param[in] item_flags
1933 * The items found in this flow rule.
1935 * Pointer to the action structure.
1937 * Pointer to flow attributes
1939 * Pointer to error structure.
1942 * 0 on success, a negative errno value otherwise and rte_errno is set.
1945 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1946 uint64_t action_flags,
1947 const struct rte_flow_item_vlan *vlan_m,
1948 const struct rte_flow_action *action,
1949 const struct rte_flow_attr *attr,
1950 struct rte_flow_error *error)
1952 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1953 const struct mlx5_priv *priv = dev->data->dev_private;
1955 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1956 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION, action,
1959 "invalid vlan ethertype");
1960 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION, action,
1963 "wrong action order, port_id should "
1964 "be after push VLAN");
1965 if (!attr->transfer && priv->representor)
1966 return rte_flow_error_set(error, ENOTSUP,
1967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968 "push vlan action for VF representor "
1969 "not supported on NIC table");
1971 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975 !(mlx5_flow_find_action
1976 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977 return rte_flow_error_set(error, EINVAL,
1978 RTE_FLOW_ERROR_TYPE_ACTION, action,
1979 "not full match mask on VLAN PCP and "
1980 "there is no of_set_vlan_pcp action, "
1981 "push VLAN action cannot figure out "
1984 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988 !(mlx5_flow_find_action
1989 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ACTION, action,
1992 "not full match mask on VLAN VID and "
1993 "there is no of_set_vlan_vid action, "
1994 "push VLAN action cannot figure out "
2001 * Validate the set VLAN PCP.
2003 * @param[in] action_flags
2004 * Holds the actions detected until now.
2005 * @param[in] actions
2006 * Pointer to the list of actions remaining in the flow rule.
2008 * Pointer to error structure.
2011 * 0 on success, a negative errno value otherwise and rte_errno is set.
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015 const struct rte_flow_action actions[],
2016 struct rte_flow_error *error)
2018 const struct rte_flow_action *action = actions;
2019 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2021 if (conf->vlan_pcp > 7)
2022 return rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ACTION, action,
2024 "VLAN PCP value is too big");
2025 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, action,
2028 "set VLAN PCP action must follow "
2029 "the push VLAN action");
2030 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031 return rte_flow_error_set(error, ENOTSUP,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "Multiple VLAN PCP modification are "
2035 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "wrong action order, port_id should "
2039 "be after set VLAN PCP");
2044 * Validate the set VLAN VID.
2046 * @param[in] item_flags
2047 * Holds the items detected in this rule.
2048 * @param[in] action_flags
2049 * Holds the actions detected until now.
2050 * @param[in] actions
2051 * Pointer to the list of actions remaining in the flow rule.
2053 * Pointer to error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060 uint64_t action_flags,
2061 const struct rte_flow_action actions[],
2062 struct rte_flow_error *error)
2064 const struct rte_flow_action *action = actions;
2065 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2067 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "VLAN VID value is too big");
2071 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "set VLAN VID action must follow push"
2076 " VLAN action or match on VLAN item");
2077 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078 return rte_flow_error_set(error, ENOTSUP,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "Multiple VLAN VID modifications are "
2082 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION, action,
2085 "wrong action order, port_id should "
2086 "be after set VLAN VID");
2091 * Validate the FLAG action.
2094 * Pointer to the rte_eth_dev structure.
2095 * @param[in] action_flags
2096 * Holds the actions detected until now.
2098 * Pointer to flow attributes
2100 * Pointer to error structure.
2103 * 0 on success, a negative errno value otherwise and rte_errno is set.
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107 uint64_t action_flags,
2108 const struct rte_flow_attr *attr,
2109 struct rte_flow_error *error)
2111 struct mlx5_priv *priv = dev->data->dev_private;
2112 struct mlx5_dev_config *config = &priv->config;
2115 /* Fall back if no extended metadata register support. */
2116 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117 return mlx5_flow_validate_action_flag(action_flags, attr,
2119 /* Extensive metadata mode requires registers. */
2120 if (!mlx5_flow_ext_mreg_supported(dev))
2121 return rte_flow_error_set(error, ENOTSUP,
2122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123 "no metadata registers "
2124 "to support flag action");
2125 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126 return rte_flow_error_set(error, ENOTSUP,
2127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128 "extended metadata register"
2129 " isn't available");
2130 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2133 MLX5_ASSERT(ret > 0);
2134 if (action_flags & MLX5_FLOW_ACTION_MARK)
2135 return rte_flow_error_set(error, EINVAL,
2136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137 "can't mark and flag in same flow");
2138 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2142 " actions in same flow");
2147 * Validate MARK action.
2150 * Pointer to the rte_eth_dev structure.
2152 * Pointer to action.
2153 * @param[in] action_flags
2154 * Holds the actions detected until now.
2156 * Pointer to flow attributes
2158 * Pointer to error structure.
2161 * 0 on success, a negative errno value otherwise and rte_errno is set.
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165 const struct rte_flow_action *action,
2166 uint64_t action_flags,
2167 const struct rte_flow_attr *attr,
2168 struct rte_flow_error *error)
2170 struct mlx5_priv *priv = dev->data->dev_private;
2171 struct mlx5_dev_config *config = &priv->config;
2172 const struct rte_flow_action_mark *mark = action->conf;
2175 /* Fall back if no extended metadata register support. */
2176 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177 return mlx5_flow_validate_action_mark(action, action_flags,
2179 /* Extensive metadata mode requires registers. */
2180 if (!mlx5_flow_ext_mreg_supported(dev))
2181 return rte_flow_error_set(error, ENOTSUP,
2182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183 "no metadata registers "
2184 "to support mark action");
2185 if (!priv->sh->dv_mark_mask)
2186 return rte_flow_error_set(error, ENOTSUP,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "extended metadata register"
2189 " isn't available");
2190 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2193 MLX5_ASSERT(ret > 0);
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "configuration cannot be null");
2198 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2202 "mark id exceeds the limit");
2203 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204 return rte_flow_error_set(error, EINVAL,
2205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206 "can't flag and mark in same flow");
2207 if (action_flags & MLX5_FLOW_ACTION_MARK)
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210 "can't have 2 mark actions in same"
2216 * Validate SET_META action.
2219 * Pointer to the rte_eth_dev structure.
2221 * Pointer to the action structure.
2222 * @param[in] action_flags
2223 * Holds the actions detected until now.
2225 * Pointer to flow attributes
2227 * Pointer to error structure.
2230 * 0 on success, a negative errno value otherwise and rte_errno is set.
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234 const struct rte_flow_action *action,
2235 uint64_t action_flags __rte_unused,
2236 const struct rte_flow_attr *attr,
2237 struct rte_flow_error *error)
2239 const struct rte_flow_action_set_meta *conf;
2240 uint32_t nic_mask = UINT32_MAX;
2243 if (!mlx5_flow_ext_mreg_supported(dev))
2244 return rte_flow_error_set(error, ENOTSUP,
2245 RTE_FLOW_ERROR_TYPE_ACTION, action,
2246 "extended metadata register"
2247 " isn't supported");
2248 reg = flow_dv_get_metadata_reg(dev, attr, error);
2251 if (reg != REG_A && reg != REG_B) {
2252 struct mlx5_priv *priv = dev->data->dev_private;
2254 nic_mask = priv->sh->dv_meta_mask;
2256 if (!(action->conf))
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, action,
2259 "configuration cannot be null");
2260 conf = (const struct rte_flow_action_set_meta *)action->conf;
2262 return rte_flow_error_set(error, EINVAL,
2263 RTE_FLOW_ERROR_TYPE_ACTION, action,
2264 "zero mask doesn't have any effect");
2265 if (conf->mask & ~nic_mask)
2266 return rte_flow_error_set(error, EINVAL,
2267 RTE_FLOW_ERROR_TYPE_ACTION, action,
2268 "meta data must be within reg C0");
2273 * Validate SET_TAG action.
2276 * Pointer to the rte_eth_dev structure.
2278 * Pointer to the action structure.
2279 * @param[in] action_flags
2280 * Holds the actions detected until now.
2282 * Pointer to flow attributes
2284 * Pointer to error structure.
2287 * 0 on success, a negative errno value otherwise and rte_errno is set.
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291 const struct rte_flow_action *action,
2292 uint64_t action_flags,
2293 const struct rte_flow_attr *attr,
2294 struct rte_flow_error *error)
2296 const struct rte_flow_action_set_tag *conf;
2297 const uint64_t terminal_action_flags =
2298 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299 MLX5_FLOW_ACTION_RSS;
2302 if (!mlx5_flow_ext_mreg_supported(dev))
2303 return rte_flow_error_set(error, ENOTSUP,
2304 RTE_FLOW_ERROR_TYPE_ACTION, action,
2305 "extensive metadata register"
2306 " isn't supported");
2307 if (!(action->conf))
2308 return rte_flow_error_set(error, EINVAL,
2309 RTE_FLOW_ERROR_TYPE_ACTION, action,
2310 "configuration cannot be null");
2311 conf = (const struct rte_flow_action_set_tag *)action->conf;
2313 return rte_flow_error_set(error, EINVAL,
2314 RTE_FLOW_ERROR_TYPE_ACTION, action,
2315 "zero mask doesn't have any effect");
2316 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2319 if (!attr->transfer && attr->ingress &&
2320 (action_flags & terminal_action_flags))
2321 return rte_flow_error_set(error, EINVAL,
2322 RTE_FLOW_ERROR_TYPE_ACTION, action,
2323 "set_tag has no effect"
2324 " with terminal actions");
2329 * Validate count action.
2332 * Pointer to rte_eth_dev structure.
2334 * Pointer to error structure.
2337 * 0 on success, a negative errno value otherwise and rte_errno is set.
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341 struct rte_flow_error *error)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2345 if (!priv->config.devx)
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2351 return rte_flow_error_set
2353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2355 "count action not supported");
2359 * Validate the L2 encap action.
2362 * Pointer to the rte_eth_dev structure.
2363 * @param[in] action_flags
2364 * Holds the actions detected until now.
2366 * Pointer to the action structure.
2368 * Pointer to flow attributes.
2370 * Pointer to error structure.
2373 * 0 on success, a negative errno value otherwise and rte_errno is set.
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377 uint64_t action_flags,
2378 const struct rte_flow_action *action,
2379 const struct rte_flow_attr *attr,
2380 struct rte_flow_error *error)
2382 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (!(action->conf))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, action,
2387 "configuration cannot be null");
2388 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389 return rte_flow_error_set(error, EINVAL,
2390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391 "can only have a single encap action "
2393 if (!attr->transfer && priv->representor)
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396 "encap action for VF representor "
2397 "not supported on NIC table");
2402 * Validate a decap action.
2405 * Pointer to the rte_eth_dev structure.
2406 * @param[in] action_flags
2407 * Holds the actions detected until now.
2409 * Pointer to flow attributes
2411 * Pointer to error structure.
2414 * 0 on success, a negative errno value otherwise and rte_errno is set.
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418 uint64_t action_flags,
2419 const struct rte_flow_attr *attr,
2420 struct rte_flow_error *error)
2422 const struct mlx5_priv *priv = dev->data->dev_private;
2424 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425 !priv->config.decap_en)
2426 return rte_flow_error_set(error, ENOTSUP,
2427 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428 "decap is not enabled");
2429 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2433 MLX5_FLOW_ACTION_DECAP ? "can only "
2434 "have a single decap action" : "decap "
2435 "after encap is not supported");
2436 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437 return rte_flow_error_set(error, EINVAL,
2438 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439 "can't have decap action after"
2442 return rte_flow_error_set(error, ENOTSUP,
2443 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2445 "decap action not supported for "
2447 if (!attr->transfer && priv->representor)
2448 return rte_flow_error_set(error, ENOTSUP,
2449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450 "decap action for VF representor "
2451 "not supported on NIC table");
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2458 * Validate the raw encap and decap actions.
2461 * Pointer to the rte_eth_dev structure.
2463 * Pointer to the decap action.
2465 * Pointer to the encap action.
2467 * Pointer to flow attributes
2468 * @param[in/out] action_flags
2469 * Holds the actions detected until now.
2470 * @param[out] actions_n
2471 * pointer to the number of actions counter.
2473 * Pointer to error structure.
2476 * 0 on success, a negative errno value otherwise and rte_errno is set.
2479 flow_dv_validate_action_raw_encap_decap
2480 (struct rte_eth_dev *dev,
2481 const struct rte_flow_action_raw_decap *decap,
2482 const struct rte_flow_action_raw_encap *encap,
2483 const struct rte_flow_attr *attr, uint64_t *action_flags,
2484 int *actions_n, struct rte_flow_error *error)
2486 const struct mlx5_priv *priv = dev->data->dev_private;
2489 if (encap && (!encap->size || !encap->data))
2490 return rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492 "raw encap data cannot be empty");
2493 if (decap && encap) {
2494 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2498 else if (encap->size <=
2499 MLX5_ENCAPSULATION_DECISION_SIZE &&
2501 MLX5_ENCAPSULATION_DECISION_SIZE)
2504 else if (encap->size >
2505 MLX5_ENCAPSULATION_DECISION_SIZE &&
2507 MLX5_ENCAPSULATION_DECISION_SIZE)
2508 /* 2 L2 actions: encap and decap. */
2511 return rte_flow_error_set(error,
2513 RTE_FLOW_ERROR_TYPE_ACTION,
2514 NULL, "unsupported too small "
2515 "raw decap and too small raw "
2516 "encap combination");
2519 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2523 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2527 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2531 "small raw encap size");
2532 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533 return rte_flow_error_set(error, EINVAL,
2534 RTE_FLOW_ERROR_TYPE_ACTION,
2536 "more than one encap action");
2537 if (!attr->transfer && priv->representor)
2538 return rte_flow_error_set
2540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541 "encap action for VF representor "
2542 "not supported on NIC table");
2543 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2550 * Find existing encap/decap resource or create and register a new one.
2552 * @param[in, out] dev
2553 * Pointer to rte_eth_dev structure.
2554 * @param[in, out] resource
2555 * Pointer to encap/decap resource.
2556 * @parm[in, out] dev_flow
2557 * Pointer to the dev_flow.
2559 * pointer to error structure.
2562 * 0 on success otherwise -errno and errno is set.
2565 flow_dv_encap_decap_resource_register
2566 (struct rte_eth_dev *dev,
2567 struct mlx5_flow_dv_encap_decap_resource *resource,
2568 struct mlx5_flow *dev_flow,
2569 struct rte_flow_error *error)
2571 struct mlx5_priv *priv = dev->data->dev_private;
2572 struct mlx5_dev_ctx_shared *sh = priv->sh;
2573 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574 struct mlx5dv_dr_domain *domain;
2578 resource->flags = dev_flow->dv.group ? 0 : 1;
2579 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580 domain = sh->fdb_domain;
2581 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582 domain = sh->rx_domain;
2584 domain = sh->tx_domain;
2585 /* Lookup a matching resource from cache. */
2586 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587 cache_resource, next) {
2588 if (resource->reformat_type == cache_resource->reformat_type &&
2589 resource->ft_type == cache_resource->ft_type &&
2590 resource->flags == cache_resource->flags &&
2591 resource->size == cache_resource->size &&
2592 !memcmp((const void *)resource->buf,
2593 (const void *)cache_resource->buf,
2595 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596 (void *)cache_resource,
2597 rte_atomic32_read(&cache_resource->refcnt));
2598 rte_atomic32_inc(&cache_resource->refcnt);
2599 dev_flow->handle->dvh.rix_encap_decap = idx;
2600 dev_flow->dv.encap_decap = cache_resource;
2604 /* Register new encap/decap resource. */
2605 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606 &dev_flow->handle->dvh.rix_encap_decap);
2607 if (!cache_resource)
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610 "cannot allocate resource memory");
2611 *cache_resource = *resource;
2612 ret = mlx5_flow_os_create_flow_action_packet_reformat
2613 (sh->ctx, domain, cache_resource,
2614 &cache_resource->action);
2616 mlx5_free(cache_resource);
2617 return rte_flow_error_set(error, ENOMEM,
2618 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619 NULL, "cannot create action");
2621 rte_atomic32_init(&cache_resource->refcnt);
2622 rte_atomic32_inc(&cache_resource->refcnt);
2623 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2626 dev_flow->dv.encap_decap = cache_resource;
2627 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628 (void *)cache_resource,
2629 rte_atomic32_read(&cache_resource->refcnt));
2634 * Find existing table jump resource or create and register a new one.
2636 * @param[in, out] dev
2637 * Pointer to rte_eth_dev structure.
2638 * @param[in, out] tbl
2639 * Pointer to flow table resource.
2640 * @parm[in, out] dev_flow
2641 * Pointer to the dev_flow.
2643 * pointer to error structure.
2646 * 0 on success otherwise -errno and errno is set.
2649 flow_dv_jump_tbl_resource_register
2650 (struct rte_eth_dev *dev __rte_unused,
2651 struct mlx5_flow_tbl_resource *tbl,
2652 struct mlx5_flow *dev_flow,
2653 struct rte_flow_error *error)
2655 struct mlx5_flow_tbl_data_entry *tbl_data =
2656 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2660 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2662 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663 (tbl->obj, &tbl_data->jump.action);
2665 return rte_flow_error_set(error, ENOMEM,
2666 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667 NULL, "cannot create jump action");
2668 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669 (void *)&tbl_data->jump, cnt);
2671 /* old jump should not make the table ref++. */
2672 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673 MLX5_ASSERT(tbl_data->jump.action);
2674 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675 (void *)&tbl_data->jump, cnt);
2677 rte_atomic32_inc(&tbl_data->jump.refcnt);
2678 dev_flow->handle->rix_jump = tbl_data->idx;
2679 dev_flow->dv.jump = &tbl_data->jump;
2684 * Find existing default miss resource or create and register a new one.
2686 * @param[in, out] dev
2687 * Pointer to rte_eth_dev structure.
2689 * pointer to error structure.
2692 * 0 on success otherwise -errno and errno is set.
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696 struct rte_flow_error *error)
2698 struct mlx5_priv *priv = dev->data->dev_private;
2699 struct mlx5_dev_ctx_shared *sh = priv->sh;
2700 struct mlx5_flow_default_miss_resource *cache_resource =
2702 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2705 MLX5_ASSERT(cache_resource->action);
2706 cache_resource->action =
2707 mlx5_glue->dr_create_flow_action_default_miss();
2708 if (!cache_resource->action)
2709 return rte_flow_error_set(error, ENOMEM,
2710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711 "cannot create default miss action");
2712 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713 (void *)cache_resource->action, cnt);
2715 rte_atomic32_inc(&cache_resource->refcnt);
2720 * Find existing table port ID resource or create and register a new one.
2722 * @param[in, out] dev
2723 * Pointer to rte_eth_dev structure.
2724 * @param[in, out] resource
2725 * Pointer to port ID action resource.
2726 * @parm[in, out] dev_flow
2727 * Pointer to the dev_flow.
2729 * pointer to error structure.
2732 * 0 on success otherwise -errno and errno is set.
2735 flow_dv_port_id_action_resource_register
2736 (struct rte_eth_dev *dev,
2737 struct mlx5_flow_dv_port_id_action_resource *resource,
2738 struct mlx5_flow *dev_flow,
2739 struct rte_flow_error *error)
2741 struct mlx5_priv *priv = dev->data->dev_private;
2742 struct mlx5_dev_ctx_shared *sh = priv->sh;
2743 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2747 /* Lookup a matching resource from cache. */
2748 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749 idx, cache_resource, next) {
2750 if (resource->port_id == cache_resource->port_id) {
2751 DRV_LOG(DEBUG, "port id action resource resource %p: "
2753 (void *)cache_resource,
2754 rte_atomic32_read(&cache_resource->refcnt));
2755 rte_atomic32_inc(&cache_resource->refcnt);
2756 dev_flow->handle->rix_port_id_action = idx;
2757 dev_flow->dv.port_id_action = cache_resource;
2761 /* Register new port id action resource. */
2762 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763 &dev_flow->handle->rix_port_id_action);
2764 if (!cache_resource)
2765 return rte_flow_error_set(error, ENOMEM,
2766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767 "cannot allocate resource memory");
2768 *cache_resource = *resource;
2769 ret = mlx5_flow_os_create_flow_action_dest_port
2770 (priv->sh->fdb_domain, resource->port_id,
2771 &cache_resource->action);
2773 mlx5_free(cache_resource);
2774 return rte_flow_error_set(error, ENOMEM,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776 NULL, "cannot create action");
2778 rte_atomic32_init(&cache_resource->refcnt);
2779 rte_atomic32_inc(&cache_resource->refcnt);
2780 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781 dev_flow->handle->rix_port_id_action, cache_resource,
2783 dev_flow->dv.port_id_action = cache_resource;
2784 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785 (void *)cache_resource,
2786 rte_atomic32_read(&cache_resource->refcnt));
2791 * Find existing push vlan resource or create and register a new one.
2793 * @param [in, out] dev
2794 * Pointer to rte_eth_dev structure.
2795 * @param[in, out] resource
2796 * Pointer to port ID action resource.
2797 * @parm[in, out] dev_flow
2798 * Pointer to the dev_flow.
2800 * pointer to error structure.
2803 * 0 on success otherwise -errno and errno is set.
2806 flow_dv_push_vlan_action_resource_register
2807 (struct rte_eth_dev *dev,
2808 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809 struct mlx5_flow *dev_flow,
2810 struct rte_flow_error *error)
2812 struct mlx5_priv *priv = dev->data->dev_private;
2813 struct mlx5_dev_ctx_shared *sh = priv->sh;
2814 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815 struct mlx5dv_dr_domain *domain;
2819 /* Lookup a matching resource from cache. */
2820 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821 sh->push_vlan_action_list, idx, cache_resource, next) {
2822 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823 resource->ft_type == cache_resource->ft_type) {
2824 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2826 (void *)cache_resource,
2827 rte_atomic32_read(&cache_resource->refcnt));
2828 rte_atomic32_inc(&cache_resource->refcnt);
2829 dev_flow->handle->dvh.rix_push_vlan = idx;
2830 dev_flow->dv.push_vlan_res = cache_resource;
2834 /* Register new push_vlan action resource. */
2835 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836 &dev_flow->handle->dvh.rix_push_vlan);
2837 if (!cache_resource)
2838 return rte_flow_error_set(error, ENOMEM,
2839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840 "cannot allocate resource memory");
2841 *cache_resource = *resource;
2842 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843 domain = sh->fdb_domain;
2844 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845 domain = sh->rx_domain;
2847 domain = sh->tx_domain;
2848 ret = mlx5_flow_os_create_flow_action_push_vlan
2849 (domain, resource->vlan_tag,
2850 &cache_resource->action);
2852 mlx5_free(cache_resource);
2853 return rte_flow_error_set(error, ENOMEM,
2854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855 NULL, "cannot create action");
2857 rte_atomic32_init(&cache_resource->refcnt);
2858 rte_atomic32_inc(&cache_resource->refcnt);
2859 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860 &sh->push_vlan_action_list,
2861 dev_flow->handle->dvh.rix_push_vlan,
2862 cache_resource, next);
2863 dev_flow->dv.push_vlan_res = cache_resource;
2864 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865 (void *)cache_resource,
2866 rte_atomic32_read(&cache_resource->refcnt));
2870 * Get the size of specific rte_flow_item_type hdr size
2872 * @param[in] item_type
2873 * Tested rte_flow_item_type.
2876 * sizeof struct item_type, 0 if void or irrelevant.
2879 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2883 switch (item_type) {
2884 case RTE_FLOW_ITEM_TYPE_ETH:
2885 retval = sizeof(struct rte_ether_hdr);
2887 case RTE_FLOW_ITEM_TYPE_VLAN:
2888 retval = sizeof(struct rte_vlan_hdr);
2890 case RTE_FLOW_ITEM_TYPE_IPV4:
2891 retval = sizeof(struct rte_ipv4_hdr);
2893 case RTE_FLOW_ITEM_TYPE_IPV6:
2894 retval = sizeof(struct rte_ipv6_hdr);
2896 case RTE_FLOW_ITEM_TYPE_UDP:
2897 retval = sizeof(struct rte_udp_hdr);
2899 case RTE_FLOW_ITEM_TYPE_TCP:
2900 retval = sizeof(struct rte_tcp_hdr);
2902 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2904 retval = sizeof(struct rte_vxlan_hdr);
2906 case RTE_FLOW_ITEM_TYPE_GRE:
2907 case RTE_FLOW_ITEM_TYPE_NVGRE:
2908 retval = sizeof(struct rte_gre_hdr);
2910 case RTE_FLOW_ITEM_TYPE_MPLS:
2911 retval = sizeof(struct rte_mpls_hdr);
2913 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2921 #define MLX5_ENCAP_IPV4_VERSION 0x40
2922 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2923 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2924 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2925 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2926 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2927 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2930 * Convert the encap action data from list of rte_flow_item to raw buffer
2933 * Pointer to rte_flow_item objects list.
2935 * Pointer to the output buffer.
2937 * Pointer to the output buffer size.
2939 * Pointer to the error structure.
2942 * 0 on success, a negative errno value otherwise and rte_errno is set.
2945 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2946 size_t *size, struct rte_flow_error *error)
2948 struct rte_ether_hdr *eth = NULL;
2949 struct rte_vlan_hdr *vlan = NULL;
2950 struct rte_ipv4_hdr *ipv4 = NULL;
2951 struct rte_ipv6_hdr *ipv6 = NULL;
2952 struct rte_udp_hdr *udp = NULL;
2953 struct rte_vxlan_hdr *vxlan = NULL;
2954 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2955 struct rte_gre_hdr *gre = NULL;
2957 size_t temp_size = 0;
2960 return rte_flow_error_set(error, EINVAL,
2961 RTE_FLOW_ERROR_TYPE_ACTION,
2962 NULL, "invalid empty data");
2963 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2964 len = flow_dv_get_item_hdr_len(items->type);
2965 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 (void *)items->type,
2969 "items total size is too big"
2970 " for encap action");
2971 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2972 switch (items->type) {
2973 case RTE_FLOW_ITEM_TYPE_ETH:
2974 eth = (struct rte_ether_hdr *)&buf[temp_size];
2976 case RTE_FLOW_ITEM_TYPE_VLAN:
2977 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2979 return rte_flow_error_set(error, EINVAL,
2980 RTE_FLOW_ERROR_TYPE_ACTION,
2981 (void *)items->type,
2982 "eth header not found");
2983 if (!eth->ether_type)
2984 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2986 case RTE_FLOW_ITEM_TYPE_IPV4:
2987 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2989 return rte_flow_error_set(error, EINVAL,
2990 RTE_FLOW_ERROR_TYPE_ACTION,
2991 (void *)items->type,
2992 "neither eth nor vlan"
2994 if (vlan && !vlan->eth_proto)
2995 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2996 else if (eth && !eth->ether_type)
2997 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2998 if (!ipv4->version_ihl)
2999 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3000 MLX5_ENCAP_IPV4_IHL_MIN;
3001 if (!ipv4->time_to_live)
3002 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3004 case RTE_FLOW_ITEM_TYPE_IPV6:
3005 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3007 return rte_flow_error_set(error, EINVAL,
3008 RTE_FLOW_ERROR_TYPE_ACTION,
3009 (void *)items->type,
3010 "neither eth nor vlan"
3012 if (vlan && !vlan->eth_proto)
3013 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3014 else if (eth && !eth->ether_type)
3015 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3016 if (!ipv6->vtc_flow)
3018 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3019 if (!ipv6->hop_limits)
3020 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3022 case RTE_FLOW_ITEM_TYPE_UDP:
3023 udp = (struct rte_udp_hdr *)&buf[temp_size];
3025 return rte_flow_error_set(error, EINVAL,
3026 RTE_FLOW_ERROR_TYPE_ACTION,
3027 (void *)items->type,
3028 "ip header not found");
3029 if (ipv4 && !ipv4->next_proto_id)
3030 ipv4->next_proto_id = IPPROTO_UDP;
3031 else if (ipv6 && !ipv6->proto)
3032 ipv6->proto = IPPROTO_UDP;
3034 case RTE_FLOW_ITEM_TYPE_VXLAN:
3035 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION,
3039 (void *)items->type,
3040 "udp header not found");
3042 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3043 if (!vxlan->vx_flags)
3045 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3047 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3048 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 (void *)items->type,
3053 "udp header not found");
3054 if (!vxlan_gpe->proto)
3055 return rte_flow_error_set(error, EINVAL,
3056 RTE_FLOW_ERROR_TYPE_ACTION,
3057 (void *)items->type,
3058 "next protocol not found");
3061 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3062 if (!vxlan_gpe->vx_flags)
3063 vxlan_gpe->vx_flags =
3064 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3066 case RTE_FLOW_ITEM_TYPE_GRE:
3067 case RTE_FLOW_ITEM_TYPE_NVGRE:
3068 gre = (struct rte_gre_hdr *)&buf[temp_size];
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION,
3072 (void *)items->type,
3073 "next protocol not found");
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION,
3077 (void *)items->type,
3078 "ip header not found");
3079 if (ipv4 && !ipv4->next_proto_id)
3080 ipv4->next_proto_id = IPPROTO_GRE;
3081 else if (ipv6 && !ipv6->proto)
3082 ipv6->proto = IPPROTO_GRE;
3084 case RTE_FLOW_ITEM_TYPE_VOID:
3087 return rte_flow_error_set(error, EINVAL,
3088 RTE_FLOW_ERROR_TYPE_ACTION,
3089 (void *)items->type,
3090 "unsupported item type");
3100 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3102 struct rte_ether_hdr *eth = NULL;
3103 struct rte_vlan_hdr *vlan = NULL;
3104 struct rte_ipv6_hdr *ipv6 = NULL;
3105 struct rte_udp_hdr *udp = NULL;
3109 eth = (struct rte_ether_hdr *)data;
3110 next_hdr = (char *)(eth + 1);
3111 proto = RTE_BE16(eth->ether_type);
3114 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3115 vlan = (struct rte_vlan_hdr *)next_hdr;
3116 proto = RTE_BE16(vlan->eth_proto);
3117 next_hdr += sizeof(struct rte_vlan_hdr);
3120 /* HW calculates IPv4 csum. no need to proceed */
3121 if (proto == RTE_ETHER_TYPE_IPV4)
3124 /* non IPv4/IPv6 header. not supported */
3125 if (proto != RTE_ETHER_TYPE_IPV6) {
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_ACTION,
3128 NULL, "Cannot offload non IPv4/IPv6");
3131 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3133 /* ignore non UDP */
3134 if (ipv6->proto != IPPROTO_UDP)
3137 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3138 udp->dgram_cksum = 0;
3144 * Convert L2 encap action to DV specification.
3147 * Pointer to rte_eth_dev structure.
3149 * Pointer to action structure.
3150 * @param[in, out] dev_flow
3151 * Pointer to the mlx5_flow.
3152 * @param[in] transfer
3153 * Mark if the flow is E-Switch flow.
3155 * Pointer to the error structure.
3158 * 0 on success, a negative errno value otherwise and rte_errno is set.
3161 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3162 const struct rte_flow_action *action,
3163 struct mlx5_flow *dev_flow,
3165 struct rte_flow_error *error)
3167 const struct rte_flow_item *encap_data;
3168 const struct rte_flow_action_raw_encap *raw_encap_data;
3169 struct mlx5_flow_dv_encap_decap_resource res = {
3171 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3172 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3173 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3176 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3178 (const struct rte_flow_action_raw_encap *)action->conf;
3179 res.size = raw_encap_data->size;
3180 memcpy(res.buf, raw_encap_data->data, res.size);
3182 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3184 ((const struct rte_flow_action_vxlan_encap *)
3185 action->conf)->definition;
3188 ((const struct rte_flow_action_nvgre_encap *)
3189 action->conf)->definition;
3190 if (flow_dv_convert_encap_data(encap_data, res.buf,
3194 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3196 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3197 return rte_flow_error_set(error, EINVAL,
3198 RTE_FLOW_ERROR_TYPE_ACTION,
3199 NULL, "can't create L2 encap action");
3204 * Convert L2 decap action to DV specification.
3207 * Pointer to rte_eth_dev structure.
3208 * @param[in, out] dev_flow
3209 * Pointer to the mlx5_flow.
3210 * @param[in] transfer
3211 * Mark if the flow is E-Switch flow.
3213 * Pointer to the error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3220 struct mlx5_flow *dev_flow,
3222 struct rte_flow_error *error)
3224 struct mlx5_flow_dv_encap_decap_resource res = {
3227 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3228 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3229 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3232 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3235 NULL, "can't create L2 decap action");
3240 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3243 * Pointer to rte_eth_dev structure.
3245 * Pointer to action structure.
3246 * @param[in, out] dev_flow
3247 * Pointer to the mlx5_flow.
3249 * Pointer to the flow attributes.
3251 * Pointer to the error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3258 const struct rte_flow_action *action,
3259 struct mlx5_flow *dev_flow,
3260 const struct rte_flow_attr *attr,
3261 struct rte_flow_error *error)
3263 const struct rte_flow_action_raw_encap *encap_data;
3264 struct mlx5_flow_dv_encap_decap_resource res;
3266 memset(&res, 0, sizeof(res));
3267 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3268 res.size = encap_data->size;
3269 memcpy(res.buf, encap_data->data, res.size);
3270 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3271 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3272 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3274 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3276 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3277 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3278 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION,
3281 NULL, "can't create encap action");
3286 * Create action push VLAN.
3289 * Pointer to rte_eth_dev structure.
3291 * Pointer to the flow attributes.
3293 * Pointer to the vlan to push to the Ethernet header.
3294 * @param[in, out] dev_flow
3295 * Pointer to the mlx5_flow.
3297 * Pointer to the error structure.
3300 * 0 on success, a negative errno value otherwise and rte_errno is set.
3303 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3304 const struct rte_flow_attr *attr,
3305 const struct rte_vlan_hdr *vlan,
3306 struct mlx5_flow *dev_flow,
3307 struct rte_flow_error *error)
3309 struct mlx5_flow_dv_push_vlan_action_resource res;
3311 memset(&res, 0, sizeof(res));
3313 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3316 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3318 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3319 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3320 return flow_dv_push_vlan_action_resource_register
3321 (dev, &res, dev_flow, error);
3325 * Validate the modify-header actions.
3327 * @param[in] action_flags
3328 * Holds the actions detected until now.
3330 * Pointer to the modify action.
3332 * Pointer to error structure.
3335 * 0 on success, a negative errno value otherwise and rte_errno is set.
3338 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3339 const struct rte_flow_action *action,
3340 struct rte_flow_error *error)
3342 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3343 return rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3345 NULL, "action configuration not set");
3346 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can't have encap action before"
3355 * Validate the modify-header MAC address actions.
3357 * @param[in] action_flags
3358 * Holds the actions detected until now.
3360 * Pointer to the modify action.
3361 * @param[in] item_flags
3362 * Holds the items detected.
3364 * Pointer to error structure.
3367 * 0 on success, a negative errno value otherwise and rte_errno is set.
3370 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3371 const struct rte_flow_action *action,
3372 const uint64_t item_flags,
3373 struct rte_flow_error *error)
3377 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3379 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "no L2 item in pattern");
3389 * Validate the modify-header IPv4 address actions.
3391 * @param[in] action_flags
3392 * Holds the actions detected until now.
3394 * Pointer to the modify action.
3395 * @param[in] item_flags
3396 * Holds the items detected.
3398 * Pointer to error structure.
3401 * 0 on success, a negative errno value otherwise and rte_errno is set.
3404 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3405 const struct rte_flow_action *action,
3406 const uint64_t item_flags,
3407 struct rte_flow_error *error)
3412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3416 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3417 if (!(item_flags & layer))
3418 return rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ACTION,
3421 "no ipv4 item in pattern");
3427 * Validate the modify-header IPv6 address actions.
3429 * @param[in] action_flags
3430 * Holds the actions detected until now.
3432 * Pointer to the modify action.
3433 * @param[in] item_flags
3434 * Holds the items detected.
3436 * Pointer to error structure.
3439 * 0 on success, a negative errno value otherwise and rte_errno is set.
3442 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const uint64_t item_flags,
3445 struct rte_flow_error *error)
3450 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3452 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3454 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3455 if (!(item_flags & layer))
3456 return rte_flow_error_set(error, EINVAL,
3457 RTE_FLOW_ERROR_TYPE_ACTION,
3459 "no ipv6 item in pattern");
3465 * Validate the modify-header TP actions.
3467 * @param[in] action_flags
3468 * Holds the actions detected until now.
3470 * Pointer to the modify action.
3471 * @param[in] item_flags
3472 * Holds the items detected.
3474 * Pointer to error structure.
3477 * 0 on success, a negative errno value otherwise and rte_errno is set.
3480 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3481 const struct rte_flow_action *action,
3482 const uint64_t item_flags,
3483 struct rte_flow_error *error)
3488 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3490 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3491 MLX5_FLOW_LAYER_INNER_L4 :
3492 MLX5_FLOW_LAYER_OUTER_L4;
3493 if (!(item_flags & layer))
3494 return rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ACTION,
3496 NULL, "no transport layer "
3503 * Validate the modify-header actions of increment/decrement
3504 * TCP Sequence-number.
3506 * @param[in] action_flags
3507 * Holds the actions detected until now.
3509 * Pointer to the modify action.
3510 * @param[in] item_flags
3511 * Holds the items detected.
3513 * Pointer to error structure.
3516 * 0 on success, a negative errno value otherwise and rte_errno is set.
3519 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3520 const struct rte_flow_action *action,
3521 const uint64_t item_flags,
3522 struct rte_flow_error *error)
3527 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3529 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3530 MLX5_FLOW_LAYER_INNER_L4_TCP :
3531 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3532 if (!(item_flags & layer))
3533 return rte_flow_error_set(error, EINVAL,
3534 RTE_FLOW_ERROR_TYPE_ACTION,
3535 NULL, "no TCP item in"
3537 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3538 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3539 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3540 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3541 return rte_flow_error_set(error, EINVAL,
3542 RTE_FLOW_ERROR_TYPE_ACTION,
3544 "cannot decrease and increase"
3545 " TCP sequence number"
3546 " at the same time");
3552 * Validate the modify-header actions of increment/decrement
3553 * TCP Acknowledgment number.
3555 * @param[in] action_flags
3556 * Holds the actions detected until now.
3558 * Pointer to the modify action.
3559 * @param[in] item_flags
3560 * Holds the items detected.
3562 * Pointer to error structure.
3565 * 0 on success, a negative errno value otherwise and rte_errno is set.
3568 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3569 const struct rte_flow_action *action,
3570 const uint64_t item_flags,
3571 struct rte_flow_error *error)
3576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579 MLX5_FLOW_LAYER_INNER_L4_TCP :
3580 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581 if (!(item_flags & layer))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_ACTION,
3584 NULL, "no TCP item in"
3586 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3587 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3588 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3589 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3590 return rte_flow_error_set(error, EINVAL,
3591 RTE_FLOW_ERROR_TYPE_ACTION,
3593 "cannot decrease and increase"
3594 " TCP acknowledgment number"
3595 " at the same time");
3601 * Validate the modify-header TTL actions.
3603 * @param[in] action_flags
3604 * Holds the actions detected until now.
3606 * Pointer to the modify action.
3607 * @param[in] item_flags
3608 * Holds the items detected.
3610 * Pointer to error structure.
3613 * 0 on success, a negative errno value otherwise and rte_errno is set.
3616 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3617 const struct rte_flow_action *action,
3618 const uint64_t item_flags,
3619 struct rte_flow_error *error)
3624 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3626 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3627 MLX5_FLOW_LAYER_INNER_L3 :
3628 MLX5_FLOW_LAYER_OUTER_L3;
3629 if (!(item_flags & layer))
3630 return rte_flow_error_set(error, EINVAL,
3631 RTE_FLOW_ERROR_TYPE_ACTION,
3633 "no IP protocol in pattern");
3639 * Validate jump action.
3642 * Pointer to the jump action.
3643 * @param[in] action_flags
3644 * Holds the actions detected until now.
3645 * @param[in] attributes
3646 * Pointer to flow attributes
3647 * @param[in] external
3648 * Action belongs to flow rule created by request external to PMD.
3650 * Pointer to error structure.
3653 * 0 on success, a negative errno value otherwise and rte_errno is set.
3656 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3657 uint64_t action_flags,
3658 const struct rte_flow_attr *attributes,
3659 bool external, struct rte_flow_error *error)
3661 uint32_t target_group, table;
3664 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3665 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3666 return rte_flow_error_set(error, EINVAL,
3667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668 "can't have 2 fate actions in"
3670 if (action_flags & MLX5_FLOW_ACTION_METER)
3671 return rte_flow_error_set(error, ENOTSUP,
3672 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673 "jump with meter not support");
3675 return rte_flow_error_set(error, EINVAL,
3676 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3677 NULL, "action configuration not set");
3679 ((const struct rte_flow_action_jump *)action->conf)->group;
3680 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3681 true, &table, error);
3684 if (attributes->group == target_group)
3685 return rte_flow_error_set(error, EINVAL,
3686 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687 "target group must be other than"
3688 " the current flow group");
3693 * Validate the port_id action.
3696 * Pointer to rte_eth_dev structure.
3697 * @param[in] action_flags
3698 * Bit-fields that holds the actions detected until now.
3700 * Port_id RTE action structure.
3702 * Attributes of flow that includes this action.
3704 * Pointer to error structure.
3707 * 0 on success, a negative errno value otherwise and rte_errno is set.
3710 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3711 uint64_t action_flags,
3712 const struct rte_flow_action *action,
3713 const struct rte_flow_attr *attr,
3714 struct rte_flow_error *error)
3716 const struct rte_flow_action_port_id *port_id;
3717 struct mlx5_priv *act_priv;
3718 struct mlx5_priv *dev_priv;
3721 if (!attr->transfer)
3722 return rte_flow_error_set(error, ENOTSUP,
3723 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3725 "port id action is valid in transfer"
3727 if (!action || !action->conf)
3728 return rte_flow_error_set(error, ENOTSUP,
3729 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3731 "port id action parameters must be"
3733 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3734 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3735 return rte_flow_error_set(error, EINVAL,
3736 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3737 "can have only one fate actions in"
3739 dev_priv = mlx5_dev_to_eswitch_info(dev);
3741 return rte_flow_error_set(error, rte_errno,
3742 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3744 "failed to obtain E-Switch info");
3745 port_id = action->conf;
3746 port = port_id->original ? dev->data->port_id : port_id->id;
3747 act_priv = mlx5_port_to_eswitch_info(port, false);
3749 return rte_flow_error_set
3751 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3752 "failed to obtain E-Switch port id for port");
3753 if (act_priv->domain_id != dev_priv->domain_id)
3754 return rte_flow_error_set
3756 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3757 "port does not belong to"
3758 " E-Switch being configured");
3763 * Get the maximum number of modify header actions.
3766 * Pointer to rte_eth_dev structure.
3768 * Flags bits to check if root level.
3771 * Max number of modify header actions device can support.
3773 static inline unsigned int
3774 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3778 * There's no way to directly query the max capacity from FW.
3779 * The maximal value on root table should be assumed to be supported.
3781 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3782 return MLX5_MAX_MODIFY_NUM;
3784 return MLX5_ROOT_TBL_MODIFY_NUM;
3788 * Validate the meter action.
3791 * Pointer to rte_eth_dev structure.
3792 * @param[in] action_flags
3793 * Bit-fields that holds the actions detected until now.
3795 * Pointer to the meter action.
3797 * Attributes of flow that includes this action.
3799 * Pointer to error structure.
3802 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3805 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3806 uint64_t action_flags,
3807 const struct rte_flow_action *action,
3808 const struct rte_flow_attr *attr,
3809 struct rte_flow_error *error)
3811 struct mlx5_priv *priv = dev->data->dev_private;
3812 const struct rte_flow_action_meter *am = action->conf;
3813 struct mlx5_flow_meter *fm;
3816 return rte_flow_error_set(error, EINVAL,
3817 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3818 "meter action conf is NULL");
3820 if (action_flags & MLX5_FLOW_ACTION_METER)
3821 return rte_flow_error_set(error, ENOTSUP,
3822 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823 "meter chaining not support");
3824 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3825 return rte_flow_error_set(error, ENOTSUP,
3826 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827 "meter with jump not support");
3829 return rte_flow_error_set(error, ENOTSUP,
3830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3832 "meter action not supported");
3833 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3835 return rte_flow_error_set(error, EINVAL,
3836 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3838 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3839 (!fm->ingress && !attr->ingress && attr->egress) ||
3840 (!fm->egress && !attr->egress && attr->ingress))))
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3843 "Flow attributes are either invalid "
3844 "or have a conflict with current "
3845 "meter attributes");
3850 * Validate the age action.
3852 * @param[in] action_flags
3853 * Holds the actions detected until now.
3855 * Pointer to the age action.
3857 * Pointer to the Ethernet device structure.
3859 * Pointer to error structure.
3862 * 0 on success, a negative errno value otherwise and rte_errno is set.
3865 flow_dv_validate_action_age(uint64_t action_flags,
3866 const struct rte_flow_action *action,
3867 struct rte_eth_dev *dev,
3868 struct rte_flow_error *error)
3870 struct mlx5_priv *priv = dev->data->dev_private;
3871 const struct rte_flow_action_age *age = action->conf;
3873 if (!priv->config.devx || priv->counter_fallback)
3874 return rte_flow_error_set(error, ENOTSUP,
3875 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3877 "age action not supported");
3878 if (!(action->conf))
3879 return rte_flow_error_set(error, EINVAL,
3880 RTE_FLOW_ERROR_TYPE_ACTION, action,
3881 "configuration cannot be null");
3882 if (age->timeout >= UINT16_MAX / 2 / 10)
3883 return rte_flow_error_set(error, ENOTSUP,
3884 RTE_FLOW_ERROR_TYPE_ACTION, action,
3885 "Max age time: 3275 seconds");
3886 if (action_flags & MLX5_FLOW_ACTION_AGE)
3887 return rte_flow_error_set(error, EINVAL,
3888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3889 "Duplicate age ctions set");
3894 * Validate the modify-header IPv4 DSCP actions.
3896 * @param[in] action_flags
3897 * Holds the actions detected until now.
3899 * Pointer to the modify action.
3900 * @param[in] item_flags
3901 * Holds the items detected.
3903 * Pointer to error structure.
3906 * 0 on success, a negative errno value otherwise and rte_errno is set.
3909 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3910 const struct rte_flow_action *action,
3911 const uint64_t item_flags,
3912 struct rte_flow_error *error)
3916 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3918 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3919 return rte_flow_error_set(error, EINVAL,
3920 RTE_FLOW_ERROR_TYPE_ACTION,
3922 "no ipv4 item in pattern");
3928 * Validate the modify-header IPv6 DSCP actions.
3930 * @param[in] action_flags
3931 * Holds the actions detected until now.
3933 * Pointer to the modify action.
3934 * @param[in] item_flags
3935 * Holds the items detected.
3937 * Pointer to error structure.
3940 * 0 on success, a negative errno value otherwise and rte_errno is set.
3943 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3944 const struct rte_flow_action *action,
3945 const uint64_t item_flags,
3946 struct rte_flow_error *error)
3950 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3952 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3953 return rte_flow_error_set(error, EINVAL,
3954 RTE_FLOW_ERROR_TYPE_ACTION,
3956 "no ipv6 item in pattern");
3962 * Find existing modify-header resource or create and register a new one.
3964 * @param dev[in, out]
3965 * Pointer to rte_eth_dev structure.
3966 * @param[in, out] resource
3967 * Pointer to modify-header resource.
3968 * @parm[in, out] dev_flow
3969 * Pointer to the dev_flow.
3971 * pointer to error structure.
3974 * 0 on success otherwise -errno and errno is set.
3977 flow_dv_modify_hdr_resource_register
3978 (struct rte_eth_dev *dev,
3979 struct mlx5_flow_dv_modify_hdr_resource *resource,
3980 struct mlx5_flow *dev_flow,
3981 struct rte_flow_error *error)
3983 struct mlx5_priv *priv = dev->data->dev_private;
3984 struct mlx5_dev_ctx_shared *sh = priv->sh;
3985 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3986 struct mlx5dv_dr_domain *ns;
3987 uint32_t actions_len;
3990 resource->flags = dev_flow->dv.group ? 0 :
3991 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3992 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3994 return rte_flow_error_set(error, EOVERFLOW,
3995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996 "too many modify header items");
3997 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3998 ns = sh->fdb_domain;
3999 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4003 /* Lookup a matching resource from cache. */
4004 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4005 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4006 if (resource->ft_type == cache_resource->ft_type &&
4007 resource->actions_num == cache_resource->actions_num &&
4008 resource->flags == cache_resource->flags &&
4009 !memcmp((const void *)resource->actions,
4010 (const void *)cache_resource->actions,
4012 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4013 (void *)cache_resource,
4014 rte_atomic32_read(&cache_resource->refcnt));
4015 rte_atomic32_inc(&cache_resource->refcnt);
4016 dev_flow->handle->dvh.modify_hdr = cache_resource;
4020 /* Register new modify-header resource. */
4021 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4022 sizeof(*cache_resource) + actions_len, 0,
4024 if (!cache_resource)
4025 return rte_flow_error_set(error, ENOMEM,
4026 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4027 "cannot allocate resource memory");
4028 *cache_resource = *resource;
4029 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4030 ret = mlx5_flow_os_create_flow_action_modify_header
4031 (sh->ctx, ns, cache_resource,
4032 actions_len, &cache_resource->action);
4034 mlx5_free(cache_resource);
4035 return rte_flow_error_set(error, ENOMEM,
4036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4037 NULL, "cannot create action");
4039 rte_atomic32_init(&cache_resource->refcnt);
4040 rte_atomic32_inc(&cache_resource->refcnt);
4041 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4042 dev_flow->handle->dvh.modify_hdr = cache_resource;
4043 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4044 (void *)cache_resource,
4045 rte_atomic32_read(&cache_resource->refcnt));
4050 * Get DV flow counter by index.
4053 * Pointer to the Ethernet device structure.
4055 * mlx5 flow counter index in the container.
4057 * mlx5 flow counter pool in the container,
4060 * Pointer to the counter, NULL otherwise.
4062 static struct mlx5_flow_counter *
4063 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4065 struct mlx5_flow_counter_pool **ppool)
4067 struct mlx5_priv *priv = dev->data->dev_private;
4068 struct mlx5_pools_container *cont;
4069 struct mlx5_flow_counter_pool *pool;
4070 uint32_t batch = 0, age = 0;
4073 age = MLX_CNT_IS_AGE(idx);
4074 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4075 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4076 idx -= MLX5_CNT_BATCH_OFFSET;
4079 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4080 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4081 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4085 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4089 * Check the devx counter belongs to the pool.
4092 * Pointer to the counter pool.
4094 * The counter devx ID.
4097 * True if counter belongs to the pool, false otherwise.
4100 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4102 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4103 MLX5_COUNTERS_PER_POOL;
4105 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4111 * Get a pool by devx counter ID.
4114 * Pointer to the counter container.
4116 * The counter devx ID.
4119 * The counter pool pointer if exists, NULL otherwise,
4121 static struct mlx5_flow_counter_pool *
4122 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4126 /* Check last used pool. */
4127 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4128 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4129 return cont->pools[cont->last_pool_idx];
4130 /* ID out of range means no suitable pool in the container. */
4131 if (id > cont->max_id || id < cont->min_id)
4134 * Find the pool from the end of the container, since mostly counter
4135 * ID is sequence increasing, and the last pool should be the needed
4138 i = rte_atomic16_read(&cont->n_valid);
4140 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4142 if (flow_dv_is_counter_in_pool(pool, id))
4149 * Allocate a new memory for the counter values wrapped by all the needed
4153 * Pointer to the Ethernet device structure.
4155 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4158 * The new memory management pointer on success, otherwise NULL and rte_errno
4161 static struct mlx5_counter_stats_mem_mng *
4162 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4164 struct mlx5_priv *priv = dev->data->dev_private;
4165 struct mlx5_dev_ctx_shared *sh = priv->sh;
4166 struct mlx5_devx_mkey_attr mkey_attr;
4167 struct mlx5_counter_stats_mem_mng *mem_mng;
4168 volatile struct flow_counter_stats *raw_data;
4169 int size = (sizeof(struct flow_counter_stats) *
4170 MLX5_COUNTERS_PER_POOL +
4171 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4172 sizeof(struct mlx5_counter_stats_mem_mng);
4173 size_t pgsize = rte_mem_page_size();
4174 if (pgsize == (size_t)-1) {
4175 DRV_LOG(ERR, "Failed to get mem page size");
4179 uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4187 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4188 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4189 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4190 IBV_ACCESS_LOCAL_WRITE);
4191 if (!mem_mng->umem) {
4196 mkey_attr.addr = (uintptr_t)mem;
4197 mkey_attr.size = size;
4198 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4199 mkey_attr.pd = sh->pdn;
4200 mkey_attr.log_entity_size = 0;
4201 mkey_attr.pg_access = 0;
4202 mkey_attr.klm_array = NULL;
4203 mkey_attr.klm_num = 0;
4204 if (priv->config.hca_attr.relaxed_ordering_write &&
4205 priv->config.hca_attr.relaxed_ordering_read &&
4206 !haswell_broadwell_cpu)
4207 mkey_attr.relaxed_ordering = 1;
4208 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4210 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4215 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4216 raw_data = (volatile struct flow_counter_stats *)mem;
4217 for (i = 0; i < raws_n; ++i) {
4218 mem_mng->raws[i].mem_mng = mem_mng;
4219 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4221 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4226 * Resize a counter container.
4229 * Pointer to the Ethernet device structure.
4231 * Whether the pool is for counter that was allocated by batch command.
4233 * Whether the pool is for Aging counter.
4236 * 0 on success, otherwise negative errno value and rte_errno is set.
4239 flow_dv_container_resize(struct rte_eth_dev *dev,
4240 uint32_t batch, uint32_t age)
4242 struct mlx5_priv *priv = dev->data->dev_private;
4243 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4245 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4246 void *old_pools = cont->pools;
4247 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4248 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4249 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4256 memcpy(pools, old_pools, cont->n *
4257 sizeof(struct mlx5_flow_counter_pool *));
4259 * Fallback mode query the counter directly, no background query
4260 * resources are needed.
4262 if (!priv->counter_fallback) {
4265 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4266 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4271 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4272 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4274 MLX5_CNT_CONTAINER_RESIZE +
4277 rte_spinlock_lock(&cont->resize_sl);
4279 cont->mem_mng = mem_mng;
4280 cont->pools = pools;
4281 rte_spinlock_unlock(&cont->resize_sl);
4283 mlx5_free(old_pools);
4288 * Query a devx flow counter.
4291 * Pointer to the Ethernet device structure.
4293 * Index to the flow counter.
4295 * The statistics value of packets.
4297 * The statistics value of bytes.
4300 * 0 on success, otherwise a negative errno value and rte_errno is set.
4303 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4306 struct mlx5_priv *priv = dev->data->dev_private;
4307 struct mlx5_flow_counter_pool *pool = NULL;
4308 struct mlx5_flow_counter *cnt;
4309 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4312 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4314 if (counter < MLX5_CNT_BATCH_OFFSET) {
4315 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4316 if (priv->counter_fallback)
4317 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4318 0, pkts, bytes, 0, NULL, NULL, 0);
4321 rte_spinlock_lock(&pool->sl);
4323 * The single counters allocation may allocate smaller ID than the
4324 * current allocated in parallel to the host reading.
4325 * In this case the new counter values must be reported as 0.
4327 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4331 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4332 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4333 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4335 rte_spinlock_unlock(&pool->sl);
4340 * Create and initialize a new counter pool.
4343 * Pointer to the Ethernet device structure.
4345 * The devX counter handle.
4347 * Whether the pool is for counter that was allocated by batch command.
4349 * Whether the pool is for counter that was allocated for aging.
4350 * @param[in/out] cont_cur
4351 * Pointer to the container pointer, it will be update in pool resize.
4354 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4358 uint32_t batch, uint32_t age)
4360 struct mlx5_priv *priv = dev->data->dev_private;
4361 struct mlx5_flow_counter_pool *pool;
4362 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4364 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4365 uint32_t size = sizeof(*pool);
4367 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4369 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4370 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4371 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4372 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4377 pool->min_dcs = dcs;
4378 if (!priv->counter_fallback)
4379 pool->raw = cont->mem_mng->raws + n_valid %
4380 MLX5_CNT_CONTAINER_RESIZE;
4381 pool->raw_hw = NULL;
4383 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4384 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4385 pool->query_gen = 0;
4386 rte_spinlock_init(&pool->sl);
4387 TAILQ_INIT(&pool->counters[0]);
4388 TAILQ_INIT(&pool->counters[1]);
4389 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4390 pool->index = n_valid;
4391 cont->pools[n_valid] = pool;
4393 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4395 if (base < cont->min_id)
4396 cont->min_id = base;
4397 if (base > cont->max_id)
4398 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4399 cont->last_pool_idx = pool->index;
4401 /* Pool initialization must be updated before host thread access. */
4403 rte_atomic16_add(&cont->n_valid, 1);
4408 * Restore skipped counters in the pool.
4410 * As counter pool query requires the first counter dcs
4411 * ID start with 4 alinged, if the pool counters with
4412 * min_dcs ID are not aligned with 4, the counters will
4414 * Once other min_dcs ID less than these skipped counter
4415 * dcs ID appears, the skipped counters will be safe to
4417 * Should be called when min_dcs is updated.
4420 * Current counter pool.
4421 * @param[in] last_min_dcs
4425 flow_dv_counter_restore(struct mlx5_flow_counter_pool *pool,
4426 struct mlx5_devx_obj *last_min_dcs)
4428 struct mlx5_flow_counter_ext *cnt_ext;
4429 uint32_t offset, new_offset;
4430 uint32_t skip_cnt = 0;
4433 if (!pool->skip_cnt)
4436 * If last min_dcs is not valid. The skipped counter may even after
4437 * last min_dcs, set the offset to the whole pool.
4439 if (last_min_dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4440 offset = MLX5_COUNTERS_PER_POOL;
4442 offset = last_min_dcs->id % MLX5_COUNTERS_PER_POOL;
4443 new_offset = pool->min_dcs->id % MLX5_COUNTERS_PER_POOL;
4445 * Check the counters from 1 to the last_min_dcs range. Counters
4446 * before new min_dcs indicates pool still has skipped counters.
4447 * Counters be skipped after new min_dcs will be ready to use.
4448 * Offset 0 counter must be empty or min_dcs, start from 1.
4450 for (i = 1; i < offset; i++) {
4451 cnt_ext = MLX5_GET_POOL_CNT_EXT(pool, i);
4452 if (cnt_ext->skipped) {
4453 if (i > new_offset) {
4454 cnt_ext->skipped = 0;
4456 (&pool->counters[pool->query_gen],
4457 MLX5_POOL_GET_CNT(pool, i), next);
4468 * Prepare a new counter and/or a new counter pool.
4471 * Pointer to the Ethernet device structure.
4472 * @param[out] cnt_free
4473 * Where to put the pointer of a new counter.
4475 * Whether the pool is for counter that was allocated by batch command.
4477 * Whether the pool is for counter that was allocated for aging.
4480 * The counter pool pointer and @p cnt_free is set on success,
4481 * NULL otherwise and rte_errno is set.
4483 static struct mlx5_flow_counter_pool *
4484 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4485 struct mlx5_flow_counter **cnt_free,
4486 uint32_t batch, uint32_t age)
4488 struct mlx5_priv *priv = dev->data->dev_private;
4489 struct mlx5_pools_container *cont;
4490 struct mlx5_flow_counter_pool *pool;
4491 struct mlx5_counters tmp_tq;
4492 struct mlx5_devx_obj *last_min_dcs;
4493 struct mlx5_devx_obj *dcs = NULL;
4494 struct mlx5_flow_counter *cnt;
4498 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4502 /* bulk_bitmap must be 0 for single counter allocation. */
4503 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4506 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4507 /* Check if counter belongs to exist pool ID range. */
4509 pool = flow_dv_find_pool_by_id
4511 (priv->sh, batch, (age ^ 0x1)), dcs->id);
4513 * Pool eixsts, counter will be added to the other
4514 * container, need to reallocate it later.
4519 pool = flow_dv_pool_create(dev, dcs, batch,
4522 mlx5_devx_cmd_destroy(dcs);
4527 if ((dcs->id < pool->min_dcs->id ||
4529 (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1)) &&
4530 !(dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))) {
4532 * Update the pool min_dcs only if current dcs is
4533 * valid and exist min_dcs is not valid or greater
4536 last_min_dcs = pool->min_dcs;
4537 rte_atomic64_set(&pool->a64_dcs,
4538 (int64_t)(uintptr_t)dcs);
4540 * Restore any skipped counters if the new min_dcs
4541 * ID is smaller or min_dcs is not valid.
4543 if (dcs->id < last_min_dcs->id ||
4545 (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4546 flow_dv_counter_restore(pool, last_min_dcs);
4548 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4549 cnt = MLX5_POOL_GET_CNT(pool, i);
4551 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4553 * If min_dcs is not valid, it means the new allocated dcs
4554 * also fail to become the valid min_dcs, just skip it.
4555 * Or if min_dcs is valid, and new dcs ID is smaller than
4556 * min_dcs, but not become the min_dcs, also skip it.
4558 if (pool->min_dcs->id &
4559 (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1) ||
4560 dcs->id < pool->min_dcs->id) {
4561 MLX5_GET_POOL_CNT_EXT(pool, i)->skipped = 1;
4566 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4573 /* bulk_bitmap is in 128 counters units. */
4574 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4575 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4577 rte_errno = ENODATA;
4580 pool = flow_dv_pool_create(dev, dcs, batch, age);
4582 mlx5_devx_cmd_destroy(dcs);
4585 TAILQ_INIT(&tmp_tq);
4586 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4587 cnt = MLX5_POOL_GET_CNT(pool, i);
4589 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4591 rte_spinlock_lock(&cont->csl);
4592 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4593 rte_spinlock_unlock(&cont->csl);
4594 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4595 (*cnt_free)->pool = pool;
4600 * Search for existed shared counter.
4603 * Pointer to the Ethernet device structure.
4605 * The shared counter ID to search.
4607 * mlx5 flow counter pool in the container,
4610 * NULL if not existed, otherwise pointer to the shared extend counter.
4612 static struct mlx5_flow_counter_ext *
4613 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4614 struct mlx5_flow_counter_pool **ppool)
4616 struct mlx5_priv *priv = dev->data->dev_private;
4617 union mlx5_l3t_data data;
4620 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4622 cnt_idx = data.dword;
4624 * Shared counters don't have age info. The counter extend is after
4625 * the counter datat structure.
4627 return (struct mlx5_flow_counter_ext *)
4628 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4632 * Allocate a flow counter.
4635 * Pointer to the Ethernet device structure.
4637 * Indicate if this counter is shared with other flows.
4639 * Counter identifier.
4641 * Counter flow group.
4643 * Whether the counter was allocated for aging.
4646 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4649 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4650 uint16_t group, uint32_t age)
4652 struct mlx5_priv *priv = dev->data->dev_private;
4653 struct mlx5_flow_counter_pool *pool = NULL;
4654 struct mlx5_flow_counter *cnt_free = NULL;
4655 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4657 * Currently group 0 flow counter cannot be assigned to a flow if it is
4658 * not the first one in the batch counter allocation, so it is better
4659 * to allocate counters one by one for these flows in a separate
4661 * A counter can be shared between different groups so need to take
4662 * shared counters from the single container.
4664 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4665 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4669 if (!priv->config.devx) {
4670 rte_errno = ENOTSUP;
4674 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4676 if (cnt_ext->ref_cnt + 1 == 0) {
4681 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4682 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4687 /* Get free counters from container. */
4688 rte_spinlock_lock(&cont->csl);
4689 cnt_free = TAILQ_FIRST(&cont->counters);
4691 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4692 rte_spinlock_unlock(&cont->csl);
4693 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4696 pool = cnt_free->pool;
4698 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4699 /* Create a DV counter action only in the first time usage. */
4700 if (!cnt_free->action) {
4702 struct mlx5_devx_obj *dcs;
4706 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4707 dcs = pool->min_dcs;
4712 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4719 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4720 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4721 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4722 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4723 /* Update the counter reset values. */
4724 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4728 cnt_ext->shared = shared;
4729 cnt_ext->ref_cnt = 1;
4732 union mlx5_l3t_data data;
4734 data.dword = cnt_idx;
4735 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4739 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4740 /* Start the asynchronous batch query by the host thread. */
4741 mlx5_set_query_alarm(priv->sh);
4745 cnt_free->pool = pool;
4746 rte_spinlock_lock(&cont->csl);
4747 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4748 rte_spinlock_unlock(&cont->csl);
4754 * Get age param from counter index.
4757 * Pointer to the Ethernet device structure.
4758 * @param[in] counter
4759 * Index to the counter handler.
4762 * The aging parameter specified for the counter index.
4764 static struct mlx5_age_param*
4765 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4768 struct mlx5_flow_counter *cnt;
4769 struct mlx5_flow_counter_pool *pool = NULL;
4771 flow_dv_counter_get_by_idx(dev, counter, &pool);
4772 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4773 cnt = MLX5_POOL_GET_CNT(pool, counter);
4774 return MLX5_CNT_TO_AGE(cnt);
4778 * Remove a flow counter from aged counter list.
4781 * Pointer to the Ethernet device structure.
4782 * @param[in] counter
4783 * Index to the counter handler.
4785 * Pointer to the counter handler.
4788 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4789 uint32_t counter, struct mlx5_flow_counter *cnt)
4791 struct mlx5_age_info *age_info;
4792 struct mlx5_age_param *age_param;
4793 struct mlx5_priv *priv = dev->data->dev_private;
4795 age_info = GET_PORT_AGE_INFO(priv);
4796 age_param = flow_dv_counter_idx_get_age(dev, counter);
4797 if (rte_atomic16_cmpset((volatile uint16_t *)
4799 AGE_CANDIDATE, AGE_FREE)
4802 * We need the lock even it is age timeout,
4803 * since counter may still in process.
4805 rte_spinlock_lock(&age_info->aged_sl);
4806 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4807 rte_spinlock_unlock(&age_info->aged_sl);
4809 rte_atomic16_set(&age_param->state, AGE_FREE);
4812 * Release a flow counter.
4815 * Pointer to the Ethernet device structure.
4816 * @param[in] counter
4817 * Index to the counter handler.
4820 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4822 struct mlx5_priv *priv = dev->data->dev_private;
4823 struct mlx5_flow_counter_pool *pool = NULL;
4824 struct mlx5_flow_counter *cnt;
4825 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4829 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4831 if (counter < MLX5_CNT_BATCH_OFFSET) {
4832 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4834 if (--cnt_ext->ref_cnt)
4836 if (cnt_ext->shared)
4837 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4841 if (IS_AGE_POOL(pool))
4842 flow_dv_counter_remove_from_age(dev, counter, cnt);
4845 * Put the counter back to list to be updated in none fallback mode.
4846 * Currently, we are using two list alternately, while one is in query,
4847 * add the freed counter to the other list based on the pool query_gen
4848 * value. After query finishes, add counter the list to the global
4849 * container counter list. The list changes while query starts. In
4850 * this case, lock will not be needed as query callback and release
4851 * function both operate with the different list.
4854 if (!priv->counter_fallback)
4855 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4857 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4858 (priv->sh, 0, 0))->counters),
4863 * Verify the @p attributes will be correctly understood by the NIC and store
4864 * them in the @p flow if everything is correct.
4867 * Pointer to dev struct.
4868 * @param[in] attributes
4869 * Pointer to flow attributes
4870 * @param[in] external
4871 * This flow rule is created by request external to PMD.
4873 * Pointer to error structure.
4876 * - 0 on success and non root table.
4877 * - 1 on success and root table.
4878 * - a negative errno value otherwise and rte_errno is set.
4881 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4882 const struct rte_flow_attr *attributes,
4883 bool external __rte_unused,
4884 struct rte_flow_error *error)
4886 struct mlx5_priv *priv = dev->data->dev_private;
4887 uint32_t priority_max = priv->config.flow_prio - 1;
4890 #ifndef HAVE_MLX5DV_DR
4891 if (attributes->group)
4892 return rte_flow_error_set(error, ENOTSUP,
4893 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4895 "groups are not supported");
4899 ret = mlx5_flow_group_to_table(attributes, external,
4900 attributes->group, !!priv->fdb_def_rule,
4905 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4907 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4908 attributes->priority >= priority_max)
4909 return rte_flow_error_set(error, ENOTSUP,
4910 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4912 "priority out of range");
4913 if (attributes->transfer) {
4914 if (!priv->config.dv_esw_en)
4915 return rte_flow_error_set
4917 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4918 "E-Switch dr is not supported");
4919 if (!(priv->representor || priv->master))
4920 return rte_flow_error_set
4921 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4922 NULL, "E-Switch configuration can only be"
4923 " done by a master or a representor device");
4924 if (attributes->egress)
4925 return rte_flow_error_set
4927 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4928 "egress is not supported");
4930 if (!(attributes->egress ^ attributes->ingress))
4931 return rte_flow_error_set(error, ENOTSUP,
4932 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4933 "must specify exactly one of "
4934 "ingress or egress");
4939 * Internal validation function. For validating both actions and items.
4942 * Pointer to the rte_eth_dev structure.
4944 * Pointer to the flow attributes.
4946 * Pointer to the list of items.
4947 * @param[in] actions
4948 * Pointer to the list of actions.
4949 * @param[in] external
4950 * This flow rule is created by request external to PMD.
4951 * @param[in] hairpin
4952 * Number of hairpin TX actions, 0 means classic flow.
4954 * Pointer to the error structure.
4957 * 0 on success, a negative errno value otherwise and rte_errno is set.
4960 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4961 const struct rte_flow_item items[],
4962 const struct rte_flow_action actions[],
4963 bool external, int hairpin, struct rte_flow_error *error)
4966 uint64_t action_flags = 0;
4967 uint64_t item_flags = 0;
4968 uint64_t last_item = 0;
4969 uint8_t next_protocol = 0xff;
4970 uint16_t ether_type = 0;
4972 uint8_t item_ipv6_proto = 0;
4973 const struct rte_flow_item *gre_item = NULL;
4974 const struct rte_flow_action_raw_decap *decap;
4975 const struct rte_flow_action_raw_encap *encap;
4976 const struct rte_flow_action_rss *rss;
4977 const struct rte_flow_item_tcp nic_tcp_mask = {
4980 .src_port = RTE_BE16(UINT16_MAX),
4981 .dst_port = RTE_BE16(UINT16_MAX),
4984 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4986 .src_addr = RTE_BE32(0xffffffff),
4987 .dst_addr = RTE_BE32(0xffffffff),
4988 .type_of_service = 0xff,
4989 .next_proto_id = 0xff,
4990 .time_to_live = 0xff,
4993 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4996 "\xff\xff\xff\xff\xff\xff\xff\xff"
4997 "\xff\xff\xff\xff\xff\xff\xff\xff",
4999 "\xff\xff\xff\xff\xff\xff\xff\xff"
5000 "\xff\xff\xff\xff\xff\xff\xff\xff",
5001 .vtc_flow = RTE_BE32(0xffffffff),
5006 const struct rte_flow_item_ecpri nic_ecpri_mask = {
5010 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5014 .dummy[0] = 0xffffffff,
5017 struct mlx5_priv *priv = dev->data->dev_private;
5018 struct mlx5_dev_config *dev_conf = &priv->config;
5019 uint16_t queue_index = 0xFFFF;
5020 const struct rte_flow_item_vlan *vlan_m = NULL;
5021 int16_t rw_act_num = 0;
5026 ret = flow_dv_validate_attributes(dev, attr, external, error);
5029 is_root = (uint64_t)ret;
5030 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5031 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5032 int type = items->type;
5034 if (!mlx5_flow_os_item_supported(type))
5035 return rte_flow_error_set(error, ENOTSUP,
5036 RTE_FLOW_ERROR_TYPE_ITEM,
5037 NULL, "item not supported");
5039 case RTE_FLOW_ITEM_TYPE_VOID:
5041 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5042 ret = flow_dv_validate_item_port_id
5043 (dev, items, attr, item_flags, error);
5046 last_item = MLX5_FLOW_ITEM_PORT_ID;
5048 case RTE_FLOW_ITEM_TYPE_ETH:
5049 ret = mlx5_flow_validate_item_eth(items, item_flags,
5053 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5054 MLX5_FLOW_LAYER_OUTER_L2;
5055 if (items->mask != NULL && items->spec != NULL) {
5057 ((const struct rte_flow_item_eth *)
5060 ((const struct rte_flow_item_eth *)
5062 ether_type = rte_be_to_cpu_16(ether_type);
5067 case RTE_FLOW_ITEM_TYPE_VLAN:
5068 ret = flow_dv_validate_item_vlan(items, item_flags,
5072 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5073 MLX5_FLOW_LAYER_OUTER_VLAN;
5074 if (items->mask != NULL && items->spec != NULL) {
5076 ((const struct rte_flow_item_vlan *)
5077 items->spec)->inner_type;
5079 ((const struct rte_flow_item_vlan *)
5080 items->mask)->inner_type;
5081 ether_type = rte_be_to_cpu_16(ether_type);
5085 /* Store outer VLAN mask for of_push_vlan action. */
5087 vlan_m = items->mask;
5089 case RTE_FLOW_ITEM_TYPE_IPV4:
5090 mlx5_flow_tunnel_ip_check(items, next_protocol,
5091 &item_flags, &tunnel);
5092 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5099 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5100 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5101 if (items->mask != NULL &&
5102 ((const struct rte_flow_item_ipv4 *)
5103 items->mask)->hdr.next_proto_id) {
5105 ((const struct rte_flow_item_ipv4 *)
5106 (items->spec))->hdr.next_proto_id;
5108 ((const struct rte_flow_item_ipv4 *)
5109 (items->mask))->hdr.next_proto_id;
5111 /* Reset for inner layer. */
5112 next_protocol = 0xff;
5115 case RTE_FLOW_ITEM_TYPE_IPV6:
5116 mlx5_flow_tunnel_ip_check(items, next_protocol,
5117 &item_flags, &tunnel);
5118 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5125 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5126 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5127 if (items->mask != NULL &&
5128 ((const struct rte_flow_item_ipv6 *)
5129 items->mask)->hdr.proto) {
5131 ((const struct rte_flow_item_ipv6 *)
5132 items->spec)->hdr.proto;
5134 ((const struct rte_flow_item_ipv6 *)
5135 items->spec)->hdr.proto;
5137 ((const struct rte_flow_item_ipv6 *)
5138 items->mask)->hdr.proto;
5140 /* Reset for inner layer. */
5141 next_protocol = 0xff;
5144 case RTE_FLOW_ITEM_TYPE_TCP:
5145 ret = mlx5_flow_validate_item_tcp
5152 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5153 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5155 case RTE_FLOW_ITEM_TYPE_UDP:
5156 ret = mlx5_flow_validate_item_udp(items, item_flags,
5161 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5162 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5164 case RTE_FLOW_ITEM_TYPE_GRE:
5165 ret = mlx5_flow_validate_item_gre(items, item_flags,
5166 next_protocol, error);
5170 last_item = MLX5_FLOW_LAYER_GRE;
5172 case RTE_FLOW_ITEM_TYPE_NVGRE:
5173 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5178 last_item = MLX5_FLOW_LAYER_NVGRE;
5180 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5181 ret = mlx5_flow_validate_item_gre_key
5182 (items, item_flags, gre_item, error);
5185 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5187 case RTE_FLOW_ITEM_TYPE_VXLAN:
5188 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5192 last_item = MLX5_FLOW_LAYER_VXLAN;
5194 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5195 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5200 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5202 case RTE_FLOW_ITEM_TYPE_GENEVE:
5203 ret = mlx5_flow_validate_item_geneve(items,
5208 last_item = MLX5_FLOW_LAYER_GENEVE;
5210 case RTE_FLOW_ITEM_TYPE_MPLS:
5211 ret = mlx5_flow_validate_item_mpls(dev, items,
5216 last_item = MLX5_FLOW_LAYER_MPLS;
5219 case RTE_FLOW_ITEM_TYPE_MARK:
5220 ret = flow_dv_validate_item_mark(dev, items, attr,
5224 last_item = MLX5_FLOW_ITEM_MARK;
5226 case RTE_FLOW_ITEM_TYPE_META:
5227 ret = flow_dv_validate_item_meta(dev, items, attr,
5231 last_item = MLX5_FLOW_ITEM_METADATA;
5233 case RTE_FLOW_ITEM_TYPE_ICMP:
5234 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5239 last_item = MLX5_FLOW_LAYER_ICMP;
5241 case RTE_FLOW_ITEM_TYPE_ICMP6:
5242 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5247 item_ipv6_proto = IPPROTO_ICMPV6;
5248 last_item = MLX5_FLOW_LAYER_ICMP6;
5250 case RTE_FLOW_ITEM_TYPE_TAG:
5251 ret = flow_dv_validate_item_tag(dev, items,
5255 last_item = MLX5_FLOW_ITEM_TAG;
5257 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5258 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5260 case RTE_FLOW_ITEM_TYPE_GTP:
5261 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5265 last_item = MLX5_FLOW_LAYER_GTP;
5267 case RTE_FLOW_ITEM_TYPE_ECPRI:
5268 /* Capacity will be checked in the translate stage. */
5269 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5276 last_item = MLX5_FLOW_LAYER_ECPRI;
5279 return rte_flow_error_set(error, ENOTSUP,
5280 RTE_FLOW_ERROR_TYPE_ITEM,
5281 NULL, "item not supported");
5283 item_flags |= last_item;
5285 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5286 int type = actions->type;
5288 if (!mlx5_flow_os_action_supported(type))
5289 return rte_flow_error_set(error, ENOTSUP,
5290 RTE_FLOW_ERROR_TYPE_ACTION,
5292 "action not supported");
5293 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5294 return rte_flow_error_set(error, ENOTSUP,
5295 RTE_FLOW_ERROR_TYPE_ACTION,
5296 actions, "too many actions");
5298 case RTE_FLOW_ACTION_TYPE_VOID:
5300 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5301 ret = flow_dv_validate_action_port_id(dev,
5308 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5311 case RTE_FLOW_ACTION_TYPE_FLAG:
5312 ret = flow_dv_validate_action_flag(dev, action_flags,
5316 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5317 /* Count all modify-header actions as one. */
5318 if (!(action_flags &
5319 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5321 action_flags |= MLX5_FLOW_ACTION_FLAG |
5322 MLX5_FLOW_ACTION_MARK_EXT;
5324 action_flags |= MLX5_FLOW_ACTION_FLAG;
5327 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5329 case RTE_FLOW_ACTION_TYPE_MARK:
5330 ret = flow_dv_validate_action_mark(dev, actions,
5335 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5336 /* Count all modify-header actions as one. */
5337 if (!(action_flags &
5338 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5340 action_flags |= MLX5_FLOW_ACTION_MARK |
5341 MLX5_FLOW_ACTION_MARK_EXT;
5343 action_flags |= MLX5_FLOW_ACTION_MARK;
5346 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5348 case RTE_FLOW_ACTION_TYPE_SET_META:
5349 ret = flow_dv_validate_action_set_meta(dev, actions,
5354 /* Count all modify-header actions as one action. */
5355 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5357 action_flags |= MLX5_FLOW_ACTION_SET_META;
5358 rw_act_num += MLX5_ACT_NUM_SET_META;
5360 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5361 ret = flow_dv_validate_action_set_tag(dev, actions,
5366 /* Count all modify-header actions as one action. */
5367 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5369 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5370 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5372 case RTE_FLOW_ACTION_TYPE_DROP:
5373 ret = mlx5_flow_validate_action_drop(action_flags,
5377 action_flags |= MLX5_FLOW_ACTION_DROP;
5380 case RTE_FLOW_ACTION_TYPE_QUEUE:
5381 ret = mlx5_flow_validate_action_queue(actions,
5386 queue_index = ((const struct rte_flow_action_queue *)
5387 (actions->conf))->index;
5388 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5391 case RTE_FLOW_ACTION_TYPE_RSS:
5392 rss = actions->conf;
5393 ret = mlx5_flow_validate_action_rss(actions,
5399 if (rss != NULL && rss->queue_num)
5400 queue_index = rss->queue[0];
5401 action_flags |= MLX5_FLOW_ACTION_RSS;
5404 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5406 mlx5_flow_validate_action_default_miss(action_flags,
5410 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5413 case RTE_FLOW_ACTION_TYPE_COUNT:
5414 ret = flow_dv_validate_action_count(dev, error);
5417 action_flags |= MLX5_FLOW_ACTION_COUNT;
5420 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5421 if (flow_dv_validate_action_pop_vlan(dev,
5427 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5430 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5431 ret = flow_dv_validate_action_push_vlan(dev,
5438 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5441 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5442 ret = flow_dv_validate_action_set_vlan_pcp
5443 (action_flags, actions, error);
5446 /* Count PCP with push_vlan command. */
5447 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5449 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5450 ret = flow_dv_validate_action_set_vlan_vid
5451 (item_flags, action_flags,
5455 /* Count VID with push_vlan command. */
5456 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5457 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5459 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5460 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5461 ret = flow_dv_validate_action_l2_encap(dev,
5467 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5470 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5471 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5472 ret = flow_dv_validate_action_decap(dev, action_flags,
5476 action_flags |= MLX5_FLOW_ACTION_DECAP;
5479 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5480 ret = flow_dv_validate_action_raw_encap_decap
5481 (dev, NULL, actions->conf, attr, &action_flags,
5486 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5487 decap = actions->conf;
5488 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5490 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5494 encap = actions->conf;
5496 ret = flow_dv_validate_action_raw_encap_decap
5498 decap ? decap : &empty_decap, encap,
5499 attr, &action_flags, &actions_n,
5504 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5505 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5506 ret = flow_dv_validate_action_modify_mac(action_flags,
5512 /* Count all modify-header actions as one action. */
5513 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5515 action_flags |= actions->type ==
5516 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5517 MLX5_FLOW_ACTION_SET_MAC_SRC :
5518 MLX5_FLOW_ACTION_SET_MAC_DST;
5520 * Even if the source and destination MAC addresses have
5521 * overlap in the header with 4B alignment, the convert
5522 * function will handle them separately and 4 SW actions
5523 * will be created. And 2 actions will be added each
5524 * time no matter how many bytes of address will be set.
5526 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5528 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5529 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5530 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5536 /* Count all modify-header actions as one action. */
5537 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5539 action_flags |= actions->type ==
5540 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5541 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5542 MLX5_FLOW_ACTION_SET_IPV4_DST;
5543 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5545 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5546 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5547 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5553 if (item_ipv6_proto == IPPROTO_ICMPV6)
5554 return rte_flow_error_set(error, ENOTSUP,
5555 RTE_FLOW_ERROR_TYPE_ACTION,
5557 "Can't change header "
5558 "with ICMPv6 proto");
5559 /* Count all modify-header actions as one action. */
5560 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5562 action_flags |= actions->type ==
5563 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5564 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5565 MLX5_FLOW_ACTION_SET_IPV6_DST;
5566 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5568 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5569 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5570 ret = flow_dv_validate_action_modify_tp(action_flags,
5576 /* Count all modify-header actions as one action. */
5577 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5579 action_flags |= actions->type ==
5580 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5581 MLX5_FLOW_ACTION_SET_TP_SRC :
5582 MLX5_FLOW_ACTION_SET_TP_DST;
5583 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5585 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5586 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5587 ret = flow_dv_validate_action_modify_ttl(action_flags,
5593 /* Count all modify-header actions as one action. */
5594 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5596 action_flags |= actions->type ==
5597 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5598 MLX5_FLOW_ACTION_SET_TTL :
5599 MLX5_FLOW_ACTION_DEC_TTL;
5600 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5602 case RTE_FLOW_ACTION_TYPE_JUMP:
5603 ret = flow_dv_validate_action_jump(actions,
5610 action_flags |= MLX5_FLOW_ACTION_JUMP;
5612 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5613 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5614 ret = flow_dv_validate_action_modify_tcp_seq
5621 /* Count all modify-header actions as one action. */
5622 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5624 action_flags |= actions->type ==
5625 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5626 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5627 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5628 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5630 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5631 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5632 ret = flow_dv_validate_action_modify_tcp_ack
5639 /* Count all modify-header actions as one action. */
5640 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5642 action_flags |= actions->type ==
5643 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5644 MLX5_FLOW_ACTION_INC_TCP_ACK :
5645 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5646 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5648 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5650 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5651 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5652 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5654 case RTE_FLOW_ACTION_TYPE_METER:
5655 ret = mlx5_flow_validate_action_meter(dev,
5661 action_flags |= MLX5_FLOW_ACTION_METER;
5663 /* Meter action will add one more TAG action. */
5664 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5666 case RTE_FLOW_ACTION_TYPE_AGE:
5667 ret = flow_dv_validate_action_age(action_flags,
5672 action_flags |= MLX5_FLOW_ACTION_AGE;
5675 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5676 ret = flow_dv_validate_action_modify_ipv4_dscp
5683 /* Count all modify-header actions as one action. */
5684 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5686 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5687 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5689 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5690 ret = flow_dv_validate_action_modify_ipv6_dscp
5697 /* Count all modify-header actions as one action. */
5698 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5700 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5701 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5704 return rte_flow_error_set(error, ENOTSUP,
5705 RTE_FLOW_ERROR_TYPE_ACTION,
5707 "action not supported");
5711 * Validate the drop action mutual exclusion with other actions.
5712 * Drop action is mutually-exclusive with any other action, except for
5715 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5716 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5717 return rte_flow_error_set(error, EINVAL,
5718 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5719 "Drop action is mutually-exclusive "
5720 "with any other action, except for "
5722 /* Eswitch has few restrictions on using items and actions */
5723 if (attr->transfer) {
5724 if (!mlx5_flow_ext_mreg_supported(dev) &&
5725 action_flags & MLX5_FLOW_ACTION_FLAG)
5726 return rte_flow_error_set(error, ENOTSUP,
5727 RTE_FLOW_ERROR_TYPE_ACTION,
5729 "unsupported action FLAG");
5730 if (!mlx5_flow_ext_mreg_supported(dev) &&
5731 action_flags & MLX5_FLOW_ACTION_MARK)
5732 return rte_flow_error_set(error, ENOTSUP,
5733 RTE_FLOW_ERROR_TYPE_ACTION,
5735 "unsupported action MARK");
5736 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5737 return rte_flow_error_set(error, ENOTSUP,
5738 RTE_FLOW_ERROR_TYPE_ACTION,
5740 "unsupported action QUEUE");
5741 if (action_flags & MLX5_FLOW_ACTION_RSS)
5742 return rte_flow_error_set(error, ENOTSUP,
5743 RTE_FLOW_ERROR_TYPE_ACTION,
5745 "unsupported action RSS");
5746 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5747 return rte_flow_error_set(error, EINVAL,
5748 RTE_FLOW_ERROR_TYPE_ACTION,
5750 "no fate action is found");
5752 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5753 return rte_flow_error_set(error, EINVAL,
5754 RTE_FLOW_ERROR_TYPE_ACTION,
5756 "no fate action is found");
5758 /* Continue validation for Xcap and VLAN actions.*/
5759 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
5760 MLX5_FLOW_VLAN_ACTIONS)) &&
5761 (queue_index == 0xFFFF ||
5762 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5763 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5764 MLX5_FLOW_XCAP_ACTIONS)
5765 return rte_flow_error_set(error, ENOTSUP,
5766 RTE_FLOW_ERROR_TYPE_ACTION,
5767 NULL, "encap and decap "
5768 "combination aren't supported");
5769 if (!attr->transfer && attr->ingress) {
5770 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
5771 return rte_flow_error_set
5773 RTE_FLOW_ERROR_TYPE_ACTION,
5774 NULL, "encap is not supported"
5775 " for ingress traffic");
5776 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5777 return rte_flow_error_set
5779 RTE_FLOW_ERROR_TYPE_ACTION,
5780 NULL, "push VLAN action not "
5781 "supported for ingress");
5782 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
5783 MLX5_FLOW_VLAN_ACTIONS)
5784 return rte_flow_error_set
5786 RTE_FLOW_ERROR_TYPE_ACTION,
5787 NULL, "no support for "
5788 "multiple VLAN actions");
5791 /* Hairpin flow will add one more TAG action. */
5793 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5794 /* extra metadata enabled: one more TAG action will be add. */
5795 if (dev_conf->dv_flow_en &&
5796 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5797 mlx5_flow_ext_mreg_supported(dev))
5798 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5799 if ((uint32_t)rw_act_num >
5800 flow_dv_modify_hdr_action_max(dev, is_root)) {
5801 return rte_flow_error_set(error, ENOTSUP,
5802 RTE_FLOW_ERROR_TYPE_ACTION,
5803 NULL, "too many header modify"
5804 " actions to support");
5810 * Internal preparation function. Allocates the DV flow size,
5811 * this size is constant.
5814 * Pointer to the rte_eth_dev structure.
5816 * Pointer to the flow attributes.
5818 * Pointer to the list of items.
5819 * @param[in] actions
5820 * Pointer to the list of actions.
5822 * Pointer to the error structure.
5825 * Pointer to mlx5_flow object on success,
5826 * otherwise NULL and rte_errno is set.
5828 static struct mlx5_flow *
5829 flow_dv_prepare(struct rte_eth_dev *dev,
5830 const struct rte_flow_attr *attr __rte_unused,
5831 const struct rte_flow_item items[] __rte_unused,
5832 const struct rte_flow_action actions[] __rte_unused,
5833 struct rte_flow_error *error)
5835 uint32_t handle_idx = 0;
5836 struct mlx5_flow *dev_flow;
5837 struct mlx5_flow_handle *dev_handle;
5838 struct mlx5_priv *priv = dev->data->dev_private;
5840 /* In case of corrupting the memory. */
5841 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5842 rte_flow_error_set(error, ENOSPC,
5843 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5844 "not free temporary device flow");
5847 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5850 rte_flow_error_set(error, ENOMEM,
5851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5852 "not enough memory to create flow handle");
5855 /* No multi-thread supporting. */
5856 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5857 dev_flow->handle = dev_handle;
5858 dev_flow->handle_idx = handle_idx;
5860 * In some old rdma-core releases, before continuing, a check of the
5861 * length of matching parameter will be done at first. It needs to use
5862 * the length without misc4 param. If the flow has misc4 support, then
5863 * the length needs to be adjusted accordingly. Each param member is
5864 * aligned with a 64B boundary naturally.
5866 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5867 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5869 * The matching value needs to be cleared to 0 before using. In the
5870 * past, it will be automatically cleared when using rte_*alloc
5871 * API. The time consumption will be almost the same as before.
5873 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5874 dev_flow->ingress = attr->ingress;
5875 dev_flow->dv.transfer = attr->transfer;
5879 #ifdef RTE_LIBRTE_MLX5_DEBUG
5881 * Sanity check for match mask and value. Similar to check_valid_spec() in
5882 * kernel driver. If unmasked bit is present in value, it returns failure.
5885 * pointer to match mask buffer.
5886 * @param match_value
5887 * pointer to match value buffer.
5890 * 0 if valid, -EINVAL otherwise.
5893 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5895 uint8_t *m = match_mask;
5896 uint8_t *v = match_value;
5899 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5902 "match_value differs from match_criteria"
5903 " %p[%u] != %p[%u]",
5904 match_value, i, match_mask, i);
5913 * Add match of ip_version.
5917 * @param[in] headers_v
5918 * Values header pointer.
5919 * @param[in] headers_m
5920 * Masks header pointer.
5921 * @param[in] ip_version
5922 * The IP version to set.
5925 flow_dv_set_match_ip_version(uint32_t group,
5931 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5933 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5935 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5936 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5941 * Add Ethernet item to matcher and to the value.
5943 * @param[in, out] matcher
5945 * @param[in, out] key
5946 * Flow matcher value.
5948 * Flow pattern to translate.
5950 * Item is inner pattern.
5953 flow_dv_translate_item_eth(void *matcher, void *key,
5954 const struct rte_flow_item *item, int inner,
5957 const struct rte_flow_item_eth *eth_m = item->mask;
5958 const struct rte_flow_item_eth *eth_v = item->spec;
5959 const struct rte_flow_item_eth nic_mask = {
5960 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5961 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5962 .type = RTE_BE16(0xffff),
5974 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5976 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5978 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5980 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5982 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5983 ð_m->dst, sizeof(eth_m->dst));
5984 /* The value must be in the range of the mask. */
5985 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5986 for (i = 0; i < sizeof(eth_m->dst); ++i)
5987 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5988 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5989 ð_m->src, sizeof(eth_m->src));
5990 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5991 /* The value must be in the range of the mask. */
5992 for (i = 0; i < sizeof(eth_m->dst); ++i)
5993 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5995 /* When ethertype is present set mask for tagged VLAN. */
5996 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5997 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5998 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5999 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6000 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6002 /* Return here to avoid setting match on ethertype. */
6007 * HW supports match on one Ethertype, the Ethertype following the last
6008 * VLAN tag of the packet (see PRM).
6009 * Set match on ethertype only if ETH header is not followed by VLAN.
6010 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6011 * ethertype, and use ip_version field instead.
6012 * eCPRI over Ether layer will use type value 0xAEFE.
6014 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6015 eth_m->type == 0xFFFF) {
6016 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6017 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6018 eth_m->type == 0xFFFF) {
6019 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6021 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6022 rte_be_to_cpu_16(eth_m->type));
6023 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6025 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6030 * Add VLAN item to matcher and to the value.
6032 * @param[in, out] dev_flow
6034 * @param[in, out] matcher
6036 * @param[in, out] key
6037 * Flow matcher value.
6039 * Flow pattern to translate.
6041 * Item is inner pattern.
6044 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6045 void *matcher, void *key,
6046 const struct rte_flow_item *item,
6047 int inner, uint32_t group)
6049 const struct rte_flow_item_vlan *vlan_m = item->mask;
6050 const struct rte_flow_item_vlan *vlan_v = item->spec;
6057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6059 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6061 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6063 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6065 * This is workaround, masks are not supported,
6066 * and pre-validated.
6069 dev_flow->handle->vf_vlan.tag =
6070 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6073 * When VLAN item exists in flow, mark packet as tagged,
6074 * even if TCI is not specified.
6076 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6077 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6081 vlan_m = &rte_flow_item_vlan_mask;
6082 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6083 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6084 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6085 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6086 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6087 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6088 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6091 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6092 * ethertype, and use ip_version field instead.
6094 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6095 vlan_m->inner_type == 0xFFFF) {
6096 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6097 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6098 vlan_m->inner_type == 0xFFFF) {
6099 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6101 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6102 rte_be_to_cpu_16(vlan_m->inner_type));
6103 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6104 rte_be_to_cpu_16(vlan_m->inner_type &
6105 vlan_v->inner_type));
6110 * Add IPV4 item to matcher and to the value.
6112 * @param[in, out] matcher
6114 * @param[in, out] key
6115 * Flow matcher value.
6117 * Flow pattern to translate.
6118 * @param[in] item_flags
6119 * Bit-fields that holds the items detected until now.
6121 * Item is inner pattern.
6123 * The group to insert the rule.
6126 flow_dv_translate_item_ipv4(void *matcher, void *key,
6127 const struct rte_flow_item *item,
6128 const uint64_t item_flags,
6129 int inner, uint32_t group)
6131 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6132 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6133 const struct rte_flow_item_ipv4 nic_mask = {
6135 .src_addr = RTE_BE32(0xffffffff),
6136 .dst_addr = RTE_BE32(0xffffffff),
6137 .type_of_service = 0xff,
6138 .next_proto_id = 0xff,
6139 .time_to_live = 0xff,
6149 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6151 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6153 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6155 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6157 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6159 * On outer header (which must contains L2), or inner header with L2,
6160 * set cvlan_tag mask bit to mark this packet as untagged.
6161 * This should be done even if item->spec is empty.
6163 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6164 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6169 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6170 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6171 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6172 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6173 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6174 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6175 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6176 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6177 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6178 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6179 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6180 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6181 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6182 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6183 ipv4_m->hdr.type_of_service);
6184 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6185 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6186 ipv4_m->hdr.type_of_service >> 2);
6187 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6188 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6189 ipv4_m->hdr.next_proto_id);
6190 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6191 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6192 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6193 ipv4_m->hdr.time_to_live);
6194 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6195 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6199 * Add IPV6 item to matcher and to the value.
6201 * @param[in, out] matcher
6203 * @param[in, out] key
6204 * Flow matcher value.
6206 * Flow pattern to translate.
6207 * @param[in] item_flags
6208 * Bit-fields that holds the items detected until now.
6210 * Item is inner pattern.
6212 * The group to insert the rule.
6215 flow_dv_translate_item_ipv6(void *matcher, void *key,
6216 const struct rte_flow_item *item,
6217 const uint64_t item_flags,
6218 int inner, uint32_t group)
6220 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6221 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6222 const struct rte_flow_item_ipv6 nic_mask = {
6225 "\xff\xff\xff\xff\xff\xff\xff\xff"
6226 "\xff\xff\xff\xff\xff\xff\xff\xff",
6228 "\xff\xff\xff\xff\xff\xff\xff\xff"
6229 "\xff\xff\xff\xff\xff\xff\xff\xff",
6230 .vtc_flow = RTE_BE32(0xffffffff),
6237 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6238 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6247 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6249 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6251 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6253 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6255 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6257 * On outer header (which must contains L2), or inner header with L2,
6258 * set cvlan_tag mask bit to mark this packet as untagged.
6259 * This should be done even if item->spec is empty.
6261 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6262 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6267 size = sizeof(ipv6_m->hdr.dst_addr);
6268 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6269 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6270 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6271 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6272 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6273 for (i = 0; i < size; ++i)
6274 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6275 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6276 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6277 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6278 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6279 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6280 for (i = 0; i < size; ++i)
6281 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6283 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6284 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6285 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6286 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6287 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6288 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6291 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6293 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6296 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6298 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6302 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6304 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6305 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6307 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6308 ipv6_m->hdr.hop_limits);
6309 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6310 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6314 * Add TCP item to matcher and to the value.
6316 * @param[in, out] matcher
6318 * @param[in, out] key
6319 * Flow matcher value.
6321 * Flow pattern to translate.
6323 * Item is inner pattern.
6326 flow_dv_translate_item_tcp(void *matcher, void *key,
6327 const struct rte_flow_item *item,
6330 const struct rte_flow_item_tcp *tcp_m = item->mask;
6331 const struct rte_flow_item_tcp *tcp_v = item->spec;
6336 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6338 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6340 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6342 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6344 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6349 tcp_m = &rte_flow_item_tcp_mask;
6350 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6351 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6352 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6353 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6354 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6355 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6356 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6357 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6358 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6359 tcp_m->hdr.tcp_flags);
6360 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6361 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6365 * Add UDP item to matcher and to the value.
6367 * @param[in, out] matcher
6369 * @param[in, out] key
6370 * Flow matcher value.
6372 * Flow pattern to translate.
6374 * Item is inner pattern.
6377 flow_dv_translate_item_udp(void *matcher, void *key,
6378 const struct rte_flow_item *item,
6381 const struct rte_flow_item_udp *udp_m = item->mask;
6382 const struct rte_flow_item_udp *udp_v = item->spec;
6387 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6389 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6391 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6393 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6395 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6396 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6400 udp_m = &rte_flow_item_udp_mask;
6401 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6402 rte_be_to_cpu_16(udp_m->hdr.src_port));
6403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6404 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6405 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6406 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6407 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6408 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6412 * Add GRE optional Key item to matcher and to the value.
6414 * @param[in, out] matcher
6416 * @param[in, out] key
6417 * Flow matcher value.
6419 * Flow pattern to translate.
6421 * Item is inner pattern.
6424 flow_dv_translate_item_gre_key(void *matcher, void *key,
6425 const struct rte_flow_item *item)
6427 const rte_be32_t *key_m = item->mask;
6428 const rte_be32_t *key_v = item->spec;
6429 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6430 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6431 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6433 /* GRE K bit must be on and should already be validated */
6434 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6435 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6439 key_m = &gre_key_default_mask;
6440 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6441 rte_be_to_cpu_32(*key_m) >> 8);
6442 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6443 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6444 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6445 rte_be_to_cpu_32(*key_m) & 0xFF);
6446 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6447 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6451 * Add GRE item to matcher and to the value.
6453 * @param[in, out] matcher
6455 * @param[in, out] key
6456 * Flow matcher value.
6458 * Flow pattern to translate.
6460 * Item is inner pattern.
6463 flow_dv_translate_item_gre(void *matcher, void *key,
6464 const struct rte_flow_item *item,
6467 const struct rte_flow_item_gre *gre_m = item->mask;
6468 const struct rte_flow_item_gre *gre_v = item->spec;
6471 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6472 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6479 uint16_t s_present:1;
6480 uint16_t k_present:1;
6481 uint16_t rsvd_bit1:1;
6482 uint16_t c_present:1;
6486 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6489 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6491 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6493 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6495 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6502 gre_m = &rte_flow_item_gre_mask;
6503 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6504 rte_be_to_cpu_16(gre_m->protocol));
6505 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6506 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6507 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6508 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6509 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6510 gre_crks_rsvd0_ver_m.c_present);
6511 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6512 gre_crks_rsvd0_ver_v.c_present &
6513 gre_crks_rsvd0_ver_m.c_present);
6514 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6515 gre_crks_rsvd0_ver_m.k_present);
6516 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6517 gre_crks_rsvd0_ver_v.k_present &
6518 gre_crks_rsvd0_ver_m.k_present);
6519 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6520 gre_crks_rsvd0_ver_m.s_present);
6521 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6522 gre_crks_rsvd0_ver_v.s_present &
6523 gre_crks_rsvd0_ver_m.s_present);
6527 * Add NVGRE item to matcher and to the value.
6529 * @param[in, out] matcher
6531 * @param[in, out] key
6532 * Flow matcher value.
6534 * Flow pattern to translate.
6536 * Item is inner pattern.
6539 flow_dv_translate_item_nvgre(void *matcher, void *key,
6540 const struct rte_flow_item *item,
6543 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6544 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6545 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6546 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6547 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6548 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6554 /* For NVGRE, GRE header fields must be set with defined values. */
6555 const struct rte_flow_item_gre gre_spec = {
6556 .c_rsvd0_ver = RTE_BE16(0x2000),
6557 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6559 const struct rte_flow_item_gre gre_mask = {
6560 .c_rsvd0_ver = RTE_BE16(0xB000),
6561 .protocol = RTE_BE16(UINT16_MAX),
6563 const struct rte_flow_item gre_item = {
6568 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6572 nvgre_m = &rte_flow_item_nvgre_mask;
6573 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6574 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6575 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6576 memcpy(gre_key_m, tni_flow_id_m, size);
6577 for (i = 0; i < size; ++i)
6578 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6582 * Add VXLAN item to matcher and to the value.
6584 * @param[in, out] matcher
6586 * @param[in, out] key
6587 * Flow matcher value.
6589 * Flow pattern to translate.
6591 * Item is inner pattern.
6594 flow_dv_translate_item_vxlan(void *matcher, void *key,
6595 const struct rte_flow_item *item,
6598 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6599 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6602 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6603 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6611 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6613 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6615 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6617 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6619 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6620 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6621 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6622 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6623 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6628 vxlan_m = &rte_flow_item_vxlan_mask;
6629 size = sizeof(vxlan_m->vni);
6630 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6631 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6632 memcpy(vni_m, vxlan_m->vni, size);
6633 for (i = 0; i < size; ++i)
6634 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6638 * Add VXLAN-GPE item to matcher and to the value.
6640 * @param[in, out] matcher
6642 * @param[in, out] key
6643 * Flow matcher value.
6645 * Flow pattern to translate.
6647 * Item is inner pattern.
6651 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6652 const struct rte_flow_item *item, int inner)
6654 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6655 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6659 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6661 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6667 uint8_t flags_m = 0xff;
6668 uint8_t flags_v = 0xc;
6671 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6673 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6675 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6677 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6679 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6680 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6681 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6682 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6688 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6689 size = sizeof(vxlan_m->vni);
6690 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6691 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6692 memcpy(vni_m, vxlan_m->vni, size);
6693 for (i = 0; i < size; ++i)
6694 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6695 if (vxlan_m->flags) {
6696 flags_m = vxlan_m->flags;
6697 flags_v = vxlan_v->flags;
6699 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6700 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6701 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6703 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6708 * Add Geneve item to matcher and to the value.
6710 * @param[in, out] matcher
6712 * @param[in, out] key
6713 * Flow matcher value.
6715 * Flow pattern to translate.
6717 * Item is inner pattern.
6721 flow_dv_translate_item_geneve(void *matcher, void *key,
6722 const struct rte_flow_item *item, int inner)
6724 const struct rte_flow_item_geneve *geneve_m = item->mask;
6725 const struct rte_flow_item_geneve *geneve_v = item->spec;
6728 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6729 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6738 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6740 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6742 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6744 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6746 dport = MLX5_UDP_PORT_GENEVE;
6747 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6748 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6754 geneve_m = &rte_flow_item_geneve_mask;
6755 size = sizeof(geneve_m->vni);
6756 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6757 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6758 memcpy(vni_m, geneve_m->vni, size);
6759 for (i = 0; i < size; ++i)
6760 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6761 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6762 rte_be_to_cpu_16(geneve_m->protocol));
6763 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6764 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6765 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6766 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6767 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6768 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6769 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6770 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6771 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6772 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6773 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6774 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6775 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6779 * Add MPLS item to matcher and to the value.
6781 * @param[in, out] matcher
6783 * @param[in, out] key
6784 * Flow matcher value.
6786 * Flow pattern to translate.
6787 * @param[in] prev_layer
6788 * The protocol layer indicated in previous item.
6790 * Item is inner pattern.
6793 flow_dv_translate_item_mpls(void *matcher, void *key,
6794 const struct rte_flow_item *item,
6795 uint64_t prev_layer,
6798 const uint32_t *in_mpls_m = item->mask;
6799 const uint32_t *in_mpls_v = item->spec;
6800 uint32_t *out_mpls_m = 0;
6801 uint32_t *out_mpls_v = 0;
6802 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6803 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6804 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6806 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6807 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6808 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6810 switch (prev_layer) {
6811 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6812 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6813 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6814 MLX5_UDP_PORT_MPLS);
6816 case MLX5_FLOW_LAYER_GRE:
6817 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6818 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6819 RTE_ETHER_TYPE_MPLS);
6822 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6823 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6830 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6831 switch (prev_layer) {
6832 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6834 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6835 outer_first_mpls_over_udp);
6837 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6838 outer_first_mpls_over_udp);
6840 case MLX5_FLOW_LAYER_GRE:
6842 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6843 outer_first_mpls_over_gre);
6845 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6846 outer_first_mpls_over_gre);
6849 /* Inner MPLS not over GRE is not supported. */
6852 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6856 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6862 if (out_mpls_m && out_mpls_v) {
6863 *out_mpls_m = *in_mpls_m;
6864 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6869 * Add metadata register item to matcher
6871 * @param[in, out] matcher
6873 * @param[in, out] key
6874 * Flow matcher value.
6875 * @param[in] reg_type
6876 * Type of device metadata register
6883 flow_dv_match_meta_reg(void *matcher, void *key,
6884 enum modify_reg reg_type,
6885 uint32_t data, uint32_t mask)
6888 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6890 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6896 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6897 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6900 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6901 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6905 * The metadata register C0 field might be divided into
6906 * source vport index and META item value, we should set
6907 * this field according to specified mask, not as whole one.
6909 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6911 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6912 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6915 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6918 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6919 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6922 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6923 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6926 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6927 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6930 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6931 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6934 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6935 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6938 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6939 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6942 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6943 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6952 * Add MARK item to matcher
6955 * The device to configure through.
6956 * @param[in, out] matcher
6958 * @param[in, out] key
6959 * Flow matcher value.
6961 * Flow pattern to translate.
6964 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6965 void *matcher, void *key,
6966 const struct rte_flow_item *item)
6968 struct mlx5_priv *priv = dev->data->dev_private;
6969 const struct rte_flow_item_mark *mark;
6973 mark = item->mask ? (const void *)item->mask :
6974 &rte_flow_item_mark_mask;
6975 mask = mark->id & priv->sh->dv_mark_mask;
6976 mark = (const void *)item->spec;
6978 value = mark->id & priv->sh->dv_mark_mask & mask;
6980 enum modify_reg reg;
6982 /* Get the metadata register index for the mark. */
6983 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6984 MLX5_ASSERT(reg > 0);
6985 if (reg == REG_C_0) {
6986 struct mlx5_priv *priv = dev->data->dev_private;
6987 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6988 uint32_t shl_c0 = rte_bsf32(msk_c0);
6994 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6999 * Add META item to matcher
7002 * The devich to configure through.
7003 * @param[in, out] matcher
7005 * @param[in, out] key
7006 * Flow matcher value.
7008 * Attributes of flow that includes this item.
7010 * Flow pattern to translate.
7013 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7014 void *matcher, void *key,
7015 const struct rte_flow_attr *attr,
7016 const struct rte_flow_item *item)
7018 const struct rte_flow_item_meta *meta_m;
7019 const struct rte_flow_item_meta *meta_v;
7021 meta_m = (const void *)item->mask;
7023 meta_m = &rte_flow_item_meta_mask;
7024 meta_v = (const void *)item->spec;
7027 uint32_t value = meta_v->data;
7028 uint32_t mask = meta_m->data;
7030 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7034 * In datapath code there is no endianness
7035 * coversions for perfromance reasons, all
7036 * pattern conversions are done in rte_flow.
7038 value = rte_cpu_to_be_32(value);
7039 mask = rte_cpu_to_be_32(mask);
7040 if (reg == REG_C_0) {
7041 struct mlx5_priv *priv = dev->data->dev_private;
7042 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7043 uint32_t shl_c0 = rte_bsf32(msk_c0);
7044 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7045 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7052 MLX5_ASSERT(msk_c0);
7053 MLX5_ASSERT(!(~msk_c0 & mask));
7055 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7060 * Add vport metadata Reg C0 item to matcher
7062 * @param[in, out] matcher
7064 * @param[in, out] key
7065 * Flow matcher value.
7067 * Flow pattern to translate.
7070 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7071 uint32_t value, uint32_t mask)
7073 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7077 * Add tag item to matcher
7080 * The devich to configure through.
7081 * @param[in, out] matcher
7083 * @param[in, out] key
7084 * Flow matcher value.
7086 * Flow pattern to translate.
7089 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7090 void *matcher, void *key,
7091 const struct rte_flow_item *item)
7093 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7094 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7095 uint32_t mask, value;
7098 value = tag_v->data;
7099 mask = tag_m ? tag_m->data : UINT32_MAX;
7100 if (tag_v->id == REG_C_0) {
7101 struct mlx5_priv *priv = dev->data->dev_private;
7102 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7103 uint32_t shl_c0 = rte_bsf32(msk_c0);
7109 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7113 * Add TAG item to matcher
7116 * The devich to configure through.
7117 * @param[in, out] matcher
7119 * @param[in, out] key
7120 * Flow matcher value.
7122 * Flow pattern to translate.
7125 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7126 void *matcher, void *key,
7127 const struct rte_flow_item *item)
7129 const struct rte_flow_item_tag *tag_v = item->spec;
7130 const struct rte_flow_item_tag *tag_m = item->mask;
7131 enum modify_reg reg;
7134 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7135 /* Get the metadata register index for the tag. */
7136 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7137 MLX5_ASSERT(reg > 0);
7138 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7142 * Add source vport match to the specified matcher.
7144 * @param[in, out] matcher
7146 * @param[in, out] key
7147 * Flow matcher value.
7149 * Source vport value to match
7154 flow_dv_translate_item_source_vport(void *matcher, void *key,
7155 int16_t port, uint16_t mask)
7157 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7158 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7160 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7161 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7165 * Translate port-id item to eswitch match on port-id.
7168 * The devich to configure through.
7169 * @param[in, out] matcher
7171 * @param[in, out] key
7172 * Flow matcher value.
7174 * Flow pattern to translate.
7177 * 0 on success, a negative errno value otherwise.
7180 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7181 void *key, const struct rte_flow_item *item)
7183 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7184 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7185 struct mlx5_priv *priv;
7188 mask = pid_m ? pid_m->id : 0xffff;
7189 id = pid_v ? pid_v->id : dev->data->port_id;
7190 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7193 /* Translate to vport field or to metadata, depending on mode. */
7194 if (priv->vport_meta_mask)
7195 flow_dv_translate_item_meta_vport(matcher, key,
7196 priv->vport_meta_tag,
7197 priv->vport_meta_mask);
7199 flow_dv_translate_item_source_vport(matcher, key,
7200 priv->vport_id, mask);
7205 * Add ICMP6 item to matcher and to the value.
7207 * @param[in, out] matcher
7209 * @param[in, out] key
7210 * Flow matcher value.
7212 * Flow pattern to translate.
7214 * Item is inner pattern.
7217 flow_dv_translate_item_icmp6(void *matcher, void *key,
7218 const struct rte_flow_item *item,
7221 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7222 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7225 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7227 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7229 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7231 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7233 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7235 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7237 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7238 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7242 icmp6_m = &rte_flow_item_icmp6_mask;
7244 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7245 * If only the protocol is specified, no need to match the frag.
7247 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7248 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7249 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7250 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7251 icmp6_v->type & icmp6_m->type);
7252 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7253 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7254 icmp6_v->code & icmp6_m->code);
7258 * Add ICMP item to matcher and to the value.
7260 * @param[in, out] matcher
7262 * @param[in, out] key
7263 * Flow matcher value.
7265 * Flow pattern to translate.
7267 * Item is inner pattern.
7270 flow_dv_translate_item_icmp(void *matcher, void *key,
7271 const struct rte_flow_item *item,
7274 const struct rte_flow_item_icmp *icmp_m = item->mask;
7275 const struct rte_flow_item_icmp *icmp_v = item->spec;
7278 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7280 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7282 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7284 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7286 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7288 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7290 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7291 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7295 icmp_m = &rte_flow_item_icmp_mask;
7297 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7298 * If only the protocol is specified, no need to match the frag.
7300 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7301 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7302 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7303 icmp_m->hdr.icmp_type);
7304 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7305 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7306 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7307 icmp_m->hdr.icmp_code);
7308 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7309 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7313 * Add GTP item to matcher and to the value.
7315 * @param[in, out] matcher
7317 * @param[in, out] key
7318 * Flow matcher value.
7320 * Flow pattern to translate.
7322 * Item is inner pattern.
7325 flow_dv_translate_item_gtp(void *matcher, void *key,
7326 const struct rte_flow_item *item, int inner)
7328 const struct rte_flow_item_gtp *gtp_m = item->mask;
7329 const struct rte_flow_item_gtp *gtp_v = item->spec;
7332 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7334 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7335 uint16_t dport = RTE_GTPU_UDP_PORT;
7338 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7340 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7342 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7344 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7346 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7347 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7348 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7353 gtp_m = &rte_flow_item_gtp_mask;
7354 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7355 gtp_m->v_pt_rsv_flags);
7356 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7357 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7358 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7359 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7360 gtp_v->msg_type & gtp_m->msg_type);
7361 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7362 rte_be_to_cpu_32(gtp_m->teid));
7363 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7364 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7368 * Add eCPRI item to matcher and to the value.
7371 * The devich to configure through.
7372 * @param[in, out] matcher
7374 * @param[in, out] key
7375 * Flow matcher value.
7377 * Flow pattern to translate.
7378 * @param[in] samples
7379 * Sample IDs to be used in the matching.
7382 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7383 void *key, const struct rte_flow_item *item)
7385 struct mlx5_priv *priv = dev->data->dev_private;
7386 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7387 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7388 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7390 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7398 ecpri_m = &rte_flow_item_ecpri_mask;
7400 * Maximal four DW samples are supported in a single matching now.
7401 * Two are used now for a eCPRI matching:
7402 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7403 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7406 if (!ecpri_m->hdr.common.u32)
7408 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7409 /* Need to take the whole DW as the mask to fill the entry. */
7410 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7411 prog_sample_field_value_0);
7412 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7413 prog_sample_field_value_0);
7414 /* Already big endian (network order) in the header. */
7415 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7416 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7417 /* Sample#0, used for matching type, offset 0. */
7418 MLX5_SET(fte_match_set_misc4, misc4_m,
7419 prog_sample_field_id_0, samples[0]);
7420 /* It makes no sense to set the sample ID in the mask field. */
7421 MLX5_SET(fte_match_set_misc4, misc4_v,
7422 prog_sample_field_id_0, samples[0]);
7424 * Checking if message body part needs to be matched.
7425 * Some wildcard rules only matching type field should be supported.
7427 if (ecpri_m->hdr.dummy[0]) {
7428 switch (ecpri_v->hdr.common.type) {
7429 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7430 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7431 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7432 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7433 prog_sample_field_value_1);
7434 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7435 prog_sample_field_value_1);
7436 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7437 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7438 /* Sample#1, to match message body, offset 4. */
7439 MLX5_SET(fte_match_set_misc4, misc4_m,
7440 prog_sample_field_id_1, samples[1]);
7441 MLX5_SET(fte_match_set_misc4, misc4_v,
7442 prog_sample_field_id_1, samples[1]);
7445 /* Others, do not match any sample ID. */
7451 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7453 #define HEADER_IS_ZERO(match_criteria, headers) \
7454 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7455 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7458 * Calculate flow matcher enable bitmap.
7460 * @param match_criteria
7461 * Pointer to flow matcher criteria.
7464 * Bitmap of enabled fields.
7467 flow_dv_matcher_enable(uint32_t *match_criteria)
7469 uint8_t match_criteria_enable;
7471 match_criteria_enable =
7472 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7473 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7474 match_criteria_enable |=
7475 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7476 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7477 match_criteria_enable |=
7478 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7479 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7480 match_criteria_enable |=
7481 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7482 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7483 match_criteria_enable |=
7484 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7485 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7486 match_criteria_enable |=
7487 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7488 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7489 return match_criteria_enable;
7496 * @param[in, out] dev
7497 * Pointer to rte_eth_dev structure.
7498 * @param[in] table_id
7501 * Direction of the table.
7502 * @param[in] transfer
7503 * E-Switch or NIC flow.
7505 * pointer to error structure.
7508 * Returns tables resource based on the index, NULL in case of failed.
7510 static struct mlx5_flow_tbl_resource *
7511 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7512 uint32_t table_id, uint8_t egress,
7514 struct rte_flow_error *error)
7516 struct mlx5_priv *priv = dev->data->dev_private;
7517 struct mlx5_dev_ctx_shared *sh = priv->sh;
7518 struct mlx5_flow_tbl_resource *tbl;
7519 union mlx5_flow_tbl_key table_key = {
7521 .table_id = table_id,
7523 .domain = !!transfer,
7524 .direction = !!egress,
7527 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7529 struct mlx5_flow_tbl_data_entry *tbl_data;
7535 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7537 tbl = &tbl_data->tbl;
7538 rte_atomic32_inc(&tbl->refcnt);
7541 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7543 rte_flow_error_set(error, ENOMEM,
7544 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7546 "cannot allocate flow table data entry");
7549 tbl_data->idx = idx;
7550 tbl = &tbl_data->tbl;
7551 pos = &tbl_data->entry;
7553 domain = sh->fdb_domain;
7555 domain = sh->tx_domain;
7557 domain = sh->rx_domain;
7558 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7560 rte_flow_error_set(error, ENOMEM,
7561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7562 NULL, "cannot create flow table object");
7563 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7567 * No multi-threads now, but still better to initialize the reference
7568 * count before insert it into the hash list.
7570 rte_atomic32_init(&tbl->refcnt);
7571 /* Jump action reference count is initialized here. */
7572 rte_atomic32_init(&tbl_data->jump.refcnt);
7573 pos->key = table_key.v64;
7574 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7576 rte_flow_error_set(error, -ret,
7577 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7578 "cannot insert flow table data entry");
7579 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7580 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7582 rte_atomic32_inc(&tbl->refcnt);
7587 * Release a flow table.
7590 * Pointer to rte_eth_dev structure.
7592 * Table resource to be released.
7595 * Returns 0 if table was released, else return 1;
7598 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7599 struct mlx5_flow_tbl_resource *tbl)
7601 struct mlx5_priv *priv = dev->data->dev_private;
7602 struct mlx5_dev_ctx_shared *sh = priv->sh;
7603 struct mlx5_flow_tbl_data_entry *tbl_data =
7604 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7608 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7609 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7611 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7613 /* remove the entry from the hash list and free memory. */
7614 mlx5_hlist_remove(sh->flow_tbls, pos);
7615 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7623 * Register the flow matcher.
7625 * @param[in, out] dev
7626 * Pointer to rte_eth_dev structure.
7627 * @param[in, out] matcher
7628 * Pointer to flow matcher.
7629 * @param[in, out] key
7630 * Pointer to flow table key.
7631 * @parm[in, out] dev_flow
7632 * Pointer to the dev_flow.
7634 * pointer to error structure.
7637 * 0 on success otherwise -errno and errno is set.
7640 flow_dv_matcher_register(struct rte_eth_dev *dev,
7641 struct mlx5_flow_dv_matcher *matcher,
7642 union mlx5_flow_tbl_key *key,
7643 struct mlx5_flow *dev_flow,
7644 struct rte_flow_error *error)
7646 struct mlx5_priv *priv = dev->data->dev_private;
7647 struct mlx5_dev_ctx_shared *sh = priv->sh;
7648 struct mlx5_flow_dv_matcher *cache_matcher;
7649 struct mlx5dv_flow_matcher_attr dv_attr = {
7650 .type = IBV_FLOW_ATTR_NORMAL,
7651 .match_mask = (void *)&matcher->mask,
7653 struct mlx5_flow_tbl_resource *tbl;
7654 struct mlx5_flow_tbl_data_entry *tbl_data;
7657 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7658 key->domain, error);
7660 return -rte_errno; /* No need to refill the error info */
7661 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7662 /* Lookup from cache. */
7663 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7664 if (matcher->crc == cache_matcher->crc &&
7665 matcher->priority == cache_matcher->priority &&
7666 !memcmp((const void *)matcher->mask.buf,
7667 (const void *)cache_matcher->mask.buf,
7668 cache_matcher->mask.size)) {
7670 "%s group %u priority %hd use %s "
7671 "matcher %p: refcnt %d++",
7672 key->domain ? "FDB" : "NIC", key->table_id,
7673 cache_matcher->priority,
7674 key->direction ? "tx" : "rx",
7675 (void *)cache_matcher,
7676 rte_atomic32_read(&cache_matcher->refcnt));
7677 rte_atomic32_inc(&cache_matcher->refcnt);
7678 dev_flow->handle->dvh.matcher = cache_matcher;
7679 /* old matcher should not make the table ref++. */
7680 flow_dv_tbl_resource_release(dev, tbl);
7684 /* Register new matcher. */
7685 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7687 if (!cache_matcher) {
7688 flow_dv_tbl_resource_release(dev, tbl);
7689 return rte_flow_error_set(error, ENOMEM,
7690 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7691 "cannot allocate matcher memory");
7693 *cache_matcher = *matcher;
7694 dv_attr.match_criteria_enable =
7695 flow_dv_matcher_enable(cache_matcher->mask.buf);
7696 dv_attr.priority = matcher->priority;
7698 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7699 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7700 &cache_matcher->matcher_object);
7702 mlx5_free(cache_matcher);
7703 #ifdef HAVE_MLX5DV_DR
7704 flow_dv_tbl_resource_release(dev, tbl);
7706 return rte_flow_error_set(error, ENOMEM,
7707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7708 NULL, "cannot create matcher");
7710 /* Save the table information */
7711 cache_matcher->tbl = tbl;
7712 rte_atomic32_init(&cache_matcher->refcnt);
7713 /* only matcher ref++, table ref++ already done above in get API. */
7714 rte_atomic32_inc(&cache_matcher->refcnt);
7715 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7716 dev_flow->handle->dvh.matcher = cache_matcher;
7717 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7718 key->domain ? "FDB" : "NIC", key->table_id,
7719 cache_matcher->priority,
7720 key->direction ? "tx" : "rx", (void *)cache_matcher,
7721 rte_atomic32_read(&cache_matcher->refcnt));
7726 * Find existing tag resource or create and register a new one.
7728 * @param dev[in, out]
7729 * Pointer to rte_eth_dev structure.
7730 * @param[in, out] tag_be24
7731 * Tag value in big endian then R-shift 8.
7732 * @parm[in, out] dev_flow
7733 * Pointer to the dev_flow.
7735 * pointer to error structure.
7738 * 0 on success otherwise -errno and errno is set.
7741 flow_dv_tag_resource_register
7742 (struct rte_eth_dev *dev,
7744 struct mlx5_flow *dev_flow,
7745 struct rte_flow_error *error)
7747 struct mlx5_priv *priv = dev->data->dev_private;
7748 struct mlx5_dev_ctx_shared *sh = priv->sh;
7749 struct mlx5_flow_dv_tag_resource *cache_resource;
7750 struct mlx5_hlist_entry *entry;
7753 /* Lookup a matching resource from cache. */
7754 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7756 cache_resource = container_of
7757 (entry, struct mlx5_flow_dv_tag_resource, entry);
7758 rte_atomic32_inc(&cache_resource->refcnt);
7759 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7760 dev_flow->dv.tag_resource = cache_resource;
7761 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7762 (void *)cache_resource,
7763 rte_atomic32_read(&cache_resource->refcnt));
7766 /* Register new resource. */
7767 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7768 &dev_flow->handle->dvh.rix_tag);
7769 if (!cache_resource)
7770 return rte_flow_error_set(error, ENOMEM,
7771 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7772 "cannot allocate resource memory");
7773 cache_resource->entry.key = (uint64_t)tag_be24;
7774 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7775 &cache_resource->action);
7777 mlx5_free(cache_resource);
7778 return rte_flow_error_set(error, ENOMEM,
7779 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7780 NULL, "cannot create action");
7782 rte_atomic32_init(&cache_resource->refcnt);
7783 rte_atomic32_inc(&cache_resource->refcnt);
7784 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7785 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7786 mlx5_free(cache_resource);
7787 return rte_flow_error_set(error, EEXIST,
7788 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7789 NULL, "cannot insert tag");
7791 dev_flow->dv.tag_resource = cache_resource;
7792 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7793 (void *)cache_resource,
7794 rte_atomic32_read(&cache_resource->refcnt));
7802 * Pointer to Ethernet device.
7807 * 1 while a reference on it exists, 0 when freed.
7810 flow_dv_tag_release(struct rte_eth_dev *dev,
7813 struct mlx5_priv *priv = dev->data->dev_private;
7814 struct mlx5_dev_ctx_shared *sh = priv->sh;
7815 struct mlx5_flow_dv_tag_resource *tag;
7817 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7820 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7821 dev->data->port_id, (void *)tag,
7822 rte_atomic32_read(&tag->refcnt));
7823 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7824 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7825 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7826 DRV_LOG(DEBUG, "port %u tag %p: removed",
7827 dev->data->port_id, (void *)tag);
7828 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7835 * Translate port ID action to vport.
7838 * Pointer to rte_eth_dev structure.
7840 * Pointer to the port ID action.
7841 * @param[out] dst_port_id
7842 * The target port ID.
7844 * Pointer to the error structure.
7847 * 0 on success, a negative errno value otherwise and rte_errno is set.
7850 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7851 const struct rte_flow_action *action,
7852 uint32_t *dst_port_id,
7853 struct rte_flow_error *error)
7856 struct mlx5_priv *priv;
7857 const struct rte_flow_action_port_id *conf =
7858 (const struct rte_flow_action_port_id *)action->conf;
7860 port = conf->original ? dev->data->port_id : conf->id;
7861 priv = mlx5_port_to_eswitch_info(port, false);
7863 return rte_flow_error_set(error, -rte_errno,
7864 RTE_FLOW_ERROR_TYPE_ACTION,
7866 "No eswitch info was found for port");
7867 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7869 * This parameter is transferred to
7870 * mlx5dv_dr_action_create_dest_ib_port().
7872 *dst_port_id = priv->dev_port;
7875 * Legacy mode, no LAG configurations is supported.
7876 * This parameter is transferred to
7877 * mlx5dv_dr_action_create_dest_vport().
7879 *dst_port_id = priv->vport_id;
7885 * Create a counter with aging configuration.
7888 * Pointer to rte_eth_dev structure.
7890 * Pointer to the counter action configuration.
7892 * Pointer to the aging action configuration.
7895 * Index to flow counter on success, 0 otherwise.
7898 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7899 struct mlx5_flow *dev_flow,
7900 const struct rte_flow_action_count *count,
7901 const struct rte_flow_action_age *age)
7904 struct mlx5_age_param *age_param;
7906 counter = flow_dv_counter_alloc(dev,
7907 count ? count->shared : 0,
7908 count ? count->id : 0,
7909 dev_flow->dv.group, !!age);
7910 if (!counter || age == NULL)
7912 age_param = flow_dv_counter_idx_get_age(dev, counter);
7914 * The counter age accuracy may have a bit delay. Have 3/4
7915 * second bias on the timeount in order to let it age in time.
7917 age_param->context = age->context ? age->context :
7918 (void *)(uintptr_t)(dev_flow->flow_idx);
7920 * The counter age accuracy may have a bit delay. Have 3/4
7921 * second bias on the timeount in order to let it age in time.
7923 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7924 /* Set expire time in unit of 0.1 sec. */
7925 age_param->port_id = dev->data->port_id;
7926 age_param->expire = age_param->timeout +
7927 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7928 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7932 * Add Tx queue matcher
7935 * Pointer to the dev struct.
7936 * @param[in, out] matcher
7938 * @param[in, out] key
7939 * Flow matcher value.
7941 * Flow pattern to translate.
7943 * Item is inner pattern.
7946 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7947 void *matcher, void *key,
7948 const struct rte_flow_item *item)
7950 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7951 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7953 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7955 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7956 struct mlx5_txq_ctrl *txq;
7960 queue_m = (const void *)item->mask;
7963 queue_v = (const void *)item->spec;
7966 txq = mlx5_txq_get(dev, queue_v->queue);
7969 queue = txq->obj->sq->id;
7970 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7971 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7972 queue & queue_m->queue);
7973 mlx5_txq_release(dev, queue_v->queue);
7977 * Set the hash fields according to the @p flow information.
7979 * @param[in] dev_flow
7980 * Pointer to the mlx5_flow.
7981 * @param[in] rss_desc
7982 * Pointer to the mlx5_flow_rss_desc.
7985 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7986 struct mlx5_flow_rss_desc *rss_desc)
7988 uint64_t items = dev_flow->handle->layers;
7990 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7992 dev_flow->hash_fields = 0;
7993 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7994 if (rss_desc->level >= 2) {
7995 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7999 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8000 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8001 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8002 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8003 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8004 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8005 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8007 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8009 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8010 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8011 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8012 if (rss_types & ETH_RSS_L3_SRC_ONLY)
8013 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8014 else if (rss_types & ETH_RSS_L3_DST_ONLY)
8015 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8017 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8020 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8021 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8022 if (rss_types & ETH_RSS_UDP) {
8023 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8024 dev_flow->hash_fields |=
8025 IBV_RX_HASH_SRC_PORT_UDP;
8026 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8027 dev_flow->hash_fields |=
8028 IBV_RX_HASH_DST_PORT_UDP;
8030 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8032 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8033 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8034 if (rss_types & ETH_RSS_TCP) {
8035 if (rss_types & ETH_RSS_L4_SRC_ONLY)
8036 dev_flow->hash_fields |=
8037 IBV_RX_HASH_SRC_PORT_TCP;
8038 else if (rss_types & ETH_RSS_L4_DST_ONLY)
8039 dev_flow->hash_fields |=
8040 IBV_RX_HASH_DST_PORT_TCP;
8042 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8048 * Fill the flow with DV spec, lock free
8049 * (mutex should be acquired by caller).
8052 * Pointer to rte_eth_dev structure.
8053 * @param[in, out] dev_flow
8054 * Pointer to the sub flow.
8056 * Pointer to the flow attributes.
8058 * Pointer to the list of items.
8059 * @param[in] actions
8060 * Pointer to the list of actions.
8062 * Pointer to the error structure.
8065 * 0 on success, a negative errno value otherwise and rte_errno is set.
8068 __flow_dv_translate(struct rte_eth_dev *dev,
8069 struct mlx5_flow *dev_flow,
8070 const struct rte_flow_attr *attr,
8071 const struct rte_flow_item items[],
8072 const struct rte_flow_action actions[],
8073 struct rte_flow_error *error)
8075 struct mlx5_priv *priv = dev->data->dev_private;
8076 struct mlx5_dev_config *dev_conf = &priv->config;
8077 struct rte_flow *flow = dev_flow->flow;
8078 struct mlx5_flow_handle *handle = dev_flow->handle;
8079 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8081 [!!priv->flow_nested_idx];
8082 uint64_t item_flags = 0;
8083 uint64_t last_item = 0;
8084 uint64_t action_flags = 0;
8085 uint64_t priority = attr->priority;
8086 struct mlx5_flow_dv_matcher matcher = {
8088 .size = sizeof(matcher.mask.buf) -
8089 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8093 bool actions_end = false;
8095 struct mlx5_flow_dv_modify_hdr_resource res;
8096 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8097 sizeof(struct mlx5_modification_cmd) *
8098 (MLX5_MAX_MODIFY_NUM + 1)];
8100 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8101 const struct rte_flow_action_count *count = NULL;
8102 const struct rte_flow_action_age *age = NULL;
8103 union flow_dv_attr flow_attr = { .attr = 0 };
8105 union mlx5_flow_tbl_key tbl_key;
8106 uint32_t modify_action_position = UINT32_MAX;
8107 void *match_mask = matcher.mask.buf;
8108 void *match_value = dev_flow->dv.value.buf;
8109 uint8_t next_protocol = 0xff;
8110 struct rte_vlan_hdr vlan = { 0 };
8114 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8115 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8116 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8117 !!priv->fdb_def_rule, &table, error);
8120 dev_flow->dv.group = table;
8122 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8123 if (priority == MLX5_FLOW_PRIO_RSVD)
8124 priority = dev_conf->flow_prio - 1;
8125 /* number of actions must be set to 0 in case of dirty stack. */
8126 mhdr_res->actions_num = 0;
8127 for (; !actions_end ; actions++) {
8128 const struct rte_flow_action_queue *queue;
8129 const struct rte_flow_action_rss *rss;
8130 const struct rte_flow_action *action = actions;
8131 const uint8_t *rss_key;
8132 const struct rte_flow_action_jump *jump_data;
8133 const struct rte_flow_action_meter *mtr;
8134 struct mlx5_flow_tbl_resource *tbl;
8135 uint32_t port_id = 0;
8136 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8137 int action_type = actions->type;
8138 const struct rte_flow_action *found_action = NULL;
8139 struct mlx5_flow_meter *fm = NULL;
8141 if (!mlx5_flow_os_action_supported(action_type))
8142 return rte_flow_error_set(error, ENOTSUP,
8143 RTE_FLOW_ERROR_TYPE_ACTION,
8145 "action not supported");
8146 switch (action_type) {
8147 case RTE_FLOW_ACTION_TYPE_VOID:
8149 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8150 if (flow_dv_translate_action_port_id(dev, action,
8153 port_id_resource.port_id = port_id;
8154 MLX5_ASSERT(!handle->rix_port_id_action);
8155 if (flow_dv_port_id_action_resource_register
8156 (dev, &port_id_resource, dev_flow, error))
8158 dev_flow->dv.actions[actions_n++] =
8159 dev_flow->dv.port_id_action->action;
8160 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8161 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8163 case RTE_FLOW_ACTION_TYPE_FLAG:
8164 action_flags |= MLX5_FLOW_ACTION_FLAG;
8165 dev_flow->handle->mark = 1;
8166 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8167 struct rte_flow_action_mark mark = {
8168 .id = MLX5_FLOW_MARK_DEFAULT,
8171 if (flow_dv_convert_action_mark(dev, &mark,
8175 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8178 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8180 * Only one FLAG or MARK is supported per device flow
8181 * right now. So the pointer to the tag resource must be
8182 * zero before the register process.
8184 MLX5_ASSERT(!handle->dvh.rix_tag);
8185 if (flow_dv_tag_resource_register(dev, tag_be,
8188 MLX5_ASSERT(dev_flow->dv.tag_resource);
8189 dev_flow->dv.actions[actions_n++] =
8190 dev_flow->dv.tag_resource->action;
8192 case RTE_FLOW_ACTION_TYPE_MARK:
8193 action_flags |= MLX5_FLOW_ACTION_MARK;
8194 dev_flow->handle->mark = 1;
8195 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8196 const struct rte_flow_action_mark *mark =
8197 (const struct rte_flow_action_mark *)
8200 if (flow_dv_convert_action_mark(dev, mark,
8204 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8208 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8209 /* Legacy (non-extensive) MARK action. */
8210 tag_be = mlx5_flow_mark_set
8211 (((const struct rte_flow_action_mark *)
8212 (actions->conf))->id);
8213 MLX5_ASSERT(!handle->dvh.rix_tag);
8214 if (flow_dv_tag_resource_register(dev, tag_be,
8217 MLX5_ASSERT(dev_flow->dv.tag_resource);
8218 dev_flow->dv.actions[actions_n++] =
8219 dev_flow->dv.tag_resource->action;
8221 case RTE_FLOW_ACTION_TYPE_SET_META:
8222 if (flow_dv_convert_action_set_meta
8223 (dev, mhdr_res, attr,
8224 (const struct rte_flow_action_set_meta *)
8225 actions->conf, error))
8227 action_flags |= MLX5_FLOW_ACTION_SET_META;
8229 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8230 if (flow_dv_convert_action_set_tag
8232 (const struct rte_flow_action_set_tag *)
8233 actions->conf, error))
8235 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8237 case RTE_FLOW_ACTION_TYPE_DROP:
8238 action_flags |= MLX5_FLOW_ACTION_DROP;
8239 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8241 case RTE_FLOW_ACTION_TYPE_QUEUE:
8242 queue = actions->conf;
8243 rss_desc->queue_num = 1;
8244 rss_desc->queue[0] = queue->index;
8245 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8246 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8248 case RTE_FLOW_ACTION_TYPE_RSS:
8249 rss = actions->conf;
8250 memcpy(rss_desc->queue, rss->queue,
8251 rss->queue_num * sizeof(uint16_t));
8252 rss_desc->queue_num = rss->queue_num;
8253 /* NULL RSS key indicates default RSS key. */
8254 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8255 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8257 * rss->level and rss.types should be set in advance
8258 * when expanding items for RSS.
8260 action_flags |= MLX5_FLOW_ACTION_RSS;
8261 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8263 case RTE_FLOW_ACTION_TYPE_AGE:
8264 case RTE_FLOW_ACTION_TYPE_COUNT:
8265 if (!dev_conf->devx) {
8266 return rte_flow_error_set
8268 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8270 "count action not supported");
8272 /* Save information first, will apply later. */
8273 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8274 count = action->conf;
8277 action_flags |= MLX5_FLOW_ACTION_COUNT;
8279 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8280 dev_flow->dv.actions[actions_n++] =
8281 priv->sh->pop_vlan_action;
8282 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8284 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8285 if (!(action_flags &
8286 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8287 flow_dev_get_vlan_info_from_items(items, &vlan);
8288 vlan.eth_proto = rte_be_to_cpu_16
8289 ((((const struct rte_flow_action_of_push_vlan *)
8290 actions->conf)->ethertype));
8291 found_action = mlx5_flow_find_action
8293 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8295 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8296 found_action = mlx5_flow_find_action
8298 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8300 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8301 if (flow_dv_create_action_push_vlan
8302 (dev, attr, &vlan, dev_flow, error))
8304 dev_flow->dv.actions[actions_n++] =
8305 dev_flow->dv.push_vlan_res->action;
8306 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8308 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8309 /* of_vlan_push action handled this action */
8310 MLX5_ASSERT(action_flags &
8311 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8313 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8314 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8316 flow_dev_get_vlan_info_from_items(items, &vlan);
8317 mlx5_update_vlan_vid_pcp(actions, &vlan);
8318 /* If no VLAN push - this is a modify header action */
8319 if (flow_dv_convert_action_modify_vlan_vid
8320 (mhdr_res, actions, error))
8322 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8324 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8325 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8326 if (flow_dv_create_action_l2_encap(dev, actions,
8331 dev_flow->dv.actions[actions_n++] =
8332 dev_flow->dv.encap_decap->action;
8333 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8335 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8336 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8337 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8341 dev_flow->dv.actions[actions_n++] =
8342 dev_flow->dv.encap_decap->action;
8343 action_flags |= MLX5_FLOW_ACTION_DECAP;
8345 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8346 /* Handle encap with preceding decap. */
8347 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8348 if (flow_dv_create_action_raw_encap
8349 (dev, actions, dev_flow, attr, error))
8351 dev_flow->dv.actions[actions_n++] =
8352 dev_flow->dv.encap_decap->action;
8354 /* Handle encap without preceding decap. */
8355 if (flow_dv_create_action_l2_encap
8356 (dev, actions, dev_flow, attr->transfer,
8359 dev_flow->dv.actions[actions_n++] =
8360 dev_flow->dv.encap_decap->action;
8362 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8364 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8365 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8367 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8368 if (flow_dv_create_action_l2_decap
8369 (dev, dev_flow, attr->transfer, error))
8371 dev_flow->dv.actions[actions_n++] =
8372 dev_flow->dv.encap_decap->action;
8374 /* If decap is followed by encap, handle it at encap. */
8375 action_flags |= MLX5_FLOW_ACTION_DECAP;
8377 case RTE_FLOW_ACTION_TYPE_JUMP:
8378 jump_data = action->conf;
8379 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8381 !!priv->fdb_def_rule,
8385 tbl = flow_dv_tbl_resource_get(dev, table,
8387 attr->transfer, error);
8389 return rte_flow_error_set
8391 RTE_FLOW_ERROR_TYPE_ACTION,
8393 "cannot create jump action.");
8394 if (flow_dv_jump_tbl_resource_register
8395 (dev, tbl, dev_flow, error)) {
8396 flow_dv_tbl_resource_release(dev, tbl);
8397 return rte_flow_error_set
8399 RTE_FLOW_ERROR_TYPE_ACTION,
8401 "cannot create jump action.");
8403 dev_flow->dv.actions[actions_n++] =
8404 dev_flow->dv.jump->action;
8405 action_flags |= MLX5_FLOW_ACTION_JUMP;
8406 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8408 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8409 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8410 if (flow_dv_convert_action_modify_mac
8411 (mhdr_res, actions, error))
8413 action_flags |= actions->type ==
8414 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8415 MLX5_FLOW_ACTION_SET_MAC_SRC :
8416 MLX5_FLOW_ACTION_SET_MAC_DST;
8418 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8419 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8420 if (flow_dv_convert_action_modify_ipv4
8421 (mhdr_res, actions, error))
8423 action_flags |= actions->type ==
8424 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8425 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8426 MLX5_FLOW_ACTION_SET_IPV4_DST;
8428 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8429 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8430 if (flow_dv_convert_action_modify_ipv6
8431 (mhdr_res, actions, error))
8433 action_flags |= actions->type ==
8434 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8435 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8436 MLX5_FLOW_ACTION_SET_IPV6_DST;
8438 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8439 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8440 if (flow_dv_convert_action_modify_tp
8441 (mhdr_res, actions, items,
8442 &flow_attr, dev_flow, !!(action_flags &
8443 MLX5_FLOW_ACTION_DECAP), error))
8445 action_flags |= actions->type ==
8446 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8447 MLX5_FLOW_ACTION_SET_TP_SRC :
8448 MLX5_FLOW_ACTION_SET_TP_DST;
8450 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8451 if (flow_dv_convert_action_modify_dec_ttl
8452 (mhdr_res, items, &flow_attr, dev_flow,
8454 MLX5_FLOW_ACTION_DECAP), error))
8456 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8458 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8459 if (flow_dv_convert_action_modify_ttl
8460 (mhdr_res, actions, items, &flow_attr,
8461 dev_flow, !!(action_flags &
8462 MLX5_FLOW_ACTION_DECAP), error))
8464 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8466 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8467 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8468 if (flow_dv_convert_action_modify_tcp_seq
8469 (mhdr_res, actions, error))
8471 action_flags |= actions->type ==
8472 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8473 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8474 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8477 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8478 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8479 if (flow_dv_convert_action_modify_tcp_ack
8480 (mhdr_res, actions, error))
8482 action_flags |= actions->type ==
8483 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8484 MLX5_FLOW_ACTION_INC_TCP_ACK :
8485 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8487 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8488 if (flow_dv_convert_action_set_reg
8489 (mhdr_res, actions, error))
8491 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8493 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8494 if (flow_dv_convert_action_copy_mreg
8495 (dev, mhdr_res, actions, error))
8497 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8499 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8500 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8501 dev_flow->handle->fate_action =
8502 MLX5_FLOW_FATE_DEFAULT_MISS;
8504 case RTE_FLOW_ACTION_TYPE_METER:
8505 mtr = actions->conf;
8507 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8510 return rte_flow_error_set(error,
8512 RTE_FLOW_ERROR_TYPE_ACTION,
8515 "or invalid parameters");
8516 flow->meter = fm->idx;
8518 /* Set the meter action. */
8520 fm = mlx5_ipool_get(priv->sh->ipool
8521 [MLX5_IPOOL_MTR], flow->meter);
8523 return rte_flow_error_set(error,
8525 RTE_FLOW_ERROR_TYPE_ACTION,
8528 "or invalid parameters");
8530 dev_flow->dv.actions[actions_n++] =
8531 fm->mfts->meter_action;
8532 action_flags |= MLX5_FLOW_ACTION_METER;
8534 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8535 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8538 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8540 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8541 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8544 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8546 case RTE_FLOW_ACTION_TYPE_END:
8548 if (mhdr_res->actions_num) {
8549 /* create modify action if needed. */
8550 if (flow_dv_modify_hdr_resource_register
8551 (dev, mhdr_res, dev_flow, error))
8553 dev_flow->dv.actions[modify_action_position] =
8554 handle->dvh.modify_hdr->action;
8556 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8558 flow_dv_translate_create_counter(dev,
8559 dev_flow, count, age);
8562 return rte_flow_error_set
8564 RTE_FLOW_ERROR_TYPE_ACTION,
8566 "cannot create counter"
8568 dev_flow->dv.actions[actions_n++] =
8569 (flow_dv_counter_get_by_idx(dev,
8570 flow->counter, NULL))->action;
8576 if (mhdr_res->actions_num &&
8577 modify_action_position == UINT32_MAX)
8578 modify_action_position = actions_n++;
8580 dev_flow->dv.actions_n = actions_n;
8581 dev_flow->act_flags = action_flags;
8582 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8583 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8584 int item_type = items->type;
8586 if (!mlx5_flow_os_item_supported(item_type))
8587 return rte_flow_error_set(error, ENOTSUP,
8588 RTE_FLOW_ERROR_TYPE_ITEM,
8589 NULL, "item not supported");
8590 switch (item_type) {
8591 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8592 flow_dv_translate_item_port_id(dev, match_mask,
8593 match_value, items);
8594 last_item = MLX5_FLOW_ITEM_PORT_ID;
8596 case RTE_FLOW_ITEM_TYPE_ETH:
8597 flow_dv_translate_item_eth(match_mask, match_value,
8599 dev_flow->dv.group);
8600 matcher.priority = action_flags &
8601 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8602 !dev_flow->external ?
8603 MLX5_PRIORITY_MAP_L3 :
8604 MLX5_PRIORITY_MAP_L2;
8605 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8606 MLX5_FLOW_LAYER_OUTER_L2;
8608 case RTE_FLOW_ITEM_TYPE_VLAN:
8609 flow_dv_translate_item_vlan(dev_flow,
8610 match_mask, match_value,
8612 dev_flow->dv.group);
8613 matcher.priority = MLX5_PRIORITY_MAP_L2;
8614 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8615 MLX5_FLOW_LAYER_INNER_VLAN) :
8616 (MLX5_FLOW_LAYER_OUTER_L2 |
8617 MLX5_FLOW_LAYER_OUTER_VLAN);
8619 case RTE_FLOW_ITEM_TYPE_IPV4:
8620 mlx5_flow_tunnel_ip_check(items, next_protocol,
8621 &item_flags, &tunnel);
8622 flow_dv_translate_item_ipv4(match_mask, match_value,
8623 items, item_flags, tunnel,
8624 dev_flow->dv.group);
8625 matcher.priority = MLX5_PRIORITY_MAP_L3;
8626 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8627 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8628 if (items->mask != NULL &&
8629 ((const struct rte_flow_item_ipv4 *)
8630 items->mask)->hdr.next_proto_id) {
8632 ((const struct rte_flow_item_ipv4 *)
8633 (items->spec))->hdr.next_proto_id;
8635 ((const struct rte_flow_item_ipv4 *)
8636 (items->mask))->hdr.next_proto_id;
8638 /* Reset for inner layer. */
8639 next_protocol = 0xff;
8642 case RTE_FLOW_ITEM_TYPE_IPV6:
8643 mlx5_flow_tunnel_ip_check(items, next_protocol,
8644 &item_flags, &tunnel);
8645 flow_dv_translate_item_ipv6(match_mask, match_value,
8646 items, item_flags, tunnel,
8647 dev_flow->dv.group);
8648 matcher.priority = MLX5_PRIORITY_MAP_L3;
8649 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8650 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8651 if (items->mask != NULL &&
8652 ((const struct rte_flow_item_ipv6 *)
8653 items->mask)->hdr.proto) {
8655 ((const struct rte_flow_item_ipv6 *)
8656 items->spec)->hdr.proto;
8658 ((const struct rte_flow_item_ipv6 *)
8659 items->mask)->hdr.proto;
8661 /* Reset for inner layer. */
8662 next_protocol = 0xff;
8665 case RTE_FLOW_ITEM_TYPE_TCP:
8666 flow_dv_translate_item_tcp(match_mask, match_value,
8668 matcher.priority = MLX5_PRIORITY_MAP_L4;
8669 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8670 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8672 case RTE_FLOW_ITEM_TYPE_UDP:
8673 flow_dv_translate_item_udp(match_mask, match_value,
8675 matcher.priority = MLX5_PRIORITY_MAP_L4;
8676 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8677 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8679 case RTE_FLOW_ITEM_TYPE_GRE:
8680 flow_dv_translate_item_gre(match_mask, match_value,
8682 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8683 last_item = MLX5_FLOW_LAYER_GRE;
8685 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8686 flow_dv_translate_item_gre_key(match_mask,
8687 match_value, items);
8688 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8690 case RTE_FLOW_ITEM_TYPE_NVGRE:
8691 flow_dv_translate_item_nvgre(match_mask, match_value,
8693 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8694 last_item = MLX5_FLOW_LAYER_GRE;
8696 case RTE_FLOW_ITEM_TYPE_VXLAN:
8697 flow_dv_translate_item_vxlan(match_mask, match_value,
8699 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8700 last_item = MLX5_FLOW_LAYER_VXLAN;
8702 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8703 flow_dv_translate_item_vxlan_gpe(match_mask,
8706 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8707 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8709 case RTE_FLOW_ITEM_TYPE_GENEVE:
8710 flow_dv_translate_item_geneve(match_mask, match_value,
8712 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8713 last_item = MLX5_FLOW_LAYER_GENEVE;
8715 case RTE_FLOW_ITEM_TYPE_MPLS:
8716 flow_dv_translate_item_mpls(match_mask, match_value,
8717 items, last_item, tunnel);
8718 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8719 last_item = MLX5_FLOW_LAYER_MPLS;
8721 case RTE_FLOW_ITEM_TYPE_MARK:
8722 flow_dv_translate_item_mark(dev, match_mask,
8723 match_value, items);
8724 last_item = MLX5_FLOW_ITEM_MARK;
8726 case RTE_FLOW_ITEM_TYPE_META:
8727 flow_dv_translate_item_meta(dev, match_mask,
8728 match_value, attr, items);
8729 last_item = MLX5_FLOW_ITEM_METADATA;
8731 case RTE_FLOW_ITEM_TYPE_ICMP:
8732 flow_dv_translate_item_icmp(match_mask, match_value,
8734 last_item = MLX5_FLOW_LAYER_ICMP;
8736 case RTE_FLOW_ITEM_TYPE_ICMP6:
8737 flow_dv_translate_item_icmp6(match_mask, match_value,
8739 last_item = MLX5_FLOW_LAYER_ICMP6;
8741 case RTE_FLOW_ITEM_TYPE_TAG:
8742 flow_dv_translate_item_tag(dev, match_mask,
8743 match_value, items);
8744 last_item = MLX5_FLOW_ITEM_TAG;
8746 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8747 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8748 match_value, items);
8749 last_item = MLX5_FLOW_ITEM_TAG;
8751 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8752 flow_dv_translate_item_tx_queue(dev, match_mask,
8755 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8757 case RTE_FLOW_ITEM_TYPE_GTP:
8758 flow_dv_translate_item_gtp(match_mask, match_value,
8760 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8761 last_item = MLX5_FLOW_LAYER_GTP;
8763 case RTE_FLOW_ITEM_TYPE_ECPRI:
8764 if (!mlx5_flex_parser_ecpri_exist(dev)) {
8765 /* Create it only the first time to be used. */
8766 ret = mlx5_flex_parser_ecpri_alloc(dev);
8768 return rte_flow_error_set
8770 RTE_FLOW_ERROR_TYPE_ITEM,
8772 "cannot create eCPRI parser");
8774 /* Adjust the length matcher and device flow value. */
8775 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8776 dev_flow->dv.value.size =
8777 MLX5_ST_SZ_BYTES(fte_match_param);
8778 flow_dv_translate_item_ecpri(dev, match_mask,
8779 match_value, items);
8780 /* No other protocol should follow eCPRI layer. */
8781 last_item = MLX5_FLOW_LAYER_ECPRI;
8786 item_flags |= last_item;
8789 * When E-Switch mode is enabled, we have two cases where we need to
8790 * set the source port manually.
8791 * The first one, is in case of Nic steering rule, and the second is
8792 * E-Switch rule where no port_id item was found. In both cases
8793 * the source port is set according the current port in use.
8795 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8796 (priv->representor || priv->master)) {
8797 if (flow_dv_translate_item_port_id(dev, match_mask,
8801 #ifdef RTE_LIBRTE_MLX5_DEBUG
8802 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8803 dev_flow->dv.value.buf));
8806 * Layers may be already initialized from prefix flow if this dev_flow
8807 * is the suffix flow.
8809 handle->layers |= item_flags;
8810 if (action_flags & MLX5_FLOW_ACTION_RSS)
8811 flow_dv_hashfields_set(dev_flow, rss_desc);
8812 /* Register matcher. */
8813 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8815 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8817 /* reserved field no needs to be set to 0 here. */
8818 tbl_key.domain = attr->transfer;
8819 tbl_key.direction = attr->egress;
8820 tbl_key.table_id = dev_flow->dv.group;
8821 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8827 * Apply the flow to the NIC, lock free,
8828 * (mutex should be acquired by caller).
8831 * Pointer to the Ethernet device structure.
8832 * @param[in, out] flow
8833 * Pointer to flow structure.
8835 * Pointer to error structure.
8838 * 0 on success, a negative errno value otherwise and rte_errno is set.
8841 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8842 struct rte_flow_error *error)
8844 struct mlx5_flow_dv_workspace *dv;
8845 struct mlx5_flow_handle *dh;
8846 struct mlx5_flow_handle_dv *dv_h;
8847 struct mlx5_flow *dev_flow;
8848 struct mlx5_priv *priv = dev->data->dev_private;
8849 uint32_t handle_idx;
8854 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8855 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8857 dh = dev_flow->handle;
8860 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8862 dv->actions[n++] = priv->sh->esw_drop_action;
8864 struct mlx5_hrxq *drop_hrxq;
8865 drop_hrxq = mlx5_hrxq_drop_new(dev);
8869 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8871 "cannot get drop hash queue");
8875 * Drop queues will be released by the specify
8876 * mlx5_hrxq_drop_release() function. Assign
8877 * the special index to hrxq to mark the queue
8878 * has been allocated.
8880 dh->rix_hrxq = UINT32_MAX;
8881 dv->actions[n++] = drop_hrxq->action;
8883 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8884 struct mlx5_hrxq *hrxq;
8886 struct mlx5_flow_rss_desc *rss_desc =
8887 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8888 [!!priv->flow_nested_idx];
8890 MLX5_ASSERT(rss_desc->queue_num);
8891 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8892 MLX5_RSS_HASH_KEY_LEN,
8893 dev_flow->hash_fields,
8895 rss_desc->queue_num);
8897 hrxq_idx = mlx5_hrxq_new
8898 (dev, rss_desc->key,
8899 MLX5_RSS_HASH_KEY_LEN,
8900 dev_flow->hash_fields,
8902 rss_desc->queue_num,
8904 MLX5_FLOW_LAYER_TUNNEL));
8906 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8912 "cannot get hash queue");
8915 dh->rix_hrxq = hrxq_idx;
8916 dv->actions[n++] = hrxq->action;
8917 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8918 if (flow_dv_default_miss_resource_register
8922 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8923 "cannot create default miss resource");
8924 goto error_default_miss;
8926 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8927 dv->actions[n++] = priv->sh->default_miss.action;
8929 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8930 (void *)&dv->value, n,
8931 dv->actions, &dh->drv_flow);
8933 rte_flow_error_set(error, errno,
8934 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8936 "hardware refuses to create flow");
8939 if (priv->vmwa_context &&
8940 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8942 * The rule contains the VLAN pattern.
8943 * For VF we are going to create VLAN
8944 * interface to make hypervisor set correct
8945 * e-Switch vport context.
8947 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8952 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8953 flow_dv_default_miss_resource_release(dev);
8955 err = rte_errno; /* Save rte_errno before cleanup. */
8956 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8957 handle_idx, dh, next) {
8958 /* hrxq is union, don't clear it if the flag is not set. */
8960 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8961 mlx5_hrxq_drop_release(dev);
8963 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8964 mlx5_hrxq_release(dev, dh->rix_hrxq);
8968 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8969 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8971 rte_errno = err; /* Restore rte_errno. */
8976 * Release the flow matcher.
8979 * Pointer to Ethernet device.
8981 * Pointer to mlx5_flow_handle.
8984 * 1 while a reference on it exists, 0 when freed.
8987 flow_dv_matcher_release(struct rte_eth_dev *dev,
8988 struct mlx5_flow_handle *handle)
8990 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8992 MLX5_ASSERT(matcher->matcher_object);
8993 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8994 dev->data->port_id, (void *)matcher,
8995 rte_atomic32_read(&matcher->refcnt));
8996 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8997 claim_zero(mlx5_flow_os_destroy_flow_matcher
8998 (matcher->matcher_object));
8999 LIST_REMOVE(matcher, next);
9000 /* table ref-- in release interface. */
9001 flow_dv_tbl_resource_release(dev, matcher->tbl);
9003 DRV_LOG(DEBUG, "port %u matcher %p: removed",
9004 dev->data->port_id, (void *)matcher);
9011 * Release an encap/decap resource.
9014 * Pointer to Ethernet device.
9016 * Pointer to mlx5_flow_handle.
9019 * 1 while a reference on it exists, 0 when freed.
9022 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
9023 struct mlx5_flow_handle *handle)
9025 struct mlx5_priv *priv = dev->data->dev_private;
9026 uint32_t idx = handle->dvh.rix_encap_decap;
9027 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
9029 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9031 if (!cache_resource)
9033 MLX5_ASSERT(cache_resource->action);
9034 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
9035 (void *)cache_resource,
9036 rte_atomic32_read(&cache_resource->refcnt));
9037 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9038 claim_zero(mlx5_flow_os_destroy_flow_action
9039 (cache_resource->action));
9040 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9041 &priv->sh->encaps_decaps, idx,
9042 cache_resource, next);
9043 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
9044 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
9045 (void *)cache_resource);
9052 * Release an jump to table action resource.
9055 * Pointer to Ethernet device.
9057 * Pointer to mlx5_flow_handle.
9060 * 1 while a reference on it exists, 0 when freed.
9063 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
9064 struct mlx5_flow_handle *handle)
9066 struct mlx5_priv *priv = dev->data->dev_private;
9067 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
9068 struct mlx5_flow_tbl_data_entry *tbl_data;
9070 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
9074 cache_resource = &tbl_data->jump;
9075 MLX5_ASSERT(cache_resource->action);
9076 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
9077 (void *)cache_resource,
9078 rte_atomic32_read(&cache_resource->refcnt));
9079 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9080 claim_zero(mlx5_flow_os_destroy_flow_action
9081 (cache_resource->action));
9082 /* jump action memory free is inside the table release. */
9083 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9084 DRV_LOG(DEBUG, "jump table resource %p: removed",
9085 (void *)cache_resource);
9092 * Release a default miss resource.
9095 * Pointer to Ethernet device.
9097 * 1 while a reference on it exists, 0 when freed.
9100 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9102 struct mlx5_priv *priv = dev->data->dev_private;
9103 struct mlx5_dev_ctx_shared *sh = priv->sh;
9104 struct mlx5_flow_default_miss_resource *cache_resource =
9107 MLX5_ASSERT(cache_resource->action);
9108 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9109 (void *)cache_resource->action,
9110 rte_atomic32_read(&cache_resource->refcnt));
9111 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9112 claim_zero(mlx5_glue->destroy_flow_action
9113 (cache_resource->action));
9114 DRV_LOG(DEBUG, "default miss resource %p: removed",
9115 (void *)cache_resource->action);
9122 * Release a modify-header resource.
9125 * Pointer to mlx5_flow_handle.
9128 * 1 while a reference on it exists, 0 when freed.
9131 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9133 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9134 handle->dvh.modify_hdr;
9136 MLX5_ASSERT(cache_resource->action);
9137 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9138 (void *)cache_resource,
9139 rte_atomic32_read(&cache_resource->refcnt));
9140 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9141 claim_zero(mlx5_flow_os_destroy_flow_action
9142 (cache_resource->action));
9143 LIST_REMOVE(cache_resource, next);
9144 mlx5_free(cache_resource);
9145 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9146 (void *)cache_resource);
9153 * Release port ID action resource.
9156 * Pointer to Ethernet device.
9158 * Pointer to mlx5_flow_handle.
9161 * 1 while a reference on it exists, 0 when freed.
9164 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9165 struct mlx5_flow_handle *handle)
9167 struct mlx5_priv *priv = dev->data->dev_private;
9168 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9169 uint32_t idx = handle->rix_port_id_action;
9171 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9173 if (!cache_resource)
9175 MLX5_ASSERT(cache_resource->action);
9176 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9177 (void *)cache_resource,
9178 rte_atomic32_read(&cache_resource->refcnt));
9179 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9180 claim_zero(mlx5_flow_os_destroy_flow_action
9181 (cache_resource->action));
9182 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9183 &priv->sh->port_id_action_list, idx,
9184 cache_resource, next);
9185 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9186 DRV_LOG(DEBUG, "port id action resource %p: removed",
9187 (void *)cache_resource);
9194 * Release push vlan action resource.
9197 * Pointer to Ethernet device.
9199 * Pointer to mlx5_flow_handle.
9202 * 1 while a reference on it exists, 0 when freed.
9205 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9206 struct mlx5_flow_handle *handle)
9208 struct mlx5_priv *priv = dev->data->dev_private;
9209 uint32_t idx = handle->dvh.rix_push_vlan;
9210 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9212 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9214 if (!cache_resource)
9216 MLX5_ASSERT(cache_resource->action);
9217 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9218 (void *)cache_resource,
9219 rte_atomic32_read(&cache_resource->refcnt));
9220 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9221 claim_zero(mlx5_flow_os_destroy_flow_action
9222 (cache_resource->action));
9223 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9224 &priv->sh->push_vlan_action_list, idx,
9225 cache_resource, next);
9226 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9227 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9228 (void *)cache_resource);
9235 * Release the fate resource.
9238 * Pointer to Ethernet device.
9240 * Pointer to mlx5_flow_handle.
9243 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9244 struct mlx5_flow_handle *handle)
9246 if (!handle->rix_fate)
9248 switch (handle->fate_action) {
9249 case MLX5_FLOW_FATE_DROP:
9250 mlx5_hrxq_drop_release(dev);
9252 case MLX5_FLOW_FATE_QUEUE:
9253 mlx5_hrxq_release(dev, handle->rix_hrxq);
9255 case MLX5_FLOW_FATE_JUMP:
9256 flow_dv_jump_tbl_resource_release(dev, handle);
9258 case MLX5_FLOW_FATE_PORT_ID:
9259 flow_dv_port_id_action_resource_release(dev, handle);
9261 case MLX5_FLOW_FATE_DEFAULT_MISS:
9262 flow_dv_default_miss_resource_release(dev);
9265 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9268 handle->rix_fate = 0;
9272 * Remove the flow from the NIC but keeps it in memory.
9273 * Lock free, (mutex should be acquired by caller).
9276 * Pointer to Ethernet device.
9277 * @param[in, out] flow
9278 * Pointer to flow structure.
9281 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9283 struct mlx5_flow_handle *dh;
9284 uint32_t handle_idx;
9285 struct mlx5_priv *priv = dev->data->dev_private;
9289 handle_idx = flow->dev_handles;
9290 while (handle_idx) {
9291 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9296 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9297 dh->drv_flow = NULL;
9299 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9300 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9301 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9302 flow_dv_fate_resource_release(dev, dh);
9303 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9304 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9305 handle_idx = dh->next.next;
9310 * Remove the flow from the NIC and the memory.
9311 * Lock free, (mutex should be acquired by caller).
9314 * Pointer to the Ethernet device structure.
9315 * @param[in, out] flow
9316 * Pointer to flow structure.
9319 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9321 struct mlx5_flow_handle *dev_handle;
9322 struct mlx5_priv *priv = dev->data->dev_private;
9326 __flow_dv_remove(dev, flow);
9327 if (flow->counter) {
9328 flow_dv_counter_release(dev, flow->counter);
9332 struct mlx5_flow_meter *fm;
9334 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9337 mlx5_flow_meter_detach(fm);
9340 while (flow->dev_handles) {
9341 uint32_t tmp_idx = flow->dev_handles;
9343 dev_handle = mlx5_ipool_get(priv->sh->ipool
9344 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9347 flow->dev_handles = dev_handle->next.next;
9348 if (dev_handle->dvh.matcher)
9349 flow_dv_matcher_release(dev, dev_handle);
9350 if (dev_handle->dvh.rix_encap_decap)
9351 flow_dv_encap_decap_resource_release(dev, dev_handle);
9352 if (dev_handle->dvh.modify_hdr)
9353 flow_dv_modify_hdr_resource_release(dev_handle);
9354 if (dev_handle->dvh.rix_push_vlan)
9355 flow_dv_push_vlan_action_resource_release(dev,
9357 if (dev_handle->dvh.rix_tag)
9358 flow_dv_tag_release(dev,
9359 dev_handle->dvh.rix_tag);
9360 flow_dv_fate_resource_release(dev, dev_handle);
9361 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9367 * Query a dv flow rule for its statistics via devx.
9370 * Pointer to Ethernet device.
9372 * Pointer to the sub flow.
9374 * data retrieved by the query.
9376 * Perform verbose error reporting if not NULL.
9379 * 0 on success, a negative errno value otherwise and rte_errno is set.
9382 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9383 void *data, struct rte_flow_error *error)
9385 struct mlx5_priv *priv = dev->data->dev_private;
9386 struct rte_flow_query_count *qc = data;
9388 if (!priv->config.devx)
9389 return rte_flow_error_set(error, ENOTSUP,
9390 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9392 "counters are not supported");
9393 if (flow->counter) {
9394 uint64_t pkts, bytes;
9395 struct mlx5_flow_counter *cnt;
9397 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9399 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9403 return rte_flow_error_set(error, -err,
9404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9405 NULL, "cannot read counters");
9408 qc->hits = pkts - cnt->hits;
9409 qc->bytes = bytes - cnt->bytes;
9416 return rte_flow_error_set(error, EINVAL,
9417 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9419 "counters are not available");
9425 * @see rte_flow_query()
9429 flow_dv_query(struct rte_eth_dev *dev,
9430 struct rte_flow *flow __rte_unused,
9431 const struct rte_flow_action *actions __rte_unused,
9432 void *data __rte_unused,
9433 struct rte_flow_error *error __rte_unused)
9437 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9438 switch (actions->type) {
9439 case RTE_FLOW_ACTION_TYPE_VOID:
9441 case RTE_FLOW_ACTION_TYPE_COUNT:
9442 ret = flow_dv_query_count(dev, flow, data, error);
9445 return rte_flow_error_set(error, ENOTSUP,
9446 RTE_FLOW_ERROR_TYPE_ACTION,
9448 "action not supported");
9455 * Destroy the meter table set.
9456 * Lock free, (mutex should be acquired by caller).
9459 * Pointer to Ethernet device.
9461 * Pointer to the meter table set.
9467 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9468 struct mlx5_meter_domains_infos *tbl)
9470 struct mlx5_priv *priv = dev->data->dev_private;
9471 struct mlx5_meter_domains_infos *mtd =
9472 (struct mlx5_meter_domains_infos *)tbl;
9474 if (!mtd || !priv->config.dv_flow_en)
9476 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9477 claim_zero(mlx5_flow_os_destroy_flow
9478 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9479 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9480 claim_zero(mlx5_flow_os_destroy_flow
9481 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9482 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9483 claim_zero(mlx5_flow_os_destroy_flow
9484 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9485 if (mtd->egress.color_matcher)
9486 claim_zero(mlx5_flow_os_destroy_flow_matcher
9487 (mtd->egress.color_matcher));
9488 if (mtd->egress.any_matcher)
9489 claim_zero(mlx5_flow_os_destroy_flow_matcher
9490 (mtd->egress.any_matcher));
9491 if (mtd->egress.tbl)
9492 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9493 if (mtd->egress.sfx_tbl)
9494 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9495 if (mtd->ingress.color_matcher)
9496 claim_zero(mlx5_flow_os_destroy_flow_matcher
9497 (mtd->ingress.color_matcher));
9498 if (mtd->ingress.any_matcher)
9499 claim_zero(mlx5_flow_os_destroy_flow_matcher
9500 (mtd->ingress.any_matcher));
9501 if (mtd->ingress.tbl)
9502 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9503 if (mtd->ingress.sfx_tbl)
9504 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9505 if (mtd->transfer.color_matcher)
9506 claim_zero(mlx5_flow_os_destroy_flow_matcher
9507 (mtd->transfer.color_matcher));
9508 if (mtd->transfer.any_matcher)
9509 claim_zero(mlx5_flow_os_destroy_flow_matcher
9510 (mtd->transfer.any_matcher));
9511 if (mtd->transfer.tbl)
9512 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9513 if (mtd->transfer.sfx_tbl)
9514 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9516 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9521 /* Number of meter flow actions, count and jump or count and drop. */
9522 #define METER_ACTIONS 2
9525 * Create specify domain meter table and suffix table.
9528 * Pointer to Ethernet device.
9529 * @param[in,out] mtb
9530 * Pointer to DV meter table set.
9533 * @param[in] transfer
9535 * @param[in] color_reg_c_idx
9536 * Reg C index for color match.
9539 * 0 on success, -1 otherwise and rte_errno is set.
9542 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9543 struct mlx5_meter_domains_infos *mtb,
9544 uint8_t egress, uint8_t transfer,
9545 uint32_t color_reg_c_idx)
9547 struct mlx5_priv *priv = dev->data->dev_private;
9548 struct mlx5_dev_ctx_shared *sh = priv->sh;
9549 struct mlx5_flow_dv_match_params mask = {
9550 .size = sizeof(mask.buf),
9552 struct mlx5_flow_dv_match_params value = {
9553 .size = sizeof(value.buf),
9555 struct mlx5dv_flow_matcher_attr dv_attr = {
9556 .type = IBV_FLOW_ATTR_NORMAL,
9558 .match_criteria_enable = 0,
9559 .match_mask = (void *)&mask,
9561 void *actions[METER_ACTIONS];
9562 struct mlx5_meter_domain_info *dtb;
9563 struct rte_flow_error error;
9568 dtb = &mtb->transfer;
9572 dtb = &mtb->ingress;
9573 /* Create the meter table with METER level. */
9574 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9575 egress, transfer, &error);
9577 DRV_LOG(ERR, "Failed to create meter policer table.");
9580 /* Create the meter suffix table with SUFFIX level. */
9581 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9582 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9583 egress, transfer, &error);
9584 if (!dtb->sfx_tbl) {
9585 DRV_LOG(ERR, "Failed to create meter suffix table.");
9588 /* Create matchers, Any and Color. */
9589 dv_attr.priority = 3;
9590 dv_attr.match_criteria_enable = 0;
9591 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9594 DRV_LOG(ERR, "Failed to create meter"
9595 " policer default matcher.");
9598 dv_attr.priority = 0;
9599 dv_attr.match_criteria_enable =
9600 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9601 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9602 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9603 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9604 &dtb->color_matcher);
9606 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9609 if (mtb->count_actns[RTE_MTR_DROPPED])
9610 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9611 actions[i++] = mtb->drop_actn;
9612 /* Default rule: lowest priority, match any, actions: drop. */
9613 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9615 &dtb->policer_rules[RTE_MTR_DROPPED]);
9617 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9626 * Create the needed meter and suffix tables.
9627 * Lock free, (mutex should be acquired by caller).
9630 * Pointer to Ethernet device.
9632 * Pointer to the flow meter.
9635 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9637 static struct mlx5_meter_domains_infos *
9638 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9639 const struct mlx5_flow_meter *fm)
9641 struct mlx5_priv *priv = dev->data->dev_private;
9642 struct mlx5_meter_domains_infos *mtb;
9646 if (!priv->mtr_en) {
9647 rte_errno = ENOTSUP;
9650 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9652 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9655 /* Create meter count actions */
9656 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9657 struct mlx5_flow_counter *cnt;
9658 if (!fm->policer_stats.cnt[i])
9660 cnt = flow_dv_counter_get_by_idx(dev,
9661 fm->policer_stats.cnt[i], NULL);
9662 mtb->count_actns[i] = cnt->action;
9664 /* Create drop action. */
9665 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9667 DRV_LOG(ERR, "Failed to create drop action.");
9670 /* Egress meter table. */
9671 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9673 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9676 /* Ingress meter table. */
9677 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9679 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9682 /* FDB meter table. */
9683 if (priv->config.dv_esw_en) {
9684 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9685 priv->mtr_color_reg);
9687 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9693 flow_dv_destroy_mtr_tbl(dev, mtb);
9698 * Destroy domain policer rule.
9701 * Pointer to domain table.
9704 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9708 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9709 if (dt->policer_rules[i]) {
9710 claim_zero(mlx5_flow_os_destroy_flow
9711 (dt->policer_rules[i]));
9712 dt->policer_rules[i] = NULL;
9715 if (dt->jump_actn) {
9716 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9717 dt->jump_actn = NULL;
9722 * Destroy policer rules.
9725 * Pointer to Ethernet device.
9727 * Pointer to flow meter structure.
9729 * Pointer to flow attributes.
9735 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9736 const struct mlx5_flow_meter *fm,
9737 const struct rte_flow_attr *attr)
9739 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9744 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9746 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9748 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9753 * Create specify domain meter policer rule.
9756 * Pointer to flow meter structure.
9758 * Pointer to DV meter table set.
9759 * @param[in] mtr_reg_c
9760 * Color match REG_C.
9763 * 0 on success, -1 otherwise.
9766 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9767 struct mlx5_meter_domain_info *dtb,
9770 struct mlx5_flow_dv_match_params matcher = {
9771 .size = sizeof(matcher.buf),
9773 struct mlx5_flow_dv_match_params value = {
9774 .size = sizeof(value.buf),
9776 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9777 void *actions[METER_ACTIONS];
9781 /* Create jump action. */
9782 if (!dtb->jump_actn)
9783 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9784 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9786 DRV_LOG(ERR, "Failed to create policer jump action.");
9789 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9792 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9793 rte_col_2_mlx5_col(i), UINT8_MAX);
9794 if (mtb->count_actns[i])
9795 actions[j++] = mtb->count_actns[i];
9796 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9797 actions[j++] = mtb->drop_actn;
9799 actions[j++] = dtb->jump_actn;
9800 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9801 (void *)&value, j, actions,
9802 &dtb->policer_rules[i]);
9804 DRV_LOG(ERR, "Failed to create policer rule.");
9815 * Create policer rules.
9818 * Pointer to Ethernet device.
9820 * Pointer to flow meter structure.
9822 * Pointer to flow attributes.
9825 * 0 on success, -1 otherwise.
9828 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9829 struct mlx5_flow_meter *fm,
9830 const struct rte_flow_attr *attr)
9832 struct mlx5_priv *priv = dev->data->dev_private;
9833 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9837 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9838 priv->mtr_color_reg);
9840 DRV_LOG(ERR, "Failed to create egress policer.");
9844 if (attr->ingress) {
9845 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9846 priv->mtr_color_reg);
9848 DRV_LOG(ERR, "Failed to create ingress policer.");
9852 if (attr->transfer) {
9853 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9854 priv->mtr_color_reg);
9856 DRV_LOG(ERR, "Failed to create transfer policer.");
9862 flow_dv_destroy_policer_rules(dev, fm, attr);
9867 * Query a devx counter.
9870 * Pointer to the Ethernet device structure.
9872 * Index to the flow counter.
9874 * Set to clear the counter statistics.
9876 * The statistics value of packets.
9878 * The statistics value of bytes.
9881 * 0 on success, otherwise return -1.
9884 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9885 uint64_t *pkts, uint64_t *bytes)
9887 struct mlx5_priv *priv = dev->data->dev_private;
9888 struct mlx5_flow_counter *cnt;
9889 uint64_t inn_pkts, inn_bytes;
9892 if (!priv->config.devx)
9895 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9898 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9899 *pkts = inn_pkts - cnt->hits;
9900 *bytes = inn_bytes - cnt->bytes;
9902 cnt->hits = inn_pkts;
9903 cnt->bytes = inn_bytes;
9909 * Get aged-out flows.
9912 * Pointer to the Ethernet device structure.
9913 * @param[in] context
9914 * The address of an array of pointers to the aged-out flows contexts.
9915 * @param[in] nb_contexts
9916 * The length of context array pointers.
9918 * Perform verbose error reporting if not NULL. Initialized in case of
9922 * how many contexts get in success, otherwise negative errno value.
9923 * if nb_contexts is 0, return the amount of all aged contexts.
9924 * if nb_contexts is not 0 , return the amount of aged flows reported
9925 * in the context array.
9926 * @note: only stub for now
9929 flow_get_aged_flows(struct rte_eth_dev *dev,
9931 uint32_t nb_contexts,
9932 struct rte_flow_error *error)
9934 struct mlx5_priv *priv = dev->data->dev_private;
9935 struct mlx5_age_info *age_info;
9936 struct mlx5_age_param *age_param;
9937 struct mlx5_flow_counter *counter;
9940 if (nb_contexts && !context)
9941 return rte_flow_error_set(error, EINVAL,
9942 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9944 "Should assign at least one flow or"
9945 " context to get if nb_contexts != 0");
9946 age_info = GET_PORT_AGE_INFO(priv);
9947 rte_spinlock_lock(&age_info->aged_sl);
9948 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9951 age_param = MLX5_CNT_TO_AGE(counter);
9952 context[nb_flows - 1] = age_param->context;
9953 if (!(--nb_contexts))
9957 rte_spinlock_unlock(&age_info->aged_sl);
9958 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9963 * Mutex-protected thunk to lock-free __flow_dv_translate().
9966 flow_dv_translate(struct rte_eth_dev *dev,
9967 struct mlx5_flow *dev_flow,
9968 const struct rte_flow_attr *attr,
9969 const struct rte_flow_item items[],
9970 const struct rte_flow_action actions[],
9971 struct rte_flow_error *error)
9975 flow_dv_shared_lock(dev);
9976 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9977 flow_dv_shared_unlock(dev);
9982 * Mutex-protected thunk to lock-free __flow_dv_apply().
9985 flow_dv_apply(struct rte_eth_dev *dev,
9986 struct rte_flow *flow,
9987 struct rte_flow_error *error)
9991 flow_dv_shared_lock(dev);
9992 ret = __flow_dv_apply(dev, flow, error);
9993 flow_dv_shared_unlock(dev);
9998 * Mutex-protected thunk to lock-free __flow_dv_remove().
10001 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10003 flow_dv_shared_lock(dev);
10004 __flow_dv_remove(dev, flow);
10005 flow_dv_shared_unlock(dev);
10009 * Mutex-protected thunk to lock-free __flow_dv_destroy().
10012 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10014 flow_dv_shared_lock(dev);
10015 __flow_dv_destroy(dev, flow);
10016 flow_dv_shared_unlock(dev);
10020 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
10023 flow_dv_counter_allocate(struct rte_eth_dev *dev)
10027 flow_dv_shared_lock(dev);
10028 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
10029 flow_dv_shared_unlock(dev);
10034 * Mutex-protected thunk to lock-free flow_dv_counter_release().
10037 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
10039 flow_dv_shared_lock(dev);
10040 flow_dv_counter_release(dev, cnt);
10041 flow_dv_shared_unlock(dev);
10044 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
10045 .validate = flow_dv_validate,
10046 .prepare = flow_dv_prepare,
10047 .translate = flow_dv_translate,
10048 .apply = flow_dv_apply,
10049 .remove = flow_dv_remove,
10050 .destroy = flow_dv_destroy,
10051 .query = flow_dv_query,
10052 .create_mtr_tbls = flow_dv_create_mtr_tbl,
10053 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
10054 .create_policer_rules = flow_dv_create_policer_rules,
10055 .destroy_policer_rules = flow_dv_destroy_policer_rules,
10056 .counter_alloc = flow_dv_counter_allocate,
10057 .counter_free = flow_dv_counter_free,
10058 .counter_query = flow_dv_counter_query,
10059 .get_aged_flows = flow_get_aged_flows,
10062 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */