drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36
  37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  38
  39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  41 #endif
  42
  43 #ifndef HAVE_MLX5DV_DR_ESWITCH
  44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  46 #endif
  47 #endif
  48
  49 #ifndef HAVE_MLX5DV_DR
  50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  51 #endif
  52
  53 /* VLAN header definitions */
  54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  59
  60 union flow_dv_attr {
  61         struct {
  62                 uint32_t valid:1;
  63                 uint32_t ipv4:1;
  64                 uint32_t ipv6:1;
  65                 uint32_t tcp:1;
  66                 uint32_t udp:1;
  67                 uint32_t reserved:27;
  68         };
  69         uint32_t attr;
  70 };
  71
  72 static int
  73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  74                              struct mlx5_flow_tbl_resource *tbl);
  75
  76 static int
  77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
  78
  79 /**
  80  * Initialize flow attributes structure according to flow items' types.
  81  *
  82  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  83  * mode. For tunnel mode, the items to be modified are the outermost ones.
  84  *
  85  * @param[in] item
  86  *   Pointer to item specification.
  87  * @param[out] attr
  88  *   Pointer to flow attributes structure.
  89  * @param[in] dev_flow
  90  *   Pointer to the sub flow.
  91  * @param[in] tunnel_decap
  92  *   Whether action is after tunnel decapsulation.
  93  */
  94 static void
  95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  96                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  97 {
  98         uint64_t layers = dev_flow->handle->layers;
  99
 100         /*
 101          * If layers is already initialized, it means this dev_flow is the
 102          * suffix flow, the layers flags is set by the prefix flow. Need to
 103          * use the layer flags from prefix flow as the suffix flow may not
 104          * have the user defined items as the flow is split.
 105          */
 106         if (layers) {
 107                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 108                         attr->ipv4 = 1;
 109                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 110                         attr->ipv6 = 1;
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 112                         attr->tcp = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 114                         attr->udp = 1;
 115                 attr->valid = 1;
 116                 return;
 117         }
 118         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 119                 uint8_t next_protocol = 0xff;
 120                 switch (item->type) {
 121                 case RTE_FLOW_ITEM_TYPE_GRE:
 122                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 123                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 125                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 126                 case RTE_FLOW_ITEM_TYPE_MPLS:
 127                         if (tunnel_decap)
 128                                 attr->attr = 0;
 129                         break;
 130                 case RTE_FLOW_ITEM_TYPE_IPV4:
 131                         if (!attr->ipv6)
 132                                 attr->ipv4 = 1;
 133                         if (item->mask != NULL &&
 134                             ((const struct rte_flow_item_ipv4 *)
 135                             item->mask)->hdr.next_proto_id)
 136                                 next_protocol =
 137                                     ((const struct rte_flow_item_ipv4 *)
 138                                       (item->spec))->hdr.next_proto_id &
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->mask))->hdr.next_proto_id;
 141                         if ((next_protocol == IPPROTO_IPIP ||
 142                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 143                                 attr->attr = 0;
 144                         break;
 145                 case RTE_FLOW_ITEM_TYPE_IPV6:
 146                         if (!attr->ipv4)
 147                                 attr->ipv6 = 1;
 148                         if (item->mask != NULL &&
 149                             ((const struct rte_flow_item_ipv6 *)
 150                             item->mask)->hdr.proto)
 151                                 next_protocol =
 152                                     ((const struct rte_flow_item_ipv6 *)
 153                                       (item->spec))->hdr.proto &
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->mask))->hdr.proto;
 156                         if ((next_protocol == IPPROTO_IPIP ||
 157                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 158                                 attr->attr = 0;
 159                         break;
 160                 case RTE_FLOW_ITEM_TYPE_UDP:
 161                         if (!attr->tcp)
 162                                 attr->udp = 1;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_TCP:
 165                         if (!attr->udp)
 166                                 attr->tcp = 1;
 167                         break;
 168                 default:
 169                         break;
 170                 }
 171         }
 172         attr->valid = 1;
 173 }
 174
 175 /**
 176  * Convert rte_mtr_color to mlx5 color.
 177  *
 178  * @param[in] rcol
 179  *   rte_mtr_color.
 180  *
 181  * @return
 182  *   mlx5 color.
 183  */
 184 static int
 185 rte_col_2_mlx5_col(enum rte_color rcol)
 186 {
 187         switch (rcol) {
 188         case RTE_COLOR_GREEN:
 189                 return MLX5_FLOW_COLOR_GREEN;
 190         case RTE_COLOR_YELLOW:
 191                 return MLX5_FLOW_COLOR_YELLOW;
 192         case RTE_COLOR_RED:
 193                 return MLX5_FLOW_COLOR_RED;
 194         default:
 195                 break;
 196         }
 197         return MLX5_FLOW_COLOR_UNDEFINED;
 198 }
 199
 200 struct field_modify_info {
 201         uint32_t size; /* Size of field in protocol header, in bytes. */
 202         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 203         enum mlx5_modification_field id;
 204 };
 205
 206 struct field_modify_info modify_eth[] = {
 207         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 208         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 209         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 210         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 211         {0, 0, 0},
 212 };
 213
 214 struct field_modify_info modify_vlan_out_first_vid[] = {
 215         /* Size in bits !!! */
 216         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_ipv4[] = {
 221         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 222         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 223         {4, 12, MLX5_MODI_OUT_SIPV4},
 224         {4, 16, MLX5_MODI_OUT_DIPV4},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv6[] = {
 229         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 231         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 232         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 233         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 234         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 235         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 236         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 237         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 238         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 239         {0, 0, 0},
 240 };
 241
 242 struct field_modify_info modify_udp[] = {
 243         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 244         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_tcp[] = {
 249         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 251         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 252         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 253         {0, 0, 0},
 254 };
 255
 256 static void
 257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 258                           uint8_t next_protocol, uint64_t *item_flags,
 259                           int *tunnel)
 260 {
 261         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 262                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 263         if (next_protocol == IPPROTO_IPIP) {
 264                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 265                 *tunnel = 1;
 266         }
 267         if (next_protocol == IPPROTO_IPV6) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 269                 *tunnel = 1;
 270         }
 271 }
 272
 273 /**
 274  * Acquire the synchronizing object to protect multithreaded access
 275  * to shared dv context. Lock occurs only if context is actually
 276  * shared, i.e. we have multiport IB device and representors are
 277  * created.
 278  *
 279  * @param[in] dev
 280  *   Pointer to the rte_eth_dev structure.
 281  */
 282 static void
 283 flow_dv_shared_lock(struct rte_eth_dev *dev)
 284 {
 285         struct mlx5_priv *priv = dev->data->dev_private;
 286         struct mlx5_dev_ctx_shared *sh = priv->sh;
 287
 288         if (sh->dv_refcnt > 1) {
 289                 int ret;
 290
 291                 ret = pthread_mutex_lock(&sh->dv_mutex);
 292                 MLX5_ASSERT(!ret);
 293                 (void)ret;
 294         }
 295 }
 296
 297 static void
 298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 299 {
 300         struct mlx5_priv *priv = dev->data->dev_private;
 301         struct mlx5_dev_ctx_shared *sh = priv->sh;
 302
 303         if (sh->dv_refcnt > 1) {
 304                 int ret;
 305
 306                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 307                 MLX5_ASSERT(!ret);
 308                 (void)ret;
 309         }
 310 }
 311
 312 /* Update VLAN's VID/PCP based on input rte_flow_action.
 313  *
 314  * @param[in] action
 315  *   Pointer to struct rte_flow_action.
 316  * @param[out] vlan
 317  *   Pointer to struct rte_vlan_hdr.
 318  */
 319 static void
 320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 321                          struct rte_vlan_hdr *vlan)
 322 {
 323         uint16_t vlan_tci;
 324         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 325                 vlan_tci =
 326                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 327                                                action->conf)->vlan_pcp;
 328                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 329                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 330                 vlan->vlan_tci |= vlan_tci;
 331         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 332                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 333                 vlan->vlan_tci |= rte_be_to_cpu_16
 334                     (((const struct rte_flow_action_of_set_vlan_vid *)
 335                                              action->conf)->vlan_vid);
 336         }
 337 }
 338
 339 /**
 340  * Fetch 1, 2, 3 or 4 byte field from the byte array
 341  * and return as unsigned integer in host-endian format.
 342  *
 343  * @param[in] data
 344  *   Pointer to data array.
 345  * @param[in] size
 346  *   Size of field to extract.
 347  *
 348  * @return
 349  *   converted field in host endian format.
 350  */
 351 static inline uint32_t
 352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 353 {
 354         uint32_t ret;
 355
 356         switch (size) {
 357         case 1:
 358                 ret = *data;
 359                 break;
 360         case 2:
 361                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 362                 break;
 363         case 3:
 364                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 365                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 366                 break;
 367         case 4:
 368                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 369                 break;
 370         default:
 371                 MLX5_ASSERT(false);
 372                 ret = 0;
 373                 break;
 374         }
 375         return ret;
 376 }
 377
 378 /**
 379  * Convert modify-header action to DV specification.
 380  *
 381  * Data length of each action is determined by provided field description
 382  * and the item mask. Data bit offset and width of each action is determined
 383  * by provided item mask.
 384  *
 385  * @param[in] item
 386  *   Pointer to item specification.
 387  * @param[in] field
 388  *   Pointer to field modification information.
 389  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 390  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 392  * @param[in] dcopy
 393  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 394  *   Negative offset value sets the same offset as source offset.
 395  *   size field is ignored, value is taken from source field.
 396  * @param[in,out] resource
 397  *   Pointer to the modify-header resource.
 398  * @param[in] type
 399  *   Type of modification.
 400  * @param[out] error
 401  *   Pointer to the error structure.
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 static int
 407 flow_dv_convert_modify_action(struct rte_flow_item *item,
 408                               struct field_modify_info *field,
 409                               struct field_modify_info *dcopy,
 410                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 411                               uint32_t type, struct rte_flow_error *error)
 412 {
 413         uint32_t i = resource->actions_num;
 414         struct mlx5_modification_cmd *actions = resource->actions;
 415
 416         /*
 417          * The item and mask are provided in big-endian format.
 418          * The fields should be presented as in big-endian format either.
 419          * Mask must be always present, it defines the actual field width.
 420          */
 421         MLX5_ASSERT(item->mask);
 422         MLX5_ASSERT(field->size);
 423         do {
 424                 unsigned int size_b;
 425                 unsigned int off_b;
 426                 uint32_t mask;
 427                 uint32_t data;
 428
 429                 if (i >= MLX5_MAX_MODIFY_NUM)
 430                         return rte_flow_error_set(error, EINVAL,
 431                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 432                                  "too many items to modify");
 433                 /* Fetch variable byte size mask from the array. */
 434                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 435                                            field->offset, field->size);
 436                 if (!mask) {
 437                         ++field;
 438                         continue;
 439                 }
 440                 /* Deduce actual data width in bits from mask value. */
 441                 off_b = rte_bsf32(mask);
 442                 size_b = sizeof(uint32_t) * CHAR_BIT -
 443                          off_b - __builtin_clz(mask);
 444                 MLX5_ASSERT(size_b);
 445                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 446                 actions[i] = (struct mlx5_modification_cmd) {
 447                         .action_type = type,
 448                         .field = field->id,
 449                         .offset = off_b,
 450                         .length = size_b,
 451                 };
 452                 /* Convert entire record to expected big-endian format. */
 453                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 454                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 455                         MLX5_ASSERT(dcopy);
 456                         actions[i].dst_field = dcopy->id;
 457                         actions[i].dst_offset =
 458                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 459                         /* Convert entire record to big-endian format. */
 460                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 461                 } else {
 462                         MLX5_ASSERT(item->spec);
 463                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 464                                                    field->offset, field->size);
 465                         /* Shift out the trailing masked bits from data. */
 466                         data = (data & mask) >> off_b;
 467                         actions[i].data1 = rte_cpu_to_be_32(data);
 468                 }
 469                 ++i;
 470                 ++field;
 471         } while (field->size);
 472         if (resource->actions_num == i)
 473                 return rte_flow_error_set(error, EINVAL,
 474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 475                                           "invalid modification flow item");
 476         resource->actions_num = i;
 477         return 0;
 478 }
 479
 480 /**
 481  * Convert modify-header set IPv4 address action to DV specification.
 482  *
 483  * @param[in,out] resource
 484  *   Pointer to the modify-header resource.
 485  * @param[in] action
 486  *   Pointer to action specification.
 487  * @param[out] error
 488  *   Pointer to the error structure.
 489  *
 490  * @return
 491  *   0 on success, a negative errno value otherwise and rte_errno is set.
 492  */
 493 static int
 494 flow_dv_convert_action_modify_ipv4
 495                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 496                          const struct rte_flow_action *action,
 497                          struct rte_flow_error *error)
 498 {
 499         const struct rte_flow_action_set_ipv4 *conf =
 500                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 501         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 502         struct rte_flow_item_ipv4 ipv4;
 503         struct rte_flow_item_ipv4 ipv4_mask;
 504
 505         memset(&ipv4, 0, sizeof(ipv4));
 506         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 507         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 508                 ipv4.hdr.src_addr = conf->ipv4_addr;
 509                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 510         } else {
 511                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 512                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 513         }
 514         item.spec = &ipv4;
 515         item.mask = &ipv4_mask;
 516         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 517                                              MLX5_MODIFICATION_TYPE_SET, error);
 518 }
 519
 520 /**
 521  * Convert modify-header set IPv6 address action to DV specification.
 522  *
 523  * @param[in,out] resource
 524  *   Pointer to the modify-header resource.
 525  * @param[in] action
 526  *   Pointer to action specification.
 527  * @param[out] error
 528  *   Pointer to the error structure.
 529  *
 530  * @return
 531  *   0 on success, a negative errno value otherwise and rte_errno is set.
 532  */
 533 static int
 534 flow_dv_convert_action_modify_ipv6
 535                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 536                          const struct rte_flow_action *action,
 537                          struct rte_flow_error *error)
 538 {
 539         const struct rte_flow_action_set_ipv6 *conf =
 540                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 541         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 542         struct rte_flow_item_ipv6 ipv6;
 543         struct rte_flow_item_ipv6 ipv6_mask;
 544
 545         memset(&ipv6, 0, sizeof(ipv6));
 546         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 547         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 548                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 549                        sizeof(ipv6.hdr.src_addr));
 550                 memcpy(&ipv6_mask.hdr.src_addr,
 551                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 552                        sizeof(ipv6.hdr.src_addr));
 553         } else {
 554                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.dst_addr));
 556                 memcpy(&ipv6_mask.hdr.dst_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 558                        sizeof(ipv6.hdr.dst_addr));
 559         }
 560         item.spec = &ipv6;
 561         item.mask = &ipv6_mask;
 562         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 563                                              MLX5_MODIFICATION_TYPE_SET, error);
 564 }
 565
 566 /**
 567  * Convert modify-header set MAC address action to DV specification.
 568  *
 569  * @param[in,out] resource
 570  *   Pointer to the modify-header resource.
 571  * @param[in] action
 572  *   Pointer to action specification.
 573  * @param[out] error
 574  *   Pointer to the error structure.
 575  *
 576  * @return
 577  *   0 on success, a negative errno value otherwise and rte_errno is set.
 578  */
 579 static int
 580 flow_dv_convert_action_modify_mac
 581                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 582                          const struct rte_flow_action *action,
 583                          struct rte_flow_error *error)
 584 {
 585         const struct rte_flow_action_set_mac *conf =
 586                 (const struct rte_flow_action_set_mac *)(action->conf);
 587         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 588         struct rte_flow_item_eth eth;
 589         struct rte_flow_item_eth eth_mask;
 590
 591         memset(&eth, 0, sizeof(eth));
 592         memset(&eth_mask, 0, sizeof(eth_mask));
 593         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 594                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 595                        sizeof(eth.src.addr_bytes));
 596                 memcpy(&eth_mask.src.addr_bytes,
 597                        &rte_flow_item_eth_mask.src.addr_bytes,
 598                        sizeof(eth_mask.src.addr_bytes));
 599         } else {
 600                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.dst.addr_bytes));
 602                 memcpy(&eth_mask.dst.addr_bytes,
 603                        &rte_flow_item_eth_mask.dst.addr_bytes,
 604                        sizeof(eth_mask.dst.addr_bytes));
 605         }
 606         item.spec = &eth;
 607         item.mask = &eth_mask;
 608         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 609                                              MLX5_MODIFICATION_TYPE_SET, error);
 610 }
 611
 612 /**
 613  * Convert modify-header set VLAN VID action to DV specification.
 614  *
 615  * @param[in,out] resource
 616  *   Pointer to the modify-header resource.
 617  * @param[in] action
 618  *   Pointer to action specification.
 619  * @param[out] error
 620  *   Pointer to the error structure.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 static int
 626 flow_dv_convert_action_modify_vlan_vid
 627                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 628                          const struct rte_flow_action *action,
 629                          struct rte_flow_error *error)
 630 {
 631         const struct rte_flow_action_of_set_vlan_vid *conf =
 632                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 633         int i = resource->actions_num;
 634         struct mlx5_modification_cmd *actions = resource->actions;
 635         struct field_modify_info *field = modify_vlan_out_first_vid;
 636
 637         if (i >= MLX5_MAX_MODIFY_NUM)
 638                 return rte_flow_error_set(error, EINVAL,
 639                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 640                          "too many items to modify");
 641         actions[i] = (struct mlx5_modification_cmd) {
 642                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 643                 .field = field->id,
 644                 .length = field->size,
 645                 .offset = field->offset,
 646         };
 647         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 648         actions[i].data1 = conf->vlan_vid;
 649         actions[i].data1 = actions[i].data1 << 16;
 650         resource->actions_num = ++i;
 651         return 0;
 652 }
 653
 654 /**
 655  * Convert modify-header set TP action to DV specification.
 656  *
 657  * @param[in,out] resource
 658  *   Pointer to the modify-header resource.
 659  * @param[in] action
 660  *   Pointer to action specification.
 661  * @param[in] items
 662  *   Pointer to rte_flow_item objects list.
 663  * @param[in] attr
 664  *   Pointer to flow attributes structure.
 665  * @param[in] dev_flow
 666  *   Pointer to the sub flow.
 667  * @param[in] tunnel_decap
 668  *   Whether action is after tunnel decapsulation.
 669  * @param[out] error
 670  *   Pointer to the error structure.
 671  *
 672  * @return
 673  *   0 on success, a negative errno value otherwise and rte_errno is set.
 674  */
 675 static int
 676 flow_dv_convert_action_modify_tp
 677                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 678                          const struct rte_flow_action *action,
 679                          const struct rte_flow_item *items,
 680                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 681                          bool tunnel_decap, struct rte_flow_error *error)
 682 {
 683         const struct rte_flow_action_set_tp *conf =
 684                 (const struct rte_flow_action_set_tp *)(action->conf);
 685         struct rte_flow_item item;
 686         struct rte_flow_item_udp udp;
 687         struct rte_flow_item_udp udp_mask;
 688         struct rte_flow_item_tcp tcp;
 689         struct rte_flow_item_tcp tcp_mask;
 690         struct field_modify_info *field;
 691
 692         if (!attr->valid)
 693                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 694         if (attr->udp) {
 695                 memset(&udp, 0, sizeof(udp));
 696                 memset(&udp_mask, 0, sizeof(udp_mask));
 697                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 698                         udp.hdr.src_port = conf->port;
 699                         udp_mask.hdr.src_port =
 700                                         rte_flow_item_udp_mask.hdr.src_port;
 701                 } else {
 702                         udp.hdr.dst_port = conf->port;
 703                         udp_mask.hdr.dst_port =
 704                                         rte_flow_item_udp_mask.hdr.dst_port;
 705                 }
 706                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 707                 item.spec = &udp;
 708                 item.mask = &udp_mask;
 709                 field = modify_udp;
 710         } else {
 711                 MLX5_ASSERT(attr->tcp);
 712                 memset(&tcp, 0, sizeof(tcp));
 713                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 714                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 715                         tcp.hdr.src_port = conf->port;
 716                         tcp_mask.hdr.src_port =
 717                                         rte_flow_item_tcp_mask.hdr.src_port;
 718                 } else {
 719                         tcp.hdr.dst_port = conf->port;
 720                         tcp_mask.hdr.dst_port =
 721                                         rte_flow_item_tcp_mask.hdr.dst_port;
 722                 }
 723                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 724                 item.spec = &tcp;
 725                 item.mask = &tcp_mask;
 726                 field = modify_tcp;
 727         }
 728         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 729                                              MLX5_MODIFICATION_TYPE_SET, error);
 730 }
 731
 732 /**
 733  * Convert modify-header set TTL action to DV specification.
 734  *
 735  * @param[in,out] resource
 736  *   Pointer to the modify-header resource.
 737  * @param[in] action
 738  *   Pointer to action specification.
 739  * @param[in] items
 740  *   Pointer to rte_flow_item objects list.
 741  * @param[in] attr
 742  *   Pointer to flow attributes structure.
 743  * @param[in] dev_flow
 744  *   Pointer to the sub flow.
 745  * @param[in] tunnel_decap
 746  *   Whether action is after tunnel decapsulation.
 747  * @param[out] error
 748  *   Pointer to the error structure.
 749  *
 750  * @return
 751  *   0 on success, a negative errno value otherwise and rte_errno is set.
 752  */
 753 static int
 754 flow_dv_convert_action_modify_ttl
 755                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 756                          const struct rte_flow_action *action,
 757                          const struct rte_flow_item *items,
 758                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 759                          bool tunnel_decap, struct rte_flow_error *error)
 760 {
 761         const struct rte_flow_action_set_ttl *conf =
 762                 (const struct rte_flow_action_set_ttl *)(action->conf);
 763         struct rte_flow_item item;
 764         struct rte_flow_item_ipv4 ipv4;
 765         struct rte_flow_item_ipv4 ipv4_mask;
 766         struct rte_flow_item_ipv6 ipv6;
 767         struct rte_flow_item_ipv6 ipv6_mask;
 768         struct field_modify_info *field;
 769
 770         if (!attr->valid)
 771                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 772         if (attr->ipv4) {
 773                 memset(&ipv4, 0, sizeof(ipv4));
 774                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 775                 ipv4.hdr.time_to_live = conf->ttl_value;
 776                 ipv4_mask.hdr.time_to_live = 0xFF;
 777                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 778                 item.spec = &ipv4;
 779                 item.mask = &ipv4_mask;
 780                 field = modify_ipv4;
 781         } else {
 782                 MLX5_ASSERT(attr->ipv6);
 783                 memset(&ipv6, 0, sizeof(ipv6));
 784                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 785                 ipv6.hdr.hop_limits = conf->ttl_value;
 786                 ipv6_mask.hdr.hop_limits = 0xFF;
 787                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 788                 item.spec = &ipv6;
 789                 item.mask = &ipv6_mask;
 790                 field = modify_ipv6;
 791         }
 792         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 793                                              MLX5_MODIFICATION_TYPE_SET, error);
 794 }
 795
 796 /**
 797  * Convert modify-header decrement TTL action to DV specification.
 798  *
 799  * @param[in,out] resource
 800  *   Pointer to the modify-header resource.
 801  * @param[in] action
 802  *   Pointer to action specification.
 803  * @param[in] items
 804  *   Pointer to rte_flow_item objects list.
 805  * @param[in] attr
 806  *   Pointer to flow attributes structure.
 807  * @param[in] dev_flow
 808  *   Pointer to the sub flow.
 809  * @param[in] tunnel_decap
 810  *   Whether action is after tunnel decapsulation.
 811  * @param[out] error
 812  *   Pointer to the error structure.
 813  *
 814  * @return
 815  *   0 on success, a negative errno value otherwise and rte_errno is set.
 816  */
 817 static int
 818 flow_dv_convert_action_modify_dec_ttl
 819                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 820                          const struct rte_flow_item *items,
 821                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 822                          bool tunnel_decap, struct rte_flow_error *error)
 823 {
 824         struct rte_flow_item item;
 825         struct rte_flow_item_ipv4 ipv4;
 826         struct rte_flow_item_ipv4 ipv4_mask;
 827         struct rte_flow_item_ipv6 ipv6;
 828         struct rte_flow_item_ipv6 ipv6_mask;
 829         struct field_modify_info *field;
 830
 831         if (!attr->valid)
 832                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 833         if (attr->ipv4) {
 834                 memset(&ipv4, 0, sizeof(ipv4));
 835                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 836                 ipv4.hdr.time_to_live = 0xFF;
 837                 ipv4_mask.hdr.time_to_live = 0xFF;
 838                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 839                 item.spec = &ipv4;
 840                 item.mask = &ipv4_mask;
 841                 field = modify_ipv4;
 842         } else {
 843                 MLX5_ASSERT(attr->ipv6);
 844                 memset(&ipv6, 0, sizeof(ipv6));
 845                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 846                 ipv6.hdr.hop_limits = 0xFF;
 847                 ipv6_mask.hdr.hop_limits = 0xFF;
 848                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 849                 item.spec = &ipv6;
 850                 item.mask = &ipv6_mask;
 851                 field = modify_ipv6;
 852         }
 853         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 854                                              MLX5_MODIFICATION_TYPE_ADD, error);
 855 }
 856
 857 /**
 858  * Convert modify-header increment/decrement TCP Sequence number
 859  * to DV specification.
 860  *
 861  * @param[in,out] resource
 862  *   Pointer to the modify-header resource.
 863  * @param[in] action
 864  *   Pointer to action specification.
 865  * @param[out] error
 866  *   Pointer to the error structure.
 867  *
 868  * @return
 869  *   0 on success, a negative errno value otherwise and rte_errno is set.
 870  */
 871 static int
 872 flow_dv_convert_action_modify_tcp_seq
 873                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 874                          const struct rte_flow_action *action,
 875                          struct rte_flow_error *error)
 876 {
 877         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 878         uint64_t value = rte_be_to_cpu_32(*conf);
 879         struct rte_flow_item item;
 880         struct rte_flow_item_tcp tcp;
 881         struct rte_flow_item_tcp tcp_mask;
 882
 883         memset(&tcp, 0, sizeof(tcp));
 884         memset(&tcp_mask, 0, sizeof(tcp_mask));
 885         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 886                 /*
 887                  * The HW has no decrement operation, only increment operation.
 888                  * To simulate decrement X from Y using increment operation
 889                  * we need to add UINT32_MAX X times to Y.
 890                  * Each adding of UINT32_MAX decrements Y by 1.
 891                  */
 892                 value *= UINT32_MAX;
 893         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 894         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 895         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 896         item.spec = &tcp;
 897         item.mask = &tcp_mask;
 898         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 899                                              MLX5_MODIFICATION_TYPE_ADD, error);
 900 }
 901
 902 /**
 903  * Convert modify-header increment/decrement TCP Acknowledgment number
 904  * to DV specification.
 905  *
 906  * @param[in,out] resource
 907  *   Pointer to the modify-header resource.
 908  * @param[in] action
 909  *   Pointer to action specification.
 910  * @param[out] error
 911  *   Pointer to the error structure.
 912  *
 913  * @return
 914  *   0 on success, a negative errno value otherwise and rte_errno is set.
 915  */
 916 static int
 917 flow_dv_convert_action_modify_tcp_ack
 918                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 919                          const struct rte_flow_action *action,
 920                          struct rte_flow_error *error)
 921 {
 922         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 923         uint64_t value = rte_be_to_cpu_32(*conf);
 924         struct rte_flow_item item;
 925         struct rte_flow_item_tcp tcp;
 926         struct rte_flow_item_tcp tcp_mask;
 927
 928         memset(&tcp, 0, sizeof(tcp));
 929         memset(&tcp_mask, 0, sizeof(tcp_mask));
 930         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 931                 /*
 932                  * The HW has no decrement operation, only increment operation.
 933                  * To simulate decrement X from Y using increment operation
 934                  * we need to add UINT32_MAX X times to Y.
 935                  * Each adding of UINT32_MAX decrements Y by 1.
 936                  */
 937                 value *= UINT32_MAX;
 938         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 939         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 940         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 941         item.spec = &tcp;
 942         item.mask = &tcp_mask;
 943         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 944                                              MLX5_MODIFICATION_TYPE_ADD, error);
 945 }
 946
 947 static enum mlx5_modification_field reg_to_field[] = {
 948         [REG_NONE] = MLX5_MODI_OUT_NONE,
 949         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 950         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 951         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 952         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 953         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 954         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 955         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 956         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 957         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 958         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 959 };
 960
 961 /**
 962  * Convert register set to DV specification.
 963  *
 964  * @param[in,out] resource
 965  *   Pointer to the modify-header resource.
 966  * @param[in] action
 967  *   Pointer to action specification.
 968  * @param[out] error
 969  *   Pointer to the error structure.
 970  *
 971  * @return
 972  *   0 on success, a negative errno value otherwise and rte_errno is set.
 973  */
 974 static int
 975 flow_dv_convert_action_set_reg
 976                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 977                          const struct rte_flow_action *action,
 978                          struct rte_flow_error *error)
 979 {
 980         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 981         struct mlx5_modification_cmd *actions = resource->actions;
 982         uint32_t i = resource->actions_num;
 983
 984         if (i >= MLX5_MAX_MODIFY_NUM)
 985                 return rte_flow_error_set(error, EINVAL,
 986                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 987                                           "too many items to modify");
 988         MLX5_ASSERT(conf->id != REG_NONE);
 989         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 990         actions[i] = (struct mlx5_modification_cmd) {
 991                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 992                 .field = reg_to_field[conf->id],
 993         };
 994         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 995         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 996         ++i;
 997         resource->actions_num = i;
 998         return 0;
 999 }
1000
1001 /**
1002  * Convert SET_TAG action to DV specification.
1003  *
1004  * @param[in] dev
1005  *   Pointer to the rte_eth_dev structure.
1006  * @param[in,out] resource
1007  *   Pointer to the modify-header resource.
1008  * @param[in] conf
1009  *   Pointer to action specification.
1010  * @param[out] error
1011  *   Pointer to the error structure.
1012  *
1013  * @return
1014  *   0 on success, a negative errno value otherwise and rte_errno is set.
1015  */
1016 static int
1017 flow_dv_convert_action_set_tag
1018                         (struct rte_eth_dev *dev,
1019                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1020                          const struct rte_flow_action_set_tag *conf,
1021                          struct rte_flow_error *error)
1022 {
1023         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025         struct rte_flow_item item = {
1026                 .spec = &data,
1027                 .mask = &mask,
1028         };
1029         struct field_modify_info reg_c_x[] = {
1030                 [1] = {0, 0, 0},
1031         };
1032         enum mlx5_modification_field reg_type;
1033         int ret;
1034
1035         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1036         if (ret < 0)
1037                 return ret;
1038         MLX5_ASSERT(ret != REG_NONE);
1039         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040         reg_type = reg_to_field[ret];
1041         MLX5_ASSERT(reg_type > 0);
1042         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044                                              MLX5_MODIFICATION_TYPE_SET, error);
1045 }
1046
1047 /**
1048  * Convert internal COPY_REG action to DV specification.
1049  *
1050  * @param[in] dev
1051  *   Pointer to the rte_eth_dev structure.
1052  * @param[in,out] res
1053  *   Pointer to the modify-header resource.
1054  * @param[in] action
1055  *   Pointer to action specification.
1056  * @param[out] error
1057  *   Pointer to the error structure.
1058  *
1059  * @return
1060  *   0 on success, a negative errno value otherwise and rte_errno is set.
1061  */
1062 static int
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1065                                  const struct rte_flow_action *action,
1066                                  struct rte_flow_error *error)
1067 {
1068         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070         struct rte_flow_item item = {
1071                 .spec = NULL,
1072                 .mask = &mask,
1073         };
1074         struct field_modify_info reg_src[] = {
1075                 {4, 0, reg_to_field[conf->src]},
1076                 {0, 0, 0},
1077         };
1078         struct field_modify_info reg_dst = {
1079                 .offset = 0,
1080                 .id = reg_to_field[conf->dst],
1081         };
1082         /* Adjust reg_c[0] usage according to reported mask. */
1083         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084                 struct mlx5_priv *priv = dev->data->dev_private;
1085                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1086
1087                 MLX5_ASSERT(reg_c0);
1088                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089                 if (conf->dst == REG_C_0) {
1090                         /* Copy to reg_c[0], within mask only. */
1091                         reg_dst.offset = rte_bsf32(reg_c0);
1092                         /*
1093                          * Mask is ignoring the enianness, because
1094                          * there is no conversion in datapath.
1095                          */
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097                         /* Copy from destination lower bits to reg_c[0]. */
1098                         mask = reg_c0 >> reg_dst.offset;
1099 #else
1100                         /* Copy from destination upper bits to reg_c[0]. */
1101                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102                                           rte_fls_u32(reg_c0));
1103 #endif
1104                 } else {
1105                         mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107                         /* Copy from reg_c[0] to destination lower bits. */
1108                         reg_dst.offset = 0;
1109 #else
1110                         /* Copy from reg_c[0] to destination upper bits. */
1111                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112                                          (rte_fls_u32(reg_c0) -
1113                                           rte_bsf32(reg_c0));
1114 #endif
1115                 }
1116         }
1117         return flow_dv_convert_modify_action(&item,
1118                                              reg_src, &reg_dst, res,
1119                                              MLX5_MODIFICATION_TYPE_COPY,
1120                                              error);
1121 }
1122
1123 /**
1124  * Convert MARK action to DV specification. This routine is used
1125  * in extensive metadata only and requires metadata register to be
1126  * handled. In legacy mode hardware tag resource is engaged.
1127  *
1128  * @param[in] dev
1129  *   Pointer to the rte_eth_dev structure.
1130  * @param[in] conf
1131  *   Pointer to MARK action specification.
1132  * @param[in,out] resource
1133  *   Pointer to the modify-header resource.
1134  * @param[out] error
1135  *   Pointer to the error structure.
1136  *
1137  * @return
1138  *   0 on success, a negative errno value otherwise and rte_errno is set.
1139  */
1140 static int
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142                             const struct rte_flow_action_mark *conf,
1143                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1144                             struct rte_flow_error *error)
1145 {
1146         struct mlx5_priv *priv = dev->data->dev_private;
1147         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148                                            priv->sh->dv_mark_mask);
1149         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150         struct rte_flow_item item = {
1151                 .spec = &data,
1152                 .mask = &mask,
1153         };
1154         struct field_modify_info reg_c_x[] = {
1155                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1156                 {0, 0, 0},
1157         };
1158         int reg;
1159
1160         if (!mask)
1161                 return rte_flow_error_set(error, EINVAL,
1162                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1163                                           NULL, "zero mark action mask");
1164         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1165         if (reg < 0)
1166                 return reg;
1167         MLX5_ASSERT(reg > 0);
1168         if (reg == REG_C_0) {
1169                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1170                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1171
1172                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1173                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1174                 mask = rte_cpu_to_be_32(mask << shl_c0);
1175         }
1176         reg_c_x[0].id = reg_to_field[reg];
1177         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1178                                              MLX5_MODIFICATION_TYPE_SET, error);
1179 }
1180
1181 /**
1182  * Get metadata register index for specified steering domain.
1183  *
1184  * @param[in] dev
1185  *   Pointer to the rte_eth_dev structure.
1186  * @param[in] attr
1187  *   Attributes of flow to determine steering domain.
1188  * @param[out] error
1189  *   Pointer to the error structure.
1190  *
1191  * @return
1192  *   positive index on success, a negative errno value otherwise
1193  *   and rte_errno is set.
1194  */
1195 static enum modify_reg
1196 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1197                          const struct rte_flow_attr *attr,
1198                          struct rte_flow_error *error)
1199 {
1200         int reg =
1201                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1202                                           MLX5_METADATA_FDB :
1203                                             attr->egress ?
1204                                             MLX5_METADATA_TX :
1205                                             MLX5_METADATA_RX, 0, error);
1206         if (reg < 0)
1207                 return rte_flow_error_set(error,
1208                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1209                                           NULL, "unavailable "
1210                                           "metadata register");
1211         return reg;
1212 }
1213
1214 /**
1215  * Convert SET_META action to DV specification.
1216  *
1217  * @param[in] dev
1218  *   Pointer to the rte_eth_dev structure.
1219  * @param[in,out] resource
1220  *   Pointer to the modify-header resource.
1221  * @param[in] attr
1222  *   Attributes of flow that includes this item.
1223  * @param[in] conf
1224  *   Pointer to action specification.
1225  * @param[out] error
1226  *   Pointer to the error structure.
1227  *
1228  * @return
1229  *   0 on success, a negative errno value otherwise and rte_errno is set.
1230  */
1231 static int
1232 flow_dv_convert_action_set_meta
1233                         (struct rte_eth_dev *dev,
1234                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1235                          const struct rte_flow_attr *attr,
1236                          const struct rte_flow_action_set_meta *conf,
1237                          struct rte_flow_error *error)
1238 {
1239         uint32_t data = conf->data;
1240         uint32_t mask = conf->mask;
1241         struct rte_flow_item item = {
1242                 .spec = &data,
1243                 .mask = &mask,
1244         };
1245         struct field_modify_info reg_c_x[] = {
1246                 [1] = {0, 0, 0},
1247         };
1248         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1249
1250         if (reg < 0)
1251                 return reg;
1252         /*
1253          * In datapath code there is no endianness
1254          * coversions for perfromance reasons, all
1255          * pattern conversions are done in rte_flow.
1256          */
1257         if (reg == REG_C_0) {
1258                 struct mlx5_priv *priv = dev->data->dev_private;
1259                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1260                 uint32_t shl_c0;
1261
1262                 MLX5_ASSERT(msk_c0);
1263 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1264                 shl_c0 = rte_bsf32(msk_c0);
1265 #else
1266                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1267 #endif
1268                 mask <<= shl_c0;
1269                 data <<= shl_c0;
1270                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1271         }
1272         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1273         /* The routine expects parameters in memory as big-endian ones. */
1274         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1275                                              MLX5_MODIFICATION_TYPE_SET, error);
1276 }
1277
1278 /**
1279  * Convert modify-header set IPv4 DSCP action to DV specification.
1280  *
1281  * @param[in,out] resource
1282  *   Pointer to the modify-header resource.
1283  * @param[in] action
1284  *   Pointer to action specification.
1285  * @param[out] error
1286  *   Pointer to the error structure.
1287  *
1288  * @return
1289  *   0 on success, a negative errno value otherwise and rte_errno is set.
1290  */
1291 static int
1292 flow_dv_convert_action_modify_ipv4_dscp
1293                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1294                          const struct rte_flow_action *action,
1295                          struct rte_flow_error *error)
1296 {
1297         const struct rte_flow_action_set_dscp *conf =
1298                 (const struct rte_flow_action_set_dscp *)(action->conf);
1299         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1300         struct rte_flow_item_ipv4 ipv4;
1301         struct rte_flow_item_ipv4 ipv4_mask;
1302
1303         memset(&ipv4, 0, sizeof(ipv4));
1304         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1305         ipv4.hdr.type_of_service = conf->dscp;
1306         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1307         item.spec = &ipv4;
1308         item.mask = &ipv4_mask;
1309         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1310                                              MLX5_MODIFICATION_TYPE_SET, error);
1311 }
1312
1313 /**
1314  * Convert modify-header set IPv6 DSCP action to DV specification.
1315  *
1316  * @param[in,out] resource
1317  *   Pointer to the modify-header resource.
1318  * @param[in] action
1319  *   Pointer to action specification.
1320  * @param[out] error
1321  *   Pointer to the error structure.
1322  *
1323  * @return
1324  *   0 on success, a negative errno value otherwise and rte_errno is set.
1325  */
1326 static int
1327 flow_dv_convert_action_modify_ipv6_dscp
1328                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1329                          const struct rte_flow_action *action,
1330                          struct rte_flow_error *error)
1331 {
1332         const struct rte_flow_action_set_dscp *conf =
1333                 (const struct rte_flow_action_set_dscp *)(action->conf);
1334         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1335         struct rte_flow_item_ipv6 ipv6;
1336         struct rte_flow_item_ipv6 ipv6_mask;
1337
1338         memset(&ipv6, 0, sizeof(ipv6));
1339         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1340         /*
1341          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1342          * rdma-core only accept the DSCP bits byte aligned start from
1343          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1344          * bits in IPv6 case as rdma-core requires byte aligned value.
1345          */
1346         ipv6.hdr.vtc_flow = conf->dscp;
1347         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1348         item.spec = &ipv6;
1349         item.mask = &ipv6_mask;
1350         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1351                                              MLX5_MODIFICATION_TYPE_SET, error);
1352 }
1353
1354 /**
1355  * Validate MARK item.
1356  *
1357  * @param[in] dev
1358  *   Pointer to the rte_eth_dev structure.
1359  * @param[in] item
1360  *   Item specification.
1361  * @param[in] attr
1362  *   Attributes of flow that includes this item.
1363  * @param[out] error
1364  *   Pointer to error structure.
1365  *
1366  * @return
1367  *   0 on success, a negative errno value otherwise and rte_errno is set.
1368  */
1369 static int
1370 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1371                            const struct rte_flow_item *item,
1372                            const struct rte_flow_attr *attr __rte_unused,
1373                            struct rte_flow_error *error)
1374 {
1375         struct mlx5_priv *priv = dev->data->dev_private;
1376         struct mlx5_dev_config *config = &priv->config;
1377         const struct rte_flow_item_mark *spec = item->spec;
1378         const struct rte_flow_item_mark *mask = item->mask;
1379         const struct rte_flow_item_mark nic_mask = {
1380                 .id = priv->sh->dv_mark_mask,
1381         };
1382         int ret;
1383
1384         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1385                 return rte_flow_error_set(error, ENOTSUP,
1386                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1387                                           "extended metadata feature"
1388                                           " isn't enabled");
1389         if (!mlx5_flow_ext_mreg_supported(dev))
1390                 return rte_flow_error_set(error, ENOTSUP,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1392                                           "extended metadata register"
1393                                           " isn't supported");
1394         if (!nic_mask.id)
1395                 return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't available");
1399         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1400         if (ret < 0)
1401                 return ret;
1402         if (!spec)
1403                 return rte_flow_error_set(error, EINVAL,
1404                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1405                                           item->spec,
1406                                           "data cannot be empty");
1407         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1408                 return rte_flow_error_set(error, EINVAL,
1409                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1410                                           &spec->id,
1411                                           "mark id exceeds the limit");
1412         if (!mask)
1413                 mask = &nic_mask;
1414         if (!mask->id)
1415                 return rte_flow_error_set(error, EINVAL,
1416                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1417                                         "mask cannot be zero");
1418
1419         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1420                                         (const uint8_t *)&nic_mask,
1421                                         sizeof(struct rte_flow_item_mark),
1422                                         error);
1423         if (ret < 0)
1424                 return ret;
1425         return 0;
1426 }
1427
1428 /**
1429  * Validate META item.
1430  *
1431  * @param[in] dev
1432  *   Pointer to the rte_eth_dev structure.
1433  * @param[in] item
1434  *   Item specification.
1435  * @param[in] attr
1436  *   Attributes of flow that includes this item.
1437  * @param[out] error
1438  *   Pointer to error structure.
1439  *
1440  * @return
1441  *   0 on success, a negative errno value otherwise and rte_errno is set.
1442  */
1443 static int
1444 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1445                            const struct rte_flow_item *item,
1446                            const struct rte_flow_attr *attr,
1447                            struct rte_flow_error *error)
1448 {
1449         struct mlx5_priv *priv = dev->data->dev_private;
1450         struct mlx5_dev_config *config = &priv->config;
1451         const struct rte_flow_item_meta *spec = item->spec;
1452         const struct rte_flow_item_meta *mask = item->mask;
1453         struct rte_flow_item_meta nic_mask = {
1454                 .data = UINT32_MAX
1455         };
1456         int reg;
1457         int ret;
1458
1459         if (!spec)
1460                 return rte_flow_error_set(error, EINVAL,
1461                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1462                                           item->spec,
1463                                           "data cannot be empty");
1464         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1465                 if (!mlx5_flow_ext_mreg_supported(dev))
1466                         return rte_flow_error_set(error, ENOTSUP,
1467                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1468                                           "extended metadata register"
1469                                           " isn't supported");
1470                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1471                 if (reg < 0)
1472                         return reg;
1473                 if (reg == REG_B)
1474                         return rte_flow_error_set(error, ENOTSUP,
1475                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1476                                           "match on reg_b "
1477                                           "isn't supported");
1478                 if (reg != REG_A)
1479                         nic_mask.data = priv->sh->dv_meta_mask;
1480         } else if (attr->transfer) {
1481                 return rte_flow_error_set(error, ENOTSUP,
1482                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1483                                         "extended metadata feature "
1484                                         "should be enabled when "
1485                                         "meta item is requested "
1486                                         "with e-switch mode ");
1487         }
1488         if (!mask)
1489                 mask = &rte_flow_item_meta_mask;
1490         if (!mask->data)
1491                 return rte_flow_error_set(error, EINVAL,
1492                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493                                         "mask cannot be zero");
1494
1495         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496                                         (const uint8_t *)&nic_mask,
1497                                         sizeof(struct rte_flow_item_meta),
1498                                         error);
1499         return ret;
1500 }
1501
1502 /**
1503  * Validate TAG item.
1504  *
1505  * @param[in] dev
1506  *   Pointer to the rte_eth_dev structure.
1507  * @param[in] item
1508  *   Item specification.
1509  * @param[in] attr
1510  *   Attributes of flow that includes this item.
1511  * @param[out] error
1512  *   Pointer to error structure.
1513  *
1514  * @return
1515  *   0 on success, a negative errno value otherwise and rte_errno is set.
1516  */
1517 static int
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519                           const struct rte_flow_item *item,
1520                           const struct rte_flow_attr *attr __rte_unused,
1521                           struct rte_flow_error *error)
1522 {
1523         const struct rte_flow_item_tag *spec = item->spec;
1524         const struct rte_flow_item_tag *mask = item->mask;
1525         const struct rte_flow_item_tag nic_mask = {
1526                 .data = RTE_BE32(UINT32_MAX),
1527                 .index = 0xff,
1528         };
1529         int ret;
1530
1531         if (!mlx5_flow_ext_mreg_supported(dev))
1532                 return rte_flow_error_set(error, ENOTSUP,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1534                                           "extensive metadata register"
1535                                           " isn't supported");
1536         if (!spec)
1537                 return rte_flow_error_set(error, EINVAL,
1538                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1539                                           item->spec,
1540                                           "data cannot be empty");
1541         if (!mask)
1542                 mask = &rte_flow_item_tag_mask;
1543         if (!mask->data)
1544                 return rte_flow_error_set(error, EINVAL,
1545                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546                                         "mask cannot be zero");
1547
1548         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549                                         (const uint8_t *)&nic_mask,
1550                                         sizeof(struct rte_flow_item_tag),
1551                                         error);
1552         if (ret < 0)
1553                 return ret;
1554         if (mask->index != 0xff)
1555                 return rte_flow_error_set(error, EINVAL,
1556                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557                                           "partial mask for tag index"
1558                                           " is not supported");
1559         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1560         if (ret < 0)
1561                 return ret;
1562         MLX5_ASSERT(ret != REG_NONE);
1563         return 0;
1564 }
1565
1566 /**
1567  * Validate vport item.
1568  *
1569  * @param[in] dev
1570  *   Pointer to the rte_eth_dev structure.
1571  * @param[in] item
1572  *   Item specification.
1573  * @param[in] attr
1574  *   Attributes of flow that includes this item.
1575  * @param[in] item_flags
1576  *   Bit-fields that holds the items detected until now.
1577  * @param[out] error
1578  *   Pointer to error structure.
1579  *
1580  * @return
1581  *   0 on success, a negative errno value otherwise and rte_errno is set.
1582  */
1583 static int
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585                               const struct rte_flow_item *item,
1586                               const struct rte_flow_attr *attr,
1587                               uint64_t item_flags,
1588                               struct rte_flow_error *error)
1589 {
1590         const struct rte_flow_item_port_id *spec = item->spec;
1591         const struct rte_flow_item_port_id *mask = item->mask;
1592         const struct rte_flow_item_port_id switch_mask = {
1593                         .id = 0xffffffff,
1594         };
1595         struct mlx5_priv *esw_priv;
1596         struct mlx5_priv *dev_priv;
1597         int ret;
1598
1599         if (!attr->transfer)
1600                 return rte_flow_error_set(error, EINVAL,
1601                                           RTE_FLOW_ERROR_TYPE_ITEM,
1602                                           NULL,
1603                                           "match on port id is valid only"
1604                                           " when transfer flag is enabled");
1605         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606                 return rte_flow_error_set(error, ENOTSUP,
1607                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1608                                           "multiple source ports are not"
1609                                           " supported");
1610         if (!mask)
1611                 mask = &switch_mask;
1612         if (mask->id != 0xffffffff)
1613                 return rte_flow_error_set(error, ENOTSUP,
1614                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1615                                            mask,
1616                                            "no support for partial mask on"
1617                                            " \"id\" field");
1618         ret = mlx5_flow_item_acceptable
1619                                 (item, (const uint8_t *)mask,
1620                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1621                                  sizeof(struct rte_flow_item_port_id),
1622                                  error);
1623         if (ret)
1624                 return ret;
1625         if (!spec)
1626                 return 0;
1627         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1628         if (!esw_priv)
1629                 return rte_flow_error_set(error, rte_errno,
1630                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631                                           "failed to obtain E-Switch info for"
1632                                           " port");
1633         dev_priv = mlx5_dev_to_eswitch_info(dev);
1634         if (!dev_priv)
1635                 return rte_flow_error_set(error, rte_errno,
1636                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1637                                           NULL,
1638                                           "failed to obtain E-Switch info");
1639         if (esw_priv->domain_id != dev_priv->domain_id)
1640                 return rte_flow_error_set(error, EINVAL,
1641                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642                                           "cannot match on a port from a"
1643                                           " different E-Switch");
1644         return 0;
1645 }
1646
1647 /**
1648  * Validate VLAN item.
1649  *
1650  * @param[in] item
1651  *   Item specification.
1652  * @param[in] item_flags
1653  *   Bit-fields that holds the items detected until now.
1654  * @param[in] dev
1655  *   Ethernet device flow is being created on.
1656  * @param[out] error
1657  *   Pointer to error structure.
1658  *
1659  * @return
1660  *   0 on success, a negative errno value otherwise and rte_errno is set.
1661  */
1662 static int
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664                            uint64_t item_flags,
1665                            struct rte_eth_dev *dev,
1666                            struct rte_flow_error *error)
1667 {
1668         const struct rte_flow_item_vlan *mask = item->mask;
1669         const struct rte_flow_item_vlan nic_mask = {
1670                 .tci = RTE_BE16(UINT16_MAX),
1671                 .inner_type = RTE_BE16(UINT16_MAX),
1672         };
1673         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1674         int ret;
1675         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676                                         MLX5_FLOW_LAYER_INNER_L4) :
1677                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1678                                         MLX5_FLOW_LAYER_OUTER_L4);
1679         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1681
1682         if (item_flags & vlanm)
1683                 return rte_flow_error_set(error, EINVAL,
1684                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1685                                           "multiple VLAN layers not supported");
1686         else if ((item_flags & l34m) != 0)
1687                 return rte_flow_error_set(error, EINVAL,
1688                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1689                                           "VLAN cannot follow L3/L4 layer");
1690         if (!mask)
1691                 mask = &rte_flow_item_vlan_mask;
1692         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693                                         (const uint8_t *)&nic_mask,
1694                                         sizeof(struct rte_flow_item_vlan),
1695                                         error);
1696         if (ret)
1697                 return ret;
1698         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699                 struct mlx5_priv *priv = dev->data->dev_private;
1700
1701                 if (priv->vmwa_context) {
1702                         /*
1703                          * Non-NULL context means we have a virtual machine
1704                          * and SR-IOV enabled, we have to create VLAN interface
1705                          * to make hypervisor to setup E-Switch vport
1706                          * context correctly. We avoid creating the multiple
1707                          * VLAN interfaces, so we cannot support VLAN tag mask.
1708                          */
1709                         return rte_flow_error_set(error, EINVAL,
1710                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1711                                                   item,
1712                                                   "VLAN tag mask is not"
1713                                                   " supported in virtual"
1714                                                   " environment");
1715                 }
1716         }
1717         return 0;
1718 }
1719
1720 /*
1721  * GTP flags are contained in 1 byte of the format:
1722  * -------------------------------------------
1723  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1724  * |-----------------------------------------|
1725  * | value | Version | PT | Res | E | S | PN |
1726  * -------------------------------------------
1727  *
1728  * Matching is supported only for GTP flags E, S, PN.
1729  */
1730 #define MLX5_GTP_FLAGS_MASK     0x07
1731
1732 /**
1733  * Validate GTP item.
1734  *
1735  * @param[in] dev
1736  *   Pointer to the rte_eth_dev structure.
1737  * @param[in] item
1738  *   Item specification.
1739  * @param[in] item_flags
1740  *   Bit-fields that holds the items detected until now.
1741  * @param[out] error
1742  *   Pointer to error structure.
1743  *
1744  * @return
1745  *   0 on success, a negative errno value otherwise and rte_errno is set.
1746  */
1747 static int
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749                           const struct rte_flow_item *item,
1750                           uint64_t item_flags,
1751                           struct rte_flow_error *error)
1752 {
1753         struct mlx5_priv *priv = dev->data->dev_private;
1754         const struct rte_flow_item_gtp *spec = item->spec;
1755         const struct rte_flow_item_gtp *mask = item->mask;
1756         const struct rte_flow_item_gtp nic_mask = {
1757                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1758                 .msg_type = 0xff,
1759                 .teid = RTE_BE32(0xffffffff),
1760         };
1761
1762         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763                 return rte_flow_error_set(error, ENOTSUP,
1764                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1765                                           "GTP support is not enabled");
1766         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767                 return rte_flow_error_set(error, ENOTSUP,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "multiple tunnel layers not"
1770                                           " supported");
1771         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772                 return rte_flow_error_set(error, EINVAL,
1773                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1774                                           "no outer UDP layer found");
1775         if (!mask)
1776                 mask = &rte_flow_item_gtp_mask;
1777         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778                 return rte_flow_error_set(error, ENOTSUP,
1779                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1780                                           "Match is supported for GTP"
1781                                           " flags only");
1782         return mlx5_flow_item_acceptable
1783                 (item, (const uint8_t *)mask,
1784                  (const uint8_t *)&nic_mask,
1785                  sizeof(struct rte_flow_item_gtp),
1786                  error);
1787 }
1788
1789 /**
1790  * Validate the pop VLAN action.
1791  *
1792  * @param[in] dev
1793  *   Pointer to the rte_eth_dev structure.
1794  * @param[in] action_flags
1795  *   Holds the actions detected until now.
1796  * @param[in] action
1797  *   Pointer to the pop vlan action.
1798  * @param[in] item_flags
1799  *   The items found in this flow rule.
1800  * @param[in] attr
1801  *   Pointer to flow attributes.
1802  * @param[out] error
1803  *   Pointer to error structure.
1804  *
1805  * @return
1806  *   0 on success, a negative errno value otherwise and rte_errno is set.
1807  */
1808 static int
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810                                  uint64_t action_flags,
1811                                  const struct rte_flow_action *action,
1812                                  uint64_t item_flags,
1813                                  const struct rte_flow_attr *attr,
1814                                  struct rte_flow_error *error)
1815 {
1816         const struct mlx5_priv *priv = dev->data->dev_private;
1817
1818         (void)action;
1819         (void)attr;
1820         if (!priv->sh->pop_vlan_action)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1823                                           NULL,
1824                                           "pop vlan action is not supported");
1825         if (attr->egress)
1826                 return rte_flow_error_set(error, ENOTSUP,
1827                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1828                                           NULL,
1829                                           "pop vlan action not supported for "
1830                                           "egress");
1831         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1834                                           "no support for multiple VLAN "
1835                                           "actions");
1836         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1837         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1838             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1841                                           NULL,
1842                                           "cannot pop vlan after decap without "
1843                                           "match on inner vlan in the flow");
1844         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1845         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1846             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847                 return rte_flow_error_set(error, ENOTSUP,
1848                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1849                                           NULL,
1850                                           "cannot pop vlan without a "
1851                                           "match on (outer) vlan in the flow");
1852         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1853                 return rte_flow_error_set(error, EINVAL,
1854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1855                                           "wrong action order, port_id should "
1856                                           "be after pop VLAN action");
1857         if (!attr->transfer && priv->representor)
1858                 return rte_flow_error_set(error, ENOTSUP,
1859                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1860                                           "pop vlan action for VF representor "
1861                                           "not supported on NIC table");
1862         return 0;
1863 }
1864
1865 /**
1866  * Get VLAN default info from vlan match info.
1867  *
1868  * @param[in] items
1869  *   the list of item specifications.
1870  * @param[out] vlan
1871  *   pointer VLAN info to fill to.
1872  *
1873  * @return
1874  *   0 on success, a negative errno value otherwise and rte_errno is set.
1875  */
1876 static void
1877 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1878                                   struct rte_vlan_hdr *vlan)
1879 {
1880         const struct rte_flow_item_vlan nic_mask = {
1881                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1882                                 MLX5DV_FLOW_VLAN_VID_MASK),
1883                 .inner_type = RTE_BE16(0xffff),
1884         };
1885
1886         if (items == NULL)
1887                 return;
1888         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1889                 int type = items->type;
1890
1891                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1892                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1893                         break;
1894         }
1895         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1896                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1897                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1898
1899                 /* If VLAN item in pattern doesn't contain data, return here. */
1900                 if (!vlan_v)
1901                         return;
1902                 if (!vlan_m)
1903                         vlan_m = &nic_mask;
1904                 /* Only full match values are accepted */
1905                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1906                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1907                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1908                         vlan->vlan_tci |=
1909                                 rte_be_to_cpu_16(vlan_v->tci &
1910                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1911                 }
1912                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1913                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1914                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1915                         vlan->vlan_tci |=
1916                                 rte_be_to_cpu_16(vlan_v->tci &
1917                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1918                 }
1919                 if (vlan_m->inner_type == nic_mask.inner_type)
1920                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1921                                                            vlan_m->inner_type);
1922         }
1923 }
1924
1925 /**
1926  * Validate the push VLAN action.
1927  *
1928  * @param[in] dev
1929  *   Pointer to the rte_eth_dev structure.
1930  * @param[in] action_flags
1931  *   Holds the actions detected until now.
1932  * @param[in] item_flags
1933  *   The items found in this flow rule.
1934  * @param[in] action
1935  *   Pointer to the action structure.
1936  * @param[in] attr
1937  *   Pointer to flow attributes
1938  * @param[out] error
1939  *   Pointer to error structure.
1940  *
1941  * @return
1942  *   0 on success, a negative errno value otherwise and rte_errno is set.
1943  */
1944 static int
1945 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1946                                   uint64_t action_flags,
1947                                   const struct rte_flow_item_vlan *vlan_m,
1948                                   const struct rte_flow_action *action,
1949                                   const struct rte_flow_attr *attr,
1950                                   struct rte_flow_error *error)
1951 {
1952         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1953         const struct mlx5_priv *priv = dev->data->dev_private;
1954
1955         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1956             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "invalid vlan ethertype");
1960         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961                 return rte_flow_error_set(error, EINVAL,
1962                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1963                                           "wrong action order, port_id should "
1964                                           "be after push VLAN");
1965         if (!attr->transfer && priv->representor)
1966                 return rte_flow_error_set(error, ENOTSUP,
1967                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968                                           "push vlan action for VF representor "
1969                                           "not supported on NIC table");
1970         if (vlan_m &&
1971             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975             !(mlx5_flow_find_action
1976                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977                 return rte_flow_error_set(error, EINVAL,
1978                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1979                                           "not full match mask on VLAN PCP and "
1980                                           "there is no of_set_vlan_pcp action, "
1981                                           "push VLAN action cannot figure out "
1982                                           "PCP value");
1983         if (vlan_m &&
1984             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988             !(mlx5_flow_find_action
1989                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990                 return rte_flow_error_set(error, EINVAL,
1991                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1992                                           "not full match mask on VLAN VID and "
1993                                           "there is no of_set_vlan_vid action, "
1994                                           "push VLAN action cannot figure out "
1995                                           "VID value");
1996         (void)attr;
1997         return 0;
1998 }
1999
2000 /**
2001  * Validate the set VLAN PCP.
2002  *
2003  * @param[in] action_flags
2004  *   Holds the actions detected until now.
2005  * @param[in] actions
2006  *   Pointer to the list of actions remaining in the flow rule.
2007  * @param[out] error
2008  *   Pointer to error structure.
2009  *
2010  * @return
2011  *   0 on success, a negative errno value otherwise and rte_errno is set.
2012  */
2013 static int
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015                                      const struct rte_flow_action actions[],
2016                                      struct rte_flow_error *error)
2017 {
2018         const struct rte_flow_action *action = actions;
2019         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2020
2021         if (conf->vlan_pcp > 7)
2022                 return rte_flow_error_set(error, EINVAL,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "VLAN PCP value is too big");
2025         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026                 return rte_flow_error_set(error, ENOTSUP,
2027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2028                                           "set VLAN PCP action must follow "
2029                                           "the push VLAN action");
2030         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031                 return rte_flow_error_set(error, ENOTSUP,
2032                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2033                                           "Multiple VLAN PCP modification are "
2034                                           "not supported");
2035         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2038                                           "wrong action order, port_id should "
2039                                           "be after set VLAN PCP");
2040         return 0;
2041 }
2042
2043 /**
2044  * Validate the set VLAN VID.
2045  *
2046  * @param[in] item_flags
2047  *   Holds the items detected in this rule.
2048  * @param[in] action_flags
2049  *   Holds the actions detected until now.
2050  * @param[in] actions
2051  *   Pointer to the list of actions remaining in the flow rule.
2052  * @param[out] error
2053  *   Pointer to error structure.
2054  *
2055  * @return
2056  *   0 on success, a negative errno value otherwise and rte_errno is set.
2057  */
2058 static int
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060                                      uint64_t action_flags,
2061                                      const struct rte_flow_action actions[],
2062                                      struct rte_flow_error *error)
2063 {
2064         const struct rte_flow_action *action = actions;
2065         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2066
2067         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068                 return rte_flow_error_set(error, EINVAL,
2069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2070                                           "VLAN VID value is too big");
2071         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073                 return rte_flow_error_set(error, ENOTSUP,
2074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2075                                           "set VLAN VID action must follow push"
2076                                           " VLAN action or match on VLAN item");
2077         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078                 return rte_flow_error_set(error, ENOTSUP,
2079                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2080                                           "Multiple VLAN VID modifications are "
2081                                           "not supported");
2082         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083                 return rte_flow_error_set(error, EINVAL,
2084                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2085                                           "wrong action order, port_id should "
2086                                           "be after set VLAN VID");
2087         return 0;
2088 }
2089
2090 /*
2091  * Validate the FLAG action.
2092  *
2093  * @param[in] dev
2094  *   Pointer to the rte_eth_dev structure.
2095  * @param[in] action_flags
2096  *   Holds the actions detected until now.
2097  * @param[in] attr
2098  *   Pointer to flow attributes
2099  * @param[out] error
2100  *   Pointer to error structure.
2101  *
2102  * @return
2103  *   0 on success, a negative errno value otherwise and rte_errno is set.
2104  */
2105 static int
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107                              uint64_t action_flags,
2108                              const struct rte_flow_attr *attr,
2109                              struct rte_flow_error *error)
2110 {
2111         struct mlx5_priv *priv = dev->data->dev_private;
2112         struct mlx5_dev_config *config = &priv->config;
2113         int ret;
2114
2115         /* Fall back if no extended metadata register support. */
2116         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117                 return mlx5_flow_validate_action_flag(action_flags, attr,
2118                                                       error);
2119         /* Extensive metadata mode requires registers. */
2120         if (!mlx5_flow_ext_mreg_supported(dev))
2121                 return rte_flow_error_set(error, ENOTSUP,
2122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123                                           "no metadata registers "
2124                                           "to support flag action");
2125         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126                 return rte_flow_error_set(error, ENOTSUP,
2127                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128                                           "extended metadata register"
2129                                           " isn't available");
2130         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2131         if (ret < 0)
2132                 return ret;
2133         MLX5_ASSERT(ret > 0);
2134         if (action_flags & MLX5_FLOW_ACTION_MARK)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't mark and flag in same flow");
2138         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2141                                           "can't have 2 flag"
2142                                           " actions in same flow");
2143         return 0;
2144 }
2145
2146 /**
2147  * Validate MARK action.
2148  *
2149  * @param[in] dev
2150  *   Pointer to the rte_eth_dev structure.
2151  * @param[in] action
2152  *   Pointer to action.
2153  * @param[in] action_flags
2154  *   Holds the actions detected until now.
2155  * @param[in] attr
2156  *   Pointer to flow attributes
2157  * @param[out] error
2158  *   Pointer to error structure.
2159  *
2160  * @return
2161  *   0 on success, a negative errno value otherwise and rte_errno is set.
2162  */
2163 static int
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165                              const struct rte_flow_action *action,
2166                              uint64_t action_flags,
2167                              const struct rte_flow_attr *attr,
2168                              struct rte_flow_error *error)
2169 {
2170         struct mlx5_priv *priv = dev->data->dev_private;
2171         struct mlx5_dev_config *config = &priv->config;
2172         const struct rte_flow_action_mark *mark = action->conf;
2173         int ret;
2174
2175         /* Fall back if no extended metadata register support. */
2176         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177                 return mlx5_flow_validate_action_mark(action, action_flags,
2178                                                       attr, error);
2179         /* Extensive metadata mode requires registers. */
2180         if (!mlx5_flow_ext_mreg_supported(dev))
2181                 return rte_flow_error_set(error, ENOTSUP,
2182                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183                                           "no metadata registers "
2184                                           "to support mark action");
2185         if (!priv->sh->dv_mark_mask)
2186                 return rte_flow_error_set(error, ENOTSUP,
2187                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188                                           "extended metadata register"
2189                                           " isn't available");
2190         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2191         if (ret < 0)
2192                 return ret;
2193         MLX5_ASSERT(ret > 0);
2194         if (!mark)
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2197                                           "configuration cannot be null");
2198         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199                 return rte_flow_error_set(error, EINVAL,
2200                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2201                                           &mark->id,
2202                                           "mark id exceeds the limit");
2203         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't flag and mark in same flow");
2207         if (action_flags & MLX5_FLOW_ACTION_MARK)
2208                 return rte_flow_error_set(error, EINVAL,
2209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210                                           "can't have 2 mark actions in same"
2211                                           " flow");
2212         return 0;
2213 }
2214
2215 /**
2216  * Validate SET_META action.
2217  *
2218  * @param[in] dev
2219  *   Pointer to the rte_eth_dev structure.
2220  * @param[in] action
2221  *   Pointer to the action structure.
2222  * @param[in] action_flags
2223  *   Holds the actions detected until now.
2224  * @param[in] attr
2225  *   Pointer to flow attributes
2226  * @param[out] error
2227  *   Pointer to error structure.
2228  *
2229  * @return
2230  *   0 on success, a negative errno value otherwise and rte_errno is set.
2231  */
2232 static int
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234                                  const struct rte_flow_action *action,
2235                                  uint64_t action_flags __rte_unused,
2236                                  const struct rte_flow_attr *attr,
2237                                  struct rte_flow_error *error)
2238 {
2239         const struct rte_flow_action_set_meta *conf;
2240         uint32_t nic_mask = UINT32_MAX;
2241         int reg;
2242
2243         if (!mlx5_flow_ext_mreg_supported(dev))
2244                 return rte_flow_error_set(error, ENOTSUP,
2245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2246                                           "extended metadata register"
2247                                           " isn't supported");
2248         reg = flow_dv_get_metadata_reg(dev, attr, error);
2249         if (reg < 0)
2250                 return reg;
2251         if (reg != REG_A && reg != REG_B) {
2252                 struct mlx5_priv *priv = dev->data->dev_private;
2253
2254                 nic_mask = priv->sh->dv_meta_mask;
2255         }
2256         if (!(action->conf))
2257                 return rte_flow_error_set(error, EINVAL,
2258                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2259                                           "configuration cannot be null");
2260         conf = (const struct rte_flow_action_set_meta *)action->conf;
2261         if (!conf->mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "zero mask doesn't have any effect");
2265         if (conf->mask & ~nic_mask)
2266                 return rte_flow_error_set(error, EINVAL,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "meta data must be within reg C0");
2269         return 0;
2270 }
2271
2272 /**
2273  * Validate SET_TAG action.
2274  *
2275  * @param[in] dev
2276  *   Pointer to the rte_eth_dev structure.
2277  * @param[in] action
2278  *   Pointer to the action structure.
2279  * @param[in] action_flags
2280  *   Holds the actions detected until now.
2281  * @param[in] attr
2282  *   Pointer to flow attributes
2283  * @param[out] error
2284  *   Pointer to error structure.
2285  *
2286  * @return
2287  *   0 on success, a negative errno value otherwise and rte_errno is set.
2288  */
2289 static int
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291                                 const struct rte_flow_action *action,
2292                                 uint64_t action_flags,
2293                                 const struct rte_flow_attr *attr,
2294                                 struct rte_flow_error *error)
2295 {
2296         const struct rte_flow_action_set_tag *conf;
2297         const uint64_t terminal_action_flags =
2298                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299                 MLX5_FLOW_ACTION_RSS;
2300         int ret;
2301
2302         if (!mlx5_flow_ext_mreg_supported(dev))
2303                 return rte_flow_error_set(error, ENOTSUP,
2304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2305                                           "extensive metadata register"
2306                                           " isn't supported");
2307         if (!(action->conf))
2308                 return rte_flow_error_set(error, EINVAL,
2309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2310                                           "configuration cannot be null");
2311         conf = (const struct rte_flow_action_set_tag *)action->conf;
2312         if (!conf->mask)
2313                 return rte_flow_error_set(error, EINVAL,
2314                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2315                                           "zero mask doesn't have any effect");
2316         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2317         if (ret < 0)
2318                 return ret;
2319         if (!attr->transfer && attr->ingress &&
2320             (action_flags & terminal_action_flags))
2321                 return rte_flow_error_set(error, EINVAL,
2322                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2323                                           "set_tag has no effect"
2324                                           " with terminal actions");
2325         return 0;
2326 }
2327
2328 /**
2329  * Validate count action.
2330  *
2331  * @param[in] dev
2332  *   Pointer to rte_eth_dev structure.
2333  * @param[out] error
2334  *   Pointer to error structure.
2335  *
2336  * @return
2337  *   0 on success, a negative errno value otherwise and rte_errno is set.
2338  */
2339 static int
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341                               struct rte_flow_error *error)
2342 {
2343         struct mlx5_priv *priv = dev->data->dev_private;
2344
2345         if (!priv->config.devx)
2346                 goto notsup_err;
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2348         return 0;
2349 #endif
2350 notsup_err:
2351         return rte_flow_error_set
2352                       (error, ENOTSUP,
2353                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2354                        NULL,
2355                        "count action not supported");
2356 }
2357
2358 /**
2359  * Validate the L2 encap action.
2360  *
2361  * @param[in] dev
2362  *   Pointer to the rte_eth_dev structure.
2363  * @param[in] action_flags
2364  *   Holds the actions detected until now.
2365  * @param[in] action
2366  *   Pointer to the action structure.
2367  * @param[in] attr
2368  *   Pointer to flow attributes.
2369  * @param[out] error
2370  *   Pointer to error structure.
2371  *
2372  * @return
2373  *   0 on success, a negative errno value otherwise and rte_errno is set.
2374  */
2375 static int
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377                                  uint64_t action_flags,
2378                                  const struct rte_flow_action *action,
2379                                  const struct rte_flow_attr *attr,
2380                                  struct rte_flow_error *error)
2381 {
2382         const struct mlx5_priv *priv = dev->data->dev_private;
2383
2384         if (!(action->conf))
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2387                                           "configuration cannot be null");
2388         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389                 return rte_flow_error_set(error, EINVAL,
2390                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391                                           "can only have a single encap action "
2392                                           "in a flow");
2393         if (!attr->transfer && priv->representor)
2394                 return rte_flow_error_set(error, ENOTSUP,
2395                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396                                           "encap action for VF representor "
2397                                           "not supported on NIC table");
2398         return 0;
2399 }
2400
2401 /**
2402  * Validate a decap action.
2403  *
2404  * @param[in] dev
2405  *   Pointer to the rte_eth_dev structure.
2406  * @param[in] action_flags
2407  *   Holds the actions detected until now.
2408  * @param[in] attr
2409  *   Pointer to flow attributes
2410  * @param[out] error
2411  *   Pointer to error structure.
2412  *
2413  * @return
2414  *   0 on success, a negative errno value otherwise and rte_errno is set.
2415  */
2416 static int
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418                               uint64_t action_flags,
2419                               const struct rte_flow_attr *attr,
2420                               struct rte_flow_error *error)
2421 {
2422         const struct mlx5_priv *priv = dev->data->dev_private;
2423
2424         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425             !priv->config.decap_en)
2426                 return rte_flow_error_set(error, ENOTSUP,
2427                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428                                           "decap is not enabled");
2429         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430                 return rte_flow_error_set(error, ENOTSUP,
2431                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2432                                           action_flags &
2433                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2434                                           "have a single decap action" : "decap "
2435                                           "after encap is not supported");
2436         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437                 return rte_flow_error_set(error, EINVAL,
2438                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439                                           "can't have decap action after"
2440                                           " modify action");
2441         if (attr->egress)
2442                 return rte_flow_error_set(error, ENOTSUP,
2443                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2444                                           NULL,
2445                                           "decap action not supported for "
2446                                           "egress");
2447         if (!attr->transfer && priv->representor)
2448                 return rte_flow_error_set(error, ENOTSUP,
2449                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450                                           "decap action for VF representor "
2451                                           "not supported on NIC table");
2452         return 0;
2453 }
2454
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2456
2457 /**
2458  * Validate the raw encap and decap actions.
2459  *
2460  * @param[in] dev
2461  *   Pointer to the rte_eth_dev structure.
2462  * @param[in] decap
2463  *   Pointer to the decap action.
2464  * @param[in] encap
2465  *   Pointer to the encap action.
2466  * @param[in] attr
2467  *   Pointer to flow attributes
2468  * @param[in/out] action_flags
2469  *   Holds the actions detected until now.
2470  * @param[out] actions_n
2471  *   pointer to the number of actions counter.
2472  * @param[out] error
2473  *   Pointer to error structure.
2474  *
2475  * @return
2476  *   0 on success, a negative errno value otherwise and rte_errno is set.
2477  */
2478 static int
2479 flow_dv_validate_action_raw_encap_decap
2480         (struct rte_eth_dev *dev,
2481          const struct rte_flow_action_raw_decap *decap,
2482          const struct rte_flow_action_raw_encap *encap,
2483          const struct rte_flow_attr *attr, uint64_t *action_flags,
2484          int *actions_n, struct rte_flow_error *error)
2485 {
2486         const struct mlx5_priv *priv = dev->data->dev_private;
2487         int ret;
2488
2489         if (encap && (!encap->size || !encap->data))
2490                 return rte_flow_error_set(error, EINVAL,
2491                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492                                           "raw encap data cannot be empty");
2493         if (decap && encap) {
2494                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2496                         /* L3 encap. */
2497                         decap = NULL;
2498                 else if (encap->size <=
2499                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2500                            decap->size >
2501                            MLX5_ENCAPSULATION_DECISION_SIZE)
2502                         /* L3 decap. */
2503                         encap = NULL;
2504                 else if (encap->size >
2505                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2506                            decap->size >
2507                            MLX5_ENCAPSULATION_DECISION_SIZE)
2508                         /* 2 L2 actions: encap and decap. */
2509                         ;
2510                 else
2511                         return rte_flow_error_set(error,
2512                                 ENOTSUP,
2513                                 RTE_FLOW_ERROR_TYPE_ACTION,
2514                                 NULL, "unsupported too small "
2515                                 "raw decap and too small raw "
2516                                 "encap combination");
2517         }
2518         if (decap) {
2519                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2520                                                     error);
2521                 if (ret < 0)
2522                         return ret;
2523                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2524                 ++(*actions_n);
2525         }
2526         if (encap) {
2527                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528                         return rte_flow_error_set(error, ENOTSUP,
2529                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2530                                                   NULL,
2531                                                   "small raw encap size");
2532                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533                         return rte_flow_error_set(error, EINVAL,
2534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2535                                                   NULL,
2536                                                   "more than one encap action");
2537                 if (!attr->transfer && priv->representor)
2538                         return rte_flow_error_set
2539                                         (error, ENOTSUP,
2540                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541                                          "encap action for VF representor "
2542                                          "not supported on NIC table");
2543                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2544                 ++(*actions_n);
2545         }
2546         return 0;
2547 }
2548
2549 /**
2550  * Find existing encap/decap resource or create and register a new one.
2551  *
2552  * @param[in, out] dev
2553  *   Pointer to rte_eth_dev structure.
2554  * @param[in, out] resource
2555  *   Pointer to encap/decap resource.
2556  * @parm[in, out] dev_flow
2557  *   Pointer to the dev_flow.
2558  * @param[out] error
2559  *   pointer to error structure.
2560  *
2561  * @return
2562  *   0 on success otherwise -errno and errno is set.
2563  */
2564 static int
2565 flow_dv_encap_decap_resource_register
2566                         (struct rte_eth_dev *dev,
2567                          struct mlx5_flow_dv_encap_decap_resource *resource,
2568                          struct mlx5_flow *dev_flow,
2569                          struct rte_flow_error *error)
2570 {
2571         struct mlx5_priv *priv = dev->data->dev_private;
2572         struct mlx5_dev_ctx_shared *sh = priv->sh;
2573         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574         struct mlx5dv_dr_domain *domain;
2575         uint32_t idx = 0;
2576         int ret;
2577
2578         resource->flags = dev_flow->dv.group ? 0 : 1;
2579         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580                 domain = sh->fdb_domain;
2581         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582                 domain = sh->rx_domain;
2583         else
2584                 domain = sh->tx_domain;
2585         /* Lookup a matching resource from cache. */
2586         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587                       cache_resource, next) {
2588                 if (resource->reformat_type == cache_resource->reformat_type &&
2589                     resource->ft_type == cache_resource->ft_type &&
2590                     resource->flags == cache_resource->flags &&
2591                     resource->size == cache_resource->size &&
2592                     !memcmp((const void *)resource->buf,
2593                             (const void *)cache_resource->buf,
2594                             resource->size)) {
2595                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596                                 (void *)cache_resource,
2597                                 rte_atomic32_read(&cache_resource->refcnt));
2598                         rte_atomic32_inc(&cache_resource->refcnt);
2599                         dev_flow->handle->dvh.rix_encap_decap = idx;
2600                         dev_flow->dv.encap_decap = cache_resource;
2601                         return 0;
2602                 }
2603         }
2604         /* Register new encap/decap resource. */
2605         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606                                        &dev_flow->handle->dvh.rix_encap_decap);
2607         if (!cache_resource)
2608                 return rte_flow_error_set(error, ENOMEM,
2609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610                                           "cannot allocate resource memory");
2611         *cache_resource = *resource;
2612         ret = mlx5_flow_os_create_flow_action_packet_reformat
2613                                         (sh->ctx, domain, cache_resource,
2614                                          &cache_resource->action);
2615         if (ret) {
2616                 mlx5_free(cache_resource);
2617                 return rte_flow_error_set(error, ENOMEM,
2618                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619                                           NULL, "cannot create action");
2620         }
2621         rte_atomic32_init(&cache_resource->refcnt);
2622         rte_atomic32_inc(&cache_resource->refcnt);
2623         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2625                      next);
2626         dev_flow->dv.encap_decap = cache_resource;
2627         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628                 (void *)cache_resource,
2629                 rte_atomic32_read(&cache_resource->refcnt));
2630         return 0;
2631 }
2632
2633 /**
2634  * Find existing table jump resource or create and register a new one.
2635  *
2636  * @param[in, out] dev
2637  *   Pointer to rte_eth_dev structure.
2638  * @param[in, out] tbl
2639  *   Pointer to flow table resource.
2640  * @parm[in, out] dev_flow
2641  *   Pointer to the dev_flow.
2642  * @param[out] error
2643  *   pointer to error structure.
2644  *
2645  * @return
2646  *   0 on success otherwise -errno and errno is set.
2647  */
2648 static int
2649 flow_dv_jump_tbl_resource_register
2650                         (struct rte_eth_dev *dev __rte_unused,
2651                          struct mlx5_flow_tbl_resource *tbl,
2652                          struct mlx5_flow *dev_flow,
2653                          struct rte_flow_error *error)
2654 {
2655         struct mlx5_flow_tbl_data_entry *tbl_data =
2656                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2657         int cnt, ret;
2658
2659         MLX5_ASSERT(tbl);
2660         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2661         if (!cnt) {
2662                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663                                 (tbl->obj, &tbl_data->jump.action);
2664                 if (ret)
2665                         return rte_flow_error_set(error, ENOMEM,
2666                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667                                         NULL, "cannot create jump action");
2668                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         } else {
2671                 /* old jump should not make the table ref++. */
2672                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673                 MLX5_ASSERT(tbl_data->jump.action);
2674                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675                         (void *)&tbl_data->jump, cnt);
2676         }
2677         rte_atomic32_inc(&tbl_data->jump.refcnt);
2678         dev_flow->handle->rix_jump = tbl_data->idx;
2679         dev_flow->dv.jump = &tbl_data->jump;
2680         return 0;
2681 }
2682
2683 /**
2684  * Find existing default miss resource or create and register a new one.
2685  *
2686  * @param[in, out] dev
2687  *   Pointer to rte_eth_dev structure.
2688  * @param[out] error
2689  *   pointer to error structure.
2690  *
2691  * @return
2692  *   0 on success otherwise -errno and errno is set.
2693  */
2694 static int
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696                 struct rte_flow_error *error)
2697 {
2698         struct mlx5_priv *priv = dev->data->dev_private;
2699         struct mlx5_dev_ctx_shared *sh = priv->sh;
2700         struct mlx5_flow_default_miss_resource *cache_resource =
2701                         &sh->default_miss;
2702         int cnt = rte_atomic32_read(&cache_resource->refcnt);
2703
2704         if (!cnt) {
2705                 MLX5_ASSERT(cache_resource->action);
2706                 cache_resource->action =
2707                 mlx5_glue->dr_create_flow_action_default_miss();
2708                 if (!cache_resource->action)
2709                         return rte_flow_error_set(error, ENOMEM,
2710                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711                                         "cannot create default miss action");
2712                 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713                                 (void *)cache_resource->action, cnt);
2714         }
2715         rte_atomic32_inc(&cache_resource->refcnt);
2716         return 0;
2717 }
2718
2719 /**
2720  * Find existing table port ID resource or create and register a new one.
2721  *
2722  * @param[in, out] dev
2723  *   Pointer to rte_eth_dev structure.
2724  * @param[in, out] resource
2725  *   Pointer to port ID action resource.
2726  * @parm[in, out] dev_flow
2727  *   Pointer to the dev_flow.
2728  * @param[out] error
2729  *   pointer to error structure.
2730  *
2731  * @return
2732  *   0 on success otherwise -errno and errno is set.
2733  */
2734 static int
2735 flow_dv_port_id_action_resource_register
2736                         (struct rte_eth_dev *dev,
2737                          struct mlx5_flow_dv_port_id_action_resource *resource,
2738                          struct mlx5_flow *dev_flow,
2739                          struct rte_flow_error *error)
2740 {
2741         struct mlx5_priv *priv = dev->data->dev_private;
2742         struct mlx5_dev_ctx_shared *sh = priv->sh;
2743         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2744         uint32_t idx = 0;
2745         int ret;
2746
2747         /* Lookup a matching resource from cache. */
2748         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749                       idx, cache_resource, next) {
2750                 if (resource->port_id == cache_resource->port_id) {
2751                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2752                                 "refcnt %d++",
2753                                 (void *)cache_resource,
2754                                 rte_atomic32_read(&cache_resource->refcnt));
2755                         rte_atomic32_inc(&cache_resource->refcnt);
2756                         dev_flow->handle->rix_port_id_action = idx;
2757                         dev_flow->dv.port_id_action = cache_resource;
2758                         return 0;
2759                 }
2760         }
2761         /* Register new port id action resource. */
2762         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763                                        &dev_flow->handle->rix_port_id_action);
2764         if (!cache_resource)
2765                 return rte_flow_error_set(error, ENOMEM,
2766                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767                                           "cannot allocate resource memory");
2768         *cache_resource = *resource;
2769         ret = mlx5_flow_os_create_flow_action_dest_port
2770                                 (priv->sh->fdb_domain, resource->port_id,
2771                                  &cache_resource->action);
2772         if (ret) {
2773                 mlx5_free(cache_resource);
2774                 return rte_flow_error_set(error, ENOMEM,
2775                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776                                           NULL, "cannot create action");
2777         }
2778         rte_atomic32_init(&cache_resource->refcnt);
2779         rte_atomic32_inc(&cache_resource->refcnt);
2780         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781                      dev_flow->handle->rix_port_id_action, cache_resource,
2782                      next);
2783         dev_flow->dv.port_id_action = cache_resource;
2784         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785                 (void *)cache_resource,
2786                 rte_atomic32_read(&cache_resource->refcnt));
2787         return 0;
2788 }
2789
2790 /**
2791  * Find existing push vlan resource or create and register a new one.
2792  *
2793  * @param [in, out] dev
2794  *   Pointer to rte_eth_dev structure.
2795  * @param[in, out] resource
2796  *   Pointer to port ID action resource.
2797  * @parm[in, out] dev_flow
2798  *   Pointer to the dev_flow.
2799  * @param[out] error
2800  *   pointer to error structure.
2801  *
2802  * @return
2803  *   0 on success otherwise -errno and errno is set.
2804  */
2805 static int
2806 flow_dv_push_vlan_action_resource_register
2807                        (struct rte_eth_dev *dev,
2808                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809                         struct mlx5_flow *dev_flow,
2810                         struct rte_flow_error *error)
2811 {
2812         struct mlx5_priv *priv = dev->data->dev_private;
2813         struct mlx5_dev_ctx_shared *sh = priv->sh;
2814         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815         struct mlx5dv_dr_domain *domain;
2816         uint32_t idx = 0;
2817         int ret;
2818
2819         /* Lookup a matching resource from cache. */
2820         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                       sh->push_vlan_action_list, idx, cache_resource, next) {
2822                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823                     resource->ft_type == cache_resource->ft_type) {
2824                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2825                                 "refcnt %d++",
2826                                 (void *)cache_resource,
2827                                 rte_atomic32_read(&cache_resource->refcnt));
2828                         rte_atomic32_inc(&cache_resource->refcnt);
2829                         dev_flow->handle->dvh.rix_push_vlan = idx;
2830                         dev_flow->dv.push_vlan_res = cache_resource;
2831                         return 0;
2832                 }
2833         }
2834         /* Register new push_vlan action resource. */
2835         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836                                        &dev_flow->handle->dvh.rix_push_vlan);
2837         if (!cache_resource)
2838                 return rte_flow_error_set(error, ENOMEM,
2839                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840                                           "cannot allocate resource memory");
2841         *cache_resource = *resource;
2842         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843                 domain = sh->fdb_domain;
2844         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845                 domain = sh->rx_domain;
2846         else
2847                 domain = sh->tx_domain;
2848         ret = mlx5_flow_os_create_flow_action_push_vlan
2849                                         (domain, resource->vlan_tag,
2850                                          &cache_resource->action);
2851         if (ret) {
2852                 mlx5_free(cache_resource);
2853                 return rte_flow_error_set(error, ENOMEM,
2854                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855                                           NULL, "cannot create action");
2856         }
2857         rte_atomic32_init(&cache_resource->refcnt);
2858         rte_atomic32_inc(&cache_resource->refcnt);
2859         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860                      &sh->push_vlan_action_list,
2861                      dev_flow->handle->dvh.rix_push_vlan,
2862                      cache_resource, next);
2863         dev_flow->dv.push_vlan_res = cache_resource;
2864         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865                 (void *)cache_resource,
2866                 rte_atomic32_read(&cache_resource->refcnt));
2867         return 0;
2868 }
2869 /**
2870  * Get the size of specific rte_flow_item_type hdr size
2871  *
2872  * @param[in] item_type
2873  *   Tested rte_flow_item_type.
2874  *
2875  * @return
2876  *   sizeof struct item_type, 0 if void or irrelevant.
2877  */
2878 static size_t
2879 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2880 {
2881         size_t retval;
2882
2883         switch (item_type) {
2884         case RTE_FLOW_ITEM_TYPE_ETH:
2885                 retval = sizeof(struct rte_ether_hdr);
2886                 break;
2887         case RTE_FLOW_ITEM_TYPE_VLAN:
2888                 retval = sizeof(struct rte_vlan_hdr);
2889                 break;
2890         case RTE_FLOW_ITEM_TYPE_IPV4:
2891                 retval = sizeof(struct rte_ipv4_hdr);
2892                 break;
2893         case RTE_FLOW_ITEM_TYPE_IPV6:
2894                 retval = sizeof(struct rte_ipv6_hdr);
2895                 break;
2896         case RTE_FLOW_ITEM_TYPE_UDP:
2897                 retval = sizeof(struct rte_udp_hdr);
2898                 break;
2899         case RTE_FLOW_ITEM_TYPE_TCP:
2900                 retval = sizeof(struct rte_tcp_hdr);
2901                 break;
2902         case RTE_FLOW_ITEM_TYPE_VXLAN:
2903         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2904                 retval = sizeof(struct rte_vxlan_hdr);
2905                 break;
2906         case RTE_FLOW_ITEM_TYPE_GRE:
2907         case RTE_FLOW_ITEM_TYPE_NVGRE:
2908                 retval = sizeof(struct rte_gre_hdr);
2909                 break;
2910         case RTE_FLOW_ITEM_TYPE_MPLS:
2911                 retval = sizeof(struct rte_mpls_hdr);
2912                 break;
2913         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2914         default:
2915                 retval = 0;
2916                 break;
2917         }
2918         return retval;
2919 }
2920
2921 #define MLX5_ENCAP_IPV4_VERSION         0x40
2922 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2923 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2924 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2925 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2926 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2927 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2928
2929 /**
2930  * Convert the encap action data from list of rte_flow_item to raw buffer
2931  *
2932  * @param[in] items
2933  *   Pointer to rte_flow_item objects list.
2934  * @param[out] buf
2935  *   Pointer to the output buffer.
2936  * @param[out] size
2937  *   Pointer to the output buffer size.
2938  * @param[out] error
2939  *   Pointer to the error structure.
2940  *
2941  * @return
2942  *   0 on success, a negative errno value otherwise and rte_errno is set.
2943  */
2944 static int
2945 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2946                            size_t *size, struct rte_flow_error *error)
2947 {
2948         struct rte_ether_hdr *eth = NULL;
2949         struct rte_vlan_hdr *vlan = NULL;
2950         struct rte_ipv4_hdr *ipv4 = NULL;
2951         struct rte_ipv6_hdr *ipv6 = NULL;
2952         struct rte_udp_hdr *udp = NULL;
2953         struct rte_vxlan_hdr *vxlan = NULL;
2954         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2955         struct rte_gre_hdr *gre = NULL;
2956         size_t len;
2957         size_t temp_size = 0;
2958
2959         if (!items)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION,
2962                                           NULL, "invalid empty data");
2963         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2964                 len = flow_dv_get_item_hdr_len(items->type);
2965                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2966                         return rte_flow_error_set(error, EINVAL,
2967                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2968                                                   (void *)items->type,
2969                                                   "items total size is too big"
2970                                                   " for encap action");
2971                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2972                 switch (items->type) {
2973                 case RTE_FLOW_ITEM_TYPE_ETH:
2974                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2975                         break;
2976                 case RTE_FLOW_ITEM_TYPE_VLAN:
2977                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2978                         if (!eth)
2979                                 return rte_flow_error_set(error, EINVAL,
2980                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2981                                                 (void *)items->type,
2982                                                 "eth header not found");
2983                         if (!eth->ether_type)
2984                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2985                         break;
2986                 case RTE_FLOW_ITEM_TYPE_IPV4:
2987                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2988                         if (!vlan && !eth)
2989                                 return rte_flow_error_set(error, EINVAL,
2990                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2991                                                 (void *)items->type,
2992                                                 "neither eth nor vlan"
2993                                                 " header found");
2994                         if (vlan && !vlan->eth_proto)
2995                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2996                         else if (eth && !eth->ether_type)
2997                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2998                         if (!ipv4->version_ihl)
2999                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3000                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3001                         if (!ipv4->time_to_live)
3002                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3003                         break;
3004                 case RTE_FLOW_ITEM_TYPE_IPV6:
3005                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3006                         if (!vlan && !eth)
3007                                 return rte_flow_error_set(error, EINVAL,
3008                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3009                                                 (void *)items->type,
3010                                                 "neither eth nor vlan"
3011                                                 " header found");
3012                         if (vlan && !vlan->eth_proto)
3013                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3014                         else if (eth && !eth->ether_type)
3015                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3016                         if (!ipv6->vtc_flow)
3017                                 ipv6->vtc_flow =
3018                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3019                         if (!ipv6->hop_limits)
3020                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3021                         break;
3022                 case RTE_FLOW_ITEM_TYPE_UDP:
3023                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3024                         if (!ipv4 && !ipv6)
3025                                 return rte_flow_error_set(error, EINVAL,
3026                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3027                                                 (void *)items->type,
3028                                                 "ip header not found");
3029                         if (ipv4 && !ipv4->next_proto_id)
3030                                 ipv4->next_proto_id = IPPROTO_UDP;
3031                         else if (ipv6 && !ipv6->proto)
3032                                 ipv6->proto = IPPROTO_UDP;
3033                         break;
3034                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3035                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3036                         if (!udp)
3037                                 return rte_flow_error_set(error, EINVAL,
3038                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3039                                                 (void *)items->type,
3040                                                 "udp header not found");
3041                         if (!udp->dst_port)
3042                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3043                         if (!vxlan->vx_flags)
3044                                 vxlan->vx_flags =
3045                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3046                         break;
3047                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3048                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3049                         if (!udp)
3050                                 return rte_flow_error_set(error, EINVAL,
3051                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3052                                                 (void *)items->type,
3053                                                 "udp header not found");
3054                         if (!vxlan_gpe->proto)
3055                                 return rte_flow_error_set(error, EINVAL,
3056                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3057                                                 (void *)items->type,
3058                                                 "next protocol not found");
3059                         if (!udp->dst_port)
3060                                 udp->dst_port =
3061                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3062                         if (!vxlan_gpe->vx_flags)
3063                                 vxlan_gpe->vx_flags =
3064                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3065                         break;
3066                 case RTE_FLOW_ITEM_TYPE_GRE:
3067                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3068                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3069                         if (!gre->proto)
3070                                 return rte_flow_error_set(error, EINVAL,
3071                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3072                                                 (void *)items->type,
3073                                                 "next protocol not found");
3074                         if (!ipv4 && !ipv6)
3075                                 return rte_flow_error_set(error, EINVAL,
3076                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3077                                                 (void *)items->type,
3078                                                 "ip header not found");
3079                         if (ipv4 && !ipv4->next_proto_id)
3080                                 ipv4->next_proto_id = IPPROTO_GRE;
3081                         else if (ipv6 && !ipv6->proto)
3082                                 ipv6->proto = IPPROTO_GRE;
3083                         break;
3084                 case RTE_FLOW_ITEM_TYPE_VOID:
3085                         break;
3086                 default:
3087                         return rte_flow_error_set(error, EINVAL,
3088                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3089                                                   (void *)items->type,
3090                                                   "unsupported item type");
3091                         break;
3092                 }
3093                 temp_size += len;
3094         }
3095         *size = temp_size;
3096         return 0;
3097 }
3098
3099 static int
3100 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3101 {
3102         struct rte_ether_hdr *eth = NULL;
3103         struct rte_vlan_hdr *vlan = NULL;
3104         struct rte_ipv6_hdr *ipv6 = NULL;
3105         struct rte_udp_hdr *udp = NULL;
3106         char *next_hdr;
3107         uint16_t proto;
3108
3109         eth = (struct rte_ether_hdr *)data;
3110         next_hdr = (char *)(eth + 1);
3111         proto = RTE_BE16(eth->ether_type);
3112
3113         /* VLAN skipping */
3114         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3115                 vlan = (struct rte_vlan_hdr *)next_hdr;
3116                 proto = RTE_BE16(vlan->eth_proto);
3117                 next_hdr += sizeof(struct rte_vlan_hdr);
3118         }
3119
3120         /* HW calculates IPv4 csum. no need to proceed */
3121         if (proto == RTE_ETHER_TYPE_IPV4)
3122                 return 0;
3123
3124         /* non IPv4/IPv6 header. not supported */
3125         if (proto != RTE_ETHER_TYPE_IPV6) {
3126                 return rte_flow_error_set(error, ENOTSUP,
3127                                           RTE_FLOW_ERROR_TYPE_ACTION,
3128                                           NULL, "Cannot offload non IPv4/IPv6");
3129         }
3130
3131         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3132
3133         /* ignore non UDP */
3134         if (ipv6->proto != IPPROTO_UDP)
3135                 return 0;
3136
3137         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3138         udp->dgram_cksum = 0;
3139
3140         return 0;
3141 }
3142
3143 /**
3144  * Convert L2 encap action to DV specification.
3145  *
3146  * @param[in] dev
3147  *   Pointer to rte_eth_dev structure.
3148  * @param[in] action
3149  *   Pointer to action structure.
3150  * @param[in, out] dev_flow
3151  *   Pointer to the mlx5_flow.
3152  * @param[in] transfer
3153  *   Mark if the flow is E-Switch flow.
3154  * @param[out] error
3155  *   Pointer to the error structure.
3156  *
3157  * @return
3158  *   0 on success, a negative errno value otherwise and rte_errno is set.
3159  */
3160 static int
3161 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3162                                const struct rte_flow_action *action,
3163                                struct mlx5_flow *dev_flow,
3164                                uint8_t transfer,
3165                                struct rte_flow_error *error)
3166 {
3167         const struct rte_flow_item *encap_data;
3168         const struct rte_flow_action_raw_encap *raw_encap_data;
3169         struct mlx5_flow_dv_encap_decap_resource res = {
3170                 .reformat_type =
3171                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3172                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3173                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3174         };
3175
3176         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3177                 raw_encap_data =
3178                         (const struct rte_flow_action_raw_encap *)action->conf;
3179                 res.size = raw_encap_data->size;
3180                 memcpy(res.buf, raw_encap_data->data, res.size);
3181         } else {
3182                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3183                         encap_data =
3184                                 ((const struct rte_flow_action_vxlan_encap *)
3185                                                 action->conf)->definition;
3186                 else
3187                         encap_data =
3188                                 ((const struct rte_flow_action_nvgre_encap *)
3189                                                 action->conf)->definition;
3190                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3191                                                &res.size, error))
3192                         return -rte_errno;
3193         }
3194         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3195                 return -rte_errno;
3196         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3197                 return rte_flow_error_set(error, EINVAL,
3198                                           RTE_FLOW_ERROR_TYPE_ACTION,
3199                                           NULL, "can't create L2 encap action");
3200         return 0;
3201 }
3202
3203 /**
3204  * Convert L2 decap action to DV specification.
3205  *
3206  * @param[in] dev
3207  *   Pointer to rte_eth_dev structure.
3208  * @param[in, out] dev_flow
3209  *   Pointer to the mlx5_flow.
3210  * @param[in] transfer
3211  *   Mark if the flow is E-Switch flow.
3212  * @param[out] error
3213  *   Pointer to the error structure.
3214  *
3215  * @return
3216  *   0 on success, a negative errno value otherwise and rte_errno is set.
3217  */
3218 static int
3219 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3220                                struct mlx5_flow *dev_flow,
3221                                uint8_t transfer,
3222                                struct rte_flow_error *error)
3223 {
3224         struct mlx5_flow_dv_encap_decap_resource res = {
3225                 .size = 0,
3226                 .reformat_type =
3227                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3228                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3229                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3230         };
3231
3232         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3233                 return rte_flow_error_set(error, EINVAL,
3234                                           RTE_FLOW_ERROR_TYPE_ACTION,
3235                                           NULL, "can't create L2 decap action");
3236         return 0;
3237 }
3238
3239 /**
3240  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3241  *
3242  * @param[in] dev
3243  *   Pointer to rte_eth_dev structure.
3244  * @param[in] action
3245  *   Pointer to action structure.
3246  * @param[in, out] dev_flow
3247  *   Pointer to the mlx5_flow.
3248  * @param[in] attr
3249  *   Pointer to the flow attributes.
3250  * @param[out] error
3251  *   Pointer to the error structure.
3252  *
3253  * @return
3254  *   0 on success, a negative errno value otherwise and rte_errno is set.
3255  */
3256 static int
3257 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3258                                 const struct rte_flow_action *action,
3259                                 struct mlx5_flow *dev_flow,
3260                                 const struct rte_flow_attr *attr,
3261                                 struct rte_flow_error *error)
3262 {
3263         const struct rte_flow_action_raw_encap *encap_data;
3264         struct mlx5_flow_dv_encap_decap_resource res;
3265
3266         memset(&res, 0, sizeof(res));
3267         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3268         res.size = encap_data->size;
3269         memcpy(res.buf, encap_data->data, res.size);
3270         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3271                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3272                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3273         if (attr->transfer)
3274                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3275         else
3276                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3277                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3278         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ACTION,
3281                                           NULL, "can't create encap action");
3282         return 0;
3283 }
3284
3285 /**
3286  * Create action push VLAN.
3287  *
3288  * @param[in] dev
3289  *   Pointer to rte_eth_dev structure.
3290  * @param[in] attr
3291  *   Pointer to the flow attributes.
3292  * @param[in] vlan
3293  *   Pointer to the vlan to push to the Ethernet header.
3294  * @param[in, out] dev_flow
3295  *   Pointer to the mlx5_flow.
3296  * @param[out] error
3297  *   Pointer to the error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3304                                 const struct rte_flow_attr *attr,
3305                                 const struct rte_vlan_hdr *vlan,
3306                                 struct mlx5_flow *dev_flow,
3307                                 struct rte_flow_error *error)
3308 {
3309         struct mlx5_flow_dv_push_vlan_action_resource res;
3310
3311         memset(&res, 0, sizeof(res));
3312         res.vlan_tag =
3313                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3314                                  vlan->vlan_tci);
3315         if (attr->transfer)
3316                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3317         else
3318                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3319                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3320         return flow_dv_push_vlan_action_resource_register
3321                                             (dev, &res, dev_flow, error);
3322 }
3323
3324 /**
3325  * Validate the modify-header actions.
3326  *
3327  * @param[in] action_flags
3328  *   Holds the actions detected until now.
3329  * @param[in] action
3330  *   Pointer to the modify action.
3331  * @param[out] error
3332  *   Pointer to error structure.
3333  *
3334  * @return
3335  *   0 on success, a negative errno value otherwise and rte_errno is set.
3336  */
3337 static int
3338 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3339                                    const struct rte_flow_action *action,
3340                                    struct rte_flow_error *error)
3341 {
3342         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3343                 return rte_flow_error_set(error, EINVAL,
3344                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3345                                           NULL, "action configuration not set");
3346         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347                 return rte_flow_error_set(error, EINVAL,
3348                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349                                           "can't have encap action before"
3350                                           " modify action");
3351         return 0;
3352 }
3353
3354 /**
3355  * Validate the modify-header MAC address actions.
3356  *
3357  * @param[in] action_flags
3358  *   Holds the actions detected until now.
3359  * @param[in] action
3360  *   Pointer to the modify action.
3361  * @param[in] item_flags
3362  *   Holds the items detected.
3363  * @param[out] error
3364  *   Pointer to error structure.
3365  *
3366  * @return
3367  *   0 on success, a negative errno value otherwise and rte_errno is set.
3368  */
3369 static int
3370 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3371                                    const struct rte_flow_action *action,
3372                                    const uint64_t item_flags,
3373                                    struct rte_flow_error *error)
3374 {
3375         int ret = 0;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3380                         return rte_flow_error_set(error, EINVAL,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "no L2 item in pattern");
3384         }
3385         return ret;
3386 }
3387
3388 /**
3389  * Validate the modify-header IPv4 address actions.
3390  *
3391  * @param[in] action_flags
3392  *   Holds the actions detected until now.
3393  * @param[in] action
3394  *   Pointer to the modify action.
3395  * @param[in] item_flags
3396  *   Holds the items detected.
3397  * @param[out] error
3398  *   Pointer to error structure.
3399  *
3400  * @return
3401  *   0 on success, a negative errno value otherwise and rte_errno is set.
3402  */
3403 static int
3404 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3405                                     const struct rte_flow_action *action,
3406                                     const uint64_t item_flags,
3407                                     struct rte_flow_error *error)
3408 {
3409         int ret = 0;
3410         uint64_t layer;
3411
3412         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3413         if (!ret) {
3414                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3416                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3417                 if (!(item_flags & layer))
3418                         return rte_flow_error_set(error, EINVAL,
3419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3420                                                   NULL,
3421                                                   "no ipv4 item in pattern");
3422         }
3423         return ret;
3424 }
3425
3426 /**
3427  * Validate the modify-header IPv6 address actions.
3428  *
3429  * @param[in] action_flags
3430  *   Holds the actions detected until now.
3431  * @param[in] action
3432  *   Pointer to the modify action.
3433  * @param[in] item_flags
3434  *   Holds the items detected.
3435  * @param[out] error
3436  *   Pointer to error structure.
3437  *
3438  * @return
3439  *   0 on success, a negative errno value otherwise and rte_errno is set.
3440  */
3441 static int
3442 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3443                                     const struct rte_flow_action *action,
3444                                     const uint64_t item_flags,
3445                                     struct rte_flow_error *error)
3446 {
3447         int ret = 0;
3448         uint64_t layer;
3449
3450         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3451         if (!ret) {
3452                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3454                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3455                 if (!(item_flags & layer))
3456                         return rte_flow_error_set(error, EINVAL,
3457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3458                                                   NULL,
3459                                                   "no ipv6 item in pattern");
3460         }
3461         return ret;
3462 }
3463
3464 /**
3465  * Validate the modify-header TP actions.
3466  *
3467  * @param[in] action_flags
3468  *   Holds the actions detected until now.
3469  * @param[in] action
3470  *   Pointer to the modify action.
3471  * @param[in] item_flags
3472  *   Holds the items detected.
3473  * @param[out] error
3474  *   Pointer to error structure.
3475  *
3476  * @return
3477  *   0 on success, a negative errno value otherwise and rte_errno is set.
3478  */
3479 static int
3480 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3481                                   const struct rte_flow_action *action,
3482                                   const uint64_t item_flags,
3483                                   struct rte_flow_error *error)
3484 {
3485         int ret = 0;
3486         uint64_t layer;
3487
3488         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3489         if (!ret) {
3490                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3491                                  MLX5_FLOW_LAYER_INNER_L4 :
3492                                  MLX5_FLOW_LAYER_OUTER_L4;
3493                 if (!(item_flags & layer))
3494                         return rte_flow_error_set(error, EINVAL,
3495                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3496                                                   NULL, "no transport layer "
3497                                                   "in pattern");
3498         }
3499         return ret;
3500 }
3501
3502 /**
3503  * Validate the modify-header actions of increment/decrement
3504  * TCP Sequence-number.
3505  *
3506  * @param[in] action_flags
3507  *   Holds the actions detected until now.
3508  * @param[in] action
3509  *   Pointer to the modify action.
3510  * @param[in] item_flags
3511  *   Holds the items detected.
3512  * @param[out] error
3513  *   Pointer to error structure.
3514  *
3515  * @return
3516  *   0 on success, a negative errno value otherwise and rte_errno is set.
3517  */
3518 static int
3519 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3520                                        const struct rte_flow_action *action,
3521                                        const uint64_t item_flags,
3522                                        struct rte_flow_error *error)
3523 {
3524         int ret = 0;
3525         uint64_t layer;
3526
3527         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3528         if (!ret) {
3529                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3530                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3531                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3532                 if (!(item_flags & layer))
3533                         return rte_flow_error_set(error, EINVAL,
3534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3535                                                   NULL, "no TCP item in"
3536                                                   " pattern");
3537                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3538                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3539                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3540                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3541                         return rte_flow_error_set(error, EINVAL,
3542                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3543                                                   NULL,
3544                                                   "cannot decrease and increase"
3545                                                   " TCP sequence number"
3546                                                   " at the same time");
3547         }
3548         return ret;
3549 }
3550
3551 /**
3552  * Validate the modify-header actions of increment/decrement
3553  * TCP Acknowledgment number.
3554  *
3555  * @param[in] action_flags
3556  *   Holds the actions detected until now.
3557  * @param[in] action
3558  *   Pointer to the modify action.
3559  * @param[in] item_flags
3560  *   Holds the items detected.
3561  * @param[out] error
3562  *   Pointer to error structure.
3563  *
3564  * @return
3565  *   0 on success, a negative errno value otherwise and rte_errno is set.
3566  */
3567 static int
3568 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3569                                        const struct rte_flow_action *action,
3570                                        const uint64_t item_flags,
3571                                        struct rte_flow_error *error)
3572 {
3573         int ret = 0;
3574         uint64_t layer;
3575
3576         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3577         if (!ret) {
3578                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3580                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581                 if (!(item_flags & layer))
3582                         return rte_flow_error_set(error, EINVAL,
3583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3584                                                   NULL, "no TCP item in"
3585                                                   " pattern");
3586                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3587                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3588                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3589                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3590                         return rte_flow_error_set(error, EINVAL,
3591                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3592                                                   NULL,
3593                                                   "cannot decrease and increase"
3594                                                   " TCP acknowledgment number"
3595                                                   " at the same time");
3596         }
3597         return ret;
3598 }
3599
3600 /**
3601  * Validate the modify-header TTL actions.
3602  *
3603  * @param[in] action_flags
3604  *   Holds the actions detected until now.
3605  * @param[in] action
3606  *   Pointer to the modify action.
3607  * @param[in] item_flags
3608  *   Holds the items detected.
3609  * @param[out] error
3610  *   Pointer to error structure.
3611  *
3612  * @return
3613  *   0 on success, a negative errno value otherwise and rte_errno is set.
3614  */
3615 static int
3616 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3617                                    const struct rte_flow_action *action,
3618                                    const uint64_t item_flags,
3619                                    struct rte_flow_error *error)
3620 {
3621         int ret = 0;
3622         uint64_t layer;
3623
3624         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3625         if (!ret) {
3626                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3627                                  MLX5_FLOW_LAYER_INNER_L3 :
3628                                  MLX5_FLOW_LAYER_OUTER_L3;
3629                 if (!(item_flags & layer))
3630                         return rte_flow_error_set(error, EINVAL,
3631                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3632                                                   NULL,
3633                                                   "no IP protocol in pattern");
3634         }
3635         return ret;
3636 }
3637
3638 /**
3639  * Validate jump action.
3640  *
3641  * @param[in] action
3642  *   Pointer to the jump action.
3643  * @param[in] action_flags
3644  *   Holds the actions detected until now.
3645  * @param[in] attributes
3646  *   Pointer to flow attributes
3647  * @param[in] external
3648  *   Action belongs to flow rule created by request external to PMD.
3649  * @param[out] error
3650  *   Pointer to error structure.
3651  *
3652  * @return
3653  *   0 on success, a negative errno value otherwise and rte_errno is set.
3654  */
3655 static int
3656 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3657                              uint64_t action_flags,
3658                              const struct rte_flow_attr *attributes,
3659                              bool external, struct rte_flow_error *error)
3660 {
3661         uint32_t target_group, table;
3662         int ret = 0;
3663
3664         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3665                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3666                 return rte_flow_error_set(error, EINVAL,
3667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668                                           "can't have 2 fate actions in"
3669                                           " same flow");
3670         if (action_flags & MLX5_FLOW_ACTION_METER)
3671                 return rte_flow_error_set(error, ENOTSUP,
3672                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673                                           "jump with meter not support");
3674         if (!action->conf)
3675                 return rte_flow_error_set(error, EINVAL,
3676                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3677                                           NULL, "action configuration not set");
3678         target_group =
3679                 ((const struct rte_flow_action_jump *)action->conf)->group;
3680         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3681                                        true, &table, error);
3682         if (ret)
3683                 return ret;
3684         if (attributes->group == target_group)
3685                 return rte_flow_error_set(error, EINVAL,
3686                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687                                           "target group must be other than"
3688                                           " the current flow group");
3689         return 0;
3690 }
3691
3692 /*
3693  * Validate the port_id action.
3694  *
3695  * @param[in] dev
3696  *   Pointer to rte_eth_dev structure.
3697  * @param[in] action_flags
3698  *   Bit-fields that holds the actions detected until now.
3699  * @param[in] action
3700  *   Port_id RTE action structure.
3701  * @param[in] attr
3702  *   Attributes of flow that includes this action.
3703  * @param[out] error
3704  *   Pointer to error structure.
3705  *
3706  * @return
3707  *   0 on success, a negative errno value otherwise and rte_errno is set.
3708  */
3709 static int
3710 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3711                                 uint64_t action_flags,
3712                                 const struct rte_flow_action *action,
3713                                 const struct rte_flow_attr *attr,
3714                                 struct rte_flow_error *error)
3715 {
3716         const struct rte_flow_action_port_id *port_id;
3717         struct mlx5_priv *act_priv;
3718         struct mlx5_priv *dev_priv;
3719         uint16_t port;
3720
3721         if (!attr->transfer)
3722                 return rte_flow_error_set(error, ENOTSUP,
3723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3724                                           NULL,
3725                                           "port id action is valid in transfer"
3726                                           " mode only");
3727         if (!action || !action->conf)
3728                 return rte_flow_error_set(error, ENOTSUP,
3729                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3730                                           NULL,
3731                                           "port id action parameters must be"
3732                                           " specified");
3733         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3734                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3735                 return rte_flow_error_set(error, EINVAL,
3736                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3737                                           "can have only one fate actions in"
3738                                           " a flow");
3739         dev_priv = mlx5_dev_to_eswitch_info(dev);
3740         if (!dev_priv)
3741                 return rte_flow_error_set(error, rte_errno,
3742                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3743                                           NULL,
3744                                           "failed to obtain E-Switch info");
3745         port_id = action->conf;
3746         port = port_id->original ? dev->data->port_id : port_id->id;
3747         act_priv = mlx5_port_to_eswitch_info(port, false);
3748         if (!act_priv)
3749                 return rte_flow_error_set
3750                                 (error, rte_errno,
3751                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3752                                  "failed to obtain E-Switch port id for port");
3753         if (act_priv->domain_id != dev_priv->domain_id)
3754                 return rte_flow_error_set
3755                                 (error, EINVAL,
3756                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3757                                  "port does not belong to"
3758                                  " E-Switch being configured");
3759         return 0;
3760 }
3761
3762 /**
3763  * Get the maximum number of modify header actions.
3764  *
3765  * @param dev
3766  *   Pointer to rte_eth_dev structure.
3767  * @param flags
3768  *   Flags bits to check if root level.
3769  *
3770  * @return
3771  *   Max number of modify header actions device can support.
3772  */
3773 static inline unsigned int
3774 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3775                               uint64_t flags)
3776 {
3777         /*
3778          * There's no way to directly query the max capacity from FW.
3779          * The maximal value on root table should be assumed to be supported.
3780          */
3781         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3782                 return MLX5_MAX_MODIFY_NUM;
3783         else
3784                 return MLX5_ROOT_TBL_MODIFY_NUM;
3785 }
3786
3787 /**
3788  * Validate the meter action.
3789  *
3790  * @param[in] dev
3791  *   Pointer to rte_eth_dev structure.
3792  * @param[in] action_flags
3793  *   Bit-fields that holds the actions detected until now.
3794  * @param[in] action
3795  *   Pointer to the meter action.
3796  * @param[in] attr
3797  *   Attributes of flow that includes this action.
3798  * @param[out] error
3799  *   Pointer to error structure.
3800  *
3801  * @return
3802  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3803  */
3804 static int
3805 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3806                                 uint64_t action_flags,
3807                                 const struct rte_flow_action *action,
3808                                 const struct rte_flow_attr *attr,
3809                                 struct rte_flow_error *error)
3810 {
3811         struct mlx5_priv *priv = dev->data->dev_private;
3812         const struct rte_flow_action_meter *am = action->conf;
3813         struct mlx5_flow_meter *fm;
3814
3815         if (!am)
3816                 return rte_flow_error_set(error, EINVAL,
3817                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3818                                           "meter action conf is NULL");
3819
3820         if (action_flags & MLX5_FLOW_ACTION_METER)
3821                 return rte_flow_error_set(error, ENOTSUP,
3822                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823                                           "meter chaining not support");
3824         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3825                 return rte_flow_error_set(error, ENOTSUP,
3826                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827                                           "meter with jump not support");
3828         if (!priv->mtr_en)
3829                 return rte_flow_error_set(error, ENOTSUP,
3830                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3831                                           NULL,
3832                                           "meter action not supported");
3833         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3834         if (!fm)
3835                 return rte_flow_error_set(error, EINVAL,
3836                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3837                                           "Meter not found");
3838         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3839               (!fm->ingress && !attr->ingress && attr->egress) ||
3840               (!fm->egress && !attr->egress && attr->ingress))))
3841                 return rte_flow_error_set(error, EINVAL,
3842                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3843                                           "Flow attributes are either invalid "
3844                                           "or have a conflict with current "
3845                                           "meter attributes");
3846         return 0;
3847 }
3848
3849 /**
3850  * Validate the age action.
3851  *
3852  * @param[in] action_flags
3853  *   Holds the actions detected until now.
3854  * @param[in] action
3855  *   Pointer to the age action.
3856  * @param[in] dev
3857  *   Pointer to the Ethernet device structure.
3858  * @param[out] error
3859  *   Pointer to error structure.
3860  *
3861  * @return
3862  *   0 on success, a negative errno value otherwise and rte_errno is set.
3863  */
3864 static int
3865 flow_dv_validate_action_age(uint64_t action_flags,
3866                             const struct rte_flow_action *action,
3867                             struct rte_eth_dev *dev,
3868                             struct rte_flow_error *error)
3869 {
3870         struct mlx5_priv *priv = dev->data->dev_private;
3871         const struct rte_flow_action_age *age = action->conf;
3872
3873         if (!priv->config.devx || priv->counter_fallback)
3874                 return rte_flow_error_set(error, ENOTSUP,
3875                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3876                                           NULL,
3877                                           "age action not supported");
3878         if (!(action->conf))
3879                 return rte_flow_error_set(error, EINVAL,
3880                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3881                                           "configuration cannot be null");
3882         if (age->timeout >= UINT16_MAX / 2 / 10)
3883                 return rte_flow_error_set(error, ENOTSUP,
3884                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3885                                           "Max age time: 3275 seconds");
3886         if (action_flags & MLX5_FLOW_ACTION_AGE)
3887                 return rte_flow_error_set(error, EINVAL,
3888                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3889                                           "Duplicate age ctions set");
3890         return 0;
3891 }
3892
3893 /**
3894  * Validate the modify-header IPv4 DSCP actions.
3895  *
3896  * @param[in] action_flags
3897  *   Holds the actions detected until now.
3898  * @param[in] action
3899  *   Pointer to the modify action.
3900  * @param[in] item_flags
3901  *   Holds the items detected.
3902  * @param[out] error
3903  *   Pointer to error structure.
3904  *
3905  * @return
3906  *   0 on success, a negative errno value otherwise and rte_errno is set.
3907  */
3908 static int
3909 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3910                                          const struct rte_flow_action *action,
3911                                          const uint64_t item_flags,
3912                                          struct rte_flow_error *error)
3913 {
3914         int ret = 0;
3915
3916         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3917         if (!ret) {
3918                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3919                         return rte_flow_error_set(error, EINVAL,
3920                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3921                                                   NULL,
3922                                                   "no ipv4 item in pattern");
3923         }
3924         return ret;
3925 }
3926
3927 /**
3928  * Validate the modify-header IPv6 DSCP actions.
3929  *
3930  * @param[in] action_flags
3931  *   Holds the actions detected until now.
3932  * @param[in] action
3933  *   Pointer to the modify action.
3934  * @param[in] item_flags
3935  *   Holds the items detected.
3936  * @param[out] error
3937  *   Pointer to error structure.
3938  *
3939  * @return
3940  *   0 on success, a negative errno value otherwise and rte_errno is set.
3941  */
3942 static int
3943 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3944                                          const struct rte_flow_action *action,
3945                                          const uint64_t item_flags,
3946                                          struct rte_flow_error *error)
3947 {
3948         int ret = 0;
3949
3950         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3951         if (!ret) {
3952                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3953                         return rte_flow_error_set(error, EINVAL,
3954                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3955                                                   NULL,
3956                                                   "no ipv6 item in pattern");
3957         }
3958         return ret;
3959 }
3960
3961 /**
3962  * Find existing modify-header resource or create and register a new one.
3963  *
3964  * @param dev[in, out]
3965  *   Pointer to rte_eth_dev structure.
3966  * @param[in, out] resource
3967  *   Pointer to modify-header resource.
3968  * @parm[in, out] dev_flow
3969  *   Pointer to the dev_flow.
3970  * @param[out] error
3971  *   pointer to error structure.
3972  *
3973  * @return
3974  *   0 on success otherwise -errno and errno is set.
3975  */
3976 static int
3977 flow_dv_modify_hdr_resource_register
3978                         (struct rte_eth_dev *dev,
3979                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3980                          struct mlx5_flow *dev_flow,
3981                          struct rte_flow_error *error)
3982 {
3983         struct mlx5_priv *priv = dev->data->dev_private;
3984         struct mlx5_dev_ctx_shared *sh = priv->sh;
3985         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3986         struct mlx5dv_dr_domain *ns;
3987         uint32_t actions_len;
3988         int ret;
3989
3990         resource->flags = dev_flow->dv.group ? 0 :
3991                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3992         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3993                                     resource->flags))
3994                 return rte_flow_error_set(error, EOVERFLOW,
3995                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996                                           "too many modify header items");
3997         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3998                 ns = sh->fdb_domain;
3999         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4000                 ns = sh->tx_domain;
4001         else
4002                 ns = sh->rx_domain;
4003         /* Lookup a matching resource from cache. */
4004         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4005         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4006                 if (resource->ft_type == cache_resource->ft_type &&
4007                     resource->actions_num == cache_resource->actions_num &&
4008                     resource->flags == cache_resource->flags &&
4009                     !memcmp((const void *)resource->actions,
4010                             (const void *)cache_resource->actions,
4011                             actions_len)) {
4012                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4013                                 (void *)cache_resource,
4014                                 rte_atomic32_read(&cache_resource->refcnt));
4015                         rte_atomic32_inc(&cache_resource->refcnt);
4016                         dev_flow->handle->dvh.modify_hdr = cache_resource;
4017                         return 0;
4018                 }
4019         }
4020         /* Register new modify-header resource. */
4021         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4022                                     sizeof(*cache_resource) + actions_len, 0,
4023                                     SOCKET_ID_ANY);
4024         if (!cache_resource)
4025                 return rte_flow_error_set(error, ENOMEM,
4026                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4027                                           "cannot allocate resource memory");
4028         *cache_resource = *resource;
4029         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4030         ret = mlx5_flow_os_create_flow_action_modify_header
4031                                         (sh->ctx, ns, cache_resource,
4032                                          actions_len, &cache_resource->action);
4033         if (ret) {
4034                 mlx5_free(cache_resource);
4035                 return rte_flow_error_set(error, ENOMEM,
4036                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4037                                           NULL, "cannot create action");
4038         }
4039         rte_atomic32_init(&cache_resource->refcnt);
4040         rte_atomic32_inc(&cache_resource->refcnt);
4041         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4042         dev_flow->handle->dvh.modify_hdr = cache_resource;
4043         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4044                 (void *)cache_resource,
4045                 rte_atomic32_read(&cache_resource->refcnt));
4046         return 0;
4047 }
4048
4049 /**
4050  * Get DV flow counter by index.
4051  *
4052  * @param[in] dev
4053  *   Pointer to the Ethernet device structure.
4054  * @param[in] idx
4055  *   mlx5 flow counter index in the container.
4056  * @param[out] ppool
4057  *   mlx5 flow counter pool in the container,
4058  *
4059  * @return
4060  *   Pointer to the counter, NULL otherwise.
4061  */
4062 static struct mlx5_flow_counter *
4063 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4064                            uint32_t idx,
4065                            struct mlx5_flow_counter_pool **ppool)
4066 {
4067         struct mlx5_priv *priv = dev->data->dev_private;
4068         struct mlx5_pools_container *cont;
4069         struct mlx5_flow_counter_pool *pool;
4070         uint32_t batch = 0, age = 0;
4071
4072         idx--;
4073         age = MLX_CNT_IS_AGE(idx);
4074         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4075         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4076                 idx -= MLX5_CNT_BATCH_OFFSET;
4077                 batch = 1;
4078         }
4079         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4080         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4081         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4082         MLX5_ASSERT(pool);
4083         if (ppool)
4084                 *ppool = pool;
4085         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4086 }
4087
4088 /**
4089  * Check the devx counter belongs to the pool.
4090  *
4091  * @param[in] pool
4092  *   Pointer to the counter pool.
4093  * @param[in] id
4094  *   The counter devx ID.
4095  *
4096  * @return
4097  *   True if counter belongs to the pool, false otherwise.
4098  */
4099 static bool
4100 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4101 {
4102         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4103                    MLX5_COUNTERS_PER_POOL;
4104
4105         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4106                 return true;
4107         return false;
4108 }
4109
4110 /**
4111  * Get a pool by devx counter ID.
4112  *
4113  * @param[in] cont
4114  *   Pointer to the counter container.
4115  * @param[in] id
4116  *   The counter devx ID.
4117  *
4118  * @return
4119  *   The counter pool pointer if exists, NULL otherwise,
4120  */
4121 static struct mlx5_flow_counter_pool *
4122 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4123 {
4124         uint32_t i;
4125
4126         /* Check last used pool. */
4127         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4128             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4129                 return cont->pools[cont->last_pool_idx];
4130         /* ID out of range means no suitable pool in the container. */
4131         if (id > cont->max_id || id < cont->min_id)
4132                 return NULL;
4133         /*
4134          * Find the pool from the end of the container, since mostly counter
4135          * ID is sequence increasing, and the last pool should be the needed
4136          * one.
4137          */
4138         i = rte_atomic16_read(&cont->n_valid);
4139         while (i--) {
4140                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4141
4142                 if (flow_dv_is_counter_in_pool(pool, id))
4143                         return pool;
4144         }
4145         return NULL;
4146 }
4147
4148 /**
4149  * Allocate a new memory for the counter values wrapped by all the needed
4150  * management.
4151  *
4152  * @param[in] dev
4153  *   Pointer to the Ethernet device structure.
4154  * @param[in] raws_n
4155  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4156  *
4157  * @return
4158  *   The new memory management pointer on success, otherwise NULL and rte_errno
4159  *   is set.
4160  */
4161 static struct mlx5_counter_stats_mem_mng *
4162 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4163 {
4164         struct mlx5_priv *priv = dev->data->dev_private;
4165         struct mlx5_dev_ctx_shared *sh = priv->sh;
4166         struct mlx5_devx_mkey_attr mkey_attr;
4167         struct mlx5_counter_stats_mem_mng *mem_mng;
4168         volatile struct flow_counter_stats *raw_data;
4169         int size = (sizeof(struct flow_counter_stats) *
4170                         MLX5_COUNTERS_PER_POOL +
4171                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4172                         sizeof(struct mlx5_counter_stats_mem_mng);
4173         size_t pgsize = rte_mem_page_size();
4174         if (pgsize == (size_t)-1) {
4175                 DRV_LOG(ERR, "Failed to get mem page size");
4176                 rte_errno = ENOMEM;
4177                 return NULL;
4178         }
4179         uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4180                                   SOCKET_ID_ANY);
4181         int i;
4182
4183         if (!mem) {
4184                 rte_errno = ENOMEM;
4185                 return NULL;
4186         }
4187         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4188         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4189         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4190                                                  IBV_ACCESS_LOCAL_WRITE);
4191         if (!mem_mng->umem) {
4192                 rte_errno = errno;
4193                 mlx5_free(mem);
4194                 return NULL;
4195         }
4196         mkey_attr.addr = (uintptr_t)mem;
4197         mkey_attr.size = size;
4198         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4199         mkey_attr.pd = sh->pdn;
4200         mkey_attr.log_entity_size = 0;
4201         mkey_attr.pg_access = 0;
4202         mkey_attr.klm_array = NULL;
4203         mkey_attr.klm_num = 0;
4204         if (priv->config.hca_attr.relaxed_ordering_write &&
4205                 priv->config.hca_attr.relaxed_ordering_read  &&
4206                 !haswell_broadwell_cpu)
4207                 mkey_attr.relaxed_ordering = 1;
4208         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4209         if (!mem_mng->dm) {
4210                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4211                 rte_errno = errno;
4212                 mlx5_free(mem);
4213                 return NULL;
4214         }
4215         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4216         raw_data = (volatile struct flow_counter_stats *)mem;
4217         for (i = 0; i < raws_n; ++i) {
4218                 mem_mng->raws[i].mem_mng = mem_mng;
4219                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4220         }
4221         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4222         return mem_mng;
4223 }
4224
4225 /**
4226  * Resize a counter container.
4227  *
4228  * @param[in] dev
4229  *   Pointer to the Ethernet device structure.
4230  * @param[in] batch
4231  *   Whether the pool is for counter that was allocated by batch command.
4232  * @param[in] age
4233  *   Whether the pool is for Aging counter.
4234  *
4235  * @return
4236  *   0 on success, otherwise negative errno value and rte_errno is set.
4237  */
4238 static int
4239 flow_dv_container_resize(struct rte_eth_dev *dev,
4240                                 uint32_t batch, uint32_t age)
4241 {
4242         struct mlx5_priv *priv = dev->data->dev_private;
4243         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4244                                                                age);
4245         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4246         void *old_pools = cont->pools;
4247         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4248         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4249         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4250
4251         if (!pools) {
4252                 rte_errno = ENOMEM;
4253                 return -ENOMEM;
4254         }
4255         if (old_pools)
4256                 memcpy(pools, old_pools, cont->n *
4257                                        sizeof(struct mlx5_flow_counter_pool *));
4258         /*
4259          * Fallback mode query the counter directly, no background query
4260          * resources are needed.
4261          */
4262         if (!priv->counter_fallback) {
4263                 int i;
4264
4265                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4266                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4267                 if (!mem_mng) {
4268                         mlx5_free(pools);
4269                         return -ENOMEM;
4270                 }
4271                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4272                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4273                                          mem_mng->raws +
4274                                          MLX5_CNT_CONTAINER_RESIZE +
4275                                          i, next);
4276         }
4277         rte_spinlock_lock(&cont->resize_sl);
4278         cont->n = resize;
4279         cont->mem_mng = mem_mng;
4280         cont->pools = pools;
4281         rte_spinlock_unlock(&cont->resize_sl);
4282         if (old_pools)
4283                 mlx5_free(old_pools);
4284         return 0;
4285 }
4286
4287 /**
4288  * Query a devx flow counter.
4289  *
4290  * @param[in] dev
4291  *   Pointer to the Ethernet device structure.
4292  * @param[in] cnt
4293  *   Index to the flow counter.
4294  * @param[out] pkts
4295  *   The statistics value of packets.
4296  * @param[out] bytes
4297  *   The statistics value of bytes.
4298  *
4299  * @return
4300  *   0 on success, otherwise a negative errno value and rte_errno is set.
4301  */
4302 static inline int
4303 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4304                      uint64_t *bytes)
4305 {
4306         struct mlx5_priv *priv = dev->data->dev_private;
4307         struct mlx5_flow_counter_pool *pool = NULL;
4308         struct mlx5_flow_counter *cnt;
4309         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4310         int offset;
4311
4312         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4313         MLX5_ASSERT(pool);
4314         if (counter < MLX5_CNT_BATCH_OFFSET) {
4315                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4316                 if (priv->counter_fallback)
4317                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4318                                         0, pkts, bytes, 0, NULL, NULL, 0);
4319         }
4320
4321         rte_spinlock_lock(&pool->sl);
4322         /*
4323          * The single counters allocation may allocate smaller ID than the
4324          * current allocated in parallel to the host reading.
4325          * In this case the new counter values must be reported as 0.
4326          */
4327         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4328                 *pkts = 0;
4329                 *bytes = 0;
4330         } else {
4331                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4332                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4333                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4334         }
4335         rte_spinlock_unlock(&pool->sl);
4336         return 0;
4337 }
4338
4339 /**
4340  * Create and initialize a new counter pool.
4341  *
4342  * @param[in] dev
4343  *   Pointer to the Ethernet device structure.
4344  * @param[out] dcs
4345  *   The devX counter handle.
4346  * @param[in] batch
4347  *   Whether the pool is for counter that was allocated by batch command.
4348  * @param[in] age
4349  *   Whether the pool is for counter that was allocated for aging.
4350  * @param[in/out] cont_cur
4351  *   Pointer to the container pointer, it will be update in pool resize.
4352  *
4353  * @return
4354  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4355  */
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4358                     uint32_t batch, uint32_t age)
4359 {
4360         struct mlx5_priv *priv = dev->data->dev_private;
4361         struct mlx5_flow_counter_pool *pool;
4362         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4363                                                                age);
4364         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4365         uint32_t size = sizeof(*pool);
4366
4367         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4368                 return NULL;
4369         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4370         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4371         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4372         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4373         if (!pool) {
4374                 rte_errno = ENOMEM;
4375                 return NULL;
4376         }
4377         pool->min_dcs = dcs;
4378         if (!priv->counter_fallback)
4379                 pool->raw = cont->mem_mng->raws + n_valid %
4380                                                       MLX5_CNT_CONTAINER_RESIZE;
4381         pool->raw_hw = NULL;
4382         pool->type = 0;
4383         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4384         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4385         pool->query_gen = 0;
4386         rte_spinlock_init(&pool->sl);
4387         TAILQ_INIT(&pool->counters[0]);
4388         TAILQ_INIT(&pool->counters[1]);
4389         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4390         pool->index = n_valid;
4391         cont->pools[n_valid] = pool;
4392         if (!batch) {
4393                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4394
4395                 if (base < cont->min_id)
4396                         cont->min_id = base;
4397                 if (base > cont->max_id)
4398                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4399                 cont->last_pool_idx = pool->index;
4400         }
4401         /* Pool initialization must be updated before host thread access. */
4402         rte_cio_wmb();
4403         rte_atomic16_add(&cont->n_valid, 1);
4404         return pool;
4405 }
4406
4407 /**
4408  * Restore skipped counters in the pool.
4409  *
4410  * As counter pool query requires the first counter dcs
4411  * ID start with 4 alinged, if the pool counters with
4412  * min_dcs ID are not aligned with 4, the counters will
4413  * be skipped.
4414  * Once other min_dcs ID less than these skipped counter
4415  * dcs ID appears, the skipped counters will be safe to
4416  * use.
4417  * Should be called when min_dcs is updated.
4418  *
4419  * @param[in] pool
4420  *   Current counter pool.
4421  * @param[in] last_min_dcs
4422  *   Last min_dcs.
4423  */
4424 static void
4425 flow_dv_counter_restore(struct mlx5_flow_counter_pool *pool,
4426                         struct mlx5_devx_obj *last_min_dcs)
4427 {
4428         struct mlx5_flow_counter_ext *cnt_ext;
4429         uint32_t offset, new_offset;
4430         uint32_t skip_cnt = 0;
4431         uint32_t i;
4432
4433         if (!pool->skip_cnt)
4434                 return;
4435         /*
4436          * If last min_dcs is not valid. The skipped counter may even after
4437          * last min_dcs, set the offset to the whole pool.
4438          */
4439         if (last_min_dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4440                 offset = MLX5_COUNTERS_PER_POOL;
4441         else
4442                 offset = last_min_dcs->id % MLX5_COUNTERS_PER_POOL;
4443         new_offset = pool->min_dcs->id % MLX5_COUNTERS_PER_POOL;
4444         /*
4445          * Check the counters from 1 to the last_min_dcs range. Counters
4446          * before new min_dcs indicates pool still has skipped counters.
4447          * Counters be skipped after new min_dcs will be ready to use.
4448          * Offset 0 counter must be empty or min_dcs, start from 1.
4449          */
4450         for (i = 1; i < offset; i++) {
4451                 cnt_ext = MLX5_GET_POOL_CNT_EXT(pool, i);
4452                 if (cnt_ext->skipped) {
4453                         if (i > new_offset) {
4454                                 cnt_ext->skipped = 0;
4455                                 TAILQ_INSERT_TAIL
4456                                         (&pool->counters[pool->query_gen],
4457                                          MLX5_POOL_GET_CNT(pool, i), next);
4458                         } else {
4459                                 skip_cnt++;
4460                         }
4461                 }
4462         }
4463         if (!skip_cnt)
4464                 pool->skip_cnt = 0;
4465 }
4466
4467 /**
4468  * Prepare a new counter and/or a new counter pool.
4469  *
4470  * @param[in] dev
4471  *   Pointer to the Ethernet device structure.
4472  * @param[out] cnt_free
4473  *   Where to put the pointer of a new counter.
4474  * @param[in] batch
4475  *   Whether the pool is for counter that was allocated by batch command.
4476  * @param[in] age
4477  *   Whether the pool is for counter that was allocated for aging.
4478  *
4479  * @return
4480  *   The counter pool pointer and @p cnt_free is set on success,
4481  *   NULL otherwise and rte_errno is set.
4482  */
4483 static struct mlx5_flow_counter_pool *
4484 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4485                              struct mlx5_flow_counter **cnt_free,
4486                              uint32_t batch, uint32_t age)
4487 {
4488         struct mlx5_priv *priv = dev->data->dev_private;
4489         struct mlx5_pools_container *cont;
4490         struct mlx5_flow_counter_pool *pool;
4491         struct mlx5_counters tmp_tq;
4492         struct mlx5_devx_obj *last_min_dcs;
4493         struct mlx5_devx_obj *dcs = NULL;
4494         struct mlx5_flow_counter *cnt;
4495         uint32_t add2other;
4496         uint32_t i;
4497
4498         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4499         if (!batch) {
4500 retry:
4501                 add2other = 0;
4502                 /* bulk_bitmap must be 0 for single counter allocation. */
4503                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4504                 if (!dcs)
4505                         return NULL;
4506                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4507                 /* Check if counter belongs to exist pool ID range. */
4508                 if (!pool) {
4509                         pool = flow_dv_find_pool_by_id
4510                                (MLX5_CNT_CONTAINER
4511                                (priv->sh, batch, (age ^ 0x1)), dcs->id);
4512                         /*
4513                          * Pool eixsts, counter will be added to the other
4514                          * container, need to reallocate it later.
4515                          */
4516                         if (pool) {
4517                                 add2other = 1;
4518                         } else {
4519                                 pool = flow_dv_pool_create(dev, dcs, batch,
4520                                                            age);
4521                                 if (!pool) {
4522                                         mlx5_devx_cmd_destroy(dcs);
4523                                         return NULL;
4524                                 }
4525                         }
4526                 }
4527                 if ((dcs->id < pool->min_dcs->id ||
4528                     pool->min_dcs->id &
4529                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1)) &&
4530                     !(dcs->id & (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))) {
4531                         /*
4532                          * Update the pool min_dcs only if current dcs is
4533                          * valid and exist min_dcs is not valid or greater
4534                          * than new dcs.
4535                          */
4536                         last_min_dcs = pool->min_dcs;
4537                         rte_atomic64_set(&pool->a64_dcs,
4538                                          (int64_t)(uintptr_t)dcs);
4539                         /*
4540                          * Restore any skipped counters if the new min_dcs
4541                          * ID is smaller or min_dcs is not valid.
4542                          */
4543                         if (dcs->id < last_min_dcs->id ||
4544                             last_min_dcs->id &
4545                             (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1))
4546                                 flow_dv_counter_restore(pool, last_min_dcs);
4547                 }
4548                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4549                 cnt = MLX5_POOL_GET_CNT(pool, i);
4550                 cnt->pool = pool;
4551                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4552                 /*
4553                  * If min_dcs is not valid, it means the new allocated dcs
4554                  * also fail to become the valid min_dcs, just skip it.
4555                  * Or if min_dcs is valid, and new dcs ID is smaller than
4556                  * min_dcs, but not become the min_dcs, also skip it.
4557                  */
4558                 if (pool->min_dcs->id &
4559                     (MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT - 1) ||
4560                     dcs->id < pool->min_dcs->id) {
4561                         MLX5_GET_POOL_CNT_EXT(pool, i)->skipped = 1;
4562                         pool->skip_cnt = 1;
4563                         goto retry;
4564                 }
4565                 if (add2other) {
4566                         TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4567                                           cnt, next);
4568                         goto retry;
4569                 }
4570                 *cnt_free = cnt;
4571                 return pool;
4572         }
4573         /* bulk_bitmap is in 128 counters units. */
4574         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4575                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4576         if (!dcs) {
4577                 rte_errno = ENODATA;
4578                 return NULL;
4579         }
4580         pool = flow_dv_pool_create(dev, dcs, batch, age);
4581         if (!pool) {
4582                 mlx5_devx_cmd_destroy(dcs);
4583                 return NULL;
4584         }
4585         TAILQ_INIT(&tmp_tq);
4586         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4587                 cnt = MLX5_POOL_GET_CNT(pool, i);
4588                 cnt->pool = pool;
4589                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4590         }
4591         rte_spinlock_lock(&cont->csl);
4592         TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4593         rte_spinlock_unlock(&cont->csl);
4594         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4595         (*cnt_free)->pool = pool;
4596         return pool;
4597 }
4598
4599 /**
4600  * Search for existed shared counter.
4601  *
4602  * @param[in] dev
4603  *   Pointer to the Ethernet device structure.
4604  * @param[in] id
4605  *   The shared counter ID to search.
4606  * @param[out] ppool
4607  *   mlx5 flow counter pool in the container,
4608  *
4609  * @return
4610  *   NULL if not existed, otherwise pointer to the shared extend counter.
4611  */
4612 static struct mlx5_flow_counter_ext *
4613 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4614                               struct mlx5_flow_counter_pool **ppool)
4615 {
4616         struct mlx5_priv *priv = dev->data->dev_private;
4617         union mlx5_l3t_data data;
4618         uint32_t cnt_idx;
4619
4620         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4621                 return NULL;
4622         cnt_idx = data.dword;
4623         /*
4624          * Shared counters don't have age info. The counter extend is after
4625          * the counter datat structure.
4626          */
4627         return (struct mlx5_flow_counter_ext *)
4628                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4629 }
4630
4631 /**
4632  * Allocate a flow counter.
4633  *
4634  * @param[in] dev
4635  *   Pointer to the Ethernet device structure.
4636  * @param[in] shared
4637  *   Indicate if this counter is shared with other flows.
4638  * @param[in] id
4639  *   Counter identifier.
4640  * @param[in] group
4641  *   Counter flow group.
4642  * @param[in] age
4643  *   Whether the counter was allocated for aging.
4644  *
4645  * @return
4646  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4647  */
4648 static uint32_t
4649 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4650                       uint16_t group, uint32_t age)
4651 {
4652         struct mlx5_priv *priv = dev->data->dev_private;
4653         struct mlx5_flow_counter_pool *pool = NULL;
4654         struct mlx5_flow_counter *cnt_free = NULL;
4655         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4656         /*
4657          * Currently group 0 flow counter cannot be assigned to a flow if it is
4658          * not the first one in the batch counter allocation, so it is better
4659          * to allocate counters one by one for these flows in a separate
4660          * container.
4661          * A counter can be shared between different groups so need to take
4662          * shared counters from the single container.
4663          */
4664         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4665         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4666                                                                age);
4667         uint32_t cnt_idx;
4668
4669         if (!priv->config.devx) {
4670                 rte_errno = ENOTSUP;
4671                 return 0;
4672         }
4673         if (shared) {
4674                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4675                 if (cnt_ext) {
4676                         if (cnt_ext->ref_cnt + 1 == 0) {
4677                                 rte_errno = E2BIG;
4678                                 return 0;
4679                         }
4680                         cnt_ext->ref_cnt++;
4681                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4682                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4683                                   + 1;
4684                         return cnt_idx;
4685                 }
4686         }
4687         /* Get free counters from container. */
4688         rte_spinlock_lock(&cont->csl);
4689         cnt_free = TAILQ_FIRST(&cont->counters);
4690         if (cnt_free)
4691                 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4692         rte_spinlock_unlock(&cont->csl);
4693         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4694                                                        batch, age))
4695                 goto err;
4696         pool = cnt_free->pool;
4697         if (!batch)
4698                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4699         /* Create a DV counter action only in the first time usage. */
4700         if (!cnt_free->action) {
4701                 uint16_t offset;
4702                 struct mlx5_devx_obj *dcs;
4703                 int ret;
4704
4705                 if (batch) {
4706                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4707                         dcs = pool->min_dcs;
4708                 } else {
4709                         offset = 0;
4710                         dcs = cnt_ext->dcs;
4711                 }
4712                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4713                                                             &cnt_free->action);
4714                 if (ret) {
4715                         rte_errno = errno;
4716                         goto err;
4717                 }
4718         }
4719         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4720                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4721         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4722         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4723         /* Update the counter reset values. */
4724         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4725                                  &cnt_free->bytes))
4726                 goto err;
4727         if (cnt_ext) {
4728                 cnt_ext->shared = shared;
4729                 cnt_ext->ref_cnt = 1;
4730                 cnt_ext->id = id;
4731                 if (shared) {
4732                         union mlx5_l3t_data data;
4733
4734                         data.dword = cnt_idx;
4735                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4736                                 return 0;
4737                 }
4738         }
4739         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4740                 /* Start the asynchronous batch query by the host thread. */
4741                 mlx5_set_query_alarm(priv->sh);
4742         return cnt_idx;
4743 err:
4744         if (cnt_free) {
4745                 cnt_free->pool = pool;
4746                 rte_spinlock_lock(&cont->csl);
4747                 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4748                 rte_spinlock_unlock(&cont->csl);
4749         }
4750         return 0;
4751 }
4752
4753 /**
4754  * Get age param from counter index.
4755  *
4756  * @param[in] dev
4757  *   Pointer to the Ethernet device structure.
4758  * @param[in] counter
4759  *   Index to the counter handler.
4760  *
4761  * @return
4762  *   The aging parameter specified for the counter index.
4763  */
4764 static struct mlx5_age_param*
4765 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4766                                 uint32_t counter)
4767 {
4768         struct mlx5_flow_counter *cnt;
4769         struct mlx5_flow_counter_pool *pool = NULL;
4770
4771         flow_dv_counter_get_by_idx(dev, counter, &pool);
4772         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4773         cnt = MLX5_POOL_GET_CNT(pool, counter);
4774         return MLX5_CNT_TO_AGE(cnt);
4775 }
4776
4777 /**
4778  * Remove a flow counter from aged counter list.
4779  *
4780  * @param[in] dev
4781  *   Pointer to the Ethernet device structure.
4782  * @param[in] counter
4783  *   Index to the counter handler.
4784  * @param[in] cnt
4785  *   Pointer to the counter handler.
4786  */
4787 static void
4788 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4789                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4790 {
4791         struct mlx5_age_info *age_info;
4792         struct mlx5_age_param *age_param;
4793         struct mlx5_priv *priv = dev->data->dev_private;
4794
4795         age_info = GET_PORT_AGE_INFO(priv);
4796         age_param = flow_dv_counter_idx_get_age(dev, counter);
4797         if (rte_atomic16_cmpset((volatile uint16_t *)
4798                         &age_param->state,
4799                         AGE_CANDIDATE, AGE_FREE)
4800                         != AGE_CANDIDATE) {
4801                 /**
4802                  * We need the lock even it is age timeout,
4803                  * since counter may still in process.
4804                  */
4805                 rte_spinlock_lock(&age_info->aged_sl);
4806                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4807                 rte_spinlock_unlock(&age_info->aged_sl);
4808         }
4809         rte_atomic16_set(&age_param->state, AGE_FREE);
4810 }
4811 /**
4812  * Release a flow counter.
4813  *
4814  * @param[in] dev
4815  *   Pointer to the Ethernet device structure.
4816  * @param[in] counter
4817  *   Index to the counter handler.
4818  */
4819 static void
4820 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4821 {
4822         struct mlx5_priv *priv = dev->data->dev_private;
4823         struct mlx5_flow_counter_pool *pool = NULL;
4824         struct mlx5_flow_counter *cnt;
4825         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4826
4827         if (!counter)
4828                 return;
4829         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4830         MLX5_ASSERT(pool);
4831         if (counter < MLX5_CNT_BATCH_OFFSET) {
4832                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4833                 if (cnt_ext) {
4834                         if (--cnt_ext->ref_cnt)
4835                                 return;
4836                         if (cnt_ext->shared)
4837                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4838                                                      cnt_ext->id);
4839                 }
4840         }
4841         if (IS_AGE_POOL(pool))
4842                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4843         cnt->pool = pool;
4844         /*
4845          * Put the counter back to list to be updated in none fallback mode.
4846          * Currently, we are using two list alternately, while one is in query,
4847          * add the freed counter to the other list based on the pool query_gen
4848          * value. After query finishes, add counter the list to the global
4849          * container counter list. The list changes while query starts. In
4850          * this case, lock will not be needed as query callback and release
4851          * function both operate with the different list.
4852          *
4853          */
4854         if (!priv->counter_fallback)
4855                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4856         else
4857                 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4858                                   (priv->sh, 0, 0))->counters),
4859                                   cnt, next);
4860 }
4861
4862 /**
4863  * Verify the @p attributes will be correctly understood by the NIC and store
4864  * them in the @p flow if everything is correct.
4865  *
4866  * @param[in] dev
4867  *   Pointer to dev struct.
4868  * @param[in] attributes
4869  *   Pointer to flow attributes
4870  * @param[in] external
4871  *   This flow rule is created by request external to PMD.
4872  * @param[out] error
4873  *   Pointer to error structure.
4874  *
4875  * @return
4876  *   - 0 on success and non root table.
4877  *   - 1 on success and root table.
4878  *   - a negative errno value otherwise and rte_errno is set.
4879  */
4880 static int
4881 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4882                             const struct rte_flow_attr *attributes,
4883                             bool external __rte_unused,
4884                             struct rte_flow_error *error)
4885 {
4886         struct mlx5_priv *priv = dev->data->dev_private;
4887         uint32_t priority_max = priv->config.flow_prio - 1;
4888         int ret = 0;
4889
4890 #ifndef HAVE_MLX5DV_DR
4891         if (attributes->group)
4892                 return rte_flow_error_set(error, ENOTSUP,
4893                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4894                                           NULL,
4895                                           "groups are not supported");
4896 #else
4897         uint32_t table = 0;
4898
4899         ret = mlx5_flow_group_to_table(attributes, external,
4900                                        attributes->group, !!priv->fdb_def_rule,
4901                                        &table, error);
4902         if (ret)
4903                 return ret;
4904         if (!table)
4905                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4906 #endif
4907         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4908             attributes->priority >= priority_max)
4909                 return rte_flow_error_set(error, ENOTSUP,
4910                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4911                                           NULL,
4912                                           "priority out of range");
4913         if (attributes->transfer) {
4914                 if (!priv->config.dv_esw_en)
4915                         return rte_flow_error_set
4916                                 (error, ENOTSUP,
4917                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4918                                  "E-Switch dr is not supported");
4919                 if (!(priv->representor || priv->master))
4920                         return rte_flow_error_set
4921                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4922                                  NULL, "E-Switch configuration can only be"
4923                                  " done by a master or a representor device");
4924                 if (attributes->egress)
4925                         return rte_flow_error_set
4926                                 (error, ENOTSUP,
4927                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4928                                  "egress is not supported");
4929         }
4930         if (!(attributes->egress ^ attributes->ingress))
4931                 return rte_flow_error_set(error, ENOTSUP,
4932                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4933                                           "must specify exactly one of "
4934                                           "ingress or egress");
4935         return ret;
4936 }
4937
4938 /**
4939  * Internal validation function. For validating both actions and items.
4940  *
4941  * @param[in] dev
4942  *   Pointer to the rte_eth_dev structure.
4943  * @param[in] attr
4944  *   Pointer to the flow attributes.
4945  * @param[in] items
4946  *   Pointer to the list of items.
4947  * @param[in] actions
4948  *   Pointer to the list of actions.
4949  * @param[in] external
4950  *   This flow rule is created by request external to PMD.
4951  * @param[in] hairpin
4952  *   Number of hairpin TX actions, 0 means classic flow.
4953  * @param[out] error
4954  *   Pointer to the error structure.
4955  *
4956  * @return
4957  *   0 on success, a negative errno value otherwise and rte_errno is set.
4958  */
4959 static int
4960 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4961                  const struct rte_flow_item items[],
4962                  const struct rte_flow_action actions[],
4963                  bool external, int hairpin, struct rte_flow_error *error)
4964 {
4965         int ret;
4966         uint64_t action_flags = 0;
4967         uint64_t item_flags = 0;
4968         uint64_t last_item = 0;
4969         uint8_t next_protocol = 0xff;
4970         uint16_t ether_type = 0;
4971         int actions_n = 0;
4972         uint8_t item_ipv6_proto = 0;
4973         const struct rte_flow_item *gre_item = NULL;
4974         const struct rte_flow_action_raw_decap *decap;
4975         const struct rte_flow_action_raw_encap *encap;
4976         const struct rte_flow_action_rss *rss;
4977         const struct rte_flow_item_tcp nic_tcp_mask = {
4978                 .hdr = {
4979                         .tcp_flags = 0xFF,
4980                         .src_port = RTE_BE16(UINT16_MAX),
4981                         .dst_port = RTE_BE16(UINT16_MAX),
4982                 }
4983         };
4984         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4985                 .hdr = {
4986                         .src_addr = RTE_BE32(0xffffffff),
4987                         .dst_addr = RTE_BE32(0xffffffff),
4988                         .type_of_service = 0xff,
4989                         .next_proto_id = 0xff,
4990                         .time_to_live = 0xff,
4991                 },
4992         };
4993         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4994                 .hdr = {
4995                         .src_addr =
4996                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4997                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4998                         .dst_addr =
4999                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5000                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5001                         .vtc_flow = RTE_BE32(0xffffffff),
5002                         .proto = 0xff,
5003                         .hop_limits = 0xff,
5004                 },
5005         };
5006         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5007                 .hdr = {
5008                         .common = {
5009                                 .u32 =
5010                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5011                                         .type = 0xFF,
5012                                         }).u32),
5013                         },
5014                         .dummy[0] = 0xffffffff,
5015                 },
5016         };
5017         struct mlx5_priv *priv = dev->data->dev_private;
5018         struct mlx5_dev_config *dev_conf = &priv->config;
5019         uint16_t queue_index = 0xFFFF;
5020         const struct rte_flow_item_vlan *vlan_m = NULL;
5021         int16_t rw_act_num = 0;
5022         uint64_t is_root;
5023
5024         if (items == NULL)
5025                 return -1;
5026         ret = flow_dv_validate_attributes(dev, attr, external, error);
5027         if (ret < 0)
5028                 return ret;
5029         is_root = (uint64_t)ret;
5030         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5031                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5032                 int type = items->type;
5033
5034                 if (!mlx5_flow_os_item_supported(type))
5035                         return rte_flow_error_set(error, ENOTSUP,
5036                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5037                                                   NULL, "item not supported");
5038                 switch (type) {
5039                 case RTE_FLOW_ITEM_TYPE_VOID:
5040                         break;
5041                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5042                         ret = flow_dv_validate_item_port_id
5043                                         (dev, items, attr, item_flags, error);
5044                         if (ret < 0)
5045                                 return ret;
5046                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5047                         break;
5048                 case RTE_FLOW_ITEM_TYPE_ETH:
5049                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5050                                                           error);
5051                         if (ret < 0)
5052                                 return ret;
5053                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5054                                              MLX5_FLOW_LAYER_OUTER_L2;
5055                         if (items->mask != NULL && items->spec != NULL) {
5056                                 ether_type =
5057                                         ((const struct rte_flow_item_eth *)
5058                                          items->spec)->type;
5059                                 ether_type &=
5060                                         ((const struct rte_flow_item_eth *)
5061                                          items->mask)->type;
5062                                 ether_type = rte_be_to_cpu_16(ether_type);
5063                         } else {
5064                                 ether_type = 0;
5065                         }
5066                         break;
5067                 case RTE_FLOW_ITEM_TYPE_VLAN:
5068                         ret = flow_dv_validate_item_vlan(items, item_flags,
5069                                                          dev, error);
5070                         if (ret < 0)
5071                                 return ret;
5072                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5073                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5074                         if (items->mask != NULL && items->spec != NULL) {
5075                                 ether_type =
5076                                         ((const struct rte_flow_item_vlan *)
5077                                          items->spec)->inner_type;
5078                                 ether_type &=
5079                                         ((const struct rte_flow_item_vlan *)
5080                                          items->mask)->inner_type;
5081                                 ether_type = rte_be_to_cpu_16(ether_type);
5082                         } else {
5083                                 ether_type = 0;
5084                         }
5085                         /* Store outer VLAN mask for of_push_vlan action. */
5086                         if (!tunnel)
5087                                 vlan_m = items->mask;
5088                         break;
5089                 case RTE_FLOW_ITEM_TYPE_IPV4:
5090                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5091                                                   &item_flags, &tunnel);
5092                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5093                                                            last_item,
5094                                                            ether_type,
5095                                                            &nic_ipv4_mask,
5096                                                            error);
5097                         if (ret < 0)
5098                                 return ret;
5099                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5100                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5101                         if (items->mask != NULL &&
5102                             ((const struct rte_flow_item_ipv4 *)
5103                              items->mask)->hdr.next_proto_id) {
5104                                 next_protocol =
5105                                         ((const struct rte_flow_item_ipv4 *)
5106                                          (items->spec))->hdr.next_proto_id;
5107                                 next_protocol &=
5108                                         ((const struct rte_flow_item_ipv4 *)
5109                                          (items->mask))->hdr.next_proto_id;
5110                         } else {
5111                                 /* Reset for inner layer. */
5112                                 next_protocol = 0xff;
5113                         }
5114                         break;
5115                 case RTE_FLOW_ITEM_TYPE_IPV6:
5116                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5117                                                   &item_flags, &tunnel);
5118                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5119                                                            last_item,
5120                                                            ether_type,
5121                                                            &nic_ipv6_mask,
5122                                                            error);
5123                         if (ret < 0)
5124                                 return ret;
5125                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5126                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5127                         if (items->mask != NULL &&
5128                             ((const struct rte_flow_item_ipv6 *)
5129                              items->mask)->hdr.proto) {
5130                                 item_ipv6_proto =
5131                                         ((const struct rte_flow_item_ipv6 *)
5132                                          items->spec)->hdr.proto;
5133                                 next_protocol =
5134                                         ((const struct rte_flow_item_ipv6 *)
5135                                          items->spec)->hdr.proto;
5136                                 next_protocol &=
5137                                         ((const struct rte_flow_item_ipv6 *)
5138                                          items->mask)->hdr.proto;
5139                         } else {
5140                                 /* Reset for inner layer. */
5141                                 next_protocol = 0xff;
5142                         }
5143                         break;
5144                 case RTE_FLOW_ITEM_TYPE_TCP:
5145                         ret = mlx5_flow_validate_item_tcp
5146                                                 (items, item_flags,
5147                                                  next_protocol,
5148                                                  &nic_tcp_mask,
5149                                                  error);
5150                         if (ret < 0)
5151                                 return ret;
5152                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5153                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5154                         break;
5155                 case RTE_FLOW_ITEM_TYPE_UDP:
5156                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5157                                                           next_protocol,
5158                                                           error);
5159                         if (ret < 0)
5160                                 return ret;
5161                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5162                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5163                         break;
5164                 case RTE_FLOW_ITEM_TYPE_GRE:
5165                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5166                                                           next_protocol, error);
5167                         if (ret < 0)
5168                                 return ret;
5169                         gre_item = items;
5170                         last_item = MLX5_FLOW_LAYER_GRE;
5171                         break;
5172                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5173                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5174                                                             next_protocol,
5175                                                             error);
5176                         if (ret < 0)
5177                                 return ret;
5178                         last_item = MLX5_FLOW_LAYER_NVGRE;
5179                         break;
5180                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5181                         ret = mlx5_flow_validate_item_gre_key
5182                                 (items, item_flags, gre_item, error);
5183                         if (ret < 0)
5184                                 return ret;
5185                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5186                         break;
5187                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5188                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5189                                                             error);
5190                         if (ret < 0)
5191                                 return ret;
5192                         last_item = MLX5_FLOW_LAYER_VXLAN;
5193                         break;
5194                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5195                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5196                                                                 item_flags, dev,
5197                                                                 error);
5198                         if (ret < 0)
5199                                 return ret;
5200                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5201                         break;
5202                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5203                         ret = mlx5_flow_validate_item_geneve(items,
5204                                                              item_flags, dev,
5205                                                              error);
5206                         if (ret < 0)
5207                                 return ret;
5208                         last_item = MLX5_FLOW_LAYER_GENEVE;
5209                         break;
5210                 case RTE_FLOW_ITEM_TYPE_MPLS:
5211                         ret = mlx5_flow_validate_item_mpls(dev, items,
5212                                                            item_flags,
5213                                                            last_item, error);
5214                         if (ret < 0)
5215                                 return ret;
5216                         last_item = MLX5_FLOW_LAYER_MPLS;
5217                         break;
5218
5219                 case RTE_FLOW_ITEM_TYPE_MARK:
5220                         ret = flow_dv_validate_item_mark(dev, items, attr,
5221                                                          error);
5222                         if (ret < 0)
5223                                 return ret;
5224                         last_item = MLX5_FLOW_ITEM_MARK;
5225                         break;
5226                 case RTE_FLOW_ITEM_TYPE_META:
5227                         ret = flow_dv_validate_item_meta(dev, items, attr,
5228                                                          error);
5229                         if (ret < 0)
5230                                 return ret;
5231                         last_item = MLX5_FLOW_ITEM_METADATA;
5232                         break;
5233                 case RTE_FLOW_ITEM_TYPE_ICMP:
5234                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5235                                                            next_protocol,
5236                                                            error);
5237                         if (ret < 0)
5238                                 return ret;
5239                         last_item = MLX5_FLOW_LAYER_ICMP;
5240                         break;
5241                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5242                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5243                                                             next_protocol,
5244                                                             error);
5245                         if (ret < 0)
5246                                 return ret;
5247                         item_ipv6_proto = IPPROTO_ICMPV6;
5248                         last_item = MLX5_FLOW_LAYER_ICMP6;
5249                         break;
5250                 case RTE_FLOW_ITEM_TYPE_TAG:
5251                         ret = flow_dv_validate_item_tag(dev, items,
5252                                                         attr, error);
5253                         if (ret < 0)
5254                                 return ret;
5255                         last_item = MLX5_FLOW_ITEM_TAG;
5256                         break;
5257                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5258                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5259                         break;
5260                 case RTE_FLOW_ITEM_TYPE_GTP:
5261                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5262                                                         error);
5263                         if (ret < 0)
5264                                 return ret;
5265                         last_item = MLX5_FLOW_LAYER_GTP;
5266                         break;
5267                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5268                         /* Capacity will be checked in the translate stage. */
5269                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5270                                                             last_item,
5271                                                             ether_type,
5272                                                             &nic_ecpri_mask,
5273                                                             error);
5274                         if (ret < 0)
5275                                 return ret;
5276                         last_item = MLX5_FLOW_LAYER_ECPRI;
5277                         break;
5278                 default:
5279                         return rte_flow_error_set(error, ENOTSUP,
5280                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5281                                                   NULL, "item not supported");
5282                 }
5283                 item_flags |= last_item;
5284         }
5285         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5286                 int type = actions->type;
5287
5288                 if (!mlx5_flow_os_action_supported(type))
5289                         return rte_flow_error_set(error, ENOTSUP,
5290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5291                                                   actions,
5292                                                   "action not supported");
5293                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5294                         return rte_flow_error_set(error, ENOTSUP,
5295                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5296                                                   actions, "too many actions");
5297                 switch (type) {
5298                 case RTE_FLOW_ACTION_TYPE_VOID:
5299                         break;
5300                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5301                         ret = flow_dv_validate_action_port_id(dev,
5302                                                               action_flags,
5303                                                               actions,
5304                                                               attr,
5305                                                               error);
5306                         if (ret)
5307                                 return ret;
5308                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5309                         ++actions_n;
5310                         break;
5311                 case RTE_FLOW_ACTION_TYPE_FLAG:
5312                         ret = flow_dv_validate_action_flag(dev, action_flags,
5313                                                            attr, error);
5314                         if (ret < 0)
5315                                 return ret;
5316                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5317                                 /* Count all modify-header actions as one. */
5318                                 if (!(action_flags &
5319                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5320                                         ++actions_n;
5321                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5322                                                 MLX5_FLOW_ACTION_MARK_EXT;
5323                         } else {
5324                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5325                                 ++actions_n;
5326                         }
5327                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5328                         break;
5329                 case RTE_FLOW_ACTION_TYPE_MARK:
5330                         ret = flow_dv_validate_action_mark(dev, actions,
5331                                                            action_flags,
5332                                                            attr, error);
5333                         if (ret < 0)
5334                                 return ret;
5335                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5336                                 /* Count all modify-header actions as one. */
5337                                 if (!(action_flags &
5338                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5339                                         ++actions_n;
5340                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5341                                                 MLX5_FLOW_ACTION_MARK_EXT;
5342                         } else {
5343                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5344                                 ++actions_n;
5345                         }
5346                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5347                         break;
5348                 case RTE_FLOW_ACTION_TYPE_SET_META:
5349                         ret = flow_dv_validate_action_set_meta(dev, actions,
5350                                                                action_flags,
5351                                                                attr, error);
5352                         if (ret < 0)
5353                                 return ret;
5354                         /* Count all modify-header actions as one action. */
5355                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5356                                 ++actions_n;
5357                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5358                         rw_act_num += MLX5_ACT_NUM_SET_META;
5359                         break;
5360                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5361                         ret = flow_dv_validate_action_set_tag(dev, actions,
5362                                                               action_flags,
5363                                                               attr, error);
5364                         if (ret < 0)
5365                                 return ret;
5366                         /* Count all modify-header actions as one action. */
5367                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5368                                 ++actions_n;
5369                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5370                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5371                         break;
5372                 case RTE_FLOW_ACTION_TYPE_DROP:
5373                         ret = mlx5_flow_validate_action_drop(action_flags,
5374                                                              attr, error);
5375                         if (ret < 0)
5376                                 return ret;
5377                         action_flags |= MLX5_FLOW_ACTION_DROP;
5378                         ++actions_n;
5379                         break;
5380                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5381                         ret = mlx5_flow_validate_action_queue(actions,
5382                                                               action_flags, dev,
5383                                                               attr, error);
5384                         if (ret < 0)
5385                                 return ret;
5386                         queue_index = ((const struct rte_flow_action_queue *)
5387                                                         (actions->conf))->index;
5388                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5389                         ++actions_n;
5390                         break;
5391                 case RTE_FLOW_ACTION_TYPE_RSS:
5392                         rss = actions->conf;
5393                         ret = mlx5_flow_validate_action_rss(actions,
5394                                                             action_flags, dev,
5395                                                             attr, item_flags,
5396                                                             error);
5397                         if (ret < 0)
5398                                 return ret;
5399                         if (rss != NULL && rss->queue_num)
5400                                 queue_index = rss->queue[0];
5401                         action_flags |= MLX5_FLOW_ACTION_RSS;
5402                         ++actions_n;
5403                         break;
5404                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5405                         ret =
5406                         mlx5_flow_validate_action_default_miss(action_flags,
5407                                         attr, error);
5408                         if (ret < 0)
5409                                 return ret;
5410                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5411                         ++actions_n;
5412                         break;
5413                 case RTE_FLOW_ACTION_TYPE_COUNT:
5414                         ret = flow_dv_validate_action_count(dev, error);
5415                         if (ret < 0)
5416                                 return ret;
5417                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5418                         ++actions_n;
5419                         break;
5420                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5421                         if (flow_dv_validate_action_pop_vlan(dev,
5422                                                              action_flags,
5423                                                              actions,
5424                                                              item_flags, attr,
5425                                                              error))
5426                                 return -rte_errno;
5427                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5428                         ++actions_n;
5429                         break;
5430                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5431                         ret = flow_dv_validate_action_push_vlan(dev,
5432                                                                 action_flags,
5433                                                                 vlan_m,
5434                                                                 actions, attr,
5435                                                                 error);
5436                         if (ret < 0)
5437                                 return ret;
5438                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5439                         ++actions_n;
5440                         break;
5441                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5442                         ret = flow_dv_validate_action_set_vlan_pcp
5443                                                 (action_flags, actions, error);
5444                         if (ret < 0)
5445                                 return ret;
5446                         /* Count PCP with push_vlan command. */
5447                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5448                         break;
5449                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5450                         ret = flow_dv_validate_action_set_vlan_vid
5451                                                 (item_flags, action_flags,
5452                                                  actions, error);
5453                         if (ret < 0)
5454                                 return ret;
5455                         /* Count VID with push_vlan command. */
5456                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5457                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5458                         break;
5459                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5460                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5461                         ret = flow_dv_validate_action_l2_encap(dev,
5462                                                                action_flags,
5463                                                                actions, attr,
5464                                                                error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5468                         ++actions_n;
5469                         break;
5470                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5471                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5472                         ret = flow_dv_validate_action_decap(dev, action_flags,
5473                                                             attr, error);
5474                         if (ret < 0)
5475                                 return ret;
5476                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5477                         ++actions_n;
5478                         break;
5479                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5480                         ret = flow_dv_validate_action_raw_encap_decap
5481                                 (dev, NULL, actions->conf, attr, &action_flags,
5482                                  &actions_n, error);
5483                         if (ret < 0)
5484                                 return ret;
5485                         break;
5486                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5487                         decap = actions->conf;
5488                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5489                                 ;
5490                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5491                                 encap = NULL;
5492                                 actions--;
5493                         } else {
5494                                 encap = actions->conf;
5495                         }
5496                         ret = flow_dv_validate_action_raw_encap_decap
5497                                            (dev,
5498                                             decap ? decap : &empty_decap, encap,
5499                                             attr, &action_flags, &actions_n,
5500                                             error);
5501                         if (ret < 0)
5502                                 return ret;
5503                         break;
5504                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5505                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5506                         ret = flow_dv_validate_action_modify_mac(action_flags,
5507                                                                  actions,
5508                                                                  item_flags,
5509                                                                  error);
5510                         if (ret < 0)
5511                                 return ret;
5512                         /* Count all modify-header actions as one action. */
5513                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5514                                 ++actions_n;
5515                         action_flags |= actions->type ==
5516                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5517                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5518                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5519                         /*
5520                          * Even if the source and destination MAC addresses have
5521                          * overlap in the header with 4B alignment, the convert
5522                          * function will handle them separately and 4 SW actions
5523                          * will be created. And 2 actions will be added each
5524                          * time no matter how many bytes of address will be set.
5525                          */
5526                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5527                         break;
5528                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5529                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5530                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5531                                                                   actions,
5532                                                                   item_flags,
5533                                                                   error);
5534                         if (ret < 0)
5535                                 return ret;
5536                         /* Count all modify-header actions as one action. */
5537                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5538                                 ++actions_n;
5539                         action_flags |= actions->type ==
5540                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5541                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5542                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5543                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5544                         break;
5545                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5546                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5547                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5548                                                                   actions,
5549                                                                   item_flags,
5550                                                                   error);
5551                         if (ret < 0)
5552                                 return ret;
5553                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5554                                 return rte_flow_error_set(error, ENOTSUP,
5555                                         RTE_FLOW_ERROR_TYPE_ACTION,
5556                                         actions,
5557                                         "Can't change header "
5558                                         "with ICMPv6 proto");
5559                         /* Count all modify-header actions as one action. */
5560                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5561                                 ++actions_n;
5562                         action_flags |= actions->type ==
5563                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5564                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5565                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5566                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5567                         break;
5568                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5569                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5570                         ret = flow_dv_validate_action_modify_tp(action_flags,
5571                                                                 actions,
5572                                                                 item_flags,
5573                                                                 error);
5574                         if (ret < 0)
5575                                 return ret;
5576                         /* Count all modify-header actions as one action. */
5577                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5578                                 ++actions_n;
5579                         action_flags |= actions->type ==
5580                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5581                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5582                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5583                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5584                         break;
5585                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5586                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5587                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5588                                                                  actions,
5589                                                                  item_flags,
5590                                                                  error);
5591                         if (ret < 0)
5592                                 return ret;
5593                         /* Count all modify-header actions as one action. */
5594                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5595                                 ++actions_n;
5596                         action_flags |= actions->type ==
5597                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5598                                                 MLX5_FLOW_ACTION_SET_TTL :
5599                                                 MLX5_FLOW_ACTION_DEC_TTL;
5600                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5601                         break;
5602                 case RTE_FLOW_ACTION_TYPE_JUMP:
5603                         ret = flow_dv_validate_action_jump(actions,
5604                                                            action_flags,
5605                                                            attr, external,
5606                                                            error);
5607                         if (ret)
5608                                 return ret;
5609                         ++actions_n;
5610                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5611                         break;
5612                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5613                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5614                         ret = flow_dv_validate_action_modify_tcp_seq
5615                                                                 (action_flags,
5616                                                                  actions,
5617                                                                  item_flags,
5618                                                                  error);
5619                         if (ret < 0)
5620                                 return ret;
5621                         /* Count all modify-header actions as one action. */
5622                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5623                                 ++actions_n;
5624                         action_flags |= actions->type ==
5625                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5626                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5627                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5628                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5629                         break;
5630                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5631                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5632                         ret = flow_dv_validate_action_modify_tcp_ack
5633                                                                 (action_flags,
5634                                                                  actions,
5635                                                                  item_flags,
5636                                                                  error);
5637                         if (ret < 0)
5638                                 return ret;
5639                         /* Count all modify-header actions as one action. */
5640                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5641                                 ++actions_n;
5642                         action_flags |= actions->type ==
5643                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5644                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5645                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5646                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5647                         break;
5648                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5649                         break;
5650                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5651                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5652                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5653                         break;
5654                 case RTE_FLOW_ACTION_TYPE_METER:
5655                         ret = mlx5_flow_validate_action_meter(dev,
5656                                                               action_flags,
5657                                                               actions, attr,
5658                                                               error);
5659                         if (ret < 0)
5660                                 return ret;
5661                         action_flags |= MLX5_FLOW_ACTION_METER;
5662                         ++actions_n;
5663                         /* Meter action will add one more TAG action. */
5664                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5665                         break;
5666                 case RTE_FLOW_ACTION_TYPE_AGE:
5667                         ret = flow_dv_validate_action_age(action_flags,
5668                                                           actions, dev,
5669                                                           error);
5670                         if (ret < 0)
5671                                 return ret;
5672                         action_flags |= MLX5_FLOW_ACTION_AGE;
5673                         ++actions_n;
5674                         break;
5675                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5676                         ret = flow_dv_validate_action_modify_ipv4_dscp
5677                                                          (action_flags,
5678                                                           actions,
5679                                                           item_flags,
5680                                                           error);
5681                         if (ret < 0)
5682                                 return ret;
5683                         /* Count all modify-header actions as one action. */
5684                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5685                                 ++actions_n;
5686                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5687                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5688                         break;
5689                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5690                         ret = flow_dv_validate_action_modify_ipv6_dscp
5691                                                                 (action_flags,
5692                                                                  actions,
5693                                                                  item_flags,
5694                                                                  error);
5695                         if (ret < 0)
5696                                 return ret;
5697                         /* Count all modify-header actions as one action. */
5698                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5699                                 ++actions_n;
5700                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5701                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5702                         break;
5703                 default:
5704                         return rte_flow_error_set(error, ENOTSUP,
5705                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5706                                                   actions,
5707                                                   "action not supported");
5708                 }
5709         }
5710         /*
5711          * Validate the drop action mutual exclusion with other actions.
5712          * Drop action is mutually-exclusive with any other action, except for
5713          * Count action.
5714          */
5715         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5716             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5717                 return rte_flow_error_set(error, EINVAL,
5718                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5719                                           "Drop action is mutually-exclusive "
5720                                           "with any other action, except for "
5721                                           "Count action");
5722         /* Eswitch has few restrictions on using items and actions */
5723         if (attr->transfer) {
5724                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5725                     action_flags & MLX5_FLOW_ACTION_FLAG)
5726                         return rte_flow_error_set(error, ENOTSUP,
5727                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5728                                                   NULL,
5729                                                   "unsupported action FLAG");
5730                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5731                     action_flags & MLX5_FLOW_ACTION_MARK)
5732                         return rte_flow_error_set(error, ENOTSUP,
5733                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5734                                                   NULL,
5735                                                   "unsupported action MARK");
5736                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5737                         return rte_flow_error_set(error, ENOTSUP,
5738                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5739                                                   NULL,
5740                                                   "unsupported action QUEUE");
5741                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5742                         return rte_flow_error_set(error, ENOTSUP,
5743                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5744                                                   NULL,
5745                                                   "unsupported action RSS");
5746                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5747                         return rte_flow_error_set(error, EINVAL,
5748                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5749                                                   actions,
5750                                                   "no fate action is found");
5751         } else {
5752                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5753                         return rte_flow_error_set(error, EINVAL,
5754                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5755                                                   actions,
5756                                                   "no fate action is found");
5757         }
5758         /* Continue validation for Xcap and VLAN actions.*/
5759         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
5760                              MLX5_FLOW_VLAN_ACTIONS)) &&
5761             (queue_index == 0xFFFF ||
5762              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5763                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5764                     MLX5_FLOW_XCAP_ACTIONS)
5765                         return rte_flow_error_set(error, ENOTSUP,
5766                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5767                                                   NULL, "encap and decap "
5768                                                   "combination aren't supported");
5769                 if (!attr->transfer && attr->ingress) {
5770                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
5771                                 return rte_flow_error_set
5772                                                 (error, ENOTSUP,
5773                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5774                                                  NULL, "encap is not supported"
5775                                                  " for ingress traffic");
5776                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5777                                 return rte_flow_error_set
5778                                                 (error, ENOTSUP,
5779                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5780                                                  NULL, "push VLAN action not "
5781                                                  "supported for ingress");
5782                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
5783                                         MLX5_FLOW_VLAN_ACTIONS)
5784                                 return rte_flow_error_set
5785                                                 (error, ENOTSUP,
5786                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5787                                                  NULL, "no support for "
5788                                                  "multiple VLAN actions");
5789                 }
5790         }
5791         /* Hairpin flow will add one more TAG action. */
5792         if (hairpin > 0)
5793                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5794         /* extra metadata enabled: one more TAG action will be add. */
5795         if (dev_conf->dv_flow_en &&
5796             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5797             mlx5_flow_ext_mreg_supported(dev))
5798                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5799         if ((uint32_t)rw_act_num >
5800                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5801                 return rte_flow_error_set(error, ENOTSUP,
5802                                           RTE_FLOW_ERROR_TYPE_ACTION,
5803                                           NULL, "too many header modify"
5804                                           " actions to support");
5805         }
5806         return 0;
5807 }
5808
5809 /**
5810  * Internal preparation function. Allocates the DV flow size,
5811  * this size is constant.
5812  *
5813  * @param[in] dev
5814  *   Pointer to the rte_eth_dev structure.
5815  * @param[in] attr
5816  *   Pointer to the flow attributes.
5817  * @param[in] items
5818  *   Pointer to the list of items.
5819  * @param[in] actions
5820  *   Pointer to the list of actions.
5821  * @param[out] error
5822  *   Pointer to the error structure.
5823  *
5824  * @return
5825  *   Pointer to mlx5_flow object on success,
5826  *   otherwise NULL and rte_errno is set.
5827  */
5828 static struct mlx5_flow *
5829 flow_dv_prepare(struct rte_eth_dev *dev,
5830                 const struct rte_flow_attr *attr __rte_unused,
5831                 const struct rte_flow_item items[] __rte_unused,
5832                 const struct rte_flow_action actions[] __rte_unused,
5833                 struct rte_flow_error *error)
5834 {
5835         uint32_t handle_idx = 0;
5836         struct mlx5_flow *dev_flow;
5837         struct mlx5_flow_handle *dev_handle;
5838         struct mlx5_priv *priv = dev->data->dev_private;
5839
5840         /* In case of corrupting the memory. */
5841         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5842                 rte_flow_error_set(error, ENOSPC,
5843                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5844                                    "not free temporary device flow");
5845                 return NULL;
5846         }
5847         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5848                                    &handle_idx);
5849         if (!dev_handle) {
5850                 rte_flow_error_set(error, ENOMEM,
5851                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5852                                    "not enough memory to create flow handle");
5853                 return NULL;
5854         }
5855         /* No multi-thread supporting. */
5856         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5857         dev_flow->handle = dev_handle;
5858         dev_flow->handle_idx = handle_idx;
5859         /*
5860          * In some old rdma-core releases, before continuing, a check of the
5861          * length of matching parameter will be done at first. It needs to use
5862          * the length without misc4 param. If the flow has misc4 support, then
5863          * the length needs to be adjusted accordingly. Each param member is
5864          * aligned with a 64B boundary naturally.
5865          */
5866         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5867                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5868         /*
5869          * The matching value needs to be cleared to 0 before using. In the
5870          * past, it will be automatically cleared when using rte_*alloc
5871          * API. The time consumption will be almost the same as before.
5872          */
5873         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5874         dev_flow->ingress = attr->ingress;
5875         dev_flow->dv.transfer = attr->transfer;
5876         return dev_flow;
5877 }
5878
5879 #ifdef RTE_LIBRTE_MLX5_DEBUG
5880 /**
5881  * Sanity check for match mask and value. Similar to check_valid_spec() in
5882  * kernel driver. If unmasked bit is present in value, it returns failure.
5883  *
5884  * @param match_mask
5885  *   pointer to match mask buffer.
5886  * @param match_value
5887  *   pointer to match value buffer.
5888  *
5889  * @return
5890  *   0 if valid, -EINVAL otherwise.
5891  */
5892 static int
5893 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5894 {
5895         uint8_t *m = match_mask;
5896         uint8_t *v = match_value;
5897         unsigned int i;
5898
5899         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5900                 if (v[i] & ~m[i]) {
5901                         DRV_LOG(ERR,
5902                                 "match_value differs from match_criteria"
5903                                 " %p[%u] != %p[%u]",
5904                                 match_value, i, match_mask, i);
5905                         return -EINVAL;
5906                 }
5907         }
5908         return 0;
5909 }
5910 #endif
5911
5912 /**
5913  * Add match of ip_version.
5914  *
5915  * @param[in] group
5916  *   Flow group.
5917  * @param[in] headers_v
5918  *   Values header pointer.
5919  * @param[in] headers_m
5920  *   Masks header pointer.
5921  * @param[in] ip_version
5922  *   The IP version to set.
5923  */
5924 static inline void
5925 flow_dv_set_match_ip_version(uint32_t group,
5926                              void *headers_v,
5927                              void *headers_m,
5928                              uint8_t ip_version)
5929 {
5930         if (group == 0)
5931                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5932         else
5933                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5934                          ip_version);
5935         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5936         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5937         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5938 }
5939
5940 /**
5941  * Add Ethernet item to matcher and to the value.
5942  *
5943  * @param[in, out] matcher
5944  *   Flow matcher.
5945  * @param[in, out] key
5946  *   Flow matcher value.
5947  * @param[in] item
5948  *   Flow pattern to translate.
5949  * @param[in] inner
5950  *   Item is inner pattern.
5951  */
5952 static void
5953 flow_dv_translate_item_eth(void *matcher, void *key,
5954                            const struct rte_flow_item *item, int inner,
5955                            uint32_t group)
5956 {
5957         const struct rte_flow_item_eth *eth_m = item->mask;
5958         const struct rte_flow_item_eth *eth_v = item->spec;
5959         const struct rte_flow_item_eth nic_mask = {
5960                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5961                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5962                 .type = RTE_BE16(0xffff),
5963         };
5964         void *headers_m;
5965         void *headers_v;
5966         char *l24_v;
5967         unsigned int i;
5968
5969         if (!eth_v)
5970                 return;
5971         if (!eth_m)
5972                 eth_m = &nic_mask;
5973         if (inner) {
5974                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5975                                          inner_headers);
5976                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5977         } else {
5978                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5979                                          outer_headers);
5980                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5981         }
5982         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5983                &eth_m->dst, sizeof(eth_m->dst));
5984         /* The value must be in the range of the mask. */
5985         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5986         for (i = 0; i < sizeof(eth_m->dst); ++i)
5987                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5988         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5989                &eth_m->src, sizeof(eth_m->src));
5990         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5991         /* The value must be in the range of the mask. */
5992         for (i = 0; i < sizeof(eth_m->dst); ++i)
5993                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5994         if (eth_v->type) {
5995                 /* When ethertype is present set mask for tagged VLAN. */
5996                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5997                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5998                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5999                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6000                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6001                                  1);
6002                         /* Return here to avoid setting match on ethertype. */
6003                         return;
6004                 }
6005         }
6006         /*
6007          * HW supports match on one Ethertype, the Ethertype following the last
6008          * VLAN tag of the packet (see PRM).
6009          * Set match on ethertype only if ETH header is not followed by VLAN.
6010          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6011          * ethertype, and use ip_version field instead.
6012          * eCPRI over Ether layer will use type value 0xAEFE.
6013          */
6014         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6015             eth_m->type == 0xFFFF) {
6016                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6017         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6018                    eth_m->type == 0xFFFF) {
6019                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6020         } else {
6021                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6022                          rte_be_to_cpu_16(eth_m->type));
6023                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6024                                      ethertype);
6025                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6026         }
6027 }
6028
6029 /**
6030  * Add VLAN item to matcher and to the value.
6031  *
6032  * @param[in, out] dev_flow
6033  *   Flow descriptor.
6034  * @param[in, out] matcher
6035  *   Flow matcher.
6036  * @param[in, out] key
6037  *   Flow matcher value.
6038  * @param[in] item
6039  *   Flow pattern to translate.
6040  * @param[in] inner
6041  *   Item is inner pattern.
6042  */
6043 static void
6044 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6045                             void *matcher, void *key,
6046                             const struct rte_flow_item *item,
6047                             int inner, uint32_t group)
6048 {
6049         const struct rte_flow_item_vlan *vlan_m = item->mask;
6050         const struct rte_flow_item_vlan *vlan_v = item->spec;
6051         void *headers_m;
6052         void *headers_v;
6053         uint16_t tci_m;
6054         uint16_t tci_v;
6055
6056         if (inner) {
6057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6058                                          inner_headers);
6059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6060         } else {
6061                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6062                                          outer_headers);
6063                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6064                 /*
6065                  * This is workaround, masks are not supported,
6066                  * and pre-validated.
6067                  */
6068                 if (vlan_v)
6069                         dev_flow->handle->vf_vlan.tag =
6070                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6071         }
6072         /*
6073          * When VLAN item exists in flow, mark packet as tagged,
6074          * even if TCI is not specified.
6075          */
6076         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6077         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6078         if (!vlan_v)
6079                 return;
6080         if (!vlan_m)
6081                 vlan_m = &rte_flow_item_vlan_mask;
6082         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6083         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6084         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6085         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6086         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6087         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6088         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6089         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6090         /*
6091          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6092          * ethertype, and use ip_version field instead.
6093          */
6094         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6095             vlan_m->inner_type == 0xFFFF) {
6096                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6097         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6098                    vlan_m->inner_type == 0xFFFF) {
6099                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6100         } else {
6101                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6102                          rte_be_to_cpu_16(vlan_m->inner_type));
6103                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6104                          rte_be_to_cpu_16(vlan_m->inner_type &
6105                                           vlan_v->inner_type));
6106         }
6107 }
6108
6109 /**
6110  * Add IPV4 item to matcher and to the value.
6111  *
6112  * @param[in, out] matcher
6113  *   Flow matcher.
6114  * @param[in, out] key
6115  *   Flow matcher value.
6116  * @param[in] item
6117  *   Flow pattern to translate.
6118  * @param[in] item_flags
6119  *   Bit-fields that holds the items detected until now.
6120  * @param[in] inner
6121  *   Item is inner pattern.
6122  * @param[in] group
6123  *   The group to insert the rule.
6124  */
6125 static void
6126 flow_dv_translate_item_ipv4(void *matcher, void *key,
6127                             const struct rte_flow_item *item,
6128                             const uint64_t item_flags,
6129                             int inner, uint32_t group)
6130 {
6131         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6132         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6133         const struct rte_flow_item_ipv4 nic_mask = {
6134                 .hdr = {
6135                         .src_addr = RTE_BE32(0xffffffff),
6136                         .dst_addr = RTE_BE32(0xffffffff),
6137                         .type_of_service = 0xff,
6138                         .next_proto_id = 0xff,
6139                         .time_to_live = 0xff,
6140                 },
6141         };
6142         void *headers_m;
6143         void *headers_v;
6144         char *l24_m;
6145         char *l24_v;
6146         uint8_t tos;
6147
6148         if (inner) {
6149                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6150                                          inner_headers);
6151                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6152         } else {
6153                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6154                                          outer_headers);
6155                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6156         }
6157         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6158         /*
6159          * On outer header (which must contains L2), or inner header with L2,
6160          * set cvlan_tag mask bit to mark this packet as untagged.
6161          * This should be done even if item->spec is empty.
6162          */
6163         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6164                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6165         if (!ipv4_v)
6166                 return;
6167         if (!ipv4_m)
6168                 ipv4_m = &nic_mask;
6169         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6170                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6171         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6172                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6173         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6174         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6175         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6176                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6177         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6178                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6179         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6180         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6181         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6182         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6183                  ipv4_m->hdr.type_of_service);
6184         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6185         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6186                  ipv4_m->hdr.type_of_service >> 2);
6187         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6188         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6189                  ipv4_m->hdr.next_proto_id);
6190         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6191                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6192         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6193                  ipv4_m->hdr.time_to_live);
6194         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6195                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6196 }
6197
6198 /**
6199  * Add IPV6 item to matcher and to the value.
6200  *
6201  * @param[in, out] matcher
6202  *   Flow matcher.
6203  * @param[in, out] key
6204  *   Flow matcher value.
6205  * @param[in] item
6206  *   Flow pattern to translate.
6207  * @param[in] item_flags
6208  *   Bit-fields that holds the items detected until now.
6209  * @param[in] inner
6210  *   Item is inner pattern.
6211  * @param[in] group
6212  *   The group to insert the rule.
6213  */
6214 static void
6215 flow_dv_translate_item_ipv6(void *matcher, void *key,
6216                             const struct rte_flow_item *item,
6217                             const uint64_t item_flags,
6218                             int inner, uint32_t group)
6219 {
6220         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6221         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6222         const struct rte_flow_item_ipv6 nic_mask = {
6223                 .hdr = {
6224                         .src_addr =
6225                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6226                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6227                         .dst_addr =
6228                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6229                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6230                         .vtc_flow = RTE_BE32(0xffffffff),
6231                         .proto = 0xff,
6232                         .hop_limits = 0xff,
6233                 },
6234         };
6235         void *headers_m;
6236         void *headers_v;
6237         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6238         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6239         char *l24_m;
6240         char *l24_v;
6241         uint32_t vtc_m;
6242         uint32_t vtc_v;
6243         int i;
6244         int size;
6245
6246         if (inner) {
6247                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6248                                          inner_headers);
6249                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6250         } else {
6251                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6252                                          outer_headers);
6253                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6254         }
6255         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6256         /*
6257          * On outer header (which must contains L2), or inner header with L2,
6258          * set cvlan_tag mask bit to mark this packet as untagged.
6259          * This should be done even if item->spec is empty.
6260          */
6261         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6262                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6263         if (!ipv6_v)
6264                 return;
6265         if (!ipv6_m)
6266                 ipv6_m = &nic_mask;
6267         size = sizeof(ipv6_m->hdr.dst_addr);
6268         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6269                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6270         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6271                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6272         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6273         for (i = 0; i < size; ++i)
6274                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6275         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6276                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6277         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6278                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6279         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6280         for (i = 0; i < size; ++i)
6281                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6282         /* TOS. */
6283         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6284         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6285         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6286         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6287         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6288         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6289         /* Label. */
6290         if (inner) {
6291                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6292                          vtc_m);
6293                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6294                          vtc_v);
6295         } else {
6296                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6297                          vtc_m);
6298                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6299                          vtc_v);
6300         }
6301         /* Protocol. */
6302         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6303                  ipv6_m->hdr.proto);
6304         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6305                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6306         /* Hop limit. */
6307         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6308                  ipv6_m->hdr.hop_limits);
6309         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6310                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6311 }
6312
6313 /**
6314  * Add TCP item to matcher and to the value.
6315  *
6316  * @param[in, out] matcher
6317  *   Flow matcher.
6318  * @param[in, out] key
6319  *   Flow matcher value.
6320  * @param[in] item
6321  *   Flow pattern to translate.
6322  * @param[in] inner
6323  *   Item is inner pattern.
6324  */
6325 static void
6326 flow_dv_translate_item_tcp(void *matcher, void *key,
6327                            const struct rte_flow_item *item,
6328                            int inner)
6329 {
6330         const struct rte_flow_item_tcp *tcp_m = item->mask;
6331         const struct rte_flow_item_tcp *tcp_v = item->spec;
6332         void *headers_m;
6333         void *headers_v;
6334
6335         if (inner) {
6336                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6337                                          inner_headers);
6338                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6339         } else {
6340                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6341                                          outer_headers);
6342                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6343         }
6344         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6345         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6346         if (!tcp_v)
6347                 return;
6348         if (!tcp_m)
6349                 tcp_m = &rte_flow_item_tcp_mask;
6350         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6351                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6352         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6353                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6354         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6355                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6356         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6357                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6358         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6359                  tcp_m->hdr.tcp_flags);
6360         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6361                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6362 }
6363
6364 /**
6365  * Add UDP item to matcher and to the value.
6366  *
6367  * @param[in, out] matcher
6368  *   Flow matcher.
6369  * @param[in, out] key
6370  *   Flow matcher value.
6371  * @param[in] item
6372  *   Flow pattern to translate.
6373  * @param[in] inner
6374  *   Item is inner pattern.
6375  */
6376 static void
6377 flow_dv_translate_item_udp(void *matcher, void *key,
6378                            const struct rte_flow_item *item,
6379                            int inner)
6380 {
6381         const struct rte_flow_item_udp *udp_m = item->mask;
6382         const struct rte_flow_item_udp *udp_v = item->spec;
6383         void *headers_m;
6384         void *headers_v;
6385
6386         if (inner) {
6387                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6388                                          inner_headers);
6389                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6390         } else {
6391                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6392                                          outer_headers);
6393                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6394         }
6395         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6396         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6397         if (!udp_v)
6398                 return;
6399         if (!udp_m)
6400                 udp_m = &rte_flow_item_udp_mask;
6401         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6402                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6403         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6404                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6405         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6406                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6407         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6408                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6409 }
6410
6411 /**
6412  * Add GRE optional Key item to matcher and to the value.
6413  *
6414  * @param[in, out] matcher
6415  *   Flow matcher.
6416  * @param[in, out] key
6417  *   Flow matcher value.
6418  * @param[in] item
6419  *   Flow pattern to translate.
6420  * @param[in] inner
6421  *   Item is inner pattern.
6422  */
6423 static void
6424 flow_dv_translate_item_gre_key(void *matcher, void *key,
6425                                    const struct rte_flow_item *item)
6426 {
6427         const rte_be32_t *key_m = item->mask;
6428         const rte_be32_t *key_v = item->spec;
6429         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6430         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6431         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6432
6433         /* GRE K bit must be on and should already be validated */
6434         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6435         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6436         if (!key_v)
6437                 return;
6438         if (!key_m)
6439                 key_m = &gre_key_default_mask;
6440         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6441                  rte_be_to_cpu_32(*key_m) >> 8);
6442         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6443                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6444         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6445                  rte_be_to_cpu_32(*key_m) & 0xFF);
6446         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6447                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6448 }
6449
6450 /**
6451  * Add GRE item to matcher and to the value.
6452  *
6453  * @param[in, out] matcher
6454  *   Flow matcher.
6455  * @param[in, out] key
6456  *   Flow matcher value.
6457  * @param[in] item
6458  *   Flow pattern to translate.
6459  * @param[in] inner
6460  *   Item is inner pattern.
6461  */
6462 static void
6463 flow_dv_translate_item_gre(void *matcher, void *key,
6464                            const struct rte_flow_item *item,
6465                            int inner)
6466 {
6467         const struct rte_flow_item_gre *gre_m = item->mask;
6468         const struct rte_flow_item_gre *gre_v = item->spec;
6469         void *headers_m;
6470         void *headers_v;
6471         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6472         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6473         struct {
6474                 union {
6475                         __extension__
6476                         struct {
6477                                 uint16_t version:3;
6478                                 uint16_t rsvd0:9;
6479                                 uint16_t s_present:1;
6480                                 uint16_t k_present:1;
6481                                 uint16_t rsvd_bit1:1;
6482                                 uint16_t c_present:1;
6483                         };
6484                         uint16_t value;
6485                 };
6486         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6487
6488         if (inner) {
6489                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6490                                          inner_headers);
6491                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6492         } else {
6493                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6494                                          outer_headers);
6495                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6496         }
6497         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6498         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6499         if (!gre_v)
6500                 return;
6501         if (!gre_m)
6502                 gre_m = &rte_flow_item_gre_mask;
6503         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6504                  rte_be_to_cpu_16(gre_m->protocol));
6505         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6506                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6507         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6508         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6509         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6510                  gre_crks_rsvd0_ver_m.c_present);
6511         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6512                  gre_crks_rsvd0_ver_v.c_present &
6513                  gre_crks_rsvd0_ver_m.c_present);
6514         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6515                  gre_crks_rsvd0_ver_m.k_present);
6516         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6517                  gre_crks_rsvd0_ver_v.k_present &
6518                  gre_crks_rsvd0_ver_m.k_present);
6519         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6520                  gre_crks_rsvd0_ver_m.s_present);
6521         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6522                  gre_crks_rsvd0_ver_v.s_present &
6523                  gre_crks_rsvd0_ver_m.s_present);
6524 }
6525
6526 /**
6527  * Add NVGRE item to matcher and to the value.
6528  *
6529  * @param[in, out] matcher
6530  *   Flow matcher.
6531  * @param[in, out] key
6532  *   Flow matcher value.
6533  * @param[in] item
6534  *   Flow pattern to translate.
6535  * @param[in] inner
6536  *   Item is inner pattern.
6537  */
6538 static void
6539 flow_dv_translate_item_nvgre(void *matcher, void *key,
6540                              const struct rte_flow_item *item,
6541                              int inner)
6542 {
6543         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6544         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6545         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6546         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6547         const char *tni_flow_id_m;
6548         const char *tni_flow_id_v;
6549         char *gre_key_m;
6550         char *gre_key_v;
6551         int size;
6552         int i;
6553
6554         /* For NVGRE, GRE header fields must be set with defined values. */
6555         const struct rte_flow_item_gre gre_spec = {
6556                 .c_rsvd0_ver = RTE_BE16(0x2000),
6557                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6558         };
6559         const struct rte_flow_item_gre gre_mask = {
6560                 .c_rsvd0_ver = RTE_BE16(0xB000),
6561                 .protocol = RTE_BE16(UINT16_MAX),
6562         };
6563         const struct rte_flow_item gre_item = {
6564                 .spec = &gre_spec,
6565                 .mask = &gre_mask,
6566                 .last = NULL,
6567         };
6568         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6569         if (!nvgre_v)
6570                 return;
6571         if (!nvgre_m)
6572                 nvgre_m = &rte_flow_item_nvgre_mask;
6573         tni_flow_id_m = (const char *)nvgre_m->tni;
6574         tni_flow_id_v = (const char *)nvgre_v->tni;
6575         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6576         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6577         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6578         memcpy(gre_key_m, tni_flow_id_m, size);
6579         for (i = 0; i < size; ++i)
6580                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6581 }
6582
6583 /**
6584  * Add VXLAN item to matcher and to the value.
6585  *
6586  * @param[in, out] matcher
6587  *   Flow matcher.
6588  * @param[in, out] key
6589  *   Flow matcher value.
6590  * @param[in] item
6591  *   Flow pattern to translate.
6592  * @param[in] inner
6593  *   Item is inner pattern.
6594  */
6595 static void
6596 flow_dv_translate_item_vxlan(void *matcher, void *key,
6597                              const struct rte_flow_item *item,
6598                              int inner)
6599 {
6600         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6601         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6602         void *headers_m;
6603         void *headers_v;
6604         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6605         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6606         char *vni_m;
6607         char *vni_v;
6608         uint16_t dport;
6609         int size;
6610         int i;
6611
6612         if (inner) {
6613                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6614                                          inner_headers);
6615                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6616         } else {
6617                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6618                                          outer_headers);
6619                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6620         }
6621         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6622                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6623         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6624                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6625                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6626         }
6627         if (!vxlan_v)
6628                 return;
6629         if (!vxlan_m)
6630                 vxlan_m = &rte_flow_item_vxlan_mask;
6631         size = sizeof(vxlan_m->vni);
6632         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6633         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6634         memcpy(vni_m, vxlan_m->vni, size);
6635         for (i = 0; i < size; ++i)
6636                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6637 }
6638
6639 /**
6640  * Add VXLAN-GPE item to matcher and to the value.
6641  *
6642  * @param[in, out] matcher
6643  *   Flow matcher.
6644  * @param[in, out] key
6645  *   Flow matcher value.
6646  * @param[in] item
6647  *   Flow pattern to translate.
6648  * @param[in] inner
6649  *   Item is inner pattern.
6650  */
6651
6652 static void
6653 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6654                                  const struct rte_flow_item *item, int inner)
6655 {
6656         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6657         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6658         void *headers_m;
6659         void *headers_v;
6660         void *misc_m =
6661                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6662         void *misc_v =
6663                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6664         char *vni_m;
6665         char *vni_v;
6666         uint16_t dport;
6667         int size;
6668         int i;
6669         uint8_t flags_m = 0xff;
6670         uint8_t flags_v = 0xc;
6671
6672         if (inner) {
6673                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6674                                          inner_headers);
6675                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6676         } else {
6677                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6678                                          outer_headers);
6679                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6680         }
6681         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6682                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6683         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6684                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6685                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6686         }
6687         if (!vxlan_v)
6688                 return;
6689         if (!vxlan_m)
6690                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6691         size = sizeof(vxlan_m->vni);
6692         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6693         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6694         memcpy(vni_m, vxlan_m->vni, size);
6695         for (i = 0; i < size; ++i)
6696                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6697         if (vxlan_m->flags) {
6698                 flags_m = vxlan_m->flags;
6699                 flags_v = vxlan_v->flags;
6700         }
6701         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6702         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6703         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6704                  vxlan_m->protocol);
6705         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6706                  vxlan_v->protocol);
6707 }
6708
6709 /**
6710  * Add Geneve item to matcher and to the value.
6711  *
6712  * @param[in, out] matcher
6713  *   Flow matcher.
6714  * @param[in, out] key
6715  *   Flow matcher value.
6716  * @param[in] item
6717  *   Flow pattern to translate.
6718  * @param[in] inner
6719  *   Item is inner pattern.
6720  */
6721
6722 static void
6723 flow_dv_translate_item_geneve(void *matcher, void *key,
6724                               const struct rte_flow_item *item, int inner)
6725 {
6726         const struct rte_flow_item_geneve *geneve_m = item->mask;
6727         const struct rte_flow_item_geneve *geneve_v = item->spec;
6728         void *headers_m;
6729         void *headers_v;
6730         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6731         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6732         uint16_t dport;
6733         uint16_t gbhdr_m;
6734         uint16_t gbhdr_v;
6735         char *vni_m;
6736         char *vni_v;
6737         size_t size, i;
6738
6739         if (inner) {
6740                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6741                                          inner_headers);
6742                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6743         } else {
6744                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6745                                          outer_headers);
6746                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6747         }
6748         dport = MLX5_UDP_PORT_GENEVE;
6749         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6750                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6751                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6752         }
6753         if (!geneve_v)
6754                 return;
6755         if (!geneve_m)
6756                 geneve_m = &rte_flow_item_geneve_mask;
6757         size = sizeof(geneve_m->vni);
6758         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6759         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6760         memcpy(vni_m, geneve_m->vni, size);
6761         for (i = 0; i < size; ++i)
6762                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6763         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6764                  rte_be_to_cpu_16(geneve_m->protocol));
6765         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6766                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6767         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6768         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6769         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6770                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6771         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6772                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6773         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6774                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6775         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6776                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6777                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6778 }
6779
6780 /**
6781  * Add MPLS item to matcher and to the value.
6782  *
6783  * @param[in, out] matcher
6784  *   Flow matcher.
6785  * @param[in, out] key
6786  *   Flow matcher value.
6787  * @param[in] item
6788  *   Flow pattern to translate.
6789  * @param[in] prev_layer
6790  *   The protocol layer indicated in previous item.
6791  * @param[in] inner
6792  *   Item is inner pattern.
6793  */
6794 static void
6795 flow_dv_translate_item_mpls(void *matcher, void *key,
6796                             const struct rte_flow_item *item,
6797                             uint64_t prev_layer,
6798                             int inner)
6799 {
6800         const uint32_t *in_mpls_m = item->mask;
6801         const uint32_t *in_mpls_v = item->spec;
6802         uint32_t *out_mpls_m = 0;
6803         uint32_t *out_mpls_v = 0;
6804         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6805         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6806         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6807                                      misc_parameters_2);
6808         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6809         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6810         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6811
6812         switch (prev_layer) {
6813         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6814                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6815                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6816                          MLX5_UDP_PORT_MPLS);
6817                 break;
6818         case MLX5_FLOW_LAYER_GRE:
6819                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6820                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6821                          RTE_ETHER_TYPE_MPLS);
6822                 break;
6823         default:
6824                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6825                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6826                          IPPROTO_MPLS);
6827                 break;
6828         }
6829         if (!in_mpls_v)
6830                 return;
6831         if (!in_mpls_m)
6832                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6833         switch (prev_layer) {
6834         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6835                 out_mpls_m =
6836                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6837                                                  outer_first_mpls_over_udp);
6838                 out_mpls_v =
6839                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6840                                                  outer_first_mpls_over_udp);
6841                 break;
6842         case MLX5_FLOW_LAYER_GRE:
6843                 out_mpls_m =
6844                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6845                                                  outer_first_mpls_over_gre);
6846                 out_mpls_v =
6847                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6848                                                  outer_first_mpls_over_gre);
6849                 break;
6850         default:
6851                 /* Inner MPLS not over GRE is not supported. */
6852                 if (!inner) {
6853                         out_mpls_m =
6854                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6855                                                          misc2_m,
6856                                                          outer_first_mpls);
6857                         out_mpls_v =
6858                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6859                                                          misc2_v,
6860                                                          outer_first_mpls);
6861                 }
6862                 break;
6863         }
6864         if (out_mpls_m && out_mpls_v) {
6865                 *out_mpls_m = *in_mpls_m;
6866                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6867         }
6868 }
6869
6870 /**
6871  * Add metadata register item to matcher
6872  *
6873  * @param[in, out] matcher
6874  *   Flow matcher.
6875  * @param[in, out] key
6876  *   Flow matcher value.
6877  * @param[in] reg_type
6878  *   Type of device metadata register
6879  * @param[in] value
6880  *   Register value
6881  * @param[in] mask
6882  *   Register mask
6883  */
6884 static void
6885 flow_dv_match_meta_reg(void *matcher, void *key,
6886                        enum modify_reg reg_type,
6887                        uint32_t data, uint32_t mask)
6888 {
6889         void *misc2_m =
6890                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6891         void *misc2_v =
6892                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6893         uint32_t temp;
6894
6895         data &= mask;
6896         switch (reg_type) {
6897         case REG_A:
6898                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6899                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6900                 break;
6901         case REG_B:
6902                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6903                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6904                 break;
6905         case REG_C_0:
6906                 /*
6907                  * The metadata register C0 field might be divided into
6908                  * source vport index and META item value, we should set
6909                  * this field according to specified mask, not as whole one.
6910                  */
6911                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6912                 temp |= mask;
6913                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6914                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6915                 temp &= ~mask;
6916                 temp |= data;
6917                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6918                 break;
6919         case REG_C_1:
6920                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6921                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6922                 break;
6923         case REG_C_2:
6924                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6925                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6926                 break;
6927         case REG_C_3:
6928                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6929                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6930                 break;
6931         case REG_C_4:
6932                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6933                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6934                 break;
6935         case REG_C_5:
6936                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6937                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6938                 break;
6939         case REG_C_6:
6940                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6941                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6942                 break;
6943         case REG_C_7:
6944                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6945                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6946                 break;
6947         default:
6948                 MLX5_ASSERT(false);
6949                 break;
6950         }
6951 }
6952
6953 /**
6954  * Add MARK item to matcher
6955  *
6956  * @param[in] dev
6957  *   The device to configure through.
6958  * @param[in, out] matcher
6959  *   Flow matcher.
6960  * @param[in, out] key
6961  *   Flow matcher value.
6962  * @param[in] item
6963  *   Flow pattern to translate.
6964  */
6965 static void
6966 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6967                             void *matcher, void *key,
6968                             const struct rte_flow_item *item)
6969 {
6970         struct mlx5_priv *priv = dev->data->dev_private;
6971         const struct rte_flow_item_mark *mark;
6972         uint32_t value;
6973         uint32_t mask;
6974
6975         mark = item->mask ? (const void *)item->mask :
6976                             &rte_flow_item_mark_mask;
6977         mask = mark->id & priv->sh->dv_mark_mask;
6978         mark = (const void *)item->spec;
6979         MLX5_ASSERT(mark);
6980         value = mark->id & priv->sh->dv_mark_mask & mask;
6981         if (mask) {
6982                 enum modify_reg reg;
6983
6984                 /* Get the metadata register index for the mark. */
6985                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6986                 MLX5_ASSERT(reg > 0);
6987                 if (reg == REG_C_0) {
6988                         struct mlx5_priv *priv = dev->data->dev_private;
6989                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6990                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6991
6992                         mask &= msk_c0;
6993                         mask <<= shl_c0;
6994                         value <<= shl_c0;
6995                 }
6996                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6997         }
6998 }
6999
7000 /**
7001  * Add META item to matcher
7002  *
7003  * @param[in] dev
7004  *   The devich to configure through.
7005  * @param[in, out] matcher
7006  *   Flow matcher.
7007  * @param[in, out] key
7008  *   Flow matcher value.
7009  * @param[in] attr
7010  *   Attributes of flow that includes this item.
7011  * @param[in] item
7012  *   Flow pattern to translate.
7013  */
7014 static void
7015 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7016                             void *matcher, void *key,
7017                             const struct rte_flow_attr *attr,
7018                             const struct rte_flow_item *item)
7019 {
7020         const struct rte_flow_item_meta *meta_m;
7021         const struct rte_flow_item_meta *meta_v;
7022
7023         meta_m = (const void *)item->mask;
7024         if (!meta_m)
7025                 meta_m = &rte_flow_item_meta_mask;
7026         meta_v = (const void *)item->spec;
7027         if (meta_v) {
7028                 int reg;
7029                 uint32_t value = meta_v->data;
7030                 uint32_t mask = meta_m->data;
7031
7032                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7033                 if (reg < 0)
7034                         return;
7035                 /*
7036                  * In datapath code there is no endianness
7037                  * coversions for perfromance reasons, all
7038                  * pattern conversions are done in rte_flow.
7039                  */
7040                 value = rte_cpu_to_be_32(value);
7041                 mask = rte_cpu_to_be_32(mask);
7042                 if (reg == REG_C_0) {
7043                         struct mlx5_priv *priv = dev->data->dev_private;
7044                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7045                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7046 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7047                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7048
7049                         value >>= shr_c0;
7050                         mask >>= shr_c0;
7051 #endif
7052                         value <<= shl_c0;
7053                         mask <<= shl_c0;
7054                         MLX5_ASSERT(msk_c0);
7055                         MLX5_ASSERT(!(~msk_c0 & mask));
7056                 }
7057                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7058         }
7059 }
7060
7061 /**
7062  * Add vport metadata Reg C0 item to matcher
7063  *
7064  * @param[in, out] matcher
7065  *   Flow matcher.
7066  * @param[in, out] key
7067  *   Flow matcher value.
7068  * @param[in] reg
7069  *   Flow pattern to translate.
7070  */
7071 static void
7072 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7073                                   uint32_t value, uint32_t mask)
7074 {
7075         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7076 }
7077
7078 /**
7079  * Add tag item to matcher
7080  *
7081  * @param[in] dev
7082  *   The devich to configure through.
7083  * @param[in, out] matcher
7084  *   Flow matcher.
7085  * @param[in, out] key
7086  *   Flow matcher value.
7087  * @param[in] item
7088  *   Flow pattern to translate.
7089  */
7090 static void
7091 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7092                                 void *matcher, void *key,
7093                                 const struct rte_flow_item *item)
7094 {
7095         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7096         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7097         uint32_t mask, value;
7098
7099         MLX5_ASSERT(tag_v);
7100         value = tag_v->data;
7101         mask = tag_m ? tag_m->data : UINT32_MAX;
7102         if (tag_v->id == REG_C_0) {
7103                 struct mlx5_priv *priv = dev->data->dev_private;
7104                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7105                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7106
7107                 mask &= msk_c0;
7108                 mask <<= shl_c0;
7109                 value <<= shl_c0;
7110         }
7111         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7112 }
7113
7114 /**
7115  * Add TAG item to matcher
7116  *
7117  * @param[in] dev
7118  *   The devich to configure through.
7119  * @param[in, out] matcher
7120  *   Flow matcher.
7121  * @param[in, out] key
7122  *   Flow matcher value.
7123  * @param[in] item
7124  *   Flow pattern to translate.
7125  */
7126 static void
7127 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7128                            void *matcher, void *key,
7129                            const struct rte_flow_item *item)
7130 {
7131         const struct rte_flow_item_tag *tag_v = item->spec;
7132         const struct rte_flow_item_tag *tag_m = item->mask;
7133         enum modify_reg reg;
7134
7135         MLX5_ASSERT(tag_v);
7136         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7137         /* Get the metadata register index for the tag. */
7138         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7139         MLX5_ASSERT(reg > 0);
7140         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7141 }
7142
7143 /**
7144  * Add source vport match to the specified matcher.
7145  *
7146  * @param[in, out] matcher
7147  *   Flow matcher.
7148  * @param[in, out] key
7149  *   Flow matcher value.
7150  * @param[in] port
7151  *   Source vport value to match
7152  * @param[in] mask
7153  *   Mask
7154  */
7155 static void
7156 flow_dv_translate_item_source_vport(void *matcher, void *key,
7157                                     int16_t port, uint16_t mask)
7158 {
7159         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7160         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7161
7162         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7163         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7164 }
7165
7166 /**
7167  * Translate port-id item to eswitch match on  port-id.
7168  *
7169  * @param[in] dev
7170  *   The devich to configure through.
7171  * @param[in, out] matcher
7172  *   Flow matcher.
7173  * @param[in, out] key
7174  *   Flow matcher value.
7175  * @param[in] item
7176  *   Flow pattern to translate.
7177  *
7178  * @return
7179  *   0 on success, a negative errno value otherwise.
7180  */
7181 static int
7182 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7183                                void *key, const struct rte_flow_item *item)
7184 {
7185         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7186         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7187         struct mlx5_priv *priv;
7188         uint16_t mask, id;
7189
7190         mask = pid_m ? pid_m->id : 0xffff;
7191         id = pid_v ? pid_v->id : dev->data->port_id;
7192         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7193         if (!priv)
7194                 return -rte_errno;
7195         /* Translate to vport field or to metadata, depending on mode. */
7196         if (priv->vport_meta_mask)
7197                 flow_dv_translate_item_meta_vport(matcher, key,
7198                                                   priv->vport_meta_tag,
7199                                                   priv->vport_meta_mask);
7200         else
7201                 flow_dv_translate_item_source_vport(matcher, key,
7202                                                     priv->vport_id, mask);
7203         return 0;
7204 }
7205
7206 /**
7207  * Add ICMP6 item to matcher and to the value.
7208  *
7209  * @param[in, out] matcher
7210  *   Flow matcher.
7211  * @param[in, out] key
7212  *   Flow matcher value.
7213  * @param[in] item
7214  *   Flow pattern to translate.
7215  * @param[in] inner
7216  *   Item is inner pattern.
7217  */
7218 static void
7219 flow_dv_translate_item_icmp6(void *matcher, void *key,
7220                               const struct rte_flow_item *item,
7221                               int inner)
7222 {
7223         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7224         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7225         void *headers_m;
7226         void *headers_v;
7227         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7228                                      misc_parameters_3);
7229         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7230         if (inner) {
7231                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7232                                          inner_headers);
7233                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7234         } else {
7235                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7236                                          outer_headers);
7237                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7238         }
7239         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7240         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7241         if (!icmp6_v)
7242                 return;
7243         if (!icmp6_m)
7244                 icmp6_m = &rte_flow_item_icmp6_mask;
7245         /*
7246          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7247          * If only the protocol is specified, no need to match the frag.
7248          */
7249         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7250         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7251         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7252         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7253                  icmp6_v->type & icmp6_m->type);
7254         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7255         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7256                  icmp6_v->code & icmp6_m->code);
7257 }
7258
7259 /**
7260  * Add ICMP item to matcher and to the value.
7261  *
7262  * @param[in, out] matcher
7263  *   Flow matcher.
7264  * @param[in, out] key
7265  *   Flow matcher value.
7266  * @param[in] item
7267  *   Flow pattern to translate.
7268  * @param[in] inner
7269  *   Item is inner pattern.
7270  */
7271 static void
7272 flow_dv_translate_item_icmp(void *matcher, void *key,
7273                             const struct rte_flow_item *item,
7274                             int inner)
7275 {
7276         const struct rte_flow_item_icmp *icmp_m = item->mask;
7277         const struct rte_flow_item_icmp *icmp_v = item->spec;
7278         void *headers_m;
7279         void *headers_v;
7280         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7281                                      misc_parameters_3);
7282         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7283         if (inner) {
7284                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7285                                          inner_headers);
7286                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7287         } else {
7288                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7289                                          outer_headers);
7290                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7291         }
7292         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7293         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7294         if (!icmp_v)
7295                 return;
7296         if (!icmp_m)
7297                 icmp_m = &rte_flow_item_icmp_mask;
7298         /*
7299          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7300          * If only the protocol is specified, no need to match the frag.
7301          */
7302         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7303         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7304         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7305                  icmp_m->hdr.icmp_type);
7306         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7307                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7308         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7309                  icmp_m->hdr.icmp_code);
7310         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7311                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7312 }
7313
7314 /**
7315  * Add GTP item to matcher and to the value.
7316  *
7317  * @param[in, out] matcher
7318  *   Flow matcher.
7319  * @param[in, out] key
7320  *   Flow matcher value.
7321  * @param[in] item
7322  *   Flow pattern to translate.
7323  * @param[in] inner
7324  *   Item is inner pattern.
7325  */
7326 static void
7327 flow_dv_translate_item_gtp(void *matcher, void *key,
7328                            const struct rte_flow_item *item, int inner)
7329 {
7330         const struct rte_flow_item_gtp *gtp_m = item->mask;
7331         const struct rte_flow_item_gtp *gtp_v = item->spec;
7332         void *headers_m;
7333         void *headers_v;
7334         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7335                                      misc_parameters_3);
7336         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7337         uint16_t dport = RTE_GTPU_UDP_PORT;
7338
7339         if (inner) {
7340                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7341                                          inner_headers);
7342                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7343         } else {
7344                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7345                                          outer_headers);
7346                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7347         }
7348         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7349                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7350                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7351         }
7352         if (!gtp_v)
7353                 return;
7354         if (!gtp_m)
7355                 gtp_m = &rte_flow_item_gtp_mask;
7356         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7357                  gtp_m->v_pt_rsv_flags);
7358         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7359                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7360         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7361         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7362                  gtp_v->msg_type & gtp_m->msg_type);
7363         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7364                  rte_be_to_cpu_32(gtp_m->teid));
7365         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7366                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7367 }
7368
7369 /**
7370  * Add eCPRI item to matcher and to the value.
7371  *
7372  * @param[in] dev
7373  *   The devich to configure through.
7374  * @param[in, out] matcher
7375  *   Flow matcher.
7376  * @param[in, out] key
7377  *   Flow matcher value.
7378  * @param[in] item
7379  *   Flow pattern to translate.
7380  * @param[in] samples
7381  *   Sample IDs to be used in the matching.
7382  */
7383 static void
7384 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7385                              void *key, const struct rte_flow_item *item)
7386 {
7387         struct mlx5_priv *priv = dev->data->dev_private;
7388         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7389         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7390         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7391                                      misc_parameters_4);
7392         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7393         uint32_t *samples;
7394         void *dw_m;
7395         void *dw_v;
7396
7397         if (!ecpri_v)
7398                 return;
7399         if (!ecpri_m)
7400                 ecpri_m = &rte_flow_item_ecpri_mask;
7401         /*
7402          * Maximal four DW samples are supported in a single matching now.
7403          * Two are used now for a eCPRI matching:
7404          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7405          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7406          *    if any.
7407          */
7408         if (!ecpri_m->hdr.common.u32)
7409                 return;
7410         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7411         /* Need to take the whole DW as the mask to fill the entry. */
7412         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7413                             prog_sample_field_value_0);
7414         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7415                             prog_sample_field_value_0);
7416         /* Already big endian (network order) in the header. */
7417         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7418         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7419         /* Sample#0, used for matching type, offset 0. */
7420         MLX5_SET(fte_match_set_misc4, misc4_m,
7421                  prog_sample_field_id_0, samples[0]);
7422         /* It makes no sense to set the sample ID in the mask field. */
7423         MLX5_SET(fte_match_set_misc4, misc4_v,
7424                  prog_sample_field_id_0, samples[0]);
7425         /*
7426          * Checking if message body part needs to be matched.
7427          * Some wildcard rules only matching type field should be supported.
7428          */
7429         if (ecpri_m->hdr.dummy[0]) {
7430                 switch (ecpri_v->hdr.common.type) {
7431                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7432                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7433                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7434                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7435                                             prog_sample_field_value_1);
7436                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7437                                             prog_sample_field_value_1);
7438                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7439                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7440                         /* Sample#1, to match message body, offset 4. */
7441                         MLX5_SET(fte_match_set_misc4, misc4_m,
7442                                  prog_sample_field_id_1, samples[1]);
7443                         MLX5_SET(fte_match_set_misc4, misc4_v,
7444                                  prog_sample_field_id_1, samples[1]);
7445                         break;
7446                 default:
7447                         /* Others, do not match any sample ID. */
7448                         break;
7449                 }
7450         }
7451 }
7452
7453 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7454
7455 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7456         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7457                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7458
7459 /**
7460  * Calculate flow matcher enable bitmap.
7461  *
7462  * @param match_criteria
7463  *   Pointer to flow matcher criteria.
7464  *
7465  * @return
7466  *   Bitmap of enabled fields.
7467  */
7468 static uint8_t
7469 flow_dv_matcher_enable(uint32_t *match_criteria)
7470 {
7471         uint8_t match_criteria_enable;
7472
7473         match_criteria_enable =
7474                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7475                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7476         match_criteria_enable |=
7477                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7478                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7479         match_criteria_enable |=
7480                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7481                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7482         match_criteria_enable |=
7483                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7484                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7485         match_criteria_enable |=
7486                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7487                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7488         match_criteria_enable |=
7489                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7490                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7491         return match_criteria_enable;
7492 }
7493
7494
7495 /**
7496  * Get a flow table.
7497  *
7498  * @param[in, out] dev
7499  *   Pointer to rte_eth_dev structure.
7500  * @param[in] table_id
7501  *   Table id to use.
7502  * @param[in] egress
7503  *   Direction of the table.
7504  * @param[in] transfer
7505  *   E-Switch or NIC flow.
7506  * @param[out] error
7507  *   pointer to error structure.
7508  *
7509  * @return
7510  *   Returns tables resource based on the index, NULL in case of failed.
7511  */
7512 static struct mlx5_flow_tbl_resource *
7513 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7514                          uint32_t table_id, uint8_t egress,
7515                          uint8_t transfer,
7516                          struct rte_flow_error *error)
7517 {
7518         struct mlx5_priv *priv = dev->data->dev_private;
7519         struct mlx5_dev_ctx_shared *sh = priv->sh;
7520         struct mlx5_flow_tbl_resource *tbl;
7521         union mlx5_flow_tbl_key table_key = {
7522                 {
7523                         .table_id = table_id,
7524                         .reserved = 0,
7525                         .domain = !!transfer,
7526                         .direction = !!egress,
7527                 }
7528         };
7529         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7530                                                          table_key.v64);
7531         struct mlx5_flow_tbl_data_entry *tbl_data;
7532         uint32_t idx = 0;
7533         int ret;
7534         void *domain;
7535
7536         if (pos) {
7537                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7538                                         entry);
7539                 tbl = &tbl_data->tbl;
7540                 rte_atomic32_inc(&tbl->refcnt);
7541                 return tbl;
7542         }
7543         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7544         if (!tbl_data) {
7545                 rte_flow_error_set(error, ENOMEM,
7546                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7547                                    NULL,
7548                                    "cannot allocate flow table data entry");
7549                 return NULL;
7550         }
7551         tbl_data->idx = idx;
7552         tbl = &tbl_data->tbl;
7553         pos = &tbl_data->entry;
7554         if (transfer)
7555                 domain = sh->fdb_domain;
7556         else if (egress)
7557                 domain = sh->tx_domain;
7558         else
7559                 domain = sh->rx_domain;
7560         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7561         if (ret) {
7562                 rte_flow_error_set(error, ENOMEM,
7563                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7564                                    NULL, "cannot create flow table object");
7565                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7566                 return NULL;
7567         }
7568         /*
7569          * No multi-threads now, but still better to initialize the reference
7570          * count before insert it into the hash list.
7571          */
7572         rte_atomic32_init(&tbl->refcnt);
7573         /* Jump action reference count is initialized here. */
7574         rte_atomic32_init(&tbl_data->jump.refcnt);
7575         pos->key = table_key.v64;
7576         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7577         if (ret < 0) {
7578                 rte_flow_error_set(error, -ret,
7579                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7580                                    "cannot insert flow table data entry");
7581                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7582                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7583         }
7584         rte_atomic32_inc(&tbl->refcnt);
7585         return tbl;
7586 }
7587
7588 /**
7589  * Release a flow table.
7590  *
7591  * @param[in] dev
7592  *   Pointer to rte_eth_dev structure.
7593  * @param[in] tbl
7594  *   Table resource to be released.
7595  *
7596  * @return
7597  *   Returns 0 if table was released, else return 1;
7598  */
7599 static int
7600 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7601                              struct mlx5_flow_tbl_resource *tbl)
7602 {
7603         struct mlx5_priv *priv = dev->data->dev_private;
7604         struct mlx5_dev_ctx_shared *sh = priv->sh;
7605         struct mlx5_flow_tbl_data_entry *tbl_data =
7606                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7607
7608         if (!tbl)
7609                 return 0;
7610         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7611                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7612
7613                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7614                 tbl->obj = NULL;
7615                 /* remove the entry from the hash list and free memory. */
7616                 mlx5_hlist_remove(sh->flow_tbls, pos);
7617                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7618                                 tbl_data->idx);
7619                 return 0;
7620         }
7621         return 1;
7622 }
7623
7624 /**
7625  * Register the flow matcher.
7626  *
7627  * @param[in, out] dev
7628  *   Pointer to rte_eth_dev structure.
7629  * @param[in, out] matcher
7630  *   Pointer to flow matcher.
7631  * @param[in, out] key
7632  *   Pointer to flow table key.
7633  * @parm[in, out] dev_flow
7634  *   Pointer to the dev_flow.
7635  * @param[out] error
7636  *   pointer to error structure.
7637  *
7638  * @return
7639  *   0 on success otherwise -errno and errno is set.
7640  */
7641 static int
7642 flow_dv_matcher_register(struct rte_eth_dev *dev,
7643                          struct mlx5_flow_dv_matcher *matcher,
7644                          union mlx5_flow_tbl_key *key,
7645                          struct mlx5_flow *dev_flow,
7646                          struct rte_flow_error *error)
7647 {
7648         struct mlx5_priv *priv = dev->data->dev_private;
7649         struct mlx5_dev_ctx_shared *sh = priv->sh;
7650         struct mlx5_flow_dv_matcher *cache_matcher;
7651         struct mlx5dv_flow_matcher_attr dv_attr = {
7652                 .type = IBV_FLOW_ATTR_NORMAL,
7653                 .match_mask = (void *)&matcher->mask,
7654         };
7655         struct mlx5_flow_tbl_resource *tbl;
7656         struct mlx5_flow_tbl_data_entry *tbl_data;
7657         int ret;
7658
7659         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7660                                        key->domain, error);
7661         if (!tbl)
7662                 return -rte_errno;      /* No need to refill the error info */
7663         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7664         /* Lookup from cache. */
7665         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7666                 if (matcher->crc == cache_matcher->crc &&
7667                     matcher->priority == cache_matcher->priority &&
7668                     !memcmp((const void *)matcher->mask.buf,
7669                             (const void *)cache_matcher->mask.buf,
7670                             cache_matcher->mask.size)) {
7671                         DRV_LOG(DEBUG,
7672                                 "%s group %u priority %hd use %s "
7673                                 "matcher %p: refcnt %d++",
7674                                 key->domain ? "FDB" : "NIC", key->table_id,
7675                                 cache_matcher->priority,
7676                                 key->direction ? "tx" : "rx",
7677                                 (void *)cache_matcher,
7678                                 rte_atomic32_read(&cache_matcher->refcnt));
7679                         rte_atomic32_inc(&cache_matcher->refcnt);
7680                         dev_flow->handle->dvh.matcher = cache_matcher;
7681                         /* old matcher should not make the table ref++. */
7682                         flow_dv_tbl_resource_release(dev, tbl);
7683                         return 0;
7684                 }
7685         }
7686         /* Register new matcher. */
7687         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7688                                     SOCKET_ID_ANY);
7689         if (!cache_matcher) {
7690                 flow_dv_tbl_resource_release(dev, tbl);
7691                 return rte_flow_error_set(error, ENOMEM,
7692                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7693                                           "cannot allocate matcher memory");
7694         }
7695         *cache_matcher = *matcher;
7696         dv_attr.match_criteria_enable =
7697                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7698         dv_attr.priority = matcher->priority;
7699         if (key->direction)
7700                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7701         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7702                                                &cache_matcher->matcher_object);
7703         if (ret) {
7704                 mlx5_free(cache_matcher);
7705 #ifdef HAVE_MLX5DV_DR
7706                 flow_dv_tbl_resource_release(dev, tbl);
7707 #endif
7708                 return rte_flow_error_set(error, ENOMEM,
7709                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7710                                           NULL, "cannot create matcher");
7711         }
7712         /* Save the table information */
7713         cache_matcher->tbl = tbl;
7714         rte_atomic32_init(&cache_matcher->refcnt);
7715         /* only matcher ref++, table ref++ already done above in get API. */
7716         rte_atomic32_inc(&cache_matcher->refcnt);
7717         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7718         dev_flow->handle->dvh.matcher = cache_matcher;
7719         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7720                 key->domain ? "FDB" : "NIC", key->table_id,
7721                 cache_matcher->priority,
7722                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7723                 rte_atomic32_read(&cache_matcher->refcnt));
7724         return 0;
7725 }
7726
7727 /**
7728  * Find existing tag resource or create and register a new one.
7729  *
7730  * @param dev[in, out]
7731  *   Pointer to rte_eth_dev structure.
7732  * @param[in, out] tag_be24
7733  *   Tag value in big endian then R-shift 8.
7734  * @parm[in, out] dev_flow
7735  *   Pointer to the dev_flow.
7736  * @param[out] error
7737  *   pointer to error structure.
7738  *
7739  * @return
7740  *   0 on success otherwise -errno and errno is set.
7741  */
7742 static int
7743 flow_dv_tag_resource_register
7744                         (struct rte_eth_dev *dev,
7745                          uint32_t tag_be24,
7746                          struct mlx5_flow *dev_flow,
7747                          struct rte_flow_error *error)
7748 {
7749         struct mlx5_priv *priv = dev->data->dev_private;
7750         struct mlx5_dev_ctx_shared *sh = priv->sh;
7751         struct mlx5_flow_dv_tag_resource *cache_resource;
7752         struct mlx5_hlist_entry *entry;
7753         int ret;
7754
7755         /* Lookup a matching resource from cache. */
7756         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7757         if (entry) {
7758                 cache_resource = container_of
7759                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7760                 rte_atomic32_inc(&cache_resource->refcnt);
7761                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7762                 dev_flow->dv.tag_resource = cache_resource;
7763                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7764                         (void *)cache_resource,
7765                         rte_atomic32_read(&cache_resource->refcnt));
7766                 return 0;
7767         }
7768         /* Register new resource. */
7769         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7770                                        &dev_flow->handle->dvh.rix_tag);
7771         if (!cache_resource)
7772                 return rte_flow_error_set(error, ENOMEM,
7773                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7774                                           "cannot allocate resource memory");
7775         cache_resource->entry.key = (uint64_t)tag_be24;
7776         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7777                                                   &cache_resource->action);
7778         if (ret) {
7779                 mlx5_free(cache_resource);
7780                 return rte_flow_error_set(error, ENOMEM,
7781                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7782                                           NULL, "cannot create action");
7783         }
7784         rte_atomic32_init(&cache_resource->refcnt);
7785         rte_atomic32_inc(&cache_resource->refcnt);
7786         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7787                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7788                 mlx5_free(cache_resource);
7789                 return rte_flow_error_set(error, EEXIST,
7790                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7791                                           NULL, "cannot insert tag");
7792         }
7793         dev_flow->dv.tag_resource = cache_resource;
7794         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7795                 (void *)cache_resource,
7796                 rte_atomic32_read(&cache_resource->refcnt));
7797         return 0;
7798 }
7799
7800 /**
7801  * Release the tag.
7802  *
7803  * @param dev
7804  *   Pointer to Ethernet device.
7805  * @param tag_idx
7806  *   Tag index.
7807  *
7808  * @return
7809  *   1 while a reference on it exists, 0 when freed.
7810  */
7811 static int
7812 flow_dv_tag_release(struct rte_eth_dev *dev,
7813                     uint32_t tag_idx)
7814 {
7815         struct mlx5_priv *priv = dev->data->dev_private;
7816         struct mlx5_dev_ctx_shared *sh = priv->sh;
7817         struct mlx5_flow_dv_tag_resource *tag;
7818
7819         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7820         if (!tag)
7821                 return 0;
7822         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7823                 dev->data->port_id, (void *)tag,
7824                 rte_atomic32_read(&tag->refcnt));
7825         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7826                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7827                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7828                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7829                         dev->data->port_id, (void *)tag);
7830                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7831                 return 0;
7832         }
7833         return 1;
7834 }
7835
7836 /**
7837  * Translate port ID action to vport.
7838  *
7839  * @param[in] dev
7840  *   Pointer to rte_eth_dev structure.
7841  * @param[in] action
7842  *   Pointer to the port ID action.
7843  * @param[out] dst_port_id
7844  *   The target port ID.
7845  * @param[out] error
7846  *   Pointer to the error structure.
7847  *
7848  * @return
7849  *   0 on success, a negative errno value otherwise and rte_errno is set.
7850  */
7851 static int
7852 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7853                                  const struct rte_flow_action *action,
7854                                  uint32_t *dst_port_id,
7855                                  struct rte_flow_error *error)
7856 {
7857         uint32_t port;
7858         struct mlx5_priv *priv;
7859         const struct rte_flow_action_port_id *conf =
7860                         (const struct rte_flow_action_port_id *)action->conf;
7861
7862         port = conf->original ? dev->data->port_id : conf->id;
7863         priv = mlx5_port_to_eswitch_info(port, false);
7864         if (!priv)
7865                 return rte_flow_error_set(error, -rte_errno,
7866                                           RTE_FLOW_ERROR_TYPE_ACTION,
7867                                           NULL,
7868                                           "No eswitch info was found for port");
7869 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7870         /*
7871          * This parameter is transferred to
7872          * mlx5dv_dr_action_create_dest_ib_port().
7873          */
7874         *dst_port_id = priv->dev_port;
7875 #else
7876         /*
7877          * Legacy mode, no LAG configurations is supported.
7878          * This parameter is transferred to
7879          * mlx5dv_dr_action_create_dest_vport().
7880          */
7881         *dst_port_id = priv->vport_id;
7882 #endif
7883         return 0;
7884 }
7885
7886 /**
7887  * Create a counter with aging configuration.
7888  *
7889  * @param[in] dev
7890  *   Pointer to rte_eth_dev structure.
7891  * @param[out] count
7892  *   Pointer to the counter action configuration.
7893  * @param[in] age
7894  *   Pointer to the aging action configuration.
7895  *
7896  * @return
7897  *   Index to flow counter on success, 0 otherwise.
7898  */
7899 static uint32_t
7900 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7901                                 struct mlx5_flow *dev_flow,
7902                                 const struct rte_flow_action_count *count,
7903                                 const struct rte_flow_action_age *age)
7904 {
7905         uint32_t counter;
7906         struct mlx5_age_param *age_param;
7907
7908         counter = flow_dv_counter_alloc(dev,
7909                                 count ? count->shared : 0,
7910                                 count ? count->id : 0,
7911                                 dev_flow->dv.group, !!age);
7912         if (!counter || age == NULL)
7913                 return counter;
7914         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7915         /*
7916          * The counter age accuracy may have a bit delay. Have 3/4
7917          * second bias on the timeount in order to let it age in time.
7918          */
7919         age_param->context = age->context ? age->context :
7920                 (void *)(uintptr_t)(dev_flow->flow_idx);
7921         /*
7922          * The counter age accuracy may have a bit delay. Have 3/4
7923          * second bias on the timeount in order to let it age in time.
7924          */
7925         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7926         /* Set expire time in unit of 0.1 sec. */
7927         age_param->port_id = dev->data->port_id;
7928         age_param->expire = age_param->timeout +
7929                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7930         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7931         return counter;
7932 }
7933 /**
7934  * Add Tx queue matcher
7935  *
7936  * @param[in] dev
7937  *   Pointer to the dev struct.
7938  * @param[in, out] matcher
7939  *   Flow matcher.
7940  * @param[in, out] key
7941  *   Flow matcher value.
7942  * @param[in] item
7943  *   Flow pattern to translate.
7944  * @param[in] inner
7945  *   Item is inner pattern.
7946  */
7947 static void
7948 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7949                                 void *matcher, void *key,
7950                                 const struct rte_flow_item *item)
7951 {
7952         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7953         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7954         void *misc_m =
7955                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7956         void *misc_v =
7957                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7958         struct mlx5_txq_ctrl *txq;
7959         uint32_t queue;
7960
7961
7962         queue_m = (const void *)item->mask;
7963         if (!queue_m)
7964                 return;
7965         queue_v = (const void *)item->spec;
7966         if (!queue_v)
7967                 return;
7968         txq = mlx5_txq_get(dev, queue_v->queue);
7969         if (!txq)
7970                 return;
7971         queue = txq->obj->sq->id;
7972         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7973         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7974                  queue & queue_m->queue);
7975         mlx5_txq_release(dev, queue_v->queue);
7976 }
7977
7978 /**
7979  * Set the hash fields according to the @p flow information.
7980  *
7981  * @param[in] dev_flow
7982  *   Pointer to the mlx5_flow.
7983  * @param[in] rss_desc
7984  *   Pointer to the mlx5_flow_rss_desc.
7985  */
7986 static void
7987 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7988                        struct mlx5_flow_rss_desc *rss_desc)
7989 {
7990         uint64_t items = dev_flow->handle->layers;
7991         int rss_inner = 0;
7992         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7993
7994         dev_flow->hash_fields = 0;
7995 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7996         if (rss_desc->level >= 2) {
7997                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7998                 rss_inner = 1;
7999         }
8000 #endif
8001         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8002             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8003                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8004                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8005                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8006                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8007                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8008                         else
8009                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8010                 }
8011         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8012                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8013                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8014                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8015                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8016                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8017                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8018                         else
8019                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8020                 }
8021         }
8022         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8023             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8024                 if (rss_types & ETH_RSS_UDP) {
8025                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8026                                 dev_flow->hash_fields |=
8027                                                 IBV_RX_HASH_SRC_PORT_UDP;
8028                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8029                                 dev_flow->hash_fields |=
8030                                                 IBV_RX_HASH_DST_PORT_UDP;
8031                         else
8032                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8033                 }
8034         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8035                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8036                 if (rss_types & ETH_RSS_TCP) {
8037                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8038                                 dev_flow->hash_fields |=
8039                                                 IBV_RX_HASH_SRC_PORT_TCP;
8040                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8041                                 dev_flow->hash_fields |=
8042                                                 IBV_RX_HASH_DST_PORT_TCP;
8043                         else
8044                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8045                 }
8046         }
8047 }
8048
8049 /**
8050  * Fill the flow with DV spec, lock free
8051  * (mutex should be acquired by caller).
8052  *
8053  * @param[in] dev
8054  *   Pointer to rte_eth_dev structure.
8055  * @param[in, out] dev_flow
8056  *   Pointer to the sub flow.
8057  * @param[in] attr
8058  *   Pointer to the flow attributes.
8059  * @param[in] items
8060  *   Pointer to the list of items.
8061  * @param[in] actions
8062  *   Pointer to the list of actions.
8063  * @param[out] error
8064  *   Pointer to the error structure.
8065  *
8066  * @return
8067  *   0 on success, a negative errno value otherwise and rte_errno is set.
8068  */
8069 static int
8070 __flow_dv_translate(struct rte_eth_dev *dev,
8071                     struct mlx5_flow *dev_flow,
8072                     const struct rte_flow_attr *attr,
8073                     const struct rte_flow_item items[],
8074                     const struct rte_flow_action actions[],
8075                     struct rte_flow_error *error)
8076 {
8077         struct mlx5_priv *priv = dev->data->dev_private;
8078         struct mlx5_dev_config *dev_conf = &priv->config;
8079         struct rte_flow *flow = dev_flow->flow;
8080         struct mlx5_flow_handle *handle = dev_flow->handle;
8081         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8082                                               priv->rss_desc)
8083                                               [!!priv->flow_nested_idx];
8084         uint64_t item_flags = 0;
8085         uint64_t last_item = 0;
8086         uint64_t action_flags = 0;
8087         uint64_t priority = attr->priority;
8088         struct mlx5_flow_dv_matcher matcher = {
8089                 .mask = {
8090                         .size = sizeof(matcher.mask.buf) -
8091                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8092                 },
8093         };
8094         int actions_n = 0;
8095         bool actions_end = false;
8096         union {
8097                 struct mlx5_flow_dv_modify_hdr_resource res;
8098                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8099                             sizeof(struct mlx5_modification_cmd) *
8100                             (MLX5_MAX_MODIFY_NUM + 1)];
8101         } mhdr_dummy;
8102         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8103         const struct rte_flow_action_count *count = NULL;
8104         const struct rte_flow_action_age *age = NULL;
8105         union flow_dv_attr flow_attr = { .attr = 0 };
8106         uint32_t tag_be;
8107         union mlx5_flow_tbl_key tbl_key;
8108         uint32_t modify_action_position = UINT32_MAX;
8109         void *match_mask = matcher.mask.buf;
8110         void *match_value = dev_flow->dv.value.buf;
8111         uint8_t next_protocol = 0xff;
8112         struct rte_vlan_hdr vlan = { 0 };
8113         uint32_t table;
8114         int ret = 0;
8115
8116         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8117                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8118         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8119                                        !!priv->fdb_def_rule, &table, error);
8120         if (ret)
8121                 return ret;
8122         dev_flow->dv.group = table;
8123         if (attr->transfer)
8124                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8125         if (priority == MLX5_FLOW_PRIO_RSVD)
8126                 priority = dev_conf->flow_prio - 1;
8127         /* number of actions must be set to 0 in case of dirty stack. */
8128         mhdr_res->actions_num = 0;
8129         for (; !actions_end ; actions++) {
8130                 const struct rte_flow_action_queue *queue;
8131                 const struct rte_flow_action_rss *rss;
8132                 const struct rte_flow_action *action = actions;
8133                 const uint8_t *rss_key;
8134                 const struct rte_flow_action_jump *jump_data;
8135                 const struct rte_flow_action_meter *mtr;
8136                 struct mlx5_flow_tbl_resource *tbl;
8137                 uint32_t port_id = 0;
8138                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8139                 int action_type = actions->type;
8140                 const struct rte_flow_action *found_action = NULL;
8141                 struct mlx5_flow_meter *fm = NULL;
8142
8143                 if (!mlx5_flow_os_action_supported(action_type))
8144                         return rte_flow_error_set(error, ENOTSUP,
8145                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8146                                                   actions,
8147                                                   "action not supported");
8148                 switch (action_type) {
8149                 case RTE_FLOW_ACTION_TYPE_VOID:
8150                         break;
8151                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8152                         if (flow_dv_translate_action_port_id(dev, action,
8153                                                              &port_id, error))
8154                                 return -rte_errno;
8155                         port_id_resource.port_id = port_id;
8156                         MLX5_ASSERT(!handle->rix_port_id_action);
8157                         if (flow_dv_port_id_action_resource_register
8158                             (dev, &port_id_resource, dev_flow, error))
8159                                 return -rte_errno;
8160                         dev_flow->dv.actions[actions_n++] =
8161                                         dev_flow->dv.port_id_action->action;
8162                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8163                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8164                         break;
8165                 case RTE_FLOW_ACTION_TYPE_FLAG:
8166                         action_flags |= MLX5_FLOW_ACTION_FLAG;
8167                         dev_flow->handle->mark = 1;
8168                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8169                                 struct rte_flow_action_mark mark = {
8170                                         .id = MLX5_FLOW_MARK_DEFAULT,
8171                                 };
8172
8173                                 if (flow_dv_convert_action_mark(dev, &mark,
8174                                                                 mhdr_res,
8175                                                                 error))
8176                                         return -rte_errno;
8177                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8178                                 break;
8179                         }
8180                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8181                         /*
8182                          * Only one FLAG or MARK is supported per device flow
8183                          * right now. So the pointer to the tag resource must be
8184                          * zero before the register process.
8185                          */
8186                         MLX5_ASSERT(!handle->dvh.rix_tag);
8187                         if (flow_dv_tag_resource_register(dev, tag_be,
8188                                                           dev_flow, error))
8189                                 return -rte_errno;
8190                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8191                         dev_flow->dv.actions[actions_n++] =
8192                                         dev_flow->dv.tag_resource->action;
8193                         break;
8194                 case RTE_FLOW_ACTION_TYPE_MARK:
8195                         action_flags |= MLX5_FLOW_ACTION_MARK;
8196                         dev_flow->handle->mark = 1;
8197                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8198                                 const struct rte_flow_action_mark *mark =
8199                                         (const struct rte_flow_action_mark *)
8200                                                 actions->conf;
8201
8202                                 if (flow_dv_convert_action_mark(dev, mark,
8203                                                                 mhdr_res,
8204                                                                 error))
8205                                         return -rte_errno;
8206                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8207                                 break;
8208                         }
8209                         /* Fall-through */
8210                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8211                         /* Legacy (non-extensive) MARK action. */
8212                         tag_be = mlx5_flow_mark_set
8213                               (((const struct rte_flow_action_mark *)
8214                                (actions->conf))->id);
8215                         MLX5_ASSERT(!handle->dvh.rix_tag);
8216                         if (flow_dv_tag_resource_register(dev, tag_be,
8217                                                           dev_flow, error))
8218                                 return -rte_errno;
8219                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8220                         dev_flow->dv.actions[actions_n++] =
8221                                         dev_flow->dv.tag_resource->action;
8222                         break;
8223                 case RTE_FLOW_ACTION_TYPE_SET_META:
8224                         if (flow_dv_convert_action_set_meta
8225                                 (dev, mhdr_res, attr,
8226                                  (const struct rte_flow_action_set_meta *)
8227                                   actions->conf, error))
8228                                 return -rte_errno;
8229                         action_flags |= MLX5_FLOW_ACTION_SET_META;
8230                         break;
8231                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8232                         if (flow_dv_convert_action_set_tag
8233                                 (dev, mhdr_res,
8234                                  (const struct rte_flow_action_set_tag *)
8235                                   actions->conf, error))
8236                                 return -rte_errno;
8237                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8238                         break;
8239                 case RTE_FLOW_ACTION_TYPE_DROP:
8240                         action_flags |= MLX5_FLOW_ACTION_DROP;
8241                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8242                         break;
8243                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8244                         queue = actions->conf;
8245                         rss_desc->queue_num = 1;
8246                         rss_desc->queue[0] = queue->index;
8247                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8248                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8249                         break;
8250                 case RTE_FLOW_ACTION_TYPE_RSS:
8251                         rss = actions->conf;
8252                         memcpy(rss_desc->queue, rss->queue,
8253                                rss->queue_num * sizeof(uint16_t));
8254                         rss_desc->queue_num = rss->queue_num;
8255                         /* NULL RSS key indicates default RSS key. */
8256                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
8257                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8258                         /*
8259                          * rss->level and rss.types should be set in advance
8260                          * when expanding items for RSS.
8261                          */
8262                         action_flags |= MLX5_FLOW_ACTION_RSS;
8263                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8264                         break;
8265                 case RTE_FLOW_ACTION_TYPE_AGE:
8266                 case RTE_FLOW_ACTION_TYPE_COUNT:
8267                         if (!dev_conf->devx) {
8268                                 return rte_flow_error_set
8269                                               (error, ENOTSUP,
8270                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8271                                                NULL,
8272                                                "count action not supported");
8273                         }
8274                         /* Save information first, will apply later. */
8275                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8276                                 count = action->conf;
8277                         else
8278                                 age = action->conf;
8279                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8280                         break;
8281                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8282                         dev_flow->dv.actions[actions_n++] =
8283                                                 priv->sh->pop_vlan_action;
8284                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8285                         break;
8286                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8287                         if (!(action_flags &
8288                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8289                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8290                         vlan.eth_proto = rte_be_to_cpu_16
8291                              ((((const struct rte_flow_action_of_push_vlan *)
8292                                                    actions->conf)->ethertype));
8293                         found_action = mlx5_flow_find_action
8294                                         (actions + 1,
8295                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8296                         if (found_action)
8297                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8298                         found_action = mlx5_flow_find_action
8299                                         (actions + 1,
8300                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8301                         if (found_action)
8302                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8303                         if (flow_dv_create_action_push_vlan
8304                                             (dev, attr, &vlan, dev_flow, error))
8305                                 return -rte_errno;
8306                         dev_flow->dv.actions[actions_n++] =
8307                                         dev_flow->dv.push_vlan_res->action;
8308                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8309                         break;
8310                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8311                         /* of_vlan_push action handled this action */
8312                         MLX5_ASSERT(action_flags &
8313                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8314                         break;
8315                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8316                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8317                                 break;
8318                         flow_dev_get_vlan_info_from_items(items, &vlan);
8319                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8320                         /* If no VLAN push - this is a modify header action */
8321                         if (flow_dv_convert_action_modify_vlan_vid
8322                                                 (mhdr_res, actions, error))
8323                                 return -rte_errno;
8324                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8325                         break;
8326                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8327                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8328                         if (flow_dv_create_action_l2_encap(dev, actions,
8329                                                            dev_flow,
8330                                                            attr->transfer,
8331                                                            error))
8332                                 return -rte_errno;
8333                         dev_flow->dv.actions[actions_n++] =
8334                                         dev_flow->dv.encap_decap->action;
8335                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8336                         break;
8337                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8338                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8339                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8340                                                            attr->transfer,
8341                                                            error))
8342                                 return -rte_errno;
8343                         dev_flow->dv.actions[actions_n++] =
8344                                         dev_flow->dv.encap_decap->action;
8345                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8346                         break;
8347                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8348                         /* Handle encap with preceding decap. */
8349                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8350                                 if (flow_dv_create_action_raw_encap
8351                                         (dev, actions, dev_flow, attr, error))
8352                                         return -rte_errno;
8353                                 dev_flow->dv.actions[actions_n++] =
8354                                         dev_flow->dv.encap_decap->action;
8355                         } else {
8356                                 /* Handle encap without preceding decap. */
8357                                 if (flow_dv_create_action_l2_encap
8358                                     (dev, actions, dev_flow, attr->transfer,
8359                                      error))
8360                                         return -rte_errno;
8361                                 dev_flow->dv.actions[actions_n++] =
8362                                         dev_flow->dv.encap_decap->action;
8363                         }
8364                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8365                         break;
8366                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8367                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8368                                 ;
8369                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8370                                 if (flow_dv_create_action_l2_decap
8371                                     (dev, dev_flow, attr->transfer, error))
8372                                         return -rte_errno;
8373                                 dev_flow->dv.actions[actions_n++] =
8374                                         dev_flow->dv.encap_decap->action;
8375                         }
8376                         /* If decap is followed by encap, handle it at encap. */
8377                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8378                         break;
8379                 case RTE_FLOW_ACTION_TYPE_JUMP:
8380                         jump_data = action->conf;
8381                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8382                                                        jump_data->group,
8383                                                        !!priv->fdb_def_rule,
8384                                                        &table, error);
8385                         if (ret)
8386                                 return ret;
8387                         tbl = flow_dv_tbl_resource_get(dev, table,
8388                                                        attr->egress,
8389                                                        attr->transfer, error);
8390                         if (!tbl)
8391                                 return rte_flow_error_set
8392                                                 (error, errno,
8393                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8394                                                  NULL,
8395                                                  "cannot create jump action.");
8396                         if (flow_dv_jump_tbl_resource_register
8397                             (dev, tbl, dev_flow, error)) {
8398                                 flow_dv_tbl_resource_release(dev, tbl);
8399                                 return rte_flow_error_set
8400                                                 (error, errno,
8401                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8402                                                  NULL,
8403                                                  "cannot create jump action.");
8404                         }
8405                         dev_flow->dv.actions[actions_n++] =
8406                                         dev_flow->dv.jump->action;
8407                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8408                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8409                         break;
8410                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8411                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8412                         if (flow_dv_convert_action_modify_mac
8413                                         (mhdr_res, actions, error))
8414                                 return -rte_errno;
8415                         action_flags |= actions->type ==
8416                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8417                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8418                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8419                         break;
8420                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8421                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8422                         if (flow_dv_convert_action_modify_ipv4
8423                                         (mhdr_res, actions, error))
8424                                 return -rte_errno;
8425                         action_flags |= actions->type ==
8426                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8427                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8428                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8429                         break;
8430                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8431                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8432                         if (flow_dv_convert_action_modify_ipv6
8433                                         (mhdr_res, actions, error))
8434                                 return -rte_errno;
8435                         action_flags |= actions->type ==
8436                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8437                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8438                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8439                         break;
8440                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8441                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8442                         if (flow_dv_convert_action_modify_tp
8443                                         (mhdr_res, actions, items,
8444                                          &flow_attr, dev_flow, !!(action_flags &
8445                                          MLX5_FLOW_ACTION_DECAP), error))
8446                                 return -rte_errno;
8447                         action_flags |= actions->type ==
8448                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8449                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8450                                         MLX5_FLOW_ACTION_SET_TP_DST;
8451                         break;
8452                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8453                         if (flow_dv_convert_action_modify_dec_ttl
8454                                         (mhdr_res, items, &flow_attr, dev_flow,
8455                                          !!(action_flags &
8456                                          MLX5_FLOW_ACTION_DECAP), error))
8457                                 return -rte_errno;
8458                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8459                         break;
8460                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8461                         if (flow_dv_convert_action_modify_ttl
8462                                         (mhdr_res, actions, items, &flow_attr,
8463                                          dev_flow, !!(action_flags &
8464                                          MLX5_FLOW_ACTION_DECAP), error))
8465                                 return -rte_errno;
8466                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8467                         break;
8468                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8469                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8470                         if (flow_dv_convert_action_modify_tcp_seq
8471                                         (mhdr_res, actions, error))
8472                                 return -rte_errno;
8473                         action_flags |= actions->type ==
8474                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8475                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8476                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8477                         break;
8478
8479                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8480                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8481                         if (flow_dv_convert_action_modify_tcp_ack
8482                                         (mhdr_res, actions, error))
8483                                 return -rte_errno;
8484                         action_flags |= actions->type ==
8485                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8486                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8487                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8488                         break;
8489                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8490                         if (flow_dv_convert_action_set_reg
8491                                         (mhdr_res, actions, error))
8492                                 return -rte_errno;
8493                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8494                         break;
8495                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8496                         if (flow_dv_convert_action_copy_mreg
8497                                         (dev, mhdr_res, actions, error))
8498                                 return -rte_errno;
8499                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8500                         break;
8501                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8502                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8503                         dev_flow->handle->fate_action =
8504                                         MLX5_FLOW_FATE_DEFAULT_MISS;
8505                         break;
8506                 case RTE_FLOW_ACTION_TYPE_METER:
8507                         mtr = actions->conf;
8508                         if (!flow->meter) {
8509                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8510                                                             attr, error);
8511                                 if (!fm)
8512                                         return rte_flow_error_set(error,
8513                                                 rte_errno,
8514                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8515                                                 NULL,
8516                                                 "meter not found "
8517                                                 "or invalid parameters");
8518                                 flow->meter = fm->idx;
8519                         }
8520                         /* Set the meter action. */
8521                         if (!fm) {
8522                                 fm = mlx5_ipool_get(priv->sh->ipool
8523                                                 [MLX5_IPOOL_MTR], flow->meter);
8524                                 if (!fm)
8525                                         return rte_flow_error_set(error,
8526                                                 rte_errno,
8527                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8528                                                 NULL,
8529                                                 "meter not found "
8530                                                 "or invalid parameters");
8531                         }
8532                         dev_flow->dv.actions[actions_n++] =
8533                                 fm->mfts->meter_action;
8534                         action_flags |= MLX5_FLOW_ACTION_METER;
8535                         break;
8536                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8537                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8538                                                               actions, error))
8539                                 return -rte_errno;
8540                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8541                         break;
8542                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8543                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8544                                                               actions, error))
8545                                 return -rte_errno;
8546                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8547                         break;
8548                 case RTE_FLOW_ACTION_TYPE_END:
8549                         actions_end = true;
8550                         if (mhdr_res->actions_num) {
8551                                 /* create modify action if needed. */
8552                                 if (flow_dv_modify_hdr_resource_register
8553                                         (dev, mhdr_res, dev_flow, error))
8554                                         return -rte_errno;
8555                                 dev_flow->dv.actions[modify_action_position] =
8556                                         handle->dvh.modify_hdr->action;
8557                         }
8558                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8559                                 flow->counter =
8560                                         flow_dv_translate_create_counter(dev,
8561                                                 dev_flow, count, age);
8562
8563                                 if (!flow->counter)
8564                                         return rte_flow_error_set
8565                                                 (error, rte_errno,
8566                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8567                                                 NULL,
8568                                                 "cannot create counter"
8569                                                 " object.");
8570                                 dev_flow->dv.actions[actions_n++] =
8571                                           (flow_dv_counter_get_by_idx(dev,
8572                                           flow->counter, NULL))->action;
8573                         }
8574                         break;
8575                 default:
8576                         break;
8577                 }
8578                 if (mhdr_res->actions_num &&
8579                     modify_action_position == UINT32_MAX)
8580                         modify_action_position = actions_n++;
8581         }
8582         dev_flow->dv.actions_n = actions_n;
8583         dev_flow->act_flags = action_flags;
8584         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8585                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8586                 int item_type = items->type;
8587
8588                 if (!mlx5_flow_os_item_supported(item_type))
8589                         return rte_flow_error_set(error, ENOTSUP,
8590                                                   RTE_FLOW_ERROR_TYPE_ITEM,
8591                                                   NULL, "item not supported");
8592                 switch (item_type) {
8593                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8594                         flow_dv_translate_item_port_id(dev, match_mask,
8595                                                        match_value, items);
8596                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8597                         break;
8598                 case RTE_FLOW_ITEM_TYPE_ETH:
8599                         flow_dv_translate_item_eth(match_mask, match_value,
8600                                                    items, tunnel,
8601                                                    dev_flow->dv.group);
8602                         matcher.priority = action_flags &
8603                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
8604                                         !dev_flow->external ?
8605                                         MLX5_PRIORITY_MAP_L3 :
8606                                         MLX5_PRIORITY_MAP_L2;
8607                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8608                                              MLX5_FLOW_LAYER_OUTER_L2;
8609                         break;
8610                 case RTE_FLOW_ITEM_TYPE_VLAN:
8611                         flow_dv_translate_item_vlan(dev_flow,
8612                                                     match_mask, match_value,
8613                                                     items, tunnel,
8614                                                     dev_flow->dv.group);
8615                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8616                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8617                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8618                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8619                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8620                         break;
8621                 case RTE_FLOW_ITEM_TYPE_IPV4:
8622                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8623                                                   &item_flags, &tunnel);
8624                         flow_dv_translate_item_ipv4(match_mask, match_value,
8625                                                     items, item_flags, tunnel,
8626                                                     dev_flow->dv.group);
8627                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8628                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8629                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8630                         if (items->mask != NULL &&
8631                             ((const struct rte_flow_item_ipv4 *)
8632                              items->mask)->hdr.next_proto_id) {
8633                                 next_protocol =
8634                                         ((const struct rte_flow_item_ipv4 *)
8635                                          (items->spec))->hdr.next_proto_id;
8636                                 next_protocol &=
8637                                         ((const struct rte_flow_item_ipv4 *)
8638                                          (items->mask))->hdr.next_proto_id;
8639                         } else {
8640                                 /* Reset for inner layer. */
8641                                 next_protocol = 0xff;
8642                         }
8643                         break;
8644                 case RTE_FLOW_ITEM_TYPE_IPV6:
8645                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8646                                                   &item_flags, &tunnel);
8647                         flow_dv_translate_item_ipv6(match_mask, match_value,
8648                                                     items, item_flags, tunnel,
8649                                                     dev_flow->dv.group);
8650                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8651                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8652                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8653                         if (items->mask != NULL &&
8654                             ((const struct rte_flow_item_ipv6 *)
8655                              items->mask)->hdr.proto) {
8656                                 next_protocol =
8657                                         ((const struct rte_flow_item_ipv6 *)
8658                                          items->spec)->hdr.proto;
8659                                 next_protocol &=
8660                                         ((const struct rte_flow_item_ipv6 *)
8661                                          items->mask)->hdr.proto;
8662                         } else {
8663                                 /* Reset for inner layer. */
8664                                 next_protocol = 0xff;
8665                         }
8666                         break;
8667                 case RTE_FLOW_ITEM_TYPE_TCP:
8668                         flow_dv_translate_item_tcp(match_mask, match_value,
8669                                                    items, tunnel);
8670                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8671                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8672                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8673                         break;
8674                 case RTE_FLOW_ITEM_TYPE_UDP:
8675                         flow_dv_translate_item_udp(match_mask, match_value,
8676                                                    items, tunnel);
8677                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8678                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8679                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8680                         break;
8681                 case RTE_FLOW_ITEM_TYPE_GRE:
8682                         flow_dv_translate_item_gre(match_mask, match_value,
8683                                                    items, tunnel);
8684                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8685                         last_item = MLX5_FLOW_LAYER_GRE;
8686                         break;
8687                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8688                         flow_dv_translate_item_gre_key(match_mask,
8689                                                        match_value, items);
8690                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8691                         break;
8692                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8693                         flow_dv_translate_item_nvgre(match_mask, match_value,
8694                                                      items, tunnel);
8695                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8696                         last_item = MLX5_FLOW_LAYER_GRE;
8697                         break;
8698                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8699                         flow_dv_translate_item_vxlan(match_mask, match_value,
8700                                                      items, tunnel);
8701                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8702                         last_item = MLX5_FLOW_LAYER_VXLAN;
8703                         break;
8704                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8705                         flow_dv_translate_item_vxlan_gpe(match_mask,
8706                                                          match_value, items,
8707                                                          tunnel);
8708                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8709                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8710                         break;
8711                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8712                         flow_dv_translate_item_geneve(match_mask, match_value,
8713                                                       items, tunnel);
8714                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8715                         last_item = MLX5_FLOW_LAYER_GENEVE;
8716                         break;
8717                 case RTE_FLOW_ITEM_TYPE_MPLS:
8718                         flow_dv_translate_item_mpls(match_mask, match_value,
8719                                                     items, last_item, tunnel);
8720                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8721                         last_item = MLX5_FLOW_LAYER_MPLS;
8722                         break;
8723                 case RTE_FLOW_ITEM_TYPE_MARK:
8724                         flow_dv_translate_item_mark(dev, match_mask,
8725                                                     match_value, items);
8726                         last_item = MLX5_FLOW_ITEM_MARK;
8727                         break;
8728                 case RTE_FLOW_ITEM_TYPE_META:
8729                         flow_dv_translate_item_meta(dev, match_mask,
8730                                                     match_value, attr, items);
8731                         last_item = MLX5_FLOW_ITEM_METADATA;
8732                         break;
8733                 case RTE_FLOW_ITEM_TYPE_ICMP:
8734                         flow_dv_translate_item_icmp(match_mask, match_value,
8735                                                     items, tunnel);
8736                         last_item = MLX5_FLOW_LAYER_ICMP;
8737                         break;
8738                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8739                         flow_dv_translate_item_icmp6(match_mask, match_value,
8740                                                       items, tunnel);
8741                         last_item = MLX5_FLOW_LAYER_ICMP6;
8742                         break;
8743                 case RTE_FLOW_ITEM_TYPE_TAG:
8744                         flow_dv_translate_item_tag(dev, match_mask,
8745                                                    match_value, items);
8746                         last_item = MLX5_FLOW_ITEM_TAG;
8747                         break;
8748                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8749                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8750                                                         match_value, items);
8751                         last_item = MLX5_FLOW_ITEM_TAG;
8752                         break;
8753                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8754                         flow_dv_translate_item_tx_queue(dev, match_mask,
8755                                                         match_value,
8756                                                         items);
8757                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8758                         break;
8759                 case RTE_FLOW_ITEM_TYPE_GTP:
8760                         flow_dv_translate_item_gtp(match_mask, match_value,
8761                                                    items, tunnel);
8762                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8763                         last_item = MLX5_FLOW_LAYER_GTP;
8764                         break;
8765                 case RTE_FLOW_ITEM_TYPE_ECPRI:
8766                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
8767                                 /* Create it only the first time to be used. */
8768                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
8769                                 if (ret)
8770                                         return rte_flow_error_set
8771                                                 (error, -ret,
8772                                                 RTE_FLOW_ERROR_TYPE_ITEM,
8773                                                 NULL,
8774                                                 "cannot create eCPRI parser");
8775                         }
8776                         /* Adjust the length matcher and device flow value. */
8777                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8778                         dev_flow->dv.value.size =
8779                                         MLX5_ST_SZ_BYTES(fte_match_param);
8780                         flow_dv_translate_item_ecpri(dev, match_mask,
8781                                                      match_value, items);
8782                         /* No other protocol should follow eCPRI layer. */
8783                         last_item = MLX5_FLOW_LAYER_ECPRI;
8784                         break;
8785                 default:
8786                         break;
8787                 }
8788                 item_flags |= last_item;
8789         }
8790         /*
8791          * When E-Switch mode is enabled, we have two cases where we need to
8792          * set the source port manually.
8793          * The first one, is in case of Nic steering rule, and the second is
8794          * E-Switch rule where no port_id item was found. In both cases
8795          * the source port is set according the current port in use.
8796          */
8797         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8798             (priv->representor || priv->master)) {
8799                 if (flow_dv_translate_item_port_id(dev, match_mask,
8800                                                    match_value, NULL))
8801                         return -rte_errno;
8802         }
8803 #ifdef RTE_LIBRTE_MLX5_DEBUG
8804         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8805                                               dev_flow->dv.value.buf));
8806 #endif
8807         /*
8808          * Layers may be already initialized from prefix flow if this dev_flow
8809          * is the suffix flow.
8810          */
8811         handle->layers |= item_flags;
8812         if (action_flags & MLX5_FLOW_ACTION_RSS)
8813                 flow_dv_hashfields_set(dev_flow, rss_desc);
8814         /* Register matcher. */
8815         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8816                                     matcher.mask.size);
8817         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8818                                                      matcher.priority);
8819         /* reserved field no needs to be set to 0 here. */
8820         tbl_key.domain = attr->transfer;
8821         tbl_key.direction = attr->egress;
8822         tbl_key.table_id = dev_flow->dv.group;
8823         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8824                 return -rte_errno;
8825         return 0;
8826 }
8827
8828 /**
8829  * Apply the flow to the NIC, lock free,
8830  * (mutex should be acquired by caller).
8831  *
8832  * @param[in] dev
8833  *   Pointer to the Ethernet device structure.
8834  * @param[in, out] flow
8835  *   Pointer to flow structure.
8836  * @param[out] error
8837  *   Pointer to error structure.
8838  *
8839  * @return
8840  *   0 on success, a negative errno value otherwise and rte_errno is set.
8841  */
8842 static int
8843 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8844                 struct rte_flow_error *error)
8845 {
8846         struct mlx5_flow_dv_workspace *dv;
8847         struct mlx5_flow_handle *dh;
8848         struct mlx5_flow_handle_dv *dv_h;
8849         struct mlx5_flow *dev_flow;
8850         struct mlx5_priv *priv = dev->data->dev_private;
8851         uint32_t handle_idx;
8852         int n;
8853         int err;
8854         int idx;
8855
8856         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8857                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8858                 dv = &dev_flow->dv;
8859                 dh = dev_flow->handle;
8860                 dv_h = &dh->dvh;
8861                 n = dv->actions_n;
8862                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8863                         if (dv->transfer) {
8864                                 dv->actions[n++] = priv->sh->esw_drop_action;
8865                         } else {
8866                                 struct mlx5_hrxq *drop_hrxq;
8867                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8868                                 if (!drop_hrxq) {
8869                                         rte_flow_error_set
8870                                                 (error, errno,
8871                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8872                                                  NULL,
8873                                                  "cannot get drop hash queue");
8874                                         goto error;
8875                                 }
8876                                 /*
8877                                  * Drop queues will be released by the specify
8878                                  * mlx5_hrxq_drop_release() function. Assign
8879                                  * the special index to hrxq to mark the queue
8880                                  * has been allocated.
8881                                  */
8882                                 dh->rix_hrxq = UINT32_MAX;
8883                                 dv->actions[n++] = drop_hrxq->action;
8884                         }
8885                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8886                         struct mlx5_hrxq *hrxq;
8887                         uint32_t hrxq_idx;
8888                         struct mlx5_flow_rss_desc *rss_desc =
8889                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8890                                 [!!priv->flow_nested_idx];
8891
8892                         MLX5_ASSERT(rss_desc->queue_num);
8893                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8894                                                  MLX5_RSS_HASH_KEY_LEN,
8895                                                  dev_flow->hash_fields,
8896                                                  rss_desc->queue,
8897                                                  rss_desc->queue_num);
8898                         if (!hrxq_idx) {
8899                                 hrxq_idx = mlx5_hrxq_new
8900                                                 (dev, rss_desc->key,
8901                                                 MLX5_RSS_HASH_KEY_LEN,
8902                                                 dev_flow->hash_fields,
8903                                                 rss_desc->queue,
8904                                                 rss_desc->queue_num,
8905                                                 !!(dh->layers &
8906                                                 MLX5_FLOW_LAYER_TUNNEL));
8907                         }
8908                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8909                                               hrxq_idx);
8910                         if (!hrxq) {
8911                                 rte_flow_error_set
8912                                         (error, rte_errno,
8913                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8914                                          "cannot get hash queue");
8915                                 goto error;
8916                         }
8917                         dh->rix_hrxq = hrxq_idx;
8918                         dv->actions[n++] = hrxq->action;
8919                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8920                         if (flow_dv_default_miss_resource_register
8921                                         (dev, error)) {
8922                                 rte_flow_error_set
8923                                         (error, rte_errno,
8924                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8925                                          "cannot create default miss resource");
8926                                 goto error_default_miss;
8927                         }
8928                         dh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;
8929                         dv->actions[n++] = priv->sh->default_miss.action;
8930                 }
8931                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8932                                                (void *)&dv->value, n,
8933                                                dv->actions, &dh->drv_flow);
8934                 if (err) {
8935                         rte_flow_error_set(error, errno,
8936                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8937                                            NULL,
8938                                            "hardware refuses to create flow");
8939                         goto error;
8940                 }
8941                 if (priv->vmwa_context &&
8942                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8943                         /*
8944                          * The rule contains the VLAN pattern.
8945                          * For VF we are going to create VLAN
8946                          * interface to make hypervisor set correct
8947                          * e-Switch vport context.
8948                          */
8949                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8950                 }
8951         }
8952         return 0;
8953 error:
8954         if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8955                 flow_dv_default_miss_resource_release(dev);
8956 error_default_miss:
8957         err = rte_errno; /* Save rte_errno before cleanup. */
8958         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8959                        handle_idx, dh, next) {
8960                 /* hrxq is union, don't clear it if the flag is not set. */
8961                 if (dh->rix_hrxq) {
8962                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8963                                 mlx5_hrxq_drop_release(dev);
8964                                 dh->rix_hrxq = 0;
8965                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8966                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8967                                 dh->rix_hrxq = 0;
8968                         }
8969                 }
8970                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8971                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8972         }
8973         rte_errno = err; /* Restore rte_errno. */
8974         return -rte_errno;
8975 }
8976
8977 /**
8978  * Release the flow matcher.
8979  *
8980  * @param dev
8981  *   Pointer to Ethernet device.
8982  * @param handle
8983  *   Pointer to mlx5_flow_handle.
8984  *
8985  * @return
8986  *   1 while a reference on it exists, 0 when freed.
8987  */
8988 static int
8989 flow_dv_matcher_release(struct rte_eth_dev *dev,
8990                         struct mlx5_flow_handle *handle)
8991 {
8992         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8993
8994         MLX5_ASSERT(matcher->matcher_object);
8995         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8996                 dev->data->port_id, (void *)matcher,
8997                 rte_atomic32_read(&matcher->refcnt));
8998         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8999                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9000                            (matcher->matcher_object));
9001                 LIST_REMOVE(matcher, next);
9002                 /* table ref-- in release interface. */
9003                 flow_dv_tbl_resource_release(dev, matcher->tbl);
9004                 mlx5_free(matcher);
9005                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
9006                         dev->data->port_id, (void *)matcher);
9007                 return 0;
9008         }
9009         return 1;
9010 }
9011
9012 /**
9013  * Release an encap/decap resource.
9014  *
9015  * @param dev
9016  *   Pointer to Ethernet device.
9017  * @param handle
9018  *   Pointer to mlx5_flow_handle.
9019  *
9020  * @return
9021  *   1 while a reference on it exists, 0 when freed.
9022  */
9023 static int
9024 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
9025                                      struct mlx5_flow_handle *handle)
9026 {
9027         struct mlx5_priv *priv = dev->data->dev_private;
9028         uint32_t idx = handle->dvh.rix_encap_decap;
9029         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
9030
9031         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9032                          idx);
9033         if (!cache_resource)
9034                 return 0;
9035         MLX5_ASSERT(cache_resource->action);
9036         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
9037                 (void *)cache_resource,
9038                 rte_atomic32_read(&cache_resource->refcnt));
9039         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9040                 claim_zero(mlx5_flow_os_destroy_flow_action
9041                                                 (cache_resource->action));
9042                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
9043                              &priv->sh->encaps_decaps, idx,
9044                              cache_resource, next);
9045                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
9046                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
9047                         (void *)cache_resource);
9048                 return 0;
9049         }
9050         return 1;
9051 }
9052
9053 /**
9054  * Release an jump to table action resource.
9055  *
9056  * @param dev
9057  *   Pointer to Ethernet device.
9058  * @param handle
9059  *   Pointer to mlx5_flow_handle.
9060  *
9061  * @return
9062  *   1 while a reference on it exists, 0 when freed.
9063  */
9064 static int
9065 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
9066                                   struct mlx5_flow_handle *handle)
9067 {
9068         struct mlx5_priv *priv = dev->data->dev_private;
9069         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
9070         struct mlx5_flow_tbl_data_entry *tbl_data;
9071
9072         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
9073                              handle->rix_jump);
9074         if (!tbl_data)
9075                 return 0;
9076         cache_resource = &tbl_data->jump;
9077         MLX5_ASSERT(cache_resource->action);
9078         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
9079                 (void *)cache_resource,
9080                 rte_atomic32_read(&cache_resource->refcnt));
9081         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9082                 claim_zero(mlx5_flow_os_destroy_flow_action
9083                                                 (cache_resource->action));
9084                 /* jump action memory free is inside the table release. */
9085                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9086                 DRV_LOG(DEBUG, "jump table resource %p: removed",
9087                         (void *)cache_resource);
9088                 return 0;
9089         }
9090         return 1;
9091 }
9092
9093 /**
9094  * Release a default miss resource.
9095  *
9096  * @param dev
9097  *   Pointer to Ethernet device.
9098  * @return
9099  *   1 while a reference on it exists, 0 when freed.
9100  */
9101 static int
9102 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9103 {
9104         struct mlx5_priv *priv = dev->data->dev_private;
9105         struct mlx5_dev_ctx_shared *sh = priv->sh;
9106         struct mlx5_flow_default_miss_resource *cache_resource =
9107                         &sh->default_miss;
9108
9109         MLX5_ASSERT(cache_resource->action);
9110         DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9111                         (void *)cache_resource->action,
9112                         rte_atomic32_read(&cache_resource->refcnt));
9113         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9114                 claim_zero(mlx5_glue->destroy_flow_action
9115                                 (cache_resource->action));
9116                 DRV_LOG(DEBUG, "default miss resource %p: removed",
9117                                 (void *)cache_resource->action);
9118                 return 0;
9119         }
9120         return 1;
9121 }
9122
9123 /**
9124  * Release a modify-header resource.
9125  *
9126  * @param handle
9127  *   Pointer to mlx5_flow_handle.
9128  *
9129  * @return
9130  *   1 while a reference on it exists, 0 when freed.
9131  */
9132 static int
9133 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9134 {
9135         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9136                                                         handle->dvh.modify_hdr;
9137
9138         MLX5_ASSERT(cache_resource->action);
9139         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9140                 (void *)cache_resource,
9141                 rte_atomic32_read(&cache_resource->refcnt));
9142         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9143                 claim_zero(mlx5_flow_os_destroy_flow_action
9144                                                 (cache_resource->action));
9145                 LIST_REMOVE(cache_resource, next);
9146                 mlx5_free(cache_resource);
9147                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9148                         (void *)cache_resource);
9149                 return 0;
9150         }
9151         return 1;
9152 }
9153
9154 /**
9155  * Release port ID action resource.
9156  *
9157  * @param dev
9158  *   Pointer to Ethernet device.
9159  * @param handle
9160  *   Pointer to mlx5_flow_handle.
9161  *
9162  * @return
9163  *   1 while a reference on it exists, 0 when freed.
9164  */
9165 static int
9166 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9167                                         struct mlx5_flow_handle *handle)
9168 {
9169         struct mlx5_priv *priv = dev->data->dev_private;
9170         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9171         uint32_t idx = handle->rix_port_id_action;
9172
9173         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9174                                         idx);
9175         if (!cache_resource)
9176                 return 0;
9177         MLX5_ASSERT(cache_resource->action);
9178         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9179                 (void *)cache_resource,
9180                 rte_atomic32_read(&cache_resource->refcnt));
9181         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9182                 claim_zero(mlx5_flow_os_destroy_flow_action
9183                                                 (cache_resource->action));
9184                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9185                              &priv->sh->port_id_action_list, idx,
9186                              cache_resource, next);
9187                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9188                 DRV_LOG(DEBUG, "port id action resource %p: removed",
9189                         (void *)cache_resource);
9190                 return 0;
9191         }
9192         return 1;
9193 }
9194
9195 /**
9196  * Release push vlan action resource.
9197  *
9198  * @param dev
9199  *   Pointer to Ethernet device.
9200  * @param handle
9201  *   Pointer to mlx5_flow_handle.
9202  *
9203  * @return
9204  *   1 while a reference on it exists, 0 when freed.
9205  */
9206 static int
9207 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9208                                           struct mlx5_flow_handle *handle)
9209 {
9210         struct mlx5_priv *priv = dev->data->dev_private;
9211         uint32_t idx = handle->dvh.rix_push_vlan;
9212         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9213
9214         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9215                                         idx);
9216         if (!cache_resource)
9217                 return 0;
9218         MLX5_ASSERT(cache_resource->action);
9219         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9220                 (void *)cache_resource,
9221                 rte_atomic32_read(&cache_resource->refcnt));
9222         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9223                 claim_zero(mlx5_flow_os_destroy_flow_action
9224                                                 (cache_resource->action));
9225                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9226                              &priv->sh->push_vlan_action_list, idx,
9227                              cache_resource, next);
9228                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9229                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9230                         (void *)cache_resource);
9231                 return 0;
9232         }
9233         return 1;
9234 }
9235
9236 /**
9237  * Release the fate resource.
9238  *
9239  * @param dev
9240  *   Pointer to Ethernet device.
9241  * @param handle
9242  *   Pointer to mlx5_flow_handle.
9243  */
9244 static void
9245 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9246                                struct mlx5_flow_handle *handle)
9247 {
9248         if (!handle->rix_fate)
9249                 return;
9250         switch (handle->fate_action) {
9251         case MLX5_FLOW_FATE_DROP:
9252                 mlx5_hrxq_drop_release(dev);
9253                 break;
9254         case MLX5_FLOW_FATE_QUEUE:
9255                 mlx5_hrxq_release(dev, handle->rix_hrxq);
9256                 break;
9257         case MLX5_FLOW_FATE_JUMP:
9258                 flow_dv_jump_tbl_resource_release(dev, handle);
9259                 break;
9260         case MLX5_FLOW_FATE_PORT_ID:
9261                 flow_dv_port_id_action_resource_release(dev, handle);
9262                 break;
9263         case MLX5_FLOW_FATE_DEFAULT_MISS:
9264                 flow_dv_default_miss_resource_release(dev);
9265                 break;
9266         default:
9267                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9268                 break;
9269         }
9270         handle->rix_fate = 0;
9271 }
9272
9273 /**
9274  * Remove the flow from the NIC but keeps it in memory.
9275  * Lock free, (mutex should be acquired by caller).
9276  *
9277  * @param[in] dev
9278  *   Pointer to Ethernet device.
9279  * @param[in, out] flow
9280  *   Pointer to flow structure.
9281  */
9282 static void
9283 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9284 {
9285         struct mlx5_flow_handle *dh;
9286         uint32_t handle_idx;
9287         struct mlx5_priv *priv = dev->data->dev_private;
9288
9289         if (!flow)
9290                 return;
9291         handle_idx = flow->dev_handles;
9292         while (handle_idx) {
9293                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9294                                     handle_idx);
9295                 if (!dh)
9296                         return;
9297                 if (dh->drv_flow) {
9298                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9299                         dh->drv_flow = NULL;
9300                 }
9301                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9302                     dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9303                     dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9304                         flow_dv_fate_resource_release(dev, dh);
9305                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9306                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9307                 handle_idx = dh->next.next;
9308         }
9309 }
9310
9311 /**
9312  * Remove the flow from the NIC and the memory.
9313  * Lock free, (mutex should be acquired by caller).
9314  *
9315  * @param[in] dev
9316  *   Pointer to the Ethernet device structure.
9317  * @param[in, out] flow
9318  *   Pointer to flow structure.
9319  */
9320 static void
9321 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9322 {
9323         struct mlx5_flow_handle *dev_handle;
9324         struct mlx5_priv *priv = dev->data->dev_private;
9325
9326         if (!flow)
9327                 return;
9328         __flow_dv_remove(dev, flow);
9329         if (flow->counter) {
9330                 flow_dv_counter_release(dev, flow->counter);
9331                 flow->counter = 0;
9332         }
9333         if (flow->meter) {
9334                 struct mlx5_flow_meter *fm;
9335
9336                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9337                                     flow->meter);
9338                 if (fm)
9339                         mlx5_flow_meter_detach(fm);
9340                 flow->meter = 0;
9341         }
9342         while (flow->dev_handles) {
9343                 uint32_t tmp_idx = flow->dev_handles;
9344
9345                 dev_handle = mlx5_ipool_get(priv->sh->ipool
9346                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9347                 if (!dev_handle)
9348                         return;
9349                 flow->dev_handles = dev_handle->next.next;
9350                 if (dev_handle->dvh.matcher)
9351                         flow_dv_matcher_release(dev, dev_handle);
9352                 if (dev_handle->dvh.rix_encap_decap)
9353                         flow_dv_encap_decap_resource_release(dev, dev_handle);
9354                 if (dev_handle->dvh.modify_hdr)
9355                         flow_dv_modify_hdr_resource_release(dev_handle);
9356                 if (dev_handle->dvh.rix_push_vlan)
9357                         flow_dv_push_vlan_action_resource_release(dev,
9358                                                                   dev_handle);
9359                 if (dev_handle->dvh.rix_tag)
9360                         flow_dv_tag_release(dev,
9361                                             dev_handle->dvh.rix_tag);
9362                 flow_dv_fate_resource_release(dev, dev_handle);
9363                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9364                            tmp_idx);
9365         }
9366 }
9367
9368 /**
9369  * Query a dv flow  rule for its statistics via devx.
9370  *
9371  * @param[in] dev
9372  *   Pointer to Ethernet device.
9373  * @param[in] flow
9374  *   Pointer to the sub flow.
9375  * @param[out] data
9376  *   data retrieved by the query.
9377  * @param[out] error
9378  *   Perform verbose error reporting if not NULL.
9379  *
9380  * @return
9381  *   0 on success, a negative errno value otherwise and rte_errno is set.
9382  */
9383 static int
9384 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9385                     void *data, struct rte_flow_error *error)
9386 {
9387         struct mlx5_priv *priv = dev->data->dev_private;
9388         struct rte_flow_query_count *qc = data;
9389
9390         if (!priv->config.devx)
9391                 return rte_flow_error_set(error, ENOTSUP,
9392                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9393                                           NULL,
9394                                           "counters are not supported");
9395         if (flow->counter) {
9396                 uint64_t pkts, bytes;
9397                 struct mlx5_flow_counter *cnt;
9398
9399                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9400                                                  NULL);
9401                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9402                                                &bytes);
9403
9404                 if (err)
9405                         return rte_flow_error_set(error, -err,
9406                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9407                                         NULL, "cannot read counters");
9408                 qc->hits_set = 1;
9409                 qc->bytes_set = 1;
9410                 qc->hits = pkts - cnt->hits;
9411                 qc->bytes = bytes - cnt->bytes;
9412                 if (qc->reset) {
9413                         cnt->hits = pkts;
9414                         cnt->bytes = bytes;
9415                 }
9416                 return 0;
9417         }
9418         return rte_flow_error_set(error, EINVAL,
9419                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9420                                   NULL,
9421                                   "counters are not available");
9422 }
9423
9424 /**
9425  * Query a flow.
9426  *
9427  * @see rte_flow_query()
9428  * @see rte_flow_ops
9429  */
9430 static int
9431 flow_dv_query(struct rte_eth_dev *dev,
9432               struct rte_flow *flow __rte_unused,
9433               const struct rte_flow_action *actions __rte_unused,
9434               void *data __rte_unused,
9435               struct rte_flow_error *error __rte_unused)
9436 {
9437         int ret = -EINVAL;
9438
9439         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9440                 switch (actions->type) {
9441                 case RTE_FLOW_ACTION_TYPE_VOID:
9442                         break;
9443                 case RTE_FLOW_ACTION_TYPE_COUNT:
9444                         ret = flow_dv_query_count(dev, flow, data, error);
9445                         break;
9446                 default:
9447                         return rte_flow_error_set(error, ENOTSUP,
9448                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9449                                                   actions,
9450                                                   "action not supported");
9451                 }
9452         }
9453         return ret;
9454 }
9455
9456 /**
9457  * Destroy the meter table set.
9458  * Lock free, (mutex should be acquired by caller).
9459  *
9460  * @param[in] dev
9461  *   Pointer to Ethernet device.
9462  * @param[in] tbl
9463  *   Pointer to the meter table set.
9464  *
9465  * @return
9466  *   Always 0.
9467  */
9468 static int
9469 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9470                         struct mlx5_meter_domains_infos *tbl)
9471 {
9472         struct mlx5_priv *priv = dev->data->dev_private;
9473         struct mlx5_meter_domains_infos *mtd =
9474                                 (struct mlx5_meter_domains_infos *)tbl;
9475
9476         if (!mtd || !priv->config.dv_flow_en)
9477                 return 0;
9478         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9479                 claim_zero(mlx5_flow_os_destroy_flow
9480                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9481         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9482                 claim_zero(mlx5_flow_os_destroy_flow
9483                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9484         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9485                 claim_zero(mlx5_flow_os_destroy_flow
9486                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9487         if (mtd->egress.color_matcher)
9488                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9489                            (mtd->egress.color_matcher));
9490         if (mtd->egress.any_matcher)
9491                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9492                            (mtd->egress.any_matcher));
9493         if (mtd->egress.tbl)
9494                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9495         if (mtd->egress.sfx_tbl)
9496                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9497         if (mtd->ingress.color_matcher)
9498                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9499                            (mtd->ingress.color_matcher));
9500         if (mtd->ingress.any_matcher)
9501                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9502                            (mtd->ingress.any_matcher));
9503         if (mtd->ingress.tbl)
9504                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9505         if (mtd->ingress.sfx_tbl)
9506                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9507         if (mtd->transfer.color_matcher)
9508                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9509                            (mtd->transfer.color_matcher));
9510         if (mtd->transfer.any_matcher)
9511                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9512                            (mtd->transfer.any_matcher));
9513         if (mtd->transfer.tbl)
9514                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9515         if (mtd->transfer.sfx_tbl)
9516                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9517         if (mtd->drop_actn)
9518                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9519         mlx5_free(mtd);
9520         return 0;
9521 }
9522
9523 /* Number of meter flow actions, count and jump or count and drop. */
9524 #define METER_ACTIONS 2
9525
9526 /**
9527  * Create specify domain meter table and suffix table.
9528  *
9529  * @param[in] dev
9530  *   Pointer to Ethernet device.
9531  * @param[in,out] mtb
9532  *   Pointer to DV meter table set.
9533  * @param[in] egress
9534  *   Table attribute.
9535  * @param[in] transfer
9536  *   Table attribute.
9537  * @param[in] color_reg_c_idx
9538  *   Reg C index for color match.
9539  *
9540  * @return
9541  *   0 on success, -1 otherwise and rte_errno is set.
9542  */
9543 static int
9544 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9545                            struct mlx5_meter_domains_infos *mtb,
9546                            uint8_t egress, uint8_t transfer,
9547                            uint32_t color_reg_c_idx)
9548 {
9549         struct mlx5_priv *priv = dev->data->dev_private;
9550         struct mlx5_dev_ctx_shared *sh = priv->sh;
9551         struct mlx5_flow_dv_match_params mask = {
9552                 .size = sizeof(mask.buf),
9553         };
9554         struct mlx5_flow_dv_match_params value = {
9555                 .size = sizeof(value.buf),
9556         };
9557         struct mlx5dv_flow_matcher_attr dv_attr = {
9558                 .type = IBV_FLOW_ATTR_NORMAL,
9559                 .priority = 0,
9560                 .match_criteria_enable = 0,
9561                 .match_mask = (void *)&mask,
9562         };
9563         void *actions[METER_ACTIONS];
9564         struct mlx5_meter_domain_info *dtb;
9565         struct rte_flow_error error;
9566         int i = 0;
9567         int ret;
9568
9569         if (transfer)
9570                 dtb = &mtb->transfer;
9571         else if (egress)
9572                 dtb = &mtb->egress;
9573         else
9574                 dtb = &mtb->ingress;
9575         /* Create the meter table with METER level. */
9576         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9577                                             egress, transfer, &error);
9578         if (!dtb->tbl) {
9579                 DRV_LOG(ERR, "Failed to create meter policer table.");
9580                 return -1;
9581         }
9582         /* Create the meter suffix table with SUFFIX level. */
9583         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9584                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9585                                             egress, transfer, &error);
9586         if (!dtb->sfx_tbl) {
9587                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9588                 return -1;
9589         }
9590         /* Create matchers, Any and Color. */
9591         dv_attr.priority = 3;
9592         dv_attr.match_criteria_enable = 0;
9593         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9594                                                &dtb->any_matcher);
9595         if (ret) {
9596                 DRV_LOG(ERR, "Failed to create meter"
9597                              " policer default matcher.");
9598                 goto error_exit;
9599         }
9600         dv_attr.priority = 0;
9601         dv_attr.match_criteria_enable =
9602                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9603         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9604                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9605         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9606                                                &dtb->color_matcher);
9607         if (ret) {
9608                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9609                 goto error_exit;
9610         }
9611         if (mtb->count_actns[RTE_MTR_DROPPED])
9612                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9613         actions[i++] = mtb->drop_actn;
9614         /* Default rule: lowest priority, match any, actions: drop. */
9615         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9616                                        actions,
9617                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
9618         if (ret) {
9619                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9620                 goto error_exit;
9621         }
9622         return 0;
9623 error_exit:
9624         return -1;
9625 }
9626
9627 /**
9628  * Create the needed meter and suffix tables.
9629  * Lock free, (mutex should be acquired by caller).
9630  *
9631  * @param[in] dev
9632  *   Pointer to Ethernet device.
9633  * @param[in] fm
9634  *   Pointer to the flow meter.
9635  *
9636  * @return
9637  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9638  */
9639 static struct mlx5_meter_domains_infos *
9640 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9641                        const struct mlx5_flow_meter *fm)
9642 {
9643         struct mlx5_priv *priv = dev->data->dev_private;
9644         struct mlx5_meter_domains_infos *mtb;
9645         int ret;
9646         int i;
9647
9648         if (!priv->mtr_en) {
9649                 rte_errno = ENOTSUP;
9650                 return NULL;
9651         }
9652         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9653         if (!mtb) {
9654                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9655                 return NULL;
9656         }
9657         /* Create meter count actions */
9658         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9659                 struct mlx5_flow_counter *cnt;
9660                 if (!fm->policer_stats.cnt[i])
9661                         continue;
9662                 cnt = flow_dv_counter_get_by_idx(dev,
9663                       fm->policer_stats.cnt[i], NULL);
9664                 mtb->count_actns[i] = cnt->action;
9665         }
9666         /* Create drop action. */
9667         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9668         if (ret) {
9669                 DRV_LOG(ERR, "Failed to create drop action.");
9670                 goto error_exit;
9671         }
9672         /* Egress meter table. */
9673         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9674         if (ret) {
9675                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9676                 goto error_exit;
9677         }
9678         /* Ingress meter table. */
9679         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9680         if (ret) {
9681                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9682                 goto error_exit;
9683         }
9684         /* FDB meter table. */
9685         if (priv->config.dv_esw_en) {
9686                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9687                                                  priv->mtr_color_reg);
9688                 if (ret) {
9689                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9690                         goto error_exit;
9691                 }
9692         }
9693         return mtb;
9694 error_exit:
9695         flow_dv_destroy_mtr_tbl(dev, mtb);
9696         return NULL;
9697 }
9698
9699 /**
9700  * Destroy domain policer rule.
9701  *
9702  * @param[in] dt
9703  *   Pointer to domain table.
9704  */
9705 static void
9706 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9707 {
9708         int i;
9709
9710         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9711                 if (dt->policer_rules[i]) {
9712                         claim_zero(mlx5_flow_os_destroy_flow
9713                                    (dt->policer_rules[i]));
9714                         dt->policer_rules[i] = NULL;
9715                 }
9716         }
9717         if (dt->jump_actn) {
9718                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9719                 dt->jump_actn = NULL;
9720         }
9721 }
9722
9723 /**
9724  * Destroy policer rules.
9725  *
9726  * @param[in] dev
9727  *   Pointer to Ethernet device.
9728  * @param[in] fm
9729  *   Pointer to flow meter structure.
9730  * @param[in] attr
9731  *   Pointer to flow attributes.
9732  *
9733  * @return
9734  *   Always 0.
9735  */
9736 static int
9737 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9738                               const struct mlx5_flow_meter *fm,
9739                               const struct rte_flow_attr *attr)
9740 {
9741         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9742
9743         if (!mtb)
9744                 return 0;
9745         if (attr->egress)
9746                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9747         if (attr->ingress)
9748                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9749         if (attr->transfer)
9750                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9751         return 0;
9752 }
9753
9754 /**
9755  * Create specify domain meter policer rule.
9756  *
9757  * @param[in] fm
9758  *   Pointer to flow meter structure.
9759  * @param[in] mtb
9760  *   Pointer to DV meter table set.
9761  * @param[in] mtr_reg_c
9762  *   Color match REG_C.
9763  *
9764  * @return
9765  *   0 on success, -1 otherwise.
9766  */
9767 static int
9768 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9769                                     struct mlx5_meter_domain_info *dtb,
9770                                     uint8_t mtr_reg_c)
9771 {
9772         struct mlx5_flow_dv_match_params matcher = {
9773                 .size = sizeof(matcher.buf),
9774         };
9775         struct mlx5_flow_dv_match_params value = {
9776                 .size = sizeof(value.buf),
9777         };
9778         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9779         void *actions[METER_ACTIONS];
9780         int i;
9781         int ret = 0;
9782
9783         /* Create jump action. */
9784         if (!dtb->jump_actn)
9785                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9786                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9787         if (ret) {
9788                 DRV_LOG(ERR, "Failed to create policer jump action.");
9789                 goto error;
9790         }
9791         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9792                 int j = 0;
9793
9794                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9795                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9796                 if (mtb->count_actns[i])
9797                         actions[j++] = mtb->count_actns[i];
9798                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9799                         actions[j++] = mtb->drop_actn;
9800                 else
9801                         actions[j++] = dtb->jump_actn;
9802                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9803                                                (void *)&value, j, actions,
9804                                                &dtb->policer_rules[i]);
9805                 if (ret) {
9806                         DRV_LOG(ERR, "Failed to create policer rule.");
9807                         goto error;
9808                 }
9809         }
9810         return 0;
9811 error:
9812         rte_errno = errno;
9813         return -1;
9814 }
9815
9816 /**
9817  * Create policer rules.
9818  *
9819  * @param[in] dev
9820  *   Pointer to Ethernet device.
9821  * @param[in] fm
9822  *   Pointer to flow meter structure.
9823  * @param[in] attr
9824  *   Pointer to flow attributes.
9825  *
9826  * @return
9827  *   0 on success, -1 otherwise.
9828  */
9829 static int
9830 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9831                              struct mlx5_flow_meter *fm,
9832                              const struct rte_flow_attr *attr)
9833 {
9834         struct mlx5_priv *priv = dev->data->dev_private;
9835         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9836         int ret;
9837
9838         if (attr->egress) {
9839                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9840                                                 priv->mtr_color_reg);
9841                 if (ret) {
9842                         DRV_LOG(ERR, "Failed to create egress policer.");
9843                         goto error;
9844                 }
9845         }
9846         if (attr->ingress) {
9847                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9848                                                 priv->mtr_color_reg);
9849                 if (ret) {
9850                         DRV_LOG(ERR, "Failed to create ingress policer.");
9851                         goto error;
9852                 }
9853         }
9854         if (attr->transfer) {
9855                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9856                                                 priv->mtr_color_reg);
9857                 if (ret) {
9858                         DRV_LOG(ERR, "Failed to create transfer policer.");
9859                         goto error;
9860                 }
9861         }
9862         return 0;
9863 error:
9864         flow_dv_destroy_policer_rules(dev, fm, attr);
9865         return -1;
9866 }
9867
9868 /**
9869  * Query a devx counter.
9870  *
9871  * @param[in] dev
9872  *   Pointer to the Ethernet device structure.
9873  * @param[in] cnt
9874  *   Index to the flow counter.
9875  * @param[in] clear
9876  *   Set to clear the counter statistics.
9877  * @param[out] pkts
9878  *   The statistics value of packets.
9879  * @param[out] bytes
9880  *   The statistics value of bytes.
9881  *
9882  * @return
9883  *   0 on success, otherwise return -1.
9884  */
9885 static int
9886 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9887                       uint64_t *pkts, uint64_t *bytes)
9888 {
9889         struct mlx5_priv *priv = dev->data->dev_private;
9890         struct mlx5_flow_counter *cnt;
9891         uint64_t inn_pkts, inn_bytes;
9892         int ret;
9893
9894         if (!priv->config.devx)
9895                 return -1;
9896
9897         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9898         if (ret)
9899                 return -1;
9900         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9901         *pkts = inn_pkts - cnt->hits;
9902         *bytes = inn_bytes - cnt->bytes;
9903         if (clear) {
9904                 cnt->hits = inn_pkts;
9905                 cnt->bytes = inn_bytes;
9906         }
9907         return 0;
9908 }
9909
9910 /**
9911  * Get aged-out flows.
9912  *
9913  * @param[in] dev
9914  *   Pointer to the Ethernet device structure.
9915  * @param[in] context
9916  *   The address of an array of pointers to the aged-out flows contexts.
9917  * @param[in] nb_contexts
9918  *   The length of context array pointers.
9919  * @param[out] error
9920  *   Perform verbose error reporting if not NULL. Initialized in case of
9921  *   error only.
9922  *
9923  * @return
9924  *   how many contexts get in success, otherwise negative errno value.
9925  *   if nb_contexts is 0, return the amount of all aged contexts.
9926  *   if nb_contexts is not 0 , return the amount of aged flows reported
9927  *   in the context array.
9928  * @note: only stub for now
9929  */
9930 static int
9931 flow_get_aged_flows(struct rte_eth_dev *dev,
9932                     void **context,
9933                     uint32_t nb_contexts,
9934                     struct rte_flow_error *error)
9935 {
9936         struct mlx5_priv *priv = dev->data->dev_private;
9937         struct mlx5_age_info *age_info;
9938         struct mlx5_age_param *age_param;
9939         struct mlx5_flow_counter *counter;
9940         int nb_flows = 0;
9941
9942         if (nb_contexts && !context)
9943                 return rte_flow_error_set(error, EINVAL,
9944                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9945                                           NULL,
9946                                           "Should assign at least one flow or"
9947                                           " context to get if nb_contexts != 0");
9948         age_info = GET_PORT_AGE_INFO(priv);
9949         rte_spinlock_lock(&age_info->aged_sl);
9950         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9951                 nb_flows++;
9952                 if (nb_contexts) {
9953                         age_param = MLX5_CNT_TO_AGE(counter);
9954                         context[nb_flows - 1] = age_param->context;
9955                         if (!(--nb_contexts))
9956                                 break;
9957                 }
9958         }
9959         rte_spinlock_unlock(&age_info->aged_sl);
9960         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9961         return nb_flows;
9962 }
9963
9964 /*
9965  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9966  */
9967 static int
9968 flow_dv_translate(struct rte_eth_dev *dev,
9969                   struct mlx5_flow *dev_flow,
9970                   const struct rte_flow_attr *attr,
9971                   const struct rte_flow_item items[],
9972                   const struct rte_flow_action actions[],
9973                   struct rte_flow_error *error)
9974 {
9975         int ret;
9976
9977         flow_dv_shared_lock(dev);
9978         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9979         flow_dv_shared_unlock(dev);
9980         return ret;
9981 }
9982
9983 /*
9984  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9985  */
9986 static int
9987 flow_dv_apply(struct rte_eth_dev *dev,
9988               struct rte_flow *flow,
9989               struct rte_flow_error *error)
9990 {
9991         int ret;
9992
9993         flow_dv_shared_lock(dev);
9994         ret = __flow_dv_apply(dev, flow, error);
9995         flow_dv_shared_unlock(dev);
9996         return ret;
9997 }
9998
9999 /*
10000  * Mutex-protected thunk to lock-free __flow_dv_remove().
10001  */
10002 static void
10003 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10004 {
10005         flow_dv_shared_lock(dev);
10006         __flow_dv_remove(dev, flow);
10007         flow_dv_shared_unlock(dev);
10008 }
10009
10010 /*
10011  * Mutex-protected thunk to lock-free __flow_dv_destroy().
10012  */
10013 static void
10014 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10015 {
10016         flow_dv_shared_lock(dev);
10017         __flow_dv_destroy(dev, flow);
10018         flow_dv_shared_unlock(dev);
10019 }
10020
10021 /*
10022  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
10023  */
10024 static uint32_t
10025 flow_dv_counter_allocate(struct rte_eth_dev *dev)
10026 {
10027         uint32_t cnt;
10028
10029         flow_dv_shared_lock(dev);
10030         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
10031         flow_dv_shared_unlock(dev);
10032         return cnt;
10033 }
10034
10035 /*
10036  * Mutex-protected thunk to lock-free flow_dv_counter_release().
10037  */
10038 static void
10039 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
10040 {
10041         flow_dv_shared_lock(dev);
10042         flow_dv_counter_release(dev, cnt);
10043         flow_dv_shared_unlock(dev);
10044 }
10045
10046 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
10047         .validate = flow_dv_validate,
10048         .prepare = flow_dv_prepare,
10049         .translate = flow_dv_translate,
10050         .apply = flow_dv_apply,
10051         .remove = flow_dv_remove,
10052         .destroy = flow_dv_destroy,
10053         .query = flow_dv_query,
10054         .create_mtr_tbls = flow_dv_create_mtr_tbl,
10055         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
10056         .create_policer_rules = flow_dv_create_policer_rules,
10057         .destroy_policer_rules = flow_dv_destroy_policer_rules,
10058         .counter_alloc = flow_dv_counter_allocate,
10059         .counter_free = flow_dv_counter_free,
10060         .counter_query = flow_dv_counter_query,
10061         .get_aged_flows = flow_get_aged_flows,
10062 };
10063
10064 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
10065