drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rx.h"
  36 #include "mlx5_tx.h"
  37 #include "rte_pmd_mlx5.h"
  38
  39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  40
  41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  43 #endif
  44
  45 #ifndef HAVE_MLX5DV_DR_ESWITCH
  46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  48 #endif
  49 #endif
  50
  51 #ifndef HAVE_MLX5DV_DR
  52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  53 #endif
  54
  55 /* VLAN header definitions */
  56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  61
  62 union flow_dv_attr {
  63         struct {
  64                 uint32_t valid:1;
  65                 uint32_t ipv4:1;
  66                 uint32_t ipv6:1;
  67                 uint32_t tcp:1;
  68                 uint32_t udp:1;
  69                 uint32_t reserved:27;
  70         };
  71         uint32_t attr;
  72 };
  73
  74 static int
  75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  76                              struct mlx5_flow_tbl_resource *tbl);
  77
  78 static int
  79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  80                                      uint32_t encap_decap_idx);
  81
  82 static int
  83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  84                                         uint32_t port_id);
  85 static void
  86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  87
  88 static int
  89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  90                                   uint32_t rix_jump);
  91
  92 /**
  93  * Initialize flow attributes structure according to flow items' types.
  94  *
  95  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  96  * mode. For tunnel mode, the items to be modified are the outermost ones.
  97  *
  98  * @param[in] item
  99  *   Pointer to item specification.
 100  * @param[out] attr
 101  *   Pointer to flow attributes structure.
 102  * @param[in] dev_flow
 103  *   Pointer to the sub flow.
 104  * @param[in] tunnel_decap
 105  *   Whether action is after tunnel decapsulation.
 106  */
 107 static void
 108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 109                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 110 {
 111         uint64_t layers = dev_flow->handle->layers;
 112
 113         /*
 114          * If layers is already initialized, it means this dev_flow is the
 115          * suffix flow, the layers flags is set by the prefix flow. Need to
 116          * use the layer flags from prefix flow as the suffix flow may not
 117          * have the user defined items as the flow is split.
 118          */
 119         if (layers) {
 120                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 121                         attr->ipv4 = 1;
 122                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 123                         attr->ipv6 = 1;
 124                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 125                         attr->tcp = 1;
 126                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 127                         attr->udp = 1;
 128                 attr->valid = 1;
 129                 return;
 130         }
 131         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 132                 uint8_t next_protocol = 0xff;
 133                 switch (item->type) {
 134                 case RTE_FLOW_ITEM_TYPE_GRE:
 135                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 137                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 138                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 139                 case RTE_FLOW_ITEM_TYPE_MPLS:
 140                         if (tunnel_decap)
 141                                 attr->attr = 0;
 142                         break;
 143                 case RTE_FLOW_ITEM_TYPE_IPV4:
 144                         if (!attr->ipv6)
 145                                 attr->ipv4 = 1;
 146                         if (item->mask != NULL &&
 147                             ((const struct rte_flow_item_ipv4 *)
 148                             item->mask)->hdr.next_proto_id)
 149                                 next_protocol =
 150                                     ((const struct rte_flow_item_ipv4 *)
 151                                       (item->spec))->hdr.next_proto_id &
 152                                     ((const struct rte_flow_item_ipv4 *)
 153                                       (item->mask))->hdr.next_proto_id;
 154                         if ((next_protocol == IPPROTO_IPIP ||
 155                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 156                                 attr->attr = 0;
 157                         break;
 158                 case RTE_FLOW_ITEM_TYPE_IPV6:
 159                         if (!attr->ipv4)
 160                                 attr->ipv6 = 1;
 161                         if (item->mask != NULL &&
 162                             ((const struct rte_flow_item_ipv6 *)
 163                             item->mask)->hdr.proto)
 164                                 next_protocol =
 165                                     ((const struct rte_flow_item_ipv6 *)
 166                                       (item->spec))->hdr.proto &
 167                                     ((const struct rte_flow_item_ipv6 *)
 168                                       (item->mask))->hdr.proto;
 169                         if ((next_protocol == IPPROTO_IPIP ||
 170                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 171                                 attr->attr = 0;
 172                         break;
 173                 case RTE_FLOW_ITEM_TYPE_UDP:
 174                         if (!attr->tcp)
 175                                 attr->udp = 1;
 176                         break;
 177                 case RTE_FLOW_ITEM_TYPE_TCP:
 178                         if (!attr->udp)
 179                                 attr->tcp = 1;
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         }
 185         attr->valid = 1;
 186 }
 187
 188 /**
 189  * Convert rte_mtr_color to mlx5 color.
 190  *
 191  * @param[in] rcol
 192  *   rte_mtr_color.
 193  *
 194  * @return
 195  *   mlx5 color.
 196  */
 197 static int
 198 rte_col_2_mlx5_col(enum rte_color rcol)
 199 {
 200         switch (rcol) {
 201         case RTE_COLOR_GREEN:
 202                 return MLX5_FLOW_COLOR_GREEN;
 203         case RTE_COLOR_YELLOW:
 204                 return MLX5_FLOW_COLOR_YELLOW;
 205         case RTE_COLOR_RED:
 206                 return MLX5_FLOW_COLOR_RED;
 207         default:
 208                 break;
 209         }
 210         return MLX5_FLOW_COLOR_UNDEFINED;
 211 }
 212
 213 struct field_modify_info {
 214         uint32_t size; /* Size of field in protocol header, in bytes. */
 215         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 216         enum mlx5_modification_field id;
 217 };
 218
 219 struct field_modify_info modify_eth[] = {
 220         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 221         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 222         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 223         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 224         {0, 0, 0},
 225 };
 226
 227 struct field_modify_info modify_vlan_out_first_vid[] = {
 228         /* Size in bits !!! */
 229         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 230         {0, 0, 0},
 231 };
 232
 233 struct field_modify_info modify_ipv4[] = {
 234         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 235         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 236         {4, 12, MLX5_MODI_OUT_SIPV4},
 237         {4, 16, MLX5_MODI_OUT_DIPV4},
 238         {0, 0, 0},
 239 };
 240
 241 struct field_modify_info modify_ipv6[] = {
 242         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 243         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 244         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 245         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 246         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 247         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 248         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 249         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 250         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 251         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 252         {0, 0, 0},
 253 };
 254
 255 struct field_modify_info modify_udp[] = {
 256         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 257         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 258         {0, 0, 0},
 259 };
 260
 261 struct field_modify_info modify_tcp[] = {
 262         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 263         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 264         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 265         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 266         {0, 0, 0},
 267 };
 268
 269 static void
 270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 271                           uint8_t next_protocol, uint64_t *item_flags,
 272                           int *tunnel)
 273 {
 274         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 275                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 276         if (next_protocol == IPPROTO_IPIP) {
 277                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 278                 *tunnel = 1;
 279         }
 280         if (next_protocol == IPPROTO_IPV6) {
 281                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 282                 *tunnel = 1;
 283         }
 284 }
 285
 286 /* Update VLAN's VID/PCP based on input rte_flow_action.
 287  *
 288  * @param[in] action
 289  *   Pointer to struct rte_flow_action.
 290  * @param[out] vlan
 291  *   Pointer to struct rte_vlan_hdr.
 292  */
 293 static void
 294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 295                          struct rte_vlan_hdr *vlan)
 296 {
 297         uint16_t vlan_tci;
 298         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 299                 vlan_tci =
 300                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 301                                                action->conf)->vlan_pcp;
 302                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 303                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 304                 vlan->vlan_tci |= vlan_tci;
 305         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 306                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 307                 vlan->vlan_tci |= rte_be_to_cpu_16
 308                     (((const struct rte_flow_action_of_set_vlan_vid *)
 309                                              action->conf)->vlan_vid);
 310         }
 311 }
 312
 313 /**
 314  * Fetch 1, 2, 3 or 4 byte field from the byte array
 315  * and return as unsigned integer in host-endian format.
 316  *
 317  * @param[in] data
 318  *   Pointer to data array.
 319  * @param[in] size
 320  *   Size of field to extract.
 321  *
 322  * @return
 323  *   converted field in host endian format.
 324  */
 325 static inline uint32_t
 326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 327 {
 328         uint32_t ret;
 329
 330         switch (size) {
 331         case 1:
 332                 ret = *data;
 333                 break;
 334         case 2:
 335                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 336                 break;
 337         case 3:
 338                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 339                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 340                 break;
 341         case 4:
 342                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 343                 break;
 344         default:
 345                 MLX5_ASSERT(false);
 346                 ret = 0;
 347                 break;
 348         }
 349         return ret;
 350 }
 351
 352 /**
 353  * Convert modify-header action to DV specification.
 354  *
 355  * Data length of each action is determined by provided field description
 356  * and the item mask. Data bit offset and width of each action is determined
 357  * by provided item mask.
 358  *
 359  * @param[in] item
 360  *   Pointer to item specification.
 361  * @param[in] field
 362  *   Pointer to field modification information.
 363  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 365  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 366  * @param[in] dcopy
 367  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 368  *   Negative offset value sets the same offset as source offset.
 369  *   size field is ignored, value is taken from source field.
 370  * @param[in,out] resource
 371  *   Pointer to the modify-header resource.
 372  * @param[in] type
 373  *   Type of modification.
 374  * @param[out] error
 375  *   Pointer to the error structure.
 376  *
 377  * @return
 378  *   0 on success, a negative errno value otherwise and rte_errno is set.
 379  */
 380 static int
 381 flow_dv_convert_modify_action(struct rte_flow_item *item,
 382                               struct field_modify_info *field,
 383                               struct field_modify_info *dcopy,
 384                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 385                               uint32_t type, struct rte_flow_error *error)
 386 {
 387         uint32_t i = resource->actions_num;
 388         struct mlx5_modification_cmd *actions = resource->actions;
 389
 390         /*
 391          * The item and mask are provided in big-endian format.
 392          * The fields should be presented as in big-endian format either.
 393          * Mask must be always present, it defines the actual field width.
 394          */
 395         MLX5_ASSERT(item->mask);
 396         MLX5_ASSERT(field->size);
 397         do {
 398                 unsigned int size_b;
 399                 unsigned int off_b;
 400                 uint32_t mask;
 401                 uint32_t data;
 402
 403                 if (i >= MLX5_MAX_MODIFY_NUM)
 404                         return rte_flow_error_set(error, EINVAL,
 405                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 406                                  "too many items to modify");
 407                 /* Fetch variable byte size mask from the array. */
 408                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 409                                            field->offset, field->size);
 410                 if (!mask) {
 411                         ++field;
 412                         continue;
 413                 }
 414                 /* Deduce actual data width in bits from mask value. */
 415                 off_b = rte_bsf32(mask);
 416                 size_b = sizeof(uint32_t) * CHAR_BIT -
 417                          off_b - __builtin_clz(mask);
 418                 MLX5_ASSERT(size_b);
 419                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 420                 actions[i] = (struct mlx5_modification_cmd) {
 421                         .action_type = type,
 422                         .field = field->id,
 423                         .offset = off_b,
 424                         .length = size_b,
 425                 };
 426                 /* Convert entire record to expected big-endian format. */
 427                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 428                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 429                         MLX5_ASSERT(dcopy);
 430                         actions[i].dst_field = dcopy->id;
 431                         actions[i].dst_offset =
 432                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 433                         /* Convert entire record to big-endian format. */
 434                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 435                         ++dcopy;
 436                 } else {
 437                         MLX5_ASSERT(item->spec);
 438                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 439                                                    field->offset, field->size);
 440                         /* Shift out the trailing masked bits from data. */
 441                         data = (data & mask) >> off_b;
 442                         actions[i].data1 = rte_cpu_to_be_32(data);
 443                 }
 444                 ++i;
 445                 ++field;
 446         } while (field->size);
 447         if (resource->actions_num == i)
 448                 return rte_flow_error_set(error, EINVAL,
 449                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 450                                           "invalid modification flow item");
 451         resource->actions_num = i;
 452         return 0;
 453 }
 454
 455 /**
 456  * Convert modify-header set IPv4 address action to DV specification.
 457  *
 458  * @param[in,out] resource
 459  *   Pointer to the modify-header resource.
 460  * @param[in] action
 461  *   Pointer to action specification.
 462  * @param[out] error
 463  *   Pointer to the error structure.
 464  *
 465  * @return
 466  *   0 on success, a negative errno value otherwise and rte_errno is set.
 467  */
 468 static int
 469 flow_dv_convert_action_modify_ipv4
 470                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 471                          const struct rte_flow_action *action,
 472                          struct rte_flow_error *error)
 473 {
 474         const struct rte_flow_action_set_ipv4 *conf =
 475                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 476         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 477         struct rte_flow_item_ipv4 ipv4;
 478         struct rte_flow_item_ipv4 ipv4_mask;
 479
 480         memset(&ipv4, 0, sizeof(ipv4));
 481         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 482         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 483                 ipv4.hdr.src_addr = conf->ipv4_addr;
 484                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 485         } else {
 486                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 487                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 488         }
 489         item.spec = &ipv4;
 490         item.mask = &ipv4_mask;
 491         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 492                                              MLX5_MODIFICATION_TYPE_SET, error);
 493 }
 494
 495 /**
 496  * Convert modify-header set IPv6 address action to DV specification.
 497  *
 498  * @param[in,out] resource
 499  *   Pointer to the modify-header resource.
 500  * @param[in] action
 501  *   Pointer to action specification.
 502  * @param[out] error
 503  *   Pointer to the error structure.
 504  *
 505  * @return
 506  *   0 on success, a negative errno value otherwise and rte_errno is set.
 507  */
 508 static int
 509 flow_dv_convert_action_modify_ipv6
 510                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 511                          const struct rte_flow_action *action,
 512                          struct rte_flow_error *error)
 513 {
 514         const struct rte_flow_action_set_ipv6 *conf =
 515                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 516         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 517         struct rte_flow_item_ipv6 ipv6;
 518         struct rte_flow_item_ipv6 ipv6_mask;
 519
 520         memset(&ipv6, 0, sizeof(ipv6));
 521         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 522         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 523                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.src_addr));
 525                 memcpy(&ipv6_mask.hdr.src_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 527                        sizeof(ipv6.hdr.src_addr));
 528         } else {
 529                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 530                        sizeof(ipv6.hdr.dst_addr));
 531                 memcpy(&ipv6_mask.hdr.dst_addr,
 532                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 533                        sizeof(ipv6.hdr.dst_addr));
 534         }
 535         item.spec = &ipv6;
 536         item.mask = &ipv6_mask;
 537         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 538                                              MLX5_MODIFICATION_TYPE_SET, error);
 539 }
 540
 541 /**
 542  * Convert modify-header set MAC address action to DV specification.
 543  *
 544  * @param[in,out] resource
 545  *   Pointer to the modify-header resource.
 546  * @param[in] action
 547  *   Pointer to action specification.
 548  * @param[out] error
 549  *   Pointer to the error structure.
 550  *
 551  * @return
 552  *   0 on success, a negative errno value otherwise and rte_errno is set.
 553  */
 554 static int
 555 flow_dv_convert_action_modify_mac
 556                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 557                          const struct rte_flow_action *action,
 558                          struct rte_flow_error *error)
 559 {
 560         const struct rte_flow_action_set_mac *conf =
 561                 (const struct rte_flow_action_set_mac *)(action->conf);
 562         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 563         struct rte_flow_item_eth eth;
 564         struct rte_flow_item_eth eth_mask;
 565
 566         memset(&eth, 0, sizeof(eth));
 567         memset(&eth_mask, 0, sizeof(eth_mask));
 568         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 569                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.src.addr_bytes));
 571                 memcpy(&eth_mask.src.addr_bytes,
 572                        &rte_flow_item_eth_mask.src.addr_bytes,
 573                        sizeof(eth_mask.src.addr_bytes));
 574         } else {
 575                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 576                        sizeof(eth.dst.addr_bytes));
 577                 memcpy(&eth_mask.dst.addr_bytes,
 578                        &rte_flow_item_eth_mask.dst.addr_bytes,
 579                        sizeof(eth_mask.dst.addr_bytes));
 580         }
 581         item.spec = &eth;
 582         item.mask = &eth_mask;
 583         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 584                                              MLX5_MODIFICATION_TYPE_SET, error);
 585 }
 586
 587 /**
 588  * Convert modify-header set VLAN VID action to DV specification.
 589  *
 590  * @param[in,out] resource
 591  *   Pointer to the modify-header resource.
 592  * @param[in] action
 593  *   Pointer to action specification.
 594  * @param[out] error
 595  *   Pointer to the error structure.
 596  *
 597  * @return
 598  *   0 on success, a negative errno value otherwise and rte_errno is set.
 599  */
 600 static int
 601 flow_dv_convert_action_modify_vlan_vid
 602                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 603                          const struct rte_flow_action *action,
 604                          struct rte_flow_error *error)
 605 {
 606         const struct rte_flow_action_of_set_vlan_vid *conf =
 607                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 608         int i = resource->actions_num;
 609         struct mlx5_modification_cmd *actions = resource->actions;
 610         struct field_modify_info *field = modify_vlan_out_first_vid;
 611
 612         if (i >= MLX5_MAX_MODIFY_NUM)
 613                 return rte_flow_error_set(error, EINVAL,
 614                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 615                          "too many items to modify");
 616         actions[i] = (struct mlx5_modification_cmd) {
 617                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 618                 .field = field->id,
 619                 .length = field->size,
 620                 .offset = field->offset,
 621         };
 622         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 623         actions[i].data1 = conf->vlan_vid;
 624         actions[i].data1 = actions[i].data1 << 16;
 625         resource->actions_num = ++i;
 626         return 0;
 627 }
 628
 629 /**
 630  * Convert modify-header set TP action to DV specification.
 631  *
 632  * @param[in,out] resource
 633  *   Pointer to the modify-header resource.
 634  * @param[in] action
 635  *   Pointer to action specification.
 636  * @param[in] items
 637  *   Pointer to rte_flow_item objects list.
 638  * @param[in] attr
 639  *   Pointer to flow attributes structure.
 640  * @param[in] dev_flow
 641  *   Pointer to the sub flow.
 642  * @param[in] tunnel_decap
 643  *   Whether action is after tunnel decapsulation.
 644  * @param[out] error
 645  *   Pointer to the error structure.
 646  *
 647  * @return
 648  *   0 on success, a negative errno value otherwise and rte_errno is set.
 649  */
 650 static int
 651 flow_dv_convert_action_modify_tp
 652                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 653                          const struct rte_flow_action *action,
 654                          const struct rte_flow_item *items,
 655                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 656                          bool tunnel_decap, struct rte_flow_error *error)
 657 {
 658         const struct rte_flow_action_set_tp *conf =
 659                 (const struct rte_flow_action_set_tp *)(action->conf);
 660         struct rte_flow_item item;
 661         struct rte_flow_item_udp udp;
 662         struct rte_flow_item_udp udp_mask;
 663         struct rte_flow_item_tcp tcp;
 664         struct rte_flow_item_tcp tcp_mask;
 665         struct field_modify_info *field;
 666
 667         if (!attr->valid)
 668                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 669         if (attr->udp) {
 670                 memset(&udp, 0, sizeof(udp));
 671                 memset(&udp_mask, 0, sizeof(udp_mask));
 672                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 673                         udp.hdr.src_port = conf->port;
 674                         udp_mask.hdr.src_port =
 675                                         rte_flow_item_udp_mask.hdr.src_port;
 676                 } else {
 677                         udp.hdr.dst_port = conf->port;
 678                         udp_mask.hdr.dst_port =
 679                                         rte_flow_item_udp_mask.hdr.dst_port;
 680                 }
 681                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 682                 item.spec = &udp;
 683                 item.mask = &udp_mask;
 684                 field = modify_udp;
 685         } else {
 686                 MLX5_ASSERT(attr->tcp);
 687                 memset(&tcp, 0, sizeof(tcp));
 688                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 689                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 690                         tcp.hdr.src_port = conf->port;
 691                         tcp_mask.hdr.src_port =
 692                                         rte_flow_item_tcp_mask.hdr.src_port;
 693                 } else {
 694                         tcp.hdr.dst_port = conf->port;
 695                         tcp_mask.hdr.dst_port =
 696                                         rte_flow_item_tcp_mask.hdr.dst_port;
 697                 }
 698                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 699                 item.spec = &tcp;
 700                 item.mask = &tcp_mask;
 701                 field = modify_tcp;
 702         }
 703         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 704                                              MLX5_MODIFICATION_TYPE_SET, error);
 705 }
 706
 707 /**
 708  * Convert modify-header set TTL action to DV specification.
 709  *
 710  * @param[in,out] resource
 711  *   Pointer to the modify-header resource.
 712  * @param[in] action
 713  *   Pointer to action specification.
 714  * @param[in] items
 715  *   Pointer to rte_flow_item objects list.
 716  * @param[in] attr
 717  *   Pointer to flow attributes structure.
 718  * @param[in] dev_flow
 719  *   Pointer to the sub flow.
 720  * @param[in] tunnel_decap
 721  *   Whether action is after tunnel decapsulation.
 722  * @param[out] error
 723  *   Pointer to the error structure.
 724  *
 725  * @return
 726  *   0 on success, a negative errno value otherwise and rte_errno is set.
 727  */
 728 static int
 729 flow_dv_convert_action_modify_ttl
 730                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 731                          const struct rte_flow_action *action,
 732                          const struct rte_flow_item *items,
 733                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 734                          bool tunnel_decap, struct rte_flow_error *error)
 735 {
 736         const struct rte_flow_action_set_ttl *conf =
 737                 (const struct rte_flow_action_set_ttl *)(action->conf);
 738         struct rte_flow_item item;
 739         struct rte_flow_item_ipv4 ipv4;
 740         struct rte_flow_item_ipv4 ipv4_mask;
 741         struct rte_flow_item_ipv6 ipv6;
 742         struct rte_flow_item_ipv6 ipv6_mask;
 743         struct field_modify_info *field;
 744
 745         if (!attr->valid)
 746                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 747         if (attr->ipv4) {
 748                 memset(&ipv4, 0, sizeof(ipv4));
 749                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 750                 ipv4.hdr.time_to_live = conf->ttl_value;
 751                 ipv4_mask.hdr.time_to_live = 0xFF;
 752                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 753                 item.spec = &ipv4;
 754                 item.mask = &ipv4_mask;
 755                 field = modify_ipv4;
 756         } else {
 757                 MLX5_ASSERT(attr->ipv6);
 758                 memset(&ipv6, 0, sizeof(ipv6));
 759                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 760                 ipv6.hdr.hop_limits = conf->ttl_value;
 761                 ipv6_mask.hdr.hop_limits = 0xFF;
 762                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 763                 item.spec = &ipv6;
 764                 item.mask = &ipv6_mask;
 765                 field = modify_ipv6;
 766         }
 767         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 768                                              MLX5_MODIFICATION_TYPE_SET, error);
 769 }
 770
 771 /**
 772  * Convert modify-header decrement TTL action to DV specification.
 773  *
 774  * @param[in,out] resource
 775  *   Pointer to the modify-header resource.
 776  * @param[in] action
 777  *   Pointer to action specification.
 778  * @param[in] items
 779  *   Pointer to rte_flow_item objects list.
 780  * @param[in] attr
 781  *   Pointer to flow attributes structure.
 782  * @param[in] dev_flow
 783  *   Pointer to the sub flow.
 784  * @param[in] tunnel_decap
 785  *   Whether action is after tunnel decapsulation.
 786  * @param[out] error
 787  *   Pointer to the error structure.
 788  *
 789  * @return
 790  *   0 on success, a negative errno value otherwise and rte_errno is set.
 791  */
 792 static int
 793 flow_dv_convert_action_modify_dec_ttl
 794                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 795                          const struct rte_flow_item *items,
 796                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 797                          bool tunnel_decap, struct rte_flow_error *error)
 798 {
 799         struct rte_flow_item item;
 800         struct rte_flow_item_ipv4 ipv4;
 801         struct rte_flow_item_ipv4 ipv4_mask;
 802         struct rte_flow_item_ipv6 ipv6;
 803         struct rte_flow_item_ipv6 ipv6_mask;
 804         struct field_modify_info *field;
 805
 806         if (!attr->valid)
 807                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 808         if (attr->ipv4) {
 809                 memset(&ipv4, 0, sizeof(ipv4));
 810                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 811                 ipv4.hdr.time_to_live = 0xFF;
 812                 ipv4_mask.hdr.time_to_live = 0xFF;
 813                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 814                 item.spec = &ipv4;
 815                 item.mask = &ipv4_mask;
 816                 field = modify_ipv4;
 817         } else {
 818                 MLX5_ASSERT(attr->ipv6);
 819                 memset(&ipv6, 0, sizeof(ipv6));
 820                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 821                 ipv6.hdr.hop_limits = 0xFF;
 822                 ipv6_mask.hdr.hop_limits = 0xFF;
 823                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 824                 item.spec = &ipv6;
 825                 item.mask = &ipv6_mask;
 826                 field = modify_ipv6;
 827         }
 828         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 829                                              MLX5_MODIFICATION_TYPE_ADD, error);
 830 }
 831
 832 /**
 833  * Convert modify-header increment/decrement TCP Sequence number
 834  * to DV specification.
 835  *
 836  * @param[in,out] resource
 837  *   Pointer to the modify-header resource.
 838  * @param[in] action
 839  *   Pointer to action specification.
 840  * @param[out] error
 841  *   Pointer to the error structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 static int
 847 flow_dv_convert_action_modify_tcp_seq
 848                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 849                          const struct rte_flow_action *action,
 850                          struct rte_flow_error *error)
 851 {
 852         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 853         uint64_t value = rte_be_to_cpu_32(*conf);
 854         struct rte_flow_item item;
 855         struct rte_flow_item_tcp tcp;
 856         struct rte_flow_item_tcp tcp_mask;
 857
 858         memset(&tcp, 0, sizeof(tcp));
 859         memset(&tcp_mask, 0, sizeof(tcp_mask));
 860         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 861                 /*
 862                  * The HW has no decrement operation, only increment operation.
 863                  * To simulate decrement X from Y using increment operation
 864                  * we need to add UINT32_MAX X times to Y.
 865                  * Each adding of UINT32_MAX decrements Y by 1.
 866                  */
 867                 value *= UINT32_MAX;
 868         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 869         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 870         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 871         item.spec = &tcp;
 872         item.mask = &tcp_mask;
 873         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 874                                              MLX5_MODIFICATION_TYPE_ADD, error);
 875 }
 876
 877 /**
 878  * Convert modify-header increment/decrement TCP Acknowledgment number
 879  * to DV specification.
 880  *
 881  * @param[in,out] resource
 882  *   Pointer to the modify-header resource.
 883  * @param[in] action
 884  *   Pointer to action specification.
 885  * @param[out] error
 886  *   Pointer to the error structure.
 887  *
 888  * @return
 889  *   0 on success, a negative errno value otherwise and rte_errno is set.
 890  */
 891 static int
 892 flow_dv_convert_action_modify_tcp_ack
 893                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 894                          const struct rte_flow_action *action,
 895                          struct rte_flow_error *error)
 896 {
 897         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 898         uint64_t value = rte_be_to_cpu_32(*conf);
 899         struct rte_flow_item item;
 900         struct rte_flow_item_tcp tcp;
 901         struct rte_flow_item_tcp tcp_mask;
 902
 903         memset(&tcp, 0, sizeof(tcp));
 904         memset(&tcp_mask, 0, sizeof(tcp_mask));
 905         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 906                 /*
 907                  * The HW has no decrement operation, only increment operation.
 908                  * To simulate decrement X from Y using increment operation
 909                  * we need to add UINT32_MAX X times to Y.
 910                  * Each adding of UINT32_MAX decrements Y by 1.
 911                  */
 912                 value *= UINT32_MAX;
 913         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 914         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 915         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 916         item.spec = &tcp;
 917         item.mask = &tcp_mask;
 918         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 919                                              MLX5_MODIFICATION_TYPE_ADD, error);
 920 }
 921
 922 static enum mlx5_modification_field reg_to_field[] = {
 923         [REG_NON] = MLX5_MODI_OUT_NONE,
 924         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 925         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 926         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 927         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 928         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 929         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 930         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 931         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 932         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 933         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 934 };
 935
 936 /**
 937  * Convert register set to DV specification.
 938  *
 939  * @param[in,out] resource
 940  *   Pointer to the modify-header resource.
 941  * @param[in] action
 942  *   Pointer to action specification.
 943  * @param[out] error
 944  *   Pointer to the error structure.
 945  *
 946  * @return
 947  *   0 on success, a negative errno value otherwise and rte_errno is set.
 948  */
 949 static int
 950 flow_dv_convert_action_set_reg
 951                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 952                          const struct rte_flow_action *action,
 953                          struct rte_flow_error *error)
 954 {
 955         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 956         struct mlx5_modification_cmd *actions = resource->actions;
 957         uint32_t i = resource->actions_num;
 958
 959         if (i >= MLX5_MAX_MODIFY_NUM)
 960                 return rte_flow_error_set(error, EINVAL,
 961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 962                                           "too many items to modify");
 963         MLX5_ASSERT(conf->id != REG_NON);
 964         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 965         actions[i] = (struct mlx5_modification_cmd) {
 966                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 967                 .field = reg_to_field[conf->id],
 968                 .offset = conf->offset,
 969                 .length = conf->length,
 970         };
 971         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 972         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 973         ++i;
 974         resource->actions_num = i;
 975         return 0;
 976 }
 977
 978 /**
 979  * Convert SET_TAG action to DV specification.
 980  *
 981  * @param[in] dev
 982  *   Pointer to the rte_eth_dev structure.
 983  * @param[in,out] resource
 984  *   Pointer to the modify-header resource.
 985  * @param[in] conf
 986  *   Pointer to action specification.
 987  * @param[out] error
 988  *   Pointer to the error structure.
 989  *
 990  * @return
 991  *   0 on success, a negative errno value otherwise and rte_errno is set.
 992  */
 993 static int
 994 flow_dv_convert_action_set_tag
 995                         (struct rte_eth_dev *dev,
 996                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 997                          const struct rte_flow_action_set_tag *conf,
 998                          struct rte_flow_error *error)
 999 {
1000         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1001         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1002         struct rte_flow_item item = {
1003                 .spec = &data,
1004                 .mask = &mask,
1005         };
1006         struct field_modify_info reg_c_x[] = {
1007                 [1] = {0, 0, 0},
1008         };
1009         enum mlx5_modification_field reg_type;
1010         int ret;
1011
1012         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1013         if (ret < 0)
1014                 return ret;
1015         MLX5_ASSERT(ret != REG_NON);
1016         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1017         reg_type = reg_to_field[ret];
1018         MLX5_ASSERT(reg_type > 0);
1019         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1020         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1021                                              MLX5_MODIFICATION_TYPE_SET, error);
1022 }
1023
1024 /**
1025  * Convert internal COPY_REG action to DV specification.
1026  *
1027  * @param[in] dev
1028  *   Pointer to the rte_eth_dev structure.
1029  * @param[in,out] res
1030  *   Pointer to the modify-header resource.
1031  * @param[in] action
1032  *   Pointer to action specification.
1033  * @param[out] error
1034  *   Pointer to the error structure.
1035  *
1036  * @return
1037  *   0 on success, a negative errno value otherwise and rte_errno is set.
1038  */
1039 static int
1040 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1041                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1042                                  const struct rte_flow_action *action,
1043                                  struct rte_flow_error *error)
1044 {
1045         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1046         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1047         struct rte_flow_item item = {
1048                 .spec = NULL,
1049                 .mask = &mask,
1050         };
1051         struct field_modify_info reg_src[] = {
1052                 {4, 0, reg_to_field[conf->src]},
1053                 {0, 0, 0},
1054         };
1055         struct field_modify_info reg_dst = {
1056                 .offset = 0,
1057                 .id = reg_to_field[conf->dst],
1058         };
1059         /* Adjust reg_c[0] usage according to reported mask. */
1060         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1061                 struct mlx5_priv *priv = dev->data->dev_private;
1062                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1063
1064                 MLX5_ASSERT(reg_c0);
1065                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1066                 if (conf->dst == REG_C_0) {
1067                         /* Copy to reg_c[0], within mask only. */
1068                         reg_dst.offset = rte_bsf32(reg_c0);
1069                         /*
1070                          * Mask is ignoring the enianness, because
1071                          * there is no conversion in datapath.
1072                          */
1073 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1074                         /* Copy from destination lower bits to reg_c[0]. */
1075                         mask = reg_c0 >> reg_dst.offset;
1076 #else
1077                         /* Copy from destination upper bits to reg_c[0]. */
1078                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1079                                           rte_fls_u32(reg_c0));
1080 #endif
1081                 } else {
1082                         mask = rte_cpu_to_be_32(reg_c0);
1083 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1084                         /* Copy from reg_c[0] to destination lower bits. */
1085                         reg_dst.offset = 0;
1086 #else
1087                         /* Copy from reg_c[0] to destination upper bits. */
1088                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1089                                          (rte_fls_u32(reg_c0) -
1090                                           rte_bsf32(reg_c0));
1091 #endif
1092                 }
1093         }
1094         return flow_dv_convert_modify_action(&item,
1095                                              reg_src, &reg_dst, res,
1096                                              MLX5_MODIFICATION_TYPE_COPY,
1097                                              error);
1098 }
1099
1100 /**
1101  * Convert MARK action to DV specification. This routine is used
1102  * in extensive metadata only and requires metadata register to be
1103  * handled. In legacy mode hardware tag resource is engaged.
1104  *
1105  * @param[in] dev
1106  *   Pointer to the rte_eth_dev structure.
1107  * @param[in] conf
1108  *   Pointer to MARK action specification.
1109  * @param[in,out] resource
1110  *   Pointer to the modify-header resource.
1111  * @param[out] error
1112  *   Pointer to the error structure.
1113  *
1114  * @return
1115  *   0 on success, a negative errno value otherwise and rte_errno is set.
1116  */
1117 static int
1118 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1119                             const struct rte_flow_action_mark *conf,
1120                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1121                             struct rte_flow_error *error)
1122 {
1123         struct mlx5_priv *priv = dev->data->dev_private;
1124         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1125                                            priv->sh->dv_mark_mask);
1126         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1127         struct rte_flow_item item = {
1128                 .spec = &data,
1129                 .mask = &mask,
1130         };
1131         struct field_modify_info reg_c_x[] = {
1132                 [1] = {0, 0, 0},
1133         };
1134         int reg;
1135
1136         if (!mask)
1137                 return rte_flow_error_set(error, EINVAL,
1138                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1139                                           NULL, "zero mark action mask");
1140         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1141         if (reg < 0)
1142                 return reg;
1143         MLX5_ASSERT(reg > 0);
1144         if (reg == REG_C_0) {
1145                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1146                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1147
1148                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1149                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1150                 mask = rte_cpu_to_be_32(mask << shl_c0);
1151         }
1152         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1153         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1154                                              MLX5_MODIFICATION_TYPE_SET, error);
1155 }
1156
1157 /**
1158  * Get metadata register index for specified steering domain.
1159  *
1160  * @param[in] dev
1161  *   Pointer to the rte_eth_dev structure.
1162  * @param[in] attr
1163  *   Attributes of flow to determine steering domain.
1164  * @param[out] error
1165  *   Pointer to the error structure.
1166  *
1167  * @return
1168  *   positive index on success, a negative errno value otherwise
1169  *   and rte_errno is set.
1170  */
1171 static enum modify_reg
1172 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1173                          const struct rte_flow_attr *attr,
1174                          struct rte_flow_error *error)
1175 {
1176         int reg =
1177                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178                                           MLX5_METADATA_FDB :
1179                                             attr->egress ?
1180                                             MLX5_METADATA_TX :
1181                                             MLX5_METADATA_RX, 0, error);
1182         if (reg < 0)
1183                 return rte_flow_error_set(error,
1184                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1185                                           NULL, "unavailable "
1186                                           "metadata register");
1187         return reg;
1188 }
1189
1190 /**
1191  * Convert SET_META action to DV specification.
1192  *
1193  * @param[in] dev
1194  *   Pointer to the rte_eth_dev structure.
1195  * @param[in,out] resource
1196  *   Pointer to the modify-header resource.
1197  * @param[in] attr
1198  *   Attributes of flow that includes this item.
1199  * @param[in] conf
1200  *   Pointer to action specification.
1201  * @param[out] error
1202  *   Pointer to the error structure.
1203  *
1204  * @return
1205  *   0 on success, a negative errno value otherwise and rte_errno is set.
1206  */
1207 static int
1208 flow_dv_convert_action_set_meta
1209                         (struct rte_eth_dev *dev,
1210                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1211                          const struct rte_flow_attr *attr,
1212                          const struct rte_flow_action_set_meta *conf,
1213                          struct rte_flow_error *error)
1214 {
1215         uint32_t data = conf->data;
1216         uint32_t mask = conf->mask;
1217         struct rte_flow_item item = {
1218                 .spec = &data,
1219                 .mask = &mask,
1220         };
1221         struct field_modify_info reg_c_x[] = {
1222                 [1] = {0, 0, 0},
1223         };
1224         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225
1226         if (reg < 0)
1227                 return reg;
1228         MLX5_ASSERT(reg != REG_NON);
1229         /*
1230          * In datapath code there is no endianness
1231          * coversions for perfromance reasons, all
1232          * pattern conversions are done in rte_flow.
1233          */
1234         if (reg == REG_C_0) {
1235                 struct mlx5_priv *priv = dev->data->dev_private;
1236                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1237                 uint32_t shl_c0;
1238
1239                 MLX5_ASSERT(msk_c0);
1240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1241                 shl_c0 = rte_bsf32(msk_c0);
1242 #else
1243                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 #endif
1245                 mask <<= shl_c0;
1246                 data <<= shl_c0;
1247                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1248         }
1249         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1250         /* The routine expects parameters in memory as big-endian ones. */
1251         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1252                                              MLX5_MODIFICATION_TYPE_SET, error);
1253 }
1254
1255 /**
1256  * Convert modify-header set IPv4 DSCP action to DV specification.
1257  *
1258  * @param[in,out] resource
1259  *   Pointer to the modify-header resource.
1260  * @param[in] action
1261  *   Pointer to action specification.
1262  * @param[out] error
1263  *   Pointer to the error structure.
1264  *
1265  * @return
1266  *   0 on success, a negative errno value otherwise and rte_errno is set.
1267  */
1268 static int
1269 flow_dv_convert_action_modify_ipv4_dscp
1270                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1271                          const struct rte_flow_action *action,
1272                          struct rte_flow_error *error)
1273 {
1274         const struct rte_flow_action_set_dscp *conf =
1275                 (const struct rte_flow_action_set_dscp *)(action->conf);
1276         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1277         struct rte_flow_item_ipv4 ipv4;
1278         struct rte_flow_item_ipv4 ipv4_mask;
1279
1280         memset(&ipv4, 0, sizeof(ipv4));
1281         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1282         ipv4.hdr.type_of_service = conf->dscp;
1283         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1284         item.spec = &ipv4;
1285         item.mask = &ipv4_mask;
1286         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1287                                              MLX5_MODIFICATION_TYPE_SET, error);
1288 }
1289
1290 /**
1291  * Convert modify-header set IPv6 DSCP action to DV specification.
1292  *
1293  * @param[in,out] resource
1294  *   Pointer to the modify-header resource.
1295  * @param[in] action
1296  *   Pointer to action specification.
1297  * @param[out] error
1298  *   Pointer to the error structure.
1299  *
1300  * @return
1301  *   0 on success, a negative errno value otherwise and rte_errno is set.
1302  */
1303 static int
1304 flow_dv_convert_action_modify_ipv6_dscp
1305                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1306                          const struct rte_flow_action *action,
1307                          struct rte_flow_error *error)
1308 {
1309         const struct rte_flow_action_set_dscp *conf =
1310                 (const struct rte_flow_action_set_dscp *)(action->conf);
1311         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1312         struct rte_flow_item_ipv6 ipv6;
1313         struct rte_flow_item_ipv6 ipv6_mask;
1314
1315         memset(&ipv6, 0, sizeof(ipv6));
1316         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1317         /*
1318          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1319          * rdma-core only accept the DSCP bits byte aligned start from
1320          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1321          * bits in IPv6 case as rdma-core requires byte aligned value.
1322          */
1323         ipv6.hdr.vtc_flow = conf->dscp;
1324         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1325         item.spec = &ipv6;
1326         item.mask = &ipv6_mask;
1327         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1328                                              MLX5_MODIFICATION_TYPE_SET, error);
1329 }
1330
1331 static int
1332 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1333 {
1334         switch (field) {
1335         case RTE_FLOW_FIELD_START:
1336                 return 32;
1337         case RTE_FLOW_FIELD_MAC_DST:
1338         case RTE_FLOW_FIELD_MAC_SRC:
1339                 return 48;
1340         case RTE_FLOW_FIELD_VLAN_TYPE:
1341                 return 16;
1342         case RTE_FLOW_FIELD_VLAN_ID:
1343                 return 12;
1344         case RTE_FLOW_FIELD_MAC_TYPE:
1345                 return 16;
1346         case RTE_FLOW_FIELD_IPV4_DSCP:
1347                 return 6;
1348         case RTE_FLOW_FIELD_IPV4_TTL:
1349                 return 8;
1350         case RTE_FLOW_FIELD_IPV4_SRC:
1351         case RTE_FLOW_FIELD_IPV4_DST:
1352                 return 32;
1353         case RTE_FLOW_FIELD_IPV6_DSCP:
1354                 return 6;
1355         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1356                 return 8;
1357         case RTE_FLOW_FIELD_IPV6_SRC:
1358         case RTE_FLOW_FIELD_IPV6_DST:
1359                 return 128;
1360         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1361         case RTE_FLOW_FIELD_TCP_PORT_DST:
1362                 return 16;
1363         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1364         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1365                 return 32;
1366         case RTE_FLOW_FIELD_TCP_FLAGS:
1367                 return 6;
1368         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1369         case RTE_FLOW_FIELD_UDP_PORT_DST:
1370                 return 16;
1371         case RTE_FLOW_FIELD_VXLAN_VNI:
1372         case RTE_FLOW_FIELD_GENEVE_VNI:
1373                 return 24;
1374         case RTE_FLOW_FIELD_GTP_TEID:
1375         case RTE_FLOW_FIELD_TAG:
1376                 return 32;
1377         case RTE_FLOW_FIELD_MARK:
1378                 return 24;
1379         case RTE_FLOW_FIELD_META:
1380                 return 32;
1381         case RTE_FLOW_FIELD_POINTER:
1382         case RTE_FLOW_FIELD_VALUE:
1383                 return 64;
1384         default:
1385                 MLX5_ASSERT(false);
1386         }
1387         return 0;
1388 }
1389
1390 static void
1391 mlx5_flow_field_id_to_modify_info
1392                 (const struct rte_flow_action_modify_data *data,
1393                  struct field_modify_info *info,
1394                  uint32_t *mask, uint32_t *value,
1395                  uint32_t width, uint32_t dst_width,
1396                  struct rte_eth_dev *dev,
1397                  const struct rte_flow_attr *attr,
1398                  struct rte_flow_error *error)
1399 {
1400         uint32_t idx = 0;
1401         uint64_t val = 0;
1402         switch (data->field) {
1403         case RTE_FLOW_FIELD_START:
1404                 /* not supported yet */
1405                 MLX5_ASSERT(false);
1406                 break;
1407         case RTE_FLOW_FIELD_MAC_DST:
1408                 if (mask) {
1409                         if (data->offset < 32) {
1410                                 info[idx] = (struct field_modify_info){4, 0,
1411                                                 MLX5_MODI_OUT_DMAC_47_16};
1412                                 if (width < 32) {
1413                                         mask[idx] =
1414                                                 rte_cpu_to_be_32(0xffffffff >>
1415                                                                  (32 - width));
1416                                         width = 0;
1417                                 } else {
1418                                         mask[idx] = RTE_BE32(0xffffffff);
1419                                         width -= 32;
1420                                 }
1421                                 if (!width)
1422                                         break;
1423                                 ++idx;
1424                         }
1425                         info[idx] = (struct field_modify_info){2, 4 * idx,
1426                                                 MLX5_MODI_OUT_DMAC_15_0};
1427                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1428                 } else {
1429                         if (data->offset < 32)
1430                                 info[idx++] = (struct field_modify_info){4, 0,
1431                                                 MLX5_MODI_OUT_DMAC_47_16};
1432                         info[idx] = (struct field_modify_info){2, 0,
1433                                                 MLX5_MODI_OUT_DMAC_15_0};
1434                 }
1435                 break;
1436         case RTE_FLOW_FIELD_MAC_SRC:
1437                 if (mask) {
1438                         if (data->offset < 32) {
1439                                 info[idx] = (struct field_modify_info){4, 0,
1440                                                 MLX5_MODI_OUT_SMAC_47_16};
1441                                 if (width < 32) {
1442                                         mask[idx] =
1443                                                 rte_cpu_to_be_32(0xffffffff >>
1444                                                                 (32 - width));
1445                                         width = 0;
1446                                 } else {
1447                                         mask[idx] = RTE_BE32(0xffffffff);
1448                                         width -= 32;
1449                                 }
1450                                 if (!width)
1451                                         break;
1452                                 ++idx;
1453                         }
1454                         info[idx] = (struct field_modify_info){2, 4 * idx,
1455                                                 MLX5_MODI_OUT_SMAC_15_0};
1456                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1457                 } else {
1458                         if (data->offset < 32)
1459                                 info[idx++] = (struct field_modify_info){4, 0,
1460                                                 MLX5_MODI_OUT_SMAC_47_16};
1461                         info[idx] = (struct field_modify_info){2, 0,
1462                                                 MLX5_MODI_OUT_SMAC_15_0};
1463                 }
1464                 break;
1465         case RTE_FLOW_FIELD_VLAN_TYPE:
1466                 /* not supported yet */
1467                 break;
1468         case RTE_FLOW_FIELD_VLAN_ID:
1469                 info[idx] = (struct field_modify_info){2, 0,
1470                                         MLX5_MODI_OUT_FIRST_VID};
1471                 if (mask)
1472                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1473                 break;
1474         case RTE_FLOW_FIELD_MAC_TYPE:
1475                 info[idx] = (struct field_modify_info){2, 0,
1476                                         MLX5_MODI_OUT_ETHERTYPE};
1477                 if (mask)
1478                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1479                 break;
1480         case RTE_FLOW_FIELD_IPV4_DSCP:
1481                 info[idx] = (struct field_modify_info){1, 0,
1482                                         MLX5_MODI_OUT_IP_DSCP};
1483                 if (mask)
1484                         mask[idx] = 0x3f >> (6 - width);
1485                 break;
1486         case RTE_FLOW_FIELD_IPV4_TTL:
1487                 info[idx] = (struct field_modify_info){1, 0,
1488                                         MLX5_MODI_OUT_IPV4_TTL};
1489                 if (mask)
1490                         mask[idx] = 0xff >> (8 - width);
1491                 break;
1492         case RTE_FLOW_FIELD_IPV4_SRC:
1493                 info[idx] = (struct field_modify_info){4, 0,
1494                                         MLX5_MODI_OUT_SIPV4};
1495                 if (mask)
1496                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1497                                                      (32 - width));
1498                 break;
1499         case RTE_FLOW_FIELD_IPV4_DST:
1500                 info[idx] = (struct field_modify_info){4, 0,
1501                                         MLX5_MODI_OUT_DIPV4};
1502                 if (mask)
1503                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1504                                                      (32 - width));
1505                 break;
1506         case RTE_FLOW_FIELD_IPV6_DSCP:
1507                 info[idx] = (struct field_modify_info){1, 0,
1508                                         MLX5_MODI_OUT_IP_DSCP};
1509                 if (mask)
1510                         mask[idx] = 0x3f >> (6 - width);
1511                 break;
1512         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1513                 info[idx] = (struct field_modify_info){1, 0,
1514                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1515                 if (mask)
1516                         mask[idx] = 0xff >> (8 - width);
1517                 break;
1518         case RTE_FLOW_FIELD_IPV6_SRC:
1519                 if (mask) {
1520                         if (data->offset < 32) {
1521                                 info[idx] = (struct field_modify_info){4,
1522                                                 4 * idx,
1523                                                 MLX5_MODI_OUT_SIPV6_31_0};
1524                                 if (width < 32) {
1525                                         mask[idx] =
1526                                                 rte_cpu_to_be_32(0xffffffff >>
1527                                                                  (32 - width));
1528                                         width = 0;
1529                                 } else {
1530                                         mask[idx] = RTE_BE32(0xffffffff);
1531                                         width -= 32;
1532                                 }
1533                                 if (!width)
1534                                         break;
1535                                 ++idx;
1536                         }
1537                         if (data->offset < 64) {
1538                                 info[idx] = (struct field_modify_info){4,
1539                                                 4 * idx,
1540                                                 MLX5_MODI_OUT_SIPV6_63_32};
1541                                 if (width < 32) {
1542                                         mask[idx] =
1543                                                 rte_cpu_to_be_32(0xffffffff >>
1544                                                                  (32 - width));
1545                                         width = 0;
1546                                 } else {
1547                                         mask[idx] = RTE_BE32(0xffffffff);
1548                                         width -= 32;
1549                                 }
1550                                 if (!width)
1551                                         break;
1552                                 ++idx;
1553                         }
1554                         if (data->offset < 96) {
1555                                 info[idx] = (struct field_modify_info){4,
1556                                                 4 * idx,
1557                                                 MLX5_MODI_OUT_SIPV6_95_64};
1558                                 if (width < 32) {
1559                                         mask[idx] =
1560                                                 rte_cpu_to_be_32(0xffffffff >>
1561                                                                  (32 - width));
1562                                         width = 0;
1563                                 } else {
1564                                         mask[idx] = RTE_BE32(0xffffffff);
1565                                         width -= 32;
1566                                 }
1567                                 if (!width)
1568                                         break;
1569                                 ++idx;
1570                         }
1571                         info[idx] = (struct field_modify_info){4, 4 * idx,
1572                                                 MLX5_MODI_OUT_SIPV6_127_96};
1573                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574                                                      (32 - width));
1575                 } else {
1576                         if (data->offset < 32)
1577                                 info[idx++] = (struct field_modify_info){4, 0,
1578                                                 MLX5_MODI_OUT_SIPV6_31_0};
1579                         if (data->offset < 64)
1580                                 info[idx++] = (struct field_modify_info){4, 0,
1581                                                 MLX5_MODI_OUT_SIPV6_63_32};
1582                         if (data->offset < 96)
1583                                 info[idx++] = (struct field_modify_info){4, 0,
1584                                                 MLX5_MODI_OUT_SIPV6_95_64};
1585                         if (data->offset < 128)
1586                                 info[idx++] = (struct field_modify_info){4, 0,
1587                                                 MLX5_MODI_OUT_SIPV6_127_96};
1588                 }
1589                 break;
1590         case RTE_FLOW_FIELD_IPV6_DST:
1591                 if (mask) {
1592                         if (data->offset < 32) {
1593                                 info[idx] = (struct field_modify_info){4,
1594                                                 4 * idx,
1595                                                 MLX5_MODI_OUT_DIPV6_31_0};
1596                                 if (width < 32) {
1597                                         mask[idx] =
1598                                                 rte_cpu_to_be_32(0xffffffff >>
1599                                                                  (32 - width));
1600                                         width = 0;
1601                                 } else {
1602                                         mask[idx] = RTE_BE32(0xffffffff);
1603                                         width -= 32;
1604                                 }
1605                                 if (!width)
1606                                         break;
1607                                 ++idx;
1608                         }
1609                         if (data->offset < 64) {
1610                                 info[idx] = (struct field_modify_info){4,
1611                                                 4 * idx,
1612                                                 MLX5_MODI_OUT_DIPV6_63_32};
1613                                 if (width < 32) {
1614                                         mask[idx] =
1615                                                 rte_cpu_to_be_32(0xffffffff >>
1616                                                                  (32 - width));
1617                                         width = 0;
1618                                 } else {
1619                                         mask[idx] = RTE_BE32(0xffffffff);
1620                                         width -= 32;
1621                                 }
1622                                 if (!width)
1623                                         break;
1624                                 ++idx;
1625                         }
1626                         if (data->offset < 96) {
1627                                 info[idx] = (struct field_modify_info){4,
1628                                                 4 * idx,
1629                                                 MLX5_MODI_OUT_DIPV6_95_64};
1630                                 if (width < 32) {
1631                                         mask[idx] =
1632                                                 rte_cpu_to_be_32(0xffffffff >>
1633                                                                  (32 - width));
1634                                         width = 0;
1635                                 } else {
1636                                         mask[idx] = RTE_BE32(0xffffffff);
1637                                         width -= 32;
1638                                 }
1639                                 if (!width)
1640                                         break;
1641                                 ++idx;
1642                         }
1643                         info[idx] = (struct field_modify_info){4, 4 * idx,
1644                                                 MLX5_MODI_OUT_DIPV6_127_96};
1645                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1646                                                      (32 - width));
1647                 } else {
1648                         if (data->offset < 32)
1649                                 info[idx++] = (struct field_modify_info){4, 0,
1650                                                 MLX5_MODI_OUT_DIPV6_31_0};
1651                         if (data->offset < 64)
1652                                 info[idx++] = (struct field_modify_info){4, 0,
1653                                                 MLX5_MODI_OUT_DIPV6_63_32};
1654                         if (data->offset < 96)
1655                                 info[idx++] = (struct field_modify_info){4, 0,
1656                                                 MLX5_MODI_OUT_DIPV6_95_64};
1657                         if (data->offset < 128)
1658                                 info[idx++] = (struct field_modify_info){4, 0,
1659                                                 MLX5_MODI_OUT_DIPV6_127_96};
1660                 }
1661                 break;
1662         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1663                 info[idx] = (struct field_modify_info){2, 0,
1664                                         MLX5_MODI_OUT_TCP_SPORT};
1665                 if (mask)
1666                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1667                 break;
1668         case RTE_FLOW_FIELD_TCP_PORT_DST:
1669                 info[idx] = (struct field_modify_info){2, 0,
1670                                         MLX5_MODI_OUT_TCP_DPORT};
1671                 if (mask)
1672                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1673                 break;
1674         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1675                 info[idx] = (struct field_modify_info){4, 0,
1676                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1677                 if (mask)
1678                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1679                                                      (32 - width));
1680                 break;
1681         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1682                 info[idx] = (struct field_modify_info){4, 0,
1683                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1684                 if (mask)
1685                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1686                                                      (32 - width));
1687                 break;
1688         case RTE_FLOW_FIELD_TCP_FLAGS:
1689                 info[idx] = (struct field_modify_info){1, 0,
1690                                         MLX5_MODI_OUT_TCP_FLAGS};
1691                 if (mask)
1692                         mask[idx] = 0x3f >> (6 - width);
1693                 break;
1694         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1695                 info[idx] = (struct field_modify_info){2, 0,
1696                                         MLX5_MODI_OUT_UDP_SPORT};
1697                 if (mask)
1698                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1699                 break;
1700         case RTE_FLOW_FIELD_UDP_PORT_DST:
1701                 info[idx] = (struct field_modify_info){2, 0,
1702                                         MLX5_MODI_OUT_UDP_DPORT};
1703                 if (mask)
1704                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1705                 break;
1706         case RTE_FLOW_FIELD_VXLAN_VNI:
1707                 /* not supported yet */
1708                 break;
1709         case RTE_FLOW_FIELD_GENEVE_VNI:
1710                 /* not supported yet*/
1711                 break;
1712         case RTE_FLOW_FIELD_GTP_TEID:
1713                 info[idx] = (struct field_modify_info){4, 0,
1714                                         MLX5_MODI_GTP_TEID};
1715                 if (mask)
1716                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1717                                                      (32 - width));
1718                 break;
1719         case RTE_FLOW_FIELD_TAG:
1720                 {
1721                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1722                                                    data->level, error);
1723                         if (reg < 0)
1724                                 return;
1725                         MLX5_ASSERT(reg != REG_NON);
1726                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1727                         info[idx] = (struct field_modify_info){4, 0,
1728                                                 reg_to_field[reg]};
1729                         if (mask)
1730                                 mask[idx] =
1731                                         rte_cpu_to_be_32(0xffffffff >>
1732                                                          (32 - width));
1733                 }
1734                 break;
1735         case RTE_FLOW_FIELD_MARK:
1736                 {
1737                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1738                                                        0, error);
1739                         if (reg < 0)
1740                                 return;
1741                         MLX5_ASSERT(reg != REG_NON);
1742                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1743                         info[idx] = (struct field_modify_info){4, 0,
1744                                                 reg_to_field[reg]};
1745                         if (mask)
1746                                 mask[idx] =
1747                                         rte_cpu_to_be_32(0xffffffff >>
1748                                                          (32 - width));
1749                 }
1750                 break;
1751         case RTE_FLOW_FIELD_META:
1752                 {
1753                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1754                         if (reg < 0)
1755                                 return;
1756                         MLX5_ASSERT(reg != REG_NON);
1757                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1758                         info[idx] = (struct field_modify_info){4, 0,
1759                                                 reg_to_field[reg]};
1760                         if (mask)
1761                                 mask[idx] =
1762                                         rte_cpu_to_be_32(0xffffffff >>
1763                                                          (32 - width));
1764                 }
1765                 break;
1766         case RTE_FLOW_FIELD_POINTER:
1767         case RTE_FLOW_FIELD_VALUE:
1768                 if (data->field == RTE_FLOW_FIELD_POINTER)
1769                         memcpy(&val, (void *)(uintptr_t)data->value,
1770                                sizeof(uint64_t));
1771                 else
1772                         val = data->value;
1773                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1774                         if (mask[idx]) {
1775                                 if (dst_width > 16) {
1776                                         value[idx] = rte_cpu_to_be_32(val);
1777                                         val >>= 32;
1778                                 } else if (dst_width > 8) {
1779                                         value[idx] = rte_cpu_to_be_16(val);
1780                                         val >>= 16;
1781                                 } else {
1782                                         value[idx] = (uint8_t)val;
1783                                         val >>= 8;
1784                                 }
1785                                 if (!val)
1786                                         break;
1787                         }
1788                 }
1789                 break;
1790         default:
1791                 MLX5_ASSERT(false);
1792                 break;
1793         }
1794 }
1795
1796 /**
1797  * Convert modify_field action to DV specification.
1798  *
1799  * @param[in] dev
1800  *   Pointer to the rte_eth_dev structure.
1801  * @param[in,out] resource
1802  *   Pointer to the modify-header resource.
1803  * @param[in] action
1804  *   Pointer to action specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to the error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_convert_action_modify_field
1815                         (struct rte_eth_dev *dev,
1816                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1817                          const struct rte_flow_action *action,
1818                          const struct rte_flow_attr *attr,
1819                          struct rte_flow_error *error)
1820 {
1821         const struct rte_flow_action_modify_field *conf =
1822                 (const struct rte_flow_action_modify_field *)(action->conf);
1823         struct rte_flow_item item;
1824         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1825                                                                 {0, 0, 0} };
1826         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1827                                                                 {0, 0, 0} };
1828         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1830         uint32_t type;
1831         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1832
1833         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1834                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1835                 type = MLX5_MODIFICATION_TYPE_SET;
1836                 /** For SET fill the destination field (field) first. */
1837                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1838                         value, conf->width, dst_width, dev, attr, error);
1839                 /** Then copy immediate value from source as per mask. */
1840                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1841                         value, conf->width, dst_width, dev, attr, error);
1842                 item.spec = &value;
1843         } else {
1844                 type = MLX5_MODIFICATION_TYPE_COPY;
1845                 /** For COPY fill the destination field (dcopy) without mask. */
1846                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1847                         value, conf->width, dst_width, dev, attr, error);
1848                 /** Then construct the source field (field) with mask. */
1849                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1850                         value, conf->width, dst_width, dev, attr, error);
1851         }
1852         item.mask = &mask;
1853         return flow_dv_convert_modify_action(&item,
1854                         field, dcopy, resource, type, error);
1855 }
1856
1857 /**
1858  * Validate MARK item.
1859  *
1860  * @param[in] dev
1861  *   Pointer to the rte_eth_dev structure.
1862  * @param[in] item
1863  *   Item specification.
1864  * @param[in] attr
1865  *   Attributes of flow that includes this item.
1866  * @param[out] error
1867  *   Pointer to error structure.
1868  *
1869  * @return
1870  *   0 on success, a negative errno value otherwise and rte_errno is set.
1871  */
1872 static int
1873 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1874                            const struct rte_flow_item *item,
1875                            const struct rte_flow_attr *attr __rte_unused,
1876                            struct rte_flow_error *error)
1877 {
1878         struct mlx5_priv *priv = dev->data->dev_private;
1879         struct mlx5_dev_config *config = &priv->config;
1880         const struct rte_flow_item_mark *spec = item->spec;
1881         const struct rte_flow_item_mark *mask = item->mask;
1882         const struct rte_flow_item_mark nic_mask = {
1883                 .id = priv->sh->dv_mark_mask,
1884         };
1885         int ret;
1886
1887         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1888                 return rte_flow_error_set(error, ENOTSUP,
1889                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1890                                           "extended metadata feature"
1891                                           " isn't enabled");
1892         if (!mlx5_flow_ext_mreg_supported(dev))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "extended metadata register"
1896                                           " isn't supported");
1897         if (!nic_mask.id)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "extended metadata register"
1901                                           " isn't available");
1902         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1903         if (ret < 0)
1904                 return ret;
1905         if (!spec)
1906                 return rte_flow_error_set(error, EINVAL,
1907                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1908                                           item->spec,
1909                                           "data cannot be empty");
1910         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1911                 return rte_flow_error_set(error, EINVAL,
1912                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1913                                           &spec->id,
1914                                           "mark id exceeds the limit");
1915         if (!mask)
1916                 mask = &nic_mask;
1917         if (!mask->id)
1918                 return rte_flow_error_set(error, EINVAL,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1920                                         "mask cannot be zero");
1921
1922         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1923                                         (const uint8_t *)&nic_mask,
1924                                         sizeof(struct rte_flow_item_mark),
1925                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1926         if (ret < 0)
1927                 return ret;
1928         return 0;
1929 }
1930
1931 /**
1932  * Validate META item.
1933  *
1934  * @param[in] dev
1935  *   Pointer to the rte_eth_dev structure.
1936  * @param[in] item
1937  *   Item specification.
1938  * @param[in] attr
1939  *   Attributes of flow that includes this item.
1940  * @param[out] error
1941  *   Pointer to error structure.
1942  *
1943  * @return
1944  *   0 on success, a negative errno value otherwise and rte_errno is set.
1945  */
1946 static int
1947 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1948                            const struct rte_flow_item *item,
1949                            const struct rte_flow_attr *attr,
1950                            struct rte_flow_error *error)
1951 {
1952         struct mlx5_priv *priv = dev->data->dev_private;
1953         struct mlx5_dev_config *config = &priv->config;
1954         const struct rte_flow_item_meta *spec = item->spec;
1955         const struct rte_flow_item_meta *mask = item->mask;
1956         struct rte_flow_item_meta nic_mask = {
1957                 .data = UINT32_MAX
1958         };
1959         int reg;
1960         int ret;
1961
1962         if (!spec)
1963                 return rte_flow_error_set(error, EINVAL,
1964                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965                                           item->spec,
1966                                           "data cannot be empty");
1967         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1968                 if (!mlx5_flow_ext_mreg_supported(dev))
1969                         return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1971                                           "extended metadata register"
1972                                           " isn't supported");
1973                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1974                 if (reg < 0)
1975                         return reg;
1976                 if (reg == REG_NON)
1977                         return rte_flow_error_set(error, ENOTSUP,
1978                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1979                                         "unavalable extended metadata register");
1980                 if (reg == REG_B)
1981                         return rte_flow_error_set(error, ENOTSUP,
1982                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1983                                           "match on reg_b "
1984                                           "isn't supported");
1985                 if (reg != REG_A)
1986                         nic_mask.data = priv->sh->dv_meta_mask;
1987         } else {
1988                 if (attr->transfer)
1989                         return rte_flow_error_set(error, ENOTSUP,
1990                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                         "extended metadata feature "
1992                                         "should be enabled when "
1993                                         "meta item is requested "
1994                                         "with e-switch mode ");
1995                 if (attr->ingress)
1996                         return rte_flow_error_set(error, ENOTSUP,
1997                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1998                                         "match on metadata for ingress "
1999                                         "is not supported in legacy "
2000                                         "metadata mode");
2001         }
2002         if (!mask)
2003                 mask = &rte_flow_item_meta_mask;
2004         if (!mask->data)
2005                 return rte_flow_error_set(error, EINVAL,
2006                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2007                                         "mask cannot be zero");
2008
2009         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2010                                         (const uint8_t *)&nic_mask,
2011                                         sizeof(struct rte_flow_item_meta),
2012                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2013         return ret;
2014 }
2015
2016 /**
2017  * Validate TAG item.
2018  *
2019  * @param[in] dev
2020  *   Pointer to the rte_eth_dev structure.
2021  * @param[in] item
2022  *   Item specification.
2023  * @param[in] attr
2024  *   Attributes of flow that includes this item.
2025  * @param[out] error
2026  *   Pointer to error structure.
2027  *
2028  * @return
2029  *   0 on success, a negative errno value otherwise and rte_errno is set.
2030  */
2031 static int
2032 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2033                           const struct rte_flow_item *item,
2034                           const struct rte_flow_attr *attr __rte_unused,
2035                           struct rte_flow_error *error)
2036 {
2037         const struct rte_flow_item_tag *spec = item->spec;
2038         const struct rte_flow_item_tag *mask = item->mask;
2039         const struct rte_flow_item_tag nic_mask = {
2040                 .data = RTE_BE32(UINT32_MAX),
2041                 .index = 0xff,
2042         };
2043         int ret;
2044
2045         if (!mlx5_flow_ext_mreg_supported(dev))
2046                 return rte_flow_error_set(error, ENOTSUP,
2047                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2048                                           "extensive metadata register"
2049                                           " isn't supported");
2050         if (!spec)
2051                 return rte_flow_error_set(error, EINVAL,
2052                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2053                                           item->spec,
2054                                           "data cannot be empty");
2055         if (!mask)
2056                 mask = &rte_flow_item_tag_mask;
2057         if (!mask->data)
2058                 return rte_flow_error_set(error, EINVAL,
2059                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2060                                         "mask cannot be zero");
2061
2062         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2063                                         (const uint8_t *)&nic_mask,
2064                                         sizeof(struct rte_flow_item_tag),
2065                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066         if (ret < 0)
2067                 return ret;
2068         if (mask->index != 0xff)
2069                 return rte_flow_error_set(error, EINVAL,
2070                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2071                                           "partial mask for tag index"
2072                                           " is not supported");
2073         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2074         if (ret < 0)
2075                 return ret;
2076         MLX5_ASSERT(ret != REG_NON);
2077         return 0;
2078 }
2079
2080 /**
2081  * Validate vport item.
2082  *
2083  * @param[in] dev
2084  *   Pointer to the rte_eth_dev structure.
2085  * @param[in] item
2086  *   Item specification.
2087  * @param[in] attr
2088  *   Attributes of flow that includes this item.
2089  * @param[in] item_flags
2090  *   Bit-fields that holds the items detected until now.
2091  * @param[out] error
2092  *   Pointer to error structure.
2093  *
2094  * @return
2095  *   0 on success, a negative errno value otherwise and rte_errno is set.
2096  */
2097 static int
2098 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2099                               const struct rte_flow_item *item,
2100                               const struct rte_flow_attr *attr,
2101                               uint64_t item_flags,
2102                               struct rte_flow_error *error)
2103 {
2104         const struct rte_flow_item_port_id *spec = item->spec;
2105         const struct rte_flow_item_port_id *mask = item->mask;
2106         const struct rte_flow_item_port_id switch_mask = {
2107                         .id = 0xffffffff,
2108         };
2109         struct mlx5_priv *esw_priv;
2110         struct mlx5_priv *dev_priv;
2111         int ret;
2112
2113         if (!attr->transfer)
2114                 return rte_flow_error_set(error, EINVAL,
2115                                           RTE_FLOW_ERROR_TYPE_ITEM,
2116                                           NULL,
2117                                           "match on port id is valid only"
2118                                           " when transfer flag is enabled");
2119         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2122                                           "multiple source ports are not"
2123                                           " supported");
2124         if (!mask)
2125                 mask = &switch_mask;
2126         if (mask->id != 0xffffffff)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2129                                            mask,
2130                                            "no support for partial mask on"
2131                                            " \"id\" field");
2132         ret = mlx5_flow_item_acceptable
2133                                 (item, (const uint8_t *)mask,
2134                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2135                                  sizeof(struct rte_flow_item_port_id),
2136                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2137         if (ret)
2138                 return ret;
2139         if (!spec)
2140                 return 0;
2141         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2142         if (!esw_priv)
2143                 return rte_flow_error_set(error, rte_errno,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2145                                           "failed to obtain E-Switch info for"
2146                                           " port");
2147         dev_priv = mlx5_dev_to_eswitch_info(dev);
2148         if (!dev_priv)
2149                 return rte_flow_error_set(error, rte_errno,
2150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2151                                           NULL,
2152                                           "failed to obtain E-Switch info");
2153         if (esw_priv->domain_id != dev_priv->domain_id)
2154                 return rte_flow_error_set(error, EINVAL,
2155                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2156                                           "cannot match on a port from a"
2157                                           " different E-Switch");
2158         return 0;
2159 }
2160
2161 /**
2162  * Validate VLAN item.
2163  *
2164  * @param[in] item
2165  *   Item specification.
2166  * @param[in] item_flags
2167  *   Bit-fields that holds the items detected until now.
2168  * @param[in] dev
2169  *   Ethernet device flow is being created on.
2170  * @param[out] error
2171  *   Pointer to error structure.
2172  *
2173  * @return
2174  *   0 on success, a negative errno value otherwise and rte_errno is set.
2175  */
2176 static int
2177 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2178                            uint64_t item_flags,
2179                            struct rte_eth_dev *dev,
2180                            struct rte_flow_error *error)
2181 {
2182         const struct rte_flow_item_vlan *mask = item->mask;
2183         const struct rte_flow_item_vlan nic_mask = {
2184                 .tci = RTE_BE16(UINT16_MAX),
2185                 .inner_type = RTE_BE16(UINT16_MAX),
2186                 .has_more_vlan = 1,
2187         };
2188         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2189         int ret;
2190         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2191                                         MLX5_FLOW_LAYER_INNER_L4) :
2192                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2193                                         MLX5_FLOW_LAYER_OUTER_L4);
2194         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2195                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2196
2197         if (item_flags & vlanm)
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2200                                           "multiple VLAN layers not supported");
2201         else if ((item_flags & l34m) != 0)
2202                 return rte_flow_error_set(error, EINVAL,
2203                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2204                                           "VLAN cannot follow L3/L4 layer");
2205         if (!mask)
2206                 mask = &rte_flow_item_vlan_mask;
2207         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2208                                         (const uint8_t *)&nic_mask,
2209                                         sizeof(struct rte_flow_item_vlan),
2210                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2211         if (ret)
2212                 return ret;
2213         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2214                 struct mlx5_priv *priv = dev->data->dev_private;
2215
2216                 if (priv->vmwa_context) {
2217                         /*
2218                          * Non-NULL context means we have a virtual machine
2219                          * and SR-IOV enabled, we have to create VLAN interface
2220                          * to make hypervisor to setup E-Switch vport
2221                          * context correctly. We avoid creating the multiple
2222                          * VLAN interfaces, so we cannot support VLAN tag mask.
2223                          */
2224                         return rte_flow_error_set(error, EINVAL,
2225                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2226                                                   item,
2227                                                   "VLAN tag mask is not"
2228                                                   " supported in virtual"
2229                                                   " environment");
2230                 }
2231         }
2232         return 0;
2233 }
2234
2235 /*
2236  * GTP flags are contained in 1 byte of the format:
2237  * -------------------------------------------
2238  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2239  * |-----------------------------------------|
2240  * | value | Version | PT | Res | E | S | PN |
2241  * -------------------------------------------
2242  *
2243  * Matching is supported only for GTP flags E, S, PN.
2244  */
2245 #define MLX5_GTP_FLAGS_MASK     0x07
2246
2247 /**
2248  * Validate GTP item.
2249  *
2250  * @param[in] dev
2251  *   Pointer to the rte_eth_dev structure.
2252  * @param[in] item
2253  *   Item specification.
2254  * @param[in] item_flags
2255  *   Bit-fields that holds the items detected until now.
2256  * @param[out] error
2257  *   Pointer to error structure.
2258  *
2259  * @return
2260  *   0 on success, a negative errno value otherwise and rte_errno is set.
2261  */
2262 static int
2263 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2264                           const struct rte_flow_item *item,
2265                           uint64_t item_flags,
2266                           struct rte_flow_error *error)
2267 {
2268         struct mlx5_priv *priv = dev->data->dev_private;
2269         const struct rte_flow_item_gtp *spec = item->spec;
2270         const struct rte_flow_item_gtp *mask = item->mask;
2271         const struct rte_flow_item_gtp nic_mask = {
2272                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2273                 .msg_type = 0xff,
2274                 .teid = RTE_BE32(0xffffffff),
2275         };
2276
2277         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2278                 return rte_flow_error_set(error, ENOTSUP,
2279                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                                           "GTP support is not enabled");
2281         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2282                 return rte_flow_error_set(error, ENOTSUP,
2283                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2284                                           "multiple tunnel layers not"
2285                                           " supported");
2286         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2287                 return rte_flow_error_set(error, EINVAL,
2288                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                                           "no outer UDP layer found");
2290         if (!mask)
2291                 mask = &rte_flow_item_gtp_mask;
2292         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2293                 return rte_flow_error_set(error, ENOTSUP,
2294                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2295                                           "Match is supported for GTP"
2296                                           " flags only");
2297         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2298                                          (const uint8_t *)&nic_mask,
2299                                          sizeof(struct rte_flow_item_gtp),
2300                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2301 }
2302
2303 /**
2304  * Validate GTP PSC item.
2305  *
2306  * @param[in] item
2307  *   Item specification.
2308  * @param[in] last_item
2309  *   Previous validated item in the pattern items.
2310  * @param[in] gtp_item
2311  *   Previous GTP item specification.
2312  * @param[in] attr
2313  *   Pointer to flow attributes.
2314  * @param[out] error
2315  *   Pointer to error structure.
2316  *
2317  * @return
2318  *   0 on success, a negative errno value otherwise and rte_errno is set.
2319  */
2320 static int
2321 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2322                               uint64_t last_item,
2323                               const struct rte_flow_item *gtp_item,
2324                               const struct rte_flow_attr *attr,
2325                               struct rte_flow_error *error)
2326 {
2327         const struct rte_flow_item_gtp *gtp_spec;
2328         const struct rte_flow_item_gtp *gtp_mask;
2329         const struct rte_flow_item_gtp_psc *spec;
2330         const struct rte_flow_item_gtp_psc *mask;
2331         const struct rte_flow_item_gtp_psc nic_mask = {
2332                 .pdu_type = 0xFF,
2333                 .qfi = 0xFF,
2334         };
2335
2336         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2337                 return rte_flow_error_set
2338                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2339                          "GTP PSC item must be preceded with GTP item");
2340         gtp_spec = gtp_item->spec;
2341         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2342         /* GTP spec and E flag is requested to match zero. */
2343         if (gtp_spec &&
2344                 (gtp_mask->v_pt_rsv_flags &
2345                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2346                 return rte_flow_error_set
2347                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2348                          "GTP E flag must be 1 to match GTP PSC");
2349         /* Check the flow is not created in group zero. */
2350         if (!attr->transfer && !attr->group)
2351                 return rte_flow_error_set
2352                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2353                          "GTP PSC is not supported for group 0");
2354         /* GTP spec is here and E flag is requested to match zero. */
2355         if (!item->spec)
2356                 return 0;
2357         spec = item->spec;
2358         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2359         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2360                 return rte_flow_error_set
2361                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2362                          "PDU type should be smaller than 16");
2363         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2364                                          (const uint8_t *)&nic_mask,
2365                                          sizeof(struct rte_flow_item_gtp_psc),
2366                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2367 }
2368
2369 /**
2370  * Validate IPV4 item.
2371  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2372  * add specific validation of fragment_offset field,
2373  *
2374  * @param[in] item
2375  *   Item specification.
2376  * @param[in] item_flags
2377  *   Bit-fields that holds the items detected until now.
2378  * @param[out] error
2379  *   Pointer to error structure.
2380  *
2381  * @return
2382  *   0 on success, a negative errno value otherwise and rte_errno is set.
2383  */
2384 static int
2385 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2386                            uint64_t item_flags,
2387                            uint64_t last_item,
2388                            uint16_t ether_type,
2389                            struct rte_flow_error *error)
2390 {
2391         int ret;
2392         const struct rte_flow_item_ipv4 *spec = item->spec;
2393         const struct rte_flow_item_ipv4 *last = item->last;
2394         const struct rte_flow_item_ipv4 *mask = item->mask;
2395         rte_be16_t fragment_offset_spec = 0;
2396         rte_be16_t fragment_offset_last = 0;
2397         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2398                 .hdr = {
2399                         .src_addr = RTE_BE32(0xffffffff),
2400                         .dst_addr = RTE_BE32(0xffffffff),
2401                         .type_of_service = 0xff,
2402                         .fragment_offset = RTE_BE16(0xffff),
2403                         .next_proto_id = 0xff,
2404                         .time_to_live = 0xff,
2405                 },
2406         };
2407
2408         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2409                                            ether_type, &nic_ipv4_mask,
2410                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2411         if (ret < 0)
2412                 return ret;
2413         if (spec && mask)
2414                 fragment_offset_spec = spec->hdr.fragment_offset &
2415                                        mask->hdr.fragment_offset;
2416         if (!fragment_offset_spec)
2417                 return 0;
2418         /*
2419          * spec and mask are valid, enforce using full mask to make sure the
2420          * complete value is used correctly.
2421          */
2422         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2424                 return rte_flow_error_set(error, EINVAL,
2425                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2426                                           item, "must use full mask for"
2427                                           " fragment_offset");
2428         /*
2429          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2430          * indicating this is 1st fragment of fragmented packet.
2431          * This is not yet supported in MLX5, return appropriate error message.
2432          */
2433         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2434                 return rte_flow_error_set(error, ENOTSUP,
2435                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2436                                           "match on first fragment not "
2437                                           "supported");
2438         if (fragment_offset_spec && !last)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2441                                           "specified value not supported");
2442         /* spec and last are valid, validate the specified range. */
2443         fragment_offset_last = last->hdr.fragment_offset &
2444                                mask->hdr.fragment_offset;
2445         /*
2446          * Match on fragment_offset spec 0x2001 and last 0x3fff
2447          * means MF is 1 and frag-offset is > 0.
2448          * This packet is fragment 2nd and onward, excluding last.
2449          * This is not yet supported in MLX5, return appropriate
2450          * error message.
2451          */
2452         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2453             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2454                 return rte_flow_error_set(error, ENOTSUP,
2455                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2456                                           last, "match on following "
2457                                           "fragments not supported");
2458         /*
2459          * Match on fragment_offset spec 0x0001 and last 0x1fff
2460          * means MF is 0 and frag-offset is > 0.
2461          * This packet is last fragment of fragmented packet.
2462          * This is not yet supported in MLX5, return appropriate
2463          * error message.
2464          */
2465         if (fragment_offset_spec == RTE_BE16(1) &&
2466             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2467                 return rte_flow_error_set(error, ENOTSUP,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2469                                           last, "match on last "
2470                                           "fragment not supported");
2471         /*
2472          * Match on fragment_offset spec 0x0001 and last 0x3fff
2473          * means MF and/or frag-offset is not 0.
2474          * This is a fragmented packet.
2475          * Other range values are invalid and rejected.
2476          */
2477         if (!(fragment_offset_spec == RTE_BE16(1) &&
2478               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2481                                           "specified range not supported");
2482         return 0;
2483 }
2484
2485 /**
2486  * Validate IPV6 fragment extension item.
2487  *
2488  * @param[in] item
2489  *   Item specification.
2490  * @param[in] item_flags
2491  *   Bit-fields that holds the items detected until now.
2492  * @param[out] error
2493  *   Pointer to error structure.
2494  *
2495  * @return
2496  *   0 on success, a negative errno value otherwise and rte_errno is set.
2497  */
2498 static int
2499 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2500                                     uint64_t item_flags,
2501                                     struct rte_flow_error *error)
2502 {
2503         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2504         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2505         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2506         rte_be16_t frag_data_spec = 0;
2507         rte_be16_t frag_data_last = 0;
2508         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2509         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2510                                       MLX5_FLOW_LAYER_OUTER_L4;
2511         int ret = 0;
2512         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2513                 .hdr = {
2514                         .next_header = 0xff,
2515                         .frag_data = RTE_BE16(0xffff),
2516                 },
2517         };
2518
2519         if (item_flags & l4m)
2520                 return rte_flow_error_set(error, EINVAL,
2521                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2522                                           "ipv6 fragment extension item cannot "
2523                                           "follow L4 item.");
2524         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2525             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2526                 return rte_flow_error_set(error, EINVAL,
2527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2528                                           "ipv6 fragment extension item must "
2529                                           "follow ipv6 item");
2530         if (spec && mask)
2531                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2532         if (!frag_data_spec)
2533                 return 0;
2534         /*
2535          * spec and mask are valid, enforce using full mask to make sure the
2536          * complete value is used correctly.
2537          */
2538         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2539                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2540                 return rte_flow_error_set(error, EINVAL,
2541                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2542                                           item, "must use full mask for"
2543                                           " frag_data");
2544         /*
2545          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2546          * This is 1st fragment of fragmented packet.
2547          */
2548         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2549                 return rte_flow_error_set(error, ENOTSUP,
2550                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2551                                           "match on first fragment not "
2552                                           "supported");
2553         if (frag_data_spec && !last)
2554                 return rte_flow_error_set(error, EINVAL,
2555                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2556                                           "specified value not supported");
2557         ret = mlx5_flow_item_acceptable
2558                                 (item, (const uint8_t *)mask,
2559                                  (const uint8_t *)&nic_mask,
2560                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2561                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2562         if (ret)
2563                 return ret;
2564         /* spec and last are valid, validate the specified range. */
2565         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2566         /*
2567          * Match on frag_data spec 0x0009 and last 0xfff9
2568          * means M is 1 and frag-offset is > 0.
2569          * This packet is fragment 2nd and onward, excluding last.
2570          * This is not yet supported in MLX5, return appropriate
2571          * error message.
2572          */
2573         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2574                                        RTE_IPV6_EHDR_MF_MASK) &&
2575             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2578                                           last, "match on following "
2579                                           "fragments not supported");
2580         /*
2581          * Match on frag_data spec 0x0008 and last 0xfff8
2582          * means M is 0 and frag-offset is > 0.
2583          * This packet is last fragment of fragmented packet.
2584          * This is not yet supported in MLX5, return appropriate
2585          * error message.
2586          */
2587         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2588             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2589                 return rte_flow_error_set(error, ENOTSUP,
2590                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2591                                           last, "match on last "
2592                                           "fragment not supported");
2593         /* Other range values are invalid and rejected. */
2594         return rte_flow_error_set(error, EINVAL,
2595                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2596                                   "specified range not supported");
2597 }
2598
2599 /**
2600  * Validate the pop VLAN action.
2601  *
2602  * @param[in] dev
2603  *   Pointer to the rte_eth_dev structure.
2604  * @param[in] action_flags
2605  *   Holds the actions detected until now.
2606  * @param[in] action
2607  *   Pointer to the pop vlan action.
2608  * @param[in] item_flags
2609  *   The items found in this flow rule.
2610  * @param[in] attr
2611  *   Pointer to flow attributes.
2612  * @param[out] error
2613  *   Pointer to error structure.
2614  *
2615  * @return
2616  *   0 on success, a negative errno value otherwise and rte_errno is set.
2617  */
2618 static int
2619 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2620                                  uint64_t action_flags,
2621                                  const struct rte_flow_action *action,
2622                                  uint64_t item_flags,
2623                                  const struct rte_flow_attr *attr,
2624                                  struct rte_flow_error *error)
2625 {
2626         const struct mlx5_priv *priv = dev->data->dev_private;
2627
2628         (void)action;
2629         (void)attr;
2630         if (!priv->sh->pop_vlan_action)
2631                 return rte_flow_error_set(error, ENOTSUP,
2632                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2633                                           NULL,
2634                                           "pop vlan action is not supported");
2635         if (attr->egress)
2636                 return rte_flow_error_set(error, ENOTSUP,
2637                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2638                                           NULL,
2639                                           "pop vlan action not supported for "
2640                                           "egress");
2641         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2642                 return rte_flow_error_set(error, ENOTSUP,
2643                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2644                                           "no support for multiple VLAN "
2645                                           "actions");
2646         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2647         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2648             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2649                 return rte_flow_error_set(error, ENOTSUP,
2650                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2651                                           NULL,
2652                                           "cannot pop vlan after decap without "
2653                                           "match on inner vlan in the flow");
2654         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2655         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2656             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2657                 return rte_flow_error_set(error, ENOTSUP,
2658                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2659                                           NULL,
2660                                           "cannot pop vlan without a "
2661                                           "match on (outer) vlan in the flow");
2662         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2663                 return rte_flow_error_set(error, EINVAL,
2664                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2665                                           "wrong action order, port_id should "
2666                                           "be after pop VLAN action");
2667         if (!attr->transfer && priv->representor)
2668                 return rte_flow_error_set(error, ENOTSUP,
2669                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2670                                           "pop vlan action for VF representor "
2671                                           "not supported on NIC table");
2672         return 0;
2673 }
2674
2675 /**
2676  * Get VLAN default info from vlan match info.
2677  *
2678  * @param[in] items
2679  *   the list of item specifications.
2680  * @param[out] vlan
2681  *   pointer VLAN info to fill to.
2682  *
2683  * @return
2684  *   0 on success, a negative errno value otherwise and rte_errno is set.
2685  */
2686 static void
2687 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2688                                   struct rte_vlan_hdr *vlan)
2689 {
2690         const struct rte_flow_item_vlan nic_mask = {
2691                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2692                                 MLX5DV_FLOW_VLAN_VID_MASK),
2693                 .inner_type = RTE_BE16(0xffff),
2694         };
2695
2696         if (items == NULL)
2697                 return;
2698         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2699                 int type = items->type;
2700
2701                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2702                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2703                         break;
2704         }
2705         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2706                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2707                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2708
2709                 /* If VLAN item in pattern doesn't contain data, return here. */
2710                 if (!vlan_v)
2711                         return;
2712                 if (!vlan_m)
2713                         vlan_m = &nic_mask;
2714                 /* Only full match values are accepted */
2715                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2716                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2717                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2718                         vlan->vlan_tci |=
2719                                 rte_be_to_cpu_16(vlan_v->tci &
2720                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2721                 }
2722                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2723                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2724                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2725                         vlan->vlan_tci |=
2726                                 rte_be_to_cpu_16(vlan_v->tci &
2727                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2728                 }
2729                 if (vlan_m->inner_type == nic_mask.inner_type)
2730                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2731                                                            vlan_m->inner_type);
2732         }
2733 }
2734
2735 /**
2736  * Validate the push VLAN action.
2737  *
2738  * @param[in] dev
2739  *   Pointer to the rte_eth_dev structure.
2740  * @param[in] action_flags
2741  *   Holds the actions detected until now.
2742  * @param[in] item_flags
2743  *   The items found in this flow rule.
2744  * @param[in] action
2745  *   Pointer to the action structure.
2746  * @param[in] attr
2747  *   Pointer to flow attributes
2748  * @param[out] error
2749  *   Pointer to error structure.
2750  *
2751  * @return
2752  *   0 on success, a negative errno value otherwise and rte_errno is set.
2753  */
2754 static int
2755 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2756                                   uint64_t action_flags,
2757                                   const struct rte_flow_item_vlan *vlan_m,
2758                                   const struct rte_flow_action *action,
2759                                   const struct rte_flow_attr *attr,
2760                                   struct rte_flow_error *error)
2761 {
2762         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2763         const struct mlx5_priv *priv = dev->data->dev_private;
2764
2765         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2766             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2767                 return rte_flow_error_set(error, EINVAL,
2768                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2769                                           "invalid vlan ethertype");
2770         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2771                 return rte_flow_error_set(error, EINVAL,
2772                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2773                                           "wrong action order, port_id should "
2774                                           "be after push VLAN");
2775         if (!attr->transfer && priv->representor)
2776                 return rte_flow_error_set(error, ENOTSUP,
2777                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2778                                           "push vlan action for VF representor "
2779                                           "not supported on NIC table");
2780         if (vlan_m &&
2781             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2782             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2783                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2784             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2785             !(mlx5_flow_find_action
2786                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "not full match mask on VLAN PCP and "
2790                                           "there is no of_set_vlan_pcp action, "
2791                                           "push VLAN action cannot figure out "
2792                                           "PCP value");
2793         if (vlan_m &&
2794             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2795             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2796                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2797             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2798             !(mlx5_flow_find_action
2799                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2800                 return rte_flow_error_set(error, EINVAL,
2801                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2802                                           "not full match mask on VLAN VID and "
2803                                           "there is no of_set_vlan_vid action, "
2804                                           "push VLAN action cannot figure out "
2805                                           "VID value");
2806         (void)attr;
2807         return 0;
2808 }
2809
2810 /**
2811  * Validate the set VLAN PCP.
2812  *
2813  * @param[in] action_flags
2814  *   Holds the actions detected until now.
2815  * @param[in] actions
2816  *   Pointer to the list of actions remaining in the flow rule.
2817  * @param[out] error
2818  *   Pointer to error structure.
2819  *
2820  * @return
2821  *   0 on success, a negative errno value otherwise and rte_errno is set.
2822  */
2823 static int
2824 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2825                                      const struct rte_flow_action actions[],
2826                                      struct rte_flow_error *error)
2827 {
2828         const struct rte_flow_action *action = actions;
2829         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2830
2831         if (conf->vlan_pcp > 7)
2832                 return rte_flow_error_set(error, EINVAL,
2833                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2834                                           "VLAN PCP value is too big");
2835         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2836                 return rte_flow_error_set(error, ENOTSUP,
2837                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2838                                           "set VLAN PCP action must follow "
2839                                           "the push VLAN action");
2840         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2841                 return rte_flow_error_set(error, ENOTSUP,
2842                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2843                                           "Multiple VLAN PCP modification are "
2844                                           "not supported");
2845         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2846                 return rte_flow_error_set(error, EINVAL,
2847                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2848                                           "wrong action order, port_id should "
2849                                           "be after set VLAN PCP");
2850         return 0;
2851 }
2852
2853 /**
2854  * Validate the set VLAN VID.
2855  *
2856  * @param[in] item_flags
2857  *   Holds the items detected in this rule.
2858  * @param[in] action_flags
2859  *   Holds the actions detected until now.
2860  * @param[in] actions
2861  *   Pointer to the list of actions remaining in the flow rule.
2862  * @param[out] error
2863  *   Pointer to error structure.
2864  *
2865  * @return
2866  *   0 on success, a negative errno value otherwise and rte_errno is set.
2867  */
2868 static int
2869 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2870                                      uint64_t action_flags,
2871                                      const struct rte_flow_action actions[],
2872                                      struct rte_flow_error *error)
2873 {
2874         const struct rte_flow_action *action = actions;
2875         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2876
2877         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2878                 return rte_flow_error_set(error, EINVAL,
2879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2880                                           "VLAN VID value is too big");
2881         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2882             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2883                 return rte_flow_error_set(error, ENOTSUP,
2884                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2885                                           "set VLAN VID action must follow push"
2886                                           " VLAN action or match on VLAN item");
2887         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2888                 return rte_flow_error_set(error, ENOTSUP,
2889                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2890                                           "Multiple VLAN VID modifications are "
2891                                           "not supported");
2892         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2893                 return rte_flow_error_set(error, EINVAL,
2894                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2895                                           "wrong action order, port_id should "
2896                                           "be after set VLAN VID");
2897         return 0;
2898 }
2899
2900 /*
2901  * Validate the FLAG action.
2902  *
2903  * @param[in] dev
2904  *   Pointer to the rte_eth_dev structure.
2905  * @param[in] action_flags
2906  *   Holds the actions detected until now.
2907  * @param[in] attr
2908  *   Pointer to flow attributes
2909  * @param[out] error
2910  *   Pointer to error structure.
2911  *
2912  * @return
2913  *   0 on success, a negative errno value otherwise and rte_errno is set.
2914  */
2915 static int
2916 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         int ret;
2924
2925         /* Fall back if no extended metadata register support. */
2926         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2927                 return mlx5_flow_validate_action_flag(action_flags, attr,
2928                                                       error);
2929         /* Extensive metadata mode requires registers. */
2930         if (!mlx5_flow_ext_mreg_supported(dev))
2931                 return rte_flow_error_set(error, ENOTSUP,
2932                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933                                           "no metadata registers "
2934                                           "to support flag action");
2935         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2936                 return rte_flow_error_set(error, ENOTSUP,
2937                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2938                                           "extended metadata register"
2939                                           " isn't available");
2940         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2941         if (ret < 0)
2942                 return ret;
2943         MLX5_ASSERT(ret > 0);
2944         if (action_flags & MLX5_FLOW_ACTION_MARK)
2945                 return rte_flow_error_set(error, EINVAL,
2946                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2947                                           "can't mark and flag in same flow");
2948         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949                 return rte_flow_error_set(error, EINVAL,
2950                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2951                                           "can't have 2 flag"
2952                                           " actions in same flow");
2953         return 0;
2954 }
2955
2956 /**
2957  * Validate MARK action.
2958  *
2959  * @param[in] dev
2960  *   Pointer to the rte_eth_dev structure.
2961  * @param[in] action
2962  *   Pointer to action.
2963  * @param[in] action_flags
2964  *   Holds the actions detected until now.
2965  * @param[in] attr
2966  *   Pointer to flow attributes
2967  * @param[out] error
2968  *   Pointer to error structure.
2969  *
2970  * @return
2971  *   0 on success, a negative errno value otherwise and rte_errno is set.
2972  */
2973 static int
2974 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2975                              const struct rte_flow_action *action,
2976                              uint64_t action_flags,
2977                              const struct rte_flow_attr *attr,
2978                              struct rte_flow_error *error)
2979 {
2980         struct mlx5_priv *priv = dev->data->dev_private;
2981         struct mlx5_dev_config *config = &priv->config;
2982         const struct rte_flow_action_mark *mark = action->conf;
2983         int ret;
2984
2985         if (is_tunnel_offload_active(dev))
2986                 return rte_flow_error_set(error, ENOTSUP,
2987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2988                                           "no mark action "
2989                                           "if tunnel offload active");
2990         /* Fall back if no extended metadata register support. */
2991         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2992                 return mlx5_flow_validate_action_mark(action, action_flags,
2993                                                       attr, error);
2994         /* Extensive metadata mode requires registers. */
2995         if (!mlx5_flow_ext_mreg_supported(dev))
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2998                                           "no metadata registers "
2999                                           "to support mark action");
3000         if (!priv->sh->dv_mark_mask)
3001                 return rte_flow_error_set(error, ENOTSUP,
3002                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3003                                           "extended metadata register"
3004                                           " isn't available");
3005         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3006         if (ret < 0)
3007                 return ret;
3008         MLX5_ASSERT(ret > 0);
3009         if (!mark)
3010                 return rte_flow_error_set(error, EINVAL,
3011                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3012                                           "configuration cannot be null");
3013         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3014                 return rte_flow_error_set(error, EINVAL,
3015                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3016                                           &mark->id,
3017                                           "mark id exceeds the limit");
3018         if (action_flags & MLX5_FLOW_ACTION_FLAG)
3019                 return rte_flow_error_set(error, EINVAL,
3020                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3021                                           "can't flag and mark in same flow");
3022         if (action_flags & MLX5_FLOW_ACTION_MARK)
3023                 return rte_flow_error_set(error, EINVAL,
3024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025                                           "can't have 2 mark actions in same"
3026                                           " flow");
3027         return 0;
3028 }
3029
3030 /**
3031  * Validate SET_META action.
3032  *
3033  * @param[in] dev
3034  *   Pointer to the rte_eth_dev structure.
3035  * @param[in] action
3036  *   Pointer to the action structure.
3037  * @param[in] action_flags
3038  *   Holds the actions detected until now.
3039  * @param[in] attr
3040  *   Pointer to flow attributes
3041  * @param[out] error
3042  *   Pointer to error structure.
3043  *
3044  * @return
3045  *   0 on success, a negative errno value otherwise and rte_errno is set.
3046  */
3047 static int
3048 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3049                                  const struct rte_flow_action *action,
3050                                  uint64_t action_flags __rte_unused,
3051                                  const struct rte_flow_attr *attr,
3052                                  struct rte_flow_error *error)
3053 {
3054         const struct rte_flow_action_set_meta *conf;
3055         uint32_t nic_mask = UINT32_MAX;
3056         int reg;
3057
3058         if (!mlx5_flow_ext_mreg_supported(dev))
3059                 return rte_flow_error_set(error, ENOTSUP,
3060                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3061                                           "extended metadata register"
3062                                           " isn't supported");
3063         reg = flow_dv_get_metadata_reg(dev, attr, error);
3064         if (reg < 0)
3065                 return reg;
3066         if (reg == REG_NON)
3067                 return rte_flow_error_set(error, ENOTSUP,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3069                                           "unavalable extended metadata register");
3070         if (reg != REG_A && reg != REG_B) {
3071                 struct mlx5_priv *priv = dev->data->dev_private;
3072
3073                 nic_mask = priv->sh->dv_meta_mask;
3074         }
3075         if (!(action->conf))
3076                 return rte_flow_error_set(error, EINVAL,
3077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3078                                           "configuration cannot be null");
3079         conf = (const struct rte_flow_action_set_meta *)action->conf;
3080         if (!conf->mask)
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "zero mask doesn't have any effect");
3084         if (conf->mask & ~nic_mask)
3085                 return rte_flow_error_set(error, EINVAL,
3086                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3087                                           "meta data must be within reg C0");
3088         return 0;
3089 }
3090
3091 /**
3092  * Validate SET_TAG action.
3093  *
3094  * @param[in] dev
3095  *   Pointer to the rte_eth_dev structure.
3096  * @param[in] action
3097  *   Pointer to the action structure.
3098  * @param[in] action_flags
3099  *   Holds the actions detected until now.
3100  * @param[in] attr
3101  *   Pointer to flow attributes
3102  * @param[out] error
3103  *   Pointer to error structure.
3104  *
3105  * @return
3106  *   0 on success, a negative errno value otherwise and rte_errno is set.
3107  */
3108 static int
3109 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3110                                 const struct rte_flow_action *action,
3111                                 uint64_t action_flags,
3112                                 const struct rte_flow_attr *attr,
3113                                 struct rte_flow_error *error)
3114 {
3115         const struct rte_flow_action_set_tag *conf;
3116         const uint64_t terminal_action_flags =
3117                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3118                 MLX5_FLOW_ACTION_RSS;
3119         int ret;
3120
3121         if (!mlx5_flow_ext_mreg_supported(dev))
3122                 return rte_flow_error_set(error, ENOTSUP,
3123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3124                                           "extensive metadata register"
3125                                           " isn't supported");
3126         if (!(action->conf))
3127                 return rte_flow_error_set(error, EINVAL,
3128                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3129                                           "configuration cannot be null");
3130         conf = (const struct rte_flow_action_set_tag *)action->conf;
3131         if (!conf->mask)
3132                 return rte_flow_error_set(error, EINVAL,
3133                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3134                                           "zero mask doesn't have any effect");
3135         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3136         if (ret < 0)
3137                 return ret;
3138         if (!attr->transfer && attr->ingress &&
3139             (action_flags & terminal_action_flags))
3140                 return rte_flow_error_set(error, EINVAL,
3141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3142                                           "set_tag has no effect"
3143                                           " with terminal actions");
3144         return 0;
3145 }
3146
3147 /**
3148  * Validate count action.
3149  *
3150  * @param[in] dev
3151  *   Pointer to rte_eth_dev structure.
3152  * @param[in] action
3153  *   Pointer to the action structure.
3154  * @param[in] action_flags
3155  *   Holds the actions detected until now.
3156  * @param[out] error
3157  *   Pointer to error structure.
3158  *
3159  * @return
3160  *   0 on success, a negative errno value otherwise and rte_errno is set.
3161  */
3162 static int
3163 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3164                               const struct rte_flow_action *action,
3165                               uint64_t action_flags,
3166                               struct rte_flow_error *error)
3167 {
3168         struct mlx5_priv *priv = dev->data->dev_private;
3169         const struct rte_flow_action_count *count;
3170
3171         if (!priv->config.devx)
3172                 goto notsup_err;
3173         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3174                 return rte_flow_error_set(error, EINVAL,
3175                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3176                                           "duplicate count actions set");
3177         count = (const struct rte_flow_action_count *)action->conf;
3178         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3179             !priv->sh->flow_hit_aso_en)
3180                 return rte_flow_error_set(error, EINVAL,
3181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3182                                           "old age and shared count combination is not supported");
3183 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3184         return 0;
3185 #endif
3186 notsup_err:
3187         return rte_flow_error_set
3188                       (error, ENOTSUP,
3189                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3190                        NULL,
3191                        "count action not supported");
3192 }
3193
3194 /**
3195  * Validate the L2 encap action.
3196  *
3197  * @param[in] dev
3198  *   Pointer to the rte_eth_dev structure.
3199  * @param[in] action_flags
3200  *   Holds the actions detected until now.
3201  * @param[in] action
3202  *   Pointer to the action structure.
3203  * @param[in] attr
3204  *   Pointer to flow attributes.
3205  * @param[out] error
3206  *   Pointer to error structure.
3207  *
3208  * @return
3209  *   0 on success, a negative errno value otherwise and rte_errno is set.
3210  */
3211 static int
3212 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3213                                  uint64_t action_flags,
3214                                  const struct rte_flow_action *action,
3215                                  const struct rte_flow_attr *attr,
3216                                  struct rte_flow_error *error)
3217 {
3218         const struct mlx5_priv *priv = dev->data->dev_private;
3219
3220         if (!(action->conf))
3221                 return rte_flow_error_set(error, EINVAL,
3222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3223                                           "configuration cannot be null");
3224         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3225                 return rte_flow_error_set(error, EINVAL,
3226                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3227                                           "can only have a single encap action "
3228                                           "in a flow");
3229         if (!attr->transfer && priv->representor)
3230                 return rte_flow_error_set(error, ENOTSUP,
3231                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3232                                           "encap action for VF representor "
3233                                           "not supported on NIC table");
3234         return 0;
3235 }
3236
3237 /**
3238  * Validate a decap action.
3239  *
3240  * @param[in] dev
3241  *   Pointer to the rte_eth_dev structure.
3242  * @param[in] action_flags
3243  *   Holds the actions detected until now.
3244  * @param[in] action
3245  *   Pointer to the action structure.
3246  * @param[in] item_flags
3247  *   Holds the items detected.
3248  * @param[in] attr
3249  *   Pointer to flow attributes
3250  * @param[out] error
3251  *   Pointer to error structure.
3252  *
3253  * @return
3254  *   0 on success, a negative errno value otherwise and rte_errno is set.
3255  */
3256 static int
3257 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3258                               uint64_t action_flags,
3259                               const struct rte_flow_action *action,
3260                               const uint64_t item_flags,
3261                               const struct rte_flow_attr *attr,
3262                               struct rte_flow_error *error)
3263 {
3264         const struct mlx5_priv *priv = dev->data->dev_private;
3265
3266         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3267             !priv->config.decap_en)
3268                 return rte_flow_error_set(error, ENOTSUP,
3269                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3270                                           "decap is not enabled");
3271         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3272                 return rte_flow_error_set(error, ENOTSUP,
3273                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3274                                           action_flags &
3275                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3276                                           "have a single decap action" : "decap "
3277                                           "after encap is not supported");
3278         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3281                                           "can't have decap action after"
3282                                           " modify action");
3283         if (attr->egress)
3284                 return rte_flow_error_set(error, ENOTSUP,
3285                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3286                                           NULL,
3287                                           "decap action not supported for "
3288                                           "egress");
3289         if (!attr->transfer && priv->representor)
3290                 return rte_flow_error_set(error, ENOTSUP,
3291                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3292                                           "decap action for VF representor "
3293                                           "not supported on NIC table");
3294         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3295             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3296                 return rte_flow_error_set(error, ENOTSUP,
3297                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3298                                 "VXLAN item should be present for VXLAN decap");
3299         return 0;
3300 }
3301
3302 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3303
3304 /**
3305  * Validate the raw encap and decap actions.
3306  *
3307  * @param[in] dev
3308  *   Pointer to the rte_eth_dev structure.
3309  * @param[in] decap
3310  *   Pointer to the decap action.
3311  * @param[in] encap
3312  *   Pointer to the encap action.
3313  * @param[in] attr
3314  *   Pointer to flow attributes
3315  * @param[in/out] action_flags
3316  *   Holds the actions detected until now.
3317  * @param[out] actions_n
3318  *   pointer to the number of actions counter.
3319  * @param[in] action
3320  *   Pointer to the action structure.
3321  * @param[in] item_flags
3322  *   Holds the items detected.
3323  * @param[out] error
3324  *   Pointer to error structure.
3325  *
3326  * @return
3327  *   0 on success, a negative errno value otherwise and rte_errno is set.
3328  */
3329 static int
3330 flow_dv_validate_action_raw_encap_decap
3331         (struct rte_eth_dev *dev,
3332          const struct rte_flow_action_raw_decap *decap,
3333          const struct rte_flow_action_raw_encap *encap,
3334          const struct rte_flow_attr *attr, uint64_t *action_flags,
3335          int *actions_n, const struct rte_flow_action *action,
3336          uint64_t item_flags, struct rte_flow_error *error)
3337 {
3338         const struct mlx5_priv *priv = dev->data->dev_private;
3339         int ret;
3340
3341         if (encap && (!encap->size || !encap->data))
3342                 return rte_flow_error_set(error, EINVAL,
3343                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3344                                           "raw encap data cannot be empty");
3345         if (decap && encap) {
3346                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3347                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3348                         /* L3 encap. */
3349                         decap = NULL;
3350                 else if (encap->size <=
3351                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3352                            decap->size >
3353                            MLX5_ENCAPSULATION_DECISION_SIZE)
3354                         /* L3 decap. */
3355                         encap = NULL;
3356                 else if (encap->size >
3357                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3358                            decap->size >
3359                            MLX5_ENCAPSULATION_DECISION_SIZE)
3360                         /* 2 L2 actions: encap and decap. */
3361                         ;
3362                 else
3363                         return rte_flow_error_set(error,
3364                                 ENOTSUP,
3365                                 RTE_FLOW_ERROR_TYPE_ACTION,
3366                                 NULL, "unsupported too small "
3367                                 "raw decap and too small raw "
3368                                 "encap combination");
3369         }
3370         if (decap) {
3371                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3372                                                     item_flags, attr, error);
3373                 if (ret < 0)
3374                         return ret;
3375                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3376                 ++(*actions_n);
3377         }
3378         if (encap) {
3379                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3380                         return rte_flow_error_set(error, ENOTSUP,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "small raw encap size");
3384                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3385                         return rte_flow_error_set(error, EINVAL,
3386                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3387                                                   NULL,
3388                                                   "more than one encap action");
3389                 if (!attr->transfer && priv->representor)
3390                         return rte_flow_error_set
3391                                         (error, ENOTSUP,
3392                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3393                                          "encap action for VF representor "
3394                                          "not supported on NIC table");
3395                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3396                 ++(*actions_n);
3397         }
3398         return 0;
3399 }
3400
3401 /**
3402  * Match encap_decap resource.
3403  *
3404  * @param list
3405  *   Pointer to the hash list.
3406  * @param entry
3407  *   Pointer to exist resource entry object.
3408  * @param key
3409  *   Key of the new entry.
3410  * @param ctx_cb
3411  *   Pointer to new encap_decap resource.
3412  *
3413  * @return
3414  *   0 on matching, none-zero otherwise.
3415  */
3416 int
3417 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3418                              struct mlx5_hlist_entry *entry,
3419                              uint64_t key __rte_unused, void *cb_ctx)
3420 {
3421         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3422         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3423         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3424
3425         cache_resource = container_of(entry,
3426                                       struct mlx5_flow_dv_encap_decap_resource,
3427                                       entry);
3428         if (resource->reformat_type == cache_resource->reformat_type &&
3429             resource->ft_type == cache_resource->ft_type &&
3430             resource->flags == cache_resource->flags &&
3431             resource->size == cache_resource->size &&
3432             !memcmp((const void *)resource->buf,
3433                     (const void *)cache_resource->buf,
3434                     resource->size))
3435                 return 0;
3436         return -1;
3437 }
3438
3439 /**
3440  * Allocate encap_decap resource.
3441  *
3442  * @param list
3443  *   Pointer to the hash list.
3444  * @param entry
3445  *   Pointer to exist resource entry object.
3446  * @param ctx_cb
3447  *   Pointer to new encap_decap resource.
3448  *
3449  * @return
3450  *   0 on matching, none-zero otherwise.
3451  */
3452 struct mlx5_hlist_entry *
3453 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3454                               uint64_t key __rte_unused,
3455                               void *cb_ctx)
3456 {
3457         struct mlx5_dev_ctx_shared *sh = list->ctx;
3458         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3459         struct mlx5dv_dr_domain *domain;
3460         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3461         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3462         uint32_t idx;
3463         int ret;
3464
3465         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3466                 domain = sh->fdb_domain;
3467         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3468                 domain = sh->rx_domain;
3469         else
3470                 domain = sh->tx_domain;
3471         /* Register new encap/decap resource. */
3472         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3473                                        &idx);
3474         if (!cache_resource) {
3475                 rte_flow_error_set(ctx->error, ENOMEM,
3476                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3477                                    "cannot allocate resource memory");
3478                 return NULL;
3479         }
3480         *cache_resource = *resource;
3481         cache_resource->idx = idx;
3482         ret = mlx5_flow_os_create_flow_action_packet_reformat
3483                                         (sh->ctx, domain, cache_resource,
3484                                          &cache_resource->action);
3485         if (ret) {
3486                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3487                 rte_flow_error_set(ctx->error, ENOMEM,
3488                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3489                                    NULL, "cannot create action");
3490                 return NULL;
3491         }
3492
3493         return &cache_resource->entry;
3494 }
3495
3496 /**
3497  * Find existing encap/decap resource or create and register a new one.
3498  *
3499  * @param[in, out] dev
3500  *   Pointer to rte_eth_dev structure.
3501  * @param[in, out] resource
3502  *   Pointer to encap/decap resource.
3503  * @parm[in, out] dev_flow
3504  *   Pointer to the dev_flow.
3505  * @param[out] error
3506  *   pointer to error structure.
3507  *
3508  * @return
3509  *   0 on success otherwise -errno and errno is set.
3510  */
3511 static int
3512 flow_dv_encap_decap_resource_register
3513                         (struct rte_eth_dev *dev,
3514                          struct mlx5_flow_dv_encap_decap_resource *resource,
3515                          struct mlx5_flow *dev_flow,
3516                          struct rte_flow_error *error)
3517 {
3518         struct mlx5_priv *priv = dev->data->dev_private;
3519         struct mlx5_dev_ctx_shared *sh = priv->sh;
3520         struct mlx5_hlist_entry *entry;
3521         union {
3522                 struct {
3523                         uint32_t ft_type:8;
3524                         uint32_t refmt_type:8;
3525                         /*
3526                          * Header reformat actions can be shared between
3527                          * non-root tables. One bit to indicate non-root
3528                          * table or not.
3529                          */
3530                         uint32_t is_root:1;
3531                         uint32_t reserve:15;
3532                 };
3533                 uint32_t v32;
3534         } encap_decap_key = {
3535                 {
3536                         .ft_type = resource->ft_type,
3537                         .refmt_type = resource->reformat_type,
3538                         .is_root = !!dev_flow->dv.group,
3539                         .reserve = 0,
3540                 }
3541         };
3542         struct mlx5_flow_cb_ctx ctx = {
3543                 .error = error,
3544                 .data = resource,
3545         };
3546         uint64_t key64;
3547
3548         resource->flags = dev_flow->dv.group ? 0 : 1;
3549         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3550                                  sizeof(encap_decap_key.v32), 0);
3551         if (resource->reformat_type !=
3552             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3553             resource->size)
3554                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3555         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3556         if (!entry)
3557                 return -rte_errno;
3558         resource = container_of(entry, typeof(*resource), entry);
3559         dev_flow->dv.encap_decap = resource;
3560         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3561         return 0;
3562 }
3563
3564 /**
3565  * Find existing table jump resource or create and register a new one.
3566  *
3567  * @param[in, out] dev
3568  *   Pointer to rte_eth_dev structure.
3569  * @param[in, out] tbl
3570  *   Pointer to flow table resource.
3571  * @parm[in, out] dev_flow
3572  *   Pointer to the dev_flow.
3573  * @param[out] error
3574  *   pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success otherwise -errno and errno is set.
3578  */
3579 static int
3580 flow_dv_jump_tbl_resource_register
3581                         (struct rte_eth_dev *dev __rte_unused,
3582                          struct mlx5_flow_tbl_resource *tbl,
3583                          struct mlx5_flow *dev_flow,
3584                          struct rte_flow_error *error __rte_unused)
3585 {
3586         struct mlx5_flow_tbl_data_entry *tbl_data =
3587                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3588
3589         MLX5_ASSERT(tbl);
3590         MLX5_ASSERT(tbl_data->jump.action);
3591         dev_flow->handle->rix_jump = tbl_data->idx;
3592         dev_flow->dv.jump = &tbl_data->jump;
3593         return 0;
3594 }
3595
3596 int
3597 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3598                          struct mlx5_cache_entry *entry, void *cb_ctx)
3599 {
3600         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3601         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3602         struct mlx5_flow_dv_port_id_action_resource *res =
3603                         container_of(entry, typeof(*res), entry);
3604
3605         return ref->port_id != res->port_id;
3606 }
3607
3608 struct mlx5_cache_entry *
3609 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3610                           struct mlx5_cache_entry *entry __rte_unused,
3611                           void *cb_ctx)
3612 {
3613         struct mlx5_dev_ctx_shared *sh = list->ctx;
3614         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3615         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3616         struct mlx5_flow_dv_port_id_action_resource *cache;
3617         uint32_t idx;
3618         int ret;
3619
3620         /* Register new port id action resource. */
3621         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3622         if (!cache) {
3623                 rte_flow_error_set(ctx->error, ENOMEM,
3624                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3625                                    "cannot allocate port_id action cache memory");
3626                 return NULL;
3627         }
3628         *cache = *ref;
3629         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3630                                                         ref->port_id,
3631                                                         &cache->action);
3632         if (ret) {
3633                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3634                 rte_flow_error_set(ctx->error, ENOMEM,
3635                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3636                                    "cannot create action");
3637                 return NULL;
3638         }
3639         cache->idx = idx;
3640         return &cache->entry;
3641 }
3642
3643 /**
3644  * Find existing table port ID resource or create and register a new one.
3645  *
3646  * @param[in, out] dev
3647  *   Pointer to rte_eth_dev structure.
3648  * @param[in, out] resource
3649  *   Pointer to port ID action resource.
3650  * @parm[in, out] dev_flow
3651  *   Pointer to the dev_flow.
3652  * @param[out] error
3653  *   pointer to error structure.
3654  *
3655  * @return
3656  *   0 on success otherwise -errno and errno is set.
3657  */
3658 static int
3659 flow_dv_port_id_action_resource_register
3660                         (struct rte_eth_dev *dev,
3661                          struct mlx5_flow_dv_port_id_action_resource *resource,
3662                          struct mlx5_flow *dev_flow,
3663                          struct rte_flow_error *error)
3664 {
3665         struct mlx5_priv *priv = dev->data->dev_private;
3666         struct mlx5_cache_entry *entry;
3667         struct mlx5_flow_dv_port_id_action_resource *cache;
3668         struct mlx5_flow_cb_ctx ctx = {
3669                 .error = error,
3670                 .data = resource,
3671         };
3672
3673         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3674         if (!entry)
3675                 return -rte_errno;
3676         cache = container_of(entry, typeof(*cache), entry);
3677         dev_flow->dv.port_id_action = cache;
3678         dev_flow->handle->rix_port_id_action = cache->idx;
3679         return 0;
3680 }
3681
3682 int
3683 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3684                          struct mlx5_cache_entry *entry, void *cb_ctx)
3685 {
3686         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3687         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3688         struct mlx5_flow_dv_push_vlan_action_resource *res =
3689                         container_of(entry, typeof(*res), entry);
3690
3691         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3692 }
3693
3694 struct mlx5_cache_entry *
3695 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3696                           struct mlx5_cache_entry *entry __rte_unused,
3697                           void *cb_ctx)
3698 {
3699         struct mlx5_dev_ctx_shared *sh = list->ctx;
3700         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3701         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3702         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3703         struct mlx5dv_dr_domain *domain;
3704         uint32_t idx;
3705         int ret;
3706
3707         /* Register new port id action resource. */
3708         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3709         if (!cache) {
3710                 rte_flow_error_set(ctx->error, ENOMEM,
3711                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3712                                    "cannot allocate push_vlan action cache memory");
3713                 return NULL;
3714         }
3715         *cache = *ref;
3716         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3717                 domain = sh->fdb_domain;
3718         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3719                 domain = sh->rx_domain;
3720         else
3721                 domain = sh->tx_domain;
3722         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3723                                                         &cache->action);
3724         if (ret) {
3725                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3726                 rte_flow_error_set(ctx->error, ENOMEM,
3727                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3728                                    "cannot create push vlan action");
3729                 return NULL;
3730         }
3731         cache->idx = idx;
3732         return &cache->entry;
3733 }
3734
3735 /**
3736  * Find existing push vlan resource or create and register a new one.
3737  *
3738  * @param [in, out] dev
3739  *   Pointer to rte_eth_dev structure.
3740  * @param[in, out] resource
3741  *   Pointer to port ID action resource.
3742  * @parm[in, out] dev_flow
3743  *   Pointer to the dev_flow.
3744  * @param[out] error
3745  *   pointer to error structure.
3746  *
3747  * @return
3748  *   0 on success otherwise -errno and errno is set.
3749  */
3750 static int
3751 flow_dv_push_vlan_action_resource_register
3752                        (struct rte_eth_dev *dev,
3753                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3754                         struct mlx5_flow *dev_flow,
3755                         struct rte_flow_error *error)
3756 {
3757         struct mlx5_priv *priv = dev->data->dev_private;
3758         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3759         struct mlx5_cache_entry *entry;
3760         struct mlx5_flow_cb_ctx ctx = {
3761                 .error = error,
3762                 .data = resource,
3763         };
3764
3765         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3766         if (!entry)
3767                 return -rte_errno;
3768         cache = container_of(entry, typeof(*cache), entry);
3769
3770         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3771         dev_flow->dv.push_vlan_res = cache;
3772         return 0;
3773 }
3774
3775 /**
3776  * Get the size of specific rte_flow_item_type hdr size
3777  *
3778  * @param[in] item_type
3779  *   Tested rte_flow_item_type.
3780  *
3781  * @return
3782  *   sizeof struct item_type, 0 if void or irrelevant.
3783  */
3784 static size_t
3785 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3786 {
3787         size_t retval;
3788
3789         switch (item_type) {
3790         case RTE_FLOW_ITEM_TYPE_ETH:
3791                 retval = sizeof(struct rte_ether_hdr);
3792                 break;
3793         case RTE_FLOW_ITEM_TYPE_VLAN:
3794                 retval = sizeof(struct rte_vlan_hdr);
3795                 break;
3796         case RTE_FLOW_ITEM_TYPE_IPV4:
3797                 retval = sizeof(struct rte_ipv4_hdr);
3798                 break;
3799         case RTE_FLOW_ITEM_TYPE_IPV6:
3800                 retval = sizeof(struct rte_ipv6_hdr);
3801                 break;
3802         case RTE_FLOW_ITEM_TYPE_UDP:
3803                 retval = sizeof(struct rte_udp_hdr);
3804                 break;
3805         case RTE_FLOW_ITEM_TYPE_TCP:
3806                 retval = sizeof(struct rte_tcp_hdr);
3807                 break;
3808         case RTE_FLOW_ITEM_TYPE_VXLAN:
3809         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3810                 retval = sizeof(struct rte_vxlan_hdr);
3811                 break;
3812         case RTE_FLOW_ITEM_TYPE_GRE:
3813         case RTE_FLOW_ITEM_TYPE_NVGRE:
3814                 retval = sizeof(struct rte_gre_hdr);
3815                 break;
3816         case RTE_FLOW_ITEM_TYPE_MPLS:
3817                 retval = sizeof(struct rte_mpls_hdr);
3818                 break;
3819         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3820         default:
3821                 retval = 0;
3822                 break;
3823         }
3824         return retval;
3825 }
3826
3827 #define MLX5_ENCAP_IPV4_VERSION         0x40
3828 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3829 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3830 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3831 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3832 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3833 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3834
3835 /**
3836  * Convert the encap action data from list of rte_flow_item to raw buffer
3837  *
3838  * @param[in] items
3839  *   Pointer to rte_flow_item objects list.
3840  * @param[out] buf
3841  *   Pointer to the output buffer.
3842  * @param[out] size
3843  *   Pointer to the output buffer size.
3844  * @param[out] error
3845  *   Pointer to the error structure.
3846  *
3847  * @return
3848  *   0 on success, a negative errno value otherwise and rte_errno is set.
3849  */
3850 static int
3851 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3852                            size_t *size, struct rte_flow_error *error)
3853 {
3854         struct rte_ether_hdr *eth = NULL;
3855         struct rte_vlan_hdr *vlan = NULL;
3856         struct rte_ipv4_hdr *ipv4 = NULL;
3857         struct rte_ipv6_hdr *ipv6 = NULL;
3858         struct rte_udp_hdr *udp = NULL;
3859         struct rte_vxlan_hdr *vxlan = NULL;
3860         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3861         struct rte_gre_hdr *gre = NULL;
3862         size_t len;
3863         size_t temp_size = 0;
3864
3865         if (!items)
3866                 return rte_flow_error_set(error, EINVAL,
3867                                           RTE_FLOW_ERROR_TYPE_ACTION,
3868                                           NULL, "invalid empty data");
3869         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3870                 len = flow_dv_get_item_hdr_len(items->type);
3871                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3872                         return rte_flow_error_set(error, EINVAL,
3873                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                   (void *)items->type,
3875                                                   "items total size is too big"
3876                                                   " for encap action");
3877                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3878                 switch (items->type) {
3879                 case RTE_FLOW_ITEM_TYPE_ETH:
3880                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3881                         break;
3882                 case RTE_FLOW_ITEM_TYPE_VLAN:
3883                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3884                         if (!eth)
3885                                 return rte_flow_error_set(error, EINVAL,
3886                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3887                                                 (void *)items->type,
3888                                                 "eth header not found");
3889                         if (!eth->ether_type)
3890                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3891                         break;
3892                 case RTE_FLOW_ITEM_TYPE_IPV4:
3893                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3894                         if (!vlan && !eth)
3895                                 return rte_flow_error_set(error, EINVAL,
3896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3897                                                 (void *)items->type,
3898                                                 "neither eth nor vlan"
3899                                                 " header found");
3900                         if (vlan && !vlan->eth_proto)
3901                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902                         else if (eth && !eth->ether_type)
3903                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3904                         if (!ipv4->version_ihl)
3905                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3906                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3907                         if (!ipv4->time_to_live)
3908                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3909                         break;
3910                 case RTE_FLOW_ITEM_TYPE_IPV6:
3911                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3912                         if (!vlan && !eth)
3913                                 return rte_flow_error_set(error, EINVAL,
3914                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3915                                                 (void *)items->type,
3916                                                 "neither eth nor vlan"
3917                                                 " header found");
3918                         if (vlan && !vlan->eth_proto)
3919                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920                         else if (eth && !eth->ether_type)
3921                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3922                         if (!ipv6->vtc_flow)
3923                                 ipv6->vtc_flow =
3924                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3925                         if (!ipv6->hop_limits)
3926                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3927                         break;
3928                 case RTE_FLOW_ITEM_TYPE_UDP:
3929                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3930                         if (!ipv4 && !ipv6)
3931                                 return rte_flow_error_set(error, EINVAL,
3932                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                 (void *)items->type,
3934                                                 "ip header not found");
3935                         if (ipv4 && !ipv4->next_proto_id)
3936                                 ipv4->next_proto_id = IPPROTO_UDP;
3937                         else if (ipv6 && !ipv6->proto)
3938                                 ipv6->proto = IPPROTO_UDP;
3939                         break;
3940                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3941                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3942                         if (!udp)
3943                                 return rte_flow_error_set(error, EINVAL,
3944                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3945                                                 (void *)items->type,
3946                                                 "udp header not found");
3947                         if (!udp->dst_port)
3948                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3949                         if (!vxlan->vx_flags)
3950                                 vxlan->vx_flags =
3951                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3952                         break;
3953                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3954                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3955                         if (!udp)
3956                                 return rte_flow_error_set(error, EINVAL,
3957                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3958                                                 (void *)items->type,
3959                                                 "udp header not found");
3960                         if (!vxlan_gpe->proto)
3961                                 return rte_flow_error_set(error, EINVAL,
3962                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3963                                                 (void *)items->type,
3964                                                 "next protocol not found");
3965                         if (!udp->dst_port)
3966                                 udp->dst_port =
3967                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3968                         if (!vxlan_gpe->vx_flags)
3969                                 vxlan_gpe->vx_flags =
3970                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3971                         break;
3972                 case RTE_FLOW_ITEM_TYPE_GRE:
3973                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3974                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3975                         if (!gre->proto)
3976                                 return rte_flow_error_set(error, EINVAL,
3977                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3978                                                 (void *)items->type,
3979                                                 "next protocol not found");
3980                         if (!ipv4 && !ipv6)
3981                                 return rte_flow_error_set(error, EINVAL,
3982                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3983                                                 (void *)items->type,
3984                                                 "ip header not found");
3985                         if (ipv4 && !ipv4->next_proto_id)
3986                                 ipv4->next_proto_id = IPPROTO_GRE;
3987                         else if (ipv6 && !ipv6->proto)
3988                                 ipv6->proto = IPPROTO_GRE;
3989                         break;
3990                 case RTE_FLOW_ITEM_TYPE_VOID:
3991                         break;
3992                 default:
3993                         return rte_flow_error_set(error, EINVAL,
3994                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3995                                                   (void *)items->type,
3996                                                   "unsupported item type");
3997                         break;
3998                 }
3999                 temp_size += len;
4000         }
4001         *size = temp_size;
4002         return 0;
4003 }
4004
4005 static int
4006 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4007 {
4008         struct rte_ether_hdr *eth = NULL;
4009         struct rte_vlan_hdr *vlan = NULL;
4010         struct rte_ipv6_hdr *ipv6 = NULL;
4011         struct rte_udp_hdr *udp = NULL;
4012         char *next_hdr;
4013         uint16_t proto;
4014
4015         eth = (struct rte_ether_hdr *)data;
4016         next_hdr = (char *)(eth + 1);
4017         proto = RTE_BE16(eth->ether_type);
4018
4019         /* VLAN skipping */
4020         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4021                 vlan = (struct rte_vlan_hdr *)next_hdr;
4022                 proto = RTE_BE16(vlan->eth_proto);
4023                 next_hdr += sizeof(struct rte_vlan_hdr);
4024         }
4025
4026         /* HW calculates IPv4 csum. no need to proceed */
4027         if (proto == RTE_ETHER_TYPE_IPV4)
4028                 return 0;
4029
4030         /* non IPv4/IPv6 header. not supported */
4031         if (proto != RTE_ETHER_TYPE_IPV6) {
4032                 return rte_flow_error_set(error, ENOTSUP,
4033                                           RTE_FLOW_ERROR_TYPE_ACTION,
4034                                           NULL, "Cannot offload non IPv4/IPv6");
4035         }
4036
4037         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4038
4039         /* ignore non UDP */
4040         if (ipv6->proto != IPPROTO_UDP)
4041                 return 0;
4042
4043         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4044         udp->dgram_cksum = 0;
4045
4046         return 0;
4047 }
4048
4049 /**
4050  * Convert L2 encap action to DV specification.
4051  *
4052  * @param[in] dev
4053  *   Pointer to rte_eth_dev structure.
4054  * @param[in] action
4055  *   Pointer to action structure.
4056  * @param[in, out] dev_flow
4057  *   Pointer to the mlx5_flow.
4058  * @param[in] transfer
4059  *   Mark if the flow is E-Switch flow.
4060  * @param[out] error
4061  *   Pointer to the error structure.
4062  *
4063  * @return
4064  *   0 on success, a negative errno value otherwise and rte_errno is set.
4065  */
4066 static int
4067 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4068                                const struct rte_flow_action *action,
4069                                struct mlx5_flow *dev_flow,
4070                                uint8_t transfer,
4071                                struct rte_flow_error *error)
4072 {
4073         const struct rte_flow_item *encap_data;
4074         const struct rte_flow_action_raw_encap *raw_encap_data;
4075         struct mlx5_flow_dv_encap_decap_resource res = {
4076                 .reformat_type =
4077                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4078                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4079                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4080         };
4081
4082         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4083                 raw_encap_data =
4084                         (const struct rte_flow_action_raw_encap *)action->conf;
4085                 res.size = raw_encap_data->size;
4086                 memcpy(res.buf, raw_encap_data->data, res.size);
4087         } else {
4088                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4089                         encap_data =
4090                                 ((const struct rte_flow_action_vxlan_encap *)
4091                                                 action->conf)->definition;
4092                 else
4093                         encap_data =
4094                                 ((const struct rte_flow_action_nvgre_encap *)
4095                                                 action->conf)->definition;
4096                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4097                                                &res.size, error))
4098                         return -rte_errno;
4099         }
4100         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4101                 return -rte_errno;
4102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4103                 return rte_flow_error_set(error, EINVAL,
4104                                           RTE_FLOW_ERROR_TYPE_ACTION,
4105                                           NULL, "can't create L2 encap action");
4106         return 0;
4107 }
4108
4109 /**
4110  * Convert L2 decap action to DV specification.
4111  *
4112  * @param[in] dev
4113  *   Pointer to rte_eth_dev structure.
4114  * @param[in, out] dev_flow
4115  *   Pointer to the mlx5_flow.
4116  * @param[in] transfer
4117  *   Mark if the flow is E-Switch flow.
4118  * @param[out] error
4119  *   Pointer to the error structure.
4120  *
4121  * @return
4122  *   0 on success, a negative errno value otherwise and rte_errno is set.
4123  */
4124 static int
4125 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4126                                struct mlx5_flow *dev_flow,
4127                                uint8_t transfer,
4128                                struct rte_flow_error *error)
4129 {
4130         struct mlx5_flow_dv_encap_decap_resource res = {
4131                 .size = 0,
4132                 .reformat_type =
4133                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4134                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4135                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4136         };
4137
4138         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4139                 return rte_flow_error_set(error, EINVAL,
4140                                           RTE_FLOW_ERROR_TYPE_ACTION,
4141                                           NULL, "can't create L2 decap action");
4142         return 0;
4143 }
4144
4145 /**
4146  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4147  *
4148  * @param[in] dev
4149  *   Pointer to rte_eth_dev structure.
4150  * @param[in] action
4151  *   Pointer to action structure.
4152  * @param[in, out] dev_flow
4153  *   Pointer to the mlx5_flow.
4154  * @param[in] attr
4155  *   Pointer to the flow attributes.
4156  * @param[out] error
4157  *   Pointer to the error structure.
4158  *
4159  * @return
4160  *   0 on success, a negative errno value otherwise and rte_errno is set.
4161  */
4162 static int
4163 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4164                                 const struct rte_flow_action *action,
4165                                 struct mlx5_flow *dev_flow,
4166                                 const struct rte_flow_attr *attr,
4167                                 struct rte_flow_error *error)
4168 {
4169         const struct rte_flow_action_raw_encap *encap_data;
4170         struct mlx5_flow_dv_encap_decap_resource res;
4171
4172         memset(&res, 0, sizeof(res));
4173         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4174         res.size = encap_data->size;
4175         memcpy(res.buf, encap_data->data, res.size);
4176         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4177                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4178                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4179         if (attr->transfer)
4180                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4181         else
4182                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4183                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4184         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4185                 return rte_flow_error_set(error, EINVAL,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION,
4187                                           NULL, "can't create encap action");
4188         return 0;
4189 }
4190
4191 /**
4192  * Create action push VLAN.
4193  *
4194  * @param[in] dev
4195  *   Pointer to rte_eth_dev structure.
4196  * @param[in] attr
4197  *   Pointer to the flow attributes.
4198  * @param[in] vlan
4199  *   Pointer to the vlan to push to the Ethernet header.
4200  * @param[in, out] dev_flow
4201  *   Pointer to the mlx5_flow.
4202  * @param[out] error
4203  *   Pointer to the error structure.
4204  *
4205  * @return
4206  *   0 on success, a negative errno value otherwise and rte_errno is set.
4207  */
4208 static int
4209 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4210                                 const struct rte_flow_attr *attr,
4211                                 const struct rte_vlan_hdr *vlan,
4212                                 struct mlx5_flow *dev_flow,
4213                                 struct rte_flow_error *error)
4214 {
4215         struct mlx5_flow_dv_push_vlan_action_resource res;
4216
4217         memset(&res, 0, sizeof(res));
4218         res.vlan_tag =
4219                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4220                                  vlan->vlan_tci);
4221         if (attr->transfer)
4222                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4223         else
4224                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4225                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4226         return flow_dv_push_vlan_action_resource_register
4227                                             (dev, &res, dev_flow, error);
4228 }
4229
4230 /**
4231  * Validate the modify-header actions.
4232  *
4233  * @param[in] action_flags
4234  *   Holds the actions detected until now.
4235  * @param[in] action
4236  *   Pointer to the modify action.
4237  * @param[out] error
4238  *   Pointer to error structure.
4239  *
4240  * @return
4241  *   0 on success, a negative errno value otherwise and rte_errno is set.
4242  */
4243 static int
4244 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4245                                    const struct rte_flow_action *action,
4246                                    struct rte_flow_error *error)
4247 {
4248         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4249                 return rte_flow_error_set(error, EINVAL,
4250                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4251                                           NULL, "action configuration not set");
4252         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4253                 return rte_flow_error_set(error, EINVAL,
4254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4255                                           "can't have encap action before"
4256                                           " modify action");
4257         return 0;
4258 }
4259
4260 /**
4261  * Validate the modify-header MAC address actions.
4262  *
4263  * @param[in] action_flags
4264  *   Holds the actions detected until now.
4265  * @param[in] action
4266  *   Pointer to the modify action.
4267  * @param[in] item_flags
4268  *   Holds the items detected.
4269  * @param[out] error
4270  *   Pointer to error structure.
4271  *
4272  * @return
4273  *   0 on success, a negative errno value otherwise and rte_errno is set.
4274  */
4275 static int
4276 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4277                                    const struct rte_flow_action *action,
4278                                    const uint64_t item_flags,
4279                                    struct rte_flow_error *error)
4280 {
4281         int ret = 0;
4282
4283         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4284         if (!ret) {
4285                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4286                         return rte_flow_error_set(error, EINVAL,
4287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4288                                                   NULL,
4289                                                   "no L2 item in pattern");
4290         }
4291         return ret;
4292 }
4293
4294 /**
4295  * Validate the modify-header IPv4 address actions.
4296  *
4297  * @param[in] action_flags
4298  *   Holds the actions detected until now.
4299  * @param[in] action
4300  *   Pointer to the modify action.
4301  * @param[in] item_flags
4302  *   Holds the items detected.
4303  * @param[out] error
4304  *   Pointer to error structure.
4305  *
4306  * @return
4307  *   0 on success, a negative errno value otherwise and rte_errno is set.
4308  */
4309 static int
4310 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4311                                     const struct rte_flow_action *action,
4312                                     const uint64_t item_flags,
4313                                     struct rte_flow_error *error)
4314 {
4315         int ret = 0;
4316         uint64_t layer;
4317
4318         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4319         if (!ret) {
4320                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4321                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4322                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4323                 if (!(item_flags & layer))
4324                         return rte_flow_error_set(error, EINVAL,
4325                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4326                                                   NULL,
4327                                                   "no ipv4 item in pattern");
4328         }
4329         return ret;
4330 }
4331
4332 /**
4333  * Validate the modify-header IPv6 address actions.
4334  *
4335  * @param[in] action_flags
4336  *   Holds the actions detected until now.
4337  * @param[in] action
4338  *   Pointer to the modify action.
4339  * @param[in] item_flags
4340  *   Holds the items detected.
4341  * @param[out] error
4342  *   Pointer to error structure.
4343  *
4344  * @return
4345  *   0 on success, a negative errno value otherwise and rte_errno is set.
4346  */
4347 static int
4348 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4349                                     const struct rte_flow_action *action,
4350                                     const uint64_t item_flags,
4351                                     struct rte_flow_error *error)
4352 {
4353         int ret = 0;
4354         uint64_t layer;
4355
4356         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4357         if (!ret) {
4358                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4359                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4360                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4361                 if (!(item_flags & layer))
4362                         return rte_flow_error_set(error, EINVAL,
4363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4364                                                   NULL,
4365                                                   "no ipv6 item in pattern");
4366         }
4367         return ret;
4368 }
4369
4370 /**
4371  * Validate the modify-header TP actions.
4372  *
4373  * @param[in] action_flags
4374  *   Holds the actions detected until now.
4375  * @param[in] action
4376  *   Pointer to the modify action.
4377  * @param[in] item_flags
4378  *   Holds the items detected.
4379  * @param[out] error
4380  *   Pointer to error structure.
4381  *
4382  * @return
4383  *   0 on success, a negative errno value otherwise and rte_errno is set.
4384  */
4385 static int
4386 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4387                                   const struct rte_flow_action *action,
4388                                   const uint64_t item_flags,
4389                                   struct rte_flow_error *error)
4390 {
4391         int ret = 0;
4392         uint64_t layer;
4393
4394         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4395         if (!ret) {
4396                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4397                                  MLX5_FLOW_LAYER_INNER_L4 :
4398                                  MLX5_FLOW_LAYER_OUTER_L4;
4399                 if (!(item_flags & layer))
4400                         return rte_flow_error_set(error, EINVAL,
4401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4402                                                   NULL, "no transport layer "
4403                                                   "in pattern");
4404         }
4405         return ret;
4406 }
4407
4408 /**
4409  * Validate the modify-header actions of increment/decrement
4410  * TCP Sequence-number.
4411  *
4412  * @param[in] action_flags
4413  *   Holds the actions detected until now.
4414  * @param[in] action
4415  *   Pointer to the modify action.
4416  * @param[in] item_flags
4417  *   Holds the items detected.
4418  * @param[out] error
4419  *   Pointer to error structure.
4420  *
4421  * @return
4422  *   0 on success, a negative errno value otherwise and rte_errno is set.
4423  */
4424 static int
4425 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4426                                        const struct rte_flow_action *action,
4427                                        const uint64_t item_flags,
4428                                        struct rte_flow_error *error)
4429 {
4430         int ret = 0;
4431         uint64_t layer;
4432
4433         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4434         if (!ret) {
4435                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4436                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4437                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4438                 if (!(item_flags & layer))
4439                         return rte_flow_error_set(error, EINVAL,
4440                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4441                                                   NULL, "no TCP item in"
4442                                                   " pattern");
4443                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4444                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4445                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4446                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4447                         return rte_flow_error_set(error, EINVAL,
4448                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4449                                                   NULL,
4450                                                   "cannot decrease and increase"
4451                                                   " TCP sequence number"
4452                                                   " at the same time");
4453         }
4454         return ret;
4455 }
4456
4457 /**
4458  * Validate the modify-header actions of increment/decrement
4459  * TCP Acknowledgment number.
4460  *
4461  * @param[in] action_flags
4462  *   Holds the actions detected until now.
4463  * @param[in] action
4464  *   Pointer to the modify action.
4465  * @param[in] item_flags
4466  *   Holds the items detected.
4467  * @param[out] error
4468  *   Pointer to error structure.
4469  *
4470  * @return
4471  *   0 on success, a negative errno value otherwise and rte_errno is set.
4472  */
4473 static int
4474 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4475                                        const struct rte_flow_action *action,
4476                                        const uint64_t item_flags,
4477                                        struct rte_flow_error *error)
4478 {
4479         int ret = 0;
4480         uint64_t layer;
4481
4482         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4483         if (!ret) {
4484                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4485                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4486                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4487                 if (!(item_flags & layer))
4488                         return rte_flow_error_set(error, EINVAL,
4489                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4490                                                   NULL, "no TCP item in"
4491                                                   " pattern");
4492                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4493                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4494                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4495                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4496                         return rte_flow_error_set(error, EINVAL,
4497                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4498                                                   NULL,
4499                                                   "cannot decrease and increase"
4500                                                   " TCP acknowledgment number"
4501                                                   " at the same time");
4502         }
4503         return ret;
4504 }
4505
4506 /**
4507  * Validate the modify-header TTL actions.
4508  *
4509  * @param[in] action_flags
4510  *   Holds the actions detected until now.
4511  * @param[in] action
4512  *   Pointer to the modify action.
4513  * @param[in] item_flags
4514  *   Holds the items detected.
4515  * @param[out] error
4516  *   Pointer to error structure.
4517  *
4518  * @return
4519  *   0 on success, a negative errno value otherwise and rte_errno is set.
4520  */
4521 static int
4522 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4523                                    const struct rte_flow_action *action,
4524                                    const uint64_t item_flags,
4525                                    struct rte_flow_error *error)
4526 {
4527         int ret = 0;
4528         uint64_t layer;
4529
4530         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4531         if (!ret) {
4532                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4533                                  MLX5_FLOW_LAYER_INNER_L3 :
4534                                  MLX5_FLOW_LAYER_OUTER_L3;
4535                 if (!(item_flags & layer))
4536                         return rte_flow_error_set(error, EINVAL,
4537                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4538                                                   NULL,
4539                                                   "no IP protocol in pattern");
4540         }
4541         return ret;
4542 }
4543
4544 /**
4545  * Validate the generic modify field actions.
4546  * @param[in] dev
4547  *   Pointer to the rte_eth_dev structure.
4548  * @param[in] action_flags
4549  *   Holds the actions detected until now.
4550  * @param[in] action
4551  *   Pointer to the modify action.
4552  * @param[in] attr
4553  *   Pointer to the flow attributes.
4554  * @param[out] error
4555  *   Pointer to error structure.
4556  *
4557  * @return
4558  *   Number of header fields to modify (0 or more) on success,
4559  *   a negative errno value otherwise and rte_errno is set.
4560  */
4561 static int
4562 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4563                                    const uint64_t action_flags,
4564                                    const struct rte_flow_action *action,
4565                                    const struct rte_flow_attr *attr,
4566                                    struct rte_flow_error *error)
4567 {
4568         int ret = 0;
4569         struct mlx5_priv *priv = dev->data->dev_private;
4570         struct mlx5_dev_config *config = &priv->config;
4571         const struct rte_flow_action_modify_field *action_modify_field =
4572                 action->conf;
4573         uint32_t dst_width =
4574                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4575         uint32_t src_width =
4576                 mlx5_flow_item_field_width(action_modify_field->src.field);
4577
4578         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4579         if (ret)
4580                 return ret;
4581
4582         if (action_modify_field->width == 0)
4583                 return rte_flow_error_set(error, EINVAL,
4584                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4585                                 "no bits are requested to be modified");
4586         else if (action_modify_field->width > dst_width ||
4587                  action_modify_field->width > src_width)
4588                 return rte_flow_error_set(error, EINVAL,
4589                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4590                                 "cannot modify more bits than"
4591                                 " the width of a field");
4592         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594                 if ((action_modify_field->dst.offset +
4595                      action_modify_field->width > dst_width) ||
4596                     (action_modify_field->dst.offset % 32))
4597                         return rte_flow_error_set(error, EINVAL,
4598                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4599                                         "destination offset is too big"
4600                                         " or not aligned to 4 bytes");
4601                 if (action_modify_field->dst.level &&
4602                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4603                         return rte_flow_error_set(error, ENOTSUP,
4604                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4605                                         "inner header fields modification"
4606                                         " is not supported");
4607         }
4608         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4609             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4610                 if (!attr->transfer && !attr->group)
4611                         return rte_flow_error_set(error, ENOTSUP,
4612                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4613                                         "modify field action is not"
4614                                         " supported for group 0");
4615                 if ((action_modify_field->src.offset +
4616                      action_modify_field->width > src_width) ||
4617                     (action_modify_field->src.offset % 32))
4618                         return rte_flow_error_set(error, EINVAL,
4619                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4620                                         "source offset is too big"
4621                                         " or not aligned to 4 bytes");
4622                 if (action_modify_field->src.level &&
4623                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4624                         return rte_flow_error_set(error, ENOTSUP,
4625                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4626                                         "inner header fields modification"
4627                                         " is not supported");
4628         }
4629         if (action_modify_field->dst.field ==
4630             action_modify_field->src.field)
4631                 return rte_flow_error_set(error, EINVAL,
4632                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633                                 "source and destination fields"
4634                                 " cannot be the same");
4635         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4636             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4637                 return rte_flow_error_set(error, EINVAL,
4638                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639                                 "immediate value or a pointer to it"
4640                                 " cannot be used as a destination");
4641         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4642             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4643                 return rte_flow_error_set(error, ENOTSUP,
4644                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645                                 "modifications of an arbitrary"
4646                                 " place in a packet is not supported");
4647         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4648             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4649                 return rte_flow_error_set(error, ENOTSUP,
4650                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651                                 "modifications of the 802.1Q Tag"
4652                                 " Identifier is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4655                 return rte_flow_error_set(error, ENOTSUP,
4656                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657                                 "modifications of the VXLAN Network"
4658                                 " Identifier is not supported");
4659         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4660             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4661                 return rte_flow_error_set(error, ENOTSUP,
4662                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4663                                 "modifications of the GENEVE Network"
4664                                 " Identifier is not supported");
4665         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4666             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4667             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4668             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4669                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4670                     !mlx5_flow_ext_mreg_supported(dev))
4671                         return rte_flow_error_set(error, ENOTSUP,
4672                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4673                                         "cannot modify mark or metadata without"
4674                                         " extended metadata register support");
4675         }
4676         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4677                 return rte_flow_error_set(error, ENOTSUP,
4678                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4679                                 "add and sub operations"
4680                                 " are not supported");
4681         return (action_modify_field->width / 32) +
4682                !!(action_modify_field->width % 32);
4683 }
4684
4685 /**
4686  * Validate jump action.
4687  *
4688  * @param[in] action
4689  *   Pointer to the jump action.
4690  * @param[in] action_flags
4691  *   Holds the actions detected until now.
4692  * @param[in] attributes
4693  *   Pointer to flow attributes
4694  * @param[in] external
4695  *   Action belongs to flow rule created by request external to PMD.
4696  * @param[out] error
4697  *   Pointer to error structure.
4698  *
4699  * @return
4700  *   0 on success, a negative errno value otherwise and rte_errno is set.
4701  */
4702 static int
4703 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4704                              const struct mlx5_flow_tunnel *tunnel,
4705                              const struct rte_flow_action *action,
4706                              uint64_t action_flags,
4707                              const struct rte_flow_attr *attributes,
4708                              bool external, struct rte_flow_error *error)
4709 {
4710         uint32_t target_group, table;
4711         int ret = 0;
4712         struct flow_grp_info grp_info = {
4713                 .external = !!external,
4714                 .transfer = !!attributes->transfer,
4715                 .fdb_def_rule = 1,
4716                 .std_tbl_fix = 0
4717         };
4718         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4719                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4720                 return rte_flow_error_set(error, EINVAL,
4721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4722                                           "can't have 2 fate actions in"
4723                                           " same flow");
4724         if (action_flags & MLX5_FLOW_ACTION_METER)
4725                 return rte_flow_error_set(error, ENOTSUP,
4726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4727                                           "jump with meter not support");
4728         if (!action->conf)
4729                 return rte_flow_error_set(error, EINVAL,
4730                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4731                                           NULL, "action configuration not set");
4732         target_group =
4733                 ((const struct rte_flow_action_jump *)action->conf)->group;
4734         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4735                                        &grp_info, error);
4736         if (ret)
4737                 return ret;
4738         if (attributes->group == target_group &&
4739             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4740                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4741                 return rte_flow_error_set(error, EINVAL,
4742                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4743                                           "target group must be other than"
4744                                           " the current flow group");
4745         return 0;
4746 }
4747
4748 /*
4749  * Validate the port_id action.
4750  *
4751  * @param[in] dev
4752  *   Pointer to rte_eth_dev structure.
4753  * @param[in] action_flags
4754  *   Bit-fields that holds the actions detected until now.
4755  * @param[in] action
4756  *   Port_id RTE action structure.
4757  * @param[in] attr
4758  *   Attributes of flow that includes this action.
4759  * @param[out] error
4760  *   Pointer to error structure.
4761  *
4762  * @return
4763  *   0 on success, a negative errno value otherwise and rte_errno is set.
4764  */
4765 static int
4766 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4767                                 uint64_t action_flags,
4768                                 const struct rte_flow_action *action,
4769                                 const struct rte_flow_attr *attr,
4770                                 struct rte_flow_error *error)
4771 {
4772         const struct rte_flow_action_port_id *port_id;
4773         struct mlx5_priv *act_priv;
4774         struct mlx5_priv *dev_priv;
4775         uint16_t port;
4776
4777         if (!attr->transfer)
4778                 return rte_flow_error_set(error, ENOTSUP,
4779                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4780                                           NULL,
4781                                           "port id action is valid in transfer"
4782                                           " mode only");
4783         if (!action || !action->conf)
4784                 return rte_flow_error_set(error, ENOTSUP,
4785                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4786                                           NULL,
4787                                           "port id action parameters must be"
4788                                           " specified");
4789         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4790                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4791                 return rte_flow_error_set(error, EINVAL,
4792                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4793                                           "can have only one fate actions in"
4794                                           " a flow");
4795         dev_priv = mlx5_dev_to_eswitch_info(dev);
4796         if (!dev_priv)
4797                 return rte_flow_error_set(error, rte_errno,
4798                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4799                                           NULL,
4800                                           "failed to obtain E-Switch info");
4801         port_id = action->conf;
4802         port = port_id->original ? dev->data->port_id : port_id->id;
4803         act_priv = mlx5_port_to_eswitch_info(port, false);
4804         if (!act_priv)
4805                 return rte_flow_error_set
4806                                 (error, rte_errno,
4807                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4808                                  "failed to obtain E-Switch port id for port");
4809         if (act_priv->domain_id != dev_priv->domain_id)
4810                 return rte_flow_error_set
4811                                 (error, EINVAL,
4812                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4813                                  "port does not belong to"
4814                                  " E-Switch being configured");
4815         return 0;
4816 }
4817
4818 /**
4819  * Get the maximum number of modify header actions.
4820  *
4821  * @param dev
4822  *   Pointer to rte_eth_dev structure.
4823  * @param flags
4824  *   Flags bits to check if root level.
4825  *
4826  * @return
4827  *   Max number of modify header actions device can support.
4828  */
4829 static inline unsigned int
4830 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4831                               uint64_t flags)
4832 {
4833         /*
4834          * There's no way to directly query the max capacity from FW.
4835          * The maximal value on root table should be assumed to be supported.
4836          */
4837         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4838                 return MLX5_MAX_MODIFY_NUM;
4839         else
4840                 return MLX5_ROOT_TBL_MODIFY_NUM;
4841 }
4842
4843 /**
4844  * Validate the meter action.
4845  *
4846  * @param[in] dev
4847  *   Pointer to rte_eth_dev structure.
4848  * @param[in] action_flags
4849  *   Bit-fields that holds the actions detected until now.
4850  * @param[in] action
4851  *   Pointer to the meter action.
4852  * @param[in] attr
4853  *   Attributes of flow that includes this action.
4854  * @param[out] error
4855  *   Pointer to error structure.
4856  *
4857  * @return
4858  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4859  */
4860 static int
4861 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4862                                 uint64_t action_flags,
4863                                 const struct rte_flow_action *action,
4864                                 const struct rte_flow_attr *attr,
4865                                 struct rte_flow_error *error)
4866 {
4867         struct mlx5_priv *priv = dev->data->dev_private;
4868         const struct rte_flow_action_meter *am = action->conf;
4869         struct mlx5_flow_meter_info *fm;
4870
4871         if (!am)
4872                 return rte_flow_error_set(error, EINVAL,
4873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874                                           "meter action conf is NULL");
4875
4876         if (action_flags & MLX5_FLOW_ACTION_METER)
4877                 return rte_flow_error_set(error, ENOTSUP,
4878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4879                                           "meter chaining not support");
4880         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4881                 return rte_flow_error_set(error, ENOTSUP,
4882                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4883                                           "meter with jump not support");
4884         if (!priv->mtr_en)
4885                 return rte_flow_error_set(error, ENOTSUP,
4886                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4887                                           NULL,
4888                                           "meter action not supported");
4889         fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4890         if (!fm)
4891                 return rte_flow_error_set(error, EINVAL,
4892                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4893                                           "Meter not found");
4894         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4895               (!fm->ingress && !attr->ingress && attr->egress) ||
4896               (!fm->egress && !attr->egress && attr->ingress))))
4897                 return rte_flow_error_set(error, EINVAL,
4898                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4899                                           "Flow attributes are either invalid "
4900                                           "or have a conflict with current "
4901                                           "meter attributes");
4902         return 0;
4903 }
4904
4905 /**
4906  * Validate the age action.
4907  *
4908  * @param[in] action_flags
4909  *   Holds the actions detected until now.
4910  * @param[in] action
4911  *   Pointer to the age action.
4912  * @param[in] dev
4913  *   Pointer to the Ethernet device structure.
4914  * @param[out] error
4915  *   Pointer to error structure.
4916  *
4917  * @return
4918  *   0 on success, a negative errno value otherwise and rte_errno is set.
4919  */
4920 static int
4921 flow_dv_validate_action_age(uint64_t action_flags,
4922                             const struct rte_flow_action *action,
4923                             struct rte_eth_dev *dev,
4924                             struct rte_flow_error *error)
4925 {
4926         struct mlx5_priv *priv = dev->data->dev_private;
4927         const struct rte_flow_action_age *age = action->conf;
4928
4929         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4930             !priv->sh->aso_age_mng))
4931                 return rte_flow_error_set(error, ENOTSUP,
4932                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4933                                           NULL,
4934                                           "age action not supported");
4935         if (!(action->conf))
4936                 return rte_flow_error_set(error, EINVAL,
4937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4938                                           "configuration cannot be null");
4939         if (!(age->timeout))
4940                 return rte_flow_error_set(error, EINVAL,
4941                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4942                                           "invalid timeout value 0");
4943         if (action_flags & MLX5_FLOW_ACTION_AGE)
4944                 return rte_flow_error_set(error, EINVAL,
4945                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4946                                           "duplicate age actions set");
4947         return 0;
4948 }
4949
4950 /**
4951  * Validate the modify-header IPv4 DSCP actions.
4952  *
4953  * @param[in] action_flags
4954  *   Holds the actions detected until now.
4955  * @param[in] action
4956  *   Pointer to the modify action.
4957  * @param[in] item_flags
4958  *   Holds the items detected.
4959  * @param[out] error
4960  *   Pointer to error structure.
4961  *
4962  * @return
4963  *   0 on success, a negative errno value otherwise and rte_errno is set.
4964  */
4965 static int
4966 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4967                                          const struct rte_flow_action *action,
4968                                          const uint64_t item_flags,
4969                                          struct rte_flow_error *error)
4970 {
4971         int ret = 0;
4972
4973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4974         if (!ret) {
4975                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4976                         return rte_flow_error_set(error, EINVAL,
4977                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4978                                                   NULL,
4979                                                   "no ipv4 item in pattern");
4980         }
4981         return ret;
4982 }
4983
4984 /**
4985  * Validate the modify-header IPv6 DSCP actions.
4986  *
4987  * @param[in] action_flags
4988  *   Holds the actions detected until now.
4989  * @param[in] action
4990  *   Pointer to the modify action.
4991  * @param[in] item_flags
4992  *   Holds the items detected.
4993  * @param[out] error
4994  *   Pointer to error structure.
4995  *
4996  * @return
4997  *   0 on success, a negative errno value otherwise and rte_errno is set.
4998  */
4999 static int
5000 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5001                                          const struct rte_flow_action *action,
5002                                          const uint64_t item_flags,
5003                                          struct rte_flow_error *error)
5004 {
5005         int ret = 0;
5006
5007         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5008         if (!ret) {
5009                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5010                         return rte_flow_error_set(error, EINVAL,
5011                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5012                                                   NULL,
5013                                                   "no ipv6 item in pattern");
5014         }
5015         return ret;
5016 }
5017
5018 /**
5019  * Match modify-header resource.
5020  *
5021  * @param list
5022  *   Pointer to the hash list.
5023  * @param entry
5024  *   Pointer to exist resource entry object.
5025  * @param key
5026  *   Key of the new entry.
5027  * @param ctx
5028  *   Pointer to new modify-header resource.
5029  *
5030  * @return
5031  *   0 on matching, non-zero otherwise.
5032  */
5033 int
5034 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5035                         struct mlx5_hlist_entry *entry,
5036                         uint64_t key __rte_unused, void *cb_ctx)
5037 {
5038         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5039         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5040         struct mlx5_flow_dv_modify_hdr_resource *resource =
5041                         container_of(entry, typeof(*resource), entry);
5042         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5043
5044         key_len += ref->actions_num * sizeof(ref->actions[0]);
5045         return ref->actions_num != resource->actions_num ||
5046                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5047 }
5048
5049 struct mlx5_hlist_entry *
5050 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5051                          void *cb_ctx)
5052 {
5053         struct mlx5_dev_ctx_shared *sh = list->ctx;
5054         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5055         struct mlx5dv_dr_domain *ns;
5056         struct mlx5_flow_dv_modify_hdr_resource *entry;
5057         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5058         int ret;
5059         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5060         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5061
5062         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5063                             SOCKET_ID_ANY);
5064         if (!entry) {
5065                 rte_flow_error_set(ctx->error, ENOMEM,
5066                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5067                                    "cannot allocate resource memory");
5068                 return NULL;
5069         }
5070         rte_memcpy(&entry->ft_type,
5071                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5072                    key_len + data_len);
5073         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5074                 ns = sh->fdb_domain;
5075         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5076                 ns = sh->tx_domain;
5077         else
5078                 ns = sh->rx_domain;
5079         ret = mlx5_flow_os_create_flow_action_modify_header
5080                                         (sh->ctx, ns, entry,
5081                                          data_len, &entry->action);
5082         if (ret) {
5083                 mlx5_free(entry);
5084                 rte_flow_error_set(ctx->error, ENOMEM,
5085                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5086                                    NULL, "cannot create modification action");
5087                 return NULL;
5088         }
5089         return &entry->entry;
5090 }
5091
5092 /**
5093  * Validate the sample action.
5094  *
5095  * @param[in, out] action_flags
5096  *   Holds the actions detected until now.
5097  * @param[in] action
5098  *   Pointer to the sample action.
5099  * @param[in] dev
5100  *   Pointer to the Ethernet device structure.
5101  * @param[in] attr
5102  *   Attributes of flow that includes this action.
5103  * @param[in] item_flags
5104  *   Holds the items detected.
5105  * @param[in] rss
5106  *   Pointer to the RSS action.
5107  * @param[out] sample_rss
5108  *   Pointer to the RSS action in sample action list.
5109  * @param[out] count
5110  *   Pointer to the COUNT action in sample action list.
5111  * @param[out] fdb_mirror_limit
5112  *   Pointer to the FDB mirror limitation flag.
5113  * @param[out] error
5114  *   Pointer to error structure.
5115  *
5116  * @return
5117  *   0 on success, a negative errno value otherwise and rte_errno is set.
5118  */
5119 static int
5120 flow_dv_validate_action_sample(uint64_t *action_flags,
5121                                const struct rte_flow_action *action,
5122                                struct rte_eth_dev *dev,
5123                                const struct rte_flow_attr *attr,
5124                                uint64_t item_flags,
5125                                const struct rte_flow_action_rss *rss,
5126                                const struct rte_flow_action_rss **sample_rss,
5127                                const struct rte_flow_action_count **count,
5128                                int *fdb_mirror_limit,
5129                                struct rte_flow_error *error)
5130 {
5131         struct mlx5_priv *priv = dev->data->dev_private;
5132         struct mlx5_dev_config *dev_conf = &priv->config;
5133         const struct rte_flow_action_sample *sample = action->conf;
5134         const struct rte_flow_action *act;
5135         uint64_t sub_action_flags = 0;
5136         uint16_t queue_index = 0xFFFF;
5137         int actions_n = 0;
5138         int ret;
5139
5140         if (!sample)
5141                 return rte_flow_error_set(error, EINVAL,
5142                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5143                                           "configuration cannot be NULL");
5144         if (sample->ratio == 0)
5145                 return rte_flow_error_set(error, EINVAL,
5146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5147                                           "ratio value starts from 1");
5148         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5149                 return rte_flow_error_set(error, ENOTSUP,
5150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5151                                           NULL,
5152                                           "sample action not supported");
5153         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5154                 return rte_flow_error_set(error, EINVAL,
5155                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5156                                           "Multiple sample actions not "
5157                                           "supported");
5158         if (*action_flags & MLX5_FLOW_ACTION_METER)
5159                 return rte_flow_error_set(error, EINVAL,
5160                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5161                                           "wrong action order, meter should "
5162                                           "be after sample action");
5163         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5164                 return rte_flow_error_set(error, EINVAL,
5165                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5166                                           "wrong action order, jump should "
5167                                           "be after sample action");
5168         act = sample->actions;
5169         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5170                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5171                         return rte_flow_error_set(error, ENOTSUP,
5172                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5173                                                   act, "too many actions");
5174                 switch (act->type) {
5175                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5176                         ret = mlx5_flow_validate_action_queue(act,
5177                                                               sub_action_flags,
5178                                                               dev,
5179                                                               attr, error);
5180                         if (ret < 0)
5181                                 return ret;
5182                         queue_index = ((const struct rte_flow_action_queue *)
5183                                                         (act->conf))->index;
5184                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5185                         ++actions_n;
5186                         break;
5187                 case RTE_FLOW_ACTION_TYPE_RSS:
5188                         *sample_rss = act->conf;
5189                         ret = mlx5_flow_validate_action_rss(act,
5190                                                             sub_action_flags,
5191                                                             dev, attr,
5192                                                             item_flags,
5193                                                             error);
5194                         if (ret < 0)
5195                                 return ret;
5196                         if (rss && *sample_rss &&
5197                             ((*sample_rss)->level != rss->level ||
5198                             (*sample_rss)->types != rss->types))
5199                                 return rte_flow_error_set(error, ENOTSUP,
5200                                         RTE_FLOW_ERROR_TYPE_ACTION,
5201                                         NULL,
5202                                         "Can't use the different RSS types "
5203                                         "or level in the same flow");
5204                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5205                                 queue_index = (*sample_rss)->queue[0];
5206                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5207                         ++actions_n;
5208                         break;
5209                 case RTE_FLOW_ACTION_TYPE_MARK:
5210                         ret = flow_dv_validate_action_mark(dev, act,
5211                                                            sub_action_flags,
5212                                                            attr, error);
5213                         if (ret < 0)
5214                                 return ret;
5215                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5216                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5217                                                 MLX5_FLOW_ACTION_MARK_EXT;
5218                         else
5219                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_COUNT:
5223                         ret = flow_dv_validate_action_count
5224                                 (dev, act,
5225                                  *action_flags | sub_action_flags,
5226                                  error);
5227                         if (ret < 0)
5228                                 return ret;
5229                         *count = act->conf;
5230                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5231                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5232                         ++actions_n;
5233                         break;
5234                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5235                         ret = flow_dv_validate_action_port_id(dev,
5236                                                               sub_action_flags,
5237                                                               act,
5238                                                               attr,
5239                                                               error);
5240                         if (ret)
5241                                 return ret;
5242                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5243                         ++actions_n;
5244                         break;
5245                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5246                         ret = flow_dv_validate_action_raw_encap_decap
5247                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5248                                  &actions_n, action, item_flags, error);
5249                         if (ret < 0)
5250                                 return ret;
5251                         ++actions_n;
5252                         break;
5253                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5254                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5255                         ret = flow_dv_validate_action_l2_encap(dev,
5256                                                                sub_action_flags,
5257                                                                act, attr,
5258                                                                error);
5259                         if (ret < 0)
5260                                 return ret;
5261                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5262                         ++actions_n;
5263                         break;
5264                 default:
5265                         return rte_flow_error_set(error, ENOTSUP,
5266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5267                                                   NULL,
5268                                                   "Doesn't support optional "
5269                                                   "action");
5270                 }
5271         }
5272         if (attr->ingress && !attr->transfer) {
5273                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5274                                           MLX5_FLOW_ACTION_RSS)))
5275                         return rte_flow_error_set(error, EINVAL,
5276                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5277                                                   NULL,
5278                                                   "Ingress must has a dest "
5279                                                   "QUEUE for Sample");
5280         } else if (attr->egress && !attr->transfer) {
5281                 return rte_flow_error_set(error, ENOTSUP,
5282                                           RTE_FLOW_ERROR_TYPE_ACTION,
5283                                           NULL,
5284                                           "Sample Only support Ingress "
5285                                           "or E-Switch");
5286         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5287                 MLX5_ASSERT(attr->transfer);
5288                 if (sample->ratio > 1)
5289                         return rte_flow_error_set(error, ENOTSUP,
5290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5291                                                   NULL,
5292                                                   "E-Switch doesn't support "
5293                                                   "any optional action "
5294                                                   "for sampling");
5295                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5296                         return rte_flow_error_set(error, ENOTSUP,
5297                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5298                                                   NULL,
5299                                                   "unsupported action QUEUE");
5300                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5301                         return rte_flow_error_set(error, ENOTSUP,
5302                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5303                                                   NULL,
5304                                                   "unsupported action QUEUE");
5305                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5306                         return rte_flow_error_set(error, EINVAL,
5307                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5308                                                   NULL,
5309                                                   "E-Switch must has a dest "
5310                                                   "port for mirroring");
5311                 if (!priv->config.hca_attr.reg_c_preserve &&
5312                      priv->representor_id != -1)
5313                         *fdb_mirror_limit = 1;
5314         }
5315         /* Continue validation for Xcap actions.*/
5316         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5317             (queue_index == 0xFFFF ||
5318              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5319                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5320                      MLX5_FLOW_XCAP_ACTIONS)
5321                         return rte_flow_error_set(error, ENOTSUP,
5322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5323                                                   NULL, "encap and decap "
5324                                                   "combination aren't "
5325                                                   "supported");
5326                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5327                                                         MLX5_FLOW_ACTION_ENCAP))
5328                         return rte_flow_error_set(error, ENOTSUP,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   NULL, "encap is not supported"
5331                                                   " for ingress traffic");
5332         }
5333         return 0;
5334 }
5335
5336 /**
5337  * Find existing modify-header resource or create and register a new one.
5338  *
5339  * @param dev[in, out]
5340  *   Pointer to rte_eth_dev structure.
5341  * @param[in, out] resource
5342  *   Pointer to modify-header resource.
5343  * @parm[in, out] dev_flow
5344  *   Pointer to the dev_flow.
5345  * @param[out] error
5346  *   pointer to error structure.
5347  *
5348  * @return
5349  *   0 on success otherwise -errno and errno is set.
5350  */
5351 static int
5352 flow_dv_modify_hdr_resource_register
5353                         (struct rte_eth_dev *dev,
5354                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5355                          struct mlx5_flow *dev_flow,
5356                          struct rte_flow_error *error)
5357 {
5358         struct mlx5_priv *priv = dev->data->dev_private;
5359         struct mlx5_dev_ctx_shared *sh = priv->sh;
5360         uint32_t key_len = sizeof(*resource) -
5361                            offsetof(typeof(*resource), ft_type) +
5362                            resource->actions_num * sizeof(resource->actions[0]);
5363         struct mlx5_hlist_entry *entry;
5364         struct mlx5_flow_cb_ctx ctx = {
5365                 .error = error,
5366                 .data = resource,
5367         };
5368         uint64_t key64;
5369
5370         resource->flags = dev_flow->dv.group ? 0 :
5371                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5372         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5373                                     resource->flags))
5374                 return rte_flow_error_set(error, EOVERFLOW,
5375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5376                                           "too many modify header items");
5377         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5378         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5379         if (!entry)
5380                 return -rte_errno;
5381         resource = container_of(entry, typeof(*resource), entry);
5382         dev_flow->handle->dvh.modify_hdr = resource;
5383         return 0;
5384 }
5385
5386 /**
5387  * Get DV flow counter by index.
5388  *
5389  * @param[in] dev
5390  *   Pointer to the Ethernet device structure.
5391  * @param[in] idx
5392  *   mlx5 flow counter index in the container.
5393  * @param[out] ppool
5394  *   mlx5 flow counter pool in the container,
5395  *
5396  * @return
5397  *   Pointer to the counter, NULL otherwise.
5398  */
5399 static struct mlx5_flow_counter *
5400 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5401                            uint32_t idx,
5402                            struct mlx5_flow_counter_pool **ppool)
5403 {
5404         struct mlx5_priv *priv = dev->data->dev_private;
5405         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5406         struct mlx5_flow_counter_pool *pool;
5407
5408         /* Decrease to original index and clear shared bit. */
5409         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5410         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5411         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5412         MLX5_ASSERT(pool);
5413         if (ppool)
5414                 *ppool = pool;
5415         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5416 }
5417
5418 /**
5419  * Check the devx counter belongs to the pool.
5420  *
5421  * @param[in] pool
5422  *   Pointer to the counter pool.
5423  * @param[in] id
5424  *   The counter devx ID.
5425  *
5426  * @return
5427  *   True if counter belongs to the pool, false otherwise.
5428  */
5429 static bool
5430 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5431 {
5432         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5433                    MLX5_COUNTERS_PER_POOL;
5434
5435         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5436                 return true;
5437         return false;
5438 }
5439
5440 /**
5441  * Get a pool by devx counter ID.
5442  *
5443  * @param[in] cmng
5444  *   Pointer to the counter management.
5445  * @param[in] id
5446  *   The counter devx ID.
5447  *
5448  * @return
5449  *   The counter pool pointer if exists, NULL otherwise,
5450  */
5451 static struct mlx5_flow_counter_pool *
5452 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5453 {
5454         uint32_t i;
5455         struct mlx5_flow_counter_pool *pool = NULL;
5456
5457         rte_spinlock_lock(&cmng->pool_update_sl);
5458         /* Check last used pool. */
5459         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5460             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5461                 pool = cmng->pools[cmng->last_pool_idx];
5462                 goto out;
5463         }
5464         /* ID out of range means no suitable pool in the container. */
5465         if (id > cmng->max_id || id < cmng->min_id)
5466                 goto out;
5467         /*
5468          * Find the pool from the end of the container, since mostly counter
5469          * ID is sequence increasing, and the last pool should be the needed
5470          * one.
5471          */
5472         i = cmng->n_valid;
5473         while (i--) {
5474                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5475
5476                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5477                         pool = pool_tmp;
5478                         break;
5479                 }
5480         }
5481 out:
5482         rte_spinlock_unlock(&cmng->pool_update_sl);
5483         return pool;
5484 }
5485
5486 /**
5487  * Resize a counter container.
5488  *
5489  * @param[in] dev
5490  *   Pointer to the Ethernet device structure.
5491  *
5492  * @return
5493  *   0 on success, otherwise negative errno value and rte_errno is set.
5494  */
5495 static int
5496 flow_dv_container_resize(struct rte_eth_dev *dev)
5497 {
5498         struct mlx5_priv *priv = dev->data->dev_private;
5499         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5500         void *old_pools = cmng->pools;
5501         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5502         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5503         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5504
5505         if (!pools) {
5506                 rte_errno = ENOMEM;
5507                 return -ENOMEM;
5508         }
5509         if (old_pools)
5510                 memcpy(pools, old_pools, cmng->n *
5511                                        sizeof(struct mlx5_flow_counter_pool *));
5512         cmng->n = resize;
5513         cmng->pools = pools;
5514         if (old_pools)
5515                 mlx5_free(old_pools);
5516         return 0;
5517 }
5518
5519 /**
5520  * Query a devx flow counter.
5521  *
5522  * @param[in] dev
5523  *   Pointer to the Ethernet device structure.
5524  * @param[in] cnt
5525  *   Index to the flow counter.
5526  * @param[out] pkts
5527  *   The statistics value of packets.
5528  * @param[out] bytes
5529  *   The statistics value of bytes.
5530  *
5531  * @return
5532  *   0 on success, otherwise a negative errno value and rte_errno is set.
5533  */
5534 static inline int
5535 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5536                      uint64_t *bytes)
5537 {
5538         struct mlx5_priv *priv = dev->data->dev_private;
5539         struct mlx5_flow_counter_pool *pool = NULL;
5540         struct mlx5_flow_counter *cnt;
5541         int offset;
5542
5543         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5544         MLX5_ASSERT(pool);
5545         if (priv->sh->cmng.counter_fallback)
5546                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5547                                         0, pkts, bytes, 0, NULL, NULL, 0);
5548         rte_spinlock_lock(&pool->sl);
5549         if (!pool->raw) {
5550                 *pkts = 0;
5551                 *bytes = 0;
5552         } else {
5553                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5554                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5555                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5556         }
5557         rte_spinlock_unlock(&pool->sl);
5558         return 0;
5559 }
5560
5561 /**
5562  * Create and initialize a new counter pool.
5563  *
5564  * @param[in] dev
5565  *   Pointer to the Ethernet device structure.
5566  * @param[out] dcs
5567  *   The devX counter handle.
5568  * @param[in] age
5569  *   Whether the pool is for counter that was allocated for aging.
5570  * @param[in/out] cont_cur
5571  *   Pointer to the container pointer, it will be update in pool resize.
5572  *
5573  * @return
5574  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5575  */
5576 static struct mlx5_flow_counter_pool *
5577 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5578                     uint32_t age)
5579 {
5580         struct mlx5_priv *priv = dev->data->dev_private;
5581         struct mlx5_flow_counter_pool *pool;
5582         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5583         bool fallback = priv->sh->cmng.counter_fallback;
5584         uint32_t size = sizeof(*pool);
5585
5586         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5587         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5588         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5589         if (!pool) {
5590                 rte_errno = ENOMEM;
5591                 return NULL;
5592         }
5593         pool->raw = NULL;
5594         pool->is_aged = !!age;
5595         pool->query_gen = 0;
5596         pool->min_dcs = dcs;
5597         rte_spinlock_init(&pool->sl);
5598         rte_spinlock_init(&pool->csl);
5599         TAILQ_INIT(&pool->counters[0]);
5600         TAILQ_INIT(&pool->counters[1]);
5601         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5602         rte_spinlock_lock(&cmng->pool_update_sl);
5603         pool->index = cmng->n_valid;
5604         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5605                 mlx5_free(pool);
5606                 rte_spinlock_unlock(&cmng->pool_update_sl);
5607                 return NULL;
5608         }
5609         cmng->pools[pool->index] = pool;
5610         cmng->n_valid++;
5611         if (unlikely(fallback)) {
5612                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5613
5614                 if (base < cmng->min_id)
5615                         cmng->min_id = base;
5616                 if (base > cmng->max_id)
5617                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5618                 cmng->last_pool_idx = pool->index;
5619         }
5620         rte_spinlock_unlock(&cmng->pool_update_sl);
5621         return pool;
5622 }
5623
5624 /**
5625  * Prepare a new counter and/or a new counter pool.
5626  *
5627  * @param[in] dev
5628  *   Pointer to the Ethernet device structure.
5629  * @param[out] cnt_free
5630  *   Where to put the pointer of a new counter.
5631  * @param[in] age
5632  *   Whether the pool is for counter that was allocated for aging.
5633  *
5634  * @return
5635  *   The counter pool pointer and @p cnt_free is set on success,
5636  *   NULL otherwise and rte_errno is set.
5637  */
5638 static struct mlx5_flow_counter_pool *
5639 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5640                              struct mlx5_flow_counter **cnt_free,
5641                              uint32_t age)
5642 {
5643         struct mlx5_priv *priv = dev->data->dev_private;
5644         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5645         struct mlx5_flow_counter_pool *pool;
5646         struct mlx5_counters tmp_tq;
5647         struct mlx5_devx_obj *dcs = NULL;
5648         struct mlx5_flow_counter *cnt;
5649         enum mlx5_counter_type cnt_type =
5650                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5651         bool fallback = priv->sh->cmng.counter_fallback;
5652         uint32_t i;
5653
5654         if (fallback) {
5655                 /* bulk_bitmap must be 0 for single counter allocation. */
5656                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5657                 if (!dcs)
5658                         return NULL;
5659                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5660                 if (!pool) {
5661                         pool = flow_dv_pool_create(dev, dcs, age);
5662                         if (!pool) {
5663                                 mlx5_devx_cmd_destroy(dcs);
5664                                 return NULL;
5665                         }
5666                 }
5667                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5668                 cnt = MLX5_POOL_GET_CNT(pool, i);
5669                 cnt->pool = pool;
5670                 cnt->dcs_when_free = dcs;
5671                 *cnt_free = cnt;
5672                 return pool;
5673         }
5674         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5675         if (!dcs) {
5676                 rte_errno = ENODATA;
5677                 return NULL;
5678         }
5679         pool = flow_dv_pool_create(dev, dcs, age);
5680         if (!pool) {
5681                 mlx5_devx_cmd_destroy(dcs);
5682                 return NULL;
5683         }
5684         TAILQ_INIT(&tmp_tq);
5685         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5686                 cnt = MLX5_POOL_GET_CNT(pool, i);
5687                 cnt->pool = pool;
5688                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5689         }
5690         rte_spinlock_lock(&cmng->csl[cnt_type]);
5691         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5692         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5693         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5694         (*cnt_free)->pool = pool;
5695         return pool;
5696 }
5697
5698 /**
5699  * Allocate a flow counter.
5700  *
5701  * @param[in] dev
5702  *   Pointer to the Ethernet device structure.
5703  * @param[in] age
5704  *   Whether the counter was allocated for aging.
5705  *
5706  * @return
5707  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5708  */
5709 static uint32_t
5710 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5711 {
5712         struct mlx5_priv *priv = dev->data->dev_private;
5713         struct mlx5_flow_counter_pool *pool = NULL;
5714         struct mlx5_flow_counter *cnt_free = NULL;
5715         bool fallback = priv->sh->cmng.counter_fallback;
5716         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5717         enum mlx5_counter_type cnt_type =
5718                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5719         uint32_t cnt_idx;
5720
5721         if (!priv->config.devx) {
5722                 rte_errno = ENOTSUP;
5723                 return 0;
5724         }
5725         /* Get free counters from container. */
5726         rte_spinlock_lock(&cmng->csl[cnt_type]);
5727         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5728         if (cnt_free)
5729                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5730         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5731         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5732                 goto err;
5733         pool = cnt_free->pool;
5734         if (fallback)
5735                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5736         /* Create a DV counter action only in the first time usage. */
5737         if (!cnt_free->action) {
5738                 uint16_t offset;
5739                 struct mlx5_devx_obj *dcs;
5740                 int ret;
5741
5742                 if (!fallback) {
5743                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5744                         dcs = pool->min_dcs;
5745                 } else {
5746                         offset = 0;
5747                         dcs = cnt_free->dcs_when_free;
5748                 }
5749                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5750                                                             &cnt_free->action);
5751                 if (ret) {
5752                         rte_errno = errno;
5753                         goto err;
5754                 }
5755         }
5756         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5757                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5758         /* Update the counter reset values. */
5759         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5760                                  &cnt_free->bytes))
5761                 goto err;
5762         if (!fallback && !priv->sh->cmng.query_thread_on)
5763                 /* Start the asynchronous batch query by the host thread. */
5764                 mlx5_set_query_alarm(priv->sh);
5765         return cnt_idx;
5766 err:
5767         if (cnt_free) {
5768                 cnt_free->pool = pool;
5769                 if (fallback)
5770                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5771                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5772                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5773                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5774         }
5775         return 0;
5776 }
5777
5778 /**
5779  * Allocate a shared flow counter.
5780  *
5781  * @param[in] ctx
5782  *   Pointer to the shared counter configuration.
5783  * @param[in] data
5784  *   Pointer to save the allocated counter index.
5785  *
5786  * @return
5787  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5788  */
5789
5790 static int32_t
5791 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5792 {
5793         struct mlx5_shared_counter_conf *conf = ctx;
5794         struct rte_eth_dev *dev = conf->dev;
5795         struct mlx5_flow_counter *cnt;
5796
5797         data->dword = flow_dv_counter_alloc(dev, 0);
5798         data->dword |= MLX5_CNT_SHARED_OFFSET;
5799         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5800         cnt->shared_info.id = conf->id;
5801         return 0;
5802 }
5803
5804 /**
5805  * Get a shared flow counter.
5806  *
5807  * @param[in] dev
5808  *   Pointer to the Ethernet device structure.
5809  * @param[in] id
5810  *   Counter identifier.
5811  *
5812  * @return
5813  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5814  */
5815 static uint32_t
5816 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5817 {
5818         struct mlx5_priv *priv = dev->data->dev_private;
5819         struct mlx5_shared_counter_conf conf = {
5820                 .dev = dev,
5821                 .id = id,
5822         };
5823         union mlx5_l3t_data data = {
5824                 .dword = 0,
5825         };
5826
5827         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5828                                flow_dv_counter_alloc_shared_cb, &conf);
5829         return data.dword;
5830 }
5831
5832 /**
5833  * Get age param from counter index.
5834  *
5835  * @param[in] dev
5836  *   Pointer to the Ethernet device structure.
5837  * @param[in] counter
5838  *   Index to the counter handler.
5839  *
5840  * @return
5841  *   The aging parameter specified for the counter index.
5842  */
5843 static struct mlx5_age_param*
5844 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5845                                 uint32_t counter)
5846 {
5847         struct mlx5_flow_counter *cnt;
5848         struct mlx5_flow_counter_pool *pool = NULL;
5849
5850         flow_dv_counter_get_by_idx(dev, counter, &pool);
5851         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5852         cnt = MLX5_POOL_GET_CNT(pool, counter);
5853         return MLX5_CNT_TO_AGE(cnt);
5854 }
5855
5856 /**
5857  * Remove a flow counter from aged counter list.
5858  *
5859  * @param[in] dev
5860  *   Pointer to the Ethernet device structure.
5861  * @param[in] counter
5862  *   Index to the counter handler.
5863  * @param[in] cnt
5864  *   Pointer to the counter handler.
5865  */
5866 static void
5867 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5868                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5869 {
5870         struct mlx5_age_info *age_info;
5871         struct mlx5_age_param *age_param;
5872         struct mlx5_priv *priv = dev->data->dev_private;
5873         uint16_t expected = AGE_CANDIDATE;
5874
5875         age_info = GET_PORT_AGE_INFO(priv);
5876         age_param = flow_dv_counter_idx_get_age(dev, counter);
5877         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5878                                          AGE_FREE, false, __ATOMIC_RELAXED,
5879                                          __ATOMIC_RELAXED)) {
5880                 /**
5881                  * We need the lock even it is age timeout,
5882                  * since counter may still in process.
5883                  */
5884                 rte_spinlock_lock(&age_info->aged_sl);
5885                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5886                 rte_spinlock_unlock(&age_info->aged_sl);
5887                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5888         }
5889 }
5890
5891 /**
5892  * Release a flow counter.
5893  *
5894  * @param[in] dev
5895  *   Pointer to the Ethernet device structure.
5896  * @param[in] counter
5897  *   Index to the counter handler.
5898  */
5899 static void
5900 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5901 {
5902         struct mlx5_priv *priv = dev->data->dev_private;
5903         struct mlx5_flow_counter_pool *pool = NULL;
5904         struct mlx5_flow_counter *cnt;
5905         enum mlx5_counter_type cnt_type;
5906
5907         if (!counter)
5908                 return;
5909         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5910         MLX5_ASSERT(pool);
5911         if (IS_SHARED_CNT(counter) &&
5912             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5913                 return;
5914         if (pool->is_aged)
5915                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5916         cnt->pool = pool;
5917         /*
5918          * Put the counter back to list to be updated in none fallback mode.
5919          * Currently, we are using two list alternately, while one is in query,
5920          * add the freed counter to the other list based on the pool query_gen
5921          * value. After query finishes, add counter the list to the global
5922          * container counter list. The list changes while query starts. In
5923          * this case, lock will not be needed as query callback and release
5924          * function both operate with the different list.
5925          *
5926          */
5927         if (!priv->sh->cmng.counter_fallback) {
5928                 rte_spinlock_lock(&pool->csl);
5929                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5930                 rte_spinlock_unlock(&pool->csl);
5931         } else {
5932                 cnt->dcs_when_free = cnt->dcs_when_active;
5933                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5934                                            MLX5_COUNTER_TYPE_ORIGIN;
5935                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5936                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5937                                   cnt, next);
5938                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5939         }
5940 }
5941
5942 /**
5943  * Resize a meter id container.
5944  *
5945  * @param[in] dev
5946  *   Pointer to the Ethernet device structure.
5947  *
5948  * @return
5949  *   0 on success, otherwise negative errno value and rte_errno is set.
5950  */
5951 static int
5952 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5953 {
5954         struct mlx5_priv *priv = dev->data->dev_private;
5955         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5956         void *old_pools = mtrmng->pools;
5957         uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5958         uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5959         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5960
5961         if (!pools) {
5962                 rte_errno = ENOMEM;
5963                 return -ENOMEM;
5964         }
5965         if (old_pools)
5966                 memcpy(pools, old_pools, mtrmng->n *
5967                                        sizeof(struct mlx5_aso_mtr_pool *));
5968         mtrmng->n = resize;
5969         mtrmng->pools = pools;
5970         if (old_pools)
5971                 mlx5_free(old_pools);
5972         return 0;
5973 }
5974
5975 /**
5976  * Prepare a new meter and/or a new meter pool.
5977  *
5978  * @param[in] dev
5979  *   Pointer to the Ethernet device structure.
5980  * @param[out] mtr_free
5981  *   Where to put the pointer of a new meter.g.
5982  *
5983  * @return
5984  *   The meter pool pointer and @mtr_free is set on success,
5985  *   NULL otherwise and rte_errno is set.
5986  */
5987 static struct mlx5_aso_mtr_pool *
5988 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5989                              struct mlx5_aso_mtr **mtr_free)
5990 {
5991         struct mlx5_priv *priv = dev->data->dev_private;
5992         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5993         struct mlx5_aso_mtr_pool *pool = NULL;
5994         struct mlx5_devx_obj *dcs = NULL;
5995         uint32_t i;
5996         uint32_t log_obj_size;
5997
5998         log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
5999         dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6000                         priv->sh->pdn, log_obj_size);
6001         if (!dcs) {
6002                 rte_errno = ENODATA;
6003                 return NULL;
6004         }
6005         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6006         if (!pool) {
6007                 rte_errno = ENOMEM;
6008                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6009                 return NULL;
6010         }
6011         pool->devx_obj = dcs;
6012         pool->index = mtrmng->n_valid;
6013         if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
6014                 mlx5_free(pool);
6015                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6016                 return NULL;
6017         }
6018         mtrmng->pools[pool->index] = pool;
6019         mtrmng->n_valid++;
6020         for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6021                 pool->mtrs[i].offset = i;
6022                 pool->mtrs[i].fm.meter_id = UINT32_MAX;
6023                 LIST_INSERT_HEAD(&mtrmng->meters,
6024                                                 &pool->mtrs[i], next);
6025         }
6026         pool->mtrs[0].offset = 0;
6027         pool->mtrs[0].fm.meter_id = UINT32_MAX;
6028         *mtr_free = &pool->mtrs[0];
6029         return pool;
6030 }
6031
6032 /**
6033  * Release a flow meter into pool.
6034  *
6035  * @param[in] dev
6036  *   Pointer to the Ethernet device structure.
6037  * @param[in] mtr_idx
6038  *   Index to aso flow meter.
6039  */
6040 static void
6041 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6042 {
6043         struct mlx5_priv *priv = dev->data->dev_private;
6044         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6045         struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6046
6047         MLX5_ASSERT(aso_mtr);
6048         rte_spinlock_lock(&mtrmng->mtrsl);
6049         memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6050         aso_mtr->state = ASO_METER_FREE;
6051         aso_mtr->fm.meter_id = UINT32_MAX;
6052         LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6053         rte_spinlock_unlock(&mtrmng->mtrsl);
6054 }
6055
6056 /**
6057  * Allocate a aso flow meter.
6058  *
6059  * @param[in] dev
6060  *   Pointer to the Ethernet device structure.
6061  *
6062  * @return
6063  *   Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6064  */
6065 static uint32_t
6066 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6067 {
6068         struct mlx5_priv *priv = dev->data->dev_private;
6069         struct mlx5_aso_mtr *mtr_free = NULL;
6070         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6071         struct mlx5_aso_mtr_pool *pool;
6072         uint32_t mtr_idx = 0;
6073
6074         if (!priv->config.devx) {
6075                 rte_errno = ENOTSUP;
6076                 return 0;
6077         }
6078         /* Allocate the flow meter memory. */
6079         /* Get free meters from management. */
6080         rte_spinlock_lock(&mtrmng->mtrsl);
6081         mtr_free = LIST_FIRST(&mtrmng->meters);
6082         if (mtr_free)
6083                 LIST_REMOVE(mtr_free, next);
6084         if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6085                 rte_spinlock_unlock(&mtrmng->mtrsl);
6086                 return 0;
6087         }
6088         mtr_free->state = ASO_METER_WAIT;
6089         rte_spinlock_unlock(&mtrmng->mtrsl);
6090         pool = container_of(mtr_free,
6091                                         struct mlx5_aso_mtr_pool,
6092                                         mtrs[mtr_free->offset]);
6093         mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6094         return mtr_idx;
6095 }
6096
6097 /**
6098  * Verify the @p attributes will be correctly understood by the NIC and store
6099  * them in the @p flow if everything is correct.
6100  *
6101  * @param[in] dev
6102  *   Pointer to dev struct.
6103  * @param[in] attributes
6104  *   Pointer to flow attributes
6105  * @param[in] external
6106  *   This flow rule is created by request external to PMD.
6107  * @param[out] error
6108  *   Pointer to error structure.
6109  *
6110  * @return
6111  *   - 0 on success and non root table.
6112  *   - 1 on success and root table.
6113  *   - a negative errno value otherwise and rte_errno is set.
6114  */
6115 static int
6116 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6117                             const struct mlx5_flow_tunnel *tunnel,
6118                             const struct rte_flow_attr *attributes,
6119                             const struct flow_grp_info *grp_info,
6120                             struct rte_flow_error *error)
6121 {
6122         struct mlx5_priv *priv = dev->data->dev_private;
6123         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6124         int ret = 0;
6125
6126 #ifndef HAVE_MLX5DV_DR
6127         RTE_SET_USED(tunnel);
6128         RTE_SET_USED(grp_info);
6129         if (attributes->group)
6130                 return rte_flow_error_set(error, ENOTSUP,
6131                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6132                                           NULL,
6133                                           "groups are not supported");
6134 #else
6135         uint32_t table = 0;
6136
6137         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6138                                        grp_info, error);
6139         if (ret)
6140                 return ret;
6141         if (!table)
6142                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6143 #endif
6144         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6145             attributes->priority > lowest_priority)
6146                 return rte_flow_error_set(error, ENOTSUP,
6147                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6148                                           NULL,
6149                                           "priority out of range");
6150         if (attributes->transfer) {
6151                 if (!priv->config.dv_esw_en)
6152                         return rte_flow_error_set
6153                                 (error, ENOTSUP,
6154                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6155                                  "E-Switch dr is not supported");
6156                 if (!(priv->representor || priv->master))
6157                         return rte_flow_error_set
6158                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6159                                  NULL, "E-Switch configuration can only be"
6160                                  " done by a master or a representor device");
6161                 if (attributes->egress)
6162                         return rte_flow_error_set
6163                                 (error, ENOTSUP,
6164                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6165                                  "egress is not supported");
6166         }
6167         if (!(attributes->egress ^ attributes->ingress))
6168                 return rte_flow_error_set(error, ENOTSUP,
6169                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6170                                           "must specify exactly one of "
6171                                           "ingress or egress");
6172         return ret;
6173 }
6174
6175 /**
6176  * Internal validation function. For validating both actions and items.
6177  *
6178  * @param[in] dev
6179  *   Pointer to the rte_eth_dev structure.
6180  * @param[in] attr
6181  *   Pointer to the flow attributes.
6182  * @param[in] items
6183  *   Pointer to the list of items.
6184  * @param[in] actions
6185  *   Pointer to the list of actions.
6186  * @param[in] external
6187  *   This flow rule is created by request external to PMD.
6188  * @param[in] hairpin
6189  *   Number of hairpin TX actions, 0 means classic flow.
6190  * @param[out] error
6191  *   Pointer to the error structure.
6192  *
6193  * @return
6194  *   0 on success, a negative errno value otherwise and rte_errno is set.
6195  */
6196 static int
6197 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6198                  const struct rte_flow_item items[],
6199                  const struct rte_flow_action actions[],
6200                  bool external, int hairpin, struct rte_flow_error *error)
6201 {
6202         int ret;
6203         uint64_t action_flags = 0;
6204         uint64_t item_flags = 0;
6205         uint64_t last_item = 0;
6206         uint8_t next_protocol = 0xff;
6207         uint16_t ether_type = 0;
6208         int actions_n = 0;
6209         uint8_t item_ipv6_proto = 0;
6210         int fdb_mirror_limit = 0;
6211         int modify_after_mirror = 0;
6212         const struct rte_flow_item *geneve_item = NULL;
6213         const struct rte_flow_item *gre_item = NULL;
6214         const struct rte_flow_item *gtp_item = NULL;
6215         const struct rte_flow_action_raw_decap *decap;
6216         const struct rte_flow_action_raw_encap *encap;
6217         const struct rte_flow_action_rss *rss = NULL;
6218         const struct rte_flow_action_rss *sample_rss = NULL;
6219         const struct rte_flow_action_count *count = NULL;
6220         const struct rte_flow_action_count *sample_count = NULL;
6221         const struct rte_flow_item_tcp nic_tcp_mask = {
6222                 .hdr = {
6223                         .tcp_flags = 0xFF,
6224                         .src_port = RTE_BE16(UINT16_MAX),
6225                         .dst_port = RTE_BE16(UINT16_MAX),
6226                 }
6227         };
6228         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6229                 .hdr = {
6230                         .src_addr =
6231                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6232                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6233                         .dst_addr =
6234                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6235                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6236                         .vtc_flow = RTE_BE32(0xffffffff),
6237                         .proto = 0xff,
6238                         .hop_limits = 0xff,
6239                 },
6240                 .has_frag_ext = 1,
6241         };
6242         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6243                 .hdr = {
6244                         .common = {
6245                                 .u32 =
6246                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6247                                         .type = 0xFF,
6248                                         }).u32),
6249                         },
6250                         .dummy[0] = 0xffffffff,
6251                 },
6252         };
6253         struct mlx5_priv *priv = dev->data->dev_private;
6254         struct mlx5_dev_config *dev_conf = &priv->config;
6255         uint16_t queue_index = 0xFFFF;
6256         const struct rte_flow_item_vlan *vlan_m = NULL;
6257         uint32_t rw_act_num = 0;
6258         uint64_t is_root;
6259         const struct mlx5_flow_tunnel *tunnel;
6260         struct flow_grp_info grp_info = {
6261                 .external = !!external,
6262                 .transfer = !!attr->transfer,
6263                 .fdb_def_rule = !!priv->fdb_def_rule,
6264         };
6265         const struct rte_eth_hairpin_conf *conf;
6266
6267         if (items == NULL)
6268                 return -1;
6269         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6270                 tunnel = flow_items_to_tunnel(items);
6271                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6272                                 MLX5_FLOW_ACTION_DECAP;
6273         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6274                 tunnel = flow_actions_to_tunnel(actions);
6275                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6276         } else {
6277                 tunnel = NULL;
6278         }
6279         if (tunnel && priv->representor)
6280                 return rte_flow_error_set(error, ENOTSUP,
6281                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6282                                           "decap not supported "
6283                                           "for VF representor");
6284         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6285                                 (dev, tunnel, attr, items, actions);
6286         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6287         if (ret < 0)
6288                 return ret;
6289         is_root = (uint64_t)ret;
6290         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6291                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6292                 int type = items->type;
6293
6294                 if (!mlx5_flow_os_item_supported(type))
6295                         return rte_flow_error_set(error, ENOTSUP,
6296                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6297                                                   NULL, "item not supported");
6298                 switch (type) {
6299                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6300                         if (items[0].type != (typeof(items[0].type))
6301                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6302                                 return rte_flow_error_set
6303                                                 (error, EINVAL,
6304                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6305                                                 NULL, "MLX5 private items "
6306                                                 "must be the first");
6307                         break;
6308                 case RTE_FLOW_ITEM_TYPE_VOID:
6309                         break;
6310                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6311                         ret = flow_dv_validate_item_port_id
6312                                         (dev, items, attr, item_flags, error);
6313                         if (ret < 0)
6314                                 return ret;
6315                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6316                         break;
6317                 case RTE_FLOW_ITEM_TYPE_ETH:
6318                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6319                                                           true, error);
6320                         if (ret < 0)
6321                                 return ret;
6322                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6323                                              MLX5_FLOW_LAYER_OUTER_L2;
6324                         if (items->mask != NULL && items->spec != NULL) {
6325                                 ether_type =
6326                                         ((const struct rte_flow_item_eth *)
6327                                          items->spec)->type;
6328                                 ether_type &=
6329                                         ((const struct rte_flow_item_eth *)
6330                                          items->mask)->type;
6331                                 ether_type = rte_be_to_cpu_16(ether_type);
6332                         } else {
6333                                 ether_type = 0;
6334                         }
6335                         break;
6336                 case RTE_FLOW_ITEM_TYPE_VLAN:
6337                         ret = flow_dv_validate_item_vlan(items, item_flags,
6338                                                          dev, error);
6339                         if (ret < 0)
6340                                 return ret;
6341                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6342                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6343                         if (items->mask != NULL && items->spec != NULL) {
6344                                 ether_type =
6345                                         ((const struct rte_flow_item_vlan *)
6346                                          items->spec)->inner_type;
6347                                 ether_type &=
6348                                         ((const struct rte_flow_item_vlan *)
6349                                          items->mask)->inner_type;
6350                                 ether_type = rte_be_to_cpu_16(ether_type);
6351                         } else {
6352                                 ether_type = 0;
6353                         }
6354                         /* Store outer VLAN mask for of_push_vlan action. */
6355                         if (!tunnel)
6356                                 vlan_m = items->mask;
6357                         break;
6358                 case RTE_FLOW_ITEM_TYPE_IPV4:
6359                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6360                                                   &item_flags, &tunnel);
6361                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6362                                                          last_item, ether_type,
6363                                                          error);
6364                         if (ret < 0)
6365                                 return ret;
6366                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6367                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6368                         if (items->mask != NULL &&
6369                             ((const struct rte_flow_item_ipv4 *)
6370                              items->mask)->hdr.next_proto_id) {
6371                                 next_protocol =
6372                                         ((const struct rte_flow_item_ipv4 *)
6373                                          (items->spec))->hdr.next_proto_id;
6374                                 next_protocol &=
6375                                         ((const struct rte_flow_item_ipv4 *)
6376                                          (items->mask))->hdr.next_proto_id;
6377                         } else {
6378                                 /* Reset for inner layer. */
6379                                 next_protocol = 0xff;
6380                         }
6381                         break;
6382                 case RTE_FLOW_ITEM_TYPE_IPV6:
6383                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6384                                                   &item_flags, &tunnel);
6385                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6386                                                            last_item,
6387                                                            ether_type,
6388                                                            &nic_ipv6_mask,
6389                                                            error);
6390                         if (ret < 0)
6391                                 return ret;
6392                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6393                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6394                         if (items->mask != NULL &&
6395                             ((const struct rte_flow_item_ipv6 *)
6396                              items->mask)->hdr.proto) {
6397                                 item_ipv6_proto =
6398                                         ((const struct rte_flow_item_ipv6 *)
6399                                          items->spec)->hdr.proto;
6400                                 next_protocol =
6401                                         ((const struct rte_flow_item_ipv6 *)
6402                                          items->spec)->hdr.proto;
6403                                 next_protocol &=
6404                                         ((const struct rte_flow_item_ipv6 *)
6405                                          items->mask)->hdr.proto;
6406                         } else {
6407                                 /* Reset for inner layer. */
6408                                 next_protocol = 0xff;
6409                         }
6410                         break;
6411                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6412                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6413                                                                   item_flags,
6414                                                                   error);
6415                         if (ret < 0)
6416                                 return ret;
6417                         last_item = tunnel ?
6418                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6419                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6420                         if (items->mask != NULL &&
6421                             ((const struct rte_flow_item_ipv6_frag_ext *)
6422                              items->mask)->hdr.next_header) {
6423                                 next_protocol =
6424                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6425                                  items->spec)->hdr.next_header;
6426                                 next_protocol &=
6427                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6428                                  items->mask)->hdr.next_header;
6429                         } else {
6430                                 /* Reset for inner layer. */
6431                                 next_protocol = 0xff;
6432                         }
6433                         break;
6434                 case RTE_FLOW_ITEM_TYPE_TCP:
6435                         ret = mlx5_flow_validate_item_tcp
6436                                                 (items, item_flags,
6437                                                  next_protocol,
6438                                                  &nic_tcp_mask,
6439                                                  error);
6440                         if (ret < 0)
6441                                 return ret;
6442                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6443                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6444                         break;
6445                 case RTE_FLOW_ITEM_TYPE_UDP:
6446                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6447                                                           next_protocol,
6448                                                           error);
6449                         if (ret < 0)
6450                                 return ret;
6451                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6452                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6453                         break;
6454                 case RTE_FLOW_ITEM_TYPE_GRE:
6455                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6456                                                           next_protocol, error);
6457                         if (ret < 0)
6458                                 return ret;
6459                         gre_item = items;
6460                         last_item = MLX5_FLOW_LAYER_GRE;
6461                         break;
6462                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6463                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6464                                                             next_protocol,
6465                                                             error);
6466                         if (ret < 0)
6467                                 return ret;
6468                         last_item = MLX5_FLOW_LAYER_NVGRE;
6469                         break;
6470                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6471                         ret = mlx5_flow_validate_item_gre_key
6472                                 (items, item_flags, gre_item, error);
6473                         if (ret < 0)
6474                                 return ret;
6475                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6476                         break;
6477                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6478                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6479                                                             error);
6480                         if (ret < 0)
6481                                 return ret;
6482                         last_item = MLX5_FLOW_LAYER_VXLAN;
6483                         break;
6484                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6485                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6486                                                                 item_flags, dev,
6487                                                                 error);
6488                         if (ret < 0)
6489                                 return ret;
6490                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6491                         break;
6492                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6493                         ret = mlx5_flow_validate_item_geneve(items,
6494                                                              item_flags, dev,
6495                                                              error);
6496                         if (ret < 0)
6497                                 return ret;
6498                         geneve_item = items;
6499                         last_item = MLX5_FLOW_LAYER_GENEVE;
6500                         break;
6501                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6502                         ret = mlx5_flow_validate_item_geneve_opt(items,
6503                                                                  last_item,
6504                                                                  geneve_item,
6505                                                                  dev,
6506                                                                  error);
6507                         if (ret < 0)
6508                                 return ret;
6509                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6510                         break;
6511                 case RTE_FLOW_ITEM_TYPE_MPLS:
6512                         ret = mlx5_flow_validate_item_mpls(dev, items,
6513                                                            item_flags,
6514                                                            last_item, error);
6515                         if (ret < 0)
6516                                 return ret;
6517                         last_item = MLX5_FLOW_LAYER_MPLS;
6518                         break;
6519
6520                 case RTE_FLOW_ITEM_TYPE_MARK:
6521                         ret = flow_dv_validate_item_mark(dev, items, attr,
6522                                                          error);
6523                         if (ret < 0)
6524                                 return ret;
6525                         last_item = MLX5_FLOW_ITEM_MARK;
6526                         break;
6527                 case RTE_FLOW_ITEM_TYPE_META:
6528                         ret = flow_dv_validate_item_meta(dev, items, attr,
6529                                                          error);
6530                         if (ret < 0)
6531                                 return ret;
6532                         last_item = MLX5_FLOW_ITEM_METADATA;
6533                         break;
6534                 case RTE_FLOW_ITEM_TYPE_ICMP:
6535                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6536                                                            next_protocol,
6537                                                            error);
6538                         if (ret < 0)
6539                                 return ret;
6540                         last_item = MLX5_FLOW_LAYER_ICMP;
6541                         break;
6542                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6543                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6544                                                             next_protocol,
6545                                                             error);
6546                         if (ret < 0)
6547                                 return ret;
6548                         item_ipv6_proto = IPPROTO_ICMPV6;
6549                         last_item = MLX5_FLOW_LAYER_ICMP6;
6550                         break;
6551                 case RTE_FLOW_ITEM_TYPE_TAG:
6552                         ret = flow_dv_validate_item_tag(dev, items,
6553                                                         attr, error);
6554                         if (ret < 0)
6555                                 return ret;
6556                         last_item = MLX5_FLOW_ITEM_TAG;
6557                         break;
6558                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6559                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6560                         break;
6561                 case RTE_FLOW_ITEM_TYPE_GTP:
6562                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6563                                                         error);
6564                         if (ret < 0)
6565                                 return ret;
6566                         gtp_item = items;
6567                         last_item = MLX5_FLOW_LAYER_GTP;
6568                         break;
6569                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6570                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6571                                                             gtp_item, attr,
6572                                                             error);
6573                         if (ret < 0)
6574                                 return ret;
6575                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6576                         break;
6577                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6578                         /* Capacity will be checked in the translate stage. */
6579                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6580                                                             last_item,
6581                                                             ether_type,
6582                                                             &nic_ecpri_mask,
6583                                                             error);
6584                         if (ret < 0)
6585                                 return ret;
6586                         last_item = MLX5_FLOW_LAYER_ECPRI;
6587                         break;
6588                 default:
6589                         return rte_flow_error_set(error, ENOTSUP,
6590                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6591                                                   NULL, "item not supported");
6592                 }
6593                 item_flags |= last_item;
6594         }
6595         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6596                 int type = actions->type;
6597
6598                 if (!mlx5_flow_os_action_supported(type))
6599                         return rte_flow_error_set(error, ENOTSUP,
6600                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6601                                                   actions,
6602                                                   "action not supported");
6603                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6604                         return rte_flow_error_set(error, ENOTSUP,
6605                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6606                                                   actions, "too many actions");
6607                 switch (type) {
6608                 case RTE_FLOW_ACTION_TYPE_VOID:
6609                         break;
6610                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6611                         ret = flow_dv_validate_action_port_id(dev,
6612                                                               action_flags,
6613                                                               actions,
6614                                                               attr,
6615                                                               error);
6616                         if (ret)
6617                                 return ret;
6618                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6619                         ++actions_n;
6620                         break;
6621                 case RTE_FLOW_ACTION_TYPE_FLAG:
6622                         ret = flow_dv_validate_action_flag(dev, action_flags,
6623                                                            attr, error);
6624                         if (ret < 0)
6625                                 return ret;
6626                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6627                                 /* Count all modify-header actions as one. */
6628                                 if (!(action_flags &
6629                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6630                                         ++actions_n;
6631                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6632                                                 MLX5_FLOW_ACTION_MARK_EXT;
6633                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6634                                         modify_after_mirror = 1;
6635
6636                         } else {
6637                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6638                                 ++actions_n;
6639                         }
6640                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6641                         break;
6642                 case RTE_FLOW_ACTION_TYPE_MARK:
6643                         ret = flow_dv_validate_action_mark(dev, actions,
6644                                                            action_flags,
6645                                                            attr, error);
6646                         if (ret < 0)
6647                                 return ret;
6648                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6649                                 /* Count all modify-header actions as one. */
6650                                 if (!(action_flags &
6651                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6652                                         ++actions_n;
6653                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6654                                                 MLX5_FLOW_ACTION_MARK_EXT;
6655                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6656                                         modify_after_mirror = 1;
6657                         } else {
6658                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6659                                 ++actions_n;
6660                         }
6661                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6662                         break;
6663                 case RTE_FLOW_ACTION_TYPE_SET_META:
6664                         ret = flow_dv_validate_action_set_meta(dev, actions,
6665                                                                action_flags,
6666                                                                attr, error);
6667                         if (ret < 0)
6668                                 return ret;
6669                         /* Count all modify-header actions as one action. */
6670                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6671                                 ++actions_n;
6672                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6673                                 modify_after_mirror = 1;
6674                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6675                         rw_act_num += MLX5_ACT_NUM_SET_META;
6676                         break;
6677                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6678                         ret = flow_dv_validate_action_set_tag(dev, actions,
6679                                                               action_flags,
6680                                                               attr, error);
6681                         if (ret < 0)
6682                                 return ret;
6683                         /* Count all modify-header actions as one action. */
6684                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6685                                 ++actions_n;
6686                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6687                                 modify_after_mirror = 1;
6688                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6689                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6690                         break;
6691                 case RTE_FLOW_ACTION_TYPE_DROP:
6692                         ret = mlx5_flow_validate_action_drop(action_flags,
6693                                                              attr, error);
6694                         if (ret < 0)
6695                                 return ret;
6696                         action_flags |= MLX5_FLOW_ACTION_DROP;
6697                         ++actions_n;
6698                         break;
6699                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6700                         ret = mlx5_flow_validate_action_queue(actions,
6701                                                               action_flags, dev,
6702                                                               attr, error);
6703                         if (ret < 0)
6704                                 return ret;
6705                         queue_index = ((const struct rte_flow_action_queue *)
6706                                                         (actions->conf))->index;
6707                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6708                         ++actions_n;
6709                         break;
6710                 case RTE_FLOW_ACTION_TYPE_RSS:
6711                         rss = actions->conf;
6712                         ret = mlx5_flow_validate_action_rss(actions,
6713                                                             action_flags, dev,
6714                                                             attr, item_flags,
6715                                                             error);
6716                         if (ret < 0)
6717                                 return ret;
6718                         if (rss && sample_rss &&
6719                             (sample_rss->level != rss->level ||
6720                             sample_rss->types != rss->types))
6721                                 return rte_flow_error_set(error, ENOTSUP,
6722                                         RTE_FLOW_ERROR_TYPE_ACTION,
6723                                         NULL,
6724                                         "Can't use the different RSS types "
6725                                         "or level in the same flow");
6726                         if (rss != NULL && rss->queue_num)
6727                                 queue_index = rss->queue[0];
6728                         action_flags |= MLX5_FLOW_ACTION_RSS;
6729                         ++actions_n;
6730                         break;
6731                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6732                         ret =
6733                         mlx5_flow_validate_action_default_miss(action_flags,
6734                                         attr, error);
6735                         if (ret < 0)
6736                                 return ret;
6737                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6738                         ++actions_n;
6739                         break;
6740                 case RTE_FLOW_ACTION_TYPE_COUNT:
6741                         ret = flow_dv_validate_action_count(dev, actions,
6742                                                             action_flags,
6743                                                             error);
6744                         if (ret < 0)
6745                                 return ret;
6746                         count = actions->conf;
6747                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6748                         ++actions_n;
6749                         break;
6750                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6751                         if (flow_dv_validate_action_pop_vlan(dev,
6752                                                              action_flags,
6753                                                              actions,
6754                                                              item_flags, attr,
6755                                                              error))
6756                                 return -rte_errno;
6757                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6758                                 modify_after_mirror = 1;
6759                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6760                         ++actions_n;
6761                         break;
6762                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6763                         ret = flow_dv_validate_action_push_vlan(dev,
6764                                                                 action_flags,
6765                                                                 vlan_m,
6766                                                                 actions, attr,
6767                                                                 error);
6768                         if (ret < 0)
6769                                 return ret;
6770                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6771                                 modify_after_mirror = 1;
6772                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6773                         ++actions_n;
6774                         break;
6775                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6776                         ret = flow_dv_validate_action_set_vlan_pcp
6777                                                 (action_flags, actions, error);
6778                         if (ret < 0)
6779                                 return ret;
6780                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6781                                 modify_after_mirror = 1;
6782                         /* Count PCP with push_vlan command. */
6783                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6784                         break;
6785                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6786                         ret = flow_dv_validate_action_set_vlan_vid
6787                                                 (item_flags, action_flags,
6788                                                  actions, error);
6789                         if (ret < 0)
6790                                 return ret;
6791                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6792                                 modify_after_mirror = 1;
6793                         /* Count VID with push_vlan command. */
6794                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6795                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6796                         break;
6797                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6798                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6799                         ret = flow_dv_validate_action_l2_encap(dev,
6800                                                                action_flags,
6801                                                                actions, attr,
6802                                                                error);
6803                         if (ret < 0)
6804                                 return ret;
6805                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6806                         ++actions_n;
6807                         break;
6808                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6809                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6810                         ret = flow_dv_validate_action_decap(dev, action_flags,
6811                                                             actions, item_flags,
6812                                                             attr, error);
6813                         if (ret < 0)
6814                                 return ret;
6815                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6816                                 modify_after_mirror = 1;
6817                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6818                         ++actions_n;
6819                         break;
6820                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6821                         ret = flow_dv_validate_action_raw_encap_decap
6822                                 (dev, NULL, actions->conf, attr, &action_flags,
6823                                  &actions_n, actions, item_flags, error);
6824                         if (ret < 0)
6825                                 return ret;
6826                         break;
6827                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6828                         decap = actions->conf;
6829                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6830                                 ;
6831                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6832                                 encap = NULL;
6833                                 actions--;
6834                         } else {
6835                                 encap = actions->conf;
6836                         }
6837                         ret = flow_dv_validate_action_raw_encap_decap
6838                                            (dev,
6839                                             decap ? decap : &empty_decap, encap,
6840                                             attr, &action_flags, &actions_n,
6841                                             actions, item_flags, error);
6842                         if (ret < 0)
6843                                 return ret;
6844                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6845                             (action_flags & MLX5_FLOW_ACTION_DECAP))
6846                                 modify_after_mirror = 1;
6847                         break;
6848                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6849                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6850                         ret = flow_dv_validate_action_modify_mac(action_flags,
6851                                                                  actions,
6852                                                                  item_flags,
6853                                                                  error);
6854                         if (ret < 0)
6855                                 return ret;
6856                         /* Count all modify-header actions as one action. */
6857                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6858                                 ++actions_n;
6859                         action_flags |= actions->type ==
6860                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6861                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6862                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6863                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6864                                 modify_after_mirror = 1;
6865                         /*
6866                          * Even if the source and destination MAC addresses have
6867                          * overlap in the header with 4B alignment, the convert
6868                          * function will handle them separately and 4 SW actions
6869                          * will be created. And 2 actions will be added each
6870                          * time no matter how many bytes of address will be set.
6871                          */
6872                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6873                         break;
6874                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6875                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6876                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6877                                                                   actions,
6878                                                                   item_flags,
6879                                                                   error);
6880                         if (ret < 0)
6881                                 return ret;
6882                         /* Count all modify-header actions as one action. */
6883                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6884                                 ++actions_n;
6885                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6886                                 modify_after_mirror = 1;
6887                         action_flags |= actions->type ==
6888                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6889                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6890                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6891                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6892                         break;
6893                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6894                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6895                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6896                                                                   actions,
6897                                                                   item_flags,
6898                                                                   error);
6899                         if (ret < 0)
6900                                 return ret;
6901                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6902                                 return rte_flow_error_set(error, ENOTSUP,
6903                                         RTE_FLOW_ERROR_TYPE_ACTION,
6904                                         actions,
6905                                         "Can't change header "
6906                                         "with ICMPv6 proto");
6907                         /* Count all modify-header actions as one action. */
6908                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6909                                 ++actions_n;
6910                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6911                                 modify_after_mirror = 1;
6912                         action_flags |= actions->type ==
6913                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6914                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6915                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6916                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6917                         break;
6918                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6919                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6920                         ret = flow_dv_validate_action_modify_tp(action_flags,
6921                                                                 actions,
6922                                                                 item_flags,
6923                                                                 error);
6924                         if (ret < 0)
6925                                 return ret;
6926                         /* Count all modify-header actions as one action. */
6927                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6928                                 ++actions_n;
6929                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6930                                 modify_after_mirror = 1;
6931                         action_flags |= actions->type ==
6932                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6933                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6934                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6935                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6936                         break;
6937                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6938                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6939                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6940                                                                  actions,
6941                                                                  item_flags,
6942                                                                  error);
6943                         if (ret < 0)
6944                                 return ret;
6945                         /* Count all modify-header actions as one action. */
6946                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6947                                 ++actions_n;
6948                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6949                                 modify_after_mirror = 1;
6950                         action_flags |= actions->type ==
6951                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6952                                                 MLX5_FLOW_ACTION_SET_TTL :
6953                                                 MLX5_FLOW_ACTION_DEC_TTL;
6954                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6955                         break;
6956                 case RTE_FLOW_ACTION_TYPE_JUMP:
6957                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6958                                                            action_flags,
6959                                                            attr, external,
6960                                                            error);
6961                         if (ret)
6962                                 return ret;
6963                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6964                             fdb_mirror_limit)
6965                                 return rte_flow_error_set(error, EINVAL,
6966                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6967                                                   NULL,
6968                                                   "sample and jump action combination is not supported");
6969                         ++actions_n;
6970                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6971                         break;
6972                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6973                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6974                         ret = flow_dv_validate_action_modify_tcp_seq
6975                                                                 (action_flags,
6976                                                                  actions,
6977                                                                  item_flags,
6978                                                                  error);
6979                         if (ret < 0)
6980                                 return ret;
6981                         /* Count all modify-header actions as one action. */
6982                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6983                                 ++actions_n;
6984                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6985                                 modify_after_mirror = 1;
6986                         action_flags |= actions->type ==
6987                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6988                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6989                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6990                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6991                         break;
6992                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6993                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6994                         ret = flow_dv_validate_action_modify_tcp_ack
6995                                                                 (action_flags,
6996                                                                  actions,
6997                                                                  item_flags,
6998                                                                  error);
6999                         if (ret < 0)
7000                                 return ret;
7001                         /* Count all modify-header actions as one action. */
7002                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7003                                 ++actions_n;
7004                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7005                                 modify_after_mirror = 1;
7006                         action_flags |= actions->type ==
7007                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7008                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
7009                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7010                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7011                         break;
7012                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7013                         break;
7014                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7015                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7016                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7017                         break;
7018                 case RTE_FLOW_ACTION_TYPE_METER:
7019                         ret = mlx5_flow_validate_action_meter(dev,
7020                                                               action_flags,
7021                                                               actions, attr,
7022                                                               error);
7023                         if (ret < 0)
7024                                 return ret;
7025                         action_flags |= MLX5_FLOW_ACTION_METER;
7026                         ++actions_n;
7027                         /* Meter action will add one more TAG action. */
7028                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7029                         break;
7030                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7031                         if (!attr->transfer && !attr->group)
7032                                 return rte_flow_error_set(error, ENOTSUP,
7033                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7034                                                                            NULL,
7035                           "Shared ASO age action is not supported for group 0");
7036                         action_flags |= MLX5_FLOW_ACTION_AGE;
7037                         ++actions_n;
7038                         break;
7039                 case RTE_FLOW_ACTION_TYPE_AGE:
7040                         ret = flow_dv_validate_action_age(action_flags,
7041                                                           actions, dev,
7042                                                           error);
7043                         if (ret < 0)
7044                                 return ret;
7045                         /*
7046                          * Validate the regular AGE action (using counter)
7047                          * mutual exclusion with share counter actions.
7048                          */
7049                         if (!priv->sh->flow_hit_aso_en) {
7050                                 if (count && count->shared)
7051                                         return rte_flow_error_set
7052                                                 (error, EINVAL,
7053                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7054                                                 NULL,
7055                                                 "old age and shared count combination is not supported");
7056                                 if (sample_count)
7057                                         return rte_flow_error_set
7058                                                 (error, EINVAL,
7059                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7060                                                 NULL,
7061                                                 "old age action and count must be in the same sub flow");
7062                         }
7063                         action_flags |= MLX5_FLOW_ACTION_AGE;
7064                         ++actions_n;
7065                         break;
7066                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7067                         ret = flow_dv_validate_action_modify_ipv4_dscp
7068                                                          (action_flags,
7069                                                           actions,
7070                                                           item_flags,
7071                                                           error);
7072                         if (ret < 0)
7073                                 return ret;
7074                         /* Count all modify-header actions as one action. */
7075                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7076                                 ++actions_n;
7077                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7078                                 modify_after_mirror = 1;
7079                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7080                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7081                         break;
7082                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7083                         ret = flow_dv_validate_action_modify_ipv6_dscp
7084                                                                 (action_flags,
7085                                                                  actions,
7086                                                                  item_flags,
7087                                                                  error);
7088                         if (ret < 0)
7089                                 return ret;
7090                         /* Count all modify-header actions as one action. */
7091                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7092                                 ++actions_n;
7093                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7094                                 modify_after_mirror = 1;
7095                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7096                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7097                         break;
7098                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7099                         ret = flow_dv_validate_action_sample(&action_flags,
7100                                                              actions, dev,
7101                                                              attr, item_flags,
7102                                                              rss, &sample_rss,
7103                                                              &sample_count,
7104                                                              &fdb_mirror_limit,
7105                                                              error);
7106                         if (ret < 0)
7107                                 return ret;
7108                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7109                         ++actions_n;
7110                         break;
7111                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7112                         if (actions[0].type != (typeof(actions[0].type))
7113                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7114                                 return rte_flow_error_set
7115                                                 (error, EINVAL,
7116                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7117                                                 NULL, "MLX5 private action "
7118                                                 "must be the first");
7119
7120                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7121                         break;
7122                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7123                         ret = flow_dv_validate_action_modify_field(dev,
7124                                                                    action_flags,
7125                                                                    actions,
7126                                                                    attr,
7127                                                                    error);
7128                         if (ret < 0)
7129                                 return ret;
7130                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7131                                 modify_after_mirror = 1;
7132                         /* Count all modify-header actions as one action. */
7133                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7134                                 ++actions_n;
7135                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7136                         rw_act_num += ret;
7137                         break;
7138                 default:
7139                         return rte_flow_error_set(error, ENOTSUP,
7140                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7141                                                   actions,
7142                                                   "action not supported");
7143                 }
7144         }
7145         /*
7146          * Validate actions in flow rules
7147          * - Explicit decap action is prohibited by the tunnel offload API.
7148          * - Drop action in tunnel steer rule is prohibited by the API.
7149          * - Application cannot use MARK action because it's value can mask
7150          *   tunnel default miss nitification.
7151          * - JUMP in tunnel match rule has no support in current PMD
7152          *   implementation.
7153          * - TAG & META are reserved for future uses.
7154          */
7155         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7156                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
7157                                             MLX5_FLOW_ACTION_MARK     |
7158                                             MLX5_FLOW_ACTION_SET_TAG  |
7159                                             MLX5_FLOW_ACTION_SET_META |
7160                                             MLX5_FLOW_ACTION_DROP;
7161
7162                 if (action_flags & bad_actions_mask)
7163                         return rte_flow_error_set
7164                                         (error, EINVAL,
7165                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7166                                         "Invalid RTE action in tunnel "
7167                                         "set decap rule");
7168                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7169                         return rte_flow_error_set
7170                                         (error, EINVAL,
7171                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7172                                         "tunnel set decap rule must terminate "
7173                                         "with JUMP");
7174                 if (!attr->ingress)
7175                         return rte_flow_error_set
7176                                         (error, EINVAL,
7177                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7178                                         "tunnel flows for ingress traffic only");
7179         }
7180         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7181                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7182                                             MLX5_FLOW_ACTION_MARK    |
7183                                             MLX5_FLOW_ACTION_SET_TAG |
7184                                             MLX5_FLOW_ACTION_SET_META;
7185
7186                 if (action_flags & bad_actions_mask)
7187                         return rte_flow_error_set
7188                                         (error, EINVAL,
7189                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7190                                         "Invalid RTE action in tunnel "
7191                                         "set match rule");
7192         }
7193         /*
7194          * Validate the drop action mutual exclusion with other actions.
7195          * Drop action is mutually-exclusive with any other action, except for
7196          * Count action.
7197          * Drop action compatibility with tunnel offload was already validated.
7198          */
7199         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7200                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7201         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7202             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7203                 return rte_flow_error_set(error, EINVAL,
7204                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7205                                           "Drop action is mutually-exclusive "
7206                                           "with any other action, except for "
7207                                           "Count action");
7208         /* Eswitch has few restrictions on using items and actions */
7209         if (attr->transfer) {
7210                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7211                     action_flags & MLX5_FLOW_ACTION_FLAG)
7212                         return rte_flow_error_set(error, ENOTSUP,
7213                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7214                                                   NULL,
7215                                                   "unsupported action FLAG");
7216                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7217                     action_flags & MLX5_FLOW_ACTION_MARK)
7218                         return rte_flow_error_set(error, ENOTSUP,
7219                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7220                                                   NULL,
7221                                                   "unsupported action MARK");
7222                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7223                         return rte_flow_error_set(error, ENOTSUP,
7224                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7225                                                   NULL,
7226                                                   "unsupported action QUEUE");
7227                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7228                         return rte_flow_error_set(error, ENOTSUP,
7229                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7230                                                   NULL,
7231                                                   "unsupported action RSS");
7232                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7233                         return rte_flow_error_set(error, EINVAL,
7234                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7235                                                   actions,
7236                                                   "no fate action is found");
7237         } else {
7238                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7239                         return rte_flow_error_set(error, EINVAL,
7240                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7241                                                   actions,
7242                                                   "no fate action is found");
7243         }
7244         /*
7245          * Continue validation for Xcap and VLAN actions.
7246          * If hairpin is working in explicit TX rule mode, there is no actions
7247          * splitting and the validation of hairpin ingress flow should be the
7248          * same as other standard flows.
7249          */
7250         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7251                              MLX5_FLOW_VLAN_ACTIONS)) &&
7252             (queue_index == 0xFFFF ||
7253              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7254              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7255              conf->tx_explicit != 0))) {
7256                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7257                     MLX5_FLOW_XCAP_ACTIONS)
7258                         return rte_flow_error_set(error, ENOTSUP,
7259                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7260                                                   NULL, "encap and decap "
7261                                                   "combination aren't supported");
7262                 if (!attr->transfer && attr->ingress) {
7263                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7264                                 return rte_flow_error_set
7265                                                 (error, ENOTSUP,
7266                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7267                                                  NULL, "encap is not supported"
7268                                                  " for ingress traffic");
7269                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7270                                 return rte_flow_error_set
7271                                                 (error, ENOTSUP,
7272                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7273                                                  NULL, "push VLAN action not "
7274                                                  "supported for ingress");
7275                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7276                                         MLX5_FLOW_VLAN_ACTIONS)
7277                                 return rte_flow_error_set
7278                                                 (error, ENOTSUP,
7279                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7280                                                  NULL, "no support for "
7281                                                  "multiple VLAN actions");
7282                 }
7283         }
7284         /*
7285          * Hairpin flow will add one more TAG action in TX implicit mode.
7286          * In TX explicit mode, there will be no hairpin flow ID.
7287          */
7288         if (hairpin > 0)
7289                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7290         /* extra metadata enabled: one more TAG action will be add. */
7291         if (dev_conf->dv_flow_en &&
7292             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7293             mlx5_flow_ext_mreg_supported(dev))
7294                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7295         if (rw_act_num >
7296                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7297                 return rte_flow_error_set(error, ENOTSUP,
7298                                           RTE_FLOW_ERROR_TYPE_ACTION,
7299                                           NULL, "too many header modify"
7300                                           " actions to support");
7301         }
7302         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7303         if (fdb_mirror_limit && modify_after_mirror)
7304                 return rte_flow_error_set(error, EINVAL,
7305                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7306                                 "sample before modify action is not supported");
7307         return 0;
7308 }
7309
7310 /**
7311  * Internal preparation function. Allocates the DV flow size,
7312  * this size is constant.
7313  *
7314  * @param[in] dev
7315  *   Pointer to the rte_eth_dev structure.
7316  * @param[in] attr
7317  *   Pointer to the flow attributes.
7318  * @param[in] items
7319  *   Pointer to the list of items.
7320  * @param[in] actions
7321  *   Pointer to the list of actions.
7322  * @param[out] error
7323  *   Pointer to the error structure.
7324  *
7325  * @return
7326  *   Pointer to mlx5_flow object on success,
7327  *   otherwise NULL and rte_errno is set.
7328  */
7329 static struct mlx5_flow *
7330 flow_dv_prepare(struct rte_eth_dev *dev,
7331                 const struct rte_flow_attr *attr __rte_unused,
7332                 const struct rte_flow_item items[] __rte_unused,
7333                 const struct rte_flow_action actions[] __rte_unused,
7334                 struct rte_flow_error *error)
7335 {
7336         uint32_t handle_idx = 0;
7337         struct mlx5_flow *dev_flow;
7338         struct mlx5_flow_handle *dev_handle;
7339         struct mlx5_priv *priv = dev->data->dev_private;
7340         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7341
7342         MLX5_ASSERT(wks);
7343         /* In case of corrupting the memory. */
7344         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7345                 rte_flow_error_set(error, ENOSPC,
7346                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7347                                    "not free temporary device flow");
7348                 return NULL;
7349         }
7350         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7351                                    &handle_idx);
7352         if (!dev_handle) {
7353                 rte_flow_error_set(error, ENOMEM,
7354                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7355                                    "not enough memory to create flow handle");
7356                 return NULL;
7357         }
7358         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7359         dev_flow = &wks->flows[wks->flow_idx++];
7360         memset(dev_flow, 0, sizeof(*dev_flow));
7361         dev_flow->handle = dev_handle;
7362         dev_flow->handle_idx = handle_idx;
7363         /*
7364          * In some old rdma-core releases, before continuing, a check of the
7365          * length of matching parameter will be done at first. It needs to use
7366          * the length without misc4 param. If the flow has misc4 support, then
7367          * the length needs to be adjusted accordingly. Each param member is
7368          * aligned with a 64B boundary naturally.
7369          */
7370         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7371                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7372         dev_flow->ingress = attr->ingress;
7373         dev_flow->dv.transfer = attr->transfer;
7374         return dev_flow;
7375 }
7376
7377 #ifdef RTE_LIBRTE_MLX5_DEBUG
7378 /**
7379  * Sanity check for match mask and value. Similar to check_valid_spec() in
7380  * kernel driver. If unmasked bit is present in value, it returns failure.
7381  *
7382  * @param match_mask
7383  *   pointer to match mask buffer.
7384  * @param match_value
7385  *   pointer to match value buffer.
7386  *
7387  * @return
7388  *   0 if valid, -EINVAL otherwise.
7389  */
7390 static int
7391 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7392 {
7393         uint8_t *m = match_mask;
7394         uint8_t *v = match_value;
7395         unsigned int i;
7396
7397         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7398                 if (v[i] & ~m[i]) {
7399                         DRV_LOG(ERR,
7400                                 "match_value differs from match_criteria"
7401                                 " %p[%u] != %p[%u]",
7402                                 match_value, i, match_mask, i);
7403                         return -EINVAL;
7404                 }
7405         }
7406         return 0;
7407 }
7408 #endif
7409
7410 /**
7411  * Add match of ip_version.
7412  *
7413  * @param[in] group
7414  *   Flow group.
7415  * @param[in] headers_v
7416  *   Values header pointer.
7417  * @param[in] headers_m
7418  *   Masks header pointer.
7419  * @param[in] ip_version
7420  *   The IP version to set.
7421  */
7422 static inline void
7423 flow_dv_set_match_ip_version(uint32_t group,
7424                              void *headers_v,
7425                              void *headers_m,
7426                              uint8_t ip_version)
7427 {
7428         if (group == 0)
7429                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7430         else
7431                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7432                          ip_version);
7433         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7434         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7435         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7436 }
7437
7438 /**
7439  * Add Ethernet item to matcher and to the value.
7440  *
7441  * @param[in, out] matcher
7442  *   Flow matcher.
7443  * @param[in, out] key
7444  *   Flow matcher value.
7445  * @param[in] item
7446  *   Flow pattern to translate.
7447  * @param[in] inner
7448  *   Item is inner pattern.
7449  */
7450 static void
7451 flow_dv_translate_item_eth(void *matcher, void *key,
7452                            const struct rte_flow_item *item, int inner,
7453                            uint32_t group)
7454 {
7455         const struct rte_flow_item_eth *eth_m = item->mask;
7456         const struct rte_flow_item_eth *eth_v = item->spec;
7457         const struct rte_flow_item_eth nic_mask = {
7458                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7459                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7460                 .type = RTE_BE16(0xffff),
7461                 .has_vlan = 0,
7462         };
7463         void *hdrs_m;
7464         void *hdrs_v;
7465         char *l24_v;
7466         unsigned int i;
7467
7468         if (!eth_v)
7469                 return;
7470         if (!eth_m)
7471                 eth_m = &nic_mask;
7472         if (inner) {
7473                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7474                                          inner_headers);
7475                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7476         } else {
7477                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7478                                          outer_headers);
7479                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7480         }
7481         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7482                &eth_m->dst, sizeof(eth_m->dst));
7483         /* The value must be in the range of the mask. */
7484         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7485         for (i = 0; i < sizeof(eth_m->dst); ++i)
7486                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7487         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7488                &eth_m->src, sizeof(eth_m->src));
7489         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7490         /* The value must be in the range of the mask. */
7491         for (i = 0; i < sizeof(eth_m->dst); ++i)
7492                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7493         /*
7494          * HW supports match on one Ethertype, the Ethertype following the last
7495          * VLAN tag of the packet (see PRM).
7496          * Set match on ethertype only if ETH header is not followed by VLAN.
7497          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7498          * ethertype, and use ip_version field instead.
7499          * eCPRI over Ether layer will use type value 0xAEFE.
7500          */
7501         if (eth_m->type == 0xFFFF) {
7502                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7503                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7504                 switch (eth_v->type) {
7505                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7506                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7507                         return;
7508                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7509                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7510                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7511                         return;
7512                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7513                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7514                         return;
7515                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7516                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7517                         return;
7518                 default:
7519                         break;
7520                 }
7521         }
7522         if (eth_m->has_vlan) {
7523                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7524                 if (eth_v->has_vlan) {
7525                         /*
7526                          * Here, when also has_more_vlan field in VLAN item is
7527                          * not set, only single-tagged packets will be matched.
7528                          */
7529                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7530                         return;
7531                 }
7532         }
7533         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7534                  rte_be_to_cpu_16(eth_m->type));
7535         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7536         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7537 }
7538
7539 /**
7540  * Add VLAN item to matcher and to the value.
7541  *
7542  * @param[in, out] dev_flow
7543  *   Flow descriptor.
7544  * @param[in, out] matcher
7545  *   Flow matcher.
7546  * @param[in, out] key
7547  *   Flow matcher value.
7548  * @param[in] item
7549  *   Flow pattern to translate.
7550  * @param[in] inner
7551  *   Item is inner pattern.
7552  */
7553 static void
7554 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7555                             void *matcher, void *key,
7556                             const struct rte_flow_item *item,
7557                             int inner, uint32_t group)
7558 {
7559         const struct rte_flow_item_vlan *vlan_m = item->mask;
7560         const struct rte_flow_item_vlan *vlan_v = item->spec;
7561         void *hdrs_m;
7562         void *hdrs_v;
7563         uint16_t tci_m;
7564         uint16_t tci_v;
7565
7566         if (inner) {
7567                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7568                                          inner_headers);
7569                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7570         } else {
7571                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7572                                          outer_headers);
7573                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7574                 /*
7575                  * This is workaround, masks are not supported,
7576                  * and pre-validated.
7577                  */
7578                 if (vlan_v)
7579                         dev_flow->handle->vf_vlan.tag =
7580                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7581         }
7582         /*
7583          * When VLAN item exists in flow, mark packet as tagged,
7584          * even if TCI is not specified.
7585          */
7586         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7587                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7588                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7589         }
7590         if (!vlan_v)
7591                 return;
7592         if (!vlan_m)
7593                 vlan_m = &rte_flow_item_vlan_mask;
7594         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7595         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7596         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7597         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7598         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7599         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7600         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7601         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7602         /*
7603          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7604          * ethertype, and use ip_version field instead.
7605          */
7606         if (vlan_m->inner_type == 0xFFFF) {
7607                 switch (vlan_v->inner_type) {
7608                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7609                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7610                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7611                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7612                         return;
7613                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7614                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7615                         return;
7616                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7617                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7618                         return;
7619                 default:
7620                         break;
7621                 }
7622         }
7623         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7624                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7625                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7626                 /* Only one vlan_tag bit can be set. */
7627                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7628                 return;
7629         }
7630         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7631                  rte_be_to_cpu_16(vlan_m->inner_type));
7632         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7633                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7634 }
7635
7636 /**
7637  * Add IPV4 item to matcher and to the value.
7638  *
7639  * @param[in, out] matcher
7640  *   Flow matcher.
7641  * @param[in, out] key
7642  *   Flow matcher value.
7643  * @param[in] item
7644  *   Flow pattern to translate.
7645  * @param[in] inner
7646  *   Item is inner pattern.
7647  * @param[in] group
7648  *   The group to insert the rule.
7649  */
7650 static void
7651 flow_dv_translate_item_ipv4(void *matcher, void *key,
7652                             const struct rte_flow_item *item,
7653                             int inner, uint32_t group)
7654 {
7655         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7656         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7657         const struct rte_flow_item_ipv4 nic_mask = {
7658                 .hdr = {
7659                         .src_addr = RTE_BE32(0xffffffff),
7660                         .dst_addr = RTE_BE32(0xffffffff),
7661                         .type_of_service = 0xff,
7662                         .next_proto_id = 0xff,
7663                         .time_to_live = 0xff,
7664                 },
7665         };
7666         void *headers_m;
7667         void *headers_v;
7668         char *l24_m;
7669         char *l24_v;
7670         uint8_t tos;
7671
7672         if (inner) {
7673                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7674                                          inner_headers);
7675                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7676         } else {
7677                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7678                                          outer_headers);
7679                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7680         }
7681         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7682         if (!ipv4_v)
7683                 return;
7684         if (!ipv4_m)
7685                 ipv4_m = &nic_mask;
7686         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7687                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7688         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7689                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7690         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7691         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7692         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7693                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7694         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7695                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7696         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7697         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7698         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7699         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7700                  ipv4_m->hdr.type_of_service);
7701         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7702         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7703                  ipv4_m->hdr.type_of_service >> 2);
7704         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7705         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7706                  ipv4_m->hdr.next_proto_id);
7707         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7708                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7709         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7710                  ipv4_m->hdr.time_to_live);
7711         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7712                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7713         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7714                  !!(ipv4_m->hdr.fragment_offset));
7715         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7716                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7717 }
7718
7719 /**
7720  * Add IPV6 item to matcher and to the value.
7721  *
7722  * @param[in, out] matcher
7723  *   Flow matcher.
7724  * @param[in, out] key
7725  *   Flow matcher value.
7726  * @param[in] item
7727  *   Flow pattern to translate.
7728  * @param[in] inner
7729  *   Item is inner pattern.
7730  * @param[in] group
7731  *   The group to insert the rule.
7732  */
7733 static void
7734 flow_dv_translate_item_ipv6(void *matcher, void *key,
7735                             const struct rte_flow_item *item,
7736                             int inner, uint32_t group)
7737 {
7738         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7739         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7740         const struct rte_flow_item_ipv6 nic_mask = {
7741                 .hdr = {
7742                         .src_addr =
7743                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7744                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7745                         .dst_addr =
7746                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7747                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7748                         .vtc_flow = RTE_BE32(0xffffffff),
7749                         .proto = 0xff,
7750                         .hop_limits = 0xff,
7751                 },
7752         };
7753         void *headers_m;
7754         void *headers_v;
7755         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7756         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7757         char *l24_m;
7758         char *l24_v;
7759         uint32_t vtc_m;
7760         uint32_t vtc_v;
7761         int i;
7762         int size;
7763
7764         if (inner) {
7765                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7766                                          inner_headers);
7767                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7768         } else {
7769                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7770                                          outer_headers);
7771                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7772         }
7773         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7774         if (!ipv6_v)
7775                 return;
7776         if (!ipv6_m)
7777                 ipv6_m = &nic_mask;
7778         size = sizeof(ipv6_m->hdr.dst_addr);
7779         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7780                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7781         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7782                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7783         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7784         for (i = 0; i < size; ++i)
7785                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7786         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7787                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7788         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7789                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7790         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7791         for (i = 0; i < size; ++i)
7792                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7793         /* TOS. */
7794         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7795         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7796         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7798         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7799         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7800         /* Label. */
7801         if (inner) {
7802                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7803                          vtc_m);
7804                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7805                          vtc_v);
7806         } else {
7807                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7808                          vtc_m);
7809                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7810                          vtc_v);
7811         }
7812         /* Protocol. */
7813         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7814                  ipv6_m->hdr.proto);
7815         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7816                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7817         /* Hop limit. */
7818         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7819                  ipv6_m->hdr.hop_limits);
7820         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7821                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7822         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7823                  !!(ipv6_m->has_frag_ext));
7824         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7825                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7826 }
7827
7828 /**
7829  * Add IPV6 fragment extension item to matcher and to the value.
7830  *
7831  * @param[in, out] matcher
7832  *   Flow matcher.
7833  * @param[in, out] key
7834  *   Flow matcher value.
7835  * @param[in] item
7836  *   Flow pattern to translate.
7837  * @param[in] inner
7838  *   Item is inner pattern.
7839  */
7840 static void
7841 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7842                                      const struct rte_flow_item *item,
7843                                      int inner)
7844 {
7845         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7846         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7847         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7848                 .hdr = {
7849                         .next_header = 0xff,
7850                         .frag_data = RTE_BE16(0xffff),
7851                 },
7852         };
7853         void *headers_m;
7854         void *headers_v;
7855
7856         if (inner) {
7857                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7858                                          inner_headers);
7859                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7860         } else {
7861                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7862                                          outer_headers);
7863                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7864         }
7865         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7866         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7867         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7868         if (!ipv6_frag_ext_v)
7869                 return;
7870         if (!ipv6_frag_ext_m)
7871                 ipv6_frag_ext_m = &nic_mask;
7872         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7873                  ipv6_frag_ext_m->hdr.next_header);
7874         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7875                  ipv6_frag_ext_v->hdr.next_header &
7876                  ipv6_frag_ext_m->hdr.next_header);
7877 }
7878
7879 /**
7880  * Add TCP item to matcher and to the value.
7881  *
7882  * @param[in, out] matcher
7883  *   Flow matcher.
7884  * @param[in, out] key
7885  *   Flow matcher value.
7886  * @param[in] item
7887  *   Flow pattern to translate.
7888  * @param[in] inner
7889  *   Item is inner pattern.
7890  */
7891 static void
7892 flow_dv_translate_item_tcp(void *matcher, void *key,
7893                            const struct rte_flow_item *item,
7894                            int inner)
7895 {
7896         const struct rte_flow_item_tcp *tcp_m = item->mask;
7897         const struct rte_flow_item_tcp *tcp_v = item->spec;
7898         void *headers_m;
7899         void *headers_v;
7900
7901         if (inner) {
7902                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7903                                          inner_headers);
7904                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7905         } else {
7906                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7907                                          outer_headers);
7908                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7909         }
7910         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7911         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7912         if (!tcp_v)
7913                 return;
7914         if (!tcp_m)
7915                 tcp_m = &rte_flow_item_tcp_mask;
7916         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7917                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7918         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7919                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7920         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7921                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7922         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7923                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7924         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7925                  tcp_m->hdr.tcp_flags);
7926         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7927                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7928 }
7929
7930 /**
7931  * Add UDP item to matcher and to the value.
7932  *
7933  * @param[in, out] matcher
7934  *   Flow matcher.
7935  * @param[in, out] key
7936  *   Flow matcher value.
7937  * @param[in] item
7938  *   Flow pattern to translate.
7939  * @param[in] inner
7940  *   Item is inner pattern.
7941  */
7942 static void
7943 flow_dv_translate_item_udp(void *matcher, void *key,
7944                            const struct rte_flow_item *item,
7945                            int inner)
7946 {
7947         const struct rte_flow_item_udp *udp_m = item->mask;
7948         const struct rte_flow_item_udp *udp_v = item->spec;
7949         void *headers_m;
7950         void *headers_v;
7951
7952         if (inner) {
7953                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7954                                          inner_headers);
7955                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7956         } else {
7957                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7958                                          outer_headers);
7959                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7960         }
7961         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7962         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7963         if (!udp_v)
7964                 return;
7965         if (!udp_m)
7966                 udp_m = &rte_flow_item_udp_mask;
7967         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7968                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7969         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7970                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7971         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7972                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7973         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7974                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7975 }
7976
7977 /**
7978  * Add GRE optional Key item to matcher and to the value.
7979  *
7980  * @param[in, out] matcher
7981  *   Flow matcher.
7982  * @param[in, out] key
7983  *   Flow matcher value.
7984  * @param[in] item
7985  *   Flow pattern to translate.
7986  * @param[in] inner
7987  *   Item is inner pattern.
7988  */
7989 static void
7990 flow_dv_translate_item_gre_key(void *matcher, void *key,
7991                                    const struct rte_flow_item *item)
7992 {
7993         const rte_be32_t *key_m = item->mask;
7994         const rte_be32_t *key_v = item->spec;
7995         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7996         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7997         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7998
7999         /* GRE K bit must be on and should already be validated */
8000         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8001         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8002         if (!key_v)
8003                 return;
8004         if (!key_m)
8005                 key_m = &gre_key_default_mask;
8006         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8007                  rte_be_to_cpu_32(*key_m) >> 8);
8008         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8009                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8010         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8011                  rte_be_to_cpu_32(*key_m) & 0xFF);
8012         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8013                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8014 }
8015
8016 /**
8017  * Add GRE item to matcher and to the value.
8018  *
8019  * @param[in, out] matcher
8020  *   Flow matcher.
8021  * @param[in, out] key
8022  *   Flow matcher value.
8023  * @param[in] item
8024  *   Flow pattern to translate.
8025  * @param[in] inner
8026  *   Item is inner pattern.
8027  */
8028 static void
8029 flow_dv_translate_item_gre(void *matcher, void *key,
8030                            const struct rte_flow_item *item,
8031                            int inner)
8032 {
8033         const struct rte_flow_item_gre *gre_m = item->mask;
8034         const struct rte_flow_item_gre *gre_v = item->spec;
8035         void *headers_m;
8036         void *headers_v;
8037         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8038         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8039         struct {
8040                 union {
8041                         __extension__
8042                         struct {
8043                                 uint16_t version:3;
8044                                 uint16_t rsvd0:9;
8045                                 uint16_t s_present:1;
8046                                 uint16_t k_present:1;
8047                                 uint16_t rsvd_bit1:1;
8048                                 uint16_t c_present:1;
8049                         };
8050                         uint16_t value;
8051                 };
8052         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8053
8054         if (inner) {
8055                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8056                                          inner_headers);
8057                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8058         } else {
8059                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8060                                          outer_headers);
8061                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8062         }
8063         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8064         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8065         if (!gre_v)
8066                 return;
8067         if (!gre_m)
8068                 gre_m = &rte_flow_item_gre_mask;
8069         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8070                  rte_be_to_cpu_16(gre_m->protocol));
8071         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8072                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8073         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8074         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8075         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8076                  gre_crks_rsvd0_ver_m.c_present);
8077         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8078                  gre_crks_rsvd0_ver_v.c_present &
8079                  gre_crks_rsvd0_ver_m.c_present);
8080         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8081                  gre_crks_rsvd0_ver_m.k_present);
8082         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8083                  gre_crks_rsvd0_ver_v.k_present &
8084                  gre_crks_rsvd0_ver_m.k_present);
8085         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8086                  gre_crks_rsvd0_ver_m.s_present);
8087         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8088                  gre_crks_rsvd0_ver_v.s_present &
8089                  gre_crks_rsvd0_ver_m.s_present);
8090 }
8091
8092 /**
8093  * Add NVGRE item to matcher and to the value.
8094  *
8095  * @param[in, out] matcher
8096  *   Flow matcher.
8097  * @param[in, out] key
8098  *   Flow matcher value.
8099  * @param[in] item
8100  *   Flow pattern to translate.
8101  * @param[in] inner
8102  *   Item is inner pattern.
8103  */
8104 static void
8105 flow_dv_translate_item_nvgre(void *matcher, void *key,
8106                              const struct rte_flow_item *item,
8107                              int inner)
8108 {
8109         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8110         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8111         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8112         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8113         const char *tni_flow_id_m;
8114         const char *tni_flow_id_v;
8115         char *gre_key_m;
8116         char *gre_key_v;
8117         int size;
8118         int i;
8119
8120         /* For NVGRE, GRE header fields must be set with defined values. */
8121         const struct rte_flow_item_gre gre_spec = {
8122                 .c_rsvd0_ver = RTE_BE16(0x2000),
8123                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8124         };
8125         const struct rte_flow_item_gre gre_mask = {
8126                 .c_rsvd0_ver = RTE_BE16(0xB000),
8127                 .protocol = RTE_BE16(UINT16_MAX),
8128         };
8129         const struct rte_flow_item gre_item = {
8130                 .spec = &gre_spec,
8131                 .mask = &gre_mask,
8132                 .last = NULL,
8133         };
8134         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8135         if (!nvgre_v)
8136                 return;
8137         if (!nvgre_m)
8138                 nvgre_m = &rte_flow_item_nvgre_mask;
8139         tni_flow_id_m = (const char *)nvgre_m->tni;
8140         tni_flow_id_v = (const char *)nvgre_v->tni;
8141         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8142         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8143         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8144         memcpy(gre_key_m, tni_flow_id_m, size);
8145         for (i = 0; i < size; ++i)
8146                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8147 }
8148
8149 /**
8150  * Add VXLAN item to matcher and to the value.
8151  *
8152  * @param[in, out] matcher
8153  *   Flow matcher.
8154  * @param[in, out] key
8155  *   Flow matcher value.
8156  * @param[in] item
8157  *   Flow pattern to translate.
8158  * @param[in] inner
8159  *   Item is inner pattern.
8160  */
8161 static void
8162 flow_dv_translate_item_vxlan(void *matcher, void *key,
8163                              const struct rte_flow_item *item,
8164                              int inner)
8165 {
8166         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8167         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8168         void *headers_m;
8169         void *headers_v;
8170         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8171         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8172         char *vni_m;
8173         char *vni_v;
8174         uint16_t dport;
8175         int size;
8176         int i;
8177
8178         if (inner) {
8179                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8180                                          inner_headers);
8181                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8182         } else {
8183                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8184                                          outer_headers);
8185                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8186         }
8187         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8188                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8189         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8190                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8191                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8192         }
8193         if (!vxlan_v)
8194                 return;
8195         if (!vxlan_m)
8196                 vxlan_m = &rte_flow_item_vxlan_mask;
8197         size = sizeof(vxlan_m->vni);
8198         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8199         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8200         memcpy(vni_m, vxlan_m->vni, size);
8201         for (i = 0; i < size; ++i)
8202                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8203 }
8204
8205 /**
8206  * Add VXLAN-GPE item to matcher and to the value.
8207  *
8208  * @param[in, out] matcher
8209  *   Flow matcher.
8210  * @param[in, out] key
8211  *   Flow matcher value.
8212  * @param[in] item
8213  *   Flow pattern to translate.
8214  * @param[in] inner
8215  *   Item is inner pattern.
8216  */
8217
8218 static void
8219 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8220                                  const struct rte_flow_item *item, int inner)
8221 {
8222         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8223         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8224         void *headers_m;
8225         void *headers_v;
8226         void *misc_m =
8227                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8228         void *misc_v =
8229                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8230         char *vni_m;
8231         char *vni_v;
8232         uint16_t dport;
8233         int size;
8234         int i;
8235         uint8_t flags_m = 0xff;
8236         uint8_t flags_v = 0xc;
8237
8238         if (inner) {
8239                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8240                                          inner_headers);
8241                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8242         } else {
8243                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8244                                          outer_headers);
8245                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8246         }
8247         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8248                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8249         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8250                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8251                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8252         }
8253         if (!vxlan_v)
8254                 return;
8255         if (!vxlan_m)
8256                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8257         size = sizeof(vxlan_m->vni);
8258         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8259         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8260         memcpy(vni_m, vxlan_m->vni, size);
8261         for (i = 0; i < size; ++i)
8262                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8263         if (vxlan_m->flags) {
8264                 flags_m = vxlan_m->flags;
8265                 flags_v = vxlan_v->flags;
8266         }
8267         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8268         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8269         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8270                  vxlan_m->protocol);
8271         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8272                  vxlan_v->protocol);
8273 }
8274
8275 /**
8276  * Add Geneve item to matcher and to the value.
8277  *
8278  * @param[in, out] matcher
8279  *   Flow matcher.
8280  * @param[in, out] key
8281  *   Flow matcher value.
8282  * @param[in] item
8283  *   Flow pattern to translate.
8284  * @param[in] inner
8285  *   Item is inner pattern.
8286  */
8287
8288 static void
8289 flow_dv_translate_item_geneve(void *matcher, void *key,
8290                               const struct rte_flow_item *item, int inner)
8291 {
8292         const struct rte_flow_item_geneve *geneve_m = item->mask;
8293         const struct rte_flow_item_geneve *geneve_v = item->spec;
8294         void *headers_m;
8295         void *headers_v;
8296         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8297         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8298         uint16_t dport;
8299         uint16_t gbhdr_m;
8300         uint16_t gbhdr_v;
8301         char *vni_m;
8302         char *vni_v;
8303         size_t size, i;
8304
8305         if (inner) {
8306                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8307                                          inner_headers);
8308                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8309         } else {
8310                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8311                                          outer_headers);
8312                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8313         }
8314         dport = MLX5_UDP_PORT_GENEVE;
8315         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8316                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8317                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8318         }
8319         if (!geneve_v)
8320                 return;
8321         if (!geneve_m)
8322                 geneve_m = &rte_flow_item_geneve_mask;
8323         size = sizeof(geneve_m->vni);
8324         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8325         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8326         memcpy(vni_m, geneve_m->vni, size);
8327         for (i = 0; i < size; ++i)
8328                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8329         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8330                  rte_be_to_cpu_16(geneve_m->protocol));
8331         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8332                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8333         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8334         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8335         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8336                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8337         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8338                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8339         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8340                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8341         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8342                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8343                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8344 }
8345
8346 /**
8347  * Create Geneve TLV option resource.
8348  *
8349  * @param dev[in, out]
8350  *   Pointer to rte_eth_dev structure.
8351  * @param[in, out] tag_be24
8352  *   Tag value in big endian then R-shift 8.
8353  * @parm[in, out] dev_flow
8354  *   Pointer to the dev_flow.
8355  * @param[out] error
8356  *   pointer to error structure.
8357  *
8358  * @return
8359  *   0 on success otherwise -errno and errno is set.
8360  */
8361
8362 int
8363 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8364                                              const struct rte_flow_item *item,
8365                                              struct rte_flow_error *error)
8366 {
8367         struct mlx5_priv *priv = dev->data->dev_private;
8368         struct mlx5_dev_ctx_shared *sh = priv->sh;
8369         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8370                         sh->geneve_tlv_option_resource;
8371         struct mlx5_devx_obj *obj;
8372         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8373         int ret = 0;
8374
8375         if (!geneve_opt_v)
8376                 return -1;
8377         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8378         if (geneve_opt_resource != NULL) {
8379                 if (geneve_opt_resource->option_class ==
8380                         geneve_opt_v->option_class &&
8381                         geneve_opt_resource->option_type ==
8382                         geneve_opt_v->option_type &&
8383                         geneve_opt_resource->length ==
8384                         geneve_opt_v->option_len) {
8385                         /* We already have GENVE TLV option obj allocated. */
8386                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8387                                            __ATOMIC_RELAXED);
8388                 } else {
8389                         ret = rte_flow_error_set(error, ENOMEM,
8390                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8391                                 "Only one GENEVE TLV option supported");
8392                         goto exit;
8393                 }
8394         } else {
8395                 /* Create a GENEVE TLV object and resource. */
8396                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8397                                 geneve_opt_v->option_class,
8398                                 geneve_opt_v->option_type,
8399                                 geneve_opt_v->option_len);
8400                 if (!obj) {
8401                         ret = rte_flow_error_set(error, ENODATA,
8402                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8403                                 "Failed to create GENEVE TLV Devx object");
8404                         goto exit;
8405                 }
8406                 sh->geneve_tlv_option_resource =
8407                                 mlx5_malloc(MLX5_MEM_ZERO,
8408                                                 sizeof(*geneve_opt_resource),
8409                                                 0, SOCKET_ID_ANY);
8410                 if (!sh->geneve_tlv_option_resource) {
8411                         claim_zero(mlx5_devx_cmd_destroy(obj));
8412                         ret = rte_flow_error_set(error, ENOMEM,
8413                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8414                                 "GENEVE TLV object memory allocation failed");
8415                         goto exit;
8416                 }
8417                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8418                 geneve_opt_resource->obj = obj;
8419                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8420                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8421                 geneve_opt_resource->length = geneve_opt_v->option_len;
8422                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8423                                 __ATOMIC_RELAXED);
8424         }
8425 exit:
8426         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8427         return ret;
8428 }
8429
8430 /**
8431  * Add Geneve TLV option item to matcher.
8432  *
8433  * @param[in, out] dev
8434  *   Pointer to rte_eth_dev structure.
8435  * @param[in, out] matcher
8436  *   Flow matcher.
8437  * @param[in, out] key
8438  *   Flow matcher value.
8439  * @param[in] item
8440  *   Flow pattern to translate.
8441  * @param[out] error
8442  *   Pointer to error structure.
8443  */
8444 static int
8445 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8446                                   void *key, const struct rte_flow_item *item,
8447                                   struct rte_flow_error *error)
8448 {
8449         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8450         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8451         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8452         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8453         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8454                         misc_parameters_3);
8455         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8456         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8457         int ret = 0;
8458
8459         if (!geneve_opt_v)
8460                 return -1;
8461         if (!geneve_opt_m)
8462                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8463         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8464                                                            error);
8465         if (ret) {
8466                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8467                 return ret;
8468         }
8469         /*
8470          * Set the option length in GENEVE header if not requested.
8471          * The GENEVE TLV option length is expressed by the option length field
8472          * in the GENEVE header.
8473          * If the option length was not requested but the GENEVE TLV option item
8474          * is present we set the option length field implicitly.
8475          */
8476         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8477                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8478                          MLX5_GENEVE_OPTLEN_MASK);
8479                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8480                          geneve_opt_v->option_len + 1);
8481         }
8482         /* Set the data. */
8483         if (geneve_opt_v->data) {
8484                 memcpy(&opt_data_key, geneve_opt_v->data,
8485                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8486                                 sizeof(opt_data_key)));
8487                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8488                                 sizeof(opt_data_key));
8489                 memcpy(&opt_data_mask, geneve_opt_m->data,
8490                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8491                                 sizeof(opt_data_mask)));
8492                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8493                                 sizeof(opt_data_mask));
8494                 MLX5_SET(fte_match_set_misc3, misc3_m,
8495                                 geneve_tlv_option_0_data,
8496                                 rte_be_to_cpu_32(opt_data_mask));
8497                 MLX5_SET(fte_match_set_misc3, misc3_v,
8498                                 geneve_tlv_option_0_data,
8499                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8500         }
8501         return ret;
8502 }
8503
8504 /**
8505  * Add MPLS item to matcher and to the value.
8506  *
8507  * @param[in, out] matcher
8508  *   Flow matcher.
8509  * @param[in, out] key
8510  *   Flow matcher value.
8511  * @param[in] item
8512  *   Flow pattern to translate.
8513  * @param[in] prev_layer
8514  *   The protocol layer indicated in previous item.
8515  * @param[in] inner
8516  *   Item is inner pattern.
8517  */
8518 static void
8519 flow_dv_translate_item_mpls(void *matcher, void *key,
8520                             const struct rte_flow_item *item,
8521                             uint64_t prev_layer,
8522                             int inner)
8523 {
8524         const uint32_t *in_mpls_m = item->mask;
8525         const uint32_t *in_mpls_v = item->spec;
8526         uint32_t *out_mpls_m = 0;
8527         uint32_t *out_mpls_v = 0;
8528         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8529         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8530         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8531                                      misc_parameters_2);
8532         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8533         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8534         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8535
8536         switch (prev_layer) {
8537         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8538                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8539                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8540                          MLX5_UDP_PORT_MPLS);
8541                 break;
8542         case MLX5_FLOW_LAYER_GRE:
8543                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8544                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8545                          RTE_ETHER_TYPE_MPLS);
8546                 break;
8547         default:
8548                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8549                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8550                          IPPROTO_MPLS);
8551                 break;
8552         }
8553         if (!in_mpls_v)
8554                 return;
8555         if (!in_mpls_m)
8556                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8557         switch (prev_layer) {
8558         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8559                 out_mpls_m =
8560                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8561                                                  outer_first_mpls_over_udp);
8562                 out_mpls_v =
8563                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8564                                                  outer_first_mpls_over_udp);
8565                 break;
8566         case MLX5_FLOW_LAYER_GRE:
8567                 out_mpls_m =
8568                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8569                                                  outer_first_mpls_over_gre);
8570                 out_mpls_v =
8571                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8572                                                  outer_first_mpls_over_gre);
8573                 break;
8574         default:
8575                 /* Inner MPLS not over GRE is not supported. */
8576                 if (!inner) {
8577                         out_mpls_m =
8578                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8579                                                          misc2_m,
8580                                                          outer_first_mpls);
8581                         out_mpls_v =
8582                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8583                                                          misc2_v,
8584                                                          outer_first_mpls);
8585                 }
8586                 break;
8587         }
8588         if (out_mpls_m && out_mpls_v) {
8589                 *out_mpls_m = *in_mpls_m;
8590                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8591         }
8592 }
8593
8594 /**
8595  * Add metadata register item to matcher
8596  *
8597  * @param[in, out] matcher
8598  *   Flow matcher.
8599  * @param[in, out] key
8600  *   Flow matcher value.
8601  * @param[in] reg_type
8602  *   Type of device metadata register
8603  * @param[in] value
8604  *   Register value
8605  * @param[in] mask
8606  *   Register mask
8607  */
8608 static void
8609 flow_dv_match_meta_reg(void *matcher, void *key,
8610                        enum modify_reg reg_type,
8611                        uint32_t data, uint32_t mask)
8612 {
8613         void *misc2_m =
8614                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8615         void *misc2_v =
8616                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8617         uint32_t temp;
8618
8619         data &= mask;
8620         switch (reg_type) {
8621         case REG_A:
8622                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8623                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8624                 break;
8625         case REG_B:
8626                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8627                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8628                 break;
8629         case REG_C_0:
8630                 /*
8631                  * The metadata register C0 field might be divided into
8632                  * source vport index and META item value, we should set
8633                  * this field according to specified mask, not as whole one.
8634                  */
8635                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8636                 temp |= mask;
8637                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8638                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8639                 temp &= ~mask;
8640                 temp |= data;
8641                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8642                 break;
8643         case REG_C_1:
8644                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8645                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8646                 break;
8647         case REG_C_2:
8648                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8649                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8650                 break;
8651         case REG_C_3:
8652                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8653                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8654                 break;
8655         case REG_C_4:
8656                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8657                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8658                 break;
8659         case REG_C_5:
8660                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8661                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8662                 break;
8663         case REG_C_6:
8664                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8665                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8666                 break;
8667         case REG_C_7:
8668                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8669                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8670                 break;
8671         default:
8672                 MLX5_ASSERT(false);
8673                 break;
8674         }
8675 }
8676
8677 /**
8678  * Add MARK item to matcher
8679  *
8680  * @param[in] dev
8681  *   The device to configure through.
8682  * @param[in, out] matcher
8683  *   Flow matcher.
8684  * @param[in, out] key
8685  *   Flow matcher value.
8686  * @param[in] item
8687  *   Flow pattern to translate.
8688  */
8689 static void
8690 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8691                             void *matcher, void *key,
8692                             const struct rte_flow_item *item)
8693 {
8694         struct mlx5_priv *priv = dev->data->dev_private;
8695         const struct rte_flow_item_mark *mark;
8696         uint32_t value;
8697         uint32_t mask;
8698
8699         mark = item->mask ? (const void *)item->mask :
8700                             &rte_flow_item_mark_mask;
8701         mask = mark->id & priv->sh->dv_mark_mask;
8702         mark = (const void *)item->spec;
8703         MLX5_ASSERT(mark);
8704         value = mark->id & priv->sh->dv_mark_mask & mask;
8705         if (mask) {
8706                 enum modify_reg reg;
8707
8708                 /* Get the metadata register index for the mark. */
8709                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8710                 MLX5_ASSERT(reg > 0);
8711                 if (reg == REG_C_0) {
8712                         struct mlx5_priv *priv = dev->data->dev_private;
8713                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8714                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8715
8716                         mask &= msk_c0;
8717                         mask <<= shl_c0;
8718                         value <<= shl_c0;
8719                 }
8720                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8721         }
8722 }
8723
8724 /**
8725  * Add META item to matcher
8726  *
8727  * @param[in] dev
8728  *   The devich to configure through.
8729  * @param[in, out] matcher
8730  *   Flow matcher.
8731  * @param[in, out] key
8732  *   Flow matcher value.
8733  * @param[in] attr
8734  *   Attributes of flow that includes this item.
8735  * @param[in] item
8736  *   Flow pattern to translate.
8737  */
8738 static void
8739 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8740                             void *matcher, void *key,
8741                             const struct rte_flow_attr *attr,
8742                             const struct rte_flow_item *item)
8743 {
8744         const struct rte_flow_item_meta *meta_m;
8745         const struct rte_flow_item_meta *meta_v;
8746
8747         meta_m = (const void *)item->mask;
8748         if (!meta_m)
8749                 meta_m = &rte_flow_item_meta_mask;
8750         meta_v = (const void *)item->spec;
8751         if (meta_v) {
8752                 int reg;
8753                 uint32_t value = meta_v->data;
8754                 uint32_t mask = meta_m->data;
8755
8756                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8757                 if (reg < 0)
8758                         return;
8759                 MLX5_ASSERT(reg != REG_NON);
8760                 /*
8761                  * In datapath code there is no endianness
8762                  * coversions for perfromance reasons, all
8763                  * pattern conversions are done in rte_flow.
8764                  */
8765                 value = rte_cpu_to_be_32(value);
8766                 mask = rte_cpu_to_be_32(mask);
8767                 if (reg == REG_C_0) {
8768                         struct mlx5_priv *priv = dev->data->dev_private;
8769                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8770                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8771 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8772                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8773
8774                         value >>= shr_c0;
8775                         mask >>= shr_c0;
8776 #endif
8777                         value <<= shl_c0;
8778                         mask <<= shl_c0;
8779                         MLX5_ASSERT(msk_c0);
8780                         MLX5_ASSERT(!(~msk_c0 & mask));
8781                 }
8782                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8783         }
8784 }
8785
8786 /**
8787  * Add vport metadata Reg C0 item to matcher
8788  *
8789  * @param[in, out] matcher
8790  *   Flow matcher.
8791  * @param[in, out] key
8792  *   Flow matcher value.
8793  * @param[in] reg
8794  *   Flow pattern to translate.
8795  */
8796 static void
8797 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8798                                   uint32_t value, uint32_t mask)
8799 {
8800         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8801 }
8802
8803 /**
8804  * Add tag item to matcher
8805  *
8806  * @param[in] dev
8807  *   The devich to configure through.
8808  * @param[in, out] matcher
8809  *   Flow matcher.
8810  * @param[in, out] key
8811  *   Flow matcher value.
8812  * @param[in] item
8813  *   Flow pattern to translate.
8814  */
8815 static void
8816 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8817                                 void *matcher, void *key,
8818                                 const struct rte_flow_item *item)
8819 {
8820         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8821         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8822         uint32_t mask, value;
8823
8824         MLX5_ASSERT(tag_v);
8825         value = tag_v->data;
8826         mask = tag_m ? tag_m->data : UINT32_MAX;
8827         if (tag_v->id == REG_C_0) {
8828                 struct mlx5_priv *priv = dev->data->dev_private;
8829                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8830                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8831
8832                 mask &= msk_c0;
8833                 mask <<= shl_c0;
8834                 value <<= shl_c0;
8835         }
8836         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8837 }
8838
8839 /**
8840  * Add TAG item to matcher
8841  *
8842  * @param[in] dev
8843  *   The devich to configure through.
8844  * @param[in, out] matcher
8845  *   Flow matcher.
8846  * @param[in, out] key
8847  *   Flow matcher value.
8848  * @param[in] item
8849  *   Flow pattern to translate.
8850  */
8851 static void
8852 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8853                            void *matcher, void *key,
8854                            const struct rte_flow_item *item)
8855 {
8856         const struct rte_flow_item_tag *tag_v = item->spec;
8857         const struct rte_flow_item_tag *tag_m = item->mask;
8858         enum modify_reg reg;
8859
8860         MLX5_ASSERT(tag_v);
8861         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8862         /* Get the metadata register index for the tag. */
8863         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8864         MLX5_ASSERT(reg > 0);
8865         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8866 }
8867
8868 /**
8869  * Add source vport match to the specified matcher.
8870  *
8871  * @param[in, out] matcher
8872  *   Flow matcher.
8873  * @param[in, out] key
8874  *   Flow matcher value.
8875  * @param[in] port
8876  *   Source vport value to match
8877  * @param[in] mask
8878  *   Mask
8879  */
8880 static void
8881 flow_dv_translate_item_source_vport(void *matcher, void *key,
8882                                     int16_t port, uint16_t mask)
8883 {
8884         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8885         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8886
8887         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8888         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8889 }
8890
8891 /**
8892  * Translate port-id item to eswitch match on  port-id.
8893  *
8894  * @param[in] dev
8895  *   The devich to configure through.
8896  * @param[in, out] matcher
8897  *   Flow matcher.
8898  * @param[in, out] key
8899  *   Flow matcher value.
8900  * @param[in] item
8901  *   Flow pattern to translate.
8902  * @param[in]
8903  *   Flow attributes.
8904  *
8905  * @return
8906  *   0 on success, a negative errno value otherwise.
8907  */
8908 static int
8909 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8910                                void *key, const struct rte_flow_item *item,
8911                                const struct rte_flow_attr *attr)
8912 {
8913         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8914         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8915         struct mlx5_priv *priv;
8916         uint16_t mask, id;
8917
8918         mask = pid_m ? pid_m->id : 0xffff;
8919         id = pid_v ? pid_v->id : dev->data->port_id;
8920         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8921         if (!priv)
8922                 return -rte_errno;
8923         /*
8924          * Translate to vport field or to metadata, depending on mode.
8925          * Kernel can use either misc.source_port or half of C0 metadata
8926          * register.
8927          */
8928         if (priv->vport_meta_mask) {
8929                 /*
8930                  * Provide the hint for SW steering library
8931                  * to insert the flow into ingress domain and
8932                  * save the extra vport match.
8933                  */
8934                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8935                     priv->pf_bond < 0 && attr->transfer)
8936                         flow_dv_translate_item_source_vport
8937                                 (matcher, key, priv->vport_id, mask);
8938                 /*
8939                  * We should always set the vport metadata register,
8940                  * otherwise the SW steering library can drop
8941                  * the rule if wire vport metadata value is not zero,
8942                  * it depends on kernel configuration.
8943                  */
8944                 flow_dv_translate_item_meta_vport(matcher, key,
8945                                                   priv->vport_meta_tag,
8946                                                   priv->vport_meta_mask);
8947         } else {
8948                 flow_dv_translate_item_source_vport(matcher, key,
8949                                                     priv->vport_id, mask);
8950         }
8951         return 0;
8952 }
8953
8954 /**
8955  * Add ICMP6 item to matcher and to the value.
8956  *
8957  * @param[in, out] matcher
8958  *   Flow matcher.
8959  * @param[in, out] key
8960  *   Flow matcher value.
8961  * @param[in] item
8962  *   Flow pattern to translate.
8963  * @param[in] inner
8964  *   Item is inner pattern.
8965  */
8966 static void
8967 flow_dv_translate_item_icmp6(void *matcher, void *key,
8968                               const struct rte_flow_item *item,
8969                               int inner)
8970 {
8971         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8972         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8973         void *headers_m;
8974         void *headers_v;
8975         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8976                                      misc_parameters_3);
8977         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8978         if (inner) {
8979                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8980                                          inner_headers);
8981                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8982         } else {
8983                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8984                                          outer_headers);
8985                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8986         }
8987         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8988         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8989         if (!icmp6_v)
8990                 return;
8991         if (!icmp6_m)
8992                 icmp6_m = &rte_flow_item_icmp6_mask;
8993         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8994         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8995                  icmp6_v->type & icmp6_m->type);
8996         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8997         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8998                  icmp6_v->code & icmp6_m->code);
8999 }
9000
9001 /**
9002  * Add ICMP item to matcher and to the value.
9003  *
9004  * @param[in, out] matcher
9005  *   Flow matcher.
9006  * @param[in, out] key
9007  *   Flow matcher value.
9008  * @param[in] item
9009  *   Flow pattern to translate.
9010  * @param[in] inner
9011  *   Item is inner pattern.
9012  */
9013 static void
9014 flow_dv_translate_item_icmp(void *matcher, void *key,
9015                             const struct rte_flow_item *item,
9016                             int inner)
9017 {
9018         const struct rte_flow_item_icmp *icmp_m = item->mask;
9019         const struct rte_flow_item_icmp *icmp_v = item->spec;
9020         uint32_t icmp_header_data_m = 0;
9021         uint32_t icmp_header_data_v = 0;
9022         void *headers_m;
9023         void *headers_v;
9024         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9025                                      misc_parameters_3);
9026         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9027         if (inner) {
9028                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9029                                          inner_headers);
9030                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9031         } else {
9032                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9033                                          outer_headers);
9034                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9035         }
9036         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9037         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9038         if (!icmp_v)
9039                 return;
9040         if (!icmp_m)
9041                 icmp_m = &rte_flow_item_icmp_mask;
9042         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9043                  icmp_m->hdr.icmp_type);
9044         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9045                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9046         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9047                  icmp_m->hdr.icmp_code);
9048         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9049                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9050         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9051         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9052         if (icmp_header_data_m) {
9053                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9054                 icmp_header_data_v |=
9055                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9056                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9057                          icmp_header_data_m);
9058                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9059                          icmp_header_data_v & icmp_header_data_m);
9060         }
9061 }
9062
9063 /**
9064  * Add GTP item to matcher and to the value.
9065  *
9066  * @param[in, out] matcher
9067  *   Flow matcher.
9068  * @param[in, out] key
9069  *   Flow matcher value.
9070  * @param[in] item
9071  *   Flow pattern to translate.
9072  * @param[in] inner
9073  *   Item is inner pattern.
9074  */
9075 static void
9076 flow_dv_translate_item_gtp(void *matcher, void *key,
9077                            const struct rte_flow_item *item, int inner)
9078 {
9079         const struct rte_flow_item_gtp *gtp_m = item->mask;
9080         const struct rte_flow_item_gtp *gtp_v = item->spec;
9081         void *headers_m;
9082         void *headers_v;
9083         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9084                                      misc_parameters_3);
9085         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9086         uint16_t dport = RTE_GTPU_UDP_PORT;
9087
9088         if (inner) {
9089                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9090                                          inner_headers);
9091                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9092         } else {
9093                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9094                                          outer_headers);
9095                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9096         }
9097         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9098                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9099                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9100         }
9101         if (!gtp_v)
9102                 return;
9103         if (!gtp_m)
9104                 gtp_m = &rte_flow_item_gtp_mask;
9105         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9106                  gtp_m->v_pt_rsv_flags);
9107         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9108                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9109         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9110         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9111                  gtp_v->msg_type & gtp_m->msg_type);
9112         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9113                  rte_be_to_cpu_32(gtp_m->teid));
9114         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9115                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9116 }
9117
9118 /**
9119  * Add GTP PSC item to matcher.
9120  *
9121  * @param[in, out] matcher
9122  *   Flow matcher.
9123  * @param[in, out] key
9124  *   Flow matcher value.
9125  * @param[in] item
9126  *   Flow pattern to translate.
9127  */
9128 static int
9129 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9130                                const struct rte_flow_item *item)
9131 {
9132         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9133         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9134         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9135                         misc_parameters_3);
9136         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9137         union {
9138                 uint32_t w32;
9139                 struct {
9140                         uint16_t seq_num;
9141                         uint8_t npdu_num;
9142                         uint8_t next_ext_header_type;
9143                 };
9144         } dw_2;
9145         uint8_t gtp_flags;
9146
9147         /* Always set E-flag match on one, regardless of GTP item settings. */
9148         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9149         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9150         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9151         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9152         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9153         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9154         /*Set next extension header type. */
9155         dw_2.seq_num = 0;
9156         dw_2.npdu_num = 0;
9157         dw_2.next_ext_header_type = 0xff;
9158         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9159                  rte_cpu_to_be_32(dw_2.w32));
9160         dw_2.seq_num = 0;
9161         dw_2.npdu_num = 0;
9162         dw_2.next_ext_header_type = 0x85;
9163         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9164                  rte_cpu_to_be_32(dw_2.w32));
9165         if (gtp_psc_v) {
9166                 union {
9167                         uint32_t w32;
9168                         struct {
9169                                 uint8_t len;
9170                                 uint8_t type_flags;
9171                                 uint8_t qfi;
9172                                 uint8_t reserved;
9173                         };
9174                 } dw_0;
9175
9176                 /*Set extension header PDU type and Qos. */
9177                 if (!gtp_psc_m)
9178                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9179                 dw_0.w32 = 0;
9180                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9181                 dw_0.qfi = gtp_psc_m->qfi;
9182                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9183                          rte_cpu_to_be_32(dw_0.w32));
9184                 dw_0.w32 = 0;
9185                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9186                                                         gtp_psc_m->pdu_type);
9187                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9188                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9189                          rte_cpu_to_be_32(dw_0.w32));
9190         }
9191         return 0;
9192 }
9193
9194 /**
9195  * Add eCPRI item to matcher and to the value.
9196  *
9197  * @param[in] dev
9198  *   The devich to configure through.
9199  * @param[in, out] matcher
9200  *   Flow matcher.
9201  * @param[in, out] key
9202  *   Flow matcher value.
9203  * @param[in] item
9204  *   Flow pattern to translate.
9205  * @param[in] samples
9206  *   Sample IDs to be used in the matching.
9207  */
9208 static void
9209 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9210                              void *key, const struct rte_flow_item *item)
9211 {
9212         struct mlx5_priv *priv = dev->data->dev_private;
9213         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9214         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9215         struct rte_ecpri_common_hdr common;
9216         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9217                                      misc_parameters_4);
9218         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9219         uint32_t *samples;
9220         void *dw_m;
9221         void *dw_v;
9222
9223         if (!ecpri_v)
9224                 return;
9225         if (!ecpri_m)
9226                 ecpri_m = &rte_flow_item_ecpri_mask;
9227         /*
9228          * Maximal four DW samples are supported in a single matching now.
9229          * Two are used now for a eCPRI matching:
9230          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9231          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9232          *    if any.
9233          */
9234         if (!ecpri_m->hdr.common.u32)
9235                 return;
9236         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9237         /* Need to take the whole DW as the mask to fill the entry. */
9238         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9239                             prog_sample_field_value_0);
9240         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9241                             prog_sample_field_value_0);
9242         /* Already big endian (network order) in the header. */
9243         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9244         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9245         /* Sample#0, used for matching type, offset 0. */
9246         MLX5_SET(fte_match_set_misc4, misc4_m,
9247                  prog_sample_field_id_0, samples[0]);
9248         /* It makes no sense to set the sample ID in the mask field. */
9249         MLX5_SET(fte_match_set_misc4, misc4_v,
9250                  prog_sample_field_id_0, samples[0]);
9251         /*
9252          * Checking if message body part needs to be matched.
9253          * Some wildcard rules only matching type field should be supported.
9254          */
9255         if (ecpri_m->hdr.dummy[0]) {
9256                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9257                 switch (common.type) {
9258                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9259                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9260                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9261                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9262                                             prog_sample_field_value_1);
9263                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9264                                             prog_sample_field_value_1);
9265                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9266                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9267                                             ecpri_m->hdr.dummy[0];
9268                         /* Sample#1, to match message body, offset 4. */
9269                         MLX5_SET(fte_match_set_misc4, misc4_m,
9270                                  prog_sample_field_id_1, samples[1]);
9271                         MLX5_SET(fte_match_set_misc4, misc4_v,
9272                                  prog_sample_field_id_1, samples[1]);
9273                         break;
9274                 default:
9275                         /* Others, do not match any sample ID. */
9276                         break;
9277                 }
9278         }
9279 }
9280
9281 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9282
9283 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9284         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9285                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9286
9287 /**
9288  * Calculate flow matcher enable bitmap.
9289  *
9290  * @param match_criteria
9291  *   Pointer to flow matcher criteria.
9292  *
9293  * @return
9294  *   Bitmap of enabled fields.
9295  */
9296 static uint8_t
9297 flow_dv_matcher_enable(uint32_t *match_criteria)
9298 {
9299         uint8_t match_criteria_enable;
9300
9301         match_criteria_enable =
9302                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9303                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9304         match_criteria_enable |=
9305                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9306                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9307         match_criteria_enable |=
9308                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9309                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9310         match_criteria_enable |=
9311                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9312                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9313         match_criteria_enable |=
9314                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9315                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9316         match_criteria_enable |=
9317                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9318                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9319         return match_criteria_enable;
9320 }
9321
9322 struct mlx5_hlist_entry *
9323 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9324 {
9325         struct mlx5_dev_ctx_shared *sh = list->ctx;
9326         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9327         struct rte_eth_dev *dev = ctx->dev;
9328         struct mlx5_flow_tbl_data_entry *tbl_data;
9329         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9330         struct rte_flow_error *error = ctx->error;
9331         union mlx5_flow_tbl_key key = { .v64 = key64 };
9332         struct mlx5_flow_tbl_resource *tbl;
9333         void *domain;
9334         uint32_t idx = 0;
9335         int ret;
9336
9337         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9338         if (!tbl_data) {
9339                 rte_flow_error_set(error, ENOMEM,
9340                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9341                                    NULL,
9342                                    "cannot allocate flow table data entry");
9343                 return NULL;
9344         }
9345         tbl_data->idx = idx;
9346         tbl_data->tunnel = tt_prm->tunnel;
9347         tbl_data->group_id = tt_prm->group_id;
9348         tbl_data->external = !!tt_prm->external;
9349         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9350         tbl_data->is_egress = !!key.direction;
9351         tbl_data->is_transfer = !!key.domain;
9352         tbl_data->dummy = !!key.dummy;
9353         tbl_data->table_id = key.table_id;
9354         tbl = &tbl_data->tbl;
9355         if (key.dummy)
9356                 return &tbl_data->entry;
9357         if (key.domain)
9358                 domain = sh->fdb_domain;
9359         else if (key.direction)
9360                 domain = sh->tx_domain;
9361         else
9362                 domain = sh->rx_domain;
9363         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9364         if (ret) {
9365                 rte_flow_error_set(error, ENOMEM,
9366                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9367                                    NULL, "cannot create flow table object");
9368                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9369                 return NULL;
9370         }
9371         if (key.table_id) {
9372                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9373                                         (tbl->obj, &tbl_data->jump.action);
9374                 if (ret) {
9375                         rte_flow_error_set(error, ENOMEM,
9376                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9377                                            NULL,
9378                                            "cannot create flow jump action");
9379                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9380                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9381                         return NULL;
9382                 }
9383         }
9384         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9385               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9386               key.table_id);
9387         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9388                              flow_dv_matcher_create_cb,
9389                              flow_dv_matcher_match_cb,
9390                              flow_dv_matcher_remove_cb);
9391         return &tbl_data->entry;
9392 }
9393
9394 int
9395 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9396                      struct mlx5_hlist_entry *entry, uint64_t key64,
9397                      void *cb_ctx __rte_unused)
9398 {
9399         struct mlx5_flow_tbl_data_entry *tbl_data =
9400                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9401         union mlx5_flow_tbl_key key = { .v64 = key64 };
9402
9403         return tbl_data->table_id != key.table_id ||
9404                tbl_data->dummy != key.dummy ||
9405                tbl_data->is_transfer != key.domain ||
9406                tbl_data->is_egress != key.direction;
9407 }
9408
9409 /**
9410  * Get a flow table.
9411  *
9412  * @param[in, out] dev
9413  *   Pointer to rte_eth_dev structure.
9414  * @param[in] table_id
9415  *   Table id to use.
9416  * @param[in] egress
9417  *   Direction of the table.
9418  * @param[in] transfer
9419  *   E-Switch or NIC flow.
9420  * @param[in] dummy
9421  *   Dummy entry for dv API.
9422  * @param[out] error
9423  *   pointer to error structure.
9424  *
9425  * @return
9426  *   Returns tables resource based on the index, NULL in case of failed.
9427  */
9428 struct mlx5_flow_tbl_resource *
9429 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9430                          uint32_t table_id, uint8_t egress,
9431                          uint8_t transfer,
9432                          bool external,
9433                          const struct mlx5_flow_tunnel *tunnel,
9434                          uint32_t group_id, uint8_t dummy,
9435                          struct rte_flow_error *error)
9436 {
9437         struct mlx5_priv *priv = dev->data->dev_private;
9438         union mlx5_flow_tbl_key table_key = {
9439                 {
9440                         .table_id = table_id,
9441                         .dummy = dummy,
9442                         .domain = !!transfer,
9443                         .direction = !!egress,
9444                 }
9445         };
9446         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9447                 .tunnel = tunnel,
9448                 .group_id = group_id,
9449                 .external = external,
9450         };
9451         struct mlx5_flow_cb_ctx ctx = {
9452                 .dev = dev,
9453                 .error = error,
9454                 .data = &tt_prm,
9455         };
9456         struct mlx5_hlist_entry *entry;
9457         struct mlx5_flow_tbl_data_entry *tbl_data;
9458
9459         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9460         if (!entry) {
9461                 rte_flow_error_set(error, ENOMEM,
9462                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9463                                    "cannot get table");
9464                 return NULL;
9465         }
9466         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9467                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9468         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9469         return &tbl_data->tbl;
9470 }
9471
9472 void
9473 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9474                       struct mlx5_hlist_entry *entry)
9475 {
9476         struct mlx5_dev_ctx_shared *sh = list->ctx;
9477         struct mlx5_flow_tbl_data_entry *tbl_data =
9478                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9479
9480         MLX5_ASSERT(entry && sh);
9481         if (tbl_data->jump.action)
9482                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9483         if (tbl_data->tbl.obj)
9484                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9485         if (tbl_data->tunnel_offload && tbl_data->external) {
9486                 struct mlx5_hlist_entry *he;
9487                 struct mlx5_hlist *tunnel_grp_hash;
9488                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9489                 union tunnel_tbl_key tunnel_key = {
9490                         .tunnel_id = tbl_data->tunnel ?
9491                                         tbl_data->tunnel->tunnel_id : 0,
9492                         .group = tbl_data->group_id
9493                 };
9494                 uint32_t table_id = tbl_data->table_id;
9495
9496                 tunnel_grp_hash = tbl_data->tunnel ?
9497                                         tbl_data->tunnel->groups :
9498                                         thub->groups;
9499                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9500                 if (he)
9501                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9502                 DRV_LOG(DEBUG,
9503                         "Table_id %u tunnel %u group %u released.",
9504                         table_id,
9505                         tbl_data->tunnel ?
9506                         tbl_data->tunnel->tunnel_id : 0,
9507                         tbl_data->group_id);
9508         }
9509         mlx5_cache_list_destroy(&tbl_data->matchers);
9510         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9511 }
9512
9513 /**
9514  * Release a flow table.
9515  *
9516  * @param[in] sh
9517  *   Pointer to device shared structure.
9518  * @param[in] tbl
9519  *   Table resource to be released.
9520  *
9521  * @return
9522  *   Returns 0 if table was released, else return 1;
9523  */
9524 static int
9525 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9526                              struct mlx5_flow_tbl_resource *tbl)
9527 {
9528         struct mlx5_flow_tbl_data_entry *tbl_data =
9529                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9530
9531         if (!tbl)
9532                 return 0;
9533         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9534 }
9535
9536 int
9537 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9538                          struct mlx5_cache_entry *entry, void *cb_ctx)
9539 {
9540         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9541         struct mlx5_flow_dv_matcher *ref = ctx->data;
9542         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9543                                                         entry);
9544
9545         return cur->crc != ref->crc ||
9546                cur->priority != ref->priority ||
9547                memcmp((const void *)cur->mask.buf,
9548                       (const void *)ref->mask.buf, ref->mask.size);
9549 }
9550
9551 struct mlx5_cache_entry *
9552 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9553                           struct mlx5_cache_entry *entry __rte_unused,
9554                           void *cb_ctx)
9555 {
9556         struct mlx5_dev_ctx_shared *sh = list->ctx;
9557         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9558         struct mlx5_flow_dv_matcher *ref = ctx->data;
9559         struct mlx5_flow_dv_matcher *cache;
9560         struct mlx5dv_flow_matcher_attr dv_attr = {
9561                 .type = IBV_FLOW_ATTR_NORMAL,
9562                 .match_mask = (void *)&ref->mask,
9563         };
9564         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9565                                                             typeof(*tbl), tbl);
9566         int ret;
9567
9568         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9569         if (!cache) {
9570                 rte_flow_error_set(ctx->error, ENOMEM,
9571                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9572                                    "cannot create matcher");
9573                 return NULL;
9574         }
9575         *cache = *ref;
9576         dv_attr.match_criteria_enable =
9577                 flow_dv_matcher_enable(cache->mask.buf);
9578         dv_attr.priority = ref->priority;
9579         if (tbl->is_egress)
9580                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9581         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9582                                                &cache->matcher_object);
9583         if (ret) {
9584                 mlx5_free(cache);
9585                 rte_flow_error_set(ctx->error, ENOMEM,
9586                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9587                                    "cannot create matcher");
9588                 return NULL;
9589         }
9590         return &cache->entry;
9591 }
9592
9593 /**
9594  * Register the flow matcher.
9595  *
9596  * @param[in, out] dev
9597  *   Pointer to rte_eth_dev structure.
9598  * @param[in, out] matcher
9599  *   Pointer to flow matcher.
9600  * @param[in, out] key
9601  *   Pointer to flow table key.
9602  * @parm[in, out] dev_flow
9603  *   Pointer to the dev_flow.
9604  * @param[out] error
9605  *   pointer to error structure.
9606  *
9607  * @return
9608  *   0 on success otherwise -errno and errno is set.
9609  */
9610 static int
9611 flow_dv_matcher_register(struct rte_eth_dev *dev,
9612                          struct mlx5_flow_dv_matcher *ref,
9613                          union mlx5_flow_tbl_key *key,
9614                          struct mlx5_flow *dev_flow,
9615                          const struct mlx5_flow_tunnel *tunnel,
9616                          uint32_t group_id,
9617                          struct rte_flow_error *error)
9618 {
9619         struct mlx5_cache_entry *entry;
9620         struct mlx5_flow_dv_matcher *cache;
9621         struct mlx5_flow_tbl_resource *tbl;
9622         struct mlx5_flow_tbl_data_entry *tbl_data;
9623         struct mlx5_flow_cb_ctx ctx = {
9624                 .error = error,
9625                 .data = ref,
9626         };
9627
9628         /**
9629          * tunnel offload API requires this registration for cases when
9630          * tunnel match rule was inserted before tunnel set rule.
9631          */
9632         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9633                                        key->direction, key->domain,
9634                                        dev_flow->external, tunnel,
9635                                        group_id, 0, error);
9636         if (!tbl)
9637                 return -rte_errno;      /* No need to refill the error info */
9638         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9639         ref->tbl = tbl;
9640         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9641         if (!entry) {
9642                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9643                 return rte_flow_error_set(error, ENOMEM,
9644                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9645                                           "cannot allocate ref memory");
9646         }
9647         cache = container_of(entry, typeof(*cache), entry);
9648         dev_flow->handle->dvh.matcher = cache;
9649         return 0;
9650 }
9651
9652 struct mlx5_hlist_entry *
9653 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9654 {
9655         struct mlx5_dev_ctx_shared *sh = list->ctx;
9656         struct rte_flow_error *error = ctx;
9657         struct mlx5_flow_dv_tag_resource *entry;
9658         uint32_t idx = 0;
9659         int ret;
9660
9661         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9662         if (!entry) {
9663                 rte_flow_error_set(error, ENOMEM,
9664                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9665                                    "cannot allocate resource memory");
9666                 return NULL;
9667         }
9668         entry->idx = idx;
9669         entry->tag_id = key;
9670         ret = mlx5_flow_os_create_flow_action_tag(key,
9671                                                   &entry->action);
9672         if (ret) {
9673                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9674                 rte_flow_error_set(error, ENOMEM,
9675                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9676                                    NULL, "cannot create action");
9677                 return NULL;
9678         }
9679         return &entry->entry;
9680 }
9681
9682 int
9683 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9684                      struct mlx5_hlist_entry *entry, uint64_t key,
9685                      void *cb_ctx __rte_unused)
9686 {
9687         struct mlx5_flow_dv_tag_resource *tag =
9688                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9689
9690         return key != tag->tag_id;
9691 }
9692
9693 /**
9694  * Find existing tag resource or create and register a new one.
9695  *
9696  * @param dev[in, out]
9697  *   Pointer to rte_eth_dev structure.
9698  * @param[in, out] tag_be24
9699  *   Tag value in big endian then R-shift 8.
9700  * @parm[in, out] dev_flow
9701  *   Pointer to the dev_flow.
9702  * @param[out] error
9703  *   pointer to error structure.
9704  *
9705  * @return
9706  *   0 on success otherwise -errno and errno is set.
9707  */
9708 static int
9709 flow_dv_tag_resource_register
9710                         (struct rte_eth_dev *dev,
9711                          uint32_t tag_be24,
9712                          struct mlx5_flow *dev_flow,
9713                          struct rte_flow_error *error)
9714 {
9715         struct mlx5_priv *priv = dev->data->dev_private;
9716         struct mlx5_flow_dv_tag_resource *cache_resource;
9717         struct mlx5_hlist_entry *entry;
9718
9719         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9720         if (entry) {
9721                 cache_resource = container_of
9722                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9723                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9724                 dev_flow->dv.tag_resource = cache_resource;
9725                 return 0;
9726         }
9727         return -rte_errno;
9728 }
9729
9730 void
9731 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9732                       struct mlx5_hlist_entry *entry)
9733 {
9734         struct mlx5_dev_ctx_shared *sh = list->ctx;
9735         struct mlx5_flow_dv_tag_resource *tag =
9736                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9737
9738         MLX5_ASSERT(tag && sh && tag->action);
9739         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9740         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9741         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9742 }
9743
9744 /**
9745  * Release the tag.
9746  *
9747  * @param dev
9748  *   Pointer to Ethernet device.
9749  * @param tag_idx
9750  *   Tag index.
9751  *
9752  * @return
9753  *   1 while a reference on it exists, 0 when freed.
9754  */
9755 static int
9756 flow_dv_tag_release(struct rte_eth_dev *dev,
9757                     uint32_t tag_idx)
9758 {
9759         struct mlx5_priv *priv = dev->data->dev_private;
9760         struct mlx5_flow_dv_tag_resource *tag;
9761
9762         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9763         if (!tag)
9764                 return 0;
9765         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9766                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9767         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9768 }
9769
9770 /**
9771  * Translate port ID action to vport.
9772  *
9773  * @param[in] dev
9774  *   Pointer to rte_eth_dev structure.
9775  * @param[in] action
9776  *   Pointer to the port ID action.
9777  * @param[out] dst_port_id
9778  *   The target port ID.
9779  * @param[out] error
9780  *   Pointer to the error structure.
9781  *
9782  * @return
9783  *   0 on success, a negative errno value otherwise and rte_errno is set.
9784  */
9785 static int
9786 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9787                                  const struct rte_flow_action *action,
9788                                  uint32_t *dst_port_id,
9789                                  struct rte_flow_error *error)
9790 {
9791         uint32_t port;
9792         struct mlx5_priv *priv;
9793         const struct rte_flow_action_port_id *conf =
9794                         (const struct rte_flow_action_port_id *)action->conf;
9795
9796         port = conf->original ? dev->data->port_id : conf->id;
9797         priv = mlx5_port_to_eswitch_info(port, false);
9798         if (!priv)
9799                 return rte_flow_error_set(error, -rte_errno,
9800                                           RTE_FLOW_ERROR_TYPE_ACTION,
9801                                           NULL,
9802                                           "No eswitch info was found for port");
9803 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9804         /*
9805          * This parameter is transferred to
9806          * mlx5dv_dr_action_create_dest_ib_port().
9807          */
9808         *dst_port_id = priv->dev_port;
9809 #else
9810         /*
9811          * Legacy mode, no LAG configurations is supported.
9812          * This parameter is transferred to
9813          * mlx5dv_dr_action_create_dest_vport().
9814          */
9815         *dst_port_id = priv->vport_id;
9816 #endif
9817         return 0;
9818 }
9819
9820 /**
9821  * Create a counter with aging configuration.
9822  *
9823  * @param[in] dev
9824  *   Pointer to rte_eth_dev structure.
9825  * @param[out] count
9826  *   Pointer to the counter action configuration.
9827  * @param[in] age
9828  *   Pointer to the aging action configuration.
9829  *
9830  * @return
9831  *   Index to flow counter on success, 0 otherwise.
9832  */
9833 static uint32_t
9834 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9835                                 struct mlx5_flow *dev_flow,
9836                                 const struct rte_flow_action_count *count,
9837                                 const struct rte_flow_action_age *age)
9838 {
9839         uint32_t counter;
9840         struct mlx5_age_param *age_param;
9841
9842         if (count && count->shared)
9843                 counter = flow_dv_counter_get_shared(dev, count->id);
9844         else
9845                 counter = flow_dv_counter_alloc(dev, !!age);
9846         if (!counter || age == NULL)
9847                 return counter;
9848         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9849         age_param->context = age->context ? age->context :
9850                 (void *)(uintptr_t)(dev_flow->flow_idx);
9851         age_param->timeout = age->timeout;
9852         age_param->port_id = dev->data->port_id;
9853         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9854         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9855         return counter;
9856 }
9857
9858 /**
9859  * Add Tx queue matcher
9860  *
9861  * @param[in] dev
9862  *   Pointer to the dev struct.
9863  * @param[in, out] matcher
9864  *   Flow matcher.
9865  * @param[in, out] key
9866  *   Flow matcher value.
9867  * @param[in] item
9868  *   Flow pattern to translate.
9869  * @param[in] inner
9870  *   Item is inner pattern.
9871  */
9872 static void
9873 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9874                                 void *matcher, void *key,
9875                                 const struct rte_flow_item *item)
9876 {
9877         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9878         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9879         void *misc_m =
9880                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9881         void *misc_v =
9882                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9883         struct mlx5_txq_ctrl *txq;
9884         uint32_t queue;
9885
9886
9887         queue_m = (const void *)item->mask;
9888         if (!queue_m)
9889                 return;
9890         queue_v = (const void *)item->spec;
9891         if (!queue_v)
9892                 return;
9893         txq = mlx5_txq_get(dev, queue_v->queue);
9894         if (!txq)
9895                 return;
9896         queue = txq->obj->sq->id;
9897         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9898         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9899                  queue & queue_m->queue);
9900         mlx5_txq_release(dev, queue_v->queue);
9901 }
9902
9903 /**
9904  * Set the hash fields according to the @p flow information.
9905  *
9906  * @param[in] dev_flow
9907  *   Pointer to the mlx5_flow.
9908  * @param[in] rss_desc
9909  *   Pointer to the mlx5_flow_rss_desc.
9910  */
9911 static void
9912 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9913                        struct mlx5_flow_rss_desc *rss_desc)
9914 {
9915         uint64_t items = dev_flow->handle->layers;
9916         int rss_inner = 0;
9917         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9918
9919         dev_flow->hash_fields = 0;
9920 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9921         if (rss_desc->level >= 2) {
9922                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9923                 rss_inner = 1;
9924         }
9925 #endif
9926         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9927             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9928                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9929                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9930                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9931                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9932                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9933                         else
9934                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9935                 }
9936         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9937                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9938                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9939                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9940                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9941                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9942                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9943                         else
9944                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9945                 }
9946         }
9947         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9948             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9949                 if (rss_types & ETH_RSS_UDP) {
9950                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9951                                 dev_flow->hash_fields |=
9952                                                 IBV_RX_HASH_SRC_PORT_UDP;
9953                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9954                                 dev_flow->hash_fields |=
9955                                                 IBV_RX_HASH_DST_PORT_UDP;
9956                         else
9957                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9958                 }
9959         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9960                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9961                 if (rss_types & ETH_RSS_TCP) {
9962                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9963                                 dev_flow->hash_fields |=
9964                                                 IBV_RX_HASH_SRC_PORT_TCP;
9965                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9966                                 dev_flow->hash_fields |=
9967                                                 IBV_RX_HASH_DST_PORT_TCP;
9968                         else
9969                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9970                 }
9971         }
9972 }
9973
9974 /**
9975  * Prepare an Rx Hash queue.
9976  *
9977  * @param dev
9978  *   Pointer to Ethernet device.
9979  * @param[in] dev_flow
9980  *   Pointer to the mlx5_flow.
9981  * @param[in] rss_desc
9982  *   Pointer to the mlx5_flow_rss_desc.
9983  * @param[out] hrxq_idx
9984  *   Hash Rx queue index.
9985  *
9986  * @return
9987  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9988  */
9989 static struct mlx5_hrxq *
9990 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9991                      struct mlx5_flow *dev_flow,
9992                      struct mlx5_flow_rss_desc *rss_desc,
9993                      uint32_t *hrxq_idx)
9994 {
9995         struct mlx5_priv *priv = dev->data->dev_private;
9996         struct mlx5_flow_handle *dh = dev_flow->handle;
9997         struct mlx5_hrxq *hrxq;
9998
9999         MLX5_ASSERT(rss_desc->queue_num);
10000         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10001         rss_desc->hash_fields = dev_flow->hash_fields;
10002         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10003         rss_desc->shared_rss = 0;
10004         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10005         if (!*hrxq_idx)
10006                 return NULL;
10007         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10008                               *hrxq_idx);
10009         return hrxq;
10010 }
10011
10012 /**
10013  * Release sample sub action resource.
10014  *
10015  * @param[in, out] dev
10016  *   Pointer to rte_eth_dev structure.
10017  * @param[in] act_res
10018  *   Pointer to sample sub action resource.
10019  */
10020 static void
10021 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10022                                    struct mlx5_flow_sub_actions_idx *act_res)
10023 {
10024         if (act_res->rix_hrxq) {
10025                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10026                 act_res->rix_hrxq = 0;
10027         }
10028         if (act_res->rix_encap_decap) {
10029                 flow_dv_encap_decap_resource_release(dev,
10030                                                      act_res->rix_encap_decap);
10031                 act_res->rix_encap_decap = 0;
10032         }
10033         if (act_res->rix_port_id_action) {
10034                 flow_dv_port_id_action_resource_release(dev,
10035                                                 act_res->rix_port_id_action);
10036                 act_res->rix_port_id_action = 0;
10037         }
10038         if (act_res->rix_tag) {
10039                 flow_dv_tag_release(dev, act_res->rix_tag);
10040                 act_res->rix_tag = 0;
10041         }
10042         if (act_res->rix_jump) {
10043                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10044                 act_res->rix_jump = 0;
10045         }
10046 }
10047
10048 int
10049 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10050                         struct mlx5_cache_entry *entry, void *cb_ctx)
10051 {
10052         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10053         struct rte_eth_dev *dev = ctx->dev;
10054         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10055         struct mlx5_flow_dv_sample_resource *cache_resource =
10056                         container_of(entry, typeof(*cache_resource), entry);
10057
10058         if (resource->ratio == cache_resource->ratio &&
10059             resource->ft_type == cache_resource->ft_type &&
10060             resource->ft_id == cache_resource->ft_id &&
10061             resource->set_action == cache_resource->set_action &&
10062             !memcmp((void *)&resource->sample_act,
10063                     (void *)&cache_resource->sample_act,
10064                     sizeof(struct mlx5_flow_sub_actions_list))) {
10065                 /*
10066                  * Existing sample action should release the prepared
10067                  * sub-actions reference counter.
10068                  */
10069                 flow_dv_sample_sub_actions_release(dev,
10070                                                 &resource->sample_idx);
10071                 return 0;
10072         }
10073         return 1;
10074 }
10075
10076 struct mlx5_cache_entry *
10077 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10078                          struct mlx5_cache_entry *entry __rte_unused,
10079                          void *cb_ctx)
10080 {
10081         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10082         struct rte_eth_dev *dev = ctx->dev;
10083         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10084         void **sample_dv_actions = resource->sub_actions;
10085         struct mlx5_flow_dv_sample_resource *cache_resource;
10086         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10087         struct mlx5_priv *priv = dev->data->dev_private;
10088         struct mlx5_dev_ctx_shared *sh = priv->sh;
10089         struct mlx5_flow_tbl_resource *tbl;
10090         uint32_t idx = 0;
10091         const uint32_t next_ft_step = 1;
10092         uint32_t next_ft_id = resource->ft_id + next_ft_step;
10093         uint8_t is_egress = 0;
10094         uint8_t is_transfer = 0;
10095         struct rte_flow_error *error = ctx->error;
10096
10097         /* Register new sample resource. */
10098         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10099         if (!cache_resource) {
10100                 rte_flow_error_set(error, ENOMEM,
10101                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10102                                           NULL,
10103                                           "cannot allocate resource memory");
10104                 return NULL;
10105         }
10106         *cache_resource = *resource;
10107         /* Create normal path table level */
10108         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10109                 is_transfer = 1;
10110         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10111                 is_egress = 1;
10112         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10113                                         is_egress, is_transfer,
10114                                         true, NULL, 0, 0, error);
10115         if (!tbl) {
10116                 rte_flow_error_set(error, ENOMEM,
10117                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10118                                           NULL,
10119                                           "fail to create normal path table "
10120                                           "for sample");
10121                 goto error;
10122         }
10123         cache_resource->normal_path_tbl = tbl;
10124         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10125                 if (!sh->default_miss_action) {
10126                         rte_flow_error_set(error, ENOMEM,
10127                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10128                                                 NULL,
10129                                                 "default miss action was not "
10130                                                 "created");
10131                         goto error;
10132                 }
10133                 sample_dv_actions[resource->sample_act.actions_num++] =
10134                                                 sh->default_miss_action;
10135         }
10136         /* Create a DR sample action */
10137         sampler_attr.sample_ratio = cache_resource->ratio;
10138         sampler_attr.default_next_table = tbl->obj;
10139         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10140         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10141                                                         &sample_dv_actions[0];
10142         sampler_attr.action = cache_resource->set_action;
10143         if (mlx5_os_flow_dr_create_flow_action_sampler
10144                         (&sampler_attr, &cache_resource->verbs_action)) {
10145                 rte_flow_error_set(error, ENOMEM,
10146                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10147                                         NULL, "cannot create sample action");
10148                 goto error;
10149         }
10150         cache_resource->idx = idx;
10151         cache_resource->dev = dev;
10152         return &cache_resource->entry;
10153 error:
10154         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10155                 flow_dv_sample_sub_actions_release(dev,
10156                                                    &cache_resource->sample_idx);
10157         if (cache_resource->normal_path_tbl)
10158                 flow_dv_tbl_resource_release(MLX5_SH(dev),
10159                                 cache_resource->normal_path_tbl);
10160         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10161         return NULL;
10162
10163 }
10164
10165 /**
10166  * Find existing sample resource or create and register a new one.
10167  *
10168  * @param[in, out] dev
10169  *   Pointer to rte_eth_dev structure.
10170  * @param[in] resource
10171  *   Pointer to sample resource.
10172  * @parm[in, out] dev_flow
10173  *   Pointer to the dev_flow.
10174  * @param[out] error
10175  *   pointer to error structure.
10176  *
10177  * @return
10178  *   0 on success otherwise -errno and errno is set.
10179  */
10180 static int
10181 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10182                          struct mlx5_flow_dv_sample_resource *resource,
10183                          struct mlx5_flow *dev_flow,
10184                          struct rte_flow_error *error)
10185 {
10186         struct mlx5_flow_dv_sample_resource *cache_resource;
10187         struct mlx5_cache_entry *entry;
10188         struct mlx5_priv *priv = dev->data->dev_private;
10189         struct mlx5_flow_cb_ctx ctx = {
10190                 .dev = dev,
10191                 .error = error,
10192                 .data = resource,
10193         };
10194
10195         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10196         if (!entry)
10197                 return -rte_errno;
10198         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10199         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10200         dev_flow->dv.sample_res = cache_resource;
10201         return 0;
10202 }
10203
10204 int
10205 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10206                             struct mlx5_cache_entry *entry, void *cb_ctx)
10207 {
10208         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10209         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10210         struct rte_eth_dev *dev = ctx->dev;
10211         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10212                         container_of(entry, typeof(*cache_resource), entry);
10213         uint32_t idx = 0;
10214
10215         if (resource->num_of_dest == cache_resource->num_of_dest &&
10216             resource->ft_type == cache_resource->ft_type &&
10217             !memcmp((void *)cache_resource->sample_act,
10218                     (void *)resource->sample_act,
10219                    (resource->num_of_dest *
10220                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10221                 /*
10222                  * Existing sample action should release the prepared
10223                  * sub-actions reference counter.
10224                  */
10225                 for (idx = 0; idx < resource->num_of_dest; idx++)
10226                         flow_dv_sample_sub_actions_release(dev,
10227                                         &resource->sample_idx[idx]);
10228                 return 0;
10229         }
10230         return 1;
10231 }
10232
10233 struct mlx5_cache_entry *
10234 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10235                          struct mlx5_cache_entry *entry __rte_unused,
10236                          void *cb_ctx)
10237 {
10238         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10239         struct rte_eth_dev *dev = ctx->dev;
10240         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10241         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10242         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10243         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10244         struct mlx5_priv *priv = dev->data->dev_private;
10245         struct mlx5_dev_ctx_shared *sh = priv->sh;
10246         struct mlx5_flow_sub_actions_list *sample_act;
10247         struct mlx5dv_dr_domain *domain;
10248         uint32_t idx = 0, res_idx = 0;
10249         struct rte_flow_error *error = ctx->error;
10250         uint64_t action_flags;
10251         int ret;
10252
10253         /* Register new destination array resource. */
10254         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10255                                             &res_idx);
10256         if (!cache_resource) {
10257                 rte_flow_error_set(error, ENOMEM,
10258                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10259                                           NULL,
10260                                           "cannot allocate resource memory");
10261                 return NULL;
10262         }
10263         *cache_resource = *resource;
10264         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10265                 domain = sh->fdb_domain;
10266         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10267                 domain = sh->rx_domain;
10268         else
10269                 domain = sh->tx_domain;
10270         for (idx = 0; idx < resource->num_of_dest; idx++) {
10271                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10272                                  mlx5_malloc(MLX5_MEM_ZERO,
10273                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10274                                  0, SOCKET_ID_ANY);
10275                 if (!dest_attr[idx]) {
10276                         rte_flow_error_set(error, ENOMEM,
10277                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10278                                            NULL,
10279                                            "cannot allocate resource memory");
10280                         goto error;
10281                 }
10282                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10283                 sample_act = &resource->sample_act[idx];
10284                 action_flags = sample_act->action_flags;
10285                 switch (action_flags) {
10286                 case MLX5_FLOW_ACTION_QUEUE:
10287                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10288                         break;
10289                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10290                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10291                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10292                         dest_attr[idx]->dest_reformat->reformat =
10293                                         sample_act->dr_encap_action;
10294                         dest_attr[idx]->dest_reformat->dest =
10295                                         sample_act->dr_port_id_action;
10296                         break;
10297                 case MLX5_FLOW_ACTION_PORT_ID:
10298                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10299                         break;
10300                 case MLX5_FLOW_ACTION_JUMP:
10301                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10302                         break;
10303                 default:
10304                         rte_flow_error_set(error, EINVAL,
10305                                            RTE_FLOW_ERROR_TYPE_ACTION,
10306                                            NULL,
10307                                            "unsupported actions type");
10308                         goto error;
10309                 }
10310         }
10311         /* create a dest array actioin */
10312         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10313                                                 (domain,
10314                                                  cache_resource->num_of_dest,
10315                                                  dest_attr,
10316                                                  &cache_resource->action);
10317         if (ret) {
10318                 rte_flow_error_set(error, ENOMEM,
10319                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10320                                    NULL,
10321                                    "cannot create destination array action");
10322                 goto error;
10323         }
10324         cache_resource->idx = res_idx;
10325         cache_resource->dev = dev;
10326         for (idx = 0; idx < resource->num_of_dest; idx++)
10327                 mlx5_free(dest_attr[idx]);
10328         return &cache_resource->entry;
10329 error:
10330         for (idx = 0; idx < resource->num_of_dest; idx++) {
10331                 flow_dv_sample_sub_actions_release(dev,
10332                                 &cache_resource->sample_idx[idx]);
10333                 if (dest_attr[idx])
10334                         mlx5_free(dest_attr[idx]);
10335         }
10336
10337         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10338         return NULL;
10339 }
10340
10341 /**
10342  * Find existing destination array resource or create and register a new one.
10343  *
10344  * @param[in, out] dev
10345  *   Pointer to rte_eth_dev structure.
10346  * @param[in] resource
10347  *   Pointer to destination array resource.
10348  * @parm[in, out] dev_flow
10349  *   Pointer to the dev_flow.
10350  * @param[out] error
10351  *   pointer to error structure.
10352  *
10353  * @return
10354  *   0 on success otherwise -errno and errno is set.
10355  */
10356 static int
10357 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10358                          struct mlx5_flow_dv_dest_array_resource *resource,
10359                          struct mlx5_flow *dev_flow,
10360                          struct rte_flow_error *error)
10361 {
10362         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10363         struct mlx5_priv *priv = dev->data->dev_private;
10364         struct mlx5_cache_entry *entry;
10365         struct mlx5_flow_cb_ctx ctx = {
10366                 .dev = dev,
10367                 .error = error,
10368                 .data = resource,
10369         };
10370
10371         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10372         if (!entry)
10373                 return -rte_errno;
10374         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10375         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10376         dev_flow->dv.dest_array_res = cache_resource;
10377         return 0;
10378 }
10379
10380 /**
10381  * Convert Sample action to DV specification.
10382  *
10383  * @param[in] dev
10384  *   Pointer to rte_eth_dev structure.
10385  * @param[in] action
10386  *   Pointer to sample action structure.
10387  * @param[in, out] dev_flow
10388  *   Pointer to the mlx5_flow.
10389  * @param[in] attr
10390  *   Pointer to the flow attributes.
10391  * @param[in, out] num_of_dest
10392  *   Pointer to the num of destination.
10393  * @param[in, out] sample_actions
10394  *   Pointer to sample actions list.
10395  * @param[in, out] res
10396  *   Pointer to sample resource.
10397  * @param[out] error
10398  *   Pointer to the error structure.
10399  *
10400  * @return
10401  *   0 on success, a negative errno value otherwise and rte_errno is set.
10402  */
10403 static int
10404 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10405                                 const struct rte_flow_action_sample *action,
10406                                 struct mlx5_flow *dev_flow,
10407                                 const struct rte_flow_attr *attr,
10408                                 uint32_t *num_of_dest,
10409                                 void **sample_actions,
10410                                 struct mlx5_flow_dv_sample_resource *res,
10411                                 struct rte_flow_error *error)
10412 {
10413         struct mlx5_priv *priv = dev->data->dev_private;
10414         const struct rte_flow_action *sub_actions;
10415         struct mlx5_flow_sub_actions_list *sample_act;
10416         struct mlx5_flow_sub_actions_idx *sample_idx;
10417         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10418         struct rte_flow *flow = dev_flow->flow;
10419         struct mlx5_flow_rss_desc *rss_desc;
10420         uint64_t action_flags = 0;
10421
10422         MLX5_ASSERT(wks);
10423         rss_desc = &wks->rss_desc;
10424         sample_act = &res->sample_act;
10425         sample_idx = &res->sample_idx;
10426         res->ratio = action->ratio;
10427         sub_actions = action->actions;
10428         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10429                 int type = sub_actions->type;
10430                 uint32_t pre_rix = 0;
10431                 void *pre_r;
10432                 switch (type) {
10433                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10434                 {
10435                         const struct rte_flow_action_queue *queue;
10436                         struct mlx5_hrxq *hrxq;
10437                         uint32_t hrxq_idx;
10438
10439                         queue = sub_actions->conf;
10440                         rss_desc->queue_num = 1;
10441                         rss_desc->queue[0] = queue->index;
10442                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10443                                                     rss_desc, &hrxq_idx);
10444                         if (!hrxq)
10445                                 return rte_flow_error_set
10446                                         (error, rte_errno,
10447                                          RTE_FLOW_ERROR_TYPE_ACTION,
10448                                          NULL,
10449                                          "cannot create fate queue");
10450                         sample_act->dr_queue_action = hrxq->action;
10451                         sample_idx->rix_hrxq = hrxq_idx;
10452                         sample_actions[sample_act->actions_num++] =
10453                                                 hrxq->action;
10454                         (*num_of_dest)++;
10455                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10456                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10457                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10458                         dev_flow->handle->fate_action =
10459                                         MLX5_FLOW_FATE_QUEUE;
10460                         break;
10461                 }
10462                 case RTE_FLOW_ACTION_TYPE_RSS:
10463                 {
10464                         struct mlx5_hrxq *hrxq;
10465                         uint32_t hrxq_idx;
10466                         const struct rte_flow_action_rss *rss;
10467                         const uint8_t *rss_key;
10468
10469                         rss = sub_actions->conf;
10470                         memcpy(rss_desc->queue, rss->queue,
10471                                rss->queue_num * sizeof(uint16_t));
10472                         rss_desc->queue_num = rss->queue_num;
10473                         /* NULL RSS key indicates default RSS key. */
10474                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10475                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10476                         /*
10477                          * rss->level and rss.types should be set in advance
10478                          * when expanding items for RSS.
10479                          */
10480                         flow_dv_hashfields_set(dev_flow, rss_desc);
10481                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10482                                                     rss_desc, &hrxq_idx);
10483                         if (!hrxq)
10484                                 return rte_flow_error_set
10485                                         (error, rte_errno,
10486                                          RTE_FLOW_ERROR_TYPE_ACTION,
10487                                          NULL,
10488                                          "cannot create fate queue");
10489                         sample_act->dr_queue_action = hrxq->action;
10490                         sample_idx->rix_hrxq = hrxq_idx;
10491                         sample_actions[sample_act->actions_num++] =
10492                                                 hrxq->action;
10493                         (*num_of_dest)++;
10494                         action_flags |= MLX5_FLOW_ACTION_RSS;
10495                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10496                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10497                         dev_flow->handle->fate_action =
10498                                         MLX5_FLOW_FATE_QUEUE;
10499                         break;
10500                 }
10501                 case RTE_FLOW_ACTION_TYPE_MARK:
10502                 {
10503                         uint32_t tag_be = mlx5_flow_mark_set
10504                                 (((const struct rte_flow_action_mark *)
10505                                 (sub_actions->conf))->id);
10506
10507                         dev_flow->handle->mark = 1;
10508                         pre_rix = dev_flow->handle->dvh.rix_tag;
10509                         /* Save the mark resource before sample */
10510                         pre_r = dev_flow->dv.tag_resource;
10511                         if (flow_dv_tag_resource_register(dev, tag_be,
10512                                                   dev_flow, error))
10513                                 return -rte_errno;
10514                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10515                         sample_act->dr_tag_action =
10516                                 dev_flow->dv.tag_resource->action;
10517                         sample_idx->rix_tag =
10518                                 dev_flow->handle->dvh.rix_tag;
10519                         sample_actions[sample_act->actions_num++] =
10520                                                 sample_act->dr_tag_action;
10521                         /* Recover the mark resource after sample */
10522                         dev_flow->dv.tag_resource = pre_r;
10523                         dev_flow->handle->dvh.rix_tag = pre_rix;
10524                         action_flags |= MLX5_FLOW_ACTION_MARK;
10525                         break;
10526                 }
10527                 case RTE_FLOW_ACTION_TYPE_COUNT:
10528                 {
10529                         if (!flow->counter) {
10530                                 flow->counter =
10531                                         flow_dv_translate_create_counter(dev,
10532                                                 dev_flow, sub_actions->conf,
10533                                                 0);
10534                                 if (!flow->counter)
10535                                         return rte_flow_error_set
10536                                                 (error, rte_errno,
10537                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10538                                                 NULL,
10539                                                 "cannot create counter"
10540                                                 " object.");
10541                         }
10542                         sample_act->dr_cnt_action =
10543                                   (flow_dv_counter_get_by_idx(dev,
10544                                   flow->counter, NULL))->action;
10545                         sample_actions[sample_act->actions_num++] =
10546                                                 sample_act->dr_cnt_action;
10547                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10548                         break;
10549                 }
10550                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10551                 {
10552                         struct mlx5_flow_dv_port_id_action_resource
10553                                         port_id_resource;
10554                         uint32_t port_id = 0;
10555
10556                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10557                         /* Save the port id resource before sample */
10558                         pre_rix = dev_flow->handle->rix_port_id_action;
10559                         pre_r = dev_flow->dv.port_id_action;
10560                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10561                                                              &port_id, error))
10562                                 return -rte_errno;
10563                         port_id_resource.port_id = port_id;
10564                         if (flow_dv_port_id_action_resource_register
10565                             (dev, &port_id_resource, dev_flow, error))
10566                                 return -rte_errno;
10567                         sample_act->dr_port_id_action =
10568                                 dev_flow->dv.port_id_action->action;
10569                         sample_idx->rix_port_id_action =
10570                                 dev_flow->handle->rix_port_id_action;
10571                         sample_actions[sample_act->actions_num++] =
10572                                                 sample_act->dr_port_id_action;
10573                         /* Recover the port id resource after sample */
10574                         dev_flow->dv.port_id_action = pre_r;
10575                         dev_flow->handle->rix_port_id_action = pre_rix;
10576                         (*num_of_dest)++;
10577                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10578                         break;
10579                 }
10580                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10581                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10582                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10583                         /* Save the encap resource before sample */
10584                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10585                         pre_r = dev_flow->dv.encap_decap;
10586                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10587                                                            dev_flow,
10588                                                            attr->transfer,
10589                                                            error))
10590                                 return -rte_errno;
10591                         sample_act->dr_encap_action =
10592                                 dev_flow->dv.encap_decap->action;
10593                         sample_idx->rix_encap_decap =
10594                                 dev_flow->handle->dvh.rix_encap_decap;
10595                         sample_actions[sample_act->actions_num++] =
10596                                                 sample_act->dr_encap_action;
10597                         /* Recover the encap resource after sample */
10598                         dev_flow->dv.encap_decap = pre_r;
10599                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10600                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10601                         break;
10602                 default:
10603                         return rte_flow_error_set(error, EINVAL,
10604                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10605                                 NULL,
10606                                 "Not support for sampler action");
10607                 }
10608         }
10609         sample_act->action_flags = action_flags;
10610         res->ft_id = dev_flow->dv.group;
10611         if (attr->transfer) {
10612                 union {
10613                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10614                         uint64_t set_action;
10615                 } action_ctx = { .set_action = 0 };
10616
10617                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10618                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10619                          MLX5_MODIFICATION_TYPE_SET);
10620                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10621                          MLX5_MODI_META_REG_C_0);
10622                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10623                          priv->vport_meta_tag);
10624                 res->set_action = action_ctx.set_action;
10625         } else if (attr->ingress) {
10626                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10627         } else {
10628                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10629         }
10630         return 0;
10631 }
10632
10633 /**
10634  * Convert Sample action to DV specification.
10635  *
10636  * @param[in] dev
10637  *   Pointer to rte_eth_dev structure.
10638  * @param[in, out] dev_flow
10639  *   Pointer to the mlx5_flow.
10640  * @param[in] num_of_dest
10641  *   The num of destination.
10642  * @param[in, out] res
10643  *   Pointer to sample resource.
10644  * @param[in, out] mdest_res
10645  *   Pointer to destination array resource.
10646  * @param[in] sample_actions
10647  *   Pointer to sample path actions list.
10648  * @param[in] action_flags
10649  *   Holds the actions detected until now.
10650  * @param[out] error
10651  *   Pointer to the error structure.
10652  *
10653  * @return
10654  *   0 on success, a negative errno value otherwise and rte_errno is set.
10655  */
10656 static int
10657 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10658                              struct mlx5_flow *dev_flow,
10659                              uint32_t num_of_dest,
10660                              struct mlx5_flow_dv_sample_resource *res,
10661                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10662                              void **sample_actions,
10663                              uint64_t action_flags,
10664                              struct rte_flow_error *error)
10665 {
10666         /* update normal path action resource into last index of array */
10667         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10668         struct mlx5_flow_sub_actions_list *sample_act =
10669                                         &mdest_res->sample_act[dest_index];
10670         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10671         struct mlx5_flow_rss_desc *rss_desc;
10672         uint32_t normal_idx = 0;
10673         struct mlx5_hrxq *hrxq;
10674         uint32_t hrxq_idx;
10675
10676         MLX5_ASSERT(wks);
10677         rss_desc = &wks->rss_desc;
10678         if (num_of_dest > 1) {
10679                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10680                         /* Handle QP action for mirroring */
10681                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10682                                                     rss_desc, &hrxq_idx);
10683                         if (!hrxq)
10684                                 return rte_flow_error_set
10685                                      (error, rte_errno,
10686                                       RTE_FLOW_ERROR_TYPE_ACTION,
10687                                       NULL,
10688                                       "cannot create rx queue");
10689                         normal_idx++;
10690                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10691                         sample_act->dr_queue_action = hrxq->action;
10692                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10693                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10694                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10695                 }
10696                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10697                         normal_idx++;
10698                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10699                                 dev_flow->handle->dvh.rix_encap_decap;
10700                         sample_act->dr_encap_action =
10701                                 dev_flow->dv.encap_decap->action;
10702                         dev_flow->handle->dvh.rix_encap_decap = 0;
10703                 }
10704                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10705                         normal_idx++;
10706                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10707                                 dev_flow->handle->rix_port_id_action;
10708                         sample_act->dr_port_id_action =
10709                                 dev_flow->dv.port_id_action->action;
10710                         dev_flow->handle->rix_port_id_action = 0;
10711                 }
10712                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10713                         normal_idx++;
10714                         mdest_res->sample_idx[dest_index].rix_jump =
10715                                 dev_flow->handle->rix_jump;
10716                         sample_act->dr_jump_action =
10717                                 dev_flow->dv.jump->action;
10718                         dev_flow->handle->rix_jump = 0;
10719                 }
10720                 sample_act->actions_num = normal_idx;
10721                 /* update sample action resource into first index of array */
10722                 mdest_res->ft_type = res->ft_type;
10723                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10724                                 sizeof(struct mlx5_flow_sub_actions_idx));
10725                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10726                                 sizeof(struct mlx5_flow_sub_actions_list));
10727                 mdest_res->num_of_dest = num_of_dest;
10728                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10729                                                          dev_flow, error))
10730                         return rte_flow_error_set(error, EINVAL,
10731                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10732                                                   NULL, "can't create sample "
10733                                                   "action");
10734         } else {
10735                 res->sub_actions = sample_actions;
10736                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10737                         return rte_flow_error_set(error, EINVAL,
10738                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10739                                                   NULL,
10740                                                   "can't create sample action");
10741         }
10742         return 0;
10743 }
10744
10745 /**
10746  * Remove an ASO age action from age actions list.
10747  *
10748  * @param[in] dev
10749  *   Pointer to the Ethernet device structure.
10750  * @param[in] age
10751  *   Pointer to the aso age action handler.
10752  */
10753 static void
10754 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10755                                 struct mlx5_aso_age_action *age)
10756 {
10757         struct mlx5_age_info *age_info;
10758         struct mlx5_age_param *age_param = &age->age_params;
10759         struct mlx5_priv *priv = dev->data->dev_private;
10760         uint16_t expected = AGE_CANDIDATE;
10761
10762         age_info = GET_PORT_AGE_INFO(priv);
10763         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10764                                          AGE_FREE, false, __ATOMIC_RELAXED,
10765                                          __ATOMIC_RELAXED)) {
10766                 /**
10767                  * We need the lock even it is age timeout,
10768                  * since age action may still in process.
10769                  */
10770                 rte_spinlock_lock(&age_info->aged_sl);
10771                 LIST_REMOVE(age, next);
10772                 rte_spinlock_unlock(&age_info->aged_sl);
10773                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10774         }
10775 }
10776
10777 /**
10778  * Release an ASO age action.
10779  *
10780  * @param[in] dev
10781  *   Pointer to the Ethernet device structure.
10782  * @param[in] age_idx
10783  *   Index of ASO age action to release.
10784  * @param[in] flow
10785  *   True if the release operation is during flow destroy operation.
10786  *   False if the release operation is during action destroy operation.
10787  *
10788  * @return
10789  *   0 when age action was removed, otherwise the number of references.
10790  */
10791 static int
10792 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10793 {
10794         struct mlx5_priv *priv = dev->data->dev_private;
10795         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10796         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10797         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10798
10799         if (!ret) {
10800                 flow_dv_aso_age_remove_from_age(dev, age);
10801                 rte_spinlock_lock(&mng->free_sl);
10802                 LIST_INSERT_HEAD(&mng->free, age, next);
10803                 rte_spinlock_unlock(&mng->free_sl);
10804         }
10805         return ret;
10806 }
10807
10808 /**
10809  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10810  *
10811  * @param[in] dev
10812  *   Pointer to the Ethernet device structure.
10813  *
10814  * @return
10815  *   0 on success, otherwise negative errno value and rte_errno is set.
10816  */
10817 static int
10818 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10819 {
10820         struct mlx5_priv *priv = dev->data->dev_private;
10821         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10822         void *old_pools = mng->pools;
10823         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10824         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10825         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10826
10827         if (!pools) {
10828                 rte_errno = ENOMEM;
10829                 return -ENOMEM;
10830         }
10831         if (old_pools) {
10832                 memcpy(pools, old_pools,
10833                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10834                 mlx5_free(old_pools);
10835         } else {
10836                 /* First ASO flow hit allocation - starting ASO data-path. */
10837                 int ret = mlx5_aso_queue_start(priv->sh);
10838
10839                 if (ret) {
10840                         mlx5_free(pools);
10841                         return ret;
10842                 }
10843         }
10844         mng->n = resize;
10845         mng->pools = pools;
10846         return 0;
10847 }
10848
10849 /**
10850  * Create and initialize a new ASO aging pool.
10851  *
10852  * @param[in] dev
10853  *   Pointer to the Ethernet device structure.
10854  * @param[out] age_free
10855  *   Where to put the pointer of a new age action.
10856  *
10857  * @return
10858  *   The age actions pool pointer and @p age_free is set on success,
10859  *   NULL otherwise and rte_errno is set.
10860  */
10861 static struct mlx5_aso_age_pool *
10862 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10863                         struct mlx5_aso_age_action **age_free)
10864 {
10865         struct mlx5_priv *priv = dev->data->dev_private;
10866         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10867         struct mlx5_aso_age_pool *pool = NULL;
10868         struct mlx5_devx_obj *obj = NULL;
10869         uint32_t i;
10870
10871         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10872                                                     priv->sh->pdn);
10873         if (!obj) {
10874                 rte_errno = ENODATA;
10875                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10876                 return NULL;
10877         }
10878         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10879         if (!pool) {
10880                 claim_zero(mlx5_devx_cmd_destroy(obj));
10881                 rte_errno = ENOMEM;
10882                 return NULL;
10883         }
10884         pool->flow_hit_aso_obj = obj;
10885         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10886         rte_spinlock_lock(&mng->resize_sl);
10887         pool->index = mng->next;
10888         /* Resize pools array if there is no room for the new pool in it. */
10889         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10890                 claim_zero(mlx5_devx_cmd_destroy(obj));
10891                 mlx5_free(pool);
10892                 rte_spinlock_unlock(&mng->resize_sl);
10893                 return NULL;
10894         }
10895         mng->pools[pool->index] = pool;
10896         mng->next++;
10897         rte_spinlock_unlock(&mng->resize_sl);
10898         /* Assign the first action in the new pool, the rest go to free list. */
10899         *age_free = &pool->actions[0];
10900         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10901                 pool->actions[i].offset = i;
10902                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10903         }
10904         return pool;
10905 }
10906
10907 /**
10908  * Allocate a ASO aging bit.
10909  *
10910  * @param[in] dev
10911  *   Pointer to the Ethernet device structure.
10912  * @param[out] error
10913  *   Pointer to the error structure.
10914  *
10915  * @return
10916  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10917  */
10918 static uint32_t
10919 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10920 {
10921         struct mlx5_priv *priv = dev->data->dev_private;
10922         const struct mlx5_aso_age_pool *pool;
10923         struct mlx5_aso_age_action *age_free = NULL;
10924         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10925
10926         MLX5_ASSERT(mng);
10927         /* Try to get the next free age action bit. */
10928         rte_spinlock_lock(&mng->free_sl);
10929         age_free = LIST_FIRST(&mng->free);
10930         if (age_free) {
10931                 LIST_REMOVE(age_free, next);
10932         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10933                 rte_spinlock_unlock(&mng->free_sl);
10934                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10935                                    NULL, "failed to create ASO age pool");
10936                 return 0; /* 0 is an error. */
10937         }
10938         rte_spinlock_unlock(&mng->free_sl);
10939         pool = container_of
10940           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10941                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10942                                                                        actions);
10943         if (!age_free->dr_action) {
10944                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10945                                                  error);
10946
10947                 if (reg_c < 0) {
10948                         rte_flow_error_set(error, rte_errno,
10949                                            RTE_FLOW_ERROR_TYPE_ACTION,
10950                                            NULL, "failed to get reg_c "
10951                                            "for ASO flow hit");
10952                         return 0; /* 0 is an error. */
10953                 }
10954 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10955                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10956                                 (priv->sh->rx_domain,
10957                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10958                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10959                                  (reg_c - REG_C_0));
10960 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10961                 if (!age_free->dr_action) {
10962                         rte_errno = errno;
10963                         rte_spinlock_lock(&mng->free_sl);
10964                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10965                         rte_spinlock_unlock(&mng->free_sl);
10966                         rte_flow_error_set(error, rte_errno,
10967                                            RTE_FLOW_ERROR_TYPE_ACTION,
10968                                            NULL, "failed to create ASO "
10969                                            "flow hit action");
10970                         return 0; /* 0 is an error. */
10971                 }
10972         }
10973         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10974         return pool->index | ((age_free->offset + 1) << 16);
10975 }
10976
10977 /**
10978  * Create a age action using ASO mechanism.
10979  *
10980  * @param[in] dev
10981  *   Pointer to rte_eth_dev structure.
10982  * @param[in] age
10983  *   Pointer to the aging action configuration.
10984  * @param[out] error
10985  *   Pointer to the error structure.
10986  *
10987  * @return
10988  *   Index to flow counter on success, 0 otherwise.
10989  */
10990 static uint32_t
10991 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10992                                  const struct rte_flow_action_age *age,
10993                                  struct rte_flow_error *error)
10994 {
10995         uint32_t age_idx = 0;
10996         struct mlx5_aso_age_action *aso_age;
10997
10998         age_idx = flow_dv_aso_age_alloc(dev, error);
10999         if (!age_idx)
11000                 return 0;
11001         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11002         aso_age->age_params.context = age->context;
11003         aso_age->age_params.timeout = age->timeout;
11004         aso_age->age_params.port_id = dev->data->port_id;
11005         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11006                          __ATOMIC_RELAXED);
11007         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11008                          __ATOMIC_RELAXED);
11009         return age_idx;
11010 }
11011
11012 /**
11013  * Fill the flow with DV spec, lock free
11014  * (mutex should be acquired by caller).
11015  *
11016  * @param[in] dev
11017  *   Pointer to rte_eth_dev structure.
11018  * @param[in, out] dev_flow
11019  *   Pointer to the sub flow.
11020  * @param[in] attr
11021  *   Pointer to the flow attributes.
11022  * @param[in] items
11023  *   Pointer to the list of items.
11024  * @param[in] actions
11025  *   Pointer to the list of actions.
11026  * @param[out] error
11027  *   Pointer to the error structure.
11028  *
11029  * @return
11030  *   0 on success, a negative errno value otherwise and rte_errno is set.
11031  */
11032 static int
11033 flow_dv_translate(struct rte_eth_dev *dev,
11034                   struct mlx5_flow *dev_flow,
11035                   const struct rte_flow_attr *attr,
11036                   const struct rte_flow_item items[],
11037                   const struct rte_flow_action actions[],
11038                   struct rte_flow_error *error)
11039 {
11040         struct mlx5_priv *priv = dev->data->dev_private;
11041         struct mlx5_dev_config *dev_conf = &priv->config;
11042         struct rte_flow *flow = dev_flow->flow;
11043         struct mlx5_flow_handle *handle = dev_flow->handle;
11044         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11045         struct mlx5_flow_rss_desc *rss_desc;
11046         uint64_t item_flags = 0;
11047         uint64_t last_item = 0;
11048         uint64_t action_flags = 0;
11049         struct mlx5_flow_dv_matcher matcher = {
11050                 .mask = {
11051                         .size = sizeof(matcher.mask.buf) -
11052                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11053                 },
11054         };
11055         int actions_n = 0;
11056         bool actions_end = false;
11057         union {
11058                 struct mlx5_flow_dv_modify_hdr_resource res;
11059                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11060                             sizeof(struct mlx5_modification_cmd) *
11061                             (MLX5_MAX_MODIFY_NUM + 1)];
11062         } mhdr_dummy;
11063         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11064         const struct rte_flow_action_count *count = NULL;
11065         const struct rte_flow_action_age *age = NULL;
11066         union flow_dv_attr flow_attr = { .attr = 0 };
11067         uint32_t tag_be;
11068         union mlx5_flow_tbl_key tbl_key;
11069         uint32_t modify_action_position = UINT32_MAX;
11070         void *match_mask = matcher.mask.buf;
11071         void *match_value = dev_flow->dv.value.buf;
11072         uint8_t next_protocol = 0xff;
11073         struct rte_vlan_hdr vlan = { 0 };
11074         struct mlx5_flow_dv_dest_array_resource mdest_res;
11075         struct mlx5_flow_dv_sample_resource sample_res;
11076         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11077         const struct rte_flow_action_sample *sample = NULL;
11078         struct mlx5_flow_sub_actions_list *sample_act;
11079         uint32_t sample_act_pos = UINT32_MAX;
11080         uint32_t num_of_dest = 0;
11081         int tmp_actions_n = 0;
11082         uint32_t table;
11083         int ret = 0;
11084         const struct mlx5_flow_tunnel *tunnel;
11085         struct flow_grp_info grp_info = {
11086                 .external = !!dev_flow->external,
11087                 .transfer = !!attr->transfer,
11088                 .fdb_def_rule = !!priv->fdb_def_rule,
11089                 .skip_scale = dev_flow->skip_scale &
11090                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11091         };
11092
11093         if (!wks)
11094                 return rte_flow_error_set(error, ENOMEM,
11095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11096                                           NULL,
11097                                           "failed to push flow workspace");
11098         rss_desc = &wks->rss_desc;
11099         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11100         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11101         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11102                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11103         /* update normal path action resource into last index of array */
11104         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11105         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11106                  flow_items_to_tunnel(items) :
11107                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11108                  flow_actions_to_tunnel(actions) :
11109                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
11110         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11111                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11112         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11113                                 (dev, tunnel, attr, items, actions);
11114         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11115                                        &grp_info, error);
11116         if (ret)
11117                 return ret;
11118         dev_flow->dv.group = table;
11119         if (attr->transfer)
11120                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11121         /* number of actions must be set to 0 in case of dirty stack. */
11122         mhdr_res->actions_num = 0;
11123         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11124                 /*
11125                  * do not add decap action if match rule drops packet
11126                  * HW rejects rules with decap & drop
11127                  *
11128                  * if tunnel match rule was inserted before matching tunnel set
11129                  * rule flow table used in the match rule must be registered.
11130                  * current implementation handles that in the
11131                  * flow_dv_match_register() at the function end.
11132                  */
11133                 bool add_decap = true;
11134                 const struct rte_flow_action *ptr = actions;
11135
11136                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11137                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11138                                 add_decap = false;
11139                                 break;
11140                         }
11141                 }
11142                 if (add_decap) {
11143                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11144                                                            attr->transfer,
11145                                                            error))
11146                                 return -rte_errno;
11147                         dev_flow->dv.actions[actions_n++] =
11148                                         dev_flow->dv.encap_decap->action;
11149                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11150                 }
11151         }
11152         for (; !actions_end ; actions++) {
11153                 const struct rte_flow_action_queue *queue;
11154                 const struct rte_flow_action_rss *rss;
11155                 const struct rte_flow_action *action = actions;
11156                 const uint8_t *rss_key;
11157                 struct mlx5_flow_tbl_resource *tbl;
11158                 struct mlx5_aso_age_action *age_act;
11159                 uint32_t port_id = 0;
11160                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11161                 int action_type = actions->type;
11162                 const struct rte_flow_action *found_action = NULL;
11163                 uint32_t jump_group = 0;
11164
11165                 if (!mlx5_flow_os_action_supported(action_type))
11166                         return rte_flow_error_set(error, ENOTSUP,
11167                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11168                                                   actions,
11169                                                   "action not supported");
11170                 switch (action_type) {
11171                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11172                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11173                         break;
11174                 case RTE_FLOW_ACTION_TYPE_VOID:
11175                         break;
11176                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11177                         if (flow_dv_translate_action_port_id(dev, action,
11178                                                              &port_id, error))
11179                                 return -rte_errno;
11180                         port_id_resource.port_id = port_id;
11181                         MLX5_ASSERT(!handle->rix_port_id_action);
11182                         if (flow_dv_port_id_action_resource_register
11183                             (dev, &port_id_resource, dev_flow, error))
11184                                 return -rte_errno;
11185                         dev_flow->dv.actions[actions_n++] =
11186                                         dev_flow->dv.port_id_action->action;
11187                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11188                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11189                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11190                         num_of_dest++;
11191                         break;
11192                 case RTE_FLOW_ACTION_TYPE_FLAG:
11193                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11194                         dev_flow->handle->mark = 1;
11195                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11196                                 struct rte_flow_action_mark mark = {
11197                                         .id = MLX5_FLOW_MARK_DEFAULT,
11198                                 };
11199
11200                                 if (flow_dv_convert_action_mark(dev, &mark,
11201                                                                 mhdr_res,
11202                                                                 error))
11203                                         return -rte_errno;
11204                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11205                                 break;
11206                         }
11207                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11208                         /*
11209                          * Only one FLAG or MARK is supported per device flow
11210                          * right now. So the pointer to the tag resource must be
11211                          * zero before the register process.
11212                          */
11213                         MLX5_ASSERT(!handle->dvh.rix_tag);
11214                         if (flow_dv_tag_resource_register(dev, tag_be,
11215                                                           dev_flow, error))
11216                                 return -rte_errno;
11217                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11218                         dev_flow->dv.actions[actions_n++] =
11219                                         dev_flow->dv.tag_resource->action;
11220                         break;
11221                 case RTE_FLOW_ACTION_TYPE_MARK:
11222                         action_flags |= MLX5_FLOW_ACTION_MARK;
11223                         dev_flow->handle->mark = 1;
11224                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11225                                 const struct rte_flow_action_mark *mark =
11226                                         (const struct rte_flow_action_mark *)
11227                                                 actions->conf;
11228
11229                                 if (flow_dv_convert_action_mark(dev, mark,
11230                                                                 mhdr_res,
11231                                                                 error))
11232                                         return -rte_errno;
11233                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11234                                 break;
11235                         }
11236                         /* Fall-through */
11237                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11238                         /* Legacy (non-extensive) MARK action. */
11239                         tag_be = mlx5_flow_mark_set
11240                               (((const struct rte_flow_action_mark *)
11241                                (actions->conf))->id);
11242                         MLX5_ASSERT(!handle->dvh.rix_tag);
11243                         if (flow_dv_tag_resource_register(dev, tag_be,
11244                                                           dev_flow, error))
11245                                 return -rte_errno;
11246                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11247                         dev_flow->dv.actions[actions_n++] =
11248                                         dev_flow->dv.tag_resource->action;
11249                         break;
11250                 case RTE_FLOW_ACTION_TYPE_SET_META:
11251                         if (flow_dv_convert_action_set_meta
11252                                 (dev, mhdr_res, attr,
11253                                  (const struct rte_flow_action_set_meta *)
11254                                   actions->conf, error))
11255                                 return -rte_errno;
11256                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11257                         break;
11258                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11259                         if (flow_dv_convert_action_set_tag
11260                                 (dev, mhdr_res,
11261                                  (const struct rte_flow_action_set_tag *)
11262                                   actions->conf, error))
11263                                 return -rte_errno;
11264                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11265                         break;
11266                 case RTE_FLOW_ACTION_TYPE_DROP:
11267                         action_flags |= MLX5_FLOW_ACTION_DROP;
11268                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11269                         break;
11270                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11271                         queue = actions->conf;
11272                         rss_desc->queue_num = 1;
11273                         rss_desc->queue[0] = queue->index;
11274                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11275                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11276                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11277                         num_of_dest++;
11278                         break;
11279                 case RTE_FLOW_ACTION_TYPE_RSS:
11280                         rss = actions->conf;
11281                         memcpy(rss_desc->queue, rss->queue,
11282                                rss->queue_num * sizeof(uint16_t));
11283                         rss_desc->queue_num = rss->queue_num;
11284                         /* NULL RSS key indicates default RSS key. */
11285                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11286                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11287                         /*
11288                          * rss->level and rss.types should be set in advance
11289                          * when expanding items for RSS.
11290                          */
11291                         action_flags |= MLX5_FLOW_ACTION_RSS;
11292                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11293                                 MLX5_FLOW_FATE_SHARED_RSS :
11294                                 MLX5_FLOW_FATE_QUEUE;
11295                         break;
11296                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11297                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11298                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11299                         __atomic_fetch_add(&age_act->refcnt, 1,
11300                                            __ATOMIC_RELAXED);
11301                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11302                         action_flags |= MLX5_FLOW_ACTION_AGE;
11303                         break;
11304                 case RTE_FLOW_ACTION_TYPE_AGE:
11305                         if (priv->sh->flow_hit_aso_en && attr->group) {
11306                                 /*
11307                                  * Create one shared age action, to be used
11308                                  * by all sub-flows.
11309                                  */
11310                                 if (!flow->age) {
11311                                         flow->age =
11312                                                 flow_dv_translate_create_aso_age
11313                                                         (dev, action->conf,
11314                                                          error);
11315                                         if (!flow->age)
11316                                                 return rte_flow_error_set
11317                                                 (error, rte_errno,
11318                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11319                                                  NULL,
11320                                                  "can't create ASO age action");
11321                                 }
11322                                 dev_flow->dv.actions[actions_n++] =
11323                                           (flow_aso_age_get_by_idx
11324                                                 (dev, flow->age))->dr_action;
11325                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11326                                 break;
11327                         }
11328                         /* Fall-through */
11329                 case RTE_FLOW_ACTION_TYPE_COUNT:
11330                         if (!dev_conf->devx) {
11331                                 return rte_flow_error_set
11332                                               (error, ENOTSUP,
11333                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11334                                                NULL,
11335                                                "count action not supported");
11336                         }
11337                         /* Save information first, will apply later. */
11338                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11339                                 count = action->conf;
11340                         else
11341                                 age = action->conf;
11342                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11343                         break;
11344                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11345                         dev_flow->dv.actions[actions_n++] =
11346                                                 priv->sh->pop_vlan_action;
11347                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11348                         break;
11349                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11350                         if (!(action_flags &
11351                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11352                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11353                         vlan.eth_proto = rte_be_to_cpu_16
11354                              ((((const struct rte_flow_action_of_push_vlan *)
11355                                                    actions->conf)->ethertype));
11356                         found_action = mlx5_flow_find_action
11357                                         (actions + 1,
11358                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11359                         if (found_action)
11360                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11361                         found_action = mlx5_flow_find_action
11362                                         (actions + 1,
11363                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11364                         if (found_action)
11365                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11366                         if (flow_dv_create_action_push_vlan
11367                                             (dev, attr, &vlan, dev_flow, error))
11368                                 return -rte_errno;
11369                         dev_flow->dv.actions[actions_n++] =
11370                                         dev_flow->dv.push_vlan_res->action;
11371                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11372                         break;
11373                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11374                         /* of_vlan_push action handled this action */
11375                         MLX5_ASSERT(action_flags &
11376                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11377                         break;
11378                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11379                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11380                                 break;
11381                         flow_dev_get_vlan_info_from_items(items, &vlan);
11382                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11383                         /* If no VLAN push - this is a modify header action */
11384                         if (flow_dv_convert_action_modify_vlan_vid
11385                                                 (mhdr_res, actions, error))
11386                                 return -rte_errno;
11387                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11388                         break;
11389                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11390                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11391                         if (flow_dv_create_action_l2_encap(dev, actions,
11392                                                            dev_flow,
11393                                                            attr->transfer,
11394                                                            error))
11395                                 return -rte_errno;
11396                         dev_flow->dv.actions[actions_n++] =
11397                                         dev_flow->dv.encap_decap->action;
11398                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11399                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11400                                 sample_act->action_flags |=
11401                                                         MLX5_FLOW_ACTION_ENCAP;
11402                         break;
11403                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11404                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11405                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11406                                                            attr->transfer,
11407                                                            error))
11408                                 return -rte_errno;
11409                         dev_flow->dv.actions[actions_n++] =
11410                                         dev_flow->dv.encap_decap->action;
11411                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11412                         break;
11413                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11414                         /* Handle encap with preceding decap. */
11415                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11416                                 if (flow_dv_create_action_raw_encap
11417                                         (dev, actions, dev_flow, attr, error))
11418                                         return -rte_errno;
11419                                 dev_flow->dv.actions[actions_n++] =
11420                                         dev_flow->dv.encap_decap->action;
11421                         } else {
11422                                 /* Handle encap without preceding decap. */
11423                                 if (flow_dv_create_action_l2_encap
11424                                     (dev, actions, dev_flow, attr->transfer,
11425                                      error))
11426                                         return -rte_errno;
11427                                 dev_flow->dv.actions[actions_n++] =
11428                                         dev_flow->dv.encap_decap->action;
11429                         }
11430                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11431                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11432                                 sample_act->action_flags |=
11433                                                         MLX5_FLOW_ACTION_ENCAP;
11434                         break;
11435                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11436                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11437                                 ;
11438                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11439                                 if (flow_dv_create_action_l2_decap
11440                                     (dev, dev_flow, attr->transfer, error))
11441                                         return -rte_errno;
11442                                 dev_flow->dv.actions[actions_n++] =
11443                                         dev_flow->dv.encap_decap->action;
11444                         }
11445                         /* If decap is followed by encap, handle it at encap. */
11446                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11447                         break;
11448                 case RTE_FLOW_ACTION_TYPE_JUMP:
11449                         jump_group = ((const struct rte_flow_action_jump *)
11450                                                         action->conf)->group;
11451                         grp_info.std_tbl_fix = 0;
11452                         if (dev_flow->skip_scale &
11453                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11454                                 grp_info.skip_scale = 1;
11455                         else
11456                                 grp_info.skip_scale = 0;
11457                         ret = mlx5_flow_group_to_table(dev, tunnel,
11458                                                        jump_group,
11459                                                        &table,
11460                                                        &grp_info, error);
11461                         if (ret)
11462                                 return ret;
11463                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11464                                                        attr->transfer,
11465                                                        !!dev_flow->external,
11466                                                        tunnel, jump_group, 0,
11467                                                        error);
11468                         if (!tbl)
11469                                 return rte_flow_error_set
11470                                                 (error, errno,
11471                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11472                                                  NULL,
11473                                                  "cannot create jump action.");
11474                         if (flow_dv_jump_tbl_resource_register
11475                             (dev, tbl, dev_flow, error)) {
11476                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11477                                 return rte_flow_error_set
11478                                                 (error, errno,
11479                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11480                                                  NULL,
11481                                                  "cannot create jump action.");
11482                         }
11483                         dev_flow->dv.actions[actions_n++] =
11484                                         dev_flow->dv.jump->action;
11485                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11486                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11487                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11488                         num_of_dest++;
11489                         break;
11490                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11491                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11492                         if (flow_dv_convert_action_modify_mac
11493                                         (mhdr_res, actions, error))
11494                                 return -rte_errno;
11495                         action_flags |= actions->type ==
11496                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11497                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11498                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11499                         break;
11500                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11501                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11502                         if (flow_dv_convert_action_modify_ipv4
11503                                         (mhdr_res, actions, error))
11504                                 return -rte_errno;
11505                         action_flags |= actions->type ==
11506                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11507                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11508                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11509                         break;
11510                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11511                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11512                         if (flow_dv_convert_action_modify_ipv6
11513                                         (mhdr_res, actions, error))
11514                                 return -rte_errno;
11515                         action_flags |= actions->type ==
11516                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11517                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11518                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11519                         break;
11520                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11521                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11522                         if (flow_dv_convert_action_modify_tp
11523                                         (mhdr_res, actions, items,
11524                                          &flow_attr, dev_flow, !!(action_flags &
11525                                          MLX5_FLOW_ACTION_DECAP), error))
11526                                 return -rte_errno;
11527                         action_flags |= actions->type ==
11528                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11529                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11530                                         MLX5_FLOW_ACTION_SET_TP_DST;
11531                         break;
11532                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11533                         if (flow_dv_convert_action_modify_dec_ttl
11534                                         (mhdr_res, items, &flow_attr, dev_flow,
11535                                          !!(action_flags &
11536                                          MLX5_FLOW_ACTION_DECAP), error))
11537                                 return -rte_errno;
11538                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11539                         break;
11540                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11541                         if (flow_dv_convert_action_modify_ttl
11542                                         (mhdr_res, actions, items, &flow_attr,
11543                                          dev_flow, !!(action_flags &
11544                                          MLX5_FLOW_ACTION_DECAP), error))
11545                                 return -rte_errno;
11546                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11547                         break;
11548                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11549                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11550                         if (flow_dv_convert_action_modify_tcp_seq
11551                                         (mhdr_res, actions, error))
11552                                 return -rte_errno;
11553                         action_flags |= actions->type ==
11554                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11555                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11556                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11557                         break;
11558
11559                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11560                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11561                         if (flow_dv_convert_action_modify_tcp_ack
11562                                         (mhdr_res, actions, error))
11563                                 return -rte_errno;
11564                         action_flags |= actions->type ==
11565                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11566                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11567                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11568                         break;
11569                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11570                         if (flow_dv_convert_action_set_reg
11571                                         (mhdr_res, actions, error))
11572                                 return -rte_errno;
11573                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11574                         break;
11575                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11576                         if (flow_dv_convert_action_copy_mreg
11577                                         (dev, mhdr_res, actions, error))
11578                                 return -rte_errno;
11579                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11580                         break;
11581                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11582                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11583                         dev_flow->handle->fate_action =
11584                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11585                         break;
11586                 case RTE_FLOW_ACTION_TYPE_METER:
11587                         if (!wks->fm)
11588                                 return rte_flow_error_set(error, rte_errno,
11589                                         RTE_FLOW_ERROR_TYPE_ACTION,
11590                                         NULL, "Failed to get meter in flow.");
11591                         /* Set the meter action. */
11592                         dev_flow->dv.actions[actions_n++] =
11593                                 wks->fm->mfts->meter_action;
11594                         action_flags |= MLX5_FLOW_ACTION_METER;
11595                         break;
11596                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11597                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11598                                                               actions, error))
11599                                 return -rte_errno;
11600                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11601                         break;
11602                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11603                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11604                                                               actions, error))
11605                                 return -rte_errno;
11606                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11607                         break;
11608                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11609                         sample_act_pos = actions_n;
11610                         sample = (const struct rte_flow_action_sample *)
11611                                  action->conf;
11612                         actions_n++;
11613                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11614                         /* put encap action into group if work with port id */
11615                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11616                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11617                                 sample_act->action_flags |=
11618                                                         MLX5_FLOW_ACTION_ENCAP;
11619                         break;
11620                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11621                         if (flow_dv_convert_action_modify_field
11622                                         (dev, mhdr_res, actions, attr, error))
11623                                 return -rte_errno;
11624                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11625                         break;
11626                 case RTE_FLOW_ACTION_TYPE_END:
11627                         actions_end = true;
11628                         if (mhdr_res->actions_num) {
11629                                 /* create modify action if needed. */
11630                                 if (flow_dv_modify_hdr_resource_register
11631                                         (dev, mhdr_res, dev_flow, error))
11632                                         return -rte_errno;
11633                                 dev_flow->dv.actions[modify_action_position] =
11634                                         handle->dvh.modify_hdr->action;
11635                         }
11636                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11637                                 /*
11638                                  * Create one count action, to be used
11639                                  * by all sub-flows.
11640                                  */
11641                                 if (!flow->counter) {
11642                                         flow->counter =
11643                                                 flow_dv_translate_create_counter
11644                                                         (dev, dev_flow, count,
11645                                                          age);
11646                                         if (!flow->counter)
11647                                                 return rte_flow_error_set
11648                                                 (error, rte_errno,
11649                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11650                                                  NULL, "cannot create counter"
11651                                                  " object.");
11652                                 }
11653                                 dev_flow->dv.actions[actions_n] =
11654                                           (flow_dv_counter_get_by_idx(dev,
11655                                           flow->counter, NULL))->action;
11656                                 actions_n++;
11657                         }
11658                 default:
11659                         break;
11660                 }
11661                 if (mhdr_res->actions_num &&
11662                     modify_action_position == UINT32_MAX)
11663                         modify_action_position = actions_n++;
11664         }
11665         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11666                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11667                 int item_type = items->type;
11668
11669                 if (!mlx5_flow_os_item_supported(item_type))
11670                         return rte_flow_error_set(error, ENOTSUP,
11671                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11672                                                   NULL, "item not supported");
11673                 switch (item_type) {
11674                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11675                         flow_dv_translate_item_port_id
11676                                 (dev, match_mask, match_value, items, attr);
11677                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11678                         break;
11679                 case RTE_FLOW_ITEM_TYPE_ETH:
11680                         flow_dv_translate_item_eth(match_mask, match_value,
11681                                                    items, tunnel,
11682                                                    dev_flow->dv.group);
11683                         matcher.priority = action_flags &
11684                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11685                                         !dev_flow->external ?
11686                                         MLX5_PRIORITY_MAP_L3 :
11687                                         MLX5_PRIORITY_MAP_L2;
11688                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11689                                              MLX5_FLOW_LAYER_OUTER_L2;
11690                         break;
11691                 case RTE_FLOW_ITEM_TYPE_VLAN:
11692                         flow_dv_translate_item_vlan(dev_flow,
11693                                                     match_mask, match_value,
11694                                                     items, tunnel,
11695                                                     dev_flow->dv.group);
11696                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11697                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11698                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11699                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11700                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11701                         break;
11702                 case RTE_FLOW_ITEM_TYPE_IPV4:
11703                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11704                                                   &item_flags, &tunnel);
11705                         flow_dv_translate_item_ipv4(match_mask, match_value,
11706                                                     items, tunnel,
11707                                                     dev_flow->dv.group);
11708                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11709                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11710                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11711                         if (items->mask != NULL &&
11712                             ((const struct rte_flow_item_ipv4 *)
11713                              items->mask)->hdr.next_proto_id) {
11714                                 next_protocol =
11715                                         ((const struct rte_flow_item_ipv4 *)
11716                                          (items->spec))->hdr.next_proto_id;
11717                                 next_protocol &=
11718                                         ((const struct rte_flow_item_ipv4 *)
11719                                          (items->mask))->hdr.next_proto_id;
11720                         } else {
11721                                 /* Reset for inner layer. */
11722                                 next_protocol = 0xff;
11723                         }
11724                         break;
11725                 case RTE_FLOW_ITEM_TYPE_IPV6:
11726                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11727                                                   &item_flags, &tunnel);
11728                         flow_dv_translate_item_ipv6(match_mask, match_value,
11729                                                     items, tunnel,
11730                                                     dev_flow->dv.group);
11731                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11732                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11733                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11734                         if (items->mask != NULL &&
11735                             ((const struct rte_flow_item_ipv6 *)
11736                              items->mask)->hdr.proto) {
11737                                 next_protocol =
11738                                         ((const struct rte_flow_item_ipv6 *)
11739                                          items->spec)->hdr.proto;
11740                                 next_protocol &=
11741                                         ((const struct rte_flow_item_ipv6 *)
11742                                          items->mask)->hdr.proto;
11743                         } else {
11744                                 /* Reset for inner layer. */
11745                                 next_protocol = 0xff;
11746                         }
11747                         break;
11748                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11749                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11750                                                              match_value,
11751                                                              items, tunnel);
11752                         last_item = tunnel ?
11753                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11754                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11755                         if (items->mask != NULL &&
11756                             ((const struct rte_flow_item_ipv6_frag_ext *)
11757                              items->mask)->hdr.next_header) {
11758                                 next_protocol =
11759                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11760                                  items->spec)->hdr.next_header;
11761                                 next_protocol &=
11762                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11763                                  items->mask)->hdr.next_header;
11764                         } else {
11765                                 /* Reset for inner layer. */
11766                                 next_protocol = 0xff;
11767                         }
11768                         break;
11769                 case RTE_FLOW_ITEM_TYPE_TCP:
11770                         flow_dv_translate_item_tcp(match_mask, match_value,
11771                                                    items, tunnel);
11772                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11773                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11774                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11775                         break;
11776                 case RTE_FLOW_ITEM_TYPE_UDP:
11777                         flow_dv_translate_item_udp(match_mask, match_value,
11778                                                    items, tunnel);
11779                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11780                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11781                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11782                         break;
11783                 case RTE_FLOW_ITEM_TYPE_GRE:
11784                         flow_dv_translate_item_gre(match_mask, match_value,
11785                                                    items, tunnel);
11786                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11787                         last_item = MLX5_FLOW_LAYER_GRE;
11788                         break;
11789                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11790                         flow_dv_translate_item_gre_key(match_mask,
11791                                                        match_value, items);
11792                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11793                         break;
11794                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11795                         flow_dv_translate_item_nvgre(match_mask, match_value,
11796                                                      items, tunnel);
11797                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11798                         last_item = MLX5_FLOW_LAYER_GRE;
11799                         break;
11800                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11801                         flow_dv_translate_item_vxlan(match_mask, match_value,
11802                                                      items, tunnel);
11803                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11804                         last_item = MLX5_FLOW_LAYER_VXLAN;
11805                         break;
11806                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11807                         flow_dv_translate_item_vxlan_gpe(match_mask,
11808                                                          match_value, items,
11809                                                          tunnel);
11810                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11811                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11812                         break;
11813                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11814                         flow_dv_translate_item_geneve(match_mask, match_value,
11815                                                       items, tunnel);
11816                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11817                         last_item = MLX5_FLOW_LAYER_GENEVE;
11818                         break;
11819                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11820                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11821                                                           match_value,
11822                                                           items, error);
11823                         if (ret)
11824                                 return rte_flow_error_set(error, -ret,
11825                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11826                                         "cannot create GENEVE TLV option");
11827                         flow->geneve_tlv_option = 1;
11828                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11829                         break;
11830                 case RTE_FLOW_ITEM_TYPE_MPLS:
11831                         flow_dv_translate_item_mpls(match_mask, match_value,
11832                                                     items, last_item, tunnel);
11833                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11834                         last_item = MLX5_FLOW_LAYER_MPLS;
11835                         break;
11836                 case RTE_FLOW_ITEM_TYPE_MARK:
11837                         flow_dv_translate_item_mark(dev, match_mask,
11838                                                     match_value, items);
11839                         last_item = MLX5_FLOW_ITEM_MARK;
11840                         break;
11841                 case RTE_FLOW_ITEM_TYPE_META:
11842                         flow_dv_translate_item_meta(dev, match_mask,
11843                                                     match_value, attr, items);
11844                         last_item = MLX5_FLOW_ITEM_METADATA;
11845                         break;
11846                 case RTE_FLOW_ITEM_TYPE_ICMP:
11847                         flow_dv_translate_item_icmp(match_mask, match_value,
11848                                                     items, tunnel);
11849                         last_item = MLX5_FLOW_LAYER_ICMP;
11850                         break;
11851                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11852                         flow_dv_translate_item_icmp6(match_mask, match_value,
11853                                                       items, tunnel);
11854                         last_item = MLX5_FLOW_LAYER_ICMP6;
11855                         break;
11856                 case RTE_FLOW_ITEM_TYPE_TAG:
11857                         flow_dv_translate_item_tag(dev, match_mask,
11858                                                    match_value, items);
11859                         last_item = MLX5_FLOW_ITEM_TAG;
11860                         break;
11861                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11862                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11863                                                         match_value, items);
11864                         last_item = MLX5_FLOW_ITEM_TAG;
11865                         break;
11866                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11867                         flow_dv_translate_item_tx_queue(dev, match_mask,
11868                                                         match_value,
11869                                                         items);
11870                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11871                         break;
11872                 case RTE_FLOW_ITEM_TYPE_GTP:
11873                         flow_dv_translate_item_gtp(match_mask, match_value,
11874                                                    items, tunnel);
11875                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11876                         last_item = MLX5_FLOW_LAYER_GTP;
11877                         break;
11878                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11879                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11880                                                           match_value,
11881                                                           items);
11882                         if (ret)
11883                                 return rte_flow_error_set(error, -ret,
11884                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11885                                         "cannot create GTP PSC item");
11886                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11887                         break;
11888                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11889                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11890                                 /* Create it only the first time to be used. */
11891                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11892                                 if (ret)
11893                                         return rte_flow_error_set
11894                                                 (error, -ret,
11895                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11896                                                 NULL,
11897                                                 "cannot create eCPRI parser");
11898                         }
11899                         /* Adjust the length matcher and device flow value. */
11900                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11901                         dev_flow->dv.value.size =
11902                                         MLX5_ST_SZ_BYTES(fte_match_param);
11903                         flow_dv_translate_item_ecpri(dev, match_mask,
11904                                                      match_value, items);
11905                         /* No other protocol should follow eCPRI layer. */
11906                         last_item = MLX5_FLOW_LAYER_ECPRI;
11907                         break;
11908                 default:
11909                         break;
11910                 }
11911                 item_flags |= last_item;
11912         }
11913         /*
11914          * When E-Switch mode is enabled, we have two cases where we need to
11915          * set the source port manually.
11916          * The first one, is in case of Nic steering rule, and the second is
11917          * E-Switch rule where no port_id item was found. In both cases
11918          * the source port is set according the current port in use.
11919          */
11920         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11921             (priv->representor || priv->master)) {
11922                 if (flow_dv_translate_item_port_id(dev, match_mask,
11923                                                    match_value, NULL, attr))
11924                         return -rte_errno;
11925         }
11926 #ifdef RTE_LIBRTE_MLX5_DEBUG
11927         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11928                                               dev_flow->dv.value.buf));
11929 #endif
11930         /*
11931          * Layers may be already initialized from prefix flow if this dev_flow
11932          * is the suffix flow.
11933          */
11934         handle->layers |= item_flags;
11935         if (action_flags & MLX5_FLOW_ACTION_RSS)
11936                 flow_dv_hashfields_set(dev_flow, rss_desc);
11937         /* If has RSS action in the sample action, the Sample/Mirror resource
11938          * should be registered after the hash filed be update.
11939          */
11940         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11941                 ret = flow_dv_translate_action_sample(dev,
11942                                                       sample,
11943                                                       dev_flow, attr,
11944                                                       &num_of_dest,
11945                                                       sample_actions,
11946                                                       &sample_res,
11947                                                       error);
11948                 if (ret < 0)
11949                         return ret;
11950                 ret = flow_dv_create_action_sample(dev,
11951                                                    dev_flow,
11952                                                    num_of_dest,
11953                                                    &sample_res,
11954                                                    &mdest_res,
11955                                                    sample_actions,
11956                                                    action_flags,
11957                                                    error);
11958                 if (ret < 0)
11959                         return rte_flow_error_set
11960                                                 (error, rte_errno,
11961                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11962                                                 NULL,
11963                                                 "cannot create sample action");
11964                 if (num_of_dest > 1) {
11965                         dev_flow->dv.actions[sample_act_pos] =
11966                         dev_flow->dv.dest_array_res->action;
11967                 } else {
11968                         dev_flow->dv.actions[sample_act_pos] =
11969                         dev_flow->dv.sample_res->verbs_action;
11970                 }
11971         }
11972         /*
11973          * For multiple destination (sample action with ratio=1), the encap
11974          * action and port id action will be combined into group action.
11975          * So need remove the original these actions in the flow and only
11976          * use the sample action instead of.
11977          */
11978         if (num_of_dest > 1 &&
11979             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11980                 int i;
11981                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11982
11983                 for (i = 0; i < actions_n; i++) {
11984                         if ((sample_act->dr_encap_action &&
11985                                 sample_act->dr_encap_action ==
11986                                 dev_flow->dv.actions[i]) ||
11987                                 (sample_act->dr_port_id_action &&
11988                                 sample_act->dr_port_id_action ==
11989                                 dev_flow->dv.actions[i]) ||
11990                                 (sample_act->dr_jump_action &&
11991                                 sample_act->dr_jump_action ==
11992                                 dev_flow->dv.actions[i]))
11993                                 continue;
11994                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11995                 }
11996                 memcpy((void *)dev_flow->dv.actions,
11997                                 (void *)temp_actions,
11998                                 tmp_actions_n * sizeof(void *));
11999                 actions_n = tmp_actions_n;
12000         }
12001         dev_flow->dv.actions_n = actions_n;
12002         dev_flow->act_flags = action_flags;
12003         /* Register matcher. */
12004         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12005                                     matcher.mask.size);
12006         matcher.priority = mlx5_get_matcher_priority(dev, attr,
12007                                         matcher.priority);
12008         /* reserved field no needs to be set to 0 here. */
12009         tbl_key.domain = attr->transfer;
12010         tbl_key.direction = attr->egress;
12011         tbl_key.table_id = dev_flow->dv.group;
12012         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12013                                      tunnel, attr->group, error))
12014                 return -rte_errno;
12015         return 0;
12016 }
12017
12018 /**
12019  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12020  * and tunnel.
12021  *
12022  * @param[in, out] action
12023  *   Shred RSS action holding hash RX queue objects.
12024  * @param[in] hash_fields
12025  *   Defines combination of packet fields to participate in RX hash.
12026  * @param[in] tunnel
12027  *   Tunnel type
12028  * @param[in] hrxq_idx
12029  *   Hash RX queue index to set.
12030  *
12031  * @return
12032  *   0 on success, otherwise negative errno value.
12033  */
12034 static int
12035 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12036                               const uint64_t hash_fields,
12037                               uint32_t hrxq_idx)
12038 {
12039         uint32_t *hrxqs = action->hrxq;
12040
12041         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12042         case MLX5_RSS_HASH_IPV4:
12043                 /* fall-through. */
12044         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12045                 /* fall-through. */
12046         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12047                 hrxqs[0] = hrxq_idx;
12048                 return 0;
12049         case MLX5_RSS_HASH_IPV4_TCP:
12050                 /* fall-through. */
12051         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12052                 /* fall-through. */
12053         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12054                 hrxqs[1] = hrxq_idx;
12055                 return 0;
12056         case MLX5_RSS_HASH_IPV4_UDP:
12057                 /* fall-through. */
12058         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12059                 /* fall-through. */
12060         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12061                 hrxqs[2] = hrxq_idx;
12062                 return 0;
12063         case MLX5_RSS_HASH_IPV6:
12064                 /* fall-through. */
12065         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12066                 /* fall-through. */
12067         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12068                 hrxqs[3] = hrxq_idx;
12069                 return 0;
12070         case MLX5_RSS_HASH_IPV6_TCP:
12071                 /* fall-through. */
12072         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12073                 /* fall-through. */
12074         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12075                 hrxqs[4] = hrxq_idx;
12076                 return 0;
12077         case MLX5_RSS_HASH_IPV6_UDP:
12078                 /* fall-through. */
12079         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12080                 /* fall-through. */
12081         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12082                 hrxqs[5] = hrxq_idx;
12083                 return 0;
12084         case MLX5_RSS_HASH_NONE:
12085                 hrxqs[6] = hrxq_idx;
12086                 return 0;
12087         default:
12088                 return -1;
12089         }
12090 }
12091
12092 /**
12093  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12094  * and tunnel.
12095  *
12096  * @param[in] dev
12097  *   Pointer to the Ethernet device structure.
12098  * @param[in] idx
12099  *   Shared RSS action ID holding hash RX queue objects.
12100  * @param[in] hash_fields
12101  *   Defines combination of packet fields to participate in RX hash.
12102  * @param[in] tunnel
12103  *   Tunnel type
12104  *
12105  * @return
12106  *   Valid hash RX queue index, otherwise 0.
12107  */
12108 static uint32_t
12109 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12110                                  const uint64_t hash_fields)
12111 {
12112         struct mlx5_priv *priv = dev->data->dev_private;
12113         struct mlx5_shared_action_rss *shared_rss =
12114             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12115         const uint32_t *hrxqs = shared_rss->hrxq;
12116
12117         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12118         case MLX5_RSS_HASH_IPV4:
12119                 /* fall-through. */
12120         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12121                 /* fall-through. */
12122         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12123                 return hrxqs[0];
12124         case MLX5_RSS_HASH_IPV4_TCP:
12125                 /* fall-through. */
12126         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12127                 /* fall-through. */
12128         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12129                 return hrxqs[1];
12130         case MLX5_RSS_HASH_IPV4_UDP:
12131                 /* fall-through. */
12132         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12133                 /* fall-through. */
12134         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12135                 return hrxqs[2];
12136         case MLX5_RSS_HASH_IPV6:
12137                 /* fall-through. */
12138         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12139                 /* fall-through. */
12140         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12141                 return hrxqs[3];
12142         case MLX5_RSS_HASH_IPV6_TCP:
12143                 /* fall-through. */
12144         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12145                 /* fall-through. */
12146         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12147                 return hrxqs[4];
12148         case MLX5_RSS_HASH_IPV6_UDP:
12149                 /* fall-through. */
12150         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12151                 /* fall-through. */
12152         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12153                 return hrxqs[5];
12154         case MLX5_RSS_HASH_NONE:
12155                 return hrxqs[6];
12156         default:
12157                 return 0;
12158         }
12159
12160 }
12161
12162 /**
12163  * Apply the flow to the NIC, lock free,
12164  * (mutex should be acquired by caller).
12165  *
12166  * @param[in] dev
12167  *   Pointer to the Ethernet device structure.
12168  * @param[in, out] flow
12169  *   Pointer to flow structure.
12170  * @param[out] error
12171  *   Pointer to error structure.
12172  *
12173  * @return
12174  *   0 on success, a negative errno value otherwise and rte_errno is set.
12175  */
12176 static int
12177 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12178               struct rte_flow_error *error)
12179 {
12180         struct mlx5_flow_dv_workspace *dv;
12181         struct mlx5_flow_handle *dh;
12182         struct mlx5_flow_handle_dv *dv_h;
12183         struct mlx5_flow *dev_flow;
12184         struct mlx5_priv *priv = dev->data->dev_private;
12185         uint32_t handle_idx;
12186         int n;
12187         int err;
12188         int idx;
12189         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12190         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12191
12192         MLX5_ASSERT(wks);
12193         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12194                 dev_flow = &wks->flows[idx];
12195                 dv = &dev_flow->dv;
12196                 dh = dev_flow->handle;
12197                 dv_h = &dh->dvh;
12198                 n = dv->actions_n;
12199                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12200                         if (dv->transfer) {
12201                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12202                                 dv->actions[n++] = priv->sh->dr_drop_action;
12203                         } else {
12204 #ifdef HAVE_MLX5DV_DR
12205                                 /* DR supports drop action placeholder. */
12206                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12207                                 dv->actions[n++] = priv->sh->dr_drop_action;
12208 #else
12209                                 /* For DV we use the explicit drop queue. */
12210                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12211                                 dv->actions[n++] =
12212                                                 priv->drop_queue.hrxq->action;
12213 #endif
12214                         }
12215                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12216                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12217                         struct mlx5_hrxq *hrxq;
12218                         uint32_t hrxq_idx;
12219
12220                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12221                                                     &hrxq_idx);
12222                         if (!hrxq) {
12223                                 rte_flow_error_set
12224                                         (error, rte_errno,
12225                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12226                                          "cannot get hash queue");
12227                                 goto error;
12228                         }
12229                         dh->rix_hrxq = hrxq_idx;
12230                         dv->actions[n++] = hrxq->action;
12231                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12232                         struct mlx5_hrxq *hrxq = NULL;
12233                         uint32_t hrxq_idx;
12234
12235                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12236                                                 rss_desc->shared_rss,
12237                                                 dev_flow->hash_fields);
12238                         if (hrxq_idx)
12239                                 hrxq = mlx5_ipool_get
12240                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12241                                          hrxq_idx);
12242                         if (!hrxq) {
12243                                 rte_flow_error_set
12244                                         (error, rte_errno,
12245                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12246                                          "cannot get hash queue");
12247                                 goto error;
12248                         }
12249                         dh->rix_srss = rss_desc->shared_rss;
12250                         dv->actions[n++] = hrxq->action;
12251                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12252                         if (!priv->sh->default_miss_action) {
12253                                 rte_flow_error_set
12254                                         (error, rte_errno,
12255                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12256                                          "default miss action not be created.");
12257                                 goto error;
12258                         }
12259                         dv->actions[n++] = priv->sh->default_miss_action;
12260                 }
12261                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12262                                                (void *)&dv->value, n,
12263                                                dv->actions, &dh->drv_flow);
12264                 if (err) {
12265                         rte_flow_error_set(error, errno,
12266                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12267                                            NULL,
12268                                            "hardware refuses to create flow");
12269                         goto error;
12270                 }
12271                 if (priv->vmwa_context &&
12272                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12273                         /*
12274                          * The rule contains the VLAN pattern.
12275                          * For VF we are going to create VLAN
12276                          * interface to make hypervisor set correct
12277                          * e-Switch vport context.
12278                          */
12279                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12280                 }
12281         }
12282         return 0;
12283 error:
12284         err = rte_errno; /* Save rte_errno before cleanup. */
12285         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12286                        handle_idx, dh, next) {
12287                 /* hrxq is union, don't clear it if the flag is not set. */
12288                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12289                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12290                         dh->rix_hrxq = 0;
12291                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12292                         dh->rix_srss = 0;
12293                 }
12294                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12295                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12296         }
12297         rte_errno = err; /* Restore rte_errno. */
12298         return -rte_errno;
12299 }
12300
12301 void
12302 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12303                           struct mlx5_cache_entry *entry)
12304 {
12305         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12306                                                           entry);
12307
12308         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12309         mlx5_free(cache);
12310 }
12311
12312 /**
12313  * Release the flow matcher.
12314  *
12315  * @param dev
12316  *   Pointer to Ethernet device.
12317  * @param port_id
12318  *   Index to port ID action resource.
12319  *
12320  * @return
12321  *   1 while a reference on it exists, 0 when freed.
12322  */
12323 static int
12324 flow_dv_matcher_release(struct rte_eth_dev *dev,
12325                         struct mlx5_flow_handle *handle)
12326 {
12327         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12328         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12329                                                             typeof(*tbl), tbl);
12330         int ret;
12331
12332         MLX5_ASSERT(matcher->matcher_object);
12333         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12334         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12335         return ret;
12336 }
12337
12338 /**
12339  * Release encap_decap resource.
12340  *
12341  * @param list
12342  *   Pointer to the hash list.
12343  * @param entry
12344  *   Pointer to exist resource entry object.
12345  */
12346 void
12347 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12348                               struct mlx5_hlist_entry *entry)
12349 {
12350         struct mlx5_dev_ctx_shared *sh = list->ctx;
12351         struct mlx5_flow_dv_encap_decap_resource *res =
12352                 container_of(entry, typeof(*res), entry);
12353
12354         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12355         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12356 }
12357
12358 /**
12359  * Release an encap/decap resource.
12360  *
12361  * @param dev
12362  *   Pointer to Ethernet device.
12363  * @param encap_decap_idx
12364  *   Index of encap decap resource.
12365  *
12366  * @return
12367  *   1 while a reference on it exists, 0 when freed.
12368  */
12369 static int
12370 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12371                                      uint32_t encap_decap_idx)
12372 {
12373         struct mlx5_priv *priv = dev->data->dev_private;
12374         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12375
12376         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12377                                         encap_decap_idx);
12378         if (!cache_resource)
12379                 return 0;
12380         MLX5_ASSERT(cache_resource->action);
12381         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12382                                      &cache_resource->entry);
12383 }
12384
12385 /**
12386  * Release an jump to table action resource.
12387  *
12388  * @param dev
12389  *   Pointer to Ethernet device.
12390  * @param rix_jump
12391  *   Index to the jump action resource.
12392  *
12393  * @return
12394  *   1 while a reference on it exists, 0 when freed.
12395  */
12396 static int
12397 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12398                                   uint32_t rix_jump)
12399 {
12400         struct mlx5_priv *priv = dev->data->dev_private;
12401         struct mlx5_flow_tbl_data_entry *tbl_data;
12402
12403         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12404                                   rix_jump);
12405         if (!tbl_data)
12406                 return 0;
12407         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12408 }
12409
12410 void
12411 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12412                          struct mlx5_hlist_entry *entry)
12413 {
12414         struct mlx5_flow_dv_modify_hdr_resource *res =
12415                 container_of(entry, typeof(*res), entry);
12416
12417         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12418         mlx5_free(entry);
12419 }
12420
12421 /**
12422  * Release a modify-header resource.
12423  *
12424  * @param dev
12425  *   Pointer to Ethernet device.
12426  * @param handle
12427  *   Pointer to mlx5_flow_handle.
12428  *
12429  * @return
12430  *   1 while a reference on it exists, 0 when freed.
12431  */
12432 static int
12433 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12434                                     struct mlx5_flow_handle *handle)
12435 {
12436         struct mlx5_priv *priv = dev->data->dev_private;
12437         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12438
12439         MLX5_ASSERT(entry->action);
12440         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12441 }
12442
12443 void
12444 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12445                           struct mlx5_cache_entry *entry)
12446 {
12447         struct mlx5_dev_ctx_shared *sh = list->ctx;
12448         struct mlx5_flow_dv_port_id_action_resource *cache =
12449                         container_of(entry, typeof(*cache), entry);
12450
12451         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12452         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12453 }
12454
12455 /**
12456  * Release port ID action resource.
12457  *
12458  * @param dev
12459  *   Pointer to Ethernet device.
12460  * @param handle
12461  *   Pointer to mlx5_flow_handle.
12462  *
12463  * @return
12464  *   1 while a reference on it exists, 0 when freed.
12465  */
12466 static int
12467 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12468                                         uint32_t port_id)
12469 {
12470         struct mlx5_priv *priv = dev->data->dev_private;
12471         struct mlx5_flow_dv_port_id_action_resource *cache;
12472
12473         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12474         if (!cache)
12475                 return 0;
12476         MLX5_ASSERT(cache->action);
12477         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12478                                      &cache->entry);
12479 }
12480
12481 /**
12482  * Release shared RSS action resource.
12483  *
12484  * @param dev
12485  *   Pointer to Ethernet device.
12486  * @param srss
12487  *   Shared RSS action index.
12488  */
12489 static void
12490 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12491 {
12492         struct mlx5_priv *priv = dev->data->dev_private;
12493         struct mlx5_shared_action_rss *shared_rss;
12494
12495         shared_rss = mlx5_ipool_get
12496                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12497         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12498 }
12499
12500 void
12501 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12502                             struct mlx5_cache_entry *entry)
12503 {
12504         struct mlx5_dev_ctx_shared *sh = list->ctx;
12505         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12506                         container_of(entry, typeof(*cache), entry);
12507
12508         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12509         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12510 }
12511
12512 /**
12513  * Release push vlan action resource.
12514  *
12515  * @param dev
12516  *   Pointer to Ethernet device.
12517  * @param handle
12518  *   Pointer to mlx5_flow_handle.
12519  *
12520  * @return
12521  *   1 while a reference on it exists, 0 when freed.
12522  */
12523 static int
12524 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12525                                           struct mlx5_flow_handle *handle)
12526 {
12527         struct mlx5_priv *priv = dev->data->dev_private;
12528         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12529         uint32_t idx = handle->dvh.rix_push_vlan;
12530
12531         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12532         if (!cache)
12533                 return 0;
12534         MLX5_ASSERT(cache->action);
12535         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12536                                      &cache->entry);
12537 }
12538
12539 /**
12540  * Release the fate resource.
12541  *
12542  * @param dev
12543  *   Pointer to Ethernet device.
12544  * @param handle
12545  *   Pointer to mlx5_flow_handle.
12546  */
12547 static void
12548 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12549                                struct mlx5_flow_handle *handle)
12550 {
12551         if (!handle->rix_fate)
12552                 return;
12553         switch (handle->fate_action) {
12554         case MLX5_FLOW_FATE_QUEUE:
12555                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12556                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12557                 break;
12558         case MLX5_FLOW_FATE_JUMP:
12559                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12560                 break;
12561         case MLX5_FLOW_FATE_PORT_ID:
12562                 flow_dv_port_id_action_resource_release(dev,
12563                                 handle->rix_port_id_action);
12564                 break;
12565         default:
12566                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12567                 break;
12568         }
12569         handle->rix_fate = 0;
12570 }
12571
12572 void
12573 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12574                          struct mlx5_cache_entry *entry)
12575 {
12576         struct mlx5_flow_dv_sample_resource *cache_resource =
12577                         container_of(entry, typeof(*cache_resource), entry);
12578         struct rte_eth_dev *dev = cache_resource->dev;
12579         struct mlx5_priv *priv = dev->data->dev_private;
12580
12581         if (cache_resource->verbs_action)
12582                 claim_zero(mlx5_flow_os_destroy_flow_action
12583                                 (cache_resource->verbs_action));
12584         if (cache_resource->normal_path_tbl)
12585                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12586                         cache_resource->normal_path_tbl);
12587         flow_dv_sample_sub_actions_release(dev,
12588                                 &cache_resource->sample_idx);
12589         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12590                         cache_resource->idx);
12591         DRV_LOG(DEBUG, "sample resource %p: removed",
12592                 (void *)cache_resource);
12593 }
12594
12595 /**
12596  * Release an sample resource.
12597  *
12598  * @param dev
12599  *   Pointer to Ethernet device.
12600  * @param handle
12601  *   Pointer to mlx5_flow_handle.
12602  *
12603  * @return
12604  *   1 while a reference on it exists, 0 when freed.
12605  */
12606 static int
12607 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12608                                      struct mlx5_flow_handle *handle)
12609 {
12610         struct mlx5_priv *priv = dev->data->dev_private;
12611         struct mlx5_flow_dv_sample_resource *cache_resource;
12612
12613         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12614                          handle->dvh.rix_sample);
12615         if (!cache_resource)
12616                 return 0;
12617         MLX5_ASSERT(cache_resource->verbs_action);
12618         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12619                                      &cache_resource->entry);
12620 }
12621
12622 void
12623 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12624                              struct mlx5_cache_entry *entry)
12625 {
12626         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12627                         container_of(entry, typeof(*cache_resource), entry);
12628         struct rte_eth_dev *dev = cache_resource->dev;
12629         struct mlx5_priv *priv = dev->data->dev_private;
12630         uint32_t i = 0;
12631
12632         MLX5_ASSERT(cache_resource->action);
12633         if (cache_resource->action)
12634                 claim_zero(mlx5_flow_os_destroy_flow_action
12635                                         (cache_resource->action));
12636         for (; i < cache_resource->num_of_dest; i++)
12637                 flow_dv_sample_sub_actions_release(dev,
12638                                 &cache_resource->sample_idx[i]);
12639         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12640                         cache_resource->idx);
12641         DRV_LOG(DEBUG, "destination array resource %p: removed",
12642                 (void *)cache_resource);
12643 }
12644
12645 /**
12646  * Release an destination array resource.
12647  *
12648  * @param dev
12649  *   Pointer to Ethernet device.
12650  * @param handle
12651  *   Pointer to mlx5_flow_handle.
12652  *
12653  * @return
12654  *   1 while a reference on it exists, 0 when freed.
12655  */
12656 static int
12657 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12658                                     struct mlx5_flow_handle *handle)
12659 {
12660         struct mlx5_priv *priv = dev->data->dev_private;
12661         struct mlx5_flow_dv_dest_array_resource *cache;
12662
12663         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12664                                handle->dvh.rix_dest_array);
12665         if (!cache)
12666                 return 0;
12667         MLX5_ASSERT(cache->action);
12668         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12669                                      &cache->entry);
12670 }
12671
12672 static void
12673 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12674 {
12675         struct mlx5_priv *priv = dev->data->dev_private;
12676         struct mlx5_dev_ctx_shared *sh = priv->sh;
12677         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12678                                 sh->geneve_tlv_option_resource;
12679         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12680         if (geneve_opt_resource) {
12681                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12682                                          __ATOMIC_RELAXED))) {
12683                         claim_zero(mlx5_devx_cmd_destroy
12684                                         (geneve_opt_resource->obj));
12685                         mlx5_free(sh->geneve_tlv_option_resource);
12686                         sh->geneve_tlv_option_resource = NULL;
12687                 }
12688         }
12689         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12690 }
12691
12692 /**
12693  * Remove the flow from the NIC but keeps it in memory.
12694  * Lock free, (mutex should be acquired by caller).
12695  *
12696  * @param[in] dev
12697  *   Pointer to Ethernet device.
12698  * @param[in, out] flow
12699  *   Pointer to flow structure.
12700  */
12701 static void
12702 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12703 {
12704         struct mlx5_flow_handle *dh;
12705         uint32_t handle_idx;
12706         struct mlx5_priv *priv = dev->data->dev_private;
12707
12708         if (!flow)
12709                 return;
12710         handle_idx = flow->dev_handles;
12711         while (handle_idx) {
12712                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12713                                     handle_idx);
12714                 if (!dh)
12715                         return;
12716                 if (dh->drv_flow) {
12717                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12718                         dh->drv_flow = NULL;
12719                 }
12720                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12721                         flow_dv_fate_resource_release(dev, dh);
12722                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12723                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12724                 handle_idx = dh->next.next;
12725         }
12726 }
12727
12728 /**
12729  * Remove the flow from the NIC and the memory.
12730  * Lock free, (mutex should be acquired by caller).
12731  *
12732  * @param[in] dev
12733  *   Pointer to the Ethernet device structure.
12734  * @param[in, out] flow
12735  *   Pointer to flow structure.
12736  */
12737 static void
12738 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12739 {
12740         struct mlx5_flow_handle *dev_handle;
12741         struct mlx5_priv *priv = dev->data->dev_private;
12742         struct mlx5_flow_meter_info *fm = NULL;
12743         uint32_t srss = 0;
12744
12745         if (!flow)
12746                 return;
12747         flow_dv_remove(dev, flow);
12748         if (flow->counter) {
12749                 flow_dv_counter_free(dev, flow->counter);
12750                 flow->counter = 0;
12751         }
12752         if (flow->meter) {
12753                 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12754                 if (fm)
12755                         mlx5_flow_meter_detach(fm);
12756                 flow->meter = 0;
12757         }
12758         if (flow->age)
12759                 flow_dv_aso_age_release(dev, flow->age);
12760         if (flow->geneve_tlv_option) {
12761                 flow_dv_geneve_tlv_option_resource_release(dev);
12762                 flow->geneve_tlv_option = 0;
12763         }
12764         while (flow->dev_handles) {
12765                 uint32_t tmp_idx = flow->dev_handles;
12766
12767                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12768                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12769                 if (!dev_handle)
12770                         return;
12771                 flow->dev_handles = dev_handle->next.next;
12772                 if (dev_handle->dvh.matcher)
12773                         flow_dv_matcher_release(dev, dev_handle);
12774                 if (dev_handle->dvh.rix_sample)
12775                         flow_dv_sample_resource_release(dev, dev_handle);
12776                 if (dev_handle->dvh.rix_dest_array)
12777                         flow_dv_dest_array_resource_release(dev, dev_handle);
12778                 if (dev_handle->dvh.rix_encap_decap)
12779                         flow_dv_encap_decap_resource_release(dev,
12780                                 dev_handle->dvh.rix_encap_decap);
12781                 if (dev_handle->dvh.modify_hdr)
12782                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12783                 if (dev_handle->dvh.rix_push_vlan)
12784                         flow_dv_push_vlan_action_resource_release(dev,
12785                                                                   dev_handle);
12786                 if (dev_handle->dvh.rix_tag)
12787                         flow_dv_tag_release(dev,
12788                                             dev_handle->dvh.rix_tag);
12789                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12790                         flow_dv_fate_resource_release(dev, dev_handle);
12791                 else if (!srss)
12792                         srss = dev_handle->rix_srss;
12793                 if (fm && dev_handle->is_meter_flow_id &&
12794                     dev_handle->split_flow_id)
12795                         mlx5_ipool_free(fm->flow_ipool,
12796                                         dev_handle->split_flow_id);
12797                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12798                            tmp_idx);
12799         }
12800         if (srss)
12801                 flow_dv_shared_rss_action_release(dev, srss);
12802 }
12803
12804 /**
12805  * Release array of hash RX queue objects.
12806  * Helper function.
12807  *
12808  * @param[in] dev
12809  *   Pointer to the Ethernet device structure.
12810  * @param[in, out] hrxqs
12811  *   Array of hash RX queue objects.
12812  *
12813  * @return
12814  *   Total number of references to hash RX queue objects in *hrxqs* array
12815  *   after this operation.
12816  */
12817 static int
12818 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12819                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12820 {
12821         size_t i;
12822         int remaining = 0;
12823
12824         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12825                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12826
12827                 if (!ret)
12828                         (*hrxqs)[i] = 0;
12829                 remaining += ret;
12830         }
12831         return remaining;
12832 }
12833
12834 /**
12835  * Release all hash RX queue objects representing shared RSS action.
12836  *
12837  * @param[in] dev
12838  *   Pointer to the Ethernet device structure.
12839  * @param[in, out] action
12840  *   Shared RSS action to remove hash RX queue objects from.
12841  *
12842  * @return
12843  *   Total number of references to hash RX queue objects stored in *action*
12844  *   after this operation.
12845  *   Expected to be 0 if no external references held.
12846  */
12847 static int
12848 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12849                                  struct mlx5_shared_action_rss *shared_rss)
12850 {
12851         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12852 }
12853
12854 /**
12855  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12856  * user input.
12857  *
12858  * Only one hash value is available for one L3+L4 combination:
12859  * for example:
12860  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12861  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12862  * same slot in mlx5_rss_hash_fields.
12863  *
12864  * @param[in] rss
12865  *   Pointer to the shared action RSS conf.
12866  * @param[in, out] hash_field
12867  *   hash_field variable needed to be adjusted.
12868  *
12869  * @return
12870  *   void
12871  */
12872 static void
12873 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12874                                      uint64_t *hash_field)
12875 {
12876         uint64_t rss_types = rss->origin.types;
12877
12878         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12879         case MLX5_RSS_HASH_IPV4:
12880                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12881                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12882                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12883                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12884                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12885                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12886                         else
12887                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12888                 }
12889                 return;
12890         case MLX5_RSS_HASH_IPV6:
12891                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12892                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12893                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12894                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12895                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12896                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12897                         else
12898                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12899                 }
12900                 return;
12901         case MLX5_RSS_HASH_IPV4_UDP:
12902                 /* fall-through. */
12903         case MLX5_RSS_HASH_IPV6_UDP:
12904                 if (rss_types & ETH_RSS_UDP) {
12905                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12906                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12907                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12908                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12909                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12910                         else
12911                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12912                 }
12913                 return;
12914         case MLX5_RSS_HASH_IPV4_TCP:
12915                 /* fall-through. */
12916         case MLX5_RSS_HASH_IPV6_TCP:
12917                 if (rss_types & ETH_RSS_TCP) {
12918                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12919                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12920                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12921                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12922                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12923                         else
12924                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12925                 }
12926                 return;
12927         default:
12928                 return;
12929         }
12930 }
12931
12932 /**
12933  * Setup shared RSS action.
12934  * Prepare set of hash RX queue objects sufficient to handle all valid
12935  * hash_fields combinations (see enum ibv_rx_hash_fields).
12936  *
12937  * @param[in] dev
12938  *   Pointer to the Ethernet device structure.
12939  * @param[in] action_idx
12940  *   Shared RSS action ipool index.
12941  * @param[in, out] action
12942  *   Partially initialized shared RSS action.
12943  * @param[out] error
12944  *   Perform verbose error reporting if not NULL. Initialized in case of
12945  *   error only.
12946  *
12947  * @return
12948  *   0 on success, otherwise negative errno value.
12949  */
12950 static int
12951 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12952                            uint32_t action_idx,
12953                            struct mlx5_shared_action_rss *shared_rss,
12954                            struct rte_flow_error *error)
12955 {
12956         struct mlx5_flow_rss_desc rss_desc = { 0 };
12957         size_t i;
12958         int err;
12959
12960         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12961                 return rte_flow_error_set(error, rte_errno,
12962                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12963                                           "cannot setup indirection table");
12964         }
12965         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12966         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12967         rss_desc.const_q = shared_rss->origin.queue;
12968         rss_desc.queue_num = shared_rss->origin.queue_num;
12969         /* Set non-zero value to indicate a shared RSS. */
12970         rss_desc.shared_rss = action_idx;
12971         rss_desc.ind_tbl = shared_rss->ind_tbl;
12972         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12973                 uint32_t hrxq_idx;
12974                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12975                 int tunnel = 0;
12976
12977                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12978                 if (shared_rss->origin.level > 1) {
12979                         hash_fields |= IBV_RX_HASH_INNER;
12980                         tunnel = 1;
12981                 }
12982                 rss_desc.tunnel = tunnel;
12983                 rss_desc.hash_fields = hash_fields;
12984                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12985                 if (!hrxq_idx) {
12986                         rte_flow_error_set
12987                                 (error, rte_errno,
12988                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12989                                  "cannot get hash queue");
12990                         goto error_hrxq_new;
12991                 }
12992                 err = __flow_dv_action_rss_hrxq_set
12993                         (shared_rss, hash_fields, hrxq_idx);
12994                 MLX5_ASSERT(!err);
12995         }
12996         return 0;
12997 error_hrxq_new:
12998         err = rte_errno;
12999         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13000         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13001                 shared_rss->ind_tbl = NULL;
13002         rte_errno = err;
13003         return -rte_errno;
13004 }
13005
13006 /**
13007  * Create shared RSS action.
13008  *
13009  * @param[in] dev
13010  *   Pointer to the Ethernet device structure.
13011  * @param[in] conf
13012  *   Shared action configuration.
13013  * @param[in] rss
13014  *   RSS action specification used to create shared action.
13015  * @param[out] error
13016  *   Perform verbose error reporting if not NULL. Initialized in case of
13017  *   error only.
13018  *
13019  * @return
13020  *   A valid shared action ID in case of success, 0 otherwise and
13021  *   rte_errno is set.
13022  */
13023 static uint32_t
13024 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13025                             const struct rte_flow_indir_action_conf *conf,
13026                             const struct rte_flow_action_rss *rss,
13027                             struct rte_flow_error *error)
13028 {
13029         struct mlx5_priv *priv = dev->data->dev_private;
13030         struct mlx5_shared_action_rss *shared_rss = NULL;
13031         void *queue = NULL;
13032         struct rte_flow_action_rss *origin;
13033         const uint8_t *rss_key;
13034         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13035         uint32_t idx;
13036
13037         RTE_SET_USED(conf);
13038         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13039                             0, SOCKET_ID_ANY);
13040         shared_rss = mlx5_ipool_zmalloc
13041                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13042         if (!shared_rss || !queue) {
13043                 rte_flow_error_set(error, ENOMEM,
13044                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13045                                    "cannot allocate resource memory");
13046                 goto error_rss_init;
13047         }
13048         if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13049                 rte_flow_error_set(error, E2BIG,
13050                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13051                                    "rss action number out of range");
13052                 goto error_rss_init;
13053         }
13054         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13055                                           sizeof(*shared_rss->ind_tbl),
13056                                           0, SOCKET_ID_ANY);
13057         if (!shared_rss->ind_tbl) {
13058                 rte_flow_error_set(error, ENOMEM,
13059                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13060                                    "cannot allocate resource memory");
13061                 goto error_rss_init;
13062         }
13063         memcpy(queue, rss->queue, queue_size);
13064         shared_rss->ind_tbl->queues = queue;
13065         shared_rss->ind_tbl->queues_n = rss->queue_num;
13066         origin = &shared_rss->origin;
13067         origin->func = rss->func;
13068         origin->level = rss->level;
13069         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13070         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13071         /* NULL RSS key indicates default RSS key. */
13072         rss_key = !rss->key ? rss_hash_default_key : rss->key;
13073         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13074         origin->key = &shared_rss->key[0];
13075         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13076         origin->queue = queue;
13077         origin->queue_num = rss->queue_num;
13078         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13079                 goto error_rss_init;
13080         rte_spinlock_init(&shared_rss->action_rss_sl);
13081         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13082         rte_spinlock_lock(&priv->shared_act_sl);
13083         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13084                      &priv->rss_shared_actions, idx, shared_rss, next);
13085         rte_spinlock_unlock(&priv->shared_act_sl);
13086         return idx;
13087 error_rss_init:
13088         if (shared_rss) {
13089                 if (shared_rss->ind_tbl)
13090                         mlx5_free(shared_rss->ind_tbl);
13091                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13092                                 idx);
13093         }
13094         if (queue)
13095                 mlx5_free(queue);
13096         return 0;
13097 }
13098
13099 /**
13100  * Destroy the shared RSS action.
13101  * Release related hash RX queue objects.
13102  *
13103  * @param[in] dev
13104  *   Pointer to the Ethernet device structure.
13105  * @param[in] idx
13106  *   The shared RSS action object ID to be removed.
13107  * @param[out] error
13108  *   Perform verbose error reporting if not NULL. Initialized in case of
13109  *   error only.
13110  *
13111  * @return
13112  *   0 on success, otherwise negative errno value.
13113  */
13114 static int
13115 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13116                              struct rte_flow_error *error)
13117 {
13118         struct mlx5_priv *priv = dev->data->dev_private;
13119         struct mlx5_shared_action_rss *shared_rss =
13120             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13121         uint32_t old_refcnt = 1;
13122         int remaining;
13123         uint16_t *queue = NULL;
13124
13125         if (!shared_rss)
13126                 return rte_flow_error_set(error, EINVAL,
13127                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13128                                           "invalid shared action");
13129         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13130         if (remaining)
13131                 return rte_flow_error_set(error, EBUSY,
13132                                           RTE_FLOW_ERROR_TYPE_ACTION,
13133                                           NULL,
13134                                           "shared rss hrxq has references");
13135         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13136                                          0, 0, __ATOMIC_ACQUIRE,
13137                                          __ATOMIC_RELAXED))
13138                 return rte_flow_error_set(error, EBUSY,
13139                                           RTE_FLOW_ERROR_TYPE_ACTION,
13140                                           NULL,
13141                                           "shared rss has references");
13142         queue = shared_rss->ind_tbl->queues;
13143         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13144         if (remaining)
13145                 return rte_flow_error_set(error, EBUSY,
13146                                           RTE_FLOW_ERROR_TYPE_ACTION,
13147                                           NULL,
13148                                           "shared rss indirection table has"
13149                                           " references");
13150         mlx5_free(queue);
13151         rte_spinlock_lock(&priv->shared_act_sl);
13152         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13153                      &priv->rss_shared_actions, idx, shared_rss, next);
13154         rte_spinlock_unlock(&priv->shared_act_sl);
13155         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13156                         idx);
13157         return 0;
13158 }
13159
13160 /**
13161  * Create indirect action, lock free,
13162  * (mutex should be acquired by caller).
13163  * Dispatcher for action type specific call.
13164  *
13165  * @param[in] dev
13166  *   Pointer to the Ethernet device structure.
13167  * @param[in] conf
13168  *   Shared action configuration.
13169  * @param[in] action
13170  *   Action specification used to create indirect action.
13171  * @param[out] error
13172  *   Perform verbose error reporting if not NULL. Initialized in case of
13173  *   error only.
13174  *
13175  * @return
13176  *   A valid shared action handle in case of success, NULL otherwise and
13177  *   rte_errno is set.
13178  */
13179 static struct rte_flow_action_handle *
13180 flow_dv_action_create(struct rte_eth_dev *dev,
13181                       const struct rte_flow_indir_action_conf *conf,
13182                       const struct rte_flow_action *action,
13183                       struct rte_flow_error *err)
13184 {
13185         uint32_t idx = 0;
13186         uint32_t ret = 0;
13187
13188         switch (action->type) {
13189         case RTE_FLOW_ACTION_TYPE_RSS:
13190                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13191                 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13192                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13193                 break;
13194         case RTE_FLOW_ACTION_TYPE_AGE:
13195                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13196                 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13197                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13198                 if (ret) {
13199                         struct mlx5_aso_age_action *aso_age =
13200                                               flow_aso_age_get_by_idx(dev, ret);
13201
13202                         if (!aso_age->age_params.context)
13203                                 aso_age->age_params.context =
13204                                                          (void *)(uintptr_t)idx;
13205                 }
13206                 break;
13207         default:
13208                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13209                                    NULL, "action type not supported");
13210                 break;
13211         }
13212         return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13213 }
13214
13215 /**
13216  * Destroy the indirect action.
13217  * Release action related resources on the NIC and the memory.
13218  * Lock free, (mutex should be acquired by caller).
13219  * Dispatcher for action type specific call.
13220  *
13221  * @param[in] dev
13222  *   Pointer to the Ethernet device structure.
13223  * @param[in] handle
13224  *   The indirect action object handle to be removed.
13225  * @param[out] error
13226  *   Perform verbose error reporting if not NULL. Initialized in case of
13227  *   error only.
13228  *
13229  * @return
13230  *   0 on success, otherwise negative errno value.
13231  */
13232 static int
13233 flow_dv_action_destroy(struct rte_eth_dev *dev,
13234                        struct rte_flow_action_handle *handle,
13235                        struct rte_flow_error *error)
13236 {
13237         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13238         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13239         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13240         int ret;
13241
13242         switch (type) {
13243         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13244                 return __flow_dv_action_rss_release(dev, idx, error);
13245         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13246                 ret = flow_dv_aso_age_release(dev, idx);
13247                 if (ret)
13248                         /*
13249                          * In this case, the last flow has a reference will
13250                          * actually release the age action.
13251                          */
13252                         DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13253                                 " released with references %d.", idx, ret);
13254                 return 0;
13255         default:
13256                 return rte_flow_error_set(error, ENOTSUP,
13257                                           RTE_FLOW_ERROR_TYPE_ACTION,
13258                                           NULL,
13259                                           "action type not supported");
13260         }
13261 }
13262
13263 /**
13264  * Updates in place shared RSS action configuration.
13265  *
13266  * @param[in] dev
13267  *   Pointer to the Ethernet device structure.
13268  * @param[in] idx
13269  *   The shared RSS action object ID to be updated.
13270  * @param[in] action_conf
13271  *   RSS action specification used to modify *shared_rss*.
13272  * @param[out] error
13273  *   Perform verbose error reporting if not NULL. Initialized in case of
13274  *   error only.
13275  *
13276  * @return
13277  *   0 on success, otherwise negative errno value.
13278  * @note: currently only support update of RSS queues.
13279  */
13280 static int
13281 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13282                             const struct rte_flow_action_rss *action_conf,
13283                             struct rte_flow_error *error)
13284 {
13285         struct mlx5_priv *priv = dev->data->dev_private;
13286         struct mlx5_shared_action_rss *shared_rss =
13287             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13288         int ret = 0;
13289         void *queue = NULL;
13290         uint16_t *queue_old = NULL;
13291         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13292
13293         if (!shared_rss)
13294                 return rte_flow_error_set(error, EINVAL,
13295                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13296                                           "invalid shared action to update");
13297         if (priv->obj_ops.ind_table_modify == NULL)
13298                 return rte_flow_error_set(error, ENOTSUP,
13299                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13300                                           "cannot modify indirection table");
13301         queue = mlx5_malloc(MLX5_MEM_ZERO,
13302                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13303                             0, SOCKET_ID_ANY);
13304         if (!queue)
13305                 return rte_flow_error_set(error, ENOMEM,
13306                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13307                                           NULL,
13308                                           "cannot allocate resource memory");
13309         memcpy(queue, action_conf->queue, queue_size);
13310         MLX5_ASSERT(shared_rss->ind_tbl);
13311         rte_spinlock_lock(&shared_rss->action_rss_sl);
13312         queue_old = shared_rss->ind_tbl->queues;
13313         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13314                                         queue, action_conf->queue_num, true);
13315         if (ret) {
13316                 mlx5_free(queue);
13317                 ret = rte_flow_error_set(error, rte_errno,
13318                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13319                                           "cannot update indirection table");
13320         } else {
13321                 mlx5_free(queue_old);
13322                 shared_rss->origin.queue = queue;
13323                 shared_rss->origin.queue_num = action_conf->queue_num;
13324         }
13325         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13326         return ret;
13327 }
13328
13329 /**
13330  * Updates in place shared action configuration, lock free,
13331  * (mutex should be acquired by caller).
13332  *
13333  * @param[in] dev
13334  *   Pointer to the Ethernet device structure.
13335  * @param[in] handle
13336  *   The indirect action object handle to be updated.
13337  * @param[in] update
13338  *   Action specification used to modify the action pointed by *handle*.
13339  *   *update* could be of same type with the action pointed by the *handle*
13340  *   handle argument, or some other structures like a wrapper, depending on
13341  *   the indirect action type.
13342  * @param[out] error
13343  *   Perform verbose error reporting if not NULL. Initialized in case of
13344  *   error only.
13345  *
13346  * @return
13347  *   0 on success, otherwise negative errno value.
13348  */
13349 static int
13350 flow_dv_action_update(struct rte_eth_dev *dev,
13351                         struct rte_flow_action_handle *handle,
13352                         const void *update,
13353                         struct rte_flow_error *err)
13354 {
13355         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13356         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13357         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13358         const void *action_conf;
13359
13360         switch (type) {
13361         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13362                 action_conf = ((const struct rte_flow_action *)update)->conf;
13363                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13364         default:
13365                 return rte_flow_error_set(err, ENOTSUP,
13366                                           RTE_FLOW_ERROR_TYPE_ACTION,
13367                                           NULL,
13368                                           "action type update not supported");
13369         }
13370 }
13371
13372 static int
13373 flow_dv_action_query(struct rte_eth_dev *dev,
13374                      const struct rte_flow_action_handle *handle, void *data,
13375                      struct rte_flow_error *error)
13376 {
13377         struct mlx5_age_param *age_param;
13378         struct rte_flow_query_age *resp;
13379         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13380         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13381         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13382
13383         switch (type) {
13384         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13385                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13386                 resp = data;
13387                 resp->aged = __atomic_load_n(&age_param->state,
13388                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13389                                                                           1 : 0;
13390                 resp->sec_since_last_hit_valid = !resp->aged;
13391                 if (resp->sec_since_last_hit_valid)
13392                         resp->sec_since_last_hit = __atomic_load_n
13393                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13394                 return 0;
13395         default:
13396                 return rte_flow_error_set(error, ENOTSUP,
13397                                           RTE_FLOW_ERROR_TYPE_ACTION,
13398                                           NULL,
13399                                           "action type query not supported");
13400         }
13401 }
13402
13403 /**
13404  * Query a dv flow  rule for its statistics via devx.
13405  *
13406  * @param[in] dev
13407  *   Pointer to Ethernet device.
13408  * @param[in] flow
13409  *   Pointer to the sub flow.
13410  * @param[out] data
13411  *   data retrieved by the query.
13412  * @param[out] error
13413  *   Perform verbose error reporting if not NULL.
13414  *
13415  * @return
13416  *   0 on success, a negative errno value otherwise and rte_errno is set.
13417  */
13418 static int
13419 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13420                     void *data, struct rte_flow_error *error)
13421 {
13422         struct mlx5_priv *priv = dev->data->dev_private;
13423         struct rte_flow_query_count *qc = data;
13424
13425         if (!priv->config.devx)
13426                 return rte_flow_error_set(error, ENOTSUP,
13427                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13428                                           NULL,
13429                                           "counters are not supported");
13430         if (flow->counter) {
13431                 uint64_t pkts, bytes;
13432                 struct mlx5_flow_counter *cnt;
13433
13434                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13435                                                  NULL);
13436                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13437                                                &bytes);
13438
13439                 if (err)
13440                         return rte_flow_error_set(error, -err,
13441                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13442                                         NULL, "cannot read counters");
13443                 qc->hits_set = 1;
13444                 qc->bytes_set = 1;
13445                 qc->hits = pkts - cnt->hits;
13446                 qc->bytes = bytes - cnt->bytes;
13447                 if (qc->reset) {
13448                         cnt->hits = pkts;
13449                         cnt->bytes = bytes;
13450                 }
13451                 return 0;
13452         }
13453         return rte_flow_error_set(error, EINVAL,
13454                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13455                                   NULL,
13456                                   "counters are not available");
13457 }
13458
13459 /**
13460  * Query a flow rule AGE action for aging information.
13461  *
13462  * @param[in] dev
13463  *   Pointer to Ethernet device.
13464  * @param[in] flow
13465  *   Pointer to the sub flow.
13466  * @param[out] data
13467  *   data retrieved by the query.
13468  * @param[out] error
13469  *   Perform verbose error reporting if not NULL.
13470  *
13471  * @return
13472  *   0 on success, a negative errno value otherwise and rte_errno is set.
13473  */
13474 static int
13475 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13476                   void *data, struct rte_flow_error *error)
13477 {
13478         struct rte_flow_query_age *resp = data;
13479         struct mlx5_age_param *age_param;
13480
13481         if (flow->age) {
13482                 struct mlx5_aso_age_action *act =
13483                                      flow_aso_age_get_by_idx(dev, flow->age);
13484
13485                 age_param = &act->age_params;
13486         } else if (flow->counter) {
13487                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13488
13489                 if (!age_param || !age_param->timeout)
13490                         return rte_flow_error_set
13491                                         (error, EINVAL,
13492                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13493                                          NULL, "cannot read age data");
13494         } else {
13495                 return rte_flow_error_set(error, EINVAL,
13496                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13497                                           NULL, "age data not available");
13498         }
13499         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13500                                      AGE_TMOUT ? 1 : 0;
13501         resp->sec_since_last_hit_valid = !resp->aged;
13502         if (resp->sec_since_last_hit_valid)
13503                 resp->sec_since_last_hit = __atomic_load_n
13504                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13505         return 0;
13506 }
13507
13508 /**
13509  * Query a flow.
13510  *
13511  * @see rte_flow_query()
13512  * @see rte_flow_ops
13513  */
13514 static int
13515 flow_dv_query(struct rte_eth_dev *dev,
13516               struct rte_flow *flow __rte_unused,
13517               const struct rte_flow_action *actions __rte_unused,
13518               void *data __rte_unused,
13519               struct rte_flow_error *error __rte_unused)
13520 {
13521         int ret = -EINVAL;
13522
13523         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13524                 switch (actions->type) {
13525                 case RTE_FLOW_ACTION_TYPE_VOID:
13526                         break;
13527                 case RTE_FLOW_ACTION_TYPE_COUNT:
13528                         ret = flow_dv_query_count(dev, flow, data, error);
13529                         break;
13530                 case RTE_FLOW_ACTION_TYPE_AGE:
13531                         ret = flow_dv_query_age(dev, flow, data, error);
13532                         break;
13533                 default:
13534                         return rte_flow_error_set(error, ENOTSUP,
13535                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13536                                                   actions,
13537                                                   "action not supported");
13538                 }
13539         }
13540         return ret;
13541 }
13542
13543 /**
13544  * Destroy the meter table set.
13545  * Lock free, (mutex should be acquired by caller).
13546  *
13547  * @param[in] dev
13548  *   Pointer to Ethernet device.
13549  * @param[in] tbl
13550  *   Pointer to the meter table set.
13551  *
13552  * @return
13553  *   Always 0.
13554  */
13555 static int
13556 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13557                         struct mlx5_meter_domains_infos *tbl)
13558 {
13559         struct mlx5_priv *priv = dev->data->dev_private;
13560         struct mlx5_meter_domains_infos *mtd =
13561                                 (struct mlx5_meter_domains_infos *)tbl;
13562
13563         if (!mtd || !priv->config.dv_flow_en)
13564                 return 0;
13565         if (mtd->egress.tbl)
13566                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13567         if (mtd->egress.sfx_tbl)
13568                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13569         if (mtd->ingress.tbl)
13570                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13571         if (mtd->ingress.sfx_tbl)
13572                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13573                                              mtd->ingress.sfx_tbl);
13574         if (mtd->transfer.tbl)
13575                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13576         if (mtd->transfer.sfx_tbl)
13577                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13578                                              mtd->transfer.sfx_tbl);
13579         mlx5_free(mtd);
13580         return 0;
13581 }
13582
13583 /* Number of meter flow actions, count and jump or count and drop. */
13584 #define METER_ACTIONS 2
13585
13586 /**
13587  * Create specify domain meter table and suffix table.
13588  *
13589  * @param[in] dev
13590  *   Pointer to Ethernet device.
13591  * @param[in,out] mtb
13592  *   Pointer to DV meter table set.
13593  * @param[in] egress
13594  *   Table attribute.
13595  * @param[in] transfer
13596  *   Table attribute.
13597  *
13598  * @return
13599  *   0 on success, -1 otherwise.
13600  */
13601 static int
13602 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13603                            struct mlx5_meter_domains_infos *mtb,
13604                            uint8_t egress, uint8_t transfer)
13605 {
13606         struct rte_flow_error error;
13607         struct mlx5_meter_domain_info *dtb;
13608
13609         if (transfer)
13610                 dtb = &mtb->transfer;
13611         else if (egress)
13612                 dtb = &mtb->egress;
13613         else
13614                 dtb = &mtb->ingress;
13615         /* Create the meter table with METER level. */
13616         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13617                                             egress, transfer, false, NULL, 0,
13618                                             0, &error);
13619         if (!dtb->tbl) {
13620                 DRV_LOG(ERR, "Failed to create meter policer table.");
13621                 return -1;
13622         }
13623         /* Create the meter suffix table with SUFFIX level. */
13624         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13625                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13626                                             egress, transfer, false, NULL, 0,
13627                                             0, &error);
13628         if (!dtb->sfx_tbl) {
13629                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13630                 return -1;
13631         }
13632         return 0;
13633 }
13634
13635 /**
13636  * Create the needed meter and suffix tables.
13637  * Lock free, (mutex should be acquired by caller).
13638  *
13639  * @param[in] dev
13640  *   Pointer to Ethernet device.
13641  *
13642  * @return
13643  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13644  */
13645 static struct mlx5_meter_domains_infos *
13646 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13647 {
13648         struct mlx5_priv *priv = dev->data->dev_private;
13649         struct mlx5_meter_domains_infos *mtb;
13650         int ret;
13651
13652         if (!priv->mtr_en) {
13653                 rte_errno = ENOTSUP;
13654                 return NULL;
13655         }
13656         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13657         if (!mtb) {
13658                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13659                 return NULL;
13660         }
13661         /* Egress meter table. */
13662         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13663         if (ret) {
13664                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13665                 goto error_exit;
13666         }
13667         /* Ingress meter table. */
13668         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13669         if (ret) {
13670                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13671                 goto error_exit;
13672         }
13673         /* FDB meter table. */
13674         if (priv->config.dv_esw_en) {
13675                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13676                 if (ret) {
13677                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13678                         goto error_exit;
13679                 }
13680         }
13681         return mtb;
13682 error_exit:
13683         flow_dv_destroy_mtr_tbl(dev, mtb);
13684         return NULL;
13685 }
13686
13687 /**
13688  * Destroy the meter table matchers.
13689  * Lock free, (mutex should be acquired by caller).
13690  *
13691  * @param[in] dev
13692  *   Pointer to Ethernet device.
13693  * @param[in,out] dtb
13694  *   Pointer to DV meter table.
13695  *
13696  * @return
13697  *   Always 0.
13698  */
13699 static int
13700 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13701                              struct mlx5_meter_domain_info *dtb)
13702 {
13703         struct mlx5_priv *priv = dev->data->dev_private;
13704         struct mlx5_flow_tbl_data_entry *tbl;
13705
13706         if (!priv->config.dv_flow_en)
13707                 return 0;
13708         if (dtb->drop_matcher) {
13709                 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13710                 mlx5_cache_unregister(&tbl->matchers,
13711                                       &dtb->drop_matcher->entry);
13712                 dtb->drop_matcher = NULL;
13713         }
13714         if (dtb->color_matcher) {
13715                 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13716                 mlx5_cache_unregister(&tbl->matchers,
13717                                       &dtb->color_matcher->entry);
13718                 dtb->color_matcher = NULL;
13719         }
13720         return 0;
13721 }
13722
13723 /**
13724  * Create the matchers for meter table.
13725  *
13726  * @param[in] dev
13727  *   Pointer to Ethernet device.
13728  * @param[in] color_reg_c_idx
13729  *   Reg C index for color match.
13730  * @param[in] mtr_id_reg_c_idx
13731  *   Reg C index for meter_id match.
13732  * @param[in] mtr_id_mask
13733  *   Mask for meter_id match criteria.
13734  * @param[in,out] dtb
13735  *   Pointer to DV meter table.
13736  * @param[out] error
13737  *   Perform verbose error reporting if not NULL.
13738  *
13739  * @return
13740  *   0 on success, a negative errno value otherwise and rte_errno is set.
13741  */
13742 static int
13743 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13744                              uint32_t color_reg_c_idx,
13745                              uint32_t mtr_id_reg_c_idx,
13746                              uint32_t mtr_id_mask,
13747                              struct mlx5_meter_domain_info *dtb,
13748                              struct rte_flow_error *error)
13749 {
13750         struct mlx5_priv *priv = dev->data->dev_private;
13751         struct mlx5_flow_tbl_data_entry *tbl_data;
13752         struct mlx5_cache_entry *entry;
13753         struct mlx5_flow_dv_matcher matcher = {
13754                 .mask = {
13755                         .size = sizeof(matcher.mask.buf) -
13756                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13757                 },
13758                 .tbl = dtb->tbl,
13759         };
13760         struct mlx5_flow_dv_match_params value = {
13761                 .size = sizeof(value.buf) -
13762                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13763         };
13764         struct mlx5_flow_cb_ctx ctx = {
13765                 .error = error,
13766                 .data = &matcher,
13767         };
13768         uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13769
13770         tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13771         if (!dtb->drop_matcher) {
13772                 /* Create matchers for Drop. */
13773                 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13774                                        mtr_id_reg_c_idx, 0, mtr_id_mask);
13775                 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13776                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13777                                         matcher.mask.size);
13778                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13779                 if (!entry) {
13780                         DRV_LOG(ERR, "Failed to register meter drop matcher.");
13781                         return -1;
13782                 }
13783                 dtb->drop_matcher =
13784                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13785         }
13786         if (!dtb->color_matcher) {
13787                 /* Create matchers for Color + meter_id. */
13788                 if (priv->mtr_reg_share) {
13789                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13790                                         color_reg_c_idx, 0,
13791                                         (mtr_id_mask | color_mask));
13792                 } else {
13793                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13794                                         color_reg_c_idx, 0, color_mask);
13795                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13796                                         mtr_id_reg_c_idx, 0, mtr_id_mask);
13797                 }
13798                 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13799                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13800                                         matcher.mask.size);
13801                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13802                 if (!entry) {
13803                         DRV_LOG(ERR, "Failed to register meter color matcher.");
13804                         return -1;
13805                 }
13806                 dtb->color_matcher =
13807                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13808         }
13809         return 0;
13810 }
13811
13812 /**
13813  * Destroy domain policer rule.
13814  *
13815  * @param[in] dev
13816  *   Pointer to Ethernet device.
13817  * @param[in] dt
13818  *   Pointer to domain table.
13819  */
13820 static void
13821 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13822                                     struct mlx5_meter_domain_info *dt)
13823 {
13824         if (dt->drop_rule) {
13825                 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13826                 dt->drop_rule = NULL;
13827         }
13828         if (dt->green_rule) {
13829                 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13830                 dt->green_rule = NULL;
13831         }
13832         flow_dv_destroy_mtr_matchers(dev, dt);
13833         if (dt->jump_actn) {
13834                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13835                 dt->jump_actn = NULL;
13836         }
13837 }
13838
13839 /**
13840  * Destroy policer rules.
13841  *
13842  * @param[in] dev
13843  *   Pointer to Ethernet device.
13844  * @param[in] fm
13845  *   Pointer to flow meter structure.
13846  * @param[in] attr
13847  *   Pointer to flow attributes.
13848  *
13849  * @return
13850  *   Always 0.
13851  */
13852 static int
13853 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13854                               const struct mlx5_flow_meter_info *fm,
13855                               const struct rte_flow_attr *attr)
13856 {
13857         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13858
13859         if (!mtb)
13860                 return 0;
13861         if (attr->egress)
13862                 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13863         if (attr->ingress)
13864                 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13865         if (attr->transfer)
13866                 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13867         return 0;
13868 }
13869
13870 /**
13871  * Create specify domain meter policer rule.
13872  *
13873  * @param[in] dev
13874  *   Pointer to Ethernet device.
13875  * @param[in] fm
13876  *   Pointer to flow meter structure.
13877  * @param[in] mtr_idx
13878  *   meter index.
13879  * @param[in] mtb
13880  *   Pointer to DV meter table set.
13881  * @param[out] drop_rule
13882  *   The address of pointer saving drop rule.
13883  * @param[out] color_rule
13884  *   The address of pointer saving green rule.
13885  *
13886  * @return
13887  *   0 on success, -1 otherwise.
13888  */
13889 static int
13890 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13891                                     struct mlx5_flow_meter_info *fm,
13892                                     uint32_t mtr_idx,
13893                                     struct mlx5_meter_domain_info *dtb,
13894                                     void **drop_rule,
13895                                     void **green_rule)
13896 {
13897         struct mlx5_priv *priv = dev->data->dev_private;
13898         struct mlx5_flow_dv_match_params matcher = {
13899                 .size = sizeof(matcher.buf) -
13900                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13901         };
13902         struct mlx5_flow_dv_match_params value = {
13903                 .size = sizeof(value.buf) -
13904                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13905         };
13906         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13907         struct rte_flow_error error;
13908         uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13909                                                     0, &error);
13910         uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13911                                                      0, &error);
13912         uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13913         uint32_t mtr_id_mask =
13914                 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13915         void *actions[METER_ACTIONS];
13916         int i;
13917         int ret = 0;
13918
13919         /* Create jump action. */
13920         if (!dtb->jump_actn)
13921                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13922                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13923         if (ret) {
13924                 DRV_LOG(ERR, "Failed to create policer jump action.");
13925                 goto error;
13926         }
13927         /* Prepare matchers. */
13928         if (!dtb->drop_matcher || !dtb->color_matcher) {
13929                 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13930                                                    mtr_id_reg_c, mtr_id_mask,
13931                                                    dtb, &error);
13932                 if (ret) {
13933                         DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13934                         goto error;
13935                 }
13936         }
13937         /* Create Drop flow, matching meter_id only. */
13938         i = 0;
13939         flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13940                                (mtr_idx << mtr_id_offset), UINT32_MAX);
13941         if (mtb->drop_count)
13942                 actions[i++] = mtb->drop_count;
13943         actions[i++] = priv->sh->dr_drop_action;
13944         ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13945                                        (void *)&value, i, actions, drop_rule);
13946         if (ret) {
13947                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13948                 goto error;
13949         }
13950         /* Create flow matching Green color + meter_id. */
13951         i = 0;
13952         if (priv->mtr_reg_share) {
13953                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13954                                        ((mtr_idx << mtr_id_offset) |
13955                                         rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13956                                        UINT32_MAX);
13957         } else {
13958                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13959                                        rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13960                                        UINT32_MAX);
13961                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13962                                        mtr_idx, UINT32_MAX);
13963         }
13964         if (mtb->green_count)
13965                 actions[i++] = mtb->green_count;
13966         actions[i++] = dtb->jump_actn;
13967         ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
13968                                        (void *)&value, i, actions, green_rule);
13969         if (ret) {
13970                 DRV_LOG(ERR, "Failed to create meter policer color rule.");
13971                 goto error;
13972         }
13973         return 0;
13974 error:
13975         rte_errno = errno;
13976         return -1;
13977 }
13978
13979 /**
13980  * Prepare policer rules for all domains.
13981  * If meter already initialized, this will replace all old rules with new ones.
13982  *
13983  * @param[in] dev
13984  *   Pointer to Ethernet device.
13985  * @param[in] fm
13986  *   Pointer to flow meter structure.
13987  * @param[in] attr
13988  *   Pointer to flow attributes.
13989  *
13990  * @return
13991  *   0 on success, -1 otherwise.
13992  */
13993 static int
13994 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
13995                               struct mlx5_flow_meter_info *fm,
13996                               const struct rte_flow_attr *attr)
13997 {
13998         struct mlx5_priv *priv = dev->data->dev_private;
13999         struct mlx5_meter_domains_infos *mtb = fm->mfts;
14000         bool initialized = false;
14001         struct mlx5_flow_counter *cnt;
14002         void *egress_drop_rule = NULL;
14003         void *egress_green_rule = NULL;
14004         void *ingress_drop_rule = NULL;
14005         void *ingress_green_rule = NULL;
14006         void *transfer_drop_rule = NULL;
14007         void *transfer_green_rule = NULL;
14008         uint32_t mtr_idx;
14009         int ret;
14010
14011         /* Get the statistics counters for green/drop. */
14012         if (fm->policer_stats.pass_cnt) {
14013                 cnt = flow_dv_counter_get_by_idx(dev,
14014                                         fm->policer_stats.pass_cnt,
14015                                         NULL);
14016                 mtb->green_count = cnt->action;
14017         } else {
14018                 mtb->green_count = NULL;
14019         }
14020         if (fm->policer_stats.drop_cnt) {
14021                 cnt = flow_dv_counter_get_by_idx(dev,
14022                                         fm->policer_stats.drop_cnt,
14023                                         NULL);
14024                 mtb->drop_count = cnt->action;
14025         } else {
14026                 mtb->drop_count = NULL;
14027         }
14028         /**
14029          * If flow meter has been initialized, all policer rules
14030          * are created. So can get if meter initialized by checking
14031          * any policer rule.
14032          */
14033         if (mtb->egress.drop_rule)
14034                 initialized = true;
14035         if (priv->sh->meter_aso_en) {
14036                 struct mlx5_aso_mtr *aso_mtr = NULL;
14037                 struct mlx5_aso_mtr_pool *pool;
14038
14039                 aso_mtr = container_of(fm, struct mlx5_aso_mtr, fm);
14040                 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
14041                                     mtrs[aso_mtr->offset]);
14042                 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, aso_mtr->offset);
14043         } else {
14044                 struct mlx5_legacy_flow_meter *legacy_fm;
14045
14046                 legacy_fm = container_of(fm, struct mlx5_legacy_flow_meter, fm);
14047                 mtr_idx = legacy_fm->idx;
14048         }
14049         if (attr->egress) {
14050                 ret = flow_dv_create_policer_forward_rule(dev,
14051                                 fm, mtr_idx, &mtb->egress,
14052                                 &egress_drop_rule, &egress_green_rule);
14053                 if (ret) {
14054                         DRV_LOG(ERR, "Failed to create egress policer.");
14055                         goto error;
14056                 }
14057         }
14058         if (attr->ingress) {
14059                 ret = flow_dv_create_policer_forward_rule(dev,
14060                                 fm, mtr_idx, &mtb->ingress,
14061                                 &ingress_drop_rule, &ingress_green_rule);
14062                 if (ret) {
14063                         DRV_LOG(ERR, "Failed to create ingress policer.");
14064                         goto error;
14065                 }
14066         }
14067         if (attr->transfer) {
14068                 ret = flow_dv_create_policer_forward_rule(dev,
14069                                 fm, mtr_idx, &mtb->transfer,
14070                                 &transfer_drop_rule, &transfer_green_rule);
14071                 if (ret) {
14072                         DRV_LOG(ERR, "Failed to create transfer policer.");
14073                         goto error;
14074                 }
14075         }
14076         /* Replace old flows if existing. */
14077         if (mtb->egress.drop_rule)
14078                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
14079         if (mtb->egress.green_rule)
14080                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
14081         if (mtb->ingress.drop_rule)
14082                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
14083         if (mtb->ingress.green_rule)
14084                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
14085         if (mtb->transfer.drop_rule)
14086                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
14087         if (mtb->transfer.green_rule)
14088                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
14089         mtb->egress.drop_rule = egress_drop_rule;
14090         mtb->egress.green_rule = egress_green_rule;
14091         mtb->ingress.drop_rule = ingress_drop_rule;
14092         mtb->ingress.green_rule = ingress_green_rule;
14093         mtb->transfer.drop_rule = transfer_drop_rule;
14094         mtb->transfer.green_rule = transfer_green_rule;
14095         return 0;
14096 error:
14097         if (egress_drop_rule)
14098                 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
14099         if (egress_green_rule)
14100                 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
14101         if (ingress_drop_rule)
14102                 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
14103         if (ingress_green_rule)
14104                 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
14105         if (transfer_drop_rule)
14106                 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
14107         if (transfer_green_rule)
14108                 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
14109         if (!initialized)
14110                 flow_dv_destroy_policer_rules(dev, fm, attr);
14111         return -1;
14112 }
14113
14114 /**
14115  * Validate the batch counter support in root table.
14116  *
14117  * Create a simple flow with invalid counter and drop action on root table to
14118  * validate if batch counter with offset on root table is supported or not.
14119  *
14120  * @param[in] dev
14121  *   Pointer to rte_eth_dev structure.
14122  *
14123  * @return
14124  *   0 on success, a negative errno value otherwise and rte_errno is set.
14125  */
14126 int
14127 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
14128 {
14129         struct mlx5_priv *priv = dev->data->dev_private;
14130         struct mlx5_dev_ctx_shared *sh = priv->sh;
14131         struct mlx5_flow_dv_match_params mask = {
14132                 .size = sizeof(mask.buf),
14133         };
14134         struct mlx5_flow_dv_match_params value = {
14135                 .size = sizeof(value.buf),
14136         };
14137         struct mlx5dv_flow_matcher_attr dv_attr = {
14138                 .type = IBV_FLOW_ATTR_NORMAL,
14139                 .priority = 0,
14140                 .match_criteria_enable = 0,
14141                 .match_mask = (void *)&mask,
14142         };
14143         void *actions[2] = { 0 };
14144         struct mlx5_flow_tbl_resource *tbl = NULL;
14145         struct mlx5_devx_obj *dcs = NULL;
14146         void *matcher = NULL;
14147         void *flow = NULL;
14148         int ret = -1;
14149
14150         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
14151         if (!tbl)
14152                 goto err;
14153         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
14154         if (!dcs)
14155                 goto err;
14156         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
14157                                                     &actions[0]);
14158         if (ret)
14159                 goto err;
14160         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
14161                                           priv->drop_queue.hrxq->action;
14162         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
14163         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
14164                                                &matcher);
14165         if (ret)
14166                 goto err;
14167         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
14168                                        actions, &flow);
14169 err:
14170         /*
14171          * If batch counter with offset is not supported, the driver will not
14172          * validate the invalid offset value, flow create should success.
14173          * In this case, it means batch counter is not supported in root table.
14174          *
14175          * Otherwise, if flow create is failed, counter offset is supported.
14176          */
14177         if (flow) {
14178                 DRV_LOG(INFO, "Batch counter is not supported in root "
14179                               "table. Switch to fallback mode.");
14180                 rte_errno = ENOTSUP;
14181                 ret = -rte_errno;
14182                 claim_zero(mlx5_flow_os_destroy_flow(flow));
14183         } else {
14184                 /* Check matcher to make sure validate fail at flow create. */
14185                 if (!matcher || (matcher && errno != EINVAL))
14186                         DRV_LOG(ERR, "Unexpected error in counter offset "
14187                                      "support detection");
14188                 ret = 0;
14189         }
14190         if (actions[0])
14191                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14192         if (matcher)
14193                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14194         if (tbl)
14195                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14196         if (dcs)
14197                 claim_zero(mlx5_devx_cmd_destroy(dcs));
14198         return ret;
14199 }
14200
14201 /**
14202  * Query a devx counter.
14203  *
14204  * @param[in] dev
14205  *   Pointer to the Ethernet device structure.
14206  * @param[in] cnt
14207  *   Index to the flow counter.
14208  * @param[in] clear
14209  *   Set to clear the counter statistics.
14210  * @param[out] pkts
14211  *   The statistics value of packets.
14212  * @param[out] bytes
14213  *   The statistics value of bytes.
14214  *
14215  * @return
14216  *   0 on success, otherwise return -1.
14217  */
14218 static int
14219 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14220                       uint64_t *pkts, uint64_t *bytes)
14221 {
14222         struct mlx5_priv *priv = dev->data->dev_private;
14223         struct mlx5_flow_counter *cnt;
14224         uint64_t inn_pkts, inn_bytes;
14225         int ret;
14226
14227         if (!priv->config.devx)
14228                 return -1;
14229
14230         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14231         if (ret)
14232                 return -1;
14233         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14234         *pkts = inn_pkts - cnt->hits;
14235         *bytes = inn_bytes - cnt->bytes;
14236         if (clear) {
14237                 cnt->hits = inn_pkts;
14238                 cnt->bytes = inn_bytes;
14239         }
14240         return 0;
14241 }
14242
14243 /**
14244  * Get aged-out flows.
14245  *
14246  * @param[in] dev
14247  *   Pointer to the Ethernet device structure.
14248  * @param[in] context
14249  *   The address of an array of pointers to the aged-out flows contexts.
14250  * @param[in] nb_contexts
14251  *   The length of context array pointers.
14252  * @param[out] error
14253  *   Perform verbose error reporting if not NULL. Initialized in case of
14254  *   error only.
14255  *
14256  * @return
14257  *   how many contexts get in success, otherwise negative errno value.
14258  *   if nb_contexts is 0, return the amount of all aged contexts.
14259  *   if nb_contexts is not 0 , return the amount of aged flows reported
14260  *   in the context array.
14261  * @note: only stub for now
14262  */
14263 static int
14264 flow_get_aged_flows(struct rte_eth_dev *dev,
14265                     void **context,
14266                     uint32_t nb_contexts,
14267                     struct rte_flow_error *error)
14268 {
14269         struct mlx5_priv *priv = dev->data->dev_private;
14270         struct mlx5_age_info *age_info;
14271         struct mlx5_age_param *age_param;
14272         struct mlx5_flow_counter *counter;
14273         struct mlx5_aso_age_action *act;
14274         int nb_flows = 0;
14275
14276         if (nb_contexts && !context)
14277                 return rte_flow_error_set(error, EINVAL,
14278                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14279                                           NULL, "empty context");
14280         age_info = GET_PORT_AGE_INFO(priv);
14281         rte_spinlock_lock(&age_info->aged_sl);
14282         LIST_FOREACH(act, &age_info->aged_aso, next) {
14283                 nb_flows++;
14284                 if (nb_contexts) {
14285                         context[nb_flows - 1] =
14286                                                 act->age_params.context;
14287                         if (!(--nb_contexts))
14288                                 break;
14289                 }
14290         }
14291         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14292                 nb_flows++;
14293                 if (nb_contexts) {
14294                         age_param = MLX5_CNT_TO_AGE(counter);
14295                         context[nb_flows - 1] = age_param->context;
14296                         if (!(--nb_contexts))
14297                                 break;
14298                 }
14299         }
14300         rte_spinlock_unlock(&age_info->aged_sl);
14301         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14302         return nb_flows;
14303 }
14304
14305 /*
14306  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14307  */
14308 static uint32_t
14309 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14310 {
14311         return flow_dv_counter_alloc(dev, 0);
14312 }
14313
14314 /**
14315  * Validate indirect action.
14316  * Dispatcher for action type specific validation.
14317  *
14318  * @param[in] dev
14319  *   Pointer to the Ethernet device structure.
14320  * @param[in] conf
14321  *   Shared action configuration.
14322  * @param[in] action
14323  *   The indirect action object to validate.
14324  * @param[out] error
14325  *   Perform verbose error reporting if not NULL. Initialized in case of
14326  *   error only.
14327  *
14328  * @return
14329  *   0 on success, otherwise negative errno value.
14330  */
14331 static int
14332 flow_dv_action_validate(struct rte_eth_dev *dev,
14333                         const struct rte_flow_indir_action_conf *conf,
14334                         const struct rte_flow_action *action,
14335                         struct rte_flow_error *err)
14336 {
14337         struct mlx5_priv *priv = dev->data->dev_private;
14338
14339         RTE_SET_USED(conf);
14340         switch (action->type) {
14341         case RTE_FLOW_ACTION_TYPE_RSS:
14342                 /*
14343                  * priv->obj_ops is set according to driver capabilities.
14344                  * When DevX capabilities are
14345                  * sufficient, it is set to devx_obj_ops.
14346                  * Otherwise, it is set to ibv_obj_ops.
14347                  * ibv_obj_ops doesn't support ind_table_modify operation.
14348                  * In this case the shared RSS action can't be used.
14349                  */
14350                 if (priv->obj_ops.ind_table_modify == NULL)
14351                         return rte_flow_error_set
14352                                         (err, ENOTSUP,
14353                                          RTE_FLOW_ERROR_TYPE_ACTION,
14354                                          NULL,
14355                                          "shared RSS action not supported");
14356                 return mlx5_validate_action_rss(dev, action, err);
14357         case RTE_FLOW_ACTION_TYPE_AGE:
14358                 if (!priv->sh->aso_age_mng)
14359                         return rte_flow_error_set(err, ENOTSUP,
14360                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14361                                                 NULL,
14362                                              "shared age action not supported");
14363                 return flow_dv_validate_action_age(0, action, dev, err);
14364         default:
14365                 return rte_flow_error_set(err, ENOTSUP,
14366                                           RTE_FLOW_ERROR_TYPE_ACTION,
14367                                           NULL,
14368                                           "action type not supported");
14369         }
14370 }
14371
14372 static int
14373 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14374 {
14375         struct mlx5_priv *priv = dev->data->dev_private;
14376         int ret = 0;
14377
14378         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14379                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14380                                                 flags);
14381                 if (ret != 0)
14382                         return ret;
14383         }
14384         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14385                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14386                 if (ret != 0)
14387                         return ret;
14388         }
14389         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14390                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14391                 if (ret != 0)
14392                         return ret;
14393         }
14394         return 0;
14395 }
14396
14397 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14398         .validate = flow_dv_validate,
14399         .prepare = flow_dv_prepare,
14400         .translate = flow_dv_translate,
14401         .apply = flow_dv_apply,
14402         .remove = flow_dv_remove,
14403         .destroy = flow_dv_destroy,
14404         .query = flow_dv_query,
14405         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14406         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14407         .prepare_policer_rules = flow_dv_prepare_policer_rules,
14408         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14409         .create_meter = flow_dv_mtr_alloc,
14410         .free_meter = flow_dv_aso_mtr_release_to_pool,
14411         .counter_alloc = flow_dv_counter_allocate,
14412         .counter_free = flow_dv_counter_free,
14413         .counter_query = flow_dv_counter_query,
14414         .get_aged_flows = flow_get_aged_flows,
14415         .action_validate = flow_dv_action_validate,
14416         .action_create = flow_dv_action_create,
14417         .action_destroy = flow_dv_action_destroy,
14418         .action_update = flow_dv_action_update,
14419         .action_query = flow_dv_action_query,
14420         .sync_domain = flow_dv_sync_domain,
14421 };
14422
14423 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14424