drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_dev_ctx_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_dev_ctx_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /*
1643  * GTP flags are contained in 1 byte of the format:
1644  * -------------------------------------------
1645  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1646  * |-----------------------------------------|
1647  * | value | Version | PT | Res | E | S | PN |
1648  * -------------------------------------------
1649  *
1650  * Matching is supported only for GTP flags E, S, PN.
1651  */
1652 #define MLX5_GTP_FLAGS_MASK     0x07
1653
1654 /**
1655  * Validate VLAN item.
1656  *
1657  * @param[in] item
1658  *   Item specification.
1659  * @param[in] item_flags
1660  *   Bit-fields that holds the items detected until now.
1661  * @param[in] dev
1662  *   Ethernet device flow is being created on.
1663  * @param[out] error
1664  *   Pointer to error structure.
1665  *
1666  * @return
1667  *   0 on success, a negative errno value otherwise and rte_errno is set.
1668  */
1669 static int
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671                            uint64_t item_flags,
1672                            struct rte_eth_dev *dev,
1673                            struct rte_flow_error *error)
1674 {
1675         const struct rte_flow_item_vlan *mask = item->mask;
1676         const struct rte_flow_item_vlan nic_mask = {
1677                 .tci = RTE_BE16(UINT16_MAX),
1678                 .inner_type = RTE_BE16(UINT16_MAX),
1679         };
1680         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1681         int ret;
1682         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683                                         MLX5_FLOW_LAYER_INNER_L4) :
1684                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1685                                         MLX5_FLOW_LAYER_OUTER_L4);
1686         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1688
1689         if (item_flags & vlanm)
1690                 return rte_flow_error_set(error, EINVAL,
1691                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1692                                           "multiple VLAN layers not supported");
1693         else if ((item_flags & l34m) != 0)
1694                 return rte_flow_error_set(error, EINVAL,
1695                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1696                                           "VLAN cannot follow L3/L4 layer");
1697         if (!mask)
1698                 mask = &rte_flow_item_vlan_mask;
1699         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700                                         (const uint8_t *)&nic_mask,
1701                                         sizeof(struct rte_flow_item_vlan),
1702                                         error);
1703         if (ret)
1704                 return ret;
1705         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706                 struct mlx5_priv *priv = dev->data->dev_private;
1707
1708                 if (priv->vmwa_context) {
1709                         /*
1710                          * Non-NULL context means we have a virtual machine
1711                          * and SR-IOV enabled, we have to create VLAN interface
1712                          * to make hypervisor to setup E-Switch vport
1713                          * context correctly. We avoid creating the multiple
1714                          * VLAN interfaces, so we cannot support VLAN tag mask.
1715                          */
1716                         return rte_flow_error_set(error, EINVAL,
1717                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1718                                                   item,
1719                                                   "VLAN tag mask is not"
1720                                                   " supported in virtual"
1721                                                   " environment");
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 /* If VLAN item in pattern doesn't contain data, return here. */
1885                 if (!vlan_v)
1886                         return;
1887                 if (!vlan_m)
1888                         vlan_m = &nic_mask;
1889                 /* Only full match values are accepted */
1890                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1891                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1892                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1893                         vlan->vlan_tci |=
1894                                 rte_be_to_cpu_16(vlan_v->tci &
1895                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1896                 }
1897                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1898                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1899                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1900                         vlan->vlan_tci |=
1901                                 rte_be_to_cpu_16(vlan_v->tci &
1902                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1903                 }
1904                 if (vlan_m->inner_type == nic_mask.inner_type)
1905                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1906                                                            vlan_m->inner_type);
1907         }
1908 }
1909
1910 /**
1911  * Validate the push VLAN action.
1912  *
1913  * @param[in] dev
1914  *   Pointer to the rte_eth_dev structure.
1915  * @param[in] action_flags
1916  *   Holds the actions detected until now.
1917  * @param[in] item_flags
1918  *   The items found in this flow rule.
1919  * @param[in] action
1920  *   Pointer to the action structure.
1921  * @param[in] attr
1922  *   Pointer to flow attributes
1923  * @param[out] error
1924  *   Pointer to error structure.
1925  *
1926  * @return
1927  *   0 on success, a negative errno value otherwise and rte_errno is set.
1928  */
1929 static int
1930 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1931                                   uint64_t action_flags,
1932                                   const struct rte_flow_item_vlan *vlan_m,
1933                                   const struct rte_flow_action *action,
1934                                   const struct rte_flow_attr *attr,
1935                                   struct rte_flow_error *error)
1936 {
1937         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1938         const struct mlx5_priv *priv = dev->data->dev_private;
1939
1940         if (!attr->transfer && attr->ingress)
1941                 return rte_flow_error_set(error, ENOTSUP,
1942                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1943                                           NULL,
1944                                           "push VLAN action not supported for "
1945                                           "ingress");
1946         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1947             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1948                 return rte_flow_error_set(error, EINVAL,
1949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1950                                           "invalid vlan ethertype");
1951         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1952                 return rte_flow_error_set(error, ENOTSUP,
1953                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1954                                           "no support for multiple VLAN "
1955                                           "actions");
1956         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "wrong action order, port_id should "
1960                                           "be after push VLAN");
1961         if (!attr->transfer && priv->representor)
1962                 return rte_flow_error_set(error, ENOTSUP,
1963                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1964                                           "push vlan action for VF representor "
1965                                           "not supported on NIC table");
1966         if (vlan_m &&
1967             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1968             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1969                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1970             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1971             !(mlx5_flow_find_action
1972                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "not full match mask on VLAN PCP and "
1976                                           "there is no of_set_vlan_pcp action, "
1977                                           "push VLAN action cannot figure out "
1978                                           "PCP value");
1979         if (vlan_m &&
1980             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1981             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1982                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1983             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1984             !(mlx5_flow_find_action
1985                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1986                 return rte_flow_error_set(error, EINVAL,
1987                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1988                                           "not full match mask on VLAN VID and "
1989                                           "there is no of_set_vlan_vid action, "
1990                                           "push VLAN action cannot figure out "
1991                                           "VID value");
1992         (void)attr;
1993         return 0;
1994 }
1995
1996 /**
1997  * Validate the set VLAN PCP.
1998  *
1999  * @param[in] action_flags
2000  *   Holds the actions detected until now.
2001  * @param[in] actions
2002  *   Pointer to the list of actions remaining in the flow rule.
2003  * @param[out] error
2004  *   Pointer to error structure.
2005  *
2006  * @return
2007  *   0 on success, a negative errno value otherwise and rte_errno is set.
2008  */
2009 static int
2010 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2011                                      const struct rte_flow_action actions[],
2012                                      struct rte_flow_error *error)
2013 {
2014         const struct rte_flow_action *action = actions;
2015         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2016
2017         if (conf->vlan_pcp > 7)
2018                 return rte_flow_error_set(error, EINVAL,
2019                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2020                                           "VLAN PCP value is too big");
2021         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "set VLAN PCP action must follow "
2025                                           "the push VLAN action");
2026         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2029                                           "Multiple VLAN PCP modification are "
2030                                           "not supported");
2031         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2032                 return rte_flow_error_set(error, EINVAL,
2033                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2034                                           "wrong action order, port_id should "
2035                                           "be after set VLAN PCP");
2036         return 0;
2037 }
2038
2039 /**
2040  * Validate the set VLAN VID.
2041  *
2042  * @param[in] item_flags
2043  *   Holds the items detected in this rule.
2044  * @param[in] action_flags
2045  *   Holds the actions detected until now.
2046  * @param[in] actions
2047  *   Pointer to the list of actions remaining in the flow rule.
2048  * @param[out] error
2049  *   Pointer to error structure.
2050  *
2051  * @return
2052  *   0 on success, a negative errno value otherwise and rte_errno is set.
2053  */
2054 static int
2055 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2056                                      uint64_t action_flags,
2057                                      const struct rte_flow_action actions[],
2058                                      struct rte_flow_error *error)
2059 {
2060         const struct rte_flow_action *action = actions;
2061         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2062
2063         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2064                 return rte_flow_error_set(error, EINVAL,
2065                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2066                                           "VLAN VID value is too big");
2067         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2068             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2069                 return rte_flow_error_set(error, ENOTSUP,
2070                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2071                                           "set VLAN VID action must follow push"
2072                                           " VLAN action or match on VLAN item");
2073         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2076                                           "Multiple VLAN VID modifications are "
2077                                           "not supported");
2078         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2079                 return rte_flow_error_set(error, EINVAL,
2080                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2081                                           "wrong action order, port_id should "
2082                                           "be after set VLAN VID");
2083         return 0;
2084 }
2085
2086 /*
2087  * Validate the FLAG action.
2088  *
2089  * @param[in] dev
2090  *   Pointer to the rte_eth_dev structure.
2091  * @param[in] action_flags
2092  *   Holds the actions detected until now.
2093  * @param[in] attr
2094  *   Pointer to flow attributes
2095  * @param[out] error
2096  *   Pointer to error structure.
2097  *
2098  * @return
2099  *   0 on success, a negative errno value otherwise and rte_errno is set.
2100  */
2101 static int
2102 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2103                              uint64_t action_flags,
2104                              const struct rte_flow_attr *attr,
2105                              struct rte_flow_error *error)
2106 {
2107         struct mlx5_priv *priv = dev->data->dev_private;
2108         struct mlx5_dev_config *config = &priv->config;
2109         int ret;
2110
2111         /* Fall back if no extended metadata register support. */
2112         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2113                 return mlx5_flow_validate_action_flag(action_flags, attr,
2114                                                       error);
2115         /* Extensive metadata mode requires registers. */
2116         if (!mlx5_flow_ext_mreg_supported(dev))
2117                 return rte_flow_error_set(error, ENOTSUP,
2118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2119                                           "no metadata registers "
2120                                           "to support flag action");
2121         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2122                 return rte_flow_error_set(error, ENOTSUP,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2124                                           "extended metadata register"
2125                                           " isn't available");
2126         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2127         if (ret < 0)
2128                 return ret;
2129         MLX5_ASSERT(ret > 0);
2130         if (action_flags & MLX5_FLOW_ACTION_MARK)
2131                 return rte_flow_error_set(error, EINVAL,
2132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2133                                           "can't mark and flag in same flow");
2134         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't have 2 flag"
2138                                           " actions in same flow");
2139         return 0;
2140 }
2141
2142 /**
2143  * Validate MARK action.
2144  *
2145  * @param[in] dev
2146  *   Pointer to the rte_eth_dev structure.
2147  * @param[in] action
2148  *   Pointer to action.
2149  * @param[in] action_flags
2150  *   Holds the actions detected until now.
2151  * @param[in] attr
2152  *   Pointer to flow attributes
2153  * @param[out] error
2154  *   Pointer to error structure.
2155  *
2156  * @return
2157  *   0 on success, a negative errno value otherwise and rte_errno is set.
2158  */
2159 static int
2160 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2161                              const struct rte_flow_action *action,
2162                              uint64_t action_flags,
2163                              const struct rte_flow_attr *attr,
2164                              struct rte_flow_error *error)
2165 {
2166         struct mlx5_priv *priv = dev->data->dev_private;
2167         struct mlx5_dev_config *config = &priv->config;
2168         const struct rte_flow_action_mark *mark = action->conf;
2169         int ret;
2170
2171         /* Fall back if no extended metadata register support. */
2172         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2173                 return mlx5_flow_validate_action_mark(action, action_flags,
2174                                                       attr, error);
2175         /* Extensive metadata mode requires registers. */
2176         if (!mlx5_flow_ext_mreg_supported(dev))
2177                 return rte_flow_error_set(error, ENOTSUP,
2178                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2179                                           "no metadata registers "
2180                                           "to support mark action");
2181         if (!priv->sh->dv_mark_mask)
2182                 return rte_flow_error_set(error, ENOTSUP,
2183                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184                                           "extended metadata register"
2185                                           " isn't available");
2186         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2187         if (ret < 0)
2188                 return ret;
2189         MLX5_ASSERT(ret > 0);
2190         if (!mark)
2191                 return rte_flow_error_set(error, EINVAL,
2192                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2193                                           "configuration cannot be null");
2194         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2197                                           &mark->id,
2198                                           "mark id exceeds the limit");
2199         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2200                 return rte_flow_error_set(error, EINVAL,
2201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2202                                           "can't flag and mark in same flow");
2203         if (action_flags & MLX5_FLOW_ACTION_MARK)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't have 2 mark actions in same"
2207                                           " flow");
2208         return 0;
2209 }
2210
2211 /**
2212  * Validate SET_META action.
2213  *
2214  * @param[in] dev
2215  *   Pointer to the rte_eth_dev structure.
2216  * @param[in] action
2217  *   Pointer to the action structure.
2218  * @param[in] action_flags
2219  *   Holds the actions detected until now.
2220  * @param[in] attr
2221  *   Pointer to flow attributes
2222  * @param[out] error
2223  *   Pointer to error structure.
2224  *
2225  * @return
2226  *   0 on success, a negative errno value otherwise and rte_errno is set.
2227  */
2228 static int
2229 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2230                                  const struct rte_flow_action *action,
2231                                  uint64_t action_flags __rte_unused,
2232                                  const struct rte_flow_attr *attr,
2233                                  struct rte_flow_error *error)
2234 {
2235         const struct rte_flow_action_set_meta *conf;
2236         uint32_t nic_mask = UINT32_MAX;
2237         int reg;
2238
2239         if (!mlx5_flow_ext_mreg_supported(dev))
2240                 return rte_flow_error_set(error, ENOTSUP,
2241                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2242                                           "extended metadata register"
2243                                           " isn't supported");
2244         reg = flow_dv_get_metadata_reg(dev, attr, error);
2245         if (reg < 0)
2246                 return reg;
2247         if (reg != REG_A && reg != REG_B) {
2248                 struct mlx5_priv *priv = dev->data->dev_private;
2249
2250                 nic_mask = priv->sh->dv_meta_mask;
2251         }
2252         if (!(action->conf))
2253                 return rte_flow_error_set(error, EINVAL,
2254                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2255                                           "configuration cannot be null");
2256         conf = (const struct rte_flow_action_set_meta *)action->conf;
2257         if (!conf->mask)
2258                 return rte_flow_error_set(error, EINVAL,
2259                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2260                                           "zero mask doesn't have any effect");
2261         if (conf->mask & ~nic_mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "meta data must be within reg C0");
2265         return 0;
2266 }
2267
2268 /**
2269  * Validate SET_TAG action.
2270  *
2271  * @param[in] dev
2272  *   Pointer to the rte_eth_dev structure.
2273  * @param[in] action
2274  *   Pointer to the action structure.
2275  * @param[in] action_flags
2276  *   Holds the actions detected until now.
2277  * @param[in] attr
2278  *   Pointer to flow attributes
2279  * @param[out] error
2280  *   Pointer to error structure.
2281  *
2282  * @return
2283  *   0 on success, a negative errno value otherwise and rte_errno is set.
2284  */
2285 static int
2286 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2287                                 const struct rte_flow_action *action,
2288                                 uint64_t action_flags,
2289                                 const struct rte_flow_attr *attr,
2290                                 struct rte_flow_error *error)
2291 {
2292         const struct rte_flow_action_set_tag *conf;
2293         const uint64_t terminal_action_flags =
2294                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2295                 MLX5_FLOW_ACTION_RSS;
2296         int ret;
2297
2298         if (!mlx5_flow_ext_mreg_supported(dev))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "extensive metadata register"
2302                                           " isn't supported");
2303         if (!(action->conf))
2304                 return rte_flow_error_set(error, EINVAL,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "configuration cannot be null");
2307         conf = (const struct rte_flow_action_set_tag *)action->conf;
2308         if (!conf->mask)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "zero mask doesn't have any effect");
2312         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2313         if (ret < 0)
2314                 return ret;
2315         if (!attr->transfer && attr->ingress &&
2316             (action_flags & terminal_action_flags))
2317                 return rte_flow_error_set(error, EINVAL,
2318                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2319                                           "set_tag has no effect"
2320                                           " with terminal actions");
2321         return 0;
2322 }
2323
2324 /**
2325  * Validate count action.
2326  *
2327  * @param[in] dev
2328  *   Pointer to rte_eth_dev structure.
2329  * @param[out] error
2330  *   Pointer to error structure.
2331  *
2332  * @return
2333  *   0 on success, a negative errno value otherwise and rte_errno is set.
2334  */
2335 static int
2336 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2337                               struct rte_flow_error *error)
2338 {
2339         struct mlx5_priv *priv = dev->data->dev_private;
2340
2341         if (!priv->config.devx)
2342                 goto notsup_err;
2343 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344         return 0;
2345 #endif
2346 notsup_err:
2347         return rte_flow_error_set
2348                       (error, ENOTSUP,
2349                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2350                        NULL,
2351                        "count action not supported");
2352 }
2353
2354 /**
2355  * Validate the L2 encap action.
2356  *
2357  * @param[in] dev
2358  *   Pointer to the rte_eth_dev structure.
2359  * @param[in] action_flags
2360  *   Holds the actions detected until now.
2361  * @param[in] action
2362  *   Pointer to the action structure.
2363  * @param[in] attr
2364  *   Pointer to flow attributes.
2365  * @param[out] error
2366  *   Pointer to error structure.
2367  *
2368  * @return
2369  *   0 on success, a negative errno value otherwise and rte_errno is set.
2370  */
2371 static int
2372 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2373                                  uint64_t action_flags,
2374                                  const struct rte_flow_action *action,
2375                                  const struct rte_flow_attr *attr,
2376                                  struct rte_flow_error *error)
2377 {
2378         const struct mlx5_priv *priv = dev->data->dev_private;
2379
2380         if (!(action->conf))
2381                 return rte_flow_error_set(error, EINVAL,
2382                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2383                                           "configuration cannot be null");
2384         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "can only have a single encap action "
2388                                           "in a flow");
2389         if (!attr->transfer && priv->representor)
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2392                                           "encap action for VF representor "
2393                                           "not supported on NIC table");
2394         return 0;
2395 }
2396
2397 /**
2398  * Validate a decap action.
2399  *
2400  * @param[in] dev
2401  *   Pointer to the rte_eth_dev structure.
2402  * @param[in] action_flags
2403  *   Holds the actions detected until now.
2404  * @param[in] attr
2405  *   Pointer to flow attributes
2406  * @param[out] error
2407  *   Pointer to error structure.
2408  *
2409  * @return
2410  *   0 on success, a negative errno value otherwise and rte_errno is set.
2411  */
2412 static int
2413 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2414                               uint64_t action_flags,
2415                               const struct rte_flow_attr *attr,
2416                               struct rte_flow_error *error)
2417 {
2418         const struct mlx5_priv *priv = dev->data->dev_private;
2419
2420         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           action_flags &
2424                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2425                                           "have a single decap action" : "decap "
2426                                           "after encap is not supported");
2427         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2428                 return rte_flow_error_set(error, EINVAL,
2429                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2430                                           "can't have decap action after"
2431                                           " modify action");
2432         if (attr->egress)
2433                 return rte_flow_error_set(error, ENOTSUP,
2434                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2435                                           NULL,
2436                                           "decap action not supported for "
2437                                           "egress");
2438         if (!attr->transfer && priv->representor)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2441                                           "decap action for VF representor "
2442                                           "not supported on NIC table");
2443         return 0;
2444 }
2445
2446 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2447
2448 /**
2449  * Validate the raw encap and decap actions.
2450  *
2451  * @param[in] dev
2452  *   Pointer to the rte_eth_dev structure.
2453  * @param[in] decap
2454  *   Pointer to the decap action.
2455  * @param[in] encap
2456  *   Pointer to the encap action.
2457  * @param[in] attr
2458  *   Pointer to flow attributes
2459  * @param[in/out] action_flags
2460  *   Holds the actions detected until now.
2461  * @param[out] actions_n
2462  *   pointer to the number of actions counter.
2463  * @param[out] error
2464  *   Pointer to error structure.
2465  *
2466  * @return
2467  *   0 on success, a negative errno value otherwise and rte_errno is set.
2468  */
2469 static int
2470 flow_dv_validate_action_raw_encap_decap
2471         (struct rte_eth_dev *dev,
2472          const struct rte_flow_action_raw_decap *decap,
2473          const struct rte_flow_action_raw_encap *encap,
2474          const struct rte_flow_attr *attr, uint64_t *action_flags,
2475          int *actions_n, struct rte_flow_error *error)
2476 {
2477         const struct mlx5_priv *priv = dev->data->dev_private;
2478         int ret;
2479
2480         if (encap && (!encap->size || !encap->data))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483                                           "raw encap data cannot be empty");
2484         if (decap && encap) {
2485                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2486                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2487                         /* L3 encap. */
2488                         decap = NULL;
2489                 else if (encap->size <=
2490                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2491                            decap->size >
2492                            MLX5_ENCAPSULATION_DECISION_SIZE)
2493                         /* L3 decap. */
2494                         encap = NULL;
2495                 else if (encap->size >
2496                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2497                            decap->size >
2498                            MLX5_ENCAPSULATION_DECISION_SIZE)
2499                         /* 2 L2 actions: encap and decap. */
2500                         ;
2501                 else
2502                         return rte_flow_error_set(error,
2503                                 ENOTSUP,
2504                                 RTE_FLOW_ERROR_TYPE_ACTION,
2505                                 NULL, "unsupported too small "
2506                                 "raw decap and too small raw "
2507                                 "encap combination");
2508         }
2509         if (decap) {
2510                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511                                                     error);
2512                 if (ret < 0)
2513                         return ret;
2514                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515                 ++(*actions_n);
2516         }
2517         if (encap) {
2518                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2519                         return rte_flow_error_set(error, ENOTSUP,
2520                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2521                                                   NULL,
2522                                                   "small raw encap size");
2523                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2524                         return rte_flow_error_set(error, EINVAL,
2525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2526                                                   NULL,
2527                                                   "more than one encap action");
2528                 if (!attr->transfer && priv->representor)
2529                         return rte_flow_error_set
2530                                         (error, ENOTSUP,
2531                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2532                                          "encap action for VF representor "
2533                                          "not supported on NIC table");
2534                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2535                 ++(*actions_n);
2536         }
2537         return 0;
2538 }
2539
2540 /**
2541  * Find existing encap/decap resource or create and register a new one.
2542  *
2543  * @param[in, out] dev
2544  *   Pointer to rte_eth_dev structure.
2545  * @param[in, out] resource
2546  *   Pointer to encap/decap resource.
2547  * @parm[in, out] dev_flow
2548  *   Pointer to the dev_flow.
2549  * @param[out] error
2550  *   pointer to error structure.
2551  *
2552  * @return
2553  *   0 on success otherwise -errno and errno is set.
2554  */
2555 static int
2556 flow_dv_encap_decap_resource_register
2557                         (struct rte_eth_dev *dev,
2558                          struct mlx5_flow_dv_encap_decap_resource *resource,
2559                          struct mlx5_flow *dev_flow,
2560                          struct rte_flow_error *error)
2561 {
2562         struct mlx5_priv *priv = dev->data->dev_private;
2563         struct mlx5_dev_ctx_shared *sh = priv->sh;
2564         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2565         struct mlx5dv_dr_domain *domain;
2566         uint32_t idx = 0;
2567
2568         resource->flags = dev_flow->dv.group ? 0 : 1;
2569         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2570                 domain = sh->fdb_domain;
2571         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2572                 domain = sh->rx_domain;
2573         else
2574                 domain = sh->tx_domain;
2575         /* Lookup a matching resource from cache. */
2576         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2577                       cache_resource, next) {
2578                 if (resource->reformat_type == cache_resource->reformat_type &&
2579                     resource->ft_type == cache_resource->ft_type &&
2580                     resource->flags == cache_resource->flags &&
2581                     resource->size == cache_resource->size &&
2582                     !memcmp((const void *)resource->buf,
2583                             (const void *)cache_resource->buf,
2584                             resource->size)) {
2585                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2586                                 (void *)cache_resource,
2587                                 rte_atomic32_read(&cache_resource->refcnt));
2588                         rte_atomic32_inc(&cache_resource->refcnt);
2589                         dev_flow->handle->dvh.rix_encap_decap = idx;
2590                         dev_flow->dv.encap_decap = cache_resource;
2591                         return 0;
2592                 }
2593         }
2594         /* Register new encap/decap resource. */
2595         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2596                                        &dev_flow->handle->dvh.rix_encap_decap);
2597         if (!cache_resource)
2598                 return rte_flow_error_set(error, ENOMEM,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600                                           "cannot allocate resource memory");
2601         *cache_resource = *resource;
2602         cache_resource->verbs_action =
2603                 mlx5_glue->dv_create_flow_action_packet_reformat
2604                         (sh->ctx, cache_resource->reformat_type,
2605                          cache_resource->ft_type, domain, cache_resource->flags,
2606                          cache_resource->size,
2607                          (cache_resource->size ? cache_resource->buf : NULL));
2608         if (!cache_resource->verbs_action) {
2609                 rte_free(cache_resource);
2610                 return rte_flow_error_set(error, ENOMEM,
2611                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2612                                           NULL, "cannot create action");
2613         }
2614         rte_atomic32_init(&cache_resource->refcnt);
2615         rte_atomic32_inc(&cache_resource->refcnt);
2616         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2617                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2618                      next);
2619         dev_flow->dv.encap_decap = cache_resource;
2620         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2621                 (void *)cache_resource,
2622                 rte_atomic32_read(&cache_resource->refcnt));
2623         return 0;
2624 }
2625
2626 /**
2627  * Find existing table jump resource or create and register a new one.
2628  *
2629  * @param[in, out] dev
2630  *   Pointer to rte_eth_dev structure.
2631  * @param[in, out] tbl
2632  *   Pointer to flow table resource.
2633  * @parm[in, out] dev_flow
2634  *   Pointer to the dev_flow.
2635  * @param[out] error
2636  *   pointer to error structure.
2637  *
2638  * @return
2639  *   0 on success otherwise -errno and errno is set.
2640  */
2641 static int
2642 flow_dv_jump_tbl_resource_register
2643                         (struct rte_eth_dev *dev __rte_unused,
2644                          struct mlx5_flow_tbl_resource *tbl,
2645                          struct mlx5_flow *dev_flow,
2646                          struct rte_flow_error *error)
2647 {
2648         struct mlx5_flow_tbl_data_entry *tbl_data =
2649                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650         int cnt;
2651
2652         MLX5_ASSERT(tbl);
2653         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2654         if (!cnt) {
2655                 tbl_data->jump.action =
2656                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2657                         (tbl->obj);
2658                 if (!tbl_data->jump.action)
2659                         return rte_flow_error_set(error, ENOMEM,
2660                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2661                                         NULL, "cannot create jump action");
2662                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2663                         (void *)&tbl_data->jump, cnt);
2664         } else {
2665                 /* old jump should not make the table ref++. */
2666                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2667                 MLX5_ASSERT(tbl_data->jump.action);
2668                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         }
2671         rte_atomic32_inc(&tbl_data->jump.refcnt);
2672         dev_flow->handle->rix_jump = tbl_data->idx;
2673         dev_flow->dv.jump = &tbl_data->jump;
2674         return 0;
2675 }
2676
2677 /**
2678  * Find existing table port ID resource or create and register a new one.
2679  *
2680  * @param[in, out] dev
2681  *   Pointer to rte_eth_dev structure.
2682  * @param[in, out] resource
2683  *   Pointer to port ID action resource.
2684  * @parm[in, out] dev_flow
2685  *   Pointer to the dev_flow.
2686  * @param[out] error
2687  *   pointer to error structure.
2688  *
2689  * @return
2690  *   0 on success otherwise -errno and errno is set.
2691  */
2692 static int
2693 flow_dv_port_id_action_resource_register
2694                         (struct rte_eth_dev *dev,
2695                          struct mlx5_flow_dv_port_id_action_resource *resource,
2696                          struct mlx5_flow *dev_flow,
2697                          struct rte_flow_error *error)
2698 {
2699         struct mlx5_priv *priv = dev->data->dev_private;
2700         struct mlx5_dev_ctx_shared *sh = priv->sh;
2701         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2702         uint32_t idx = 0;
2703
2704         /* Lookup a matching resource from cache. */
2705         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2706                       idx, cache_resource, next) {
2707                 if (resource->port_id == cache_resource->port_id) {
2708                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2709                                 "refcnt %d++",
2710                                 (void *)cache_resource,
2711                                 rte_atomic32_read(&cache_resource->refcnt));
2712                         rte_atomic32_inc(&cache_resource->refcnt);
2713                         dev_flow->handle->rix_port_id_action = idx;
2714                         dev_flow->dv.port_id_action = cache_resource;
2715                         return 0;
2716                 }
2717         }
2718         /* Register new port id action resource. */
2719         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2720                                        &dev_flow->handle->rix_port_id_action);
2721         if (!cache_resource)
2722                 return rte_flow_error_set(error, ENOMEM,
2723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2724                                           "cannot allocate resource memory");
2725         *cache_resource = *resource;
2726         /*
2727          * Depending on rdma_core version the glue routine calls
2728          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2729          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2730          */
2731         cache_resource->action =
2732                 mlx5_glue->dr_create_flow_action_dest_port
2733                         (priv->sh->fdb_domain, resource->port_id);
2734         if (!cache_resource->action) {
2735                 rte_free(cache_resource);
2736                 return rte_flow_error_set(error, ENOMEM,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2738                                           NULL, "cannot create action");
2739         }
2740         rte_atomic32_init(&cache_resource->refcnt);
2741         rte_atomic32_inc(&cache_resource->refcnt);
2742         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2743                      dev_flow->handle->rix_port_id_action, cache_resource,
2744                      next);
2745         dev_flow->dv.port_id_action = cache_resource;
2746         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2747                 (void *)cache_resource,
2748                 rte_atomic32_read(&cache_resource->refcnt));
2749         return 0;
2750 }
2751
2752 /**
2753  * Find existing push vlan resource or create and register a new one.
2754  *
2755  * @param [in, out] dev
2756  *   Pointer to rte_eth_dev structure.
2757  * @param[in, out] resource
2758  *   Pointer to port ID action resource.
2759  * @parm[in, out] dev_flow
2760  *   Pointer to the dev_flow.
2761  * @param[out] error
2762  *   pointer to error structure.
2763  *
2764  * @return
2765  *   0 on success otherwise -errno and errno is set.
2766  */
2767 static int
2768 flow_dv_push_vlan_action_resource_register
2769                        (struct rte_eth_dev *dev,
2770                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2771                         struct mlx5_flow *dev_flow,
2772                         struct rte_flow_error *error)
2773 {
2774         struct mlx5_priv *priv = dev->data->dev_private;
2775         struct mlx5_dev_ctx_shared *sh = priv->sh;
2776         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2777         struct mlx5dv_dr_domain *domain;
2778         uint32_t idx = 0;
2779
2780         /* Lookup a matching resource from cache. */
2781         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2782                       sh->push_vlan_action_list, idx, cache_resource, next) {
2783                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2784                     resource->ft_type == cache_resource->ft_type) {
2785                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2786                                 "refcnt %d++",
2787                                 (void *)cache_resource,
2788                                 rte_atomic32_read(&cache_resource->refcnt));
2789                         rte_atomic32_inc(&cache_resource->refcnt);
2790                         dev_flow->handle->dvh.rix_push_vlan = idx;
2791                         dev_flow->dv.push_vlan_res = cache_resource;
2792                         return 0;
2793                 }
2794         }
2795         /* Register new push_vlan action resource. */
2796         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2797                                        &dev_flow->handle->dvh.rix_push_vlan);
2798         if (!cache_resource)
2799                 return rte_flow_error_set(error, ENOMEM,
2800                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2801                                           "cannot allocate resource memory");
2802         *cache_resource = *resource;
2803         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804                 domain = sh->fdb_domain;
2805         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2806                 domain = sh->rx_domain;
2807         else
2808                 domain = sh->tx_domain;
2809         cache_resource->action =
2810                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2811                                                            resource->vlan_tag);
2812         if (!cache_resource->action) {
2813                 rte_free(cache_resource);
2814                 return rte_flow_error_set(error, ENOMEM,
2815                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2816                                           NULL, "cannot create action");
2817         }
2818         rte_atomic32_init(&cache_resource->refcnt);
2819         rte_atomic32_inc(&cache_resource->refcnt);
2820         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                      &sh->push_vlan_action_list,
2822                      dev_flow->handle->dvh.rix_push_vlan,
2823                      cache_resource, next);
2824         dev_flow->dv.push_vlan_res = cache_resource;
2825         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2826                 (void *)cache_resource,
2827                 rte_atomic32_read(&cache_resource->refcnt));
2828         return 0;
2829 }
2830 /**
2831  * Get the size of specific rte_flow_item_type
2832  *
2833  * @param[in] item_type
2834  *   Tested rte_flow_item_type.
2835  *
2836  * @return
2837  *   sizeof struct item_type, 0 if void or irrelevant.
2838  */
2839 static size_t
2840 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 {
2842         size_t retval;
2843
2844         switch (item_type) {
2845         case RTE_FLOW_ITEM_TYPE_ETH:
2846                 retval = sizeof(struct rte_flow_item_eth);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_VLAN:
2849                 retval = sizeof(struct rte_flow_item_vlan);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV4:
2852                 retval = sizeof(struct rte_flow_item_ipv4);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_IPV6:
2855                 retval = sizeof(struct rte_flow_item_ipv6);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_UDP:
2858                 retval = sizeof(struct rte_flow_item_udp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_TCP:
2861                 retval = sizeof(struct rte_flow_item_tcp);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_VXLAN:
2864                 retval = sizeof(struct rte_flow_item_vxlan);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_GRE:
2867                 retval = sizeof(struct rte_flow_item_gre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_NVGRE:
2870                 retval = sizeof(struct rte_flow_item_nvgre);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2873                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_MPLS:
2876                 retval = sizeof(struct rte_flow_item_mpls);
2877                 break;
2878         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2879         default:
2880                 retval = 0;
2881                 break;
2882         }
2883         return retval;
2884 }
2885
2886 #define MLX5_ENCAP_IPV4_VERSION         0x40
2887 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2888 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2889 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2890 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2891 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2892 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2893
2894 /**
2895  * Convert the encap action data from list of rte_flow_item to raw buffer
2896  *
2897  * @param[in] items
2898  *   Pointer to rte_flow_item objects list.
2899  * @param[out] buf
2900  *   Pointer to the output buffer.
2901  * @param[out] size
2902  *   Pointer to the output buffer size.
2903  * @param[out] error
2904  *   Pointer to the error structure.
2905  *
2906  * @return
2907  *   0 on success, a negative errno value otherwise and rte_errno is set.
2908  */
2909 static int
2910 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2911                            size_t *size, struct rte_flow_error *error)
2912 {
2913         struct rte_ether_hdr *eth = NULL;
2914         struct rte_vlan_hdr *vlan = NULL;
2915         struct rte_ipv4_hdr *ipv4 = NULL;
2916         struct rte_ipv6_hdr *ipv6 = NULL;
2917         struct rte_udp_hdr *udp = NULL;
2918         struct rte_vxlan_hdr *vxlan = NULL;
2919         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2920         struct rte_gre_hdr *gre = NULL;
2921         size_t len;
2922         size_t temp_size = 0;
2923
2924         if (!items)
2925                 return rte_flow_error_set(error, EINVAL,
2926                                           RTE_FLOW_ERROR_TYPE_ACTION,
2927                                           NULL, "invalid empty data");
2928         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2929                 len = flow_dv_get_item_len(items->type);
2930                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2931                         return rte_flow_error_set(error, EINVAL,
2932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2933                                                   (void *)items->type,
2934                                                   "items total size is too big"
2935                                                   " for encap action");
2936                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2937                 switch (items->type) {
2938                 case RTE_FLOW_ITEM_TYPE_ETH:
2939                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2940                         break;
2941                 case RTE_FLOW_ITEM_TYPE_VLAN:
2942                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2943                         if (!eth)
2944                                 return rte_flow_error_set(error, EINVAL,
2945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2946                                                 (void *)items->type,
2947                                                 "eth header not found");
2948                         if (!eth->ether_type)
2949                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2950                         break;
2951                 case RTE_FLOW_ITEM_TYPE_IPV4:
2952                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2953                         if (!vlan && !eth)
2954                                 return rte_flow_error_set(error, EINVAL,
2955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2956                                                 (void *)items->type,
2957                                                 "neither eth nor vlan"
2958                                                 " header found");
2959                         if (vlan && !vlan->eth_proto)
2960                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2961                         else if (eth && !eth->ether_type)
2962                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2963                         if (!ipv4->version_ihl)
2964                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2965                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2966                         if (!ipv4->time_to_live)
2967                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2968                         break;
2969                 case RTE_FLOW_ITEM_TYPE_IPV6:
2970                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2971                         if (!vlan && !eth)
2972                                 return rte_flow_error_set(error, EINVAL,
2973                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2974                                                 (void *)items->type,
2975                                                 "neither eth nor vlan"
2976                                                 " header found");
2977                         if (vlan && !vlan->eth_proto)
2978                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2979                         else if (eth && !eth->ether_type)
2980                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2981                         if (!ipv6->vtc_flow)
2982                                 ipv6->vtc_flow =
2983                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2984                         if (!ipv6->hop_limits)
2985                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2986                         break;
2987                 case RTE_FLOW_ITEM_TYPE_UDP:
2988                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2989                         if (!ipv4 && !ipv6)
2990                                 return rte_flow_error_set(error, EINVAL,
2991                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2992                                                 (void *)items->type,
2993                                                 "ip header not found");
2994                         if (ipv4 && !ipv4->next_proto_id)
2995                                 ipv4->next_proto_id = IPPROTO_UDP;
2996                         else if (ipv6 && !ipv6->proto)
2997                                 ipv6->proto = IPPROTO_UDP;
2998                         break;
2999                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3000                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3001                         if (!udp)
3002                                 return rte_flow_error_set(error, EINVAL,
3003                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3004                                                 (void *)items->type,
3005                                                 "udp header not found");
3006                         if (!udp->dst_port)
3007                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3008                         if (!vxlan->vx_flags)
3009                                 vxlan->vx_flags =
3010                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3011                         break;
3012                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3013                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3014                         if (!udp)
3015                                 return rte_flow_error_set(error, EINVAL,
3016                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3017                                                 (void *)items->type,
3018                                                 "udp header not found");
3019                         if (!vxlan_gpe->proto)
3020                                 return rte_flow_error_set(error, EINVAL,
3021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3022                                                 (void *)items->type,
3023                                                 "next protocol not found");
3024                         if (!udp->dst_port)
3025                                 udp->dst_port =
3026                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3027                         if (!vxlan_gpe->vx_flags)
3028                                 vxlan_gpe->vx_flags =
3029                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3030                         break;
3031                 case RTE_FLOW_ITEM_TYPE_GRE:
3032                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3033                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3034                         if (!gre->proto)
3035                                 return rte_flow_error_set(error, EINVAL,
3036                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3037                                                 (void *)items->type,
3038                                                 "next protocol not found");
3039                         if (!ipv4 && !ipv6)
3040                                 return rte_flow_error_set(error, EINVAL,
3041                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3042                                                 (void *)items->type,
3043                                                 "ip header not found");
3044                         if (ipv4 && !ipv4->next_proto_id)
3045                                 ipv4->next_proto_id = IPPROTO_GRE;
3046                         else if (ipv6 && !ipv6->proto)
3047                                 ipv6->proto = IPPROTO_GRE;
3048                         break;
3049                 case RTE_FLOW_ITEM_TYPE_VOID:
3050                         break;
3051                 default:
3052                         return rte_flow_error_set(error, EINVAL,
3053                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3054                                                   (void *)items->type,
3055                                                   "unsupported item type");
3056                         break;
3057                 }
3058                 temp_size += len;
3059         }
3060         *size = temp_size;
3061         return 0;
3062 }
3063
3064 static int
3065 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3066 {
3067         struct rte_ether_hdr *eth = NULL;
3068         struct rte_vlan_hdr *vlan = NULL;
3069         struct rte_ipv6_hdr *ipv6 = NULL;
3070         struct rte_udp_hdr *udp = NULL;
3071         char *next_hdr;
3072         uint16_t proto;
3073
3074         eth = (struct rte_ether_hdr *)data;
3075         next_hdr = (char *)(eth + 1);
3076         proto = RTE_BE16(eth->ether_type);
3077
3078         /* VLAN skipping */
3079         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3080                 vlan = (struct rte_vlan_hdr *)next_hdr;
3081                 proto = RTE_BE16(vlan->eth_proto);
3082                 next_hdr += sizeof(struct rte_vlan_hdr);
3083         }
3084
3085         /* HW calculates IPv4 csum. no need to proceed */
3086         if (proto == RTE_ETHER_TYPE_IPV4)
3087                 return 0;
3088
3089         /* non IPv4/IPv6 header. not supported */
3090         if (proto != RTE_ETHER_TYPE_IPV6) {
3091                 return rte_flow_error_set(error, ENOTSUP,
3092                                           RTE_FLOW_ERROR_TYPE_ACTION,
3093                                           NULL, "Cannot offload non IPv4/IPv6");
3094         }
3095
3096         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3097
3098         /* ignore non UDP */
3099         if (ipv6->proto != IPPROTO_UDP)
3100                 return 0;
3101
3102         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3103         udp->dgram_cksum = 0;
3104
3105         return 0;
3106 }
3107
3108 /**
3109  * Convert L2 encap action to DV specification.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] action
3114  *   Pointer to action structure.
3115  * @param[in, out] dev_flow
3116  *   Pointer to the mlx5_flow.
3117  * @param[in] transfer
3118  *   Mark if the flow is E-Switch flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3127                                const struct rte_flow_action *action,
3128                                struct mlx5_flow *dev_flow,
3129                                uint8_t transfer,
3130                                struct rte_flow_error *error)
3131 {
3132         const struct rte_flow_item *encap_data;
3133         const struct rte_flow_action_raw_encap *raw_encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res = {
3135                 .reformat_type =
3136                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3137                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3138                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3139         };
3140
3141         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3142                 raw_encap_data =
3143                         (const struct rte_flow_action_raw_encap *)action->conf;
3144                 res.size = raw_encap_data->size;
3145                 memcpy(res.buf, raw_encap_data->data, res.size);
3146         } else {
3147                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3148                         encap_data =
3149                                 ((const struct rte_flow_action_vxlan_encap *)
3150                                                 action->conf)->definition;
3151                 else
3152                         encap_data =
3153                                 ((const struct rte_flow_action_nvgre_encap *)
3154                                                 action->conf)->definition;
3155                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156                                                &res.size, error))
3157                         return -rte_errno;
3158         }
3159         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3160                 return -rte_errno;
3161         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION,
3164                                           NULL, "can't create L2 encap action");
3165         return 0;
3166 }
3167
3168 /**
3169  * Convert L2 decap action to DV specification.
3170  *
3171  * @param[in] dev
3172  *   Pointer to rte_eth_dev structure.
3173  * @param[in, out] dev_flow
3174  *   Pointer to the mlx5_flow.
3175  * @param[in] transfer
3176  *   Mark if the flow is E-Switch flow.
3177  * @param[out] error
3178  *   Pointer to the error structure.
3179  *
3180  * @return
3181  *   0 on success, a negative errno value otherwise and rte_errno is set.
3182  */
3183 static int
3184 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3185                                struct mlx5_flow *dev_flow,
3186                                uint8_t transfer,
3187                                struct rte_flow_error *error)
3188 {
3189         struct mlx5_flow_dv_encap_decap_resource res = {
3190                 .size = 0,
3191                 .reformat_type =
3192                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3193                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3194                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3195         };
3196
3197         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3198                 return rte_flow_error_set(error, EINVAL,
3199                                           RTE_FLOW_ERROR_TYPE_ACTION,
3200                                           NULL, "can't create L2 decap action");
3201         return 0;
3202 }
3203
3204 /**
3205  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3206  *
3207  * @param[in] dev
3208  *   Pointer to rte_eth_dev structure.
3209  * @param[in] action
3210  *   Pointer to action structure.
3211  * @param[in, out] dev_flow
3212  *   Pointer to the mlx5_flow.
3213  * @param[in] attr
3214  *   Pointer to the flow attributes.
3215  * @param[out] error
3216  *   Pointer to the error structure.
3217  *
3218  * @return
3219  *   0 on success, a negative errno value otherwise and rte_errno is set.
3220  */
3221 static int
3222 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3223                                 const struct rte_flow_action *action,
3224                                 struct mlx5_flow *dev_flow,
3225                                 const struct rte_flow_attr *attr,
3226                                 struct rte_flow_error *error)
3227 {
3228         const struct rte_flow_action_raw_encap *encap_data;
3229         struct mlx5_flow_dv_encap_decap_resource res;
3230
3231         memset(&res, 0, sizeof(res));
3232         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3233         res.size = encap_data->size;
3234         memcpy(res.buf, encap_data->data, res.size);
3235         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3236                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3237                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3238         if (attr->transfer)
3239                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3240         else
3241                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3242                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3243         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3244                 return rte_flow_error_set(error, EINVAL,
3245                                           RTE_FLOW_ERROR_TYPE_ACTION,
3246                                           NULL, "can't create encap action");
3247         return 0;
3248 }
3249
3250 /**
3251  * Create action push VLAN.
3252  *
3253  * @param[in] dev
3254  *   Pointer to rte_eth_dev structure.
3255  * @param[in] attr
3256  *   Pointer to the flow attributes.
3257  * @param[in] vlan
3258  *   Pointer to the vlan to push to the Ethernet header.
3259  * @param[in, out] dev_flow
3260  *   Pointer to the mlx5_flow.
3261  * @param[out] error
3262  *   Pointer to the error structure.
3263  *
3264  * @return
3265  *   0 on success, a negative errno value otherwise and rte_errno is set.
3266  */
3267 static int
3268 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3269                                 const struct rte_flow_attr *attr,
3270                                 const struct rte_vlan_hdr *vlan,
3271                                 struct mlx5_flow *dev_flow,
3272                                 struct rte_flow_error *error)
3273 {
3274         struct mlx5_flow_dv_push_vlan_action_resource res;
3275
3276         memset(&res, 0, sizeof(res));
3277         res.vlan_tag =
3278                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3279                                  vlan->vlan_tci);
3280         if (attr->transfer)
3281                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282         else
3283                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3284                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3285         return flow_dv_push_vlan_action_resource_register
3286                                             (dev, &res, dev_flow, error);
3287 }
3288
3289 /**
3290  * Validate the modify-header actions.
3291  *
3292  * @param[in] action_flags
3293  *   Holds the actions detected until now.
3294  * @param[in] action
3295  *   Pointer to the modify action.
3296  * @param[out] error
3297  *   Pointer to error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3304                                    const struct rte_flow_action *action,
3305                                    struct rte_flow_error *error)
3306 {
3307         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3308                 return rte_flow_error_set(error, EINVAL,
3309                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3310                                           NULL, "action configuration not set");
3311         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3312                 return rte_flow_error_set(error, EINVAL,
3313                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314                                           "can't have encap action before"
3315                                           " modify action");
3316         return 0;
3317 }
3318
3319 /**
3320  * Validate the modify-header MAC address actions.
3321  *
3322  * @param[in] action_flags
3323  *   Holds the actions detected until now.
3324  * @param[in] action
3325  *   Pointer to the modify action.
3326  * @param[in] item_flags
3327  *   Holds the items detected.
3328  * @param[out] error
3329  *   Pointer to error structure.
3330  *
3331  * @return
3332  *   0 on success, a negative errno value otherwise and rte_errno is set.
3333  */
3334 static int
3335 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3336                                    const struct rte_flow_action *action,
3337                                    const uint64_t item_flags,
3338                                    struct rte_flow_error *error)
3339 {
3340         int ret = 0;
3341
3342         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3343         if (!ret) {
3344                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3345                         return rte_flow_error_set(error, EINVAL,
3346                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3347                                                   NULL,
3348                                                   "no L2 item in pattern");
3349         }
3350         return ret;
3351 }
3352
3353 /**
3354  * Validate the modify-header IPv4 address actions.
3355  *
3356  * @param[in] action_flags
3357  *   Holds the actions detected until now.
3358  * @param[in] action
3359  *   Pointer to the modify action.
3360  * @param[in] item_flags
3361  *   Holds the items detected.
3362  * @param[out] error
3363  *   Pointer to error structure.
3364  *
3365  * @return
3366  *   0 on success, a negative errno value otherwise and rte_errno is set.
3367  */
3368 static int
3369 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3370                                     const struct rte_flow_action *action,
3371                                     const uint64_t item_flags,
3372                                     struct rte_flow_error *error)
3373 {
3374         int ret = 0;
3375         uint64_t layer;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3380                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3381                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3382                 if (!(item_flags & layer))
3383                         return rte_flow_error_set(error, EINVAL,
3384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3385                                                   NULL,
3386                                                   "no ipv4 item in pattern");
3387         }
3388         return ret;
3389 }
3390
3391 /**
3392  * Validate the modify-header IPv6 address actions.
3393  *
3394  * @param[in] action_flags
3395  *   Holds the actions detected until now.
3396  * @param[in] action
3397  *   Pointer to the modify action.
3398  * @param[in] item_flags
3399  *   Holds the items detected.
3400  * @param[out] error
3401  *   Pointer to error structure.
3402  *
3403  * @return
3404  *   0 on success, a negative errno value otherwise and rte_errno is set.
3405  */
3406 static int
3407 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3408                                     const struct rte_flow_action *action,
3409                                     const uint64_t item_flags,
3410                                     struct rte_flow_error *error)
3411 {
3412         int ret = 0;
3413         uint64_t layer;
3414
3415         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3416         if (!ret) {
3417                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3418                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3419                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3420                 if (!(item_flags & layer))
3421                         return rte_flow_error_set(error, EINVAL,
3422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3423                                                   NULL,
3424                                                   "no ipv6 item in pattern");
3425         }
3426         return ret;
3427 }
3428
3429 /**
3430  * Validate the modify-header TP actions.
3431  *
3432  * @param[in] action_flags
3433  *   Holds the actions detected until now.
3434  * @param[in] action
3435  *   Pointer to the modify action.
3436  * @param[in] item_flags
3437  *   Holds the items detected.
3438  * @param[out] error
3439  *   Pointer to error structure.
3440  *
3441  * @return
3442  *   0 on success, a negative errno value otherwise and rte_errno is set.
3443  */
3444 static int
3445 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3446                                   const struct rte_flow_action *action,
3447                                   const uint64_t item_flags,
3448                                   struct rte_flow_error *error)
3449 {
3450         int ret = 0;
3451         uint64_t layer;
3452
3453         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3454         if (!ret) {
3455                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3456                                  MLX5_FLOW_LAYER_INNER_L4 :
3457                                  MLX5_FLOW_LAYER_OUTER_L4;
3458                 if (!(item_flags & layer))
3459                         return rte_flow_error_set(error, EINVAL,
3460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3461                                                   NULL, "no transport layer "
3462                                                   "in pattern");
3463         }
3464         return ret;
3465 }
3466
3467 /**
3468  * Validate the modify-header actions of increment/decrement
3469  * TCP Sequence-number.
3470  *
3471  * @param[in] action_flags
3472  *   Holds the actions detected until now.
3473  * @param[in] action
3474  *   Pointer to the modify action.
3475  * @param[in] item_flags
3476  *   Holds the items detected.
3477  * @param[out] error
3478  *   Pointer to error structure.
3479  *
3480  * @return
3481  *   0 on success, a negative errno value otherwise and rte_errno is set.
3482  */
3483 static int
3484 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3485                                        const struct rte_flow_action *action,
3486                                        const uint64_t item_flags,
3487                                        struct rte_flow_error *error)
3488 {
3489         int ret = 0;
3490         uint64_t layer;
3491
3492         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493         if (!ret) {
3494                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3496                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3497                 if (!(item_flags & layer))
3498                         return rte_flow_error_set(error, EINVAL,
3499                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3500                                                   NULL, "no TCP item in"
3501                                                   " pattern");
3502                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3503                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3504                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3505                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3506                         return rte_flow_error_set(error, EINVAL,
3507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3508                                                   NULL,
3509                                                   "cannot decrease and increase"
3510                                                   " TCP sequence number"
3511                                                   " at the same time");
3512         }
3513         return ret;
3514 }
3515
3516 /**
3517  * Validate the modify-header actions of increment/decrement
3518  * TCP Acknowledgment number.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3534                                        const struct rte_flow_action *action,
3535                                        const uint64_t item_flags,
3536                                        struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539         uint64_t layer;
3540
3541         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542         if (!ret) {
3543                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3544                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3545                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3546                 if (!(item_flags & layer))
3547                         return rte_flow_error_set(error, EINVAL,
3548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3549                                                   NULL, "no TCP item in"
3550                                                   " pattern");
3551                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3552                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3553                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3554                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3555                         return rte_flow_error_set(error, EINVAL,
3556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3557                                                   NULL,
3558                                                   "cannot decrease and increase"
3559                                                   " TCP acknowledgment number"
3560                                                   " at the same time");
3561         }
3562         return ret;
3563 }
3564
3565 /**
3566  * Validate the modify-header TTL actions.
3567  *
3568  * @param[in] action_flags
3569  *   Holds the actions detected until now.
3570  * @param[in] action
3571  *   Pointer to the modify action.
3572  * @param[in] item_flags
3573  *   Holds the items detected.
3574  * @param[out] error
3575  *   Pointer to error structure.
3576  *
3577  * @return
3578  *   0 on success, a negative errno value otherwise and rte_errno is set.
3579  */
3580 static int
3581 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3582                                    const struct rte_flow_action *action,
3583                                    const uint64_t item_flags,
3584                                    struct rte_flow_error *error)
3585 {
3586         int ret = 0;
3587         uint64_t layer;
3588
3589         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3590         if (!ret) {
3591                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3592                                  MLX5_FLOW_LAYER_INNER_L3 :
3593                                  MLX5_FLOW_LAYER_OUTER_L3;
3594                 if (!(item_flags & layer))
3595                         return rte_flow_error_set(error, EINVAL,
3596                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3597                                                   NULL,
3598                                                   "no IP protocol in pattern");
3599         }
3600         return ret;
3601 }
3602
3603 /**
3604  * Validate jump action.
3605  *
3606  * @param[in] action
3607  *   Pointer to the jump action.
3608  * @param[in] action_flags
3609  *   Holds the actions detected until now.
3610  * @param[in] attributes
3611  *   Pointer to flow attributes
3612  * @param[in] external
3613  *   Action belongs to flow rule created by request external to PMD.
3614  * @param[out] error
3615  *   Pointer to error structure.
3616  *
3617  * @return
3618  *   0 on success, a negative errno value otherwise and rte_errno is set.
3619  */
3620 static int
3621 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3622                              uint64_t action_flags,
3623                              const struct rte_flow_attr *attributes,
3624                              bool external, struct rte_flow_error *error)
3625 {
3626         uint32_t target_group, table;
3627         int ret = 0;
3628
3629         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3630                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3631                 return rte_flow_error_set(error, EINVAL,
3632                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3633                                           "can't have 2 fate actions in"
3634                                           " same flow");
3635         if (action_flags & MLX5_FLOW_ACTION_METER)
3636                 return rte_flow_error_set(error, ENOTSUP,
3637                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3638                                           "jump with meter not support");
3639         if (!action->conf)
3640                 return rte_flow_error_set(error, EINVAL,
3641                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3642                                           NULL, "action configuration not set");
3643         target_group =
3644                 ((const struct rte_flow_action_jump *)action->conf)->group;
3645         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3646                                        true, &table, error);
3647         if (ret)
3648                 return ret;
3649         if (attributes->group == target_group)
3650                 return rte_flow_error_set(error, EINVAL,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "target group must be other than"
3653                                           " the current flow group");
3654         return 0;
3655 }
3656
3657 /*
3658  * Validate the port_id action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Port_id RTE action structure.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_errno is set.
3673  */
3674 static int
3675 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         const struct rte_flow_action_port_id *port_id;
3682         struct mlx5_priv *act_priv;
3683         struct mlx5_priv *dev_priv;
3684         uint16_t port;
3685
3686         if (!attr->transfer)
3687                 return rte_flow_error_set(error, ENOTSUP,
3688                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3689                                           NULL,
3690                                           "port id action is valid in transfer"
3691                                           " mode only");
3692         if (!action || !action->conf)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL,
3696                                           "port id action parameters must be"
3697                                           " specified");
3698         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3699                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3700                 return rte_flow_error_set(error, EINVAL,
3701                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3702                                           "can have only one fate actions in"
3703                                           " a flow");
3704         dev_priv = mlx5_dev_to_eswitch_info(dev);
3705         if (!dev_priv)
3706                 return rte_flow_error_set(error, rte_errno,
3707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3708                                           NULL,
3709                                           "failed to obtain E-Switch info");
3710         port_id = action->conf;
3711         port = port_id->original ? dev->data->port_id : port_id->id;
3712         act_priv = mlx5_port_to_eswitch_info(port, false);
3713         if (!act_priv)
3714                 return rte_flow_error_set
3715                                 (error, rte_errno,
3716                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3717                                  "failed to obtain E-Switch port id for port");
3718         if (act_priv->domain_id != dev_priv->domain_id)
3719                 return rte_flow_error_set
3720                                 (error, EINVAL,
3721                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3722                                  "port does not belong to"
3723                                  " E-Switch being configured");
3724         return 0;
3725 }
3726
3727 /**
3728  * Get the maximum number of modify header actions.
3729  *
3730  * @param dev
3731  *   Pointer to rte_eth_dev structure.
3732  * @param flags
3733  *   Flags bits to check if root level.
3734  *
3735  * @return
3736  *   Max number of modify header actions device can support.
3737  */
3738 static inline unsigned int
3739 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740                               uint64_t flags)
3741 {
3742         /*
3743          * There's no way to directly query the max capacity from FW.
3744          * The maximal value on root table should be assumed to be supported.
3745          */
3746         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3747                 return MLX5_MAX_MODIFY_NUM;
3748         else
3749                 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 }
3751
3752 /**
3753  * Validate the meter action.
3754  *
3755  * @param[in] dev
3756  *   Pointer to rte_eth_dev structure.
3757  * @param[in] action_flags
3758  *   Bit-fields that holds the actions detected until now.
3759  * @param[in] action
3760  *   Pointer to the meter action.
3761  * @param[in] attr
3762  *   Attributes of flow that includes this action.
3763  * @param[out] error
3764  *   Pointer to error structure.
3765  *
3766  * @return
3767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3768  */
3769 static int
3770 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3771                                 uint64_t action_flags,
3772                                 const struct rte_flow_action *action,
3773                                 const struct rte_flow_attr *attr,
3774                                 struct rte_flow_error *error)
3775 {
3776         struct mlx5_priv *priv = dev->data->dev_private;
3777         const struct rte_flow_action_meter *am = action->conf;
3778         struct mlx5_flow_meter *fm;
3779
3780         if (!am)
3781                 return rte_flow_error_set(error, EINVAL,
3782                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3783                                           "meter action conf is NULL");
3784
3785         if (action_flags & MLX5_FLOW_ACTION_METER)
3786                 return rte_flow_error_set(error, ENOTSUP,
3787                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3788                                           "meter chaining not support");
3789         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3790                 return rte_flow_error_set(error, ENOTSUP,
3791                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3792                                           "meter with jump not support");
3793         if (!priv->mtr_en)
3794                 return rte_flow_error_set(error, ENOTSUP,
3795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3796                                           NULL,
3797                                           "meter action not supported");
3798         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3799         if (!fm)
3800                 return rte_flow_error_set(error, EINVAL,
3801                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3802                                           "Meter not found");
3803         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3804               (!fm->ingress && !attr->ingress && attr->egress) ||
3805               (!fm->egress && !attr->egress && attr->ingress))))
3806                 return rte_flow_error_set(error, EINVAL,
3807                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3808                                           "Flow attributes are either invalid "
3809                                           "or have a conflict with current "
3810                                           "meter attributes");
3811         return 0;
3812 }
3813
3814 /**
3815  * Validate the age action.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the age action.
3821  * @param[in] dev
3822  *   Pointer to the Ethernet device structure.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_age(uint64_t action_flags,
3831                             const struct rte_flow_action *action,
3832                             struct rte_eth_dev *dev,
3833                             struct rte_flow_error *error)
3834 {
3835         struct mlx5_priv *priv = dev->data->dev_private;
3836         const struct rte_flow_action_age *age = action->conf;
3837
3838         if (!priv->config.devx || priv->counter_fallback)
3839                 return rte_flow_error_set(error, ENOTSUP,
3840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3841                                           NULL,
3842                                           "age action not supported");
3843         if (!(action->conf))
3844                 return rte_flow_error_set(error, EINVAL,
3845                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3846                                           "configuration cannot be null");
3847         if (age->timeout >= UINT16_MAX / 2 / 10)
3848                 return rte_flow_error_set(error, ENOTSUP,
3849                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3850                                           "Max age time: 3275 seconds");
3851         if (action_flags & MLX5_FLOW_ACTION_AGE)
3852                 return rte_flow_error_set(error, EINVAL,
3853                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3854                                           "Duplicate age ctions set");
3855         return 0;
3856 }
3857
3858 /**
3859  * Validate the modify-header IPv4 DSCP actions.
3860  *
3861  * @param[in] action_flags
3862  *   Holds the actions detected until now.
3863  * @param[in] action
3864  *   Pointer to the modify action.
3865  * @param[in] item_flags
3866  *   Holds the items detected.
3867  * @param[out] error
3868  *   Pointer to error structure.
3869  *
3870  * @return
3871  *   0 on success, a negative errno value otherwise and rte_errno is set.
3872  */
3873 static int
3874 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3875                                          const struct rte_flow_action *action,
3876                                          const uint64_t item_flags,
3877                                          struct rte_flow_error *error)
3878 {
3879         int ret = 0;
3880
3881         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3882         if (!ret) {
3883                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3884                         return rte_flow_error_set(error, EINVAL,
3885                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                   NULL,
3887                                                   "no ipv4 item in pattern");
3888         }
3889         return ret;
3890 }
3891
3892 /**
3893  * Validate the modify-header IPv6 DSCP actions.
3894  *
3895  * @param[in] action_flags
3896  *   Holds the actions detected until now.
3897  * @param[in] action
3898  *   Pointer to the modify action.
3899  * @param[in] item_flags
3900  *   Holds the items detected.
3901  * @param[out] error
3902  *   Pointer to error structure.
3903  *
3904  * @return
3905  *   0 on success, a negative errno value otherwise and rte_errno is set.
3906  */
3907 static int
3908 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3909                                          const struct rte_flow_action *action,
3910                                          const uint64_t item_flags,
3911                                          struct rte_flow_error *error)
3912 {
3913         int ret = 0;
3914
3915         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3916         if (!ret) {
3917                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3918                         return rte_flow_error_set(error, EINVAL,
3919                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3920                                                   NULL,
3921                                                   "no ipv6 item in pattern");
3922         }
3923         return ret;
3924 }
3925
3926 /**
3927  * Find existing modify-header resource or create and register a new one.
3928  *
3929  * @param dev[in, out]
3930  *   Pointer to rte_eth_dev structure.
3931  * @param[in, out] resource
3932  *   Pointer to modify-header resource.
3933  * @parm[in, out] dev_flow
3934  *   Pointer to the dev_flow.
3935  * @param[out] error
3936  *   pointer to error structure.
3937  *
3938  * @return
3939  *   0 on success otherwise -errno and errno is set.
3940  */
3941 static int
3942 flow_dv_modify_hdr_resource_register
3943                         (struct rte_eth_dev *dev,
3944                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3945                          struct mlx5_flow *dev_flow,
3946                          struct rte_flow_error *error)
3947 {
3948         struct mlx5_priv *priv = dev->data->dev_private;
3949         struct mlx5_dev_ctx_shared *sh = priv->sh;
3950         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3951         struct mlx5dv_dr_domain *ns;
3952         uint32_t actions_len;
3953
3954         resource->flags = dev_flow->dv.group ? 0 :
3955                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3956         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3957                                     resource->flags))
3958                 return rte_flow_error_set(error, EOVERFLOW,
3959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3960                                           "too many modify header items");
3961         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3962                 ns = sh->fdb_domain;
3963         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964                 ns = sh->tx_domain;
3965         else
3966                 ns = sh->rx_domain;
3967         /* Lookup a matching resource from cache. */
3968         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3969         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3970                 if (resource->ft_type == cache_resource->ft_type &&
3971                     resource->actions_num == cache_resource->actions_num &&
3972                     resource->flags == cache_resource->flags &&
3973                     !memcmp((const void *)resource->actions,
3974                             (const void *)cache_resource->actions,
3975                             actions_len)) {
3976                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3977                                 (void *)cache_resource,
3978                                 rte_atomic32_read(&cache_resource->refcnt));
3979                         rte_atomic32_inc(&cache_resource->refcnt);
3980                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3981                         return 0;
3982                 }
3983         }
3984         /* Register new modify-header resource. */
3985         cache_resource = rte_calloc(__func__, 1,
3986                                     sizeof(*cache_resource) + actions_len, 0);
3987         if (!cache_resource)
3988                 return rte_flow_error_set(error, ENOMEM,
3989                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3990                                           "cannot allocate resource memory");
3991         *cache_resource = *resource;
3992         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3993         cache_resource->verbs_action =
3994                 mlx5_glue->dv_create_flow_action_modify_header
3995                                         (sh->ctx, cache_resource->ft_type, ns,
3996                                          cache_resource->flags, actions_len,
3997                                          (uint64_t *)cache_resource->actions);
3998         if (!cache_resource->verbs_action) {
3999                 rte_free(cache_resource);
4000                 return rte_flow_error_set(error, ENOMEM,
4001                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4002                                           NULL, "cannot create action");
4003         }
4004         rte_atomic32_init(&cache_resource->refcnt);
4005         rte_atomic32_inc(&cache_resource->refcnt);
4006         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4007         dev_flow->handle->dvh.modify_hdr = cache_resource;
4008         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4009                 (void *)cache_resource,
4010                 rte_atomic32_read(&cache_resource->refcnt));
4011         return 0;
4012 }
4013
4014 /**
4015  * Get DV flow counter by index.
4016  *
4017  * @param[in] dev
4018  *   Pointer to the Ethernet device structure.
4019  * @param[in] idx
4020  *   mlx5 flow counter index in the container.
4021  * @param[out] ppool
4022  *   mlx5 flow counter pool in the container,
4023  *
4024  * @return
4025  *   Pointer to the counter, NULL otherwise.
4026  */
4027 static struct mlx5_flow_counter *
4028 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4029                            uint32_t idx,
4030                            struct mlx5_flow_counter_pool **ppool)
4031 {
4032         struct mlx5_priv *priv = dev->data->dev_private;
4033         struct mlx5_pools_container *cont;
4034         struct mlx5_flow_counter_pool *pool;
4035         uint32_t batch = 0, age = 0;
4036
4037         idx--;
4038         age = MLX_CNT_IS_AGE(idx);
4039         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4040         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4041                 idx -= MLX5_CNT_BATCH_OFFSET;
4042                 batch = 1;
4043         }
4044         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4045         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4046         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047         MLX5_ASSERT(pool);
4048         if (ppool)
4049                 *ppool = pool;
4050         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 }
4052
4053 /**
4054  * Get a pool by devx counter ID.
4055  *
4056  * @param[in] cont
4057  *   Pointer to the counter container.
4058  * @param[in] id
4059  *   The counter devx ID.
4060  *
4061  * @return
4062  *   The counter pool pointer if exists, NULL otherwise,
4063  */
4064 static struct mlx5_flow_counter_pool *
4065 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4066 {
4067         uint32_t i;
4068         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4069
4070         for (i = 0; i < n_valid; i++) {
4071                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4072                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4073                            MLX5_COUNTERS_PER_POOL;
4074
4075                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4076                         /*
4077                          * Move the pool to the head, as counter allocate
4078                          * always gets the first pool in the container.
4079                          */
4080                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4081                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4082                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4083                         }
4084                         return pool;
4085                 }
4086         }
4087         return NULL;
4088 }
4089
4090 /**
4091  * Allocate a new memory for the counter values wrapped by all the needed
4092  * management.
4093  *
4094  * @param[in] dev
4095  *   Pointer to the Ethernet device structure.
4096  * @param[in] raws_n
4097  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4098  *
4099  * @return
4100  *   The new memory management pointer on success, otherwise NULL and rte_errno
4101  *   is set.
4102  */
4103 static struct mlx5_counter_stats_mem_mng *
4104 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4105 {
4106         struct mlx5_priv *priv = dev->data->dev_private;
4107         struct mlx5_dev_ctx_shared *sh = priv->sh;
4108         struct mlx5_devx_mkey_attr mkey_attr;
4109         struct mlx5_counter_stats_mem_mng *mem_mng;
4110         volatile struct flow_counter_stats *raw_data;
4111         int size = (sizeof(struct flow_counter_stats) *
4112                         MLX5_COUNTERS_PER_POOL +
4113                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4114                         sizeof(struct mlx5_counter_stats_mem_mng);
4115         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4116         int i;
4117
4118         if (!mem) {
4119                 rte_errno = ENOMEM;
4120                 return NULL;
4121         }
4122         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4123         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4124         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4125                                                  IBV_ACCESS_LOCAL_WRITE);
4126         if (!mem_mng->umem) {
4127                 rte_errno = errno;
4128                 rte_free(mem);
4129                 return NULL;
4130         }
4131         mkey_attr.addr = (uintptr_t)mem;
4132         mkey_attr.size = size;
4133         mkey_attr.umem_id = mem_mng->umem->umem_id;
4134         mkey_attr.pd = sh->pdn;
4135         mkey_attr.log_entity_size = 0;
4136         mkey_attr.pg_access = 0;
4137         mkey_attr.klm_array = NULL;
4138         mkey_attr.klm_num = 0;
4139         if (priv->config.hca_attr.relaxed_ordering_write &&
4140                 priv->config.hca_attr.relaxed_ordering_read  &&
4141                 !haswell_broadwell_cpu)
4142                 mkey_attr.relaxed_ordering = 1;
4143         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4144         if (!mem_mng->dm) {
4145                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4146                 rte_errno = errno;
4147                 rte_free(mem);
4148                 return NULL;
4149         }
4150         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4151         raw_data = (volatile struct flow_counter_stats *)mem;
4152         for (i = 0; i < raws_n; ++i) {
4153                 mem_mng->raws[i].mem_mng = mem_mng;
4154                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4155         }
4156         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4157         return mem_mng;
4158 }
4159
4160 /**
4161  * Resize a counter container.
4162  *
4163  * @param[in] dev
4164  *   Pointer to the Ethernet device structure.
4165  * @param[in] batch
4166  *   Whether the pool is for counter that was allocated by batch command.
4167  * @param[in] age
4168  *   Whether the pool is for Aging counter.
4169  *
4170  * @return
4171  *   0 on success, otherwise negative errno value and rte_errno is set.
4172  */
4173 static int
4174 flow_dv_container_resize(struct rte_eth_dev *dev,
4175                                 uint32_t batch, uint32_t age)
4176 {
4177         struct mlx5_priv *priv = dev->data->dev_private;
4178         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4179                                                                age);
4180         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4181         void *old_pools = cont->pools;
4182         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4183         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4184         void *pools = rte_calloc(__func__, 1, mem_size, 0);
4185
4186         if (!pools) {
4187                 rte_errno = ENOMEM;
4188                 return -ENOMEM;
4189         }
4190         if (old_pools)
4191                 memcpy(pools, old_pools, cont->n *
4192                                        sizeof(struct mlx5_flow_counter_pool *));
4193         /*
4194          * Fallback mode query the counter directly, no background query
4195          * resources are needed.
4196          */
4197         if (!priv->counter_fallback) {
4198                 int i;
4199
4200                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4201                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4202                 if (!mem_mng) {
4203                         rte_free(pools);
4204                         return -ENOMEM;
4205                 }
4206                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4207                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4208                                          mem_mng->raws +
4209                                          MLX5_CNT_CONTAINER_RESIZE +
4210                                          i, next);
4211         }
4212         rte_spinlock_lock(&cont->resize_sl);
4213         cont->n = resize;
4214         cont->mem_mng = mem_mng;
4215         cont->pools = pools;
4216         rte_spinlock_unlock(&cont->resize_sl);
4217         if (old_pools)
4218                 rte_free(old_pools);
4219         return 0;
4220 }
4221
4222 /**
4223  * Query a devx flow counter.
4224  *
4225  * @param[in] dev
4226  *   Pointer to the Ethernet device structure.
4227  * @param[in] cnt
4228  *   Index to the flow counter.
4229  * @param[out] pkts
4230  *   The statistics value of packets.
4231  * @param[out] bytes
4232  *   The statistics value of bytes.
4233  *
4234  * @return
4235  *   0 on success, otherwise a negative errno value and rte_errno is set.
4236  */
4237 static inline int
4238 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4239                      uint64_t *bytes)
4240 {
4241         struct mlx5_priv *priv = dev->data->dev_private;
4242         struct mlx5_flow_counter_pool *pool = NULL;
4243         struct mlx5_flow_counter *cnt;
4244         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4245         int offset;
4246
4247         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4248         MLX5_ASSERT(pool);
4249         if (counter < MLX5_CNT_BATCH_OFFSET) {
4250                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4251                 if (priv->counter_fallback)
4252                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4253                                         0, pkts, bytes, 0, NULL, NULL, 0);
4254         }
4255
4256         rte_spinlock_lock(&pool->sl);
4257         /*
4258          * The single counters allocation may allocate smaller ID than the
4259          * current allocated in parallel to the host reading.
4260          * In this case the new counter values must be reported as 0.
4261          */
4262         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4263                 *pkts = 0;
4264                 *bytes = 0;
4265         } else {
4266                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4267                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4268                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4269         }
4270         rte_spinlock_unlock(&pool->sl);
4271         return 0;
4272 }
4273
4274 /**
4275  * Create and initialize a new counter pool.
4276  *
4277  * @param[in] dev
4278  *   Pointer to the Ethernet device structure.
4279  * @param[out] dcs
4280  *   The devX counter handle.
4281  * @param[in] batch
4282  *   Whether the pool is for counter that was allocated by batch command.
4283  * @param[in] age
4284  *   Whether the pool is for counter that was allocated for aging.
4285  * @param[in/out] cont_cur
4286  *   Pointer to the container pointer, it will be update in pool resize.
4287  *
4288  * @return
4289  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4290  */
4291 static struct mlx5_flow_counter_pool *
4292 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4293                     uint32_t batch, uint32_t age)
4294 {
4295         struct mlx5_priv *priv = dev->data->dev_private;
4296         struct mlx5_flow_counter_pool *pool;
4297         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4298                                                                age);
4299         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4300         uint32_t size = sizeof(*pool);
4301
4302         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4303                 return NULL;
4304         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4305         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4306         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4307         pool = rte_calloc(__func__, 1, size, 0);
4308         if (!pool) {
4309                 rte_errno = ENOMEM;
4310                 return NULL;
4311         }
4312         pool->min_dcs = dcs;
4313         if (!priv->counter_fallback)
4314                 pool->raw = cont->mem_mng->raws + n_valid %
4315                                                       MLX5_CNT_CONTAINER_RESIZE;
4316         pool->raw_hw = NULL;
4317         pool->type = 0;
4318         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4319         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4320         rte_spinlock_init(&pool->sl);
4321         /*
4322          * The generation of the new allocated counters in this pool is 0, 2 in
4323          * the pool generation makes all the counters valid for allocation.
4324          * The start and end query generation protect the counters be released
4325          * between the query and update gap period will not be reallocated
4326          * without the last query finished and stats updated to the memory.
4327          */
4328         rte_atomic64_set(&pool->start_query_gen, 0x2);
4329         /*
4330          * There's no background query thread for fallback mode, set the
4331          * end_query_gen to the maximum value since no need to wait for
4332          * statistics update.
4333          */
4334         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4335                          INT64_MAX : 0x2);
4336         TAILQ_INIT(&pool->counters);
4337         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4338         pool->index = n_valid;
4339         cont->pools[n_valid] = pool;
4340         /* Pool initialization must be updated before host thread access. */
4341         rte_cio_wmb();
4342         rte_atomic16_add(&cont->n_valid, 1);
4343         return pool;
4344 }
4345
4346 /**
4347  * Update the minimum dcs-id for aged or no-aged counter pool.
4348  *
4349  * @param[in] dev
4350  *   Pointer to the Ethernet device structure.
4351  * @param[in] pool
4352  *   Current counter pool.
4353  * @param[in] batch
4354  *   Whether the pool is for counter that was allocated by batch command.
4355  * @param[in] age
4356  *   Whether the counter is for aging.
4357  */
4358 static void
4359 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4360                         struct mlx5_flow_counter_pool *pool,
4361                         uint32_t batch, uint32_t age)
4362 {
4363         struct mlx5_priv *priv = dev->data->dev_private;
4364         struct mlx5_flow_counter_pool *other;
4365         struct mlx5_pools_container *cont;
4366
4367         cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4368         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4369         if (!other)
4370                 return;
4371         if (pool->min_dcs->id < other->min_dcs->id) {
4372                 rte_atomic64_set(&other->a64_dcs,
4373                         rte_atomic64_read(&pool->a64_dcs));
4374         } else {
4375                 rte_atomic64_set(&pool->a64_dcs,
4376                         rte_atomic64_read(&other->a64_dcs));
4377         }
4378 }
4379 /**
4380  * Prepare a new counter and/or a new counter pool.
4381  *
4382  * @param[in] dev
4383  *   Pointer to the Ethernet device structure.
4384  * @param[out] cnt_free
4385  *   Where to put the pointer of a new counter.
4386  * @param[in] batch
4387  *   Whether the pool is for counter that was allocated by batch command.
4388  * @param[in] age
4389  *   Whether the pool is for counter that was allocated for aging.
4390  *
4391  * @return
4392  *   The counter pool pointer and @p cnt_free is set on success,
4393  *   NULL otherwise and rte_errno is set.
4394  */
4395 static struct mlx5_flow_counter_pool *
4396 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4397                              struct mlx5_flow_counter **cnt_free,
4398                              uint32_t batch, uint32_t age)
4399 {
4400         struct mlx5_priv *priv = dev->data->dev_private;
4401         struct mlx5_pools_container *cont;
4402         struct mlx5_flow_counter_pool *pool;
4403         struct mlx5_devx_obj *dcs = NULL;
4404         struct mlx5_flow_counter *cnt;
4405         uint32_t i;
4406
4407         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4408         if (!batch) {
4409                 /* bulk_bitmap must be 0 for single counter allocation. */
4410                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4411                 if (!dcs)
4412                         return NULL;
4413                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4414                 if (!pool) {
4415                         pool = flow_dv_pool_create(dev, dcs, batch, age);
4416                         if (!pool) {
4417                                 mlx5_devx_cmd_destroy(dcs);
4418                                 return NULL;
4419                         }
4420                 } else if (dcs->id < pool->min_dcs->id) {
4421                         rte_atomic64_set(&pool->a64_dcs,
4422                                          (int64_t)(uintptr_t)dcs);
4423                 }
4424                 flow_dv_counter_update_min_dcs(dev,
4425                                                 pool, batch, age);
4426                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4427                 cnt = MLX5_POOL_GET_CNT(pool, i);
4428                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4429                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4430                 *cnt_free = cnt;
4431                 return pool;
4432         }
4433         /* bulk_bitmap is in 128 counters units. */
4434         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4435                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4436         if (!dcs) {
4437                 rte_errno = ENODATA;
4438                 return NULL;
4439         }
4440         pool = flow_dv_pool_create(dev, dcs, batch, age);
4441         if (!pool) {
4442                 mlx5_devx_cmd_destroy(dcs);
4443                 return NULL;
4444         }
4445         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4446                 cnt = MLX5_POOL_GET_CNT(pool, i);
4447                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4448         }
4449         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4450         return pool;
4451 }
4452
4453 /**
4454  * Search for existed shared counter.
4455  *
4456  * @param[in] cont
4457  *   Pointer to the relevant counter pool container.
4458  * @param[in] id
4459  *   The shared counter ID to search.
4460  * @param[out] ppool
4461  *   mlx5 flow counter pool in the container,
4462  *
4463  * @return
4464  *   NULL if not existed, otherwise pointer to the shared extend counter.
4465  */
4466 static struct mlx5_flow_counter_ext *
4467 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4468                               struct mlx5_flow_counter_pool **ppool)
4469 {
4470         struct mlx5_flow_counter_ext *cnt;
4471         struct mlx5_flow_counter_pool *pool;
4472         uint32_t i, j;
4473         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4474
4475         for (i = 0; i < n_valid; i++) {
4476                 pool = cont->pools[i];
4477                 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
4478                         cnt = MLX5_GET_POOL_CNT_EXT(pool, j);
4479                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4480                                 if (ppool)
4481                                         *ppool = cont->pools[i];
4482                                 return cnt;
4483                         }
4484                 }
4485         }
4486         return NULL;
4487 }
4488
4489 /**
4490  * Allocate a flow counter.
4491  *
4492  * @param[in] dev
4493  *   Pointer to the Ethernet device structure.
4494  * @param[in] shared
4495  *   Indicate if this counter is shared with other flows.
4496  * @param[in] id
4497  *   Counter identifier.
4498  * @param[in] group
4499  *   Counter flow group.
4500  * @param[in] age
4501  *   Whether the counter was allocated for aging.
4502  *
4503  * @return
4504  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4505  */
4506 static uint32_t
4507 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4508                       uint16_t group, uint32_t age)
4509 {
4510         struct mlx5_priv *priv = dev->data->dev_private;
4511         struct mlx5_flow_counter_pool *pool = NULL;
4512         struct mlx5_flow_counter *cnt_free = NULL;
4513         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4514         /*
4515          * Currently group 0 flow counter cannot be assigned to a flow if it is
4516          * not the first one in the batch counter allocation, so it is better
4517          * to allocate counters one by one for these flows in a separate
4518          * container.
4519          * A counter can be shared between different groups so need to take
4520          * shared counters from the single container.
4521          */
4522         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4523         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4524                                                                age);
4525         uint32_t cnt_idx;
4526
4527         if (!priv->config.devx) {
4528                 rte_errno = ENOTSUP;
4529                 return 0;
4530         }
4531         if (shared) {
4532                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4533                 if (cnt_ext) {
4534                         if (cnt_ext->ref_cnt + 1 == 0) {
4535                                 rte_errno = E2BIG;
4536                                 return 0;
4537                         }
4538                         cnt_ext->ref_cnt++;
4539                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4540                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4541                                   + 1;
4542                         return cnt_idx;
4543                 }
4544         }
4545         /* Pools which has a free counters are in the start. */
4546         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4547                 /*
4548                  * The free counter reset values must be updated between the
4549                  * counter release to the counter allocation, so, at least one
4550                  * query must be done in this time. ensure it by saving the
4551                  * query generation in the release time.
4552                  * The free list is sorted according to the generation - so if
4553                  * the first one is not updated, all the others are not
4554                  * updated too.
4555                  */
4556                 cnt_free = TAILQ_FIRST(&pool->counters);
4557                 if (cnt_free && cnt_free->query_gen <
4558                     rte_atomic64_read(&pool->end_query_gen))
4559                         break;
4560                 cnt_free = NULL;
4561         }
4562         if (!cnt_free) {
4563                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4564                 if (!pool)
4565                         return 0;
4566         }
4567         if (!batch)
4568                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4569         /* Create a DV counter action only in the first time usage. */
4570         if (!cnt_free->action) {
4571                 uint16_t offset;
4572                 struct mlx5_devx_obj *dcs;
4573
4574                 if (batch) {
4575                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4576                         dcs = pool->min_dcs;
4577                 } else {
4578                         offset = 0;
4579                         dcs = cnt_ext->dcs;
4580                 }
4581                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4582                                         (dcs->obj, offset);
4583                 if (!cnt_free->action) {
4584                         rte_errno = errno;
4585                         return 0;
4586                 }
4587         }
4588         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4589                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4590         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4591         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4592         /* Update the counter reset values. */
4593         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4594                                  &cnt_free->bytes))
4595                 return 0;
4596         if (cnt_ext) {
4597                 cnt_ext->shared = shared;
4598                 cnt_ext->ref_cnt = 1;
4599                 cnt_ext->id = id;
4600         }
4601         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4602                 /* Start the asynchronous batch query by the host thread. */
4603                 mlx5_set_query_alarm(priv->sh);
4604         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4605         if (TAILQ_EMPTY(&pool->counters)) {
4606                 /* Move the pool to the end of the container pool list. */
4607                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4608                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4609         }
4610         return cnt_idx;
4611 }
4612
4613 /**
4614  * Get age param from counter index.
4615  *
4616  * @param[in] dev
4617  *   Pointer to the Ethernet device structure.
4618  * @param[in] counter
4619  *   Index to the counter handler.
4620  *
4621  * @return
4622  *   The aging parameter specified for the counter index.
4623  */
4624 static struct mlx5_age_param*
4625 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4626                                 uint32_t counter)
4627 {
4628         struct mlx5_flow_counter *cnt;
4629         struct mlx5_flow_counter_pool *pool = NULL;
4630
4631         flow_dv_counter_get_by_idx(dev, counter, &pool);
4632         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4633         cnt = MLX5_POOL_GET_CNT(pool, counter);
4634         return MLX5_CNT_TO_AGE(cnt);
4635 }
4636
4637 /**
4638  * Remove a flow counter from aged counter list.
4639  *
4640  * @param[in] dev
4641  *   Pointer to the Ethernet device structure.
4642  * @param[in] counter
4643  *   Index to the counter handler.
4644  * @param[in] cnt
4645  *   Pointer to the counter handler.
4646  */
4647 static void
4648 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4649                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4650 {
4651         struct mlx5_age_info *age_info;
4652         struct mlx5_age_param *age_param;
4653         struct mlx5_priv *priv = dev->data->dev_private;
4654
4655         age_info = GET_PORT_AGE_INFO(priv);
4656         age_param = flow_dv_counter_idx_get_age(dev, counter);
4657         if (rte_atomic16_cmpset((volatile uint16_t *)
4658                         &age_param->state,
4659                         AGE_CANDIDATE, AGE_FREE)
4660                         != AGE_CANDIDATE) {
4661                 /**
4662                  * We need the lock even it is age timeout,
4663                  * since counter may still in process.
4664                  */
4665                 rte_spinlock_lock(&age_info->aged_sl);
4666                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4667                 rte_spinlock_unlock(&age_info->aged_sl);
4668         }
4669         rte_atomic16_set(&age_param->state, AGE_FREE);
4670 }
4671 /**
4672  * Release a flow counter.
4673  *
4674  * @param[in] dev
4675  *   Pointer to the Ethernet device structure.
4676  * @param[in] counter
4677  *   Index to the counter handler.
4678  */
4679 static void
4680 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4681 {
4682         struct mlx5_flow_counter_pool *pool = NULL;
4683         struct mlx5_flow_counter *cnt;
4684         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4685
4686         if (!counter)
4687                 return;
4688         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4689         MLX5_ASSERT(pool);
4690         if (counter < MLX5_CNT_BATCH_OFFSET) {
4691                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4692                 if (cnt_ext && --cnt_ext->ref_cnt)
4693                         return;
4694         }
4695         if (IS_AGE_POOL(pool))
4696                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4697         /* Put the counter in the end - the last updated one. */
4698         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4699         /*
4700          * Counters released between query trigger and handler need
4701          * to wait the next round of query. Since the packets arrive
4702          * in the gap period will not be taken into account to the
4703          * old counter.
4704          */
4705         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4706 }
4707
4708 /**
4709  * Verify the @p attributes will be correctly understood by the NIC and store
4710  * them in the @p flow if everything is correct.
4711  *
4712  * @param[in] dev
4713  *   Pointer to dev struct.
4714  * @param[in] attributes
4715  *   Pointer to flow attributes
4716  * @param[in] external
4717  *   This flow rule is created by request external to PMD.
4718  * @param[out] error
4719  *   Pointer to error structure.
4720  *
4721  * @return
4722  *   - 0 on success and non root table.
4723  *   - 1 on success and root table.
4724  *   - a negative errno value otherwise and rte_errno is set.
4725  */
4726 static int
4727 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4728                             const struct rte_flow_attr *attributes,
4729                             bool external __rte_unused,
4730                             struct rte_flow_error *error)
4731 {
4732         struct mlx5_priv *priv = dev->data->dev_private;
4733         uint32_t priority_max = priv->config.flow_prio - 1;
4734         int ret = 0;
4735
4736 #ifndef HAVE_MLX5DV_DR
4737         if (attributes->group)
4738                 return rte_flow_error_set(error, ENOTSUP,
4739                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4740                                           NULL,
4741                                           "groups are not supported");
4742 #else
4743         uint32_t table = 0;
4744
4745         ret = mlx5_flow_group_to_table(attributes, external,
4746                                        attributes->group, !!priv->fdb_def_rule,
4747                                        &table, error);
4748         if (ret)
4749                 return ret;
4750         if (!table)
4751                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4752 #endif
4753         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4754             attributes->priority >= priority_max)
4755                 return rte_flow_error_set(error, ENOTSUP,
4756                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4757                                           NULL,
4758                                           "priority out of range");
4759         if (attributes->transfer) {
4760                 if (!priv->config.dv_esw_en)
4761                         return rte_flow_error_set
4762                                 (error, ENOTSUP,
4763                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4764                                  "E-Switch dr is not supported");
4765                 if (!(priv->representor || priv->master))
4766                         return rte_flow_error_set
4767                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4768                                  NULL, "E-Switch configuration can only be"
4769                                  " done by a master or a representor device");
4770                 if (attributes->egress)
4771                         return rte_flow_error_set
4772                                 (error, ENOTSUP,
4773                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4774                                  "egress is not supported");
4775         }
4776         if (!(attributes->egress ^ attributes->ingress))
4777                 return rte_flow_error_set(error, ENOTSUP,
4778                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4779                                           "must specify exactly one of "
4780                                           "ingress or egress");
4781         return ret;
4782 }
4783
4784 /**
4785  * Internal validation function. For validating both actions and items.
4786  *
4787  * @param[in] dev
4788  *   Pointer to the rte_eth_dev structure.
4789  * @param[in] attr
4790  *   Pointer to the flow attributes.
4791  * @param[in] items
4792  *   Pointer to the list of items.
4793  * @param[in] actions
4794  *   Pointer to the list of actions.
4795  * @param[in] external
4796  *   This flow rule is created by request external to PMD.
4797  * @param[in] hairpin
4798  *   Number of hairpin TX actions, 0 means classic flow.
4799  * @param[out] error
4800  *   Pointer to the error structure.
4801  *
4802  * @return
4803  *   0 on success, a negative errno value otherwise and rte_errno is set.
4804  */
4805 static int
4806 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4807                  const struct rte_flow_item items[],
4808                  const struct rte_flow_action actions[],
4809                  bool external, int hairpin, struct rte_flow_error *error)
4810 {
4811         int ret;
4812         uint64_t action_flags = 0;
4813         uint64_t item_flags = 0;
4814         uint64_t last_item = 0;
4815         uint8_t next_protocol = 0xff;
4816         uint16_t ether_type = 0;
4817         int actions_n = 0;
4818         uint8_t item_ipv6_proto = 0;
4819         const struct rte_flow_item *gre_item = NULL;
4820         const struct rte_flow_action_raw_decap *decap;
4821         const struct rte_flow_action_raw_encap *encap;
4822         const struct rte_flow_action_rss *rss;
4823         const struct rte_flow_item_tcp nic_tcp_mask = {
4824                 .hdr = {
4825                         .tcp_flags = 0xFF,
4826                         .src_port = RTE_BE16(UINT16_MAX),
4827                         .dst_port = RTE_BE16(UINT16_MAX),
4828                 }
4829         };
4830         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4831                 .hdr = {
4832                         .src_addr = RTE_BE32(0xffffffff),
4833                         .dst_addr = RTE_BE32(0xffffffff),
4834                         .type_of_service = 0xff,
4835                         .next_proto_id = 0xff,
4836                         .time_to_live = 0xff,
4837                 },
4838         };
4839         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4840                 .hdr = {
4841                         .src_addr =
4842                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4843                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4844                         .dst_addr =
4845                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4846                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4847                         .vtc_flow = RTE_BE32(0xffffffff),
4848                         .proto = 0xff,
4849                         .hop_limits = 0xff,
4850                 },
4851         };
4852         struct mlx5_priv *priv = dev->data->dev_private;
4853         struct mlx5_dev_config *dev_conf = &priv->config;
4854         uint16_t queue_index = 0xFFFF;
4855         const struct rte_flow_item_vlan *vlan_m = NULL;
4856         int16_t rw_act_num = 0;
4857         uint64_t is_root;
4858
4859         if (items == NULL)
4860                 return -1;
4861         ret = flow_dv_validate_attributes(dev, attr, external, error);
4862         if (ret < 0)
4863                 return ret;
4864         is_root = (uint64_t)ret;
4865         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4866                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4867                 int type = items->type;
4868
4869                 switch (type) {
4870                 case RTE_FLOW_ITEM_TYPE_VOID:
4871                         break;
4872                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4873                         ret = flow_dv_validate_item_port_id
4874                                         (dev, items, attr, item_flags, error);
4875                         if (ret < 0)
4876                                 return ret;
4877                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4878                         break;
4879                 case RTE_FLOW_ITEM_TYPE_ETH:
4880                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4881                                                           error);
4882                         if (ret < 0)
4883                                 return ret;
4884                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4885                                              MLX5_FLOW_LAYER_OUTER_L2;
4886                         if (items->mask != NULL && items->spec != NULL) {
4887                                 ether_type =
4888                                         ((const struct rte_flow_item_eth *)
4889                                          items->spec)->type;
4890                                 ether_type &=
4891                                         ((const struct rte_flow_item_eth *)
4892                                          items->mask)->type;
4893                                 ether_type = rte_be_to_cpu_16(ether_type);
4894                         } else {
4895                                 ether_type = 0;
4896                         }
4897                         break;
4898                 case RTE_FLOW_ITEM_TYPE_VLAN:
4899                         ret = flow_dv_validate_item_vlan(items, item_flags,
4900                                                          dev, error);
4901                         if (ret < 0)
4902                                 return ret;
4903                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4904                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4905                         if (items->mask != NULL && items->spec != NULL) {
4906                                 ether_type =
4907                                         ((const struct rte_flow_item_vlan *)
4908                                          items->spec)->inner_type;
4909                                 ether_type &=
4910                                         ((const struct rte_flow_item_vlan *)
4911                                          items->mask)->inner_type;
4912                                 ether_type = rte_be_to_cpu_16(ether_type);
4913                         } else {
4914                                 ether_type = 0;
4915                         }
4916                         /* Store outer VLAN mask for of_push_vlan action. */
4917                         if (!tunnel)
4918                                 vlan_m = items->mask;
4919                         break;
4920                 case RTE_FLOW_ITEM_TYPE_IPV4:
4921                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4922                                                   &item_flags, &tunnel);
4923                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4924                                                            last_item,
4925                                                            ether_type,
4926                                                            &nic_ipv4_mask,
4927                                                            error);
4928                         if (ret < 0)
4929                                 return ret;
4930                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4931                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4932                         if (items->mask != NULL &&
4933                             ((const struct rte_flow_item_ipv4 *)
4934                              items->mask)->hdr.next_proto_id) {
4935                                 next_protocol =
4936                                         ((const struct rte_flow_item_ipv4 *)
4937                                          (items->spec))->hdr.next_proto_id;
4938                                 next_protocol &=
4939                                         ((const struct rte_flow_item_ipv4 *)
4940                                          (items->mask))->hdr.next_proto_id;
4941                         } else {
4942                                 /* Reset for inner layer. */
4943                                 next_protocol = 0xff;
4944                         }
4945                         break;
4946                 case RTE_FLOW_ITEM_TYPE_IPV6:
4947                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4948                                                   &item_flags, &tunnel);
4949                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4950                                                            last_item,
4951                                                            ether_type,
4952                                                            &nic_ipv6_mask,
4953                                                            error);
4954                         if (ret < 0)
4955                                 return ret;
4956                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4957                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4958                         if (items->mask != NULL &&
4959                             ((const struct rte_flow_item_ipv6 *)
4960                              items->mask)->hdr.proto) {
4961                                 item_ipv6_proto =
4962                                         ((const struct rte_flow_item_ipv6 *)
4963                                          items->spec)->hdr.proto;
4964                                 next_protocol =
4965                                         ((const struct rte_flow_item_ipv6 *)
4966                                          items->spec)->hdr.proto;
4967                                 next_protocol &=
4968                                         ((const struct rte_flow_item_ipv6 *)
4969                                          items->mask)->hdr.proto;
4970                         } else {
4971                                 /* Reset for inner layer. */
4972                                 next_protocol = 0xff;
4973                         }
4974                         break;
4975                 case RTE_FLOW_ITEM_TYPE_TCP:
4976                         ret = mlx5_flow_validate_item_tcp
4977                                                 (items, item_flags,
4978                                                  next_protocol,
4979                                                  &nic_tcp_mask,
4980                                                  error);
4981                         if (ret < 0)
4982                                 return ret;
4983                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4984                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4985                         break;
4986                 case RTE_FLOW_ITEM_TYPE_UDP:
4987                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4988                                                           next_protocol,
4989                                                           error);
4990                         if (ret < 0)
4991                                 return ret;
4992                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4993                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4994                         break;
4995                 case RTE_FLOW_ITEM_TYPE_GRE:
4996                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4997                                                           next_protocol, error);
4998                         if (ret < 0)
4999                                 return ret;
5000                         gre_item = items;
5001                         last_item = MLX5_FLOW_LAYER_GRE;
5002                         break;
5003                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5004                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5005                                                             next_protocol,
5006                                                             error);
5007                         if (ret < 0)
5008                                 return ret;
5009                         last_item = MLX5_FLOW_LAYER_NVGRE;
5010                         break;
5011                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5012                         ret = mlx5_flow_validate_item_gre_key
5013                                 (items, item_flags, gre_item, error);
5014                         if (ret < 0)
5015                                 return ret;
5016                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5017                         break;
5018                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5019                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5020                                                             error);
5021                         if (ret < 0)
5022                                 return ret;
5023                         last_item = MLX5_FLOW_LAYER_VXLAN;
5024                         break;
5025                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5026                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5027                                                                 item_flags, dev,
5028                                                                 error);
5029                         if (ret < 0)
5030                                 return ret;
5031                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5032                         break;
5033                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5034                         ret = mlx5_flow_validate_item_geneve(items,
5035                                                              item_flags, dev,
5036                                                              error);
5037                         if (ret < 0)
5038                                 return ret;
5039                         last_item = MLX5_FLOW_LAYER_GENEVE;
5040                         break;
5041                 case RTE_FLOW_ITEM_TYPE_MPLS:
5042                         ret = mlx5_flow_validate_item_mpls(dev, items,
5043                                                            item_flags,
5044                                                            last_item, error);
5045                         if (ret < 0)
5046                                 return ret;
5047                         last_item = MLX5_FLOW_LAYER_MPLS;
5048                         break;
5049
5050                 case RTE_FLOW_ITEM_TYPE_MARK:
5051                         ret = flow_dv_validate_item_mark(dev, items, attr,
5052                                                          error);
5053                         if (ret < 0)
5054                                 return ret;
5055                         last_item = MLX5_FLOW_ITEM_MARK;
5056                         break;
5057                 case RTE_FLOW_ITEM_TYPE_META:
5058                         ret = flow_dv_validate_item_meta(dev, items, attr,
5059                                                          error);
5060                         if (ret < 0)
5061                                 return ret;
5062                         last_item = MLX5_FLOW_ITEM_METADATA;
5063                         break;
5064                 case RTE_FLOW_ITEM_TYPE_ICMP:
5065                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5066                                                            next_protocol,
5067                                                            error);
5068                         if (ret < 0)
5069                                 return ret;
5070                         last_item = MLX5_FLOW_LAYER_ICMP;
5071                         break;
5072                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5073                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5074                                                             next_protocol,
5075                                                             error);
5076                         if (ret < 0)
5077                                 return ret;
5078                         item_ipv6_proto = IPPROTO_ICMPV6;
5079                         last_item = MLX5_FLOW_LAYER_ICMP6;
5080                         break;
5081                 case RTE_FLOW_ITEM_TYPE_TAG:
5082                         ret = flow_dv_validate_item_tag(dev, items,
5083                                                         attr, error);
5084                         if (ret < 0)
5085                                 return ret;
5086                         last_item = MLX5_FLOW_ITEM_TAG;
5087                         break;
5088                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5089                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5090                         break;
5091                 case RTE_FLOW_ITEM_TYPE_GTP:
5092                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5093                                                         error);
5094                         if (ret < 0)
5095                                 return ret;
5096                         last_item = MLX5_FLOW_LAYER_GTP;
5097                         break;
5098                 default:
5099                         return rte_flow_error_set(error, ENOTSUP,
5100                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5101                                                   NULL, "item not supported");
5102                 }
5103                 item_flags |= last_item;
5104         }
5105         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5106                 int type = actions->type;
5107                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5108                         return rte_flow_error_set(error, ENOTSUP,
5109                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5110                                                   actions, "too many actions");
5111                 switch (type) {
5112                 case RTE_FLOW_ACTION_TYPE_VOID:
5113                         break;
5114                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5115                         ret = flow_dv_validate_action_port_id(dev,
5116                                                               action_flags,
5117                                                               actions,
5118                                                               attr,
5119                                                               error);
5120                         if (ret)
5121                                 return ret;
5122                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5123                         ++actions_n;
5124                         break;
5125                 case RTE_FLOW_ACTION_TYPE_FLAG:
5126                         ret = flow_dv_validate_action_flag(dev, action_flags,
5127                                                            attr, error);
5128                         if (ret < 0)
5129                                 return ret;
5130                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5131                                 /* Count all modify-header actions as one. */
5132                                 if (!(action_flags &
5133                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5134                                         ++actions_n;
5135                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5136                                                 MLX5_FLOW_ACTION_MARK_EXT;
5137                         } else {
5138                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5139                                 ++actions_n;
5140                         }
5141                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5142                         break;
5143                 case RTE_FLOW_ACTION_TYPE_MARK:
5144                         ret = flow_dv_validate_action_mark(dev, actions,
5145                                                            action_flags,
5146                                                            attr, error);
5147                         if (ret < 0)
5148                                 return ret;
5149                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5150                                 /* Count all modify-header actions as one. */
5151                                 if (!(action_flags &
5152                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5153                                         ++actions_n;
5154                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5155                                                 MLX5_FLOW_ACTION_MARK_EXT;
5156                         } else {
5157                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5158                                 ++actions_n;
5159                         }
5160                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5161                         break;
5162                 case RTE_FLOW_ACTION_TYPE_SET_META:
5163                         ret = flow_dv_validate_action_set_meta(dev, actions,
5164                                                                action_flags,
5165                                                                attr, error);
5166                         if (ret < 0)
5167                                 return ret;
5168                         /* Count all modify-header actions as one action. */
5169                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5170                                 ++actions_n;
5171                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5172                         rw_act_num += MLX5_ACT_NUM_SET_META;
5173                         break;
5174                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5175                         ret = flow_dv_validate_action_set_tag(dev, actions,
5176                                                               action_flags,
5177                                                               attr, error);
5178                         if (ret < 0)
5179                                 return ret;
5180                         /* Count all modify-header actions as one action. */
5181                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5182                                 ++actions_n;
5183                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5184                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5185                         break;
5186                 case RTE_FLOW_ACTION_TYPE_DROP:
5187                         ret = mlx5_flow_validate_action_drop(action_flags,
5188                                                              attr, error);
5189                         if (ret < 0)
5190                                 return ret;
5191                         action_flags |= MLX5_FLOW_ACTION_DROP;
5192                         ++actions_n;
5193                         break;
5194                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5195                         ret = mlx5_flow_validate_action_queue(actions,
5196                                                               action_flags, dev,
5197                                                               attr, error);
5198                         if (ret < 0)
5199                                 return ret;
5200                         queue_index = ((const struct rte_flow_action_queue *)
5201                                                         (actions->conf))->index;
5202                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5203                         ++actions_n;
5204                         break;
5205                 case RTE_FLOW_ACTION_TYPE_RSS:
5206                         rss = actions->conf;
5207                         ret = mlx5_flow_validate_action_rss(actions,
5208                                                             action_flags, dev,
5209                                                             attr, item_flags,
5210                                                             error);
5211                         if (ret < 0)
5212                                 return ret;
5213                         if (rss != NULL && rss->queue_num)
5214                                 queue_index = rss->queue[0];
5215                         action_flags |= MLX5_FLOW_ACTION_RSS;
5216                         ++actions_n;
5217                         break;
5218                 case RTE_FLOW_ACTION_TYPE_COUNT:
5219                         ret = flow_dv_validate_action_count(dev, error);
5220                         if (ret < 0)
5221                                 return ret;
5222                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5223                         ++actions_n;
5224                         break;
5225                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5226                         if (flow_dv_validate_action_pop_vlan(dev,
5227                                                              action_flags,
5228                                                              actions,
5229                                                              item_flags, attr,
5230                                                              error))
5231                                 return -rte_errno;
5232                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5233                         ++actions_n;
5234                         break;
5235                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5236                         ret = flow_dv_validate_action_push_vlan(dev,
5237                                                                 action_flags,
5238                                                                 vlan_m,
5239                                                                 actions, attr,
5240                                                                 error);
5241                         if (ret < 0)
5242                                 return ret;
5243                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5244                         ++actions_n;
5245                         break;
5246                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5247                         ret = flow_dv_validate_action_set_vlan_pcp
5248                                                 (action_flags, actions, error);
5249                         if (ret < 0)
5250                                 return ret;
5251                         /* Count PCP with push_vlan command. */
5252                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5253                         break;
5254                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5255                         ret = flow_dv_validate_action_set_vlan_vid
5256                                                 (item_flags, action_flags,
5257                                                  actions, error);
5258                         if (ret < 0)
5259                                 return ret;
5260                         /* Count VID with push_vlan command. */
5261                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5262                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5263                         break;
5264                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5265                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5266                         ret = flow_dv_validate_action_l2_encap(dev,
5267                                                                action_flags,
5268                                                                actions, attr,
5269                                                                error);
5270                         if (ret < 0)
5271                                 return ret;
5272                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5273                         ++actions_n;
5274                         break;
5275                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5276                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5277                         ret = flow_dv_validate_action_decap(dev, action_flags,
5278                                                             attr, error);
5279                         if (ret < 0)
5280                                 return ret;
5281                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5282                         ++actions_n;
5283                         break;
5284                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5285                         ret = flow_dv_validate_action_raw_encap_decap
5286                                 (dev, NULL, actions->conf, attr, &action_flags,
5287                                  &actions_n, error);
5288                         if (ret < 0)
5289                                 return ret;
5290                         break;
5291                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5292                         decap = actions->conf;
5293                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5294                                 ;
5295                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5296                                 encap = NULL;
5297                                 actions--;
5298                         } else {
5299                                 encap = actions->conf;
5300                         }
5301                         ret = flow_dv_validate_action_raw_encap_decap
5302                                            (dev,
5303                                             decap ? decap : &empty_decap, encap,
5304                                             attr, &action_flags, &actions_n,
5305                                             error);
5306                         if (ret < 0)
5307                                 return ret;
5308                         break;
5309                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5310                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5311                         ret = flow_dv_validate_action_modify_mac(action_flags,
5312                                                                  actions,
5313                                                                  item_flags,
5314                                                                  error);
5315                         if (ret < 0)
5316                                 return ret;
5317                         /* Count all modify-header actions as one action. */
5318                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5319                                 ++actions_n;
5320                         action_flags |= actions->type ==
5321                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5322                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5323                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5324                         /*
5325                          * Even if the source and destination MAC addresses have
5326                          * overlap in the header with 4B alignment, the convert
5327                          * function will handle them separately and 4 SW actions
5328                          * will be created. And 2 actions will be added each
5329                          * time no matter how many bytes of address will be set.
5330                          */
5331                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5332                         break;
5333                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5334                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5335                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5336                                                                   actions,
5337                                                                   item_flags,
5338                                                                   error);
5339                         if (ret < 0)
5340                                 return ret;
5341                         /* Count all modify-header actions as one action. */
5342                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5343                                 ++actions_n;
5344                         action_flags |= actions->type ==
5345                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5346                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5347                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5348                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5349                         break;
5350                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5351                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5352                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5353                                                                   actions,
5354                                                                   item_flags,
5355                                                                   error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5359                                 return rte_flow_error_set(error, ENOTSUP,
5360                                         RTE_FLOW_ERROR_TYPE_ACTION,
5361                                         actions,
5362                                         "Can't change header "
5363                                         "with ICMPv6 proto");
5364                         /* Count all modify-header actions as one action. */
5365                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5366                                 ++actions_n;
5367                         action_flags |= actions->type ==
5368                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5369                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5370                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5371                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5372                         break;
5373                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5374                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5375                         ret = flow_dv_validate_action_modify_tp(action_flags,
5376                                                                 actions,
5377                                                                 item_flags,
5378                                                                 error);
5379                         if (ret < 0)
5380                                 return ret;
5381                         /* Count all modify-header actions as one action. */
5382                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5383                                 ++actions_n;
5384                         action_flags |= actions->type ==
5385                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5386                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5387                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5388                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5389                         break;
5390                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5391                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5392                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5393                                                                  actions,
5394                                                                  item_flags,
5395                                                                  error);
5396                         if (ret < 0)
5397                                 return ret;
5398                         /* Count all modify-header actions as one action. */
5399                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5400                                 ++actions_n;
5401                         action_flags |= actions->type ==
5402                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5403                                                 MLX5_FLOW_ACTION_SET_TTL :
5404                                                 MLX5_FLOW_ACTION_DEC_TTL;
5405                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5406                         break;
5407                 case RTE_FLOW_ACTION_TYPE_JUMP:
5408                         ret = flow_dv_validate_action_jump(actions,
5409                                                            action_flags,
5410                                                            attr, external,
5411                                                            error);
5412                         if (ret)
5413                                 return ret;
5414                         ++actions_n;
5415                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5416                         break;
5417                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5418                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5419                         ret = flow_dv_validate_action_modify_tcp_seq
5420                                                                 (action_flags,
5421                                                                  actions,
5422                                                                  item_flags,
5423                                                                  error);
5424                         if (ret < 0)
5425                                 return ret;
5426                         /* Count all modify-header actions as one action. */
5427                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5428                                 ++actions_n;
5429                         action_flags |= actions->type ==
5430                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5431                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5432                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5433                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5434                         break;
5435                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5436                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5437                         ret = flow_dv_validate_action_modify_tcp_ack
5438                                                                 (action_flags,
5439                                                                  actions,
5440                                                                  item_flags,
5441                                                                  error);
5442                         if (ret < 0)
5443                                 return ret;
5444                         /* Count all modify-header actions as one action. */
5445                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5446                                 ++actions_n;
5447                         action_flags |= actions->type ==
5448                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5449                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5450                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5451                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5452                         break;
5453                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5454                         break;
5455                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5456                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5457                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5458                         break;
5459                 case RTE_FLOW_ACTION_TYPE_METER:
5460                         ret = mlx5_flow_validate_action_meter(dev,
5461                                                               action_flags,
5462                                                               actions, attr,
5463                                                               error);
5464                         if (ret < 0)
5465                                 return ret;
5466                         action_flags |= MLX5_FLOW_ACTION_METER;
5467                         ++actions_n;
5468                         /* Meter action will add one more TAG action. */
5469                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5470                         break;
5471                 case RTE_FLOW_ACTION_TYPE_AGE:
5472                         ret = flow_dv_validate_action_age(action_flags,
5473                                                           actions, dev,
5474                                                           error);
5475                         if (ret < 0)
5476                                 return ret;
5477                         action_flags |= MLX5_FLOW_ACTION_AGE;
5478                         ++actions_n;
5479                         break;
5480                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5481                         ret = flow_dv_validate_action_modify_ipv4_dscp
5482                                                          (action_flags,
5483                                                           actions,
5484                                                           item_flags,
5485                                                           error);
5486                         if (ret < 0)
5487                                 return ret;
5488                         /* Count all modify-header actions as one action. */
5489                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5490                                 ++actions_n;
5491                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5492                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5493                         break;
5494                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5495                         ret = flow_dv_validate_action_modify_ipv6_dscp
5496                                                                 (action_flags,
5497                                                                  actions,
5498                                                                  item_flags,
5499                                                                  error);
5500                         if (ret < 0)
5501                                 return ret;
5502                         /* Count all modify-header actions as one action. */
5503                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5504                                 ++actions_n;
5505                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5506                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5507                         break;
5508                 default:
5509                         return rte_flow_error_set(error, ENOTSUP,
5510                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5511                                                   actions,
5512                                                   "action not supported");
5513                 }
5514         }
5515         /*
5516          * Validate the drop action mutual exclusion with other actions.
5517          * Drop action is mutually-exclusive with any other action, except for
5518          * Count action.
5519          */
5520         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5521             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5522                 return rte_flow_error_set(error, EINVAL,
5523                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5524                                           "Drop action is mutually-exclusive "
5525                                           "with any other action, except for "
5526                                           "Count action");
5527         /* Eswitch has few restrictions on using items and actions */
5528         if (attr->transfer) {
5529                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5530                     action_flags & MLX5_FLOW_ACTION_FLAG)
5531                         return rte_flow_error_set(error, ENOTSUP,
5532                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5533                                                   NULL,
5534                                                   "unsupported action FLAG");
5535                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5536                     action_flags & MLX5_FLOW_ACTION_MARK)
5537                         return rte_flow_error_set(error, ENOTSUP,
5538                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5539                                                   NULL,
5540                                                   "unsupported action MARK");
5541                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5542                         return rte_flow_error_set(error, ENOTSUP,
5543                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5544                                                   NULL,
5545                                                   "unsupported action QUEUE");
5546                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5547                         return rte_flow_error_set(error, ENOTSUP,
5548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5549                                                   NULL,
5550                                                   "unsupported action RSS");
5551                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5552                         return rte_flow_error_set(error, EINVAL,
5553                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5554                                                   actions,
5555                                                   "no fate action is found");
5556         } else {
5557                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5558                         return rte_flow_error_set(error, EINVAL,
5559                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5560                                                   actions,
5561                                                   "no fate action is found");
5562         }
5563         /* Continue validation for Xcap actions.*/
5564         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5565             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5566                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5567                     MLX5_FLOW_XCAP_ACTIONS)
5568                         return rte_flow_error_set(error, ENOTSUP,
5569                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5570                                                   NULL, "encap and decap "
5571                                                   "combination aren't supported");
5572                 if (!attr->transfer && attr->ingress && (action_flags &
5573                                                         MLX5_FLOW_ACTION_ENCAP))
5574                         return rte_flow_error_set(error, ENOTSUP,
5575                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5576                                                   NULL, "encap is not supported"
5577                                                   " for ingress traffic");
5578         }
5579         /* Hairpin flow will add one more TAG action. */
5580         if (hairpin > 0)
5581                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5582         /* extra metadata enabled: one more TAG action will be add. */
5583         if (dev_conf->dv_flow_en &&
5584             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5585             mlx5_flow_ext_mreg_supported(dev))
5586                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5587         if ((uint32_t)rw_act_num >
5588                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5589                 return rte_flow_error_set(error, ENOTSUP,
5590                                           RTE_FLOW_ERROR_TYPE_ACTION,
5591                                           NULL, "too many header modify"
5592                                           " actions to support");
5593         }
5594         return 0;
5595 }
5596
5597 /**
5598  * Internal preparation function. Allocates the DV flow size,
5599  * this size is constant.
5600  *
5601  * @param[in] dev
5602  *   Pointer to the rte_eth_dev structure.
5603  * @param[in] attr
5604  *   Pointer to the flow attributes.
5605  * @param[in] items
5606  *   Pointer to the list of items.
5607  * @param[in] actions
5608  *   Pointer to the list of actions.
5609  * @param[out] error
5610  *   Pointer to the error structure.
5611  *
5612  * @return
5613  *   Pointer to mlx5_flow object on success,
5614  *   otherwise NULL and rte_errno is set.
5615  */
5616 static struct mlx5_flow *
5617 flow_dv_prepare(struct rte_eth_dev *dev,
5618                 const struct rte_flow_attr *attr __rte_unused,
5619                 const struct rte_flow_item items[] __rte_unused,
5620                 const struct rte_flow_action actions[] __rte_unused,
5621                 struct rte_flow_error *error)
5622 {
5623         uint32_t handle_idx = 0;
5624         struct mlx5_flow *dev_flow;
5625         struct mlx5_flow_handle *dev_handle;
5626         struct mlx5_priv *priv = dev->data->dev_private;
5627
5628         /* In case of corrupting the memory. */
5629         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5630                 rte_flow_error_set(error, ENOSPC,
5631                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5632                                    "not free temporary device flow");
5633                 return NULL;
5634         }
5635         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5636                                    &handle_idx);
5637         if (!dev_handle) {
5638                 rte_flow_error_set(error, ENOMEM,
5639                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5640                                    "not enough memory to create flow handle");
5641                 return NULL;
5642         }
5643         /* No multi-thread supporting. */
5644         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5645         dev_flow->handle = dev_handle;
5646         dev_flow->handle_idx = handle_idx;
5647         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5648         /*
5649          * The matching value needs to be cleared to 0 before using. In the
5650          * past, it will be automatically cleared when using rte_*alloc
5651          * API. The time consumption will be almost the same as before.
5652          */
5653         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5654         dev_flow->ingress = attr->ingress;
5655         dev_flow->dv.transfer = attr->transfer;
5656         return dev_flow;
5657 }
5658
5659 #ifdef RTE_LIBRTE_MLX5_DEBUG
5660 /**
5661  * Sanity check for match mask and value. Similar to check_valid_spec() in
5662  * kernel driver. If unmasked bit is present in value, it returns failure.
5663  *
5664  * @param match_mask
5665  *   pointer to match mask buffer.
5666  * @param match_value
5667  *   pointer to match value buffer.
5668  *
5669  * @return
5670  *   0 if valid, -EINVAL otherwise.
5671  */
5672 static int
5673 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5674 {
5675         uint8_t *m = match_mask;
5676         uint8_t *v = match_value;
5677         unsigned int i;
5678
5679         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5680                 if (v[i] & ~m[i]) {
5681                         DRV_LOG(ERR,
5682                                 "match_value differs from match_criteria"
5683                                 " %p[%u] != %p[%u]",
5684                                 match_value, i, match_mask, i);
5685                         return -EINVAL;
5686                 }
5687         }
5688         return 0;
5689 }
5690 #endif
5691
5692 /**
5693  * Add match of ip_version.
5694  *
5695  * @param[in] group
5696  *   Flow group.
5697  * @param[in] headers_v
5698  *   Values header pointer.
5699  * @param[in] headers_m
5700  *   Masks header pointer.
5701  * @param[in] ip_version
5702  *   The IP version to set.
5703  */
5704 static inline void
5705 flow_dv_set_match_ip_version(uint32_t group,
5706                              void *headers_v,
5707                              void *headers_m,
5708                              uint8_t ip_version)
5709 {
5710         if (group == 0)
5711                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5712         else
5713                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5714                          ip_version);
5715         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5716         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5717         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5718 }
5719
5720 /**
5721  * Add Ethernet item to matcher and to the value.
5722  *
5723  * @param[in, out] matcher
5724  *   Flow matcher.
5725  * @param[in, out] key
5726  *   Flow matcher value.
5727  * @param[in] item
5728  *   Flow pattern to translate.
5729  * @param[in] inner
5730  *   Item is inner pattern.
5731  */
5732 static void
5733 flow_dv_translate_item_eth(void *matcher, void *key,
5734                            const struct rte_flow_item *item, int inner,
5735                            uint32_t group)
5736 {
5737         const struct rte_flow_item_eth *eth_m = item->mask;
5738         const struct rte_flow_item_eth *eth_v = item->spec;
5739         const struct rte_flow_item_eth nic_mask = {
5740                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5741                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5742                 .type = RTE_BE16(0xffff),
5743         };
5744         void *headers_m;
5745         void *headers_v;
5746         char *l24_v;
5747         unsigned int i;
5748
5749         if (!eth_v)
5750                 return;
5751         if (!eth_m)
5752                 eth_m = &nic_mask;
5753         if (inner) {
5754                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5755                                          inner_headers);
5756                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5757         } else {
5758                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5759                                          outer_headers);
5760                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5761         }
5762         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5763                &eth_m->dst, sizeof(eth_m->dst));
5764         /* The value must be in the range of the mask. */
5765         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5766         for (i = 0; i < sizeof(eth_m->dst); ++i)
5767                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5768         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5769                &eth_m->src, sizeof(eth_m->src));
5770         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5771         /* The value must be in the range of the mask. */
5772         for (i = 0; i < sizeof(eth_m->dst); ++i)
5773                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5774         if (eth_v->type) {
5775                 /* When ethertype is present set mask for tagged VLAN. */
5776                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5777                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5778                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5779                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5780                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5781                                  1);
5782                         /* Return here to avoid setting match on ethertype. */
5783                         return;
5784                 }
5785         }
5786         /*
5787          * HW supports match on one Ethertype, the Ethertype following the last
5788          * VLAN tag of the packet (see PRM).
5789          * Set match on ethertype only if ETH header is not followed by VLAN.
5790          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5791          * ethertype, and use ip_version field instead.
5792          */
5793         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5794             eth_m->type == 0xFFFF) {
5795                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5796         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5797                    eth_m->type == 0xFFFF) {
5798                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5799         } else {
5800                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5801                          rte_be_to_cpu_16(eth_m->type));
5802                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5803                                      ethertype);
5804                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5805         }
5806 }
5807
5808 /**
5809  * Add VLAN item to matcher and to the value.
5810  *
5811  * @param[in, out] dev_flow
5812  *   Flow descriptor.
5813  * @param[in, out] matcher
5814  *   Flow matcher.
5815  * @param[in, out] key
5816  *   Flow matcher value.
5817  * @param[in] item
5818  *   Flow pattern to translate.
5819  * @param[in] inner
5820  *   Item is inner pattern.
5821  */
5822 static void
5823 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5824                             void *matcher, void *key,
5825                             const struct rte_flow_item *item,
5826                             int inner, uint32_t group)
5827 {
5828         const struct rte_flow_item_vlan *vlan_m = item->mask;
5829         const struct rte_flow_item_vlan *vlan_v = item->spec;
5830         void *headers_m;
5831         void *headers_v;
5832         uint16_t tci_m;
5833         uint16_t tci_v;
5834
5835         if (inner) {
5836                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5837                                          inner_headers);
5838                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5839         } else {
5840                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5841                                          outer_headers);
5842                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5843                 /*
5844                  * This is workaround, masks are not supported,
5845                  * and pre-validated.
5846                  */
5847                 if (vlan_v)
5848                         dev_flow->handle->vf_vlan.tag =
5849                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5850         }
5851         /*
5852          * When VLAN item exists in flow, mark packet as tagged,
5853          * even if TCI is not specified.
5854          */
5855         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5856         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5857         if (!vlan_v)
5858                 return;
5859         if (!vlan_m)
5860                 vlan_m = &rte_flow_item_vlan_mask;
5861         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5862         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5863         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5864         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5865         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5866         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5867         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5868         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5869         /*
5870          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5871          * ethertype, and use ip_version field instead.
5872          */
5873         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5874             vlan_m->inner_type == 0xFFFF) {
5875                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5876         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5877                    vlan_m->inner_type == 0xFFFF) {
5878                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5879         } else {
5880                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5881                          rte_be_to_cpu_16(vlan_m->inner_type));
5882                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5883                          rte_be_to_cpu_16(vlan_m->inner_type &
5884                                           vlan_v->inner_type));
5885         }
5886 }
5887
5888 /**
5889  * Add IPV4 item to matcher and to the value.
5890  *
5891  * @param[in, out] matcher
5892  *   Flow matcher.
5893  * @param[in, out] key
5894  *   Flow matcher value.
5895  * @param[in] item
5896  *   Flow pattern to translate.
5897  * @param[in] item_flags
5898  *   Bit-fields that holds the items detected until now.
5899  * @param[in] inner
5900  *   Item is inner pattern.
5901  * @param[in] group
5902  *   The group to insert the rule.
5903  */
5904 static void
5905 flow_dv_translate_item_ipv4(void *matcher, void *key,
5906                             const struct rte_flow_item *item,
5907                             const uint64_t item_flags,
5908                             int inner, uint32_t group)
5909 {
5910         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5911         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5912         const struct rte_flow_item_ipv4 nic_mask = {
5913                 .hdr = {
5914                         .src_addr = RTE_BE32(0xffffffff),
5915                         .dst_addr = RTE_BE32(0xffffffff),
5916                         .type_of_service = 0xff,
5917                         .next_proto_id = 0xff,
5918                         .time_to_live = 0xff,
5919                 },
5920         };
5921         void *headers_m;
5922         void *headers_v;
5923         char *l24_m;
5924         char *l24_v;
5925         uint8_t tos;
5926
5927         if (inner) {
5928                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5929                                          inner_headers);
5930                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5931         } else {
5932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5933                                          outer_headers);
5934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5935         }
5936         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5937         /*
5938          * On outer header (which must contains L2), or inner header with L2,
5939          * set cvlan_tag mask bit to mark this packet as untagged.
5940          * This should be done even if item->spec is empty.
5941          */
5942         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5943                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5944         if (!ipv4_v)
5945                 return;
5946         if (!ipv4_m)
5947                 ipv4_m = &nic_mask;
5948         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5949                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5950         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5951                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5952         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5953         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5954         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5955                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5956         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5957                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5958         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5959         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5960         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5961         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5962                  ipv4_m->hdr.type_of_service);
5963         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5964         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5965                  ipv4_m->hdr.type_of_service >> 2);
5966         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5967         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5968                  ipv4_m->hdr.next_proto_id);
5969         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5970                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5971         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5972                  ipv4_m->hdr.time_to_live);
5973         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5974                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5975 }
5976
5977 /**
5978  * Add IPV6 item to matcher and to the value.
5979  *
5980  * @param[in, out] matcher
5981  *   Flow matcher.
5982  * @param[in, out] key
5983  *   Flow matcher value.
5984  * @param[in] item
5985  *   Flow pattern to translate.
5986  * @param[in] item_flags
5987  *   Bit-fields that holds the items detected until now.
5988  * @param[in] inner
5989  *   Item is inner pattern.
5990  * @param[in] group
5991  *   The group to insert the rule.
5992  */
5993 static void
5994 flow_dv_translate_item_ipv6(void *matcher, void *key,
5995                             const struct rte_flow_item *item,
5996                             const uint64_t item_flags,
5997                             int inner, uint32_t group)
5998 {
5999         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6000         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6001         const struct rte_flow_item_ipv6 nic_mask = {
6002                 .hdr = {
6003                         .src_addr =
6004                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6005                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6006                         .dst_addr =
6007                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6008                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6009                         .vtc_flow = RTE_BE32(0xffffffff),
6010                         .proto = 0xff,
6011                         .hop_limits = 0xff,
6012                 },
6013         };
6014         void *headers_m;
6015         void *headers_v;
6016         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6017         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6018         char *l24_m;
6019         char *l24_v;
6020         uint32_t vtc_m;
6021         uint32_t vtc_v;
6022         int i;
6023         int size;
6024
6025         if (inner) {
6026                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6027                                          inner_headers);
6028                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6029         } else {
6030                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6031                                          outer_headers);
6032                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6033         }
6034         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6035         /*
6036          * On outer header (which must contains L2), or inner header with L2,
6037          * set cvlan_tag mask bit to mark this packet as untagged.
6038          * This should be done even if item->spec is empty.
6039          */
6040         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6041                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6042         if (!ipv6_v)
6043                 return;
6044         if (!ipv6_m)
6045                 ipv6_m = &nic_mask;
6046         size = sizeof(ipv6_m->hdr.dst_addr);
6047         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6048                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6049         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6050                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6051         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6052         for (i = 0; i < size; ++i)
6053                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6054         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6055                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6056         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6057                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6058         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6059         for (i = 0; i < size; ++i)
6060                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6061         /* TOS. */
6062         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6063         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6064         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6065         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6066         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6067         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6068         /* Label. */
6069         if (inner) {
6070                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6071                          vtc_m);
6072                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6073                          vtc_v);
6074         } else {
6075                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6076                          vtc_m);
6077                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6078                          vtc_v);
6079         }
6080         /* Protocol. */
6081         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6082                  ipv6_m->hdr.proto);
6083         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6084                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6085         /* Hop limit. */
6086         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6087                  ipv6_m->hdr.hop_limits);
6088         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6089                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6090 }
6091
6092 /**
6093  * Add TCP item to matcher and to the value.
6094  *
6095  * @param[in, out] matcher
6096  *   Flow matcher.
6097  * @param[in, out] key
6098  *   Flow matcher value.
6099  * @param[in] item
6100  *   Flow pattern to translate.
6101  * @param[in] inner
6102  *   Item is inner pattern.
6103  */
6104 static void
6105 flow_dv_translate_item_tcp(void *matcher, void *key,
6106                            const struct rte_flow_item *item,
6107                            int inner)
6108 {
6109         const struct rte_flow_item_tcp *tcp_m = item->mask;
6110         const struct rte_flow_item_tcp *tcp_v = item->spec;
6111         void *headers_m;
6112         void *headers_v;
6113
6114         if (inner) {
6115                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6116                                          inner_headers);
6117                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6118         } else {
6119                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6120                                          outer_headers);
6121                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6122         }
6123         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6124         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6125         if (!tcp_v)
6126                 return;
6127         if (!tcp_m)
6128                 tcp_m = &rte_flow_item_tcp_mask;
6129         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6130                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6131         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6132                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6133         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6134                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6135         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6136                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6137         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6138                  tcp_m->hdr.tcp_flags);
6139         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6140                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6141 }
6142
6143 /**
6144  * Add UDP item to matcher and to the value.
6145  *
6146  * @param[in, out] matcher
6147  *   Flow matcher.
6148  * @param[in, out] key
6149  *   Flow matcher value.
6150  * @param[in] item
6151  *   Flow pattern to translate.
6152  * @param[in] inner
6153  *   Item is inner pattern.
6154  */
6155 static void
6156 flow_dv_translate_item_udp(void *matcher, void *key,
6157                            const struct rte_flow_item *item,
6158                            int inner)
6159 {
6160         const struct rte_flow_item_udp *udp_m = item->mask;
6161         const struct rte_flow_item_udp *udp_v = item->spec;
6162         void *headers_m;
6163         void *headers_v;
6164
6165         if (inner) {
6166                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6167                                          inner_headers);
6168                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6169         } else {
6170                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6171                                          outer_headers);
6172                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6173         }
6174         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6175         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6176         if (!udp_v)
6177                 return;
6178         if (!udp_m)
6179                 udp_m = &rte_flow_item_udp_mask;
6180         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6181                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6182         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6183                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6184         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6185                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6186         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6187                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6188 }
6189
6190 /**
6191  * Add GRE optional Key item to matcher and to the value.
6192  *
6193  * @param[in, out] matcher
6194  *   Flow matcher.
6195  * @param[in, out] key
6196  *   Flow matcher value.
6197  * @param[in] item
6198  *   Flow pattern to translate.
6199  * @param[in] inner
6200  *   Item is inner pattern.
6201  */
6202 static void
6203 flow_dv_translate_item_gre_key(void *matcher, void *key,
6204                                    const struct rte_flow_item *item)
6205 {
6206         const rte_be32_t *key_m = item->mask;
6207         const rte_be32_t *key_v = item->spec;
6208         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6209         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6210         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6211
6212         /* GRE K bit must be on and should already be validated */
6213         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6214         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6215         if (!key_v)
6216                 return;
6217         if (!key_m)
6218                 key_m = &gre_key_default_mask;
6219         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6220                  rte_be_to_cpu_32(*key_m) >> 8);
6221         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6222                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6223         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6224                  rte_be_to_cpu_32(*key_m) & 0xFF);
6225         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6226                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6227 }
6228
6229 /**
6230  * Add GRE item to matcher and to the value.
6231  *
6232  * @param[in, out] matcher
6233  *   Flow matcher.
6234  * @param[in, out] key
6235  *   Flow matcher value.
6236  * @param[in] item
6237  *   Flow pattern to translate.
6238  * @param[in] inner
6239  *   Item is inner pattern.
6240  */
6241 static void
6242 flow_dv_translate_item_gre(void *matcher, void *key,
6243                            const struct rte_flow_item *item,
6244                            int inner)
6245 {
6246         const struct rte_flow_item_gre *gre_m = item->mask;
6247         const struct rte_flow_item_gre *gre_v = item->spec;
6248         void *headers_m;
6249         void *headers_v;
6250         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6251         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6252         struct {
6253                 union {
6254                         __extension__
6255                         struct {
6256                                 uint16_t version:3;
6257                                 uint16_t rsvd0:9;
6258                                 uint16_t s_present:1;
6259                                 uint16_t k_present:1;
6260                                 uint16_t rsvd_bit1:1;
6261                                 uint16_t c_present:1;
6262                         };
6263                         uint16_t value;
6264                 };
6265         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6266
6267         if (inner) {
6268                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6269                                          inner_headers);
6270                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6271         } else {
6272                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6273                                          outer_headers);
6274                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6275         }
6276         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6277         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6278         if (!gre_v)
6279                 return;
6280         if (!gre_m)
6281                 gre_m = &rte_flow_item_gre_mask;
6282         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6283                  rte_be_to_cpu_16(gre_m->protocol));
6284         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6285                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6286         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6287         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6288         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6289                  gre_crks_rsvd0_ver_m.c_present);
6290         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6291                  gre_crks_rsvd0_ver_v.c_present &
6292                  gre_crks_rsvd0_ver_m.c_present);
6293         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6294                  gre_crks_rsvd0_ver_m.k_present);
6295         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6296                  gre_crks_rsvd0_ver_v.k_present &
6297                  gre_crks_rsvd0_ver_m.k_present);
6298         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6299                  gre_crks_rsvd0_ver_m.s_present);
6300         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6301                  gre_crks_rsvd0_ver_v.s_present &
6302                  gre_crks_rsvd0_ver_m.s_present);
6303 }
6304
6305 /**
6306  * Add NVGRE item to matcher and to the value.
6307  *
6308  * @param[in, out] matcher
6309  *   Flow matcher.
6310  * @param[in, out] key
6311  *   Flow matcher value.
6312  * @param[in] item
6313  *   Flow pattern to translate.
6314  * @param[in] inner
6315  *   Item is inner pattern.
6316  */
6317 static void
6318 flow_dv_translate_item_nvgre(void *matcher, void *key,
6319                              const struct rte_flow_item *item,
6320                              int inner)
6321 {
6322         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6323         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6324         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6325         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6326         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6327         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6328         char *gre_key_m;
6329         char *gre_key_v;
6330         int size;
6331         int i;
6332
6333         /* For NVGRE, GRE header fields must be set with defined values. */
6334         const struct rte_flow_item_gre gre_spec = {
6335                 .c_rsvd0_ver = RTE_BE16(0x2000),
6336                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6337         };
6338         const struct rte_flow_item_gre gre_mask = {
6339                 .c_rsvd0_ver = RTE_BE16(0xB000),
6340                 .protocol = RTE_BE16(UINT16_MAX),
6341         };
6342         const struct rte_flow_item gre_item = {
6343                 .spec = &gre_spec,
6344                 .mask = &gre_mask,
6345                 .last = NULL,
6346         };
6347         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6348         if (!nvgre_v)
6349                 return;
6350         if (!nvgre_m)
6351                 nvgre_m = &rte_flow_item_nvgre_mask;
6352         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6353         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6354         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6355         memcpy(gre_key_m, tni_flow_id_m, size);
6356         for (i = 0; i < size; ++i)
6357                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6358 }
6359
6360 /**
6361  * Add VXLAN item to matcher and to the value.
6362  *
6363  * @param[in, out] matcher
6364  *   Flow matcher.
6365  * @param[in, out] key
6366  *   Flow matcher value.
6367  * @param[in] item
6368  *   Flow pattern to translate.
6369  * @param[in] inner
6370  *   Item is inner pattern.
6371  */
6372 static void
6373 flow_dv_translate_item_vxlan(void *matcher, void *key,
6374                              const struct rte_flow_item *item,
6375                              int inner)
6376 {
6377         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6378         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6379         void *headers_m;
6380         void *headers_v;
6381         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6382         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6383         char *vni_m;
6384         char *vni_v;
6385         uint16_t dport;
6386         int size;
6387         int i;
6388
6389         if (inner) {
6390                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6391                                          inner_headers);
6392                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6393         } else {
6394                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6395                                          outer_headers);
6396                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6397         }
6398         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6399                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6400         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6401                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6402                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6403         }
6404         if (!vxlan_v)
6405                 return;
6406         if (!vxlan_m)
6407                 vxlan_m = &rte_flow_item_vxlan_mask;
6408         size = sizeof(vxlan_m->vni);
6409         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6410         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6411         memcpy(vni_m, vxlan_m->vni, size);
6412         for (i = 0; i < size; ++i)
6413                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6414 }
6415
6416 /**
6417  * Add VXLAN-GPE item to matcher and to the value.
6418  *
6419  * @param[in, out] matcher
6420  *   Flow matcher.
6421  * @param[in, out] key
6422  *   Flow matcher value.
6423  * @param[in] item
6424  *   Flow pattern to translate.
6425  * @param[in] inner
6426  *   Item is inner pattern.
6427  */
6428
6429 static void
6430 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6431                                  const struct rte_flow_item *item, int inner)
6432 {
6433         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6434         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6435         void *headers_m;
6436         void *headers_v;
6437         void *misc_m =
6438                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6439         void *misc_v =
6440                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6441         char *vni_m;
6442         char *vni_v;
6443         uint16_t dport;
6444         int size;
6445         int i;
6446         uint8_t flags_m = 0xff;
6447         uint8_t flags_v = 0xc;
6448
6449         if (inner) {
6450                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6451                                          inner_headers);
6452                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6453         } else {
6454                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6455                                          outer_headers);
6456                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6457         }
6458         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6459                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6460         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6461                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6462                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6463         }
6464         if (!vxlan_v)
6465                 return;
6466         if (!vxlan_m)
6467                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6468         size = sizeof(vxlan_m->vni);
6469         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6470         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6471         memcpy(vni_m, vxlan_m->vni, size);
6472         for (i = 0; i < size; ++i)
6473                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6474         if (vxlan_m->flags) {
6475                 flags_m = vxlan_m->flags;
6476                 flags_v = vxlan_v->flags;
6477         }
6478         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6479         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6480         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6481                  vxlan_m->protocol);
6482         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6483                  vxlan_v->protocol);
6484 }
6485
6486 /**
6487  * Add Geneve item to matcher and to the value.
6488  *
6489  * @param[in, out] matcher
6490  *   Flow matcher.
6491  * @param[in, out] key
6492  *   Flow matcher value.
6493  * @param[in] item
6494  *   Flow pattern to translate.
6495  * @param[in] inner
6496  *   Item is inner pattern.
6497  */
6498
6499 static void
6500 flow_dv_translate_item_geneve(void *matcher, void *key,
6501                               const struct rte_flow_item *item, int inner)
6502 {
6503         const struct rte_flow_item_geneve *geneve_m = item->mask;
6504         const struct rte_flow_item_geneve *geneve_v = item->spec;
6505         void *headers_m;
6506         void *headers_v;
6507         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6508         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6509         uint16_t dport;
6510         uint16_t gbhdr_m;
6511         uint16_t gbhdr_v;
6512         char *vni_m;
6513         char *vni_v;
6514         size_t size, i;
6515
6516         if (inner) {
6517                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6518                                          inner_headers);
6519                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6520         } else {
6521                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6522                                          outer_headers);
6523                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6524         }
6525         dport = MLX5_UDP_PORT_GENEVE;
6526         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6527                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6528                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6529         }
6530         if (!geneve_v)
6531                 return;
6532         if (!geneve_m)
6533                 geneve_m = &rte_flow_item_geneve_mask;
6534         size = sizeof(geneve_m->vni);
6535         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6536         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6537         memcpy(vni_m, geneve_m->vni, size);
6538         for (i = 0; i < size; ++i)
6539                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6540         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6541                  rte_be_to_cpu_16(geneve_m->protocol));
6542         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6543                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6544         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6545         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6546         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6547                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6548         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6549                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6550         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6551                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6552         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6553                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6554                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6555 }
6556
6557 /**
6558  * Add MPLS item to matcher and to the value.
6559  *
6560  * @param[in, out] matcher
6561  *   Flow matcher.
6562  * @param[in, out] key
6563  *   Flow matcher value.
6564  * @param[in] item
6565  *   Flow pattern to translate.
6566  * @param[in] prev_layer
6567  *   The protocol layer indicated in previous item.
6568  * @param[in] inner
6569  *   Item is inner pattern.
6570  */
6571 static void
6572 flow_dv_translate_item_mpls(void *matcher, void *key,
6573                             const struct rte_flow_item *item,
6574                             uint64_t prev_layer,
6575                             int inner)
6576 {
6577         const uint32_t *in_mpls_m = item->mask;
6578         const uint32_t *in_mpls_v = item->spec;
6579         uint32_t *out_mpls_m = 0;
6580         uint32_t *out_mpls_v = 0;
6581         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6582         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6583         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6584                                      misc_parameters_2);
6585         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6586         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6587         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6588
6589         switch (prev_layer) {
6590         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6591                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6592                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6593                          MLX5_UDP_PORT_MPLS);
6594                 break;
6595         case MLX5_FLOW_LAYER_GRE:
6596                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6597                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6598                          RTE_ETHER_TYPE_MPLS);
6599                 break;
6600         default:
6601                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6602                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6603                          IPPROTO_MPLS);
6604                 break;
6605         }
6606         if (!in_mpls_v)
6607                 return;
6608         if (!in_mpls_m)
6609                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6610         switch (prev_layer) {
6611         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6612                 out_mpls_m =
6613                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6614                                                  outer_first_mpls_over_udp);
6615                 out_mpls_v =
6616                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6617                                                  outer_first_mpls_over_udp);
6618                 break;
6619         case MLX5_FLOW_LAYER_GRE:
6620                 out_mpls_m =
6621                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6622                                                  outer_first_mpls_over_gre);
6623                 out_mpls_v =
6624                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6625                                                  outer_first_mpls_over_gre);
6626                 break;
6627         default:
6628                 /* Inner MPLS not over GRE is not supported. */
6629                 if (!inner) {
6630                         out_mpls_m =
6631                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6632                                                          misc2_m,
6633                                                          outer_first_mpls);
6634                         out_mpls_v =
6635                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6636                                                          misc2_v,
6637                                                          outer_first_mpls);
6638                 }
6639                 break;
6640         }
6641         if (out_mpls_m && out_mpls_v) {
6642                 *out_mpls_m = *in_mpls_m;
6643                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6644         }
6645 }
6646
6647 /**
6648  * Add metadata register item to matcher
6649  *
6650  * @param[in, out] matcher
6651  *   Flow matcher.
6652  * @param[in, out] key
6653  *   Flow matcher value.
6654  * @param[in] reg_type
6655  *   Type of device metadata register
6656  * @param[in] value
6657  *   Register value
6658  * @param[in] mask
6659  *   Register mask
6660  */
6661 static void
6662 flow_dv_match_meta_reg(void *matcher, void *key,
6663                        enum modify_reg reg_type,
6664                        uint32_t data, uint32_t mask)
6665 {
6666         void *misc2_m =
6667                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6668         void *misc2_v =
6669                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6670         uint32_t temp;
6671
6672         data &= mask;
6673         switch (reg_type) {
6674         case REG_A:
6675                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6676                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6677                 break;
6678         case REG_B:
6679                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6680                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6681                 break;
6682         case REG_C_0:
6683                 /*
6684                  * The metadata register C0 field might be divided into
6685                  * source vport index and META item value, we should set
6686                  * this field according to specified mask, not as whole one.
6687                  */
6688                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6689                 temp |= mask;
6690                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6691                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6692                 temp &= ~mask;
6693                 temp |= data;
6694                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6695                 break;
6696         case REG_C_1:
6697                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6698                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6699                 break;
6700         case REG_C_2:
6701                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6702                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6703                 break;
6704         case REG_C_3:
6705                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6706                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6707                 break;
6708         case REG_C_4:
6709                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6710                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6711                 break;
6712         case REG_C_5:
6713                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6714                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6715                 break;
6716         case REG_C_6:
6717                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6718                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6719                 break;
6720         case REG_C_7:
6721                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6722                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6723                 break;
6724         default:
6725                 MLX5_ASSERT(false);
6726                 break;
6727         }
6728 }
6729
6730 /**
6731  * Add MARK item to matcher
6732  *
6733  * @param[in] dev
6734  *   The device to configure through.
6735  * @param[in, out] matcher
6736  *   Flow matcher.
6737  * @param[in, out] key
6738  *   Flow matcher value.
6739  * @param[in] item
6740  *   Flow pattern to translate.
6741  */
6742 static void
6743 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6744                             void *matcher, void *key,
6745                             const struct rte_flow_item *item)
6746 {
6747         struct mlx5_priv *priv = dev->data->dev_private;
6748         const struct rte_flow_item_mark *mark;
6749         uint32_t value;
6750         uint32_t mask;
6751
6752         mark = item->mask ? (const void *)item->mask :
6753                             &rte_flow_item_mark_mask;
6754         mask = mark->id & priv->sh->dv_mark_mask;
6755         mark = (const void *)item->spec;
6756         MLX5_ASSERT(mark);
6757         value = mark->id & priv->sh->dv_mark_mask & mask;
6758         if (mask) {
6759                 enum modify_reg reg;
6760
6761                 /* Get the metadata register index for the mark. */
6762                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6763                 MLX5_ASSERT(reg > 0);
6764                 if (reg == REG_C_0) {
6765                         struct mlx5_priv *priv = dev->data->dev_private;
6766                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6767                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6768
6769                         mask &= msk_c0;
6770                         mask <<= shl_c0;
6771                         value <<= shl_c0;
6772                 }
6773                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6774         }
6775 }
6776
6777 /**
6778  * Add META item to matcher
6779  *
6780  * @param[in] dev
6781  *   The devich to configure through.
6782  * @param[in, out] matcher
6783  *   Flow matcher.
6784  * @param[in, out] key
6785  *   Flow matcher value.
6786  * @param[in] attr
6787  *   Attributes of flow that includes this item.
6788  * @param[in] item
6789  *   Flow pattern to translate.
6790  */
6791 static void
6792 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6793                             void *matcher, void *key,
6794                             const struct rte_flow_attr *attr,
6795                             const struct rte_flow_item *item)
6796 {
6797         const struct rte_flow_item_meta *meta_m;
6798         const struct rte_flow_item_meta *meta_v;
6799
6800         meta_m = (const void *)item->mask;
6801         if (!meta_m)
6802                 meta_m = &rte_flow_item_meta_mask;
6803         meta_v = (const void *)item->spec;
6804         if (meta_v) {
6805                 int reg;
6806                 uint32_t value = meta_v->data;
6807                 uint32_t mask = meta_m->data;
6808
6809                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6810                 if (reg < 0)
6811                         return;
6812                 /*
6813                  * In datapath code there is no endianness
6814                  * coversions for perfromance reasons, all
6815                  * pattern conversions are done in rte_flow.
6816                  */
6817                 value = rte_cpu_to_be_32(value);
6818                 mask = rte_cpu_to_be_32(mask);
6819                 if (reg == REG_C_0) {
6820                         struct mlx5_priv *priv = dev->data->dev_private;
6821                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6822                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6823 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6824                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6825
6826                         value >>= shr_c0;
6827                         mask >>= shr_c0;
6828 #endif
6829                         value <<= shl_c0;
6830                         mask <<= shl_c0;
6831                         MLX5_ASSERT(msk_c0);
6832                         MLX5_ASSERT(!(~msk_c0 & mask));
6833                 }
6834                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6835         }
6836 }
6837
6838 /**
6839  * Add vport metadata Reg C0 item to matcher
6840  *
6841  * @param[in, out] matcher
6842  *   Flow matcher.
6843  * @param[in, out] key
6844  *   Flow matcher value.
6845  * @param[in] reg
6846  *   Flow pattern to translate.
6847  */
6848 static void
6849 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6850                                   uint32_t value, uint32_t mask)
6851 {
6852         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6853 }
6854
6855 /**
6856  * Add tag item to matcher
6857  *
6858  * @param[in] dev
6859  *   The devich to configure through.
6860  * @param[in, out] matcher
6861  *   Flow matcher.
6862  * @param[in, out] key
6863  *   Flow matcher value.
6864  * @param[in] item
6865  *   Flow pattern to translate.
6866  */
6867 static void
6868 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6869                                 void *matcher, void *key,
6870                                 const struct rte_flow_item *item)
6871 {
6872         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6873         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6874         uint32_t mask, value;
6875
6876         MLX5_ASSERT(tag_v);
6877         value = tag_v->data;
6878         mask = tag_m ? tag_m->data : UINT32_MAX;
6879         if (tag_v->id == REG_C_0) {
6880                 struct mlx5_priv *priv = dev->data->dev_private;
6881                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6882                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6883
6884                 mask &= msk_c0;
6885                 mask <<= shl_c0;
6886                 value <<= shl_c0;
6887         }
6888         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6889 }
6890
6891 /**
6892  * Add TAG item to matcher
6893  *
6894  * @param[in] dev
6895  *   The devich to configure through.
6896  * @param[in, out] matcher
6897  *   Flow matcher.
6898  * @param[in, out] key
6899  *   Flow matcher value.
6900  * @param[in] item
6901  *   Flow pattern to translate.
6902  */
6903 static void
6904 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6905                            void *matcher, void *key,
6906                            const struct rte_flow_item *item)
6907 {
6908         const struct rte_flow_item_tag *tag_v = item->spec;
6909         const struct rte_flow_item_tag *tag_m = item->mask;
6910         enum modify_reg reg;
6911
6912         MLX5_ASSERT(tag_v);
6913         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6914         /* Get the metadata register index for the tag. */
6915         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6916         MLX5_ASSERT(reg > 0);
6917         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6918 }
6919
6920 /**
6921  * Add source vport match to the specified matcher.
6922  *
6923  * @param[in, out] matcher
6924  *   Flow matcher.
6925  * @param[in, out] key
6926  *   Flow matcher value.
6927  * @param[in] port
6928  *   Source vport value to match
6929  * @param[in] mask
6930  *   Mask
6931  */
6932 static void
6933 flow_dv_translate_item_source_vport(void *matcher, void *key,
6934                                     int16_t port, uint16_t mask)
6935 {
6936         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6937         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6938
6939         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6940         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6941 }
6942
6943 /**
6944  * Translate port-id item to eswitch match on  port-id.
6945  *
6946  * @param[in] dev
6947  *   The devich to configure through.
6948  * @param[in, out] matcher
6949  *   Flow matcher.
6950  * @param[in, out] key
6951  *   Flow matcher value.
6952  * @param[in] item
6953  *   Flow pattern to translate.
6954  *
6955  * @return
6956  *   0 on success, a negative errno value otherwise.
6957  */
6958 static int
6959 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6960                                void *key, const struct rte_flow_item *item)
6961 {
6962         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6963         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6964         struct mlx5_priv *priv;
6965         uint16_t mask, id;
6966
6967         mask = pid_m ? pid_m->id : 0xffff;
6968         id = pid_v ? pid_v->id : dev->data->port_id;
6969         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6970         if (!priv)
6971                 return -rte_errno;
6972         /* Translate to vport field or to metadata, depending on mode. */
6973         if (priv->vport_meta_mask)
6974                 flow_dv_translate_item_meta_vport(matcher, key,
6975                                                   priv->vport_meta_tag,
6976                                                   priv->vport_meta_mask);
6977         else
6978                 flow_dv_translate_item_source_vport(matcher, key,
6979                                                     priv->vport_id, mask);
6980         return 0;
6981 }
6982
6983 /**
6984  * Add ICMP6 item to matcher and to the value.
6985  *
6986  * @param[in, out] matcher
6987  *   Flow matcher.
6988  * @param[in, out] key
6989  *   Flow matcher value.
6990  * @param[in] item
6991  *   Flow pattern to translate.
6992  * @param[in] inner
6993  *   Item is inner pattern.
6994  */
6995 static void
6996 flow_dv_translate_item_icmp6(void *matcher, void *key,
6997                               const struct rte_flow_item *item,
6998                               int inner)
6999 {
7000         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7001         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7002         void *headers_m;
7003         void *headers_v;
7004         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7005                                      misc_parameters_3);
7006         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7007         if (inner) {
7008                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7009                                          inner_headers);
7010                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7011         } else {
7012                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7013                                          outer_headers);
7014                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7015         }
7016         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7017         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7018         if (!icmp6_v)
7019                 return;
7020         if (!icmp6_m)
7021                 icmp6_m = &rte_flow_item_icmp6_mask;
7022         /*
7023          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7024          * If only the protocol is specified, no need to match the frag.
7025          */
7026         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7027         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7028         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7029         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7030                  icmp6_v->type & icmp6_m->type);
7031         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7032         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7033                  icmp6_v->code & icmp6_m->code);
7034 }
7035
7036 /**
7037  * Add ICMP item to matcher and to the value.
7038  *
7039  * @param[in, out] matcher
7040  *   Flow matcher.
7041  * @param[in, out] key
7042  *   Flow matcher value.
7043  * @param[in] item
7044  *   Flow pattern to translate.
7045  * @param[in] inner
7046  *   Item is inner pattern.
7047  */
7048 static void
7049 flow_dv_translate_item_icmp(void *matcher, void *key,
7050                             const struct rte_flow_item *item,
7051                             int inner)
7052 {
7053         const struct rte_flow_item_icmp *icmp_m = item->mask;
7054         const struct rte_flow_item_icmp *icmp_v = item->spec;
7055         void *headers_m;
7056         void *headers_v;
7057         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7058                                      misc_parameters_3);
7059         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7060         if (inner) {
7061                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7062                                          inner_headers);
7063                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7064         } else {
7065                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7066                                          outer_headers);
7067                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7068         }
7069         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7070         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7071         if (!icmp_v)
7072                 return;
7073         if (!icmp_m)
7074                 icmp_m = &rte_flow_item_icmp_mask;
7075         /*
7076          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7077          * If only the protocol is specified, no need to match the frag.
7078          */
7079         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7080         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7081         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7082                  icmp_m->hdr.icmp_type);
7083         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7084                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7085         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7086                  icmp_m->hdr.icmp_code);
7087         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7088                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7089 }
7090
7091 /**
7092  * Add GTP item to matcher and to the value.
7093  *
7094  * @param[in, out] matcher
7095  *   Flow matcher.
7096  * @param[in, out] key
7097  *   Flow matcher value.
7098  * @param[in] item
7099  *   Flow pattern to translate.
7100  * @param[in] inner
7101  *   Item is inner pattern.
7102  */
7103 static void
7104 flow_dv_translate_item_gtp(void *matcher, void *key,
7105                            const struct rte_flow_item *item, int inner)
7106 {
7107         const struct rte_flow_item_gtp *gtp_m = item->mask;
7108         const struct rte_flow_item_gtp *gtp_v = item->spec;
7109         void *headers_m;
7110         void *headers_v;
7111         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7112                                      misc_parameters_3);
7113         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7114         uint16_t dport = RTE_GTPU_UDP_PORT;
7115
7116         if (inner) {
7117                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7118                                          inner_headers);
7119                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7120         } else {
7121                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7122                                          outer_headers);
7123                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7124         }
7125         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7126                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7127                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7128         }
7129         if (!gtp_v)
7130                 return;
7131         if (!gtp_m)
7132                 gtp_m = &rte_flow_item_gtp_mask;
7133         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7134                  gtp_m->v_pt_rsv_flags);
7135         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7136                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7137         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7138         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7139                  gtp_v->msg_type & gtp_m->msg_type);
7140         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7141                  rte_be_to_cpu_32(gtp_m->teid));
7142         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7143                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7144 }
7145
7146 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7147
7148 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7149         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7150                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7151
7152 /**
7153  * Calculate flow matcher enable bitmap.
7154  *
7155  * @param match_criteria
7156  *   Pointer to flow matcher criteria.
7157  *
7158  * @return
7159  *   Bitmap of enabled fields.
7160  */
7161 static uint8_t
7162 flow_dv_matcher_enable(uint32_t *match_criteria)
7163 {
7164         uint8_t match_criteria_enable;
7165
7166         match_criteria_enable =
7167                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7168                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7169         match_criteria_enable |=
7170                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7171                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7172         match_criteria_enable |=
7173                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7174                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7175         match_criteria_enable |=
7176                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7177                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7178         match_criteria_enable |=
7179                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7180                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7181         return match_criteria_enable;
7182 }
7183
7184
7185 /**
7186  * Get a flow table.
7187  *
7188  * @param[in, out] dev
7189  *   Pointer to rte_eth_dev structure.
7190  * @param[in] table_id
7191  *   Table id to use.
7192  * @param[in] egress
7193  *   Direction of the table.
7194  * @param[in] transfer
7195  *   E-Switch or NIC flow.
7196  * @param[out] error
7197  *   pointer to error structure.
7198  *
7199  * @return
7200  *   Returns tables resource based on the index, NULL in case of failed.
7201  */
7202 static struct mlx5_flow_tbl_resource *
7203 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7204                          uint32_t table_id, uint8_t egress,
7205                          uint8_t transfer,
7206                          struct rte_flow_error *error)
7207 {
7208         struct mlx5_priv *priv = dev->data->dev_private;
7209         struct mlx5_dev_ctx_shared *sh = priv->sh;
7210         struct mlx5_flow_tbl_resource *tbl;
7211         union mlx5_flow_tbl_key table_key = {
7212                 {
7213                         .table_id = table_id,
7214                         .reserved = 0,
7215                         .domain = !!transfer,
7216                         .direction = !!egress,
7217                 }
7218         };
7219         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7220                                                          table_key.v64);
7221         struct mlx5_flow_tbl_data_entry *tbl_data;
7222         uint32_t idx = 0;
7223         int ret;
7224         void *domain;
7225
7226         if (pos) {
7227                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7228                                         entry);
7229                 tbl = &tbl_data->tbl;
7230                 rte_atomic32_inc(&tbl->refcnt);
7231                 return tbl;
7232         }
7233         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7234         if (!tbl_data) {
7235                 rte_flow_error_set(error, ENOMEM,
7236                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7237                                    NULL,
7238                                    "cannot allocate flow table data entry");
7239                 return NULL;
7240         }
7241         tbl_data->idx = idx;
7242         tbl = &tbl_data->tbl;
7243         pos = &tbl_data->entry;
7244         if (transfer)
7245                 domain = sh->fdb_domain;
7246         else if (egress)
7247                 domain = sh->tx_domain;
7248         else
7249                 domain = sh->rx_domain;
7250         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7251         if (!tbl->obj) {
7252                 rte_flow_error_set(error, ENOMEM,
7253                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7254                                    NULL, "cannot create flow table object");
7255                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7256                 return NULL;
7257         }
7258         /*
7259          * No multi-threads now, but still better to initialize the reference
7260          * count before insert it into the hash list.
7261          */
7262         rte_atomic32_init(&tbl->refcnt);
7263         /* Jump action reference count is initialized here. */
7264         rte_atomic32_init(&tbl_data->jump.refcnt);
7265         pos->key = table_key.v64;
7266         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7267         if (ret < 0) {
7268                 rte_flow_error_set(error, -ret,
7269                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7270                                    "cannot insert flow table data entry");
7271                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7272                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7273         }
7274         rte_atomic32_inc(&tbl->refcnt);
7275         return tbl;
7276 }
7277
7278 /**
7279  * Release a flow table.
7280  *
7281  * @param[in] dev
7282  *   Pointer to rte_eth_dev structure.
7283  * @param[in] tbl
7284  *   Table resource to be released.
7285  *
7286  * @return
7287  *   Returns 0 if table was released, else return 1;
7288  */
7289 static int
7290 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7291                              struct mlx5_flow_tbl_resource *tbl)
7292 {
7293         struct mlx5_priv *priv = dev->data->dev_private;
7294         struct mlx5_dev_ctx_shared *sh = priv->sh;
7295         struct mlx5_flow_tbl_data_entry *tbl_data =
7296                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7297
7298         if (!tbl)
7299                 return 0;
7300         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7301                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7302
7303                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7304                 tbl->obj = NULL;
7305                 /* remove the entry from the hash list and free memory. */
7306                 mlx5_hlist_remove(sh->flow_tbls, pos);
7307                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7308                                 tbl_data->idx);
7309                 return 0;
7310         }
7311         return 1;
7312 }
7313
7314 /**
7315  * Register the flow matcher.
7316  *
7317  * @param[in, out] dev
7318  *   Pointer to rte_eth_dev structure.
7319  * @param[in, out] matcher
7320  *   Pointer to flow matcher.
7321  * @param[in, out] key
7322  *   Pointer to flow table key.
7323  * @parm[in, out] dev_flow
7324  *   Pointer to the dev_flow.
7325  * @param[out] error
7326  *   pointer to error structure.
7327  *
7328  * @return
7329  *   0 on success otherwise -errno and errno is set.
7330  */
7331 static int
7332 flow_dv_matcher_register(struct rte_eth_dev *dev,
7333                          struct mlx5_flow_dv_matcher *matcher,
7334                          union mlx5_flow_tbl_key *key,
7335                          struct mlx5_flow *dev_flow,
7336                          struct rte_flow_error *error)
7337 {
7338         struct mlx5_priv *priv = dev->data->dev_private;
7339         struct mlx5_dev_ctx_shared *sh = priv->sh;
7340         struct mlx5_flow_dv_matcher *cache_matcher;
7341         struct mlx5dv_flow_matcher_attr dv_attr = {
7342                 .type = IBV_FLOW_ATTR_NORMAL,
7343                 .match_mask = (void *)&matcher->mask,
7344         };
7345         struct mlx5_flow_tbl_resource *tbl;
7346         struct mlx5_flow_tbl_data_entry *tbl_data;
7347
7348         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7349                                        key->domain, error);
7350         if (!tbl)
7351                 return -rte_errno;      /* No need to refill the error info */
7352         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7353         /* Lookup from cache. */
7354         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7355                 if (matcher->crc == cache_matcher->crc &&
7356                     matcher->priority == cache_matcher->priority &&
7357                     !memcmp((const void *)matcher->mask.buf,
7358                             (const void *)cache_matcher->mask.buf,
7359                             cache_matcher->mask.size)) {
7360                         DRV_LOG(DEBUG,
7361                                 "%s group %u priority %hd use %s "
7362                                 "matcher %p: refcnt %d++",
7363                                 key->domain ? "FDB" : "NIC", key->table_id,
7364                                 cache_matcher->priority,
7365                                 key->direction ? "tx" : "rx",
7366                                 (void *)cache_matcher,
7367                                 rte_atomic32_read(&cache_matcher->refcnt));
7368                         rte_atomic32_inc(&cache_matcher->refcnt);
7369                         dev_flow->handle->dvh.matcher = cache_matcher;
7370                         /* old matcher should not make the table ref++. */
7371                         flow_dv_tbl_resource_release(dev, tbl);
7372                         return 0;
7373                 }
7374         }
7375         /* Register new matcher. */
7376         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7377         if (!cache_matcher) {
7378                 flow_dv_tbl_resource_release(dev, tbl);
7379                 return rte_flow_error_set(error, ENOMEM,
7380                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7381                                           "cannot allocate matcher memory");
7382         }
7383         *cache_matcher = *matcher;
7384         dv_attr.match_criteria_enable =
7385                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7386         dv_attr.priority = matcher->priority;
7387         if (key->direction)
7388                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7389         cache_matcher->matcher_object =
7390                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7391         if (!cache_matcher->matcher_object) {
7392                 rte_free(cache_matcher);
7393 #ifdef HAVE_MLX5DV_DR
7394                 flow_dv_tbl_resource_release(dev, tbl);
7395 #endif
7396                 return rte_flow_error_set(error, ENOMEM,
7397                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7398                                           NULL, "cannot create matcher");
7399         }
7400         /* Save the table information */
7401         cache_matcher->tbl = tbl;
7402         rte_atomic32_init(&cache_matcher->refcnt);
7403         /* only matcher ref++, table ref++ already done above in get API. */
7404         rte_atomic32_inc(&cache_matcher->refcnt);
7405         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7406         dev_flow->handle->dvh.matcher = cache_matcher;
7407         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7408                 key->domain ? "FDB" : "NIC", key->table_id,
7409                 cache_matcher->priority,
7410                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7411                 rte_atomic32_read(&cache_matcher->refcnt));
7412         return 0;
7413 }
7414
7415 /**
7416  * Find existing tag resource or create and register a new one.
7417  *
7418  * @param dev[in, out]
7419  *   Pointer to rte_eth_dev structure.
7420  * @param[in, out] tag_be24
7421  *   Tag value in big endian then R-shift 8.
7422  * @parm[in, out] dev_flow
7423  *   Pointer to the dev_flow.
7424  * @param[out] error
7425  *   pointer to error structure.
7426  *
7427  * @return
7428  *   0 on success otherwise -errno and errno is set.
7429  */
7430 static int
7431 flow_dv_tag_resource_register
7432                         (struct rte_eth_dev *dev,
7433                          uint32_t tag_be24,
7434                          struct mlx5_flow *dev_flow,
7435                          struct rte_flow_error *error)
7436 {
7437         struct mlx5_priv *priv = dev->data->dev_private;
7438         struct mlx5_dev_ctx_shared *sh = priv->sh;
7439         struct mlx5_flow_dv_tag_resource *cache_resource;
7440         struct mlx5_hlist_entry *entry;
7441
7442         /* Lookup a matching resource from cache. */
7443         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7444         if (entry) {
7445                 cache_resource = container_of
7446                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7447                 rte_atomic32_inc(&cache_resource->refcnt);
7448                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7449                 dev_flow->dv.tag_resource = cache_resource;
7450                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7451                         (void *)cache_resource,
7452                         rte_atomic32_read(&cache_resource->refcnt));
7453                 return 0;
7454         }
7455         /* Register new resource. */
7456         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7457                                        &dev_flow->handle->dvh.rix_tag);
7458         if (!cache_resource)
7459                 return rte_flow_error_set(error, ENOMEM,
7460                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7461                                           "cannot allocate resource memory");
7462         cache_resource->entry.key = (uint64_t)tag_be24;
7463         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7464         if (!cache_resource->action) {
7465                 rte_free(cache_resource);
7466                 return rte_flow_error_set(error, ENOMEM,
7467                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7468                                           NULL, "cannot create action");
7469         }
7470         rte_atomic32_init(&cache_resource->refcnt);
7471         rte_atomic32_inc(&cache_resource->refcnt);
7472         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7473                 mlx5_glue->destroy_flow_action(cache_resource->action);
7474                 rte_free(cache_resource);
7475                 return rte_flow_error_set(error, EEXIST,
7476                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7477                                           NULL, "cannot insert tag");
7478         }
7479         dev_flow->dv.tag_resource = cache_resource;
7480         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7481                 (void *)cache_resource,
7482                 rte_atomic32_read(&cache_resource->refcnt));
7483         return 0;
7484 }
7485
7486 /**
7487  * Release the tag.
7488  *
7489  * @param dev
7490  *   Pointer to Ethernet device.
7491  * @param tag_idx
7492  *   Tag index.
7493  *
7494  * @return
7495  *   1 while a reference on it exists, 0 when freed.
7496  */
7497 static int
7498 flow_dv_tag_release(struct rte_eth_dev *dev,
7499                     uint32_t tag_idx)
7500 {
7501         struct mlx5_priv *priv = dev->data->dev_private;
7502         struct mlx5_dev_ctx_shared *sh = priv->sh;
7503         struct mlx5_flow_dv_tag_resource *tag;
7504
7505         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7506         if (!tag)
7507                 return 0;
7508         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7509                 dev->data->port_id, (void *)tag,
7510                 rte_atomic32_read(&tag->refcnt));
7511         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7512                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7513                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7514                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7515                         dev->data->port_id, (void *)tag);
7516                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7517                 return 0;
7518         }
7519         return 1;
7520 }
7521
7522 /**
7523  * Translate port ID action to vport.
7524  *
7525  * @param[in] dev
7526  *   Pointer to rte_eth_dev structure.
7527  * @param[in] action
7528  *   Pointer to the port ID action.
7529  * @param[out] dst_port_id
7530  *   The target port ID.
7531  * @param[out] error
7532  *   Pointer to the error structure.
7533  *
7534  * @return
7535  *   0 on success, a negative errno value otherwise and rte_errno is set.
7536  */
7537 static int
7538 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7539                                  const struct rte_flow_action *action,
7540                                  uint32_t *dst_port_id,
7541                                  struct rte_flow_error *error)
7542 {
7543         uint32_t port;
7544         struct mlx5_priv *priv;
7545         const struct rte_flow_action_port_id *conf =
7546                         (const struct rte_flow_action_port_id *)action->conf;
7547
7548         port = conf->original ? dev->data->port_id : conf->id;
7549         priv = mlx5_port_to_eswitch_info(port, false);
7550         if (!priv)
7551                 return rte_flow_error_set(error, -rte_errno,
7552                                           RTE_FLOW_ERROR_TYPE_ACTION,
7553                                           NULL,
7554                                           "No eswitch info was found for port");
7555 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7556         /*
7557          * This parameter is transferred to
7558          * mlx5dv_dr_action_create_dest_ib_port().
7559          */
7560         *dst_port_id = priv->ibv_port;
7561 #else
7562         /*
7563          * Legacy mode, no LAG configurations is supported.
7564          * This parameter is transferred to
7565          * mlx5dv_dr_action_create_dest_vport().
7566          */
7567         *dst_port_id = priv->vport_id;
7568 #endif
7569         return 0;
7570 }
7571
7572 /**
7573  * Create a counter with aging configuration.
7574  *
7575  * @param[in] dev
7576  *   Pointer to rte_eth_dev structure.
7577  * @param[out] count
7578  *   Pointer to the counter action configuration.
7579  * @param[in] age
7580  *   Pointer to the aging action configuration.
7581  *
7582  * @return
7583  *   Index to flow counter on success, 0 otherwise.
7584  */
7585 static uint32_t
7586 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7587                                 struct mlx5_flow *dev_flow,
7588                                 const struct rte_flow_action_count *count,
7589                                 const struct rte_flow_action_age *age)
7590 {
7591         uint32_t counter;
7592         struct mlx5_age_param *age_param;
7593
7594         counter = flow_dv_counter_alloc(dev,
7595                                 count ? count->shared : 0,
7596                                 count ? count->id : 0,
7597                                 dev_flow->dv.group, !!age);
7598         if (!counter || age == NULL)
7599                 return counter;
7600         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7601         /*
7602          * The counter age accuracy may have a bit delay. Have 3/4
7603          * second bias on the timeount in order to let it age in time.
7604          */
7605         age_param->context = age->context ? age->context :
7606                 (void *)(uintptr_t)(dev_flow->flow_idx);
7607         /*
7608          * The counter age accuracy may have a bit delay. Have 3/4
7609          * second bias on the timeount in order to let it age in time.
7610          */
7611         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7612         /* Set expire time in unit of 0.1 sec. */
7613         age_param->port_id = dev->data->port_id;
7614         age_param->expire = age_param->timeout +
7615                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7616         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7617         return counter;
7618 }
7619 /**
7620  * Add Tx queue matcher
7621  *
7622  * @param[in] dev
7623  *   Pointer to the dev struct.
7624  * @param[in, out] matcher
7625  *   Flow matcher.
7626  * @param[in, out] key
7627  *   Flow matcher value.
7628  * @param[in] item
7629  *   Flow pattern to translate.
7630  * @param[in] inner
7631  *   Item is inner pattern.
7632  */
7633 static void
7634 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7635                                 void *matcher, void *key,
7636                                 const struct rte_flow_item *item)
7637 {
7638         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7639         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7640         void *misc_m =
7641                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7642         void *misc_v =
7643                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7644         struct mlx5_txq_ctrl *txq;
7645         uint32_t queue;
7646
7647
7648         queue_m = (const void *)item->mask;
7649         if (!queue_m)
7650                 return;
7651         queue_v = (const void *)item->spec;
7652         if (!queue_v)
7653                 return;
7654         txq = mlx5_txq_get(dev, queue_v->queue);
7655         if (!txq)
7656                 return;
7657         queue = txq->obj->sq->id;
7658         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7659         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7660                  queue & queue_m->queue);
7661         mlx5_txq_release(dev, queue_v->queue);
7662 }
7663
7664 /**
7665  * Set the hash fields according to the @p flow information.
7666  *
7667  * @param[in] dev_flow
7668  *   Pointer to the mlx5_flow.
7669  * @param[in] rss_desc
7670  *   Pointer to the mlx5_flow_rss_desc.
7671  */
7672 static void
7673 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7674                        struct mlx5_flow_rss_desc *rss_desc)
7675 {
7676         uint64_t items = dev_flow->handle->layers;
7677         int rss_inner = 0;
7678         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7679
7680         dev_flow->hash_fields = 0;
7681 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7682         if (rss_desc->level >= 2) {
7683                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7684                 rss_inner = 1;
7685         }
7686 #endif
7687         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7688             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7689                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7690                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7691                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7692                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7693                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7694                         else
7695                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7696                 }
7697         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7698                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7699                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7700                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7701                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7702                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7703                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7704                         else
7705                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7706                 }
7707         }
7708         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7709             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7710                 if (rss_types & ETH_RSS_UDP) {
7711                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7712                                 dev_flow->hash_fields |=
7713                                                 IBV_RX_HASH_SRC_PORT_UDP;
7714                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7715                                 dev_flow->hash_fields |=
7716                                                 IBV_RX_HASH_DST_PORT_UDP;
7717                         else
7718                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7719                 }
7720         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7721                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7722                 if (rss_types & ETH_RSS_TCP) {
7723                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7724                                 dev_flow->hash_fields |=
7725                                                 IBV_RX_HASH_SRC_PORT_TCP;
7726                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7727                                 dev_flow->hash_fields |=
7728                                                 IBV_RX_HASH_DST_PORT_TCP;
7729                         else
7730                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7731                 }
7732         }
7733 }
7734
7735 /**
7736  * Fill the flow with DV spec, lock free
7737  * (mutex should be acquired by caller).
7738  *
7739  * @param[in] dev
7740  *   Pointer to rte_eth_dev structure.
7741  * @param[in, out] dev_flow
7742  *   Pointer to the sub flow.
7743  * @param[in] attr
7744  *   Pointer to the flow attributes.
7745  * @param[in] items
7746  *   Pointer to the list of items.
7747  * @param[in] actions
7748  *   Pointer to the list of actions.
7749  * @param[out] error
7750  *   Pointer to the error structure.
7751  *
7752  * @return
7753  *   0 on success, a negative errno value otherwise and rte_errno is set.
7754  */
7755 static int
7756 __flow_dv_translate(struct rte_eth_dev *dev,
7757                     struct mlx5_flow *dev_flow,
7758                     const struct rte_flow_attr *attr,
7759                     const struct rte_flow_item items[],
7760                     const struct rte_flow_action actions[],
7761                     struct rte_flow_error *error)
7762 {
7763         struct mlx5_priv *priv = dev->data->dev_private;
7764         struct mlx5_dev_config *dev_conf = &priv->config;
7765         struct rte_flow *flow = dev_flow->flow;
7766         struct mlx5_flow_handle *handle = dev_flow->handle;
7767         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7768                                               priv->rss_desc)
7769                                               [!!priv->flow_nested_idx];
7770         uint64_t item_flags = 0;
7771         uint64_t last_item = 0;
7772         uint64_t action_flags = 0;
7773         uint64_t priority = attr->priority;
7774         struct mlx5_flow_dv_matcher matcher = {
7775                 .mask = {
7776                         .size = sizeof(matcher.mask.buf),
7777                 },
7778         };
7779         int actions_n = 0;
7780         bool actions_end = false;
7781         union {
7782                 struct mlx5_flow_dv_modify_hdr_resource res;
7783                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7784                             sizeof(struct mlx5_modification_cmd) *
7785                             (MLX5_MAX_MODIFY_NUM + 1)];
7786         } mhdr_dummy;
7787         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7788         const struct rte_flow_action_count *count = NULL;
7789         const struct rte_flow_action_age *age = NULL;
7790         union flow_dv_attr flow_attr = { .attr = 0 };
7791         uint32_t tag_be;
7792         union mlx5_flow_tbl_key tbl_key;
7793         uint32_t modify_action_position = UINT32_MAX;
7794         void *match_mask = matcher.mask.buf;
7795         void *match_value = dev_flow->dv.value.buf;
7796         uint8_t next_protocol = 0xff;
7797         struct rte_vlan_hdr vlan = { 0 };
7798         uint32_t table;
7799         int ret = 0;
7800
7801         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7802                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7803         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7804                                        !!priv->fdb_def_rule, &table, error);
7805         if (ret)
7806                 return ret;
7807         dev_flow->dv.group = table;
7808         if (attr->transfer)
7809                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7810         if (priority == MLX5_FLOW_PRIO_RSVD)
7811                 priority = dev_conf->flow_prio - 1;
7812         /* number of actions must be set to 0 in case of dirty stack. */
7813         mhdr_res->actions_num = 0;
7814         for (; !actions_end ; actions++) {
7815                 const struct rte_flow_action_queue *queue;
7816                 const struct rte_flow_action_rss *rss;
7817                 const struct rte_flow_action *action = actions;
7818                 const uint8_t *rss_key;
7819                 const struct rte_flow_action_jump *jump_data;
7820                 const struct rte_flow_action_meter *mtr;
7821                 struct mlx5_flow_tbl_resource *tbl;
7822                 uint32_t port_id = 0;
7823                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7824                 int action_type = actions->type;
7825                 const struct rte_flow_action *found_action = NULL;
7826                 struct mlx5_flow_meter *fm = NULL;
7827
7828                 switch (action_type) {
7829                 case RTE_FLOW_ACTION_TYPE_VOID:
7830                         break;
7831                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7832                         if (flow_dv_translate_action_port_id(dev, action,
7833                                                              &port_id, error))
7834                                 return -rte_errno;
7835                         port_id_resource.port_id = port_id;
7836                         MLX5_ASSERT(!handle->rix_port_id_action);
7837                         if (flow_dv_port_id_action_resource_register
7838                             (dev, &port_id_resource, dev_flow, error))
7839                                 return -rte_errno;
7840                         dev_flow->dv.actions[actions_n++] =
7841                                         dev_flow->dv.port_id_action->action;
7842                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7843                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7844                         break;
7845                 case RTE_FLOW_ACTION_TYPE_FLAG:
7846                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7847                         dev_flow->handle->mark = 1;
7848                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7849                                 struct rte_flow_action_mark mark = {
7850                                         .id = MLX5_FLOW_MARK_DEFAULT,
7851                                 };
7852
7853                                 if (flow_dv_convert_action_mark(dev, &mark,
7854                                                                 mhdr_res,
7855                                                                 error))
7856                                         return -rte_errno;
7857                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7858                                 break;
7859                         }
7860                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7861                         /*
7862                          * Only one FLAG or MARK is supported per device flow
7863                          * right now. So the pointer to the tag resource must be
7864                          * zero before the register process.
7865                          */
7866                         MLX5_ASSERT(!handle->dvh.rix_tag);
7867                         if (flow_dv_tag_resource_register(dev, tag_be,
7868                                                           dev_flow, error))
7869                                 return -rte_errno;
7870                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7871                         dev_flow->dv.actions[actions_n++] =
7872                                         dev_flow->dv.tag_resource->action;
7873                         break;
7874                 case RTE_FLOW_ACTION_TYPE_MARK:
7875                         action_flags |= MLX5_FLOW_ACTION_MARK;
7876                         dev_flow->handle->mark = 1;
7877                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7878                                 const struct rte_flow_action_mark *mark =
7879                                         (const struct rte_flow_action_mark *)
7880                                                 actions->conf;
7881
7882                                 if (flow_dv_convert_action_mark(dev, mark,
7883                                                                 mhdr_res,
7884                                                                 error))
7885                                         return -rte_errno;
7886                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7887                                 break;
7888                         }
7889                         /* Fall-through */
7890                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7891                         /* Legacy (non-extensive) MARK action. */
7892                         tag_be = mlx5_flow_mark_set
7893                               (((const struct rte_flow_action_mark *)
7894                                (actions->conf))->id);
7895                         MLX5_ASSERT(!handle->dvh.rix_tag);
7896                         if (flow_dv_tag_resource_register(dev, tag_be,
7897                                                           dev_flow, error))
7898                                 return -rte_errno;
7899                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7900                         dev_flow->dv.actions[actions_n++] =
7901                                         dev_flow->dv.tag_resource->action;
7902                         break;
7903                 case RTE_FLOW_ACTION_TYPE_SET_META:
7904                         if (flow_dv_convert_action_set_meta
7905                                 (dev, mhdr_res, attr,
7906                                  (const struct rte_flow_action_set_meta *)
7907                                   actions->conf, error))
7908                                 return -rte_errno;
7909                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7910                         break;
7911                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7912                         if (flow_dv_convert_action_set_tag
7913                                 (dev, mhdr_res,
7914                                  (const struct rte_flow_action_set_tag *)
7915                                   actions->conf, error))
7916                                 return -rte_errno;
7917                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7918                         break;
7919                 case RTE_FLOW_ACTION_TYPE_DROP:
7920                         action_flags |= MLX5_FLOW_ACTION_DROP;
7921                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7922                         break;
7923                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7924                         queue = actions->conf;
7925                         rss_desc->queue_num = 1;
7926                         rss_desc->queue[0] = queue->index;
7927                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7928                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7929                         break;
7930                 case RTE_FLOW_ACTION_TYPE_RSS:
7931                         rss = actions->conf;
7932                         memcpy(rss_desc->queue, rss->queue,
7933                                rss->queue_num * sizeof(uint16_t));
7934                         rss_desc->queue_num = rss->queue_num;
7935                         /* NULL RSS key indicates default RSS key. */
7936                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7937                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7938                         /*
7939                          * rss->level and rss.types should be set in advance
7940                          * when expanding items for RSS.
7941                          */
7942                         action_flags |= MLX5_FLOW_ACTION_RSS;
7943                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7944                         break;
7945                 case RTE_FLOW_ACTION_TYPE_AGE:
7946                 case RTE_FLOW_ACTION_TYPE_COUNT:
7947                         if (!dev_conf->devx) {
7948                                 return rte_flow_error_set
7949                                               (error, ENOTSUP,
7950                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7951                                                NULL,
7952                                                "count action not supported");
7953                         }
7954                         /* Save information first, will apply later. */
7955                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7956                                 count = action->conf;
7957                         else
7958                                 age = action->conf;
7959                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7960                         break;
7961                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7962                         dev_flow->dv.actions[actions_n++] =
7963                                                 priv->sh->pop_vlan_action;
7964                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7965                         break;
7966                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7967                         if (!(action_flags &
7968                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7969                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7970                         vlan.eth_proto = rte_be_to_cpu_16
7971                              ((((const struct rte_flow_action_of_push_vlan *)
7972                                                    actions->conf)->ethertype));
7973                         found_action = mlx5_flow_find_action
7974                                         (actions + 1,
7975                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7976                         if (found_action)
7977                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7978                         found_action = mlx5_flow_find_action
7979                                         (actions + 1,
7980                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7981                         if (found_action)
7982                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7983                         if (flow_dv_create_action_push_vlan
7984                                             (dev, attr, &vlan, dev_flow, error))
7985                                 return -rte_errno;
7986                         dev_flow->dv.actions[actions_n++] =
7987                                         dev_flow->dv.push_vlan_res->action;
7988                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7989                         break;
7990                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7991                         /* of_vlan_push action handled this action */
7992                         MLX5_ASSERT(action_flags &
7993                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7994                         break;
7995                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7996                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7997                                 break;
7998                         flow_dev_get_vlan_info_from_items(items, &vlan);
7999                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8000                         /* If no VLAN push - this is a modify header action */
8001                         if (flow_dv_convert_action_modify_vlan_vid
8002                                                 (mhdr_res, actions, error))
8003                                 return -rte_errno;
8004                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8005                         break;
8006                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8007                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8008                         if (flow_dv_create_action_l2_encap(dev, actions,
8009                                                            dev_flow,
8010                                                            attr->transfer,
8011                                                            error))
8012                                 return -rte_errno;
8013                         dev_flow->dv.actions[actions_n++] =
8014                                         dev_flow->dv.encap_decap->verbs_action;
8015                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8016                         break;
8017                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8018                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8019                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8020                                                            attr->transfer,
8021                                                            error))
8022                                 return -rte_errno;
8023                         dev_flow->dv.actions[actions_n++] =
8024                                         dev_flow->dv.encap_decap->verbs_action;
8025                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8026                         break;
8027                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8028                         /* Handle encap with preceding decap. */
8029                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8030                                 if (flow_dv_create_action_raw_encap
8031                                         (dev, actions, dev_flow, attr, error))
8032                                         return -rte_errno;
8033                                 dev_flow->dv.actions[actions_n++] =
8034                                         dev_flow->dv.encap_decap->verbs_action;
8035                         } else {
8036                                 /* Handle encap without preceding decap. */
8037                                 if (flow_dv_create_action_l2_encap
8038                                     (dev, actions, dev_flow, attr->transfer,
8039                                      error))
8040                                         return -rte_errno;
8041                                 dev_flow->dv.actions[actions_n++] =
8042                                         dev_flow->dv.encap_decap->verbs_action;
8043                         }
8044                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8045                         break;
8046                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8047                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8048                                 ;
8049                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8050                                 if (flow_dv_create_action_l2_decap
8051                                     (dev, dev_flow, attr->transfer, error))
8052                                         return -rte_errno;
8053                                 dev_flow->dv.actions[actions_n++] =
8054                                         dev_flow->dv.encap_decap->verbs_action;
8055                         }
8056                         /* If decap is followed by encap, handle it at encap. */
8057                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8058                         break;
8059                 case RTE_FLOW_ACTION_TYPE_JUMP:
8060                         jump_data = action->conf;
8061                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8062                                                        jump_data->group,
8063                                                        !!priv->fdb_def_rule,
8064                                                        &table, error);
8065                         if (ret)
8066                                 return ret;
8067                         tbl = flow_dv_tbl_resource_get(dev, table,
8068                                                        attr->egress,
8069                                                        attr->transfer, error);
8070                         if (!tbl)
8071                                 return rte_flow_error_set
8072                                                 (error, errno,
8073                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8074                                                  NULL,
8075                                                  "cannot create jump action.");
8076                         if (flow_dv_jump_tbl_resource_register
8077                             (dev, tbl, dev_flow, error)) {
8078                                 flow_dv_tbl_resource_release(dev, tbl);
8079                                 return rte_flow_error_set
8080                                                 (error, errno,
8081                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8082                                                  NULL,
8083                                                  "cannot create jump action.");
8084                         }
8085                         dev_flow->dv.actions[actions_n++] =
8086                                         dev_flow->dv.jump->action;
8087                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8088                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8089                         break;
8090                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8091                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8092                         if (flow_dv_convert_action_modify_mac
8093                                         (mhdr_res, actions, error))
8094                                 return -rte_errno;
8095                         action_flags |= actions->type ==
8096                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8097                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8098                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8099                         break;
8100                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8101                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8102                         if (flow_dv_convert_action_modify_ipv4
8103                                         (mhdr_res, actions, error))
8104                                 return -rte_errno;
8105                         action_flags |= actions->type ==
8106                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8107                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8108                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8109                         break;
8110                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8111                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8112                         if (flow_dv_convert_action_modify_ipv6
8113                                         (mhdr_res, actions, error))
8114                                 return -rte_errno;
8115                         action_flags |= actions->type ==
8116                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8117                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8118                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8119                         break;
8120                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8121                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8122                         if (flow_dv_convert_action_modify_tp
8123                                         (mhdr_res, actions, items,
8124                                          &flow_attr, dev_flow, !!(action_flags &
8125                                          MLX5_FLOW_ACTION_DECAP), error))
8126                                 return -rte_errno;
8127                         action_flags |= actions->type ==
8128                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8129                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8130                                         MLX5_FLOW_ACTION_SET_TP_DST;
8131                         break;
8132                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8133                         if (flow_dv_convert_action_modify_dec_ttl
8134                                         (mhdr_res, items, &flow_attr, dev_flow,
8135                                          !!(action_flags &
8136                                          MLX5_FLOW_ACTION_DECAP), error))
8137                                 return -rte_errno;
8138                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8139                         break;
8140                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8141                         if (flow_dv_convert_action_modify_ttl
8142                                         (mhdr_res, actions, items, &flow_attr,
8143                                          dev_flow, !!(action_flags &
8144                                          MLX5_FLOW_ACTION_DECAP), error))
8145                                 return -rte_errno;
8146                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8147                         break;
8148                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8149                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8150                         if (flow_dv_convert_action_modify_tcp_seq
8151                                         (mhdr_res, actions, error))
8152                                 return -rte_errno;
8153                         action_flags |= actions->type ==
8154                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8155                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8156                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8157                         break;
8158
8159                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8160                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8161                         if (flow_dv_convert_action_modify_tcp_ack
8162                                         (mhdr_res, actions, error))
8163                                 return -rte_errno;
8164                         action_flags |= actions->type ==
8165                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8166                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8167                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8168                         break;
8169                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8170                         if (flow_dv_convert_action_set_reg
8171                                         (mhdr_res, actions, error))
8172                                 return -rte_errno;
8173                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8174                         break;
8175                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8176                         if (flow_dv_convert_action_copy_mreg
8177                                         (dev, mhdr_res, actions, error))
8178                                 return -rte_errno;
8179                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8180                         break;
8181                 case RTE_FLOW_ACTION_TYPE_METER:
8182                         mtr = actions->conf;
8183                         if (!flow->meter) {
8184                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8185                                                             attr, error);
8186                                 if (!fm)
8187                                         return rte_flow_error_set(error,
8188                                                 rte_errno,
8189                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8190                                                 NULL,
8191                                                 "meter not found "
8192                                                 "or invalid parameters");
8193                                 flow->meter = fm->idx;
8194                         }
8195                         /* Set the meter action. */
8196                         if (!fm) {
8197                                 fm = mlx5_ipool_get(priv->sh->ipool
8198                                                 [MLX5_IPOOL_MTR], flow->meter);
8199                                 if (!fm)
8200                                         return rte_flow_error_set(error,
8201                                                 rte_errno,
8202                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8203                                                 NULL,
8204                                                 "meter not found "
8205                                                 "or invalid parameters");
8206                         }
8207                         dev_flow->dv.actions[actions_n++] =
8208                                 fm->mfts->meter_action;
8209                         action_flags |= MLX5_FLOW_ACTION_METER;
8210                         break;
8211                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8212                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8213                                                               actions, error))
8214                                 return -rte_errno;
8215                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8216                         break;
8217                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8218                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8219                                                               actions, error))
8220                                 return -rte_errno;
8221                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8222                         break;
8223                 case RTE_FLOW_ACTION_TYPE_END:
8224                         actions_end = true;
8225                         if (mhdr_res->actions_num) {
8226                                 /* create modify action if needed. */
8227                                 if (flow_dv_modify_hdr_resource_register
8228                                         (dev, mhdr_res, dev_flow, error))
8229                                         return -rte_errno;
8230                                 dev_flow->dv.actions[modify_action_position] =
8231                                         handle->dvh.modify_hdr->verbs_action;
8232                         }
8233                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8234                                 flow->counter =
8235                                         flow_dv_translate_create_counter(dev,
8236                                                 dev_flow, count, age);
8237
8238                                 if (!flow->counter)
8239                                         return rte_flow_error_set
8240                                                 (error, rte_errno,
8241                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8242                                                 NULL,
8243                                                 "cannot create counter"
8244                                                 " object.");
8245                                 dev_flow->dv.actions[actions_n++] =
8246                                           (flow_dv_counter_get_by_idx(dev,
8247                                           flow->counter, NULL))->action;
8248                         }
8249                         break;
8250                 default:
8251                         break;
8252                 }
8253                 if (mhdr_res->actions_num &&
8254                     modify_action_position == UINT32_MAX)
8255                         modify_action_position = actions_n++;
8256         }
8257         dev_flow->dv.actions_n = actions_n;
8258         dev_flow->act_flags = action_flags;
8259         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8260                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8261                 int item_type = items->type;
8262
8263                 switch (item_type) {
8264                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8265                         flow_dv_translate_item_port_id(dev, match_mask,
8266                                                        match_value, items);
8267                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8268                         break;
8269                 case RTE_FLOW_ITEM_TYPE_ETH:
8270                         flow_dv_translate_item_eth(match_mask, match_value,
8271                                                    items, tunnel,
8272                                                    dev_flow->dv.group);
8273                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8274                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8275                                              MLX5_FLOW_LAYER_OUTER_L2;
8276                         break;
8277                 case RTE_FLOW_ITEM_TYPE_VLAN:
8278                         flow_dv_translate_item_vlan(dev_flow,
8279                                                     match_mask, match_value,
8280                                                     items, tunnel,
8281                                                     dev_flow->dv.group);
8282                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8283                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8284                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8285                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8286                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8287                         break;
8288                 case RTE_FLOW_ITEM_TYPE_IPV4:
8289                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8290                                                   &item_flags, &tunnel);
8291                         flow_dv_translate_item_ipv4(match_mask, match_value,
8292                                                     items, item_flags, tunnel,
8293                                                     dev_flow->dv.group);
8294                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8295                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8296                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8297                         if (items->mask != NULL &&
8298                             ((const struct rte_flow_item_ipv4 *)
8299                              items->mask)->hdr.next_proto_id) {
8300                                 next_protocol =
8301                                         ((const struct rte_flow_item_ipv4 *)
8302                                          (items->spec))->hdr.next_proto_id;
8303                                 next_protocol &=
8304                                         ((const struct rte_flow_item_ipv4 *)
8305                                          (items->mask))->hdr.next_proto_id;
8306                         } else {
8307                                 /* Reset for inner layer. */
8308                                 next_protocol = 0xff;
8309                         }
8310                         break;
8311                 case RTE_FLOW_ITEM_TYPE_IPV6:
8312                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8313                                                   &item_flags, &tunnel);
8314                         flow_dv_translate_item_ipv6(match_mask, match_value,
8315                                                     items, item_flags, tunnel,
8316                                                     dev_flow->dv.group);
8317                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8318                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8319                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8320                         if (items->mask != NULL &&
8321                             ((const struct rte_flow_item_ipv6 *)
8322                              items->mask)->hdr.proto) {
8323                                 next_protocol =
8324                                         ((const struct rte_flow_item_ipv6 *)
8325                                          items->spec)->hdr.proto;
8326                                 next_protocol &=
8327                                         ((const struct rte_flow_item_ipv6 *)
8328                                          items->mask)->hdr.proto;
8329                         } else {
8330                                 /* Reset for inner layer. */
8331                                 next_protocol = 0xff;
8332                         }
8333                         break;
8334                 case RTE_FLOW_ITEM_TYPE_TCP:
8335                         flow_dv_translate_item_tcp(match_mask, match_value,
8336                                                    items, tunnel);
8337                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8338                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8339                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8340                         break;
8341                 case RTE_FLOW_ITEM_TYPE_UDP:
8342                         flow_dv_translate_item_udp(match_mask, match_value,
8343                                                    items, tunnel);
8344                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8345                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8346                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8347                         break;
8348                 case RTE_FLOW_ITEM_TYPE_GRE:
8349                         flow_dv_translate_item_gre(match_mask, match_value,
8350                                                    items, tunnel);
8351                         matcher.priority = rss_desc->level >= 2 ?
8352                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8353                         last_item = MLX5_FLOW_LAYER_GRE;
8354                         break;
8355                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8356                         flow_dv_translate_item_gre_key(match_mask,
8357                                                        match_value, items);
8358                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8359                         break;
8360                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8361                         flow_dv_translate_item_nvgre(match_mask, match_value,
8362                                                      items, tunnel);
8363                         matcher.priority = rss_desc->level >= 2 ?
8364                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8365                         last_item = MLX5_FLOW_LAYER_GRE;
8366                         break;
8367                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8368                         flow_dv_translate_item_vxlan(match_mask, match_value,
8369                                                      items, tunnel);
8370                         matcher.priority = rss_desc->level >= 2 ?
8371                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8372                         last_item = MLX5_FLOW_LAYER_VXLAN;
8373                         break;
8374                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8375                         flow_dv_translate_item_vxlan_gpe(match_mask,
8376                                                          match_value, items,
8377                                                          tunnel);
8378                         matcher.priority = rss_desc->level >= 2 ?
8379                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8380                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8381                         break;
8382                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8383                         flow_dv_translate_item_geneve(match_mask, match_value,
8384                                                       items, tunnel);
8385                         matcher.priority = rss_desc->level >= 2 ?
8386                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8387                         last_item = MLX5_FLOW_LAYER_GENEVE;
8388                         break;
8389                 case RTE_FLOW_ITEM_TYPE_MPLS:
8390                         flow_dv_translate_item_mpls(match_mask, match_value,
8391                                                     items, last_item, tunnel);
8392                         matcher.priority = rss_desc->level >= 2 ?
8393                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8394                         last_item = MLX5_FLOW_LAYER_MPLS;
8395                         break;
8396                 case RTE_FLOW_ITEM_TYPE_MARK:
8397                         flow_dv_translate_item_mark(dev, match_mask,
8398                                                     match_value, items);
8399                         last_item = MLX5_FLOW_ITEM_MARK;
8400                         break;
8401                 case RTE_FLOW_ITEM_TYPE_META:
8402                         flow_dv_translate_item_meta(dev, match_mask,
8403                                                     match_value, attr, items);
8404                         last_item = MLX5_FLOW_ITEM_METADATA;
8405                         break;
8406                 case RTE_FLOW_ITEM_TYPE_ICMP:
8407                         flow_dv_translate_item_icmp(match_mask, match_value,
8408                                                     items, tunnel);
8409                         last_item = MLX5_FLOW_LAYER_ICMP;
8410                         break;
8411                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8412                         flow_dv_translate_item_icmp6(match_mask, match_value,
8413                                                       items, tunnel);
8414                         last_item = MLX5_FLOW_LAYER_ICMP6;
8415                         break;
8416                 case RTE_FLOW_ITEM_TYPE_TAG:
8417                         flow_dv_translate_item_tag(dev, match_mask,
8418                                                    match_value, items);
8419                         last_item = MLX5_FLOW_ITEM_TAG;
8420                         break;
8421                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8422                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8423                                                         match_value, items);
8424                         last_item = MLX5_FLOW_ITEM_TAG;
8425                         break;
8426                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8427                         flow_dv_translate_item_tx_queue(dev, match_mask,
8428                                                         match_value,
8429                                                         items);
8430                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8431                         break;
8432                 case RTE_FLOW_ITEM_TYPE_GTP:
8433                         flow_dv_translate_item_gtp(match_mask, match_value,
8434                                                    items, tunnel);
8435                         matcher.priority = rss_desc->level >= 2 ?
8436                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8437                         last_item = MLX5_FLOW_LAYER_GTP;
8438                         break;
8439                 default:
8440                         break;
8441                 }
8442                 item_flags |= last_item;
8443         }
8444         /*
8445          * When E-Switch mode is enabled, we have two cases where we need to
8446          * set the source port manually.
8447          * The first one, is in case of Nic steering rule, and the second is
8448          * E-Switch rule where no port_id item was found. In both cases
8449          * the source port is set according the current port in use.
8450          */
8451         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8452             (priv->representor || priv->master)) {
8453                 if (flow_dv_translate_item_port_id(dev, match_mask,
8454                                                    match_value, NULL))
8455                         return -rte_errno;
8456         }
8457 #ifdef RTE_LIBRTE_MLX5_DEBUG
8458         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8459                                               dev_flow->dv.value.buf));
8460 #endif
8461         /*
8462          * Layers may be already initialized from prefix flow if this dev_flow
8463          * is the suffix flow.
8464          */
8465         handle->layers |= item_flags;
8466         if (action_flags & MLX5_FLOW_ACTION_RSS)
8467                 flow_dv_hashfields_set(dev_flow, rss_desc);
8468         /* Register matcher. */
8469         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8470                                     matcher.mask.size);
8471         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8472                                                      matcher.priority);
8473         /* reserved field no needs to be set to 0 here. */
8474         tbl_key.domain = attr->transfer;
8475         tbl_key.direction = attr->egress;
8476         tbl_key.table_id = dev_flow->dv.group;
8477         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8478                 return -rte_errno;
8479         return 0;
8480 }
8481
8482 /**
8483  * Apply the flow to the NIC, lock free,
8484  * (mutex should be acquired by caller).
8485  *
8486  * @param[in] dev
8487  *   Pointer to the Ethernet device structure.
8488  * @param[in, out] flow
8489  *   Pointer to flow structure.
8490  * @param[out] error
8491  *   Pointer to error structure.
8492  *
8493  * @return
8494  *   0 on success, a negative errno value otherwise and rte_errno is set.
8495  */
8496 static int
8497 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8498                 struct rte_flow_error *error)
8499 {
8500         struct mlx5_flow_dv_workspace *dv;
8501         struct mlx5_flow_handle *dh;
8502         struct mlx5_flow_handle_dv *dv_h;
8503         struct mlx5_flow *dev_flow;
8504         struct mlx5_priv *priv = dev->data->dev_private;
8505         uint32_t handle_idx;
8506         int n;
8507         int err;
8508         int idx;
8509
8510         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8511                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8512                 dv = &dev_flow->dv;
8513                 dh = dev_flow->handle;
8514                 dv_h = &dh->dvh;
8515                 n = dv->actions_n;
8516                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8517                         if (dv->transfer) {
8518                                 dv->actions[n++] = priv->sh->esw_drop_action;
8519                         } else {
8520                                 struct mlx5_hrxq *drop_hrxq;
8521                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8522                                 if (!drop_hrxq) {
8523                                         rte_flow_error_set
8524                                                 (error, errno,
8525                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8526                                                  NULL,
8527                                                  "cannot get drop hash queue");
8528                                         goto error;
8529                                 }
8530                                 /*
8531                                  * Drop queues will be released by the specify
8532                                  * mlx5_hrxq_drop_release() function. Assign
8533                                  * the special index to hrxq to mark the queue
8534                                  * has been allocated.
8535                                  */
8536                                 dh->rix_hrxq = UINT32_MAX;
8537                                 dv->actions[n++] = drop_hrxq->action;
8538                         }
8539                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8540                         struct mlx5_hrxq *hrxq;
8541                         uint32_t hrxq_idx;
8542                         struct mlx5_flow_rss_desc *rss_desc =
8543                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8544                                 [!!priv->flow_nested_idx];
8545
8546                         MLX5_ASSERT(rss_desc->queue_num);
8547                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8548                                                  MLX5_RSS_HASH_KEY_LEN,
8549                                                  dev_flow->hash_fields,
8550                                                  rss_desc->queue,
8551                                                  rss_desc->queue_num);
8552                         if (!hrxq_idx) {
8553                                 hrxq_idx = mlx5_hrxq_new
8554                                                 (dev, rss_desc->key,
8555                                                 MLX5_RSS_HASH_KEY_LEN,
8556                                                 dev_flow->hash_fields,
8557                                                 rss_desc->queue,
8558                                                 rss_desc->queue_num,
8559                                                 !!(dh->layers &
8560                                                 MLX5_FLOW_LAYER_TUNNEL));
8561                         }
8562                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8563                                               hrxq_idx);
8564                         if (!hrxq) {
8565                                 rte_flow_error_set
8566                                         (error, rte_errno,
8567                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8568                                          "cannot get hash queue");
8569                                 goto error;
8570                         }
8571                         dh->rix_hrxq = hrxq_idx;
8572                         dv->actions[n++] = hrxq->action;
8573                 }
8574                 dh->ib_flow =
8575                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8576                                                   (void *)&dv->value, n,
8577                                                   dv->actions);
8578                 if (!dh->ib_flow) {
8579                         rte_flow_error_set(error, errno,
8580                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8581                                            NULL,
8582                                            "hardware refuses to create flow");
8583                         goto error;
8584                 }
8585                 if (priv->vmwa_context &&
8586                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8587                         /*
8588                          * The rule contains the VLAN pattern.
8589                          * For VF we are going to create VLAN
8590                          * interface to make hypervisor set correct
8591                          * e-Switch vport context.
8592                          */
8593                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8594                 }
8595         }
8596         return 0;
8597 error:
8598         err = rte_errno; /* Save rte_errno before cleanup. */
8599         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8600                        handle_idx, dh, next) {
8601                 /* hrxq is union, don't clear it if the flag is not set. */
8602                 if (dh->rix_hrxq) {
8603                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8604                                 mlx5_hrxq_drop_release(dev);
8605                                 dh->rix_hrxq = 0;
8606                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8607                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8608                                 dh->rix_hrxq = 0;
8609                         }
8610                 }
8611                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8612                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8613         }
8614         rte_errno = err; /* Restore rte_errno. */
8615         return -rte_errno;
8616 }
8617
8618 /**
8619  * Release the flow matcher.
8620  *
8621  * @param dev
8622  *   Pointer to Ethernet device.
8623  * @param handle
8624  *   Pointer to mlx5_flow_handle.
8625  *
8626  * @return
8627  *   1 while a reference on it exists, 0 when freed.
8628  */
8629 static int
8630 flow_dv_matcher_release(struct rte_eth_dev *dev,
8631                         struct mlx5_flow_handle *handle)
8632 {
8633         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8634
8635         MLX5_ASSERT(matcher->matcher_object);
8636         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8637                 dev->data->port_id, (void *)matcher,
8638                 rte_atomic32_read(&matcher->refcnt));
8639         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8640                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8641                            (matcher->matcher_object));
8642                 LIST_REMOVE(matcher, next);
8643                 /* table ref-- in release interface. */
8644                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8645                 rte_free(matcher);
8646                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8647                         dev->data->port_id, (void *)matcher);
8648                 return 0;
8649         }
8650         return 1;
8651 }
8652
8653 /**
8654  * Release an encap/decap resource.
8655  *
8656  * @param dev
8657  *   Pointer to Ethernet device.
8658  * @param handle
8659  *   Pointer to mlx5_flow_handle.
8660  *
8661  * @return
8662  *   1 while a reference on it exists, 0 when freed.
8663  */
8664 static int
8665 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8666                                      struct mlx5_flow_handle *handle)
8667 {
8668         struct mlx5_priv *priv = dev->data->dev_private;
8669         uint32_t idx = handle->dvh.rix_encap_decap;
8670         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8671
8672         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8673                          idx);
8674         if (!cache_resource)
8675                 return 0;
8676         MLX5_ASSERT(cache_resource->verbs_action);
8677         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8678                 (void *)cache_resource,
8679                 rte_atomic32_read(&cache_resource->refcnt));
8680         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8681                 claim_zero(mlx5_glue->destroy_flow_action
8682                                 (cache_resource->verbs_action));
8683                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8684                              &priv->sh->encaps_decaps, idx,
8685                              cache_resource, next);
8686                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8687                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8688                         (void *)cache_resource);
8689                 return 0;
8690         }
8691         return 1;
8692 }
8693
8694 /**
8695  * Release an jump to table action resource.
8696  *
8697  * @param dev
8698  *   Pointer to Ethernet device.
8699  * @param handle
8700  *   Pointer to mlx5_flow_handle.
8701  *
8702  * @return
8703  *   1 while a reference on it exists, 0 when freed.
8704  */
8705 static int
8706 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8707                                   struct mlx5_flow_handle *handle)
8708 {
8709         struct mlx5_priv *priv = dev->data->dev_private;
8710         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8711         struct mlx5_flow_tbl_data_entry *tbl_data;
8712
8713         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8714                              handle->rix_jump);
8715         if (!tbl_data)
8716                 return 0;
8717         cache_resource = &tbl_data->jump;
8718         MLX5_ASSERT(cache_resource->action);
8719         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8720                 (void *)cache_resource,
8721                 rte_atomic32_read(&cache_resource->refcnt));
8722         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8723                 claim_zero(mlx5_glue->destroy_flow_action
8724                                 (cache_resource->action));
8725                 /* jump action memory free is inside the table release. */
8726                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8727                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8728                         (void *)cache_resource);
8729                 return 0;
8730         }
8731         return 1;
8732 }
8733
8734 /**
8735  * Release a modify-header resource.
8736  *
8737  * @param handle
8738  *   Pointer to mlx5_flow_handle.
8739  *
8740  * @return
8741  *   1 while a reference on it exists, 0 when freed.
8742  */
8743 static int
8744 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8745 {
8746         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8747                                                         handle->dvh.modify_hdr;
8748
8749         MLX5_ASSERT(cache_resource->verbs_action);
8750         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8751                 (void *)cache_resource,
8752                 rte_atomic32_read(&cache_resource->refcnt));
8753         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8754                 claim_zero(mlx5_glue->destroy_flow_action
8755                                 (cache_resource->verbs_action));
8756                 LIST_REMOVE(cache_resource, next);
8757                 rte_free(cache_resource);
8758                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8759                         (void *)cache_resource);
8760                 return 0;
8761         }
8762         return 1;
8763 }
8764
8765 /**
8766  * Release port ID action resource.
8767  *
8768  * @param dev
8769  *   Pointer to Ethernet device.
8770  * @param handle
8771  *   Pointer to mlx5_flow_handle.
8772  *
8773  * @return
8774  *   1 while a reference on it exists, 0 when freed.
8775  */
8776 static int
8777 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8778                                         struct mlx5_flow_handle *handle)
8779 {
8780         struct mlx5_priv *priv = dev->data->dev_private;
8781         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8782         uint32_t idx = handle->rix_port_id_action;
8783
8784         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8785                                         idx);
8786         if (!cache_resource)
8787                 return 0;
8788         MLX5_ASSERT(cache_resource->action);
8789         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8790                 (void *)cache_resource,
8791                 rte_atomic32_read(&cache_resource->refcnt));
8792         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8793                 claim_zero(mlx5_glue->destroy_flow_action
8794                                 (cache_resource->action));
8795                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8796                              &priv->sh->port_id_action_list, idx,
8797                              cache_resource, next);
8798                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8799                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8800                         (void *)cache_resource);
8801                 return 0;
8802         }
8803         return 1;
8804 }
8805
8806 /**
8807  * Release push vlan action resource.
8808  *
8809  * @param dev
8810  *   Pointer to Ethernet device.
8811  * @param handle
8812  *   Pointer to mlx5_flow_handle.
8813  *
8814  * @return
8815  *   1 while a reference on it exists, 0 when freed.
8816  */
8817 static int
8818 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8819                                           struct mlx5_flow_handle *handle)
8820 {
8821         struct mlx5_priv *priv = dev->data->dev_private;
8822         uint32_t idx = handle->dvh.rix_push_vlan;
8823         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8824
8825         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8826                                         idx);
8827         if (!cache_resource)
8828                 return 0;
8829         MLX5_ASSERT(cache_resource->action);
8830         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8831                 (void *)cache_resource,
8832                 rte_atomic32_read(&cache_resource->refcnt));
8833         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8834                 claim_zero(mlx5_glue->destroy_flow_action
8835                                 (cache_resource->action));
8836                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8837                              &priv->sh->push_vlan_action_list, idx,
8838                              cache_resource, next);
8839                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8840                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8841                         (void *)cache_resource);
8842                 return 0;
8843         }
8844         return 1;
8845 }
8846
8847 /**
8848  * Release the fate resource.
8849  *
8850  * @param dev
8851  *   Pointer to Ethernet device.
8852  * @param handle
8853  *   Pointer to mlx5_flow_handle.
8854  */
8855 static void
8856 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8857                                struct mlx5_flow_handle *handle)
8858 {
8859         if (!handle->rix_fate)
8860                 return;
8861         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8862                 mlx5_hrxq_drop_release(dev);
8863         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8864                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8865         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8866                 flow_dv_jump_tbl_resource_release(dev, handle);
8867         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8868                 flow_dv_port_id_action_resource_release(dev, handle);
8869         else
8870                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8871         handle->rix_fate = 0;
8872 }
8873
8874 /**
8875  * Remove the flow from the NIC but keeps it in memory.
8876  * Lock free, (mutex should be acquired by caller).
8877  *
8878  * @param[in] dev
8879  *   Pointer to Ethernet device.
8880  * @param[in, out] flow
8881  *   Pointer to flow structure.
8882  */
8883 static void
8884 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8885 {
8886         struct mlx5_flow_handle *dh;
8887         uint32_t handle_idx;
8888         struct mlx5_priv *priv = dev->data->dev_private;
8889
8890         if (!flow)
8891                 return;
8892         handle_idx = flow->dev_handles;
8893         while (handle_idx) {
8894                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8895                                     handle_idx);
8896                 if (!dh)
8897                         return;
8898                 if (dh->ib_flow) {
8899                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8900                         dh->ib_flow = NULL;
8901                 }
8902                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8903                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8904                         flow_dv_fate_resource_release(dev, dh);
8905                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8906                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8907                 handle_idx = dh->next.next;
8908         }
8909 }
8910
8911 /**
8912  * Remove the flow from the NIC and the memory.
8913  * Lock free, (mutex should be acquired by caller).
8914  *
8915  * @param[in] dev
8916  *   Pointer to the Ethernet device structure.
8917  * @param[in, out] flow
8918  *   Pointer to flow structure.
8919  */
8920 static void
8921 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8922 {
8923         struct mlx5_flow_handle *dev_handle;
8924         struct mlx5_priv *priv = dev->data->dev_private;
8925
8926         if (!flow)
8927                 return;
8928         __flow_dv_remove(dev, flow);
8929         if (flow->counter) {
8930                 flow_dv_counter_release(dev, flow->counter);
8931                 flow->counter = 0;
8932         }
8933         if (flow->meter) {
8934                 struct mlx5_flow_meter *fm;
8935
8936                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8937                                     flow->meter);
8938                 if (fm)
8939                         mlx5_flow_meter_detach(fm);
8940                 flow->meter = 0;
8941         }
8942         while (flow->dev_handles) {
8943                 uint32_t tmp_idx = flow->dev_handles;
8944
8945                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8946                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8947                 if (!dev_handle)
8948                         return;
8949                 flow->dev_handles = dev_handle->next.next;
8950                 if (dev_handle->dvh.matcher)
8951                         flow_dv_matcher_release(dev, dev_handle);
8952                 if (dev_handle->dvh.rix_encap_decap)
8953                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8954                 if (dev_handle->dvh.modify_hdr)
8955                         flow_dv_modify_hdr_resource_release(dev_handle);
8956                 if (dev_handle->dvh.rix_push_vlan)
8957                         flow_dv_push_vlan_action_resource_release(dev,
8958                                                                   dev_handle);
8959                 if (dev_handle->dvh.rix_tag)
8960                         flow_dv_tag_release(dev,
8961                                             dev_handle->dvh.rix_tag);
8962                 flow_dv_fate_resource_release(dev, dev_handle);
8963                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8964                            tmp_idx);
8965         }
8966 }
8967
8968 /**
8969  * Query a dv flow  rule for its statistics via devx.
8970  *
8971  * @param[in] dev
8972  *   Pointer to Ethernet device.
8973  * @param[in] flow
8974  *   Pointer to the sub flow.
8975  * @param[out] data
8976  *   data retrieved by the query.
8977  * @param[out] error
8978  *   Perform verbose error reporting if not NULL.
8979  *
8980  * @return
8981  *   0 on success, a negative errno value otherwise and rte_errno is set.
8982  */
8983 static int
8984 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8985                     void *data, struct rte_flow_error *error)
8986 {
8987         struct mlx5_priv *priv = dev->data->dev_private;
8988         struct rte_flow_query_count *qc = data;
8989
8990         if (!priv->config.devx)
8991                 return rte_flow_error_set(error, ENOTSUP,
8992                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8993                                           NULL,
8994                                           "counters are not supported");
8995         if (flow->counter) {
8996                 uint64_t pkts, bytes;
8997                 struct mlx5_flow_counter *cnt;
8998
8999                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9000                                                  NULL);
9001                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9002                                                &bytes);
9003
9004                 if (err)
9005                         return rte_flow_error_set(error, -err,
9006                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9007                                         NULL, "cannot read counters");
9008                 qc->hits_set = 1;
9009                 qc->bytes_set = 1;
9010                 qc->hits = pkts - cnt->hits;
9011                 qc->bytes = bytes - cnt->bytes;
9012                 if (qc->reset) {
9013                         cnt->hits = pkts;
9014                         cnt->bytes = bytes;
9015                 }
9016                 return 0;
9017         }
9018         return rte_flow_error_set(error, EINVAL,
9019                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9020                                   NULL,
9021                                   "counters are not available");
9022 }
9023
9024 /**
9025  * Query a flow.
9026  *
9027  * @see rte_flow_query()
9028  * @see rte_flow_ops
9029  */
9030 static int
9031 flow_dv_query(struct rte_eth_dev *dev,
9032               struct rte_flow *flow __rte_unused,
9033               const struct rte_flow_action *actions __rte_unused,
9034               void *data __rte_unused,
9035               struct rte_flow_error *error __rte_unused)
9036 {
9037         int ret = -EINVAL;
9038
9039         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9040                 switch (actions->type) {
9041                 case RTE_FLOW_ACTION_TYPE_VOID:
9042                         break;
9043                 case RTE_FLOW_ACTION_TYPE_COUNT:
9044                         ret = flow_dv_query_count(dev, flow, data, error);
9045                         break;
9046                 default:
9047                         return rte_flow_error_set(error, ENOTSUP,
9048                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9049                                                   actions,
9050                                                   "action not supported");
9051                 }
9052         }
9053         return ret;
9054 }
9055
9056 /**
9057  * Destroy the meter table set.
9058  * Lock free, (mutex should be acquired by caller).
9059  *
9060  * @param[in] dev
9061  *   Pointer to Ethernet device.
9062  * @param[in] tbl
9063  *   Pointer to the meter table set.
9064  *
9065  * @return
9066  *   Always 0.
9067  */
9068 static int
9069 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9070                         struct mlx5_meter_domains_infos *tbl)
9071 {
9072         struct mlx5_priv *priv = dev->data->dev_private;
9073         struct mlx5_meter_domains_infos *mtd =
9074                                 (struct mlx5_meter_domains_infos *)tbl;
9075
9076         if (!mtd || !priv->config.dv_flow_en)
9077                 return 0;
9078         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9079                 claim_zero(mlx5_glue->dv_destroy_flow
9080                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9081         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9082                 claim_zero(mlx5_glue->dv_destroy_flow
9083                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9084         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9085                 claim_zero(mlx5_glue->dv_destroy_flow
9086                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9087         if (mtd->egress.color_matcher)
9088                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9089                           (mtd->egress.color_matcher));
9090         if (mtd->egress.any_matcher)
9091                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9092                           (mtd->egress.any_matcher));
9093         if (mtd->egress.tbl)
9094                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9095         if (mtd->egress.sfx_tbl)
9096                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9097         if (mtd->ingress.color_matcher)
9098                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9099                           (mtd->ingress.color_matcher));
9100         if (mtd->ingress.any_matcher)
9101                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9102                           (mtd->ingress.any_matcher));
9103         if (mtd->ingress.tbl)
9104                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9105         if (mtd->ingress.sfx_tbl)
9106                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9107         if (mtd->transfer.color_matcher)
9108                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9109                           (mtd->transfer.color_matcher));
9110         if (mtd->transfer.any_matcher)
9111                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9112                           (mtd->transfer.any_matcher));
9113         if (mtd->transfer.tbl)
9114                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9115         if (mtd->transfer.sfx_tbl)
9116                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9117         if (mtd->drop_actn)
9118                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9119         rte_free(mtd);
9120         return 0;
9121 }
9122
9123 /* Number of meter flow actions, count and jump or count and drop. */
9124 #define METER_ACTIONS 2
9125
9126 /**
9127  * Create specify domain meter table and suffix table.
9128  *
9129  * @param[in] dev
9130  *   Pointer to Ethernet device.
9131  * @param[in,out] mtb
9132  *   Pointer to DV meter table set.
9133  * @param[in] egress
9134  *   Table attribute.
9135  * @param[in] transfer
9136  *   Table attribute.
9137  * @param[in] color_reg_c_idx
9138  *   Reg C index for color match.
9139  *
9140  * @return
9141  *   0 on success, -1 otherwise and rte_errno is set.
9142  */
9143 static int
9144 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9145                            struct mlx5_meter_domains_infos *mtb,
9146                            uint8_t egress, uint8_t transfer,
9147                            uint32_t color_reg_c_idx)
9148 {
9149         struct mlx5_priv *priv = dev->data->dev_private;
9150         struct mlx5_dev_ctx_shared *sh = priv->sh;
9151         struct mlx5_flow_dv_match_params mask = {
9152                 .size = sizeof(mask.buf),
9153         };
9154         struct mlx5_flow_dv_match_params value = {
9155                 .size = sizeof(value.buf),
9156         };
9157         struct mlx5dv_flow_matcher_attr dv_attr = {
9158                 .type = IBV_FLOW_ATTR_NORMAL,
9159                 .priority = 0,
9160                 .match_criteria_enable = 0,
9161                 .match_mask = (void *)&mask,
9162         };
9163         void *actions[METER_ACTIONS];
9164         struct mlx5_meter_domain_info *dtb;
9165         struct rte_flow_error error;
9166         int i = 0;
9167
9168         if (transfer)
9169                 dtb = &mtb->transfer;
9170         else if (egress)
9171                 dtb = &mtb->egress;
9172         else
9173                 dtb = &mtb->ingress;
9174         /* Create the meter table with METER level. */
9175         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9176                                             egress, transfer, &error);
9177         if (!dtb->tbl) {
9178                 DRV_LOG(ERR, "Failed to create meter policer table.");
9179                 return -1;
9180         }
9181         /* Create the meter suffix table with SUFFIX level. */
9182         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9183                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9184                                             egress, transfer, &error);
9185         if (!dtb->sfx_tbl) {
9186                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9187                 return -1;
9188         }
9189         /* Create matchers, Any and Color. */
9190         dv_attr.priority = 3;
9191         dv_attr.match_criteria_enable = 0;
9192         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9193                                                              &dv_attr,
9194                                                              dtb->tbl->obj);
9195         if (!dtb->any_matcher) {
9196                 DRV_LOG(ERR, "Failed to create meter"
9197                              " policer default matcher.");
9198                 goto error_exit;
9199         }
9200         dv_attr.priority = 0;
9201         dv_attr.match_criteria_enable =
9202                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9203         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9204                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9205         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9206                                                                &dv_attr,
9207                                                                dtb->tbl->obj);
9208         if (!dtb->color_matcher) {
9209                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9210                 goto error_exit;
9211         }
9212         if (mtb->count_actns[RTE_MTR_DROPPED])
9213                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9214         actions[i++] = mtb->drop_actn;
9215         /* Default rule: lowest priority, match any, actions: drop. */
9216         dtb->policer_rules[RTE_MTR_DROPPED] =
9217                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9218                                                  (void *)&value, i, actions);
9219         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9220                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9221                 goto error_exit;
9222         }
9223         return 0;
9224 error_exit:
9225         return -1;
9226 }
9227
9228 /**
9229  * Create the needed meter and suffix tables.
9230  * Lock free, (mutex should be acquired by caller).
9231  *
9232  * @param[in] dev
9233  *   Pointer to Ethernet device.
9234  * @param[in] fm
9235  *   Pointer to the flow meter.
9236  *
9237  * @return
9238  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9239  */
9240 static struct mlx5_meter_domains_infos *
9241 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9242                        const struct mlx5_flow_meter *fm)
9243 {
9244         struct mlx5_priv *priv = dev->data->dev_private;
9245         struct mlx5_meter_domains_infos *mtb;
9246         int ret;
9247         int i;
9248
9249         if (!priv->mtr_en) {
9250                 rte_errno = ENOTSUP;
9251                 return NULL;
9252         }
9253         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9254         if (!mtb) {
9255                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9256                 return NULL;
9257         }
9258         /* Create meter count actions */
9259         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9260                 struct mlx5_flow_counter *cnt;
9261                 if (!fm->policer_stats.cnt[i])
9262                         continue;
9263                 cnt = flow_dv_counter_get_by_idx(dev,
9264                       fm->policer_stats.cnt[i], NULL);
9265                 mtb->count_actns[i] = cnt->action;
9266         }
9267         /* Create drop action. */
9268         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9269         if (!mtb->drop_actn) {
9270                 DRV_LOG(ERR, "Failed to create drop action.");
9271                 goto error_exit;
9272         }
9273         /* Egress meter table. */
9274         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9275         if (ret) {
9276                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9277                 goto error_exit;
9278         }
9279         /* Ingress meter table. */
9280         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9281         if (ret) {
9282                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9283                 goto error_exit;
9284         }
9285         /* FDB meter table. */
9286         if (priv->config.dv_esw_en) {
9287                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9288                                                  priv->mtr_color_reg);
9289                 if (ret) {
9290                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9291                         goto error_exit;
9292                 }
9293         }
9294         return mtb;
9295 error_exit:
9296         flow_dv_destroy_mtr_tbl(dev, mtb);
9297         return NULL;
9298 }
9299
9300 /**
9301  * Destroy domain policer rule.
9302  *
9303  * @param[in] dt
9304  *   Pointer to domain table.
9305  */
9306 static void
9307 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9308 {
9309         int i;
9310
9311         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9312                 if (dt->policer_rules[i]) {
9313                         claim_zero(mlx5_glue->dv_destroy_flow
9314                                   (dt->policer_rules[i]));
9315                         dt->policer_rules[i] = NULL;
9316                 }
9317         }
9318         if (dt->jump_actn) {
9319                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9320                 dt->jump_actn = NULL;
9321         }
9322 }
9323
9324 /**
9325  * Destroy policer rules.
9326  *
9327  * @param[in] dev
9328  *   Pointer to Ethernet device.
9329  * @param[in] fm
9330  *   Pointer to flow meter structure.
9331  * @param[in] attr
9332  *   Pointer to flow attributes.
9333  *
9334  * @return
9335  *   Always 0.
9336  */
9337 static int
9338 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9339                               const struct mlx5_flow_meter *fm,
9340                               const struct rte_flow_attr *attr)
9341 {
9342         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9343
9344         if (!mtb)
9345                 return 0;
9346         if (attr->egress)
9347                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9348         if (attr->ingress)
9349                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9350         if (attr->transfer)
9351                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9352         return 0;
9353 }
9354
9355 /**
9356  * Create specify domain meter policer rule.
9357  *
9358  * @param[in] fm
9359  *   Pointer to flow meter structure.
9360  * @param[in] mtb
9361  *   Pointer to DV meter table set.
9362  * @param[in] mtr_reg_c
9363  *   Color match REG_C.
9364  *
9365  * @return
9366  *   0 on success, -1 otherwise.
9367  */
9368 static int
9369 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9370                                     struct mlx5_meter_domain_info *dtb,
9371                                     uint8_t mtr_reg_c)
9372 {
9373         struct mlx5_flow_dv_match_params matcher = {
9374                 .size = sizeof(matcher.buf),
9375         };
9376         struct mlx5_flow_dv_match_params value = {
9377                 .size = sizeof(value.buf),
9378         };
9379         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9380         void *actions[METER_ACTIONS];
9381         int i;
9382
9383         /* Create jump action. */
9384         if (!dtb->jump_actn)
9385                 dtb->jump_actn =
9386                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9387                                                         (dtb->sfx_tbl->obj);
9388         if (!dtb->jump_actn) {
9389                 DRV_LOG(ERR, "Failed to create policer jump action.");
9390                 goto error;
9391         }
9392         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9393                 int j = 0;
9394
9395                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9396                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9397                 if (mtb->count_actns[i])
9398                         actions[j++] = mtb->count_actns[i];
9399                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9400                         actions[j++] = mtb->drop_actn;
9401                 else
9402                         actions[j++] = dtb->jump_actn;
9403                 dtb->policer_rules[i] =
9404                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9405                                                  (void *)&value,
9406                                                   j, actions);
9407                 if (!dtb->policer_rules[i]) {
9408                         DRV_LOG(ERR, "Failed to create policer rule.");
9409                         goto error;
9410                 }
9411         }
9412         return 0;
9413 error:
9414         rte_errno = errno;
9415         return -1;
9416 }
9417
9418 /**
9419  * Create policer rules.
9420  *
9421  * @param[in] dev
9422  *   Pointer to Ethernet device.
9423  * @param[in] fm
9424  *   Pointer to flow meter structure.
9425  * @param[in] attr
9426  *   Pointer to flow attributes.
9427  *
9428  * @return
9429  *   0 on success, -1 otherwise.
9430  */
9431 static int
9432 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9433                              struct mlx5_flow_meter *fm,
9434                              const struct rte_flow_attr *attr)
9435 {
9436         struct mlx5_priv *priv = dev->data->dev_private;
9437         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9438         int ret;
9439
9440         if (attr->egress) {
9441                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9442                                                 priv->mtr_color_reg);
9443                 if (ret) {
9444                         DRV_LOG(ERR, "Failed to create egress policer.");
9445                         goto error;
9446                 }
9447         }
9448         if (attr->ingress) {
9449                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9450                                                 priv->mtr_color_reg);
9451                 if (ret) {
9452                         DRV_LOG(ERR, "Failed to create ingress policer.");
9453                         goto error;
9454                 }
9455         }
9456         if (attr->transfer) {
9457                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9458                                                 priv->mtr_color_reg);
9459                 if (ret) {
9460                         DRV_LOG(ERR, "Failed to create transfer policer.");
9461                         goto error;
9462                 }
9463         }
9464         return 0;
9465 error:
9466         flow_dv_destroy_policer_rules(dev, fm, attr);
9467         return -1;
9468 }
9469
9470 /**
9471  * Query a devx counter.
9472  *
9473  * @param[in] dev
9474  *   Pointer to the Ethernet device structure.
9475  * @param[in] cnt
9476  *   Index to the flow counter.
9477  * @param[in] clear
9478  *   Set to clear the counter statistics.
9479  * @param[out] pkts
9480  *   The statistics value of packets.
9481  * @param[out] bytes
9482  *   The statistics value of bytes.
9483  *
9484  * @return
9485  *   0 on success, otherwise return -1.
9486  */
9487 static int
9488 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9489                       uint64_t *pkts, uint64_t *bytes)
9490 {
9491         struct mlx5_priv *priv = dev->data->dev_private;
9492         struct mlx5_flow_counter *cnt;
9493         uint64_t inn_pkts, inn_bytes;
9494         int ret;
9495
9496         if (!priv->config.devx)
9497                 return -1;
9498
9499         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9500         if (ret)
9501                 return -1;
9502         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9503         *pkts = inn_pkts - cnt->hits;
9504         *bytes = inn_bytes - cnt->bytes;
9505         if (clear) {
9506                 cnt->hits = inn_pkts;
9507                 cnt->bytes = inn_bytes;
9508         }
9509         return 0;
9510 }
9511
9512 /**
9513  * Get aged-out flows.
9514  *
9515  * @param[in] dev
9516  *   Pointer to the Ethernet device structure.
9517  * @param[in] context
9518  *   The address of an array of pointers to the aged-out flows contexts.
9519  * @param[in] nb_contexts
9520  *   The length of context array pointers.
9521  * @param[out] error
9522  *   Perform verbose error reporting if not NULL. Initialized in case of
9523  *   error only.
9524  *
9525  * @return
9526  *   how many contexts get in success, otherwise negative errno value.
9527  *   if nb_contexts is 0, return the amount of all aged contexts.
9528  *   if nb_contexts is not 0 , return the amount of aged flows reported
9529  *   in the context array.
9530  * @note: only stub for now
9531  */
9532 static int
9533 flow_get_aged_flows(struct rte_eth_dev *dev,
9534                     void **context,
9535                     uint32_t nb_contexts,
9536                     struct rte_flow_error *error)
9537 {
9538         struct mlx5_priv *priv = dev->data->dev_private;
9539         struct mlx5_age_info *age_info;
9540         struct mlx5_age_param *age_param;
9541         struct mlx5_flow_counter *counter;
9542         int nb_flows = 0;
9543
9544         if (nb_contexts && !context)
9545                 return rte_flow_error_set(error, EINVAL,
9546                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9547                                           NULL,
9548                                           "Should assign at least one flow or"
9549                                           " context to get if nb_contexts != 0");
9550         age_info = GET_PORT_AGE_INFO(priv);
9551         rte_spinlock_lock(&age_info->aged_sl);
9552         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9553                 nb_flows++;
9554                 if (nb_contexts) {
9555                         age_param = MLX5_CNT_TO_AGE(counter);
9556                         context[nb_flows - 1] = age_param->context;
9557                         if (!(--nb_contexts))
9558                                 break;
9559                 }
9560         }
9561         rte_spinlock_unlock(&age_info->aged_sl);
9562         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9563         return nb_flows;
9564 }
9565
9566 /*
9567  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9568  */
9569 static int
9570 flow_dv_translate(struct rte_eth_dev *dev,
9571                   struct mlx5_flow *dev_flow,
9572                   const struct rte_flow_attr *attr,
9573                   const struct rte_flow_item items[],
9574                   const struct rte_flow_action actions[],
9575                   struct rte_flow_error *error)
9576 {
9577         int ret;
9578
9579         flow_dv_shared_lock(dev);
9580         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9581         flow_dv_shared_unlock(dev);
9582         return ret;
9583 }
9584
9585 /*
9586  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9587  */
9588 static int
9589 flow_dv_apply(struct rte_eth_dev *dev,
9590               struct rte_flow *flow,
9591               struct rte_flow_error *error)
9592 {
9593         int ret;
9594
9595         flow_dv_shared_lock(dev);
9596         ret = __flow_dv_apply(dev, flow, error);
9597         flow_dv_shared_unlock(dev);
9598         return ret;
9599 }
9600
9601 /*
9602  * Mutex-protected thunk to lock-free __flow_dv_remove().
9603  */
9604 static void
9605 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9606 {
9607         flow_dv_shared_lock(dev);
9608         __flow_dv_remove(dev, flow);
9609         flow_dv_shared_unlock(dev);
9610 }
9611
9612 /*
9613  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9614  */
9615 static void
9616 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9617 {
9618         flow_dv_shared_lock(dev);
9619         __flow_dv_destroy(dev, flow);
9620         flow_dv_shared_unlock(dev);
9621 }
9622
9623 /*
9624  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9625  */
9626 static uint32_t
9627 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9628 {
9629         uint32_t cnt;
9630
9631         flow_dv_shared_lock(dev);
9632         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9633         flow_dv_shared_unlock(dev);
9634         return cnt;
9635 }
9636
9637 /*
9638  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9639  */
9640 static void
9641 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9642 {
9643         flow_dv_shared_lock(dev);
9644         flow_dv_counter_release(dev, cnt);
9645         flow_dv_shared_unlock(dev);
9646 }
9647
9648 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9649         .validate = flow_dv_validate,
9650         .prepare = flow_dv_prepare,
9651         .translate = flow_dv_translate,
9652         .apply = flow_dv_apply,
9653         .remove = flow_dv_remove,
9654         .destroy = flow_dv_destroy,
9655         .query = flow_dv_query,
9656         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9657         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9658         .create_policer_rules = flow_dv_create_policer_rules,
9659         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9660         .counter_alloc = flow_dv_counter_allocate,
9661         .counter_free = flow_dv_counter_free,
9662         .counter_query = flow_dv_counter_query,
9663         .get_aged_flows = flow_get_aged_flows,
9664 };
9665
9666 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */