1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
27 #include <rte_cycles.h>
30 #include <rte_vxlan.h>
33 #include <mlx5_glue.h>
34 #include <mlx5_devx_cmds.h>
37 #include "mlx5_defs.h"
39 #include "mlx5_flow.h"
40 #include "mlx5_rxtx.h"
42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
48 #ifndef HAVE_MLX5DV_DR_ESWITCH
49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
54 #ifndef HAVE_MLX5DV_DR
55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
58 /* VLAN header definitions */
59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
79 struct mlx5_flow_tbl_resource *tbl);
82 * Initialize flow attributes structure according to flow items' types.
84 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
85 * mode. For tunnel mode, the items to be modified are the outermost ones.
88 * Pointer to item specification.
90 * Pointer to flow attributes structure.
92 * Pointer to the sub flow.
93 * @param[in] tunnel_decap
94 * Whether action is after tunnel decapsulation.
97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
98 struct mlx5_flow *dev_flow, bool tunnel_decap)
100 uint64_t layers = dev_flow->handle->layers;
103 * If layers is already initialized, it means this dev_flow is the
104 * suffix flow, the layers flags is set by the prefix flow. Need to
105 * use the layer flags from prefix flow as the suffix flow may not
106 * have the user defined items as the flow is split.
109 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
111 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
113 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
115 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
120 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
121 uint8_t next_protocol = 0xff;
122 switch (item->type) {
123 case RTE_FLOW_ITEM_TYPE_GRE:
124 case RTE_FLOW_ITEM_TYPE_NVGRE:
125 case RTE_FLOW_ITEM_TYPE_VXLAN:
126 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
127 case RTE_FLOW_ITEM_TYPE_GENEVE:
128 case RTE_FLOW_ITEM_TYPE_MPLS:
132 case RTE_FLOW_ITEM_TYPE_IPV4:
135 if (item->mask != NULL &&
136 ((const struct rte_flow_item_ipv4 *)
137 item->mask)->hdr.next_proto_id)
139 ((const struct rte_flow_item_ipv4 *)
140 (item->spec))->hdr.next_proto_id &
141 ((const struct rte_flow_item_ipv4 *)
142 (item->mask))->hdr.next_proto_id;
143 if ((next_protocol == IPPROTO_IPIP ||
144 next_protocol == IPPROTO_IPV6) && tunnel_decap)
147 case RTE_FLOW_ITEM_TYPE_IPV6:
150 if (item->mask != NULL &&
151 ((const struct rte_flow_item_ipv6 *)
152 item->mask)->hdr.proto)
154 ((const struct rte_flow_item_ipv6 *)
155 (item->spec))->hdr.proto &
156 ((const struct rte_flow_item_ipv6 *)
157 (item->mask))->hdr.proto;
158 if ((next_protocol == IPPROTO_IPIP ||
159 next_protocol == IPPROTO_IPV6) && tunnel_decap)
162 case RTE_FLOW_ITEM_TYPE_UDP:
166 case RTE_FLOW_ITEM_TYPE_TCP:
178 * Convert rte_mtr_color to mlx5 color.
187 rte_col_2_mlx5_col(enum rte_color rcol)
190 case RTE_COLOR_GREEN:
191 return MLX5_FLOW_COLOR_GREEN;
192 case RTE_COLOR_YELLOW:
193 return MLX5_FLOW_COLOR_YELLOW;
195 return MLX5_FLOW_COLOR_RED;
199 return MLX5_FLOW_COLOR_UNDEFINED;
202 struct field_modify_info {
203 uint32_t size; /* Size of field in protocol header, in bytes. */
204 uint32_t offset; /* Offset of field in protocol header, in bytes. */
205 enum mlx5_modification_field id;
208 struct field_modify_info modify_eth[] = {
209 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
210 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
211 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
212 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
216 struct field_modify_info modify_vlan_out_first_vid[] = {
217 /* Size in bits !!! */
218 {12, 0, MLX5_MODI_OUT_FIRST_VID},
222 struct field_modify_info modify_ipv4[] = {
223 {1, 1, MLX5_MODI_OUT_IP_DSCP},
224 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
225 {4, 12, MLX5_MODI_OUT_SIPV4},
226 {4, 16, MLX5_MODI_OUT_DIPV4},
230 struct field_modify_info modify_ipv6[] = {
231 {1, 0, MLX5_MODI_OUT_IP_DSCP},
232 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
233 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
234 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
235 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
236 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
237 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
238 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
239 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
240 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
244 struct field_modify_info modify_udp[] = {
245 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
246 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
250 struct field_modify_info modify_tcp[] = {
251 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
252 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
253 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
254 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
260 uint8_t next_protocol, uint64_t *item_flags,
263 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
264 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
265 if (next_protocol == IPPROTO_IPIP) {
266 *item_flags |= MLX5_FLOW_LAYER_IPIP;
269 if (next_protocol == IPPROTO_IPV6) {
270 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
276 * Acquire the synchronizing object to protect multithreaded access
277 * to shared dv context. Lock occurs only if context is actually
278 * shared, i.e. we have multiport IB device and representors are
282 * Pointer to the rte_eth_dev structure.
285 flow_dv_shared_lock(struct rte_eth_dev *dev)
287 struct mlx5_priv *priv = dev->data->dev_private;
288 struct mlx5_ibv_shared *sh = priv->sh;
290 if (sh->dv_refcnt > 1) {
293 ret = pthread_mutex_lock(&sh->dv_mutex);
300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
302 struct mlx5_priv *priv = dev->data->dev_private;
303 struct mlx5_ibv_shared *sh = priv->sh;
305 if (sh->dv_refcnt > 1) {
308 ret = pthread_mutex_unlock(&sh->dv_mutex);
314 /* Update VLAN's VID/PCP based on input rte_flow_action.
317 * Pointer to struct rte_flow_action.
319 * Pointer to struct rte_vlan_hdr.
322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
323 struct rte_vlan_hdr *vlan)
326 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
328 ((const struct rte_flow_action_of_set_vlan_pcp *)
329 action->conf)->vlan_pcp;
330 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
331 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
332 vlan->vlan_tci |= vlan_tci;
333 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
334 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
335 vlan->vlan_tci |= rte_be_to_cpu_16
336 (((const struct rte_flow_action_of_set_vlan_vid *)
337 action->conf)->vlan_vid);
342 * Fetch 1, 2, 3 or 4 byte field from the byte array
343 * and return as unsigned integer in host-endian format.
346 * Pointer to data array.
348 * Size of field to extract.
351 * converted field in host endian format.
353 static inline uint32_t
354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
363 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
367 ret = (ret << 8) | *(data + sizeof(uint16_t));
370 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
381 * Convert modify-header action to DV specification.
383 * Data length of each action is determined by provided field description
384 * and the item mask. Data bit offset and width of each action is determined
385 * by provided item mask.
388 * Pointer to item specification.
390 * Pointer to field modification information.
391 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
393 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
395 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
396 * Negative offset value sets the same offset as source offset.
397 * size field is ignored, value is taken from source field.
398 * @param[in,out] resource
399 * Pointer to the modify-header resource.
401 * Type of modification.
403 * Pointer to the error structure.
406 * 0 on success, a negative errno value otherwise and rte_errno is set.
409 flow_dv_convert_modify_action(struct rte_flow_item *item,
410 struct field_modify_info *field,
411 struct field_modify_info *dcopy,
412 struct mlx5_flow_dv_modify_hdr_resource *resource,
413 uint32_t type, struct rte_flow_error *error)
415 uint32_t i = resource->actions_num;
416 struct mlx5_modification_cmd *actions = resource->actions;
419 * The item and mask are provided in big-endian format.
420 * The fields should be presented as in big-endian format either.
421 * Mask must be always present, it defines the actual field width.
423 MLX5_ASSERT(item->mask);
424 MLX5_ASSERT(field->size);
431 if (i >= MLX5_MAX_MODIFY_NUM)
432 return rte_flow_error_set(error, EINVAL,
433 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
434 "too many items to modify");
435 /* Fetch variable byte size mask from the array. */
436 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
437 field->offset, field->size);
442 /* Deduce actual data width in bits from mask value. */
443 off_b = rte_bsf32(mask);
444 size_b = sizeof(uint32_t) * CHAR_BIT -
445 off_b - __builtin_clz(mask);
447 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
448 actions[i] = (struct mlx5_modification_cmd) {
454 /* Convert entire record to expected big-endian format. */
455 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
456 if (type == MLX5_MODIFICATION_TYPE_COPY) {
458 actions[i].dst_field = dcopy->id;
459 actions[i].dst_offset =
460 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
461 /* Convert entire record to big-endian format. */
462 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
464 MLX5_ASSERT(item->spec);
465 data = flow_dv_fetch_field((const uint8_t *)item->spec +
466 field->offset, field->size);
467 /* Shift out the trailing masked bits from data. */
468 data = (data & mask) >> off_b;
469 actions[i].data1 = rte_cpu_to_be_32(data);
473 } while (field->size);
474 if (resource->actions_num == i)
475 return rte_flow_error_set(error, EINVAL,
476 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
477 "invalid modification flow item");
478 resource->actions_num = i;
483 * Convert modify-header set IPv4 address action to DV specification.
485 * @param[in,out] resource
486 * Pointer to the modify-header resource.
488 * Pointer to action specification.
490 * Pointer to the error structure.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 flow_dv_convert_action_modify_ipv4
497 (struct mlx5_flow_dv_modify_hdr_resource *resource,
498 const struct rte_flow_action *action,
499 struct rte_flow_error *error)
501 const struct rte_flow_action_set_ipv4 *conf =
502 (const struct rte_flow_action_set_ipv4 *)(action->conf);
503 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
504 struct rte_flow_item_ipv4 ipv4;
505 struct rte_flow_item_ipv4 ipv4_mask;
507 memset(&ipv4, 0, sizeof(ipv4));
508 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
509 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
510 ipv4.hdr.src_addr = conf->ipv4_addr;
511 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
513 ipv4.hdr.dst_addr = conf->ipv4_addr;
514 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
517 item.mask = &ipv4_mask;
518 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
519 MLX5_MODIFICATION_TYPE_SET, error);
523 * Convert modify-header set IPv6 address action to DV specification.
525 * @param[in,out] resource
526 * Pointer to the modify-header resource.
528 * Pointer to action specification.
530 * Pointer to the error structure.
533 * 0 on success, a negative errno value otherwise and rte_errno is set.
536 flow_dv_convert_action_modify_ipv6
537 (struct mlx5_flow_dv_modify_hdr_resource *resource,
538 const struct rte_flow_action *action,
539 struct rte_flow_error *error)
541 const struct rte_flow_action_set_ipv6 *conf =
542 (const struct rte_flow_action_set_ipv6 *)(action->conf);
543 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
544 struct rte_flow_item_ipv6 ipv6;
545 struct rte_flow_item_ipv6 ipv6_mask;
547 memset(&ipv6, 0, sizeof(ipv6));
548 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
549 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
550 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
551 sizeof(ipv6.hdr.src_addr));
552 memcpy(&ipv6_mask.hdr.src_addr,
553 &rte_flow_item_ipv6_mask.hdr.src_addr,
554 sizeof(ipv6.hdr.src_addr));
556 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
557 sizeof(ipv6.hdr.dst_addr));
558 memcpy(&ipv6_mask.hdr.dst_addr,
559 &rte_flow_item_ipv6_mask.hdr.dst_addr,
560 sizeof(ipv6.hdr.dst_addr));
563 item.mask = &ipv6_mask;
564 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
565 MLX5_MODIFICATION_TYPE_SET, error);
569 * Convert modify-header set MAC address action to DV specification.
571 * @param[in,out] resource
572 * Pointer to the modify-header resource.
574 * Pointer to action specification.
576 * Pointer to the error structure.
579 * 0 on success, a negative errno value otherwise and rte_errno is set.
582 flow_dv_convert_action_modify_mac
583 (struct mlx5_flow_dv_modify_hdr_resource *resource,
584 const struct rte_flow_action *action,
585 struct rte_flow_error *error)
587 const struct rte_flow_action_set_mac *conf =
588 (const struct rte_flow_action_set_mac *)(action->conf);
589 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
590 struct rte_flow_item_eth eth;
591 struct rte_flow_item_eth eth_mask;
593 memset(ð, 0, sizeof(eth));
594 memset(ð_mask, 0, sizeof(eth_mask));
595 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
596 memcpy(ð.src.addr_bytes, &conf->mac_addr,
597 sizeof(eth.src.addr_bytes));
598 memcpy(ð_mask.src.addr_bytes,
599 &rte_flow_item_eth_mask.src.addr_bytes,
600 sizeof(eth_mask.src.addr_bytes));
602 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
603 sizeof(eth.dst.addr_bytes));
604 memcpy(ð_mask.dst.addr_bytes,
605 &rte_flow_item_eth_mask.dst.addr_bytes,
606 sizeof(eth_mask.dst.addr_bytes));
609 item.mask = ð_mask;
610 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
611 MLX5_MODIFICATION_TYPE_SET, error);
615 * Convert modify-header set VLAN VID action to DV specification.
617 * @param[in,out] resource
618 * Pointer to the modify-header resource.
620 * Pointer to action specification.
622 * Pointer to the error structure.
625 * 0 on success, a negative errno value otherwise and rte_errno is set.
628 flow_dv_convert_action_modify_vlan_vid
629 (struct mlx5_flow_dv_modify_hdr_resource *resource,
630 const struct rte_flow_action *action,
631 struct rte_flow_error *error)
633 const struct rte_flow_action_of_set_vlan_vid *conf =
634 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
635 int i = resource->actions_num;
636 struct mlx5_modification_cmd *actions = resource->actions;
637 struct field_modify_info *field = modify_vlan_out_first_vid;
639 if (i >= MLX5_MAX_MODIFY_NUM)
640 return rte_flow_error_set(error, EINVAL,
641 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
642 "too many items to modify");
643 actions[i] = (struct mlx5_modification_cmd) {
644 .action_type = MLX5_MODIFICATION_TYPE_SET,
646 .length = field->size,
647 .offset = field->offset,
649 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
650 actions[i].data1 = conf->vlan_vid;
651 actions[i].data1 = actions[i].data1 << 16;
652 resource->actions_num = ++i;
657 * Convert modify-header set TP action to DV specification.
659 * @param[in,out] resource
660 * Pointer to the modify-header resource.
662 * Pointer to action specification.
664 * Pointer to rte_flow_item objects list.
666 * Pointer to flow attributes structure.
667 * @param[in] dev_flow
668 * Pointer to the sub flow.
669 * @param[in] tunnel_decap
670 * Whether action is after tunnel decapsulation.
672 * Pointer to the error structure.
675 * 0 on success, a negative errno value otherwise and rte_errno is set.
678 flow_dv_convert_action_modify_tp
679 (struct mlx5_flow_dv_modify_hdr_resource *resource,
680 const struct rte_flow_action *action,
681 const struct rte_flow_item *items,
682 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
683 bool tunnel_decap, struct rte_flow_error *error)
685 const struct rte_flow_action_set_tp *conf =
686 (const struct rte_flow_action_set_tp *)(action->conf);
687 struct rte_flow_item item;
688 struct rte_flow_item_udp udp;
689 struct rte_flow_item_udp udp_mask;
690 struct rte_flow_item_tcp tcp;
691 struct rte_flow_item_tcp tcp_mask;
692 struct field_modify_info *field;
695 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
697 memset(&udp, 0, sizeof(udp));
698 memset(&udp_mask, 0, sizeof(udp_mask));
699 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
700 udp.hdr.src_port = conf->port;
701 udp_mask.hdr.src_port =
702 rte_flow_item_udp_mask.hdr.src_port;
704 udp.hdr.dst_port = conf->port;
705 udp_mask.hdr.dst_port =
706 rte_flow_item_udp_mask.hdr.dst_port;
708 item.type = RTE_FLOW_ITEM_TYPE_UDP;
710 item.mask = &udp_mask;
713 MLX5_ASSERT(attr->tcp);
714 memset(&tcp, 0, sizeof(tcp));
715 memset(&tcp_mask, 0, sizeof(tcp_mask));
716 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
717 tcp.hdr.src_port = conf->port;
718 tcp_mask.hdr.src_port =
719 rte_flow_item_tcp_mask.hdr.src_port;
721 tcp.hdr.dst_port = conf->port;
722 tcp_mask.hdr.dst_port =
723 rte_flow_item_tcp_mask.hdr.dst_port;
725 item.type = RTE_FLOW_ITEM_TYPE_TCP;
727 item.mask = &tcp_mask;
730 return flow_dv_convert_modify_action(&item, field, NULL, resource,
731 MLX5_MODIFICATION_TYPE_SET, error);
735 * Convert modify-header set TTL action to DV specification.
737 * @param[in,out] resource
738 * Pointer to the modify-header resource.
740 * Pointer to action specification.
742 * Pointer to rte_flow_item objects list.
744 * Pointer to flow attributes structure.
745 * @param[in] dev_flow
746 * Pointer to the sub flow.
747 * @param[in] tunnel_decap
748 * Whether action is after tunnel decapsulation.
750 * Pointer to the error structure.
753 * 0 on success, a negative errno value otherwise and rte_errno is set.
756 flow_dv_convert_action_modify_ttl
757 (struct mlx5_flow_dv_modify_hdr_resource *resource,
758 const struct rte_flow_action *action,
759 const struct rte_flow_item *items,
760 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
761 bool tunnel_decap, struct rte_flow_error *error)
763 const struct rte_flow_action_set_ttl *conf =
764 (const struct rte_flow_action_set_ttl *)(action->conf);
765 struct rte_flow_item item;
766 struct rte_flow_item_ipv4 ipv4;
767 struct rte_flow_item_ipv4 ipv4_mask;
768 struct rte_flow_item_ipv6 ipv6;
769 struct rte_flow_item_ipv6 ipv6_mask;
770 struct field_modify_info *field;
773 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
775 memset(&ipv4, 0, sizeof(ipv4));
776 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
777 ipv4.hdr.time_to_live = conf->ttl_value;
778 ipv4_mask.hdr.time_to_live = 0xFF;
779 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
781 item.mask = &ipv4_mask;
784 MLX5_ASSERT(attr->ipv6);
785 memset(&ipv6, 0, sizeof(ipv6));
786 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
787 ipv6.hdr.hop_limits = conf->ttl_value;
788 ipv6_mask.hdr.hop_limits = 0xFF;
789 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
791 item.mask = &ipv6_mask;
794 return flow_dv_convert_modify_action(&item, field, NULL, resource,
795 MLX5_MODIFICATION_TYPE_SET, error);
799 * Convert modify-header decrement TTL action to DV specification.
801 * @param[in,out] resource
802 * Pointer to the modify-header resource.
804 * Pointer to action specification.
806 * Pointer to rte_flow_item objects list.
808 * Pointer to flow attributes structure.
809 * @param[in] dev_flow
810 * Pointer to the sub flow.
811 * @param[in] tunnel_decap
812 * Whether action is after tunnel decapsulation.
814 * Pointer to the error structure.
817 * 0 on success, a negative errno value otherwise and rte_errno is set.
820 flow_dv_convert_action_modify_dec_ttl
821 (struct mlx5_flow_dv_modify_hdr_resource *resource,
822 const struct rte_flow_item *items,
823 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
824 bool tunnel_decap, struct rte_flow_error *error)
826 struct rte_flow_item item;
827 struct rte_flow_item_ipv4 ipv4;
828 struct rte_flow_item_ipv4 ipv4_mask;
829 struct rte_flow_item_ipv6 ipv6;
830 struct rte_flow_item_ipv6 ipv6_mask;
831 struct field_modify_info *field;
834 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
836 memset(&ipv4, 0, sizeof(ipv4));
837 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
838 ipv4.hdr.time_to_live = 0xFF;
839 ipv4_mask.hdr.time_to_live = 0xFF;
840 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
842 item.mask = &ipv4_mask;
845 MLX5_ASSERT(attr->ipv6);
846 memset(&ipv6, 0, sizeof(ipv6));
847 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
848 ipv6.hdr.hop_limits = 0xFF;
849 ipv6_mask.hdr.hop_limits = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
852 item.mask = &ipv6_mask;
855 return flow_dv_convert_modify_action(&item, field, NULL, resource,
856 MLX5_MODIFICATION_TYPE_ADD, error);
860 * Convert modify-header increment/decrement TCP Sequence number
861 * to DV specification.
863 * @param[in,out] resource
864 * Pointer to the modify-header resource.
866 * Pointer to action specification.
868 * Pointer to the error structure.
871 * 0 on success, a negative errno value otherwise and rte_errno is set.
874 flow_dv_convert_action_modify_tcp_seq
875 (struct mlx5_flow_dv_modify_hdr_resource *resource,
876 const struct rte_flow_action *action,
877 struct rte_flow_error *error)
879 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
880 uint64_t value = rte_be_to_cpu_32(*conf);
881 struct rte_flow_item item;
882 struct rte_flow_item_tcp tcp;
883 struct rte_flow_item_tcp tcp_mask;
885 memset(&tcp, 0, sizeof(tcp));
886 memset(&tcp_mask, 0, sizeof(tcp_mask));
887 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
889 * The HW has no decrement operation, only increment operation.
890 * To simulate decrement X from Y using increment operation
891 * we need to add UINT32_MAX X times to Y.
892 * Each adding of UINT32_MAX decrements Y by 1.
895 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
896 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
897 item.type = RTE_FLOW_ITEM_TYPE_TCP;
899 item.mask = &tcp_mask;
900 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
901 MLX5_MODIFICATION_TYPE_ADD, error);
905 * Convert modify-header increment/decrement TCP Acknowledgment number
906 * to DV specification.
908 * @param[in,out] resource
909 * Pointer to the modify-header resource.
911 * Pointer to action specification.
913 * Pointer to the error structure.
916 * 0 on success, a negative errno value otherwise and rte_errno is set.
919 flow_dv_convert_action_modify_tcp_ack
920 (struct mlx5_flow_dv_modify_hdr_resource *resource,
921 const struct rte_flow_action *action,
922 struct rte_flow_error *error)
924 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
925 uint64_t value = rte_be_to_cpu_32(*conf);
926 struct rte_flow_item item;
927 struct rte_flow_item_tcp tcp;
928 struct rte_flow_item_tcp tcp_mask;
930 memset(&tcp, 0, sizeof(tcp));
931 memset(&tcp_mask, 0, sizeof(tcp_mask));
932 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
934 * The HW has no decrement operation, only increment operation.
935 * To simulate decrement X from Y using increment operation
936 * we need to add UINT32_MAX X times to Y.
937 * Each adding of UINT32_MAX decrements Y by 1.
940 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
941 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
942 item.type = RTE_FLOW_ITEM_TYPE_TCP;
944 item.mask = &tcp_mask;
945 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
946 MLX5_MODIFICATION_TYPE_ADD, error);
949 static enum mlx5_modification_field reg_to_field[] = {
950 [REG_NONE] = MLX5_MODI_OUT_NONE,
951 [REG_A] = MLX5_MODI_META_DATA_REG_A,
952 [REG_B] = MLX5_MODI_META_DATA_REG_B,
953 [REG_C_0] = MLX5_MODI_META_REG_C_0,
954 [REG_C_1] = MLX5_MODI_META_REG_C_1,
955 [REG_C_2] = MLX5_MODI_META_REG_C_2,
956 [REG_C_3] = MLX5_MODI_META_REG_C_3,
957 [REG_C_4] = MLX5_MODI_META_REG_C_4,
958 [REG_C_5] = MLX5_MODI_META_REG_C_5,
959 [REG_C_6] = MLX5_MODI_META_REG_C_6,
960 [REG_C_7] = MLX5_MODI_META_REG_C_7,
964 * Convert register set to DV specification.
966 * @param[in,out] resource
967 * Pointer to the modify-header resource.
969 * Pointer to action specification.
971 * Pointer to the error structure.
974 * 0 on success, a negative errno value otherwise and rte_errno is set.
977 flow_dv_convert_action_set_reg
978 (struct mlx5_flow_dv_modify_hdr_resource *resource,
979 const struct rte_flow_action *action,
980 struct rte_flow_error *error)
982 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
983 struct mlx5_modification_cmd *actions = resource->actions;
984 uint32_t i = resource->actions_num;
986 if (i >= MLX5_MAX_MODIFY_NUM)
987 return rte_flow_error_set(error, EINVAL,
988 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
989 "too many items to modify");
990 MLX5_ASSERT(conf->id != REG_NONE);
991 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
992 actions[i] = (struct mlx5_modification_cmd) {
993 .action_type = MLX5_MODIFICATION_TYPE_SET,
994 .field = reg_to_field[conf->id],
996 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
997 actions[i].data1 = rte_cpu_to_be_32(conf->data);
999 resource->actions_num = i;
1004 * Convert SET_TAG action to DV specification.
1007 * Pointer to the rte_eth_dev structure.
1008 * @param[in,out] resource
1009 * Pointer to the modify-header resource.
1011 * Pointer to action specification.
1013 * Pointer to the error structure.
1016 * 0 on success, a negative errno value otherwise and rte_errno is set.
1019 flow_dv_convert_action_set_tag
1020 (struct rte_eth_dev *dev,
1021 struct mlx5_flow_dv_modify_hdr_resource *resource,
1022 const struct rte_flow_action_set_tag *conf,
1023 struct rte_flow_error *error)
1025 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027 struct rte_flow_item item = {
1031 struct field_modify_info reg_c_x[] = {
1034 enum mlx5_modification_field reg_type;
1037 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040 MLX5_ASSERT(ret != REG_NONE);
1041 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042 reg_type = reg_to_field[ret];
1043 MLX5_ASSERT(reg_type > 0);
1044 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046 MLX5_MODIFICATION_TYPE_SET, error);
1050 * Convert internal COPY_REG action to DV specification.
1053 * Pointer to the rte_eth_dev structure.
1054 * @param[in,out] res
1055 * Pointer to the modify-header resource.
1057 * Pointer to action specification.
1059 * Pointer to the error structure.
1062 * 0 on success, a negative errno value otherwise and rte_errno is set.
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066 struct mlx5_flow_dv_modify_hdr_resource *res,
1067 const struct rte_flow_action *action,
1068 struct rte_flow_error *error)
1070 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_src[] = {
1077 {4, 0, reg_to_field[conf->src]},
1080 struct field_modify_info reg_dst = {
1082 .id = reg_to_field[conf->dst],
1084 /* Adjust reg_c[0] usage according to reported mask. */
1085 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086 struct mlx5_priv *priv = dev->data->dev_private;
1087 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1089 MLX5_ASSERT(reg_c0);
1090 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091 if (conf->dst == REG_C_0) {
1092 /* Copy to reg_c[0], within mask only. */
1093 reg_dst.offset = rte_bsf32(reg_c0);
1095 * Mask is ignoring the enianness, because
1096 * there is no conversion in datapath.
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099 /* Copy from destination lower bits to reg_c[0]. */
1100 mask = reg_c0 >> reg_dst.offset;
1102 /* Copy from destination upper bits to reg_c[0]. */
1103 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104 rte_fls_u32(reg_c0));
1107 mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109 /* Copy from reg_c[0] to destination lower bits. */
1112 /* Copy from reg_c[0] to destination upper bits. */
1113 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114 (rte_fls_u32(reg_c0) -
1119 return flow_dv_convert_modify_action(&item,
1120 reg_src, ®_dst, res,
1121 MLX5_MODIFICATION_TYPE_COPY,
1126 * Convert MARK action to DV specification. This routine is used
1127 * in extensive metadata only and requires metadata register to be
1128 * handled. In legacy mode hardware tag resource is engaged.
1131 * Pointer to the rte_eth_dev structure.
1133 * Pointer to MARK action specification.
1134 * @param[in,out] resource
1135 * Pointer to the modify-header resource.
1137 * Pointer to the error structure.
1140 * 0 on success, a negative errno value otherwise and rte_errno is set.
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144 const struct rte_flow_action_mark *conf,
1145 struct mlx5_flow_dv_modify_hdr_resource *resource,
1146 struct rte_flow_error *error)
1148 struct mlx5_priv *priv = dev->data->dev_private;
1149 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150 priv->sh->dv_mark_mask);
1151 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152 struct rte_flow_item item = {
1156 struct field_modify_info reg_c_x[] = {
1157 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1163 return rte_flow_error_set(error, EINVAL,
1164 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165 NULL, "zero mark action mask");
1166 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1169 MLX5_ASSERT(reg > 0);
1170 if (reg == REG_C_0) {
1171 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172 uint32_t shl_c0 = rte_bsf32(msk_c0);
1174 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176 mask = rte_cpu_to_be_32(mask << shl_c0);
1178 reg_c_x[0].id = reg_to_field[reg];
1179 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180 MLX5_MODIFICATION_TYPE_SET, error);
1184 * Get metadata register index for specified steering domain.
1187 * Pointer to the rte_eth_dev structure.
1189 * Attributes of flow to determine steering domain.
1191 * Pointer to the error structure.
1194 * positive index on success, a negative errno value otherwise
1195 * and rte_errno is set.
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199 const struct rte_flow_attr *attr,
1200 struct rte_flow_error *error)
1203 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207 MLX5_METADATA_RX, 0, error);
1209 return rte_flow_error_set(error,
1210 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211 NULL, "unavailable "
1212 "metadata register");
1217 * Convert SET_META action to DV specification.
1220 * Pointer to the rte_eth_dev structure.
1221 * @param[in,out] resource
1222 * Pointer to the modify-header resource.
1224 * Attributes of flow that includes this item.
1226 * Pointer to action specification.
1228 * Pointer to the error structure.
1231 * 0 on success, a negative errno value otherwise and rte_errno is set.
1234 flow_dv_convert_action_set_meta
1235 (struct rte_eth_dev *dev,
1236 struct mlx5_flow_dv_modify_hdr_resource *resource,
1237 const struct rte_flow_attr *attr,
1238 const struct rte_flow_action_set_meta *conf,
1239 struct rte_flow_error *error)
1241 uint32_t data = conf->data;
1242 uint32_t mask = conf->mask;
1243 struct rte_flow_item item = {
1247 struct field_modify_info reg_c_x[] = {
1250 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1255 * In datapath code there is no endianness
1256 * coversions for perfromance reasons, all
1257 * pattern conversions are done in rte_flow.
1259 if (reg == REG_C_0) {
1260 struct mlx5_priv *priv = dev->data->dev_private;
1261 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1264 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266 shl_c0 = rte_bsf32(msk_c0);
1268 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1274 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275 /* The routine expects parameters in memory as big-endian ones. */
1276 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277 MLX5_MODIFICATION_TYPE_SET, error);
1281 * Convert modify-header set IPv4 DSCP action to DV specification.
1283 * @param[in,out] resource
1284 * Pointer to the modify-header resource.
1286 * Pointer to action specification.
1288 * Pointer to the error structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 flow_dv_convert_action_modify_ipv4_dscp
1295 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296 const struct rte_flow_action *action,
1297 struct rte_flow_error *error)
1299 const struct rte_flow_action_set_dscp *conf =
1300 (const struct rte_flow_action_set_dscp *)(action->conf);
1301 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302 struct rte_flow_item_ipv4 ipv4;
1303 struct rte_flow_item_ipv4 ipv4_mask;
1305 memset(&ipv4, 0, sizeof(ipv4));
1306 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307 ipv4.hdr.type_of_service = conf->dscp;
1308 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1310 item.mask = &ipv4_mask;
1311 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312 MLX5_MODIFICATION_TYPE_SET, error);
1316 * Convert modify-header set IPv6 DSCP action to DV specification.
1318 * @param[in,out] resource
1319 * Pointer to the modify-header resource.
1321 * Pointer to action specification.
1323 * Pointer to the error structure.
1326 * 0 on success, a negative errno value otherwise and rte_errno is set.
1329 flow_dv_convert_action_modify_ipv6_dscp
1330 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331 const struct rte_flow_action *action,
1332 struct rte_flow_error *error)
1334 const struct rte_flow_action_set_dscp *conf =
1335 (const struct rte_flow_action_set_dscp *)(action->conf);
1336 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337 struct rte_flow_item_ipv6 ipv6;
1338 struct rte_flow_item_ipv6 ipv6_mask;
1340 memset(&ipv6, 0, sizeof(ipv6));
1341 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1343 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344 * rdma-core only accept the DSCP bits byte aligned start from
1345 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346 * bits in IPv6 case as rdma-core requires byte aligned value.
1348 ipv6.hdr.vtc_flow = conf->dscp;
1349 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1351 item.mask = &ipv6_mask;
1352 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353 MLX5_MODIFICATION_TYPE_SET, error);
1357 * Validate MARK item.
1360 * Pointer to the rte_eth_dev structure.
1362 * Item specification.
1364 * Attributes of flow that includes this item.
1366 * Pointer to error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373 const struct rte_flow_item *item,
1374 const struct rte_flow_attr *attr __rte_unused,
1375 struct rte_flow_error *error)
1377 struct mlx5_priv *priv = dev->data->dev_private;
1378 struct mlx5_dev_config *config = &priv->config;
1379 const struct rte_flow_item_mark *spec = item->spec;
1380 const struct rte_flow_item_mark *mask = item->mask;
1381 const struct rte_flow_item_mark nic_mask = {
1382 .id = priv->sh->dv_mark_mask,
1386 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata feature"
1391 if (!mlx5_flow_ext_mreg_supported(dev))
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't supported");
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1399 "extended metadata register"
1400 " isn't available");
1401 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1408 "data cannot be empty");
1409 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410 return rte_flow_error_set(error, EINVAL,
1411 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1413 "mark id exceeds the limit");
1417 return rte_flow_error_set(error, EINVAL,
1418 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419 "mask cannot be zero");
1421 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422 (const uint8_t *)&nic_mask,
1423 sizeof(struct rte_flow_item_mark),
1431 * Validate META item.
1434 * Pointer to the rte_eth_dev structure.
1436 * Item specification.
1438 * Attributes of flow that includes this item.
1440 * Pointer to error structure.
1443 * 0 on success, a negative errno value otherwise and rte_errno is set.
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447 const struct rte_flow_item *item,
1448 const struct rte_flow_attr *attr,
1449 struct rte_flow_error *error)
1451 struct mlx5_priv *priv = dev->data->dev_private;
1452 struct mlx5_dev_config *config = &priv->config;
1453 const struct rte_flow_item_meta *spec = item->spec;
1454 const struct rte_flow_item_meta *mask = item->mask;
1455 struct rte_flow_item_meta nic_mask = {
1462 return rte_flow_error_set(error, EINVAL,
1463 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1465 "data cannot be empty");
1466 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467 if (!mlx5_flow_ext_mreg_supported(dev))
1468 return rte_flow_error_set(error, ENOTSUP,
1469 RTE_FLOW_ERROR_TYPE_ITEM, item,
1470 "extended metadata register"
1471 " isn't supported");
1472 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476 return rte_flow_error_set(error, ENOTSUP,
1477 RTE_FLOW_ERROR_TYPE_ITEM, item,
1481 nic_mask.data = priv->sh->dv_meta_mask;
1484 mask = &rte_flow_item_meta_mask;
1486 return rte_flow_error_set(error, EINVAL,
1487 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488 "mask cannot be zero");
1490 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491 (const uint8_t *)&nic_mask,
1492 sizeof(struct rte_flow_item_meta),
1498 * Validate TAG item.
1501 * Pointer to the rte_eth_dev structure.
1503 * Item specification.
1505 * Attributes of flow that includes this item.
1507 * Pointer to error structure.
1510 * 0 on success, a negative errno value otherwise and rte_errno is set.
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514 const struct rte_flow_item *item,
1515 const struct rte_flow_attr *attr __rte_unused,
1516 struct rte_flow_error *error)
1518 const struct rte_flow_item_tag *spec = item->spec;
1519 const struct rte_flow_item_tag *mask = item->mask;
1520 const struct rte_flow_item_tag nic_mask = {
1521 .data = RTE_BE32(UINT32_MAX),
1526 if (!mlx5_flow_ext_mreg_supported(dev))
1527 return rte_flow_error_set(error, ENOTSUP,
1528 RTE_FLOW_ERROR_TYPE_ITEM, item,
1529 "extensive metadata register"
1530 " isn't supported");
1532 return rte_flow_error_set(error, EINVAL,
1533 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1535 "data cannot be empty");
1537 mask = &rte_flow_item_tag_mask;
1539 return rte_flow_error_set(error, EINVAL,
1540 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541 "mask cannot be zero");
1543 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544 (const uint8_t *)&nic_mask,
1545 sizeof(struct rte_flow_item_tag),
1549 if (mask->index != 0xff)
1550 return rte_flow_error_set(error, EINVAL,
1551 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552 "partial mask for tag index"
1553 " is not supported");
1554 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1557 MLX5_ASSERT(ret != REG_NONE);
1562 * Validate vport item.
1565 * Pointer to the rte_eth_dev structure.
1567 * Item specification.
1569 * Attributes of flow that includes this item.
1570 * @param[in] item_flags
1571 * Bit-fields that holds the items detected until now.
1573 * Pointer to error structure.
1576 * 0 on success, a negative errno value otherwise and rte_errno is set.
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580 const struct rte_flow_item *item,
1581 const struct rte_flow_attr *attr,
1582 uint64_t item_flags,
1583 struct rte_flow_error *error)
1585 const struct rte_flow_item_port_id *spec = item->spec;
1586 const struct rte_flow_item_port_id *mask = item->mask;
1587 const struct rte_flow_item_port_id switch_mask = {
1590 struct mlx5_priv *esw_priv;
1591 struct mlx5_priv *dev_priv;
1594 if (!attr->transfer)
1595 return rte_flow_error_set(error, EINVAL,
1596 RTE_FLOW_ERROR_TYPE_ITEM,
1598 "match on port id is valid only"
1599 " when transfer flag is enabled");
1600 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601 return rte_flow_error_set(error, ENOTSUP,
1602 RTE_FLOW_ERROR_TYPE_ITEM, item,
1603 "multiple source ports are not"
1606 mask = &switch_mask;
1607 if (mask->id != 0xffffffff)
1608 return rte_flow_error_set(error, ENOTSUP,
1609 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1611 "no support for partial mask on"
1613 ret = mlx5_flow_item_acceptable
1614 (item, (const uint8_t *)mask,
1615 (const uint8_t *)&rte_flow_item_port_id_mask,
1616 sizeof(struct rte_flow_item_port_id),
1622 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1624 return rte_flow_error_set(error, rte_errno,
1625 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626 "failed to obtain E-Switch info for"
1628 dev_priv = mlx5_dev_to_eswitch_info(dev);
1630 return rte_flow_error_set(error, rte_errno,
1631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1633 "failed to obtain E-Switch info");
1634 if (esw_priv->domain_id != dev_priv->domain_id)
1635 return rte_flow_error_set(error, EINVAL,
1636 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637 "cannot match on a port from a"
1638 " different E-Switch");
1643 * GTP flags are contained in 1 byte of the format:
1644 * -------------------------------------------
1645 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1646 * |-----------------------------------------|
1647 * | value | Version | PT | Res | E | S | PN |
1648 * -------------------------------------------
1650 * Matching is supported only for GTP flags E, S, PN.
1652 #define MLX5_GTP_FLAGS_MASK 0x07
1655 * Validate VLAN item.
1658 * Item specification.
1659 * @param[in] item_flags
1660 * Bit-fields that holds the items detected until now.
1662 * Ethernet device flow is being created on.
1664 * Pointer to error structure.
1667 * 0 on success, a negative errno value otherwise and rte_errno is set.
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671 uint64_t item_flags,
1672 struct rte_eth_dev *dev,
1673 struct rte_flow_error *error)
1675 const struct rte_flow_item_vlan *mask = item->mask;
1676 const struct rte_flow_item_vlan nic_mask = {
1677 .tci = RTE_BE16(UINT16_MAX),
1678 .inner_type = RTE_BE16(UINT16_MAX),
1680 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1682 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683 MLX5_FLOW_LAYER_INNER_L4) :
1684 (MLX5_FLOW_LAYER_OUTER_L3 |
1685 MLX5_FLOW_LAYER_OUTER_L4);
1686 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687 MLX5_FLOW_LAYER_OUTER_VLAN;
1689 if (item_flags & vlanm)
1690 return rte_flow_error_set(error, EINVAL,
1691 RTE_FLOW_ERROR_TYPE_ITEM, item,
1692 "multiple VLAN layers not supported");
1693 else if ((item_flags & l34m) != 0)
1694 return rte_flow_error_set(error, EINVAL,
1695 RTE_FLOW_ERROR_TYPE_ITEM, item,
1696 "VLAN cannot follow L3/L4 layer");
1698 mask = &rte_flow_item_vlan_mask;
1699 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700 (const uint8_t *)&nic_mask,
1701 sizeof(struct rte_flow_item_vlan),
1705 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706 struct mlx5_priv *priv = dev->data->dev_private;
1708 if (priv->vmwa_context) {
1710 * Non-NULL context means we have a virtual machine
1711 * and SR-IOV enabled, we have to create VLAN interface
1712 * to make hypervisor to setup E-Switch vport
1713 * context correctly. We avoid creating the multiple
1714 * VLAN interfaces, so we cannot support VLAN tag mask.
1716 return rte_flow_error_set(error, EINVAL,
1717 RTE_FLOW_ERROR_TYPE_ITEM,
1719 "VLAN tag mask is not"
1720 " supported in virtual"
1728 * Validate GTP item.
1731 * Pointer to the rte_eth_dev structure.
1733 * Item specification.
1734 * @param[in] item_flags
1735 * Bit-fields that holds the items detected until now.
1737 * Pointer to error structure.
1740 * 0 on success, a negative errno value otherwise and rte_errno is set.
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744 const struct rte_flow_item *item,
1745 uint64_t item_flags,
1746 struct rte_flow_error *error)
1748 struct mlx5_priv *priv = dev->data->dev_private;
1749 const struct rte_flow_item_gtp *spec = item->spec;
1750 const struct rte_flow_item_gtp *mask = item->mask;
1751 const struct rte_flow_item_gtp nic_mask = {
1752 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1754 .teid = RTE_BE32(0xffffffff),
1757 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758 return rte_flow_error_set(error, ENOTSUP,
1759 RTE_FLOW_ERROR_TYPE_ITEM, item,
1760 "GTP support is not enabled");
1761 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762 return rte_flow_error_set(error, ENOTSUP,
1763 RTE_FLOW_ERROR_TYPE_ITEM, item,
1764 "multiple tunnel layers not"
1766 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767 return rte_flow_error_set(error, EINVAL,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "no outer UDP layer found");
1771 mask = &rte_flow_item_gtp_mask;
1772 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773 return rte_flow_error_set(error, ENOTSUP,
1774 RTE_FLOW_ERROR_TYPE_ITEM, item,
1775 "Match is supported for GTP"
1777 return mlx5_flow_item_acceptable
1778 (item, (const uint8_t *)mask,
1779 (const uint8_t *)&nic_mask,
1780 sizeof(struct rte_flow_item_gtp),
1785 * Validate the pop VLAN action.
1788 * Pointer to the rte_eth_dev structure.
1789 * @param[in] action_flags
1790 * Holds the actions detected until now.
1792 * Pointer to the pop vlan action.
1793 * @param[in] item_flags
1794 * The items found in this flow rule.
1796 * Pointer to flow attributes.
1798 * Pointer to error structure.
1801 * 0 on success, a negative errno value otherwise and rte_errno is set.
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805 uint64_t action_flags,
1806 const struct rte_flow_action *action,
1807 uint64_t item_flags,
1808 const struct rte_flow_attr *attr,
1809 struct rte_flow_error *error)
1811 const struct mlx5_priv *priv = dev->data->dev_private;
1815 if (!priv->sh->pop_vlan_action)
1816 return rte_flow_error_set(error, ENOTSUP,
1817 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1819 "pop vlan action is not supported");
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1824 "pop vlan action not supported for "
1826 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827 return rte_flow_error_set(error, ENOTSUP,
1828 RTE_FLOW_ERROR_TYPE_ACTION, action,
1829 "no support for multiple VLAN "
1831 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1835 "cannot pop vlan without a "
1836 "match on (outer) vlan in the flow");
1837 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838 return rte_flow_error_set(error, EINVAL,
1839 RTE_FLOW_ERROR_TYPE_ACTION, action,
1840 "wrong action order, port_id should "
1841 "be after pop VLAN action");
1842 if (!attr->transfer && priv->representor)
1843 return rte_flow_error_set(error, ENOTSUP,
1844 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845 "pop vlan action for VF representor "
1846 "not supported on NIC table");
1851 * Get VLAN default info from vlan match info.
1854 * the list of item specifications.
1856 * pointer VLAN info to fill to.
1859 * 0 on success, a negative errno value otherwise and rte_errno is set.
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863 struct rte_vlan_hdr *vlan)
1865 const struct rte_flow_item_vlan nic_mask = {
1866 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867 MLX5DV_FLOW_VLAN_VID_MASK),
1868 .inner_type = RTE_BE16(0xffff),
1873 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874 int type = items->type;
1876 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1880 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882 const struct rte_flow_item_vlan *vlan_v = items->spec;
1886 /* Only full match values are accepted */
1887 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1888 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1889 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1891 rte_be_to_cpu_16(vlan_v->tci &
1892 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1894 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1895 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1896 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1898 rte_be_to_cpu_16(vlan_v->tci &
1899 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1901 if (vlan_m->inner_type == nic_mask.inner_type)
1902 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1903 vlan_m->inner_type);
1908 * Validate the push VLAN action.
1911 * Pointer to the rte_eth_dev structure.
1912 * @param[in] action_flags
1913 * Holds the actions detected until now.
1914 * @param[in] item_flags
1915 * The items found in this flow rule.
1917 * Pointer to the action structure.
1919 * Pointer to flow attributes
1921 * Pointer to error structure.
1924 * 0 on success, a negative errno value otherwise and rte_errno is set.
1927 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1928 uint64_t action_flags,
1929 const struct rte_flow_item_vlan *vlan_m,
1930 const struct rte_flow_action *action,
1931 const struct rte_flow_attr *attr,
1932 struct rte_flow_error *error)
1934 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1935 const struct mlx5_priv *priv = dev->data->dev_private;
1937 if (!attr->transfer && attr->ingress)
1938 return rte_flow_error_set(error, ENOTSUP,
1939 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1941 "push VLAN action not supported for "
1943 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1944 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1945 return rte_flow_error_set(error, EINVAL,
1946 RTE_FLOW_ERROR_TYPE_ACTION, action,
1947 "invalid vlan ethertype");
1948 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ACTION, action,
1951 "no support for multiple VLAN "
1953 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1954 return rte_flow_error_set(error, EINVAL,
1955 RTE_FLOW_ERROR_TYPE_ACTION, action,
1956 "wrong action order, port_id should "
1957 "be after push VLAN");
1958 if (!attr->transfer && priv->representor)
1959 return rte_flow_error_set(error, ENOTSUP,
1960 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1961 "push vlan action for VF representor "
1962 "not supported on NIC table");
1964 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1965 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1966 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1967 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1968 !(mlx5_flow_find_action
1969 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1970 return rte_flow_error_set(error, EINVAL,
1971 RTE_FLOW_ERROR_TYPE_ACTION, action,
1972 "not full match mask on VLAN PCP and "
1973 "there is no of_set_vlan_pcp action, "
1974 "push VLAN action cannot figure out "
1977 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1978 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1979 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1980 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1981 !(mlx5_flow_find_action
1982 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ACTION, action,
1985 "not full match mask on VLAN VID and "
1986 "there is no of_set_vlan_vid action, "
1987 "push VLAN action cannot figure out "
1994 * Validate the set VLAN PCP.
1996 * @param[in] action_flags
1997 * Holds the actions detected until now.
1998 * @param[in] actions
1999 * Pointer to the list of actions remaining in the flow rule.
2001 * Pointer to error structure.
2004 * 0 on success, a negative errno value otherwise and rte_errno is set.
2007 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2008 const struct rte_flow_action actions[],
2009 struct rte_flow_error *error)
2011 const struct rte_flow_action *action = actions;
2012 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2014 if (conf->vlan_pcp > 7)
2015 return rte_flow_error_set(error, EINVAL,
2016 RTE_FLOW_ERROR_TYPE_ACTION, action,
2017 "VLAN PCP value is too big");
2018 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2019 return rte_flow_error_set(error, ENOTSUP,
2020 RTE_FLOW_ERROR_TYPE_ACTION, action,
2021 "set VLAN PCP action must follow "
2022 "the push VLAN action");
2023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2024 return rte_flow_error_set(error, ENOTSUP,
2025 RTE_FLOW_ERROR_TYPE_ACTION, action,
2026 "Multiple VLAN PCP modification are "
2028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2029 return rte_flow_error_set(error, EINVAL,
2030 RTE_FLOW_ERROR_TYPE_ACTION, action,
2031 "wrong action order, port_id should "
2032 "be after set VLAN PCP");
2037 * Validate the set VLAN VID.
2039 * @param[in] item_flags
2040 * Holds the items detected in this rule.
2041 * @param[in] action_flags
2042 * Holds the actions detected until now.
2043 * @param[in] actions
2044 * Pointer to the list of actions remaining in the flow rule.
2046 * Pointer to error structure.
2049 * 0 on success, a negative errno value otherwise and rte_errno is set.
2052 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2053 uint64_t action_flags,
2054 const struct rte_flow_action actions[],
2055 struct rte_flow_error *error)
2057 const struct rte_flow_action *action = actions;
2058 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2060 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ACTION, action,
2063 "VLAN VID value is too big");
2064 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2065 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2066 return rte_flow_error_set(error, ENOTSUP,
2067 RTE_FLOW_ERROR_TYPE_ACTION, action,
2068 "set VLAN VID action must follow push"
2069 " VLAN action or match on VLAN item");
2070 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2071 return rte_flow_error_set(error, ENOTSUP,
2072 RTE_FLOW_ERROR_TYPE_ACTION, action,
2073 "Multiple VLAN VID modifications are "
2075 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2076 return rte_flow_error_set(error, EINVAL,
2077 RTE_FLOW_ERROR_TYPE_ACTION, action,
2078 "wrong action order, port_id should "
2079 "be after set VLAN VID");
2084 * Validate the FLAG action.
2087 * Pointer to the rte_eth_dev structure.
2088 * @param[in] action_flags
2089 * Holds the actions detected until now.
2091 * Pointer to flow attributes
2093 * Pointer to error structure.
2096 * 0 on success, a negative errno value otherwise and rte_errno is set.
2099 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2100 uint64_t action_flags,
2101 const struct rte_flow_attr *attr,
2102 struct rte_flow_error *error)
2104 struct mlx5_priv *priv = dev->data->dev_private;
2105 struct mlx5_dev_config *config = &priv->config;
2108 /* Fall back if no extended metadata register support. */
2109 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2110 return mlx5_flow_validate_action_flag(action_flags, attr,
2112 /* Extensive metadata mode requires registers. */
2113 if (!mlx5_flow_ext_mreg_supported(dev))
2114 return rte_flow_error_set(error, ENOTSUP,
2115 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2116 "no metadata registers "
2117 "to support flag action");
2118 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2119 return rte_flow_error_set(error, ENOTSUP,
2120 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2121 "extended metadata register"
2122 " isn't available");
2123 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2126 MLX5_ASSERT(ret > 0);
2127 if (action_flags & MLX5_FLOW_ACTION_MARK)
2128 return rte_flow_error_set(error, EINVAL,
2129 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2130 "can't mark and flag in same flow");
2131 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2135 " actions in same flow");
2140 * Validate MARK action.
2143 * Pointer to the rte_eth_dev structure.
2145 * Pointer to action.
2146 * @param[in] action_flags
2147 * Holds the actions detected until now.
2149 * Pointer to flow attributes
2151 * Pointer to error structure.
2154 * 0 on success, a negative errno value otherwise and rte_errno is set.
2157 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2158 const struct rte_flow_action *action,
2159 uint64_t action_flags,
2160 const struct rte_flow_attr *attr,
2161 struct rte_flow_error *error)
2163 struct mlx5_priv *priv = dev->data->dev_private;
2164 struct mlx5_dev_config *config = &priv->config;
2165 const struct rte_flow_action_mark *mark = action->conf;
2168 /* Fall back if no extended metadata register support. */
2169 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2170 return mlx5_flow_validate_action_mark(action, action_flags,
2172 /* Extensive metadata mode requires registers. */
2173 if (!mlx5_flow_ext_mreg_supported(dev))
2174 return rte_flow_error_set(error, ENOTSUP,
2175 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2176 "no metadata registers "
2177 "to support mark action");
2178 if (!priv->sh->dv_mark_mask)
2179 return rte_flow_error_set(error, ENOTSUP,
2180 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2181 "extended metadata register"
2182 " isn't available");
2183 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2186 MLX5_ASSERT(ret > 0);
2188 return rte_flow_error_set(error, EINVAL,
2189 RTE_FLOW_ERROR_TYPE_ACTION, action,
2190 "configuration cannot be null");
2191 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2192 return rte_flow_error_set(error, EINVAL,
2193 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2195 "mark id exceeds the limit");
2196 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2197 return rte_flow_error_set(error, EINVAL,
2198 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2199 "can't flag and mark in same flow");
2200 if (action_flags & MLX5_FLOW_ACTION_MARK)
2201 return rte_flow_error_set(error, EINVAL,
2202 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2203 "can't have 2 mark actions in same"
2209 * Validate SET_META action.
2212 * Pointer to the rte_eth_dev structure.
2214 * Pointer to the action structure.
2215 * @param[in] action_flags
2216 * Holds the actions detected until now.
2218 * Pointer to flow attributes
2220 * Pointer to error structure.
2223 * 0 on success, a negative errno value otherwise and rte_errno is set.
2226 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2227 const struct rte_flow_action *action,
2228 uint64_t action_flags __rte_unused,
2229 const struct rte_flow_attr *attr,
2230 struct rte_flow_error *error)
2232 const struct rte_flow_action_set_meta *conf;
2233 uint32_t nic_mask = UINT32_MAX;
2236 if (!mlx5_flow_ext_mreg_supported(dev))
2237 return rte_flow_error_set(error, ENOTSUP,
2238 RTE_FLOW_ERROR_TYPE_ACTION, action,
2239 "extended metadata register"
2240 " isn't supported");
2241 reg = flow_dv_get_metadata_reg(dev, attr, error);
2244 if (reg != REG_A && reg != REG_B) {
2245 struct mlx5_priv *priv = dev->data->dev_private;
2247 nic_mask = priv->sh->dv_meta_mask;
2249 if (!(action->conf))
2250 return rte_flow_error_set(error, EINVAL,
2251 RTE_FLOW_ERROR_TYPE_ACTION, action,
2252 "configuration cannot be null");
2253 conf = (const struct rte_flow_action_set_meta *)action->conf;
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "zero mask doesn't have any effect");
2258 if (conf->mask & ~nic_mask)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, action,
2261 "meta data must be within reg C0");
2266 * Validate SET_TAG action.
2269 * Pointer to the rte_eth_dev structure.
2271 * Pointer to the action structure.
2272 * @param[in] action_flags
2273 * Holds the actions detected until now.
2275 * Pointer to flow attributes
2277 * Pointer to error structure.
2280 * 0 on success, a negative errno value otherwise and rte_errno is set.
2283 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2284 const struct rte_flow_action *action,
2285 uint64_t action_flags,
2286 const struct rte_flow_attr *attr,
2287 struct rte_flow_error *error)
2289 const struct rte_flow_action_set_tag *conf;
2290 const uint64_t terminal_action_flags =
2291 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2292 MLX5_FLOW_ACTION_RSS;
2295 if (!mlx5_flow_ext_mreg_supported(dev))
2296 return rte_flow_error_set(error, ENOTSUP,
2297 RTE_FLOW_ERROR_TYPE_ACTION, action,
2298 "extensive metadata register"
2299 " isn't supported");
2300 if (!(action->conf))
2301 return rte_flow_error_set(error, EINVAL,
2302 RTE_FLOW_ERROR_TYPE_ACTION, action,
2303 "configuration cannot be null");
2304 conf = (const struct rte_flow_action_set_tag *)action->conf;
2306 return rte_flow_error_set(error, EINVAL,
2307 RTE_FLOW_ERROR_TYPE_ACTION, action,
2308 "zero mask doesn't have any effect");
2309 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2312 if (!attr->transfer && attr->ingress &&
2313 (action_flags & terminal_action_flags))
2314 return rte_flow_error_set(error, EINVAL,
2315 RTE_FLOW_ERROR_TYPE_ACTION, action,
2316 "set_tag has no effect"
2317 " with terminal actions");
2322 * Validate count action.
2325 * Pointer to rte_eth_dev structure.
2327 * Pointer to error structure.
2330 * 0 on success, a negative errno value otherwise and rte_errno is set.
2333 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2334 struct rte_flow_error *error)
2336 struct mlx5_priv *priv = dev->data->dev_private;
2338 if (!priv->config.devx)
2340 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344 return rte_flow_error_set
2346 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2348 "count action not supported");
2352 * Validate the L2 encap action.
2355 * Pointer to the rte_eth_dev structure.
2356 * @param[in] action_flags
2357 * Holds the actions detected until now.
2359 * Pointer to the action structure.
2361 * Pointer to flow attributes.
2363 * Pointer to error structure.
2366 * 0 on success, a negative errno value otherwise and rte_errno is set.
2369 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2370 uint64_t action_flags,
2371 const struct rte_flow_action *action,
2372 const struct rte_flow_attr *attr,
2373 struct rte_flow_error *error)
2375 const struct mlx5_priv *priv = dev->data->dev_private;
2377 if (!(action->conf))
2378 return rte_flow_error_set(error, EINVAL,
2379 RTE_FLOW_ERROR_TYPE_ACTION, action,
2380 "configuration cannot be null");
2381 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2382 return rte_flow_error_set(error, EINVAL,
2383 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2384 "can only have a single encap action "
2386 if (!attr->transfer && priv->representor)
2387 return rte_flow_error_set(error, ENOTSUP,
2388 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2389 "encap action for VF representor "
2390 "not supported on NIC table");
2395 * Validate a decap action.
2398 * Pointer to the rte_eth_dev structure.
2399 * @param[in] action_flags
2400 * Holds the actions detected until now.
2402 * Pointer to flow attributes
2404 * Pointer to error structure.
2407 * 0 on success, a negative errno value otherwise and rte_errno is set.
2410 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2411 uint64_t action_flags,
2412 const struct rte_flow_attr *attr,
2413 struct rte_flow_error *error)
2415 const struct mlx5_priv *priv = dev->data->dev_private;
2417 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2418 return rte_flow_error_set(error, ENOTSUP,
2419 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2421 MLX5_FLOW_ACTION_DECAP ? "can only "
2422 "have a single decap action" : "decap "
2423 "after encap is not supported");
2424 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2425 return rte_flow_error_set(error, EINVAL,
2426 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2427 "can't have decap action after"
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2433 "decap action not supported for "
2435 if (!attr->transfer && priv->representor)
2436 return rte_flow_error_set(error, ENOTSUP,
2437 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2438 "decap action for VF representor "
2439 "not supported on NIC table");
2443 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2446 * Validate the raw encap and decap actions.
2449 * Pointer to the rte_eth_dev structure.
2451 * Pointer to the decap action.
2453 * Pointer to the encap action.
2455 * Pointer to flow attributes
2456 * @param[in/out] action_flags
2457 * Holds the actions detected until now.
2458 * @param[out] actions_n
2459 * pointer to the number of actions counter.
2461 * Pointer to error structure.
2464 * 0 on success, a negative errno value otherwise and rte_errno is set.
2467 flow_dv_validate_action_raw_encap_decap
2468 (struct rte_eth_dev *dev,
2469 const struct rte_flow_action_raw_decap *decap,
2470 const struct rte_flow_action_raw_encap *encap,
2471 const struct rte_flow_attr *attr, uint64_t *action_flags,
2472 int *actions_n, struct rte_flow_error *error)
2474 const struct mlx5_priv *priv = dev->data->dev_private;
2477 if (encap && (!encap->size || !encap->data))
2478 return rte_flow_error_set(error, EINVAL,
2479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2480 "raw encap data cannot be empty");
2481 if (decap && encap) {
2482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2486 else if (encap->size <=
2487 MLX5_ENCAPSULATION_DECISION_SIZE &&
2489 MLX5_ENCAPSULATION_DECISION_SIZE)
2492 else if (encap->size >
2493 MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 MLX5_ENCAPSULATION_DECISION_SIZE)
2496 /* 2 L2 actions: encap and decap. */
2499 return rte_flow_error_set(error,
2501 RTE_FLOW_ERROR_TYPE_ACTION,
2502 NULL, "unsupported too small "
2503 "raw decap and too small raw "
2504 "encap combination");
2507 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2516 return rte_flow_error_set(error, ENOTSUP,
2517 RTE_FLOW_ERROR_TYPE_ACTION,
2519 "small raw encap size");
2520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2521 return rte_flow_error_set(error, EINVAL,
2522 RTE_FLOW_ERROR_TYPE_ACTION,
2524 "more than one encap action");
2525 if (!attr->transfer && priv->representor)
2526 return rte_flow_error_set
2528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2529 "encap action for VF representor "
2530 "not supported on NIC table");
2531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2538 * Find existing encap/decap resource or create and register a new one.
2540 * @param[in, out] dev
2541 * Pointer to rte_eth_dev structure.
2542 * @param[in, out] resource
2543 * Pointer to encap/decap resource.
2544 * @parm[in, out] dev_flow
2545 * Pointer to the dev_flow.
2547 * pointer to error structure.
2550 * 0 on success otherwise -errno and errno is set.
2553 flow_dv_encap_decap_resource_register
2554 (struct rte_eth_dev *dev,
2555 struct mlx5_flow_dv_encap_decap_resource *resource,
2556 struct mlx5_flow *dev_flow,
2557 struct rte_flow_error *error)
2559 struct mlx5_priv *priv = dev->data->dev_private;
2560 struct mlx5_ibv_shared *sh = priv->sh;
2561 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2562 struct mlx5dv_dr_domain *domain;
2565 resource->flags = dev_flow->dv.group ? 0 : 1;
2566 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2567 domain = sh->fdb_domain;
2568 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2569 domain = sh->rx_domain;
2571 domain = sh->tx_domain;
2572 /* Lookup a matching resource from cache. */
2573 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2574 cache_resource, next) {
2575 if (resource->reformat_type == cache_resource->reformat_type &&
2576 resource->ft_type == cache_resource->ft_type &&
2577 resource->flags == cache_resource->flags &&
2578 resource->size == cache_resource->size &&
2579 !memcmp((const void *)resource->buf,
2580 (const void *)cache_resource->buf,
2582 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2583 (void *)cache_resource,
2584 rte_atomic32_read(&cache_resource->refcnt));
2585 rte_atomic32_inc(&cache_resource->refcnt);
2586 dev_flow->handle->dvh.rix_encap_decap = idx;
2587 dev_flow->dv.encap_decap = cache_resource;
2591 /* Register new encap/decap resource. */
2592 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2593 &dev_flow->handle->dvh.rix_encap_decap);
2594 if (!cache_resource)
2595 return rte_flow_error_set(error, ENOMEM,
2596 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597 "cannot allocate resource memory");
2598 *cache_resource = *resource;
2599 cache_resource->verbs_action =
2600 mlx5_glue->dv_create_flow_action_packet_reformat
2601 (sh->ctx, cache_resource->reformat_type,
2602 cache_resource->ft_type, domain, cache_resource->flags,
2603 cache_resource->size,
2604 (cache_resource->size ? cache_resource->buf : NULL));
2605 if (!cache_resource->verbs_action) {
2606 rte_free(cache_resource);
2607 return rte_flow_error_set(error, ENOMEM,
2608 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2609 NULL, "cannot create action");
2611 rte_atomic32_init(&cache_resource->refcnt);
2612 rte_atomic32_inc(&cache_resource->refcnt);
2613 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2614 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2616 dev_flow->dv.encap_decap = cache_resource;
2617 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2618 (void *)cache_resource,
2619 rte_atomic32_read(&cache_resource->refcnt));
2624 * Find existing table jump resource or create and register a new one.
2626 * @param[in, out] dev
2627 * Pointer to rte_eth_dev structure.
2628 * @param[in, out] tbl
2629 * Pointer to flow table resource.
2630 * @parm[in, out] dev_flow
2631 * Pointer to the dev_flow.
2633 * pointer to error structure.
2636 * 0 on success otherwise -errno and errno is set.
2639 flow_dv_jump_tbl_resource_register
2640 (struct rte_eth_dev *dev __rte_unused,
2641 struct mlx5_flow_tbl_resource *tbl,
2642 struct mlx5_flow *dev_flow,
2643 struct rte_flow_error *error)
2645 struct mlx5_flow_tbl_data_entry *tbl_data =
2646 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2652 tbl_data->jump.action =
2653 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2655 if (!tbl_data->jump.action)
2656 return rte_flow_error_set(error, ENOMEM,
2657 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2658 NULL, "cannot create jump action");
2659 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2660 (void *)&tbl_data->jump, cnt);
2662 /* old jump should not make the table ref++. */
2663 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2664 MLX5_ASSERT(tbl_data->jump.action);
2665 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2666 (void *)&tbl_data->jump, cnt);
2668 rte_atomic32_inc(&tbl_data->jump.refcnt);
2669 dev_flow->handle->rix_jump = tbl_data->idx;
2670 dev_flow->dv.jump = &tbl_data->jump;
2675 * Find existing table port ID resource or create and register a new one.
2677 * @param[in, out] dev
2678 * Pointer to rte_eth_dev structure.
2679 * @param[in, out] resource
2680 * Pointer to port ID action resource.
2681 * @parm[in, out] dev_flow
2682 * Pointer to the dev_flow.
2684 * pointer to error structure.
2687 * 0 on success otherwise -errno and errno is set.
2690 flow_dv_port_id_action_resource_register
2691 (struct rte_eth_dev *dev,
2692 struct mlx5_flow_dv_port_id_action_resource *resource,
2693 struct mlx5_flow *dev_flow,
2694 struct rte_flow_error *error)
2696 struct mlx5_priv *priv = dev->data->dev_private;
2697 struct mlx5_ibv_shared *sh = priv->sh;
2698 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2701 /* Lookup a matching resource from cache. */
2702 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2703 idx, cache_resource, next) {
2704 if (resource->port_id == cache_resource->port_id) {
2705 DRV_LOG(DEBUG, "port id action resource resource %p: "
2707 (void *)cache_resource,
2708 rte_atomic32_read(&cache_resource->refcnt));
2709 rte_atomic32_inc(&cache_resource->refcnt);
2710 dev_flow->handle->rix_port_id_action = idx;
2711 dev_flow->dv.port_id_action = cache_resource;
2715 /* Register new port id action resource. */
2716 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2717 &dev_flow->handle->rix_port_id_action);
2718 if (!cache_resource)
2719 return rte_flow_error_set(error, ENOMEM,
2720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2721 "cannot allocate resource memory");
2722 *cache_resource = *resource;
2724 * Depending on rdma_core version the glue routine calls
2725 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2726 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2728 cache_resource->action =
2729 mlx5_glue->dr_create_flow_action_dest_port
2730 (priv->sh->fdb_domain, resource->port_id);
2731 if (!cache_resource->action) {
2732 rte_free(cache_resource);
2733 return rte_flow_error_set(error, ENOMEM,
2734 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2735 NULL, "cannot create action");
2737 rte_atomic32_init(&cache_resource->refcnt);
2738 rte_atomic32_inc(&cache_resource->refcnt);
2739 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2740 dev_flow->handle->rix_port_id_action, cache_resource,
2742 dev_flow->dv.port_id_action = cache_resource;
2743 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2744 (void *)cache_resource,
2745 rte_atomic32_read(&cache_resource->refcnt));
2750 * Find existing push vlan resource or create and register a new one.
2752 * @param [in, out] dev
2753 * Pointer to rte_eth_dev structure.
2754 * @param[in, out] resource
2755 * Pointer to port ID action resource.
2756 * @parm[in, out] dev_flow
2757 * Pointer to the dev_flow.
2759 * pointer to error structure.
2762 * 0 on success otherwise -errno and errno is set.
2765 flow_dv_push_vlan_action_resource_register
2766 (struct rte_eth_dev *dev,
2767 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2768 struct mlx5_flow *dev_flow,
2769 struct rte_flow_error *error)
2771 struct mlx5_priv *priv = dev->data->dev_private;
2772 struct mlx5_ibv_shared *sh = priv->sh;
2773 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2774 struct mlx5dv_dr_domain *domain;
2777 /* Lookup a matching resource from cache. */
2778 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2779 sh->push_vlan_action_list, idx, cache_resource, next) {
2780 if (resource->vlan_tag == cache_resource->vlan_tag &&
2781 resource->ft_type == cache_resource->ft_type) {
2782 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2784 (void *)cache_resource,
2785 rte_atomic32_read(&cache_resource->refcnt));
2786 rte_atomic32_inc(&cache_resource->refcnt);
2787 dev_flow->handle->dvh.rix_push_vlan = idx;
2788 dev_flow->dv.push_vlan_res = cache_resource;
2792 /* Register new push_vlan action resource. */
2793 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2794 &dev_flow->handle->dvh.rix_push_vlan);
2795 if (!cache_resource)
2796 return rte_flow_error_set(error, ENOMEM,
2797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2798 "cannot allocate resource memory");
2799 *cache_resource = *resource;
2800 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2801 domain = sh->fdb_domain;
2802 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2803 domain = sh->rx_domain;
2805 domain = sh->tx_domain;
2806 cache_resource->action =
2807 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2808 resource->vlan_tag);
2809 if (!cache_resource->action) {
2810 rte_free(cache_resource);
2811 return rte_flow_error_set(error, ENOMEM,
2812 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2813 NULL, "cannot create action");
2815 rte_atomic32_init(&cache_resource->refcnt);
2816 rte_atomic32_inc(&cache_resource->refcnt);
2817 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2818 &sh->push_vlan_action_list,
2819 dev_flow->handle->dvh.rix_push_vlan,
2820 cache_resource, next);
2821 dev_flow->dv.push_vlan_res = cache_resource;
2822 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2823 (void *)cache_resource,
2824 rte_atomic32_read(&cache_resource->refcnt));
2828 * Get the size of specific rte_flow_item_type
2830 * @param[in] item_type
2831 * Tested rte_flow_item_type.
2834 * sizeof struct item_type, 0 if void or irrelevant.
2837 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 switch (item_type) {
2842 case RTE_FLOW_ITEM_TYPE_ETH:
2843 retval = sizeof(struct rte_flow_item_eth);
2845 case RTE_FLOW_ITEM_TYPE_VLAN:
2846 retval = sizeof(struct rte_flow_item_vlan);
2848 case RTE_FLOW_ITEM_TYPE_IPV4:
2849 retval = sizeof(struct rte_flow_item_ipv4);
2851 case RTE_FLOW_ITEM_TYPE_IPV6:
2852 retval = sizeof(struct rte_flow_item_ipv6);
2854 case RTE_FLOW_ITEM_TYPE_UDP:
2855 retval = sizeof(struct rte_flow_item_udp);
2857 case RTE_FLOW_ITEM_TYPE_TCP:
2858 retval = sizeof(struct rte_flow_item_tcp);
2860 case RTE_FLOW_ITEM_TYPE_VXLAN:
2861 retval = sizeof(struct rte_flow_item_vxlan);
2863 case RTE_FLOW_ITEM_TYPE_GRE:
2864 retval = sizeof(struct rte_flow_item_gre);
2866 case RTE_FLOW_ITEM_TYPE_NVGRE:
2867 retval = sizeof(struct rte_flow_item_nvgre);
2869 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2870 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2872 case RTE_FLOW_ITEM_TYPE_MPLS:
2873 retval = sizeof(struct rte_flow_item_mpls);
2875 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2883 #define MLX5_ENCAP_IPV4_VERSION 0x40
2884 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2885 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2886 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2887 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2888 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2889 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2892 * Convert the encap action data from list of rte_flow_item to raw buffer
2895 * Pointer to rte_flow_item objects list.
2897 * Pointer to the output buffer.
2899 * Pointer to the output buffer size.
2901 * Pointer to the error structure.
2904 * 0 on success, a negative errno value otherwise and rte_errno is set.
2907 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2908 size_t *size, struct rte_flow_error *error)
2910 struct rte_ether_hdr *eth = NULL;
2911 struct rte_vlan_hdr *vlan = NULL;
2912 struct rte_ipv4_hdr *ipv4 = NULL;
2913 struct rte_ipv6_hdr *ipv6 = NULL;
2914 struct rte_udp_hdr *udp = NULL;
2915 struct rte_vxlan_hdr *vxlan = NULL;
2916 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2917 struct rte_gre_hdr *gre = NULL;
2919 size_t temp_size = 0;
2922 return rte_flow_error_set(error, EINVAL,
2923 RTE_FLOW_ERROR_TYPE_ACTION,
2924 NULL, "invalid empty data");
2925 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2926 len = flow_dv_get_item_len(items->type);
2927 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2928 return rte_flow_error_set(error, EINVAL,
2929 RTE_FLOW_ERROR_TYPE_ACTION,
2930 (void *)items->type,
2931 "items total size is too big"
2932 " for encap action");
2933 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2934 switch (items->type) {
2935 case RTE_FLOW_ITEM_TYPE_ETH:
2936 eth = (struct rte_ether_hdr *)&buf[temp_size];
2938 case RTE_FLOW_ITEM_TYPE_VLAN:
2939 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2941 return rte_flow_error_set(error, EINVAL,
2942 RTE_FLOW_ERROR_TYPE_ACTION,
2943 (void *)items->type,
2944 "eth header not found");
2945 if (!eth->ether_type)
2946 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2948 case RTE_FLOW_ITEM_TYPE_IPV4:
2949 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2951 return rte_flow_error_set(error, EINVAL,
2952 RTE_FLOW_ERROR_TYPE_ACTION,
2953 (void *)items->type,
2954 "neither eth nor vlan"
2956 if (vlan && !vlan->eth_proto)
2957 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2958 else if (eth && !eth->ether_type)
2959 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2960 if (!ipv4->version_ihl)
2961 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2962 MLX5_ENCAP_IPV4_IHL_MIN;
2963 if (!ipv4->time_to_live)
2964 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2966 case RTE_FLOW_ITEM_TYPE_IPV6:
2967 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2969 return rte_flow_error_set(error, EINVAL,
2970 RTE_FLOW_ERROR_TYPE_ACTION,
2971 (void *)items->type,
2972 "neither eth nor vlan"
2974 if (vlan && !vlan->eth_proto)
2975 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2976 else if (eth && !eth->ether_type)
2977 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2978 if (!ipv6->vtc_flow)
2980 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2981 if (!ipv6->hop_limits)
2982 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2984 case RTE_FLOW_ITEM_TYPE_UDP:
2985 udp = (struct rte_udp_hdr *)&buf[temp_size];
2987 return rte_flow_error_set(error, EINVAL,
2988 RTE_FLOW_ERROR_TYPE_ACTION,
2989 (void *)items->type,
2990 "ip header not found");
2991 if (ipv4 && !ipv4->next_proto_id)
2992 ipv4->next_proto_id = IPPROTO_UDP;
2993 else if (ipv6 && !ipv6->proto)
2994 ipv6->proto = IPPROTO_UDP;
2996 case RTE_FLOW_ITEM_TYPE_VXLAN:
2997 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2999 return rte_flow_error_set(error, EINVAL,
3000 RTE_FLOW_ERROR_TYPE_ACTION,
3001 (void *)items->type,
3002 "udp header not found");
3004 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3005 if (!vxlan->vx_flags)
3007 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3009 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3010 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3012 return rte_flow_error_set(error, EINVAL,
3013 RTE_FLOW_ERROR_TYPE_ACTION,
3014 (void *)items->type,
3015 "udp header not found");
3016 if (!vxlan_gpe->proto)
3017 return rte_flow_error_set(error, EINVAL,
3018 RTE_FLOW_ERROR_TYPE_ACTION,
3019 (void *)items->type,
3020 "next protocol not found");
3023 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3024 if (!vxlan_gpe->vx_flags)
3025 vxlan_gpe->vx_flags =
3026 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3028 case RTE_FLOW_ITEM_TYPE_GRE:
3029 case RTE_FLOW_ITEM_TYPE_NVGRE:
3030 gre = (struct rte_gre_hdr *)&buf[temp_size];
3032 return rte_flow_error_set(error, EINVAL,
3033 RTE_FLOW_ERROR_TYPE_ACTION,
3034 (void *)items->type,
3035 "next protocol not found");
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION,
3039 (void *)items->type,
3040 "ip header not found");
3041 if (ipv4 && !ipv4->next_proto_id)
3042 ipv4->next_proto_id = IPPROTO_GRE;
3043 else if (ipv6 && !ipv6->proto)
3044 ipv6->proto = IPPROTO_GRE;
3046 case RTE_FLOW_ITEM_TYPE_VOID:
3049 return rte_flow_error_set(error, EINVAL,
3050 RTE_FLOW_ERROR_TYPE_ACTION,
3051 (void *)items->type,
3052 "unsupported item type");
3062 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3064 struct rte_ether_hdr *eth = NULL;
3065 struct rte_vlan_hdr *vlan = NULL;
3066 struct rte_ipv6_hdr *ipv6 = NULL;
3067 struct rte_udp_hdr *udp = NULL;
3071 eth = (struct rte_ether_hdr *)data;
3072 next_hdr = (char *)(eth + 1);
3073 proto = RTE_BE16(eth->ether_type);
3076 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3077 vlan = (struct rte_vlan_hdr *)next_hdr;
3078 proto = RTE_BE16(vlan->eth_proto);
3079 next_hdr += sizeof(struct rte_vlan_hdr);
3082 /* HW calculates IPv4 csum. no need to proceed */
3083 if (proto == RTE_ETHER_TYPE_IPV4)
3086 /* non IPv4/IPv6 header. not supported */
3087 if (proto != RTE_ETHER_TYPE_IPV6) {
3088 return rte_flow_error_set(error, ENOTSUP,
3089 RTE_FLOW_ERROR_TYPE_ACTION,
3090 NULL, "Cannot offload non IPv4/IPv6");
3093 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3095 /* ignore non UDP */
3096 if (ipv6->proto != IPPROTO_UDP)
3099 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3100 udp->dgram_cksum = 0;
3106 * Convert L2 encap action to DV specification.
3109 * Pointer to rte_eth_dev structure.
3111 * Pointer to action structure.
3112 * @param[in, out] dev_flow
3113 * Pointer to the mlx5_flow.
3114 * @param[in] transfer
3115 * Mark if the flow is E-Switch flow.
3117 * Pointer to the error structure.
3120 * 0 on success, a negative errno value otherwise and rte_errno is set.
3123 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3124 const struct rte_flow_action *action,
3125 struct mlx5_flow *dev_flow,
3127 struct rte_flow_error *error)
3129 const struct rte_flow_item *encap_data;
3130 const struct rte_flow_action_raw_encap *raw_encap_data;
3131 struct mlx5_flow_dv_encap_decap_resource res = {
3133 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3134 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3135 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3138 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3140 (const struct rte_flow_action_raw_encap *)action->conf;
3141 res.size = raw_encap_data->size;
3142 memcpy(res.buf, raw_encap_data->data, res.size);
3144 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3146 ((const struct rte_flow_action_vxlan_encap *)
3147 action->conf)->definition;
3150 ((const struct rte_flow_action_nvgre_encap *)
3151 action->conf)->definition;
3152 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3158 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION,
3161 NULL, "can't create L2 encap action");
3166 * Convert L2 decap action to DV specification.
3169 * Pointer to rte_eth_dev structure.
3170 * @param[in, out] dev_flow
3171 * Pointer to the mlx5_flow.
3172 * @param[in] transfer
3173 * Mark if the flow is E-Switch flow.
3175 * Pointer to the error structure.
3178 * 0 on success, a negative errno value otherwise and rte_errno is set.
3181 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3182 struct mlx5_flow *dev_flow,
3184 struct rte_flow_error *error)
3186 struct mlx5_flow_dv_encap_decap_resource res = {
3189 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3190 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3191 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3194 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3195 return rte_flow_error_set(error, EINVAL,
3196 RTE_FLOW_ERROR_TYPE_ACTION,
3197 NULL, "can't create L2 decap action");
3202 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3205 * Pointer to rte_eth_dev structure.
3207 * Pointer to action structure.
3208 * @param[in, out] dev_flow
3209 * Pointer to the mlx5_flow.
3211 * Pointer to the flow attributes.
3213 * Pointer to the error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3220 const struct rte_flow_action *action,
3221 struct mlx5_flow *dev_flow,
3222 const struct rte_flow_attr *attr,
3223 struct rte_flow_error *error)
3225 const struct rte_flow_action_raw_encap *encap_data;
3226 struct mlx5_flow_dv_encap_decap_resource res;
3228 memset(&res, 0, sizeof(res));
3229 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3230 res.size = encap_data->size;
3231 memcpy(res.buf, encap_data->data, res.size);
3232 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3233 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3234 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3236 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3238 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3239 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3240 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3241 return rte_flow_error_set(error, EINVAL,
3242 RTE_FLOW_ERROR_TYPE_ACTION,
3243 NULL, "can't create encap action");
3248 * Create action push VLAN.
3251 * Pointer to rte_eth_dev structure.
3253 * Pointer to the flow attributes.
3255 * Pointer to the vlan to push to the Ethernet header.
3256 * @param[in, out] dev_flow
3257 * Pointer to the mlx5_flow.
3259 * Pointer to the error structure.
3262 * 0 on success, a negative errno value otherwise and rte_errno is set.
3265 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3266 const struct rte_flow_attr *attr,
3267 const struct rte_vlan_hdr *vlan,
3268 struct mlx5_flow *dev_flow,
3269 struct rte_flow_error *error)
3271 struct mlx5_flow_dv_push_vlan_action_resource res;
3273 memset(&res, 0, sizeof(res));
3275 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3278 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3280 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3281 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3282 return flow_dv_push_vlan_action_resource_register
3283 (dev, &res, dev_flow, error);
3287 * Validate the modify-header actions.
3289 * @param[in] action_flags
3290 * Holds the actions detected until now.
3292 * Pointer to the modify action.
3294 * Pointer to error structure.
3297 * 0 on success, a negative errno value otherwise and rte_errno is set.
3300 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3301 const struct rte_flow_action *action,
3302 struct rte_flow_error *error)
3304 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3305 return rte_flow_error_set(error, EINVAL,
3306 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3307 NULL, "action configuration not set");
3308 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311 "can't have encap action before"
3317 * Validate the modify-header MAC address actions.
3319 * @param[in] action_flags
3320 * Holds the actions detected until now.
3322 * Pointer to the modify action.
3323 * @param[in] item_flags
3324 * Holds the items detected.
3326 * Pointer to error structure.
3329 * 0 on success, a negative errno value otherwise and rte_errno is set.
3332 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3333 const struct rte_flow_action *action,
3334 const uint64_t item_flags,
3335 struct rte_flow_error *error)
3339 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3341 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3342 return rte_flow_error_set(error, EINVAL,
3343 RTE_FLOW_ERROR_TYPE_ACTION,
3345 "no L2 item in pattern");
3351 * Validate the modify-header IPv4 address actions.
3353 * @param[in] action_flags
3354 * Holds the actions detected until now.
3356 * Pointer to the modify action.
3357 * @param[in] item_flags
3358 * Holds the items detected.
3360 * Pointer to error structure.
3363 * 0 on success, a negative errno value otherwise and rte_errno is set.
3366 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3367 const struct rte_flow_action *action,
3368 const uint64_t item_flags,
3369 struct rte_flow_error *error)
3374 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3376 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3377 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3378 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3379 if (!(item_flags & layer))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "no ipv4 item in pattern");
3389 * Validate the modify-header IPv6 address actions.
3391 * @param[in] action_flags
3392 * Holds the actions detected until now.
3394 * Pointer to the modify action.
3395 * @param[in] item_flags
3396 * Holds the items detected.
3398 * Pointer to error structure.
3401 * 0 on success, a negative errno value otherwise and rte_errno is set.
3404 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3405 const struct rte_flow_action *action,
3406 const uint64_t item_flags,
3407 struct rte_flow_error *error)
3412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3416 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3417 if (!(item_flags & layer))
3418 return rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ACTION,
3421 "no ipv6 item in pattern");
3427 * Validate the modify-header TP actions.
3429 * @param[in] action_flags
3430 * Holds the actions detected until now.
3432 * Pointer to the modify action.
3433 * @param[in] item_flags
3434 * Holds the items detected.
3436 * Pointer to error structure.
3439 * 0 on success, a negative errno value otherwise and rte_errno is set.
3442 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const uint64_t item_flags,
3445 struct rte_flow_error *error)
3450 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3452 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453 MLX5_FLOW_LAYER_INNER_L4 :
3454 MLX5_FLOW_LAYER_OUTER_L4;
3455 if (!(item_flags & layer))
3456 return rte_flow_error_set(error, EINVAL,
3457 RTE_FLOW_ERROR_TYPE_ACTION,
3458 NULL, "no transport layer "
3465 * Validate the modify-header actions of increment/decrement
3466 * TCP Sequence-number.
3468 * @param[in] action_flags
3469 * Holds the actions detected until now.
3471 * Pointer to the modify action.
3472 * @param[in] item_flags
3473 * Holds the items detected.
3475 * Pointer to error structure.
3478 * 0 on success, a negative errno value otherwise and rte_errno is set.
3481 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3482 const struct rte_flow_action *action,
3483 const uint64_t item_flags,
3484 struct rte_flow_error *error)
3489 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3491 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3492 MLX5_FLOW_LAYER_INNER_L4_TCP :
3493 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3494 if (!(item_flags & layer))
3495 return rte_flow_error_set(error, EINVAL,
3496 RTE_FLOW_ERROR_TYPE_ACTION,
3497 NULL, "no TCP item in"
3499 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3500 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3501 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3502 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3503 return rte_flow_error_set(error, EINVAL,
3504 RTE_FLOW_ERROR_TYPE_ACTION,
3506 "cannot decrease and increase"
3507 " TCP sequence number"
3508 " at the same time");
3514 * Validate the modify-header actions of increment/decrement
3515 * TCP Acknowledgment number.
3517 * @param[in] action_flags
3518 * Holds the actions detected until now.
3520 * Pointer to the modify action.
3521 * @param[in] item_flags
3522 * Holds the items detected.
3524 * Pointer to error structure.
3527 * 0 on success, a negative errno value otherwise and rte_errno is set.
3530 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3531 const struct rte_flow_action *action,
3532 const uint64_t item_flags,
3533 struct rte_flow_error *error)
3538 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3540 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3541 MLX5_FLOW_LAYER_INNER_L4_TCP :
3542 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3543 if (!(item_flags & layer))
3544 return rte_flow_error_set(error, EINVAL,
3545 RTE_FLOW_ERROR_TYPE_ACTION,
3546 NULL, "no TCP item in"
3548 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3549 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3550 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3551 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3552 return rte_flow_error_set(error, EINVAL,
3553 RTE_FLOW_ERROR_TYPE_ACTION,
3555 "cannot decrease and increase"
3556 " TCP acknowledgment number"
3557 " at the same time");
3563 * Validate the modify-header TTL actions.
3565 * @param[in] action_flags
3566 * Holds the actions detected until now.
3568 * Pointer to the modify action.
3569 * @param[in] item_flags
3570 * Holds the items detected.
3572 * Pointer to error structure.
3575 * 0 on success, a negative errno value otherwise and rte_errno is set.
3578 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3579 const struct rte_flow_action *action,
3580 const uint64_t item_flags,
3581 struct rte_flow_error *error)
3586 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3588 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3589 MLX5_FLOW_LAYER_INNER_L3 :
3590 MLX5_FLOW_LAYER_OUTER_L3;
3591 if (!(item_flags & layer))
3592 return rte_flow_error_set(error, EINVAL,
3593 RTE_FLOW_ERROR_TYPE_ACTION,
3595 "no IP protocol in pattern");
3601 * Validate jump action.
3604 * Pointer to the jump action.
3605 * @param[in] action_flags
3606 * Holds the actions detected until now.
3607 * @param[in] attributes
3608 * Pointer to flow attributes
3609 * @param[in] external
3610 * Action belongs to flow rule created by request external to PMD.
3612 * Pointer to error structure.
3615 * 0 on success, a negative errno value otherwise and rte_errno is set.
3618 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3619 uint64_t action_flags,
3620 const struct rte_flow_attr *attributes,
3621 bool external, struct rte_flow_error *error)
3623 uint32_t target_group, table;
3626 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3627 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3628 return rte_flow_error_set(error, EINVAL,
3629 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3630 "can't have 2 fate actions in"
3632 if (action_flags & MLX5_FLOW_ACTION_METER)
3633 return rte_flow_error_set(error, ENOTSUP,
3634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3635 "jump with meter not support");
3637 return rte_flow_error_set(error, EINVAL,
3638 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3639 NULL, "action configuration not set");
3641 ((const struct rte_flow_action_jump *)action->conf)->group;
3642 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3643 true, &table, error);
3646 if (attributes->group == target_group)
3647 return rte_flow_error_set(error, EINVAL,
3648 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3649 "target group must be other than"
3650 " the current flow group");
3655 * Validate the port_id action.
3658 * Pointer to rte_eth_dev structure.
3659 * @param[in] action_flags
3660 * Bit-fields that holds the actions detected until now.
3662 * Port_id RTE action structure.
3664 * Attributes of flow that includes this action.
3666 * Pointer to error structure.
3669 * 0 on success, a negative errno value otherwise and rte_errno is set.
3672 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3673 uint64_t action_flags,
3674 const struct rte_flow_action *action,
3675 const struct rte_flow_attr *attr,
3676 struct rte_flow_error *error)
3678 const struct rte_flow_action_port_id *port_id;
3679 struct mlx5_priv *act_priv;
3680 struct mlx5_priv *dev_priv;
3683 if (!attr->transfer)
3684 return rte_flow_error_set(error, ENOTSUP,
3685 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3687 "port id action is valid in transfer"
3689 if (!action || !action->conf)
3690 return rte_flow_error_set(error, ENOTSUP,
3691 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3693 "port id action parameters must be"
3695 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3696 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3697 return rte_flow_error_set(error, EINVAL,
3698 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699 "can have only one fate actions in"
3701 dev_priv = mlx5_dev_to_eswitch_info(dev);
3703 return rte_flow_error_set(error, rte_errno,
3704 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3706 "failed to obtain E-Switch info");
3707 port_id = action->conf;
3708 port = port_id->original ? dev->data->port_id : port_id->id;
3709 act_priv = mlx5_port_to_eswitch_info(port, false);
3711 return rte_flow_error_set
3713 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3714 "failed to obtain E-Switch port id for port");
3715 if (act_priv->domain_id != dev_priv->domain_id)
3716 return rte_flow_error_set
3718 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3719 "port does not belong to"
3720 " E-Switch being configured");
3725 * Get the maximum number of modify header actions.
3728 * Pointer to rte_eth_dev structure.
3730 * Flags bits to check if root level.
3733 * Max number of modify header actions device can support.
3735 static inline unsigned int
3736 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740 * There's no way to directly query the max capacity from FW.
3741 * The maximal value on root table should be assumed to be supported.
3743 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3744 return MLX5_MAX_MODIFY_NUM;
3746 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 * Validate the meter action.
3753 * Pointer to rte_eth_dev structure.
3754 * @param[in] action_flags
3755 * Bit-fields that holds the actions detected until now.
3757 * Pointer to the meter action.
3759 * Attributes of flow that includes this action.
3761 * Pointer to error structure.
3764 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3767 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3768 uint64_t action_flags,
3769 const struct rte_flow_action *action,
3770 const struct rte_flow_attr *attr,
3771 struct rte_flow_error *error)
3773 struct mlx5_priv *priv = dev->data->dev_private;
3774 const struct rte_flow_action_meter *am = action->conf;
3775 struct mlx5_flow_meter *fm;
3778 return rte_flow_error_set(error, EINVAL,
3779 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3780 "meter action conf is NULL");
3782 if (action_flags & MLX5_FLOW_ACTION_METER)
3783 return rte_flow_error_set(error, ENOTSUP,
3784 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3785 "meter chaining not support");
3786 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3787 return rte_flow_error_set(error, ENOTSUP,
3788 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3789 "meter with jump not support");
3791 return rte_flow_error_set(error, ENOTSUP,
3792 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3794 "meter action not supported");
3795 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3797 return rte_flow_error_set(error, EINVAL,
3798 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3800 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3801 (!fm->ingress && !attr->ingress && attr->egress) ||
3802 (!fm->egress && !attr->egress && attr->ingress))))
3803 return rte_flow_error_set(error, EINVAL,
3804 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3805 "Flow attributes are either invalid "
3806 "or have a conflict with current "
3807 "meter attributes");
3812 * Validate the age action.
3814 * @param[in] action_flags
3815 * Holds the actions detected until now.
3817 * Pointer to the age action.
3819 * Pointer to the Ethernet device structure.
3821 * Pointer to error structure.
3824 * 0 on success, a negative errno value otherwise and rte_errno is set.
3827 flow_dv_validate_action_age(uint64_t action_flags,
3828 const struct rte_flow_action *action,
3829 struct rte_eth_dev *dev,
3830 struct rte_flow_error *error)
3832 struct mlx5_priv *priv = dev->data->dev_private;
3833 const struct rte_flow_action_age *age = action->conf;
3835 if (!priv->config.devx || priv->counter_fallback)
3836 return rte_flow_error_set(error, ENOTSUP,
3837 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3839 "age action not supported");
3840 if (!(action->conf))
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, action,
3843 "configuration cannot be null");
3844 if (age->timeout >= UINT16_MAX / 2 / 10)
3845 return rte_flow_error_set(error, ENOTSUP,
3846 RTE_FLOW_ERROR_TYPE_ACTION, action,
3847 "Max age time: 3275 seconds");
3848 if (action_flags & MLX5_FLOW_ACTION_AGE)
3849 return rte_flow_error_set(error, EINVAL,
3850 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3851 "Duplicate age ctions set");
3856 * Validate the modify-header IPv4 DSCP actions.
3858 * @param[in] action_flags
3859 * Holds the actions detected until now.
3861 * Pointer to the modify action.
3862 * @param[in] item_flags
3863 * Holds the items detected.
3865 * Pointer to error structure.
3868 * 0 on success, a negative errno value otherwise and rte_errno is set.
3871 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3872 const struct rte_flow_action *action,
3873 const uint64_t item_flags,
3874 struct rte_flow_error *error)
3878 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3880 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3881 return rte_flow_error_set(error, EINVAL,
3882 RTE_FLOW_ERROR_TYPE_ACTION,
3884 "no ipv4 item in pattern");
3890 * Validate the modify-header IPv6 DSCP actions.
3892 * @param[in] action_flags
3893 * Holds the actions detected until now.
3895 * Pointer to the modify action.
3896 * @param[in] item_flags
3897 * Holds the items detected.
3899 * Pointer to error structure.
3902 * 0 on success, a negative errno value otherwise and rte_errno is set.
3905 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3906 const struct rte_flow_action *action,
3907 const uint64_t item_flags,
3908 struct rte_flow_error *error)
3912 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3914 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3915 return rte_flow_error_set(error, EINVAL,
3916 RTE_FLOW_ERROR_TYPE_ACTION,
3918 "no ipv6 item in pattern");
3924 * Find existing modify-header resource or create and register a new one.
3926 * @param dev[in, out]
3927 * Pointer to rte_eth_dev structure.
3928 * @param[in, out] resource
3929 * Pointer to modify-header resource.
3930 * @parm[in, out] dev_flow
3931 * Pointer to the dev_flow.
3933 * pointer to error structure.
3936 * 0 on success otherwise -errno and errno is set.
3939 flow_dv_modify_hdr_resource_register
3940 (struct rte_eth_dev *dev,
3941 struct mlx5_flow_dv_modify_hdr_resource *resource,
3942 struct mlx5_flow *dev_flow,
3943 struct rte_flow_error *error)
3945 struct mlx5_priv *priv = dev->data->dev_private;
3946 struct mlx5_ibv_shared *sh = priv->sh;
3947 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3948 struct mlx5dv_dr_domain *ns;
3949 uint32_t actions_len;
3951 resource->flags = dev_flow->dv.group ? 0 :
3952 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3953 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3955 return rte_flow_error_set(error, EOVERFLOW,
3956 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3957 "too many modify header items");
3958 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3959 ns = sh->fdb_domain;
3960 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964 /* Lookup a matching resource from cache. */
3965 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3966 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3967 if (resource->ft_type == cache_resource->ft_type &&
3968 resource->actions_num == cache_resource->actions_num &&
3969 resource->flags == cache_resource->flags &&
3970 !memcmp((const void *)resource->actions,
3971 (const void *)cache_resource->actions,
3973 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3974 (void *)cache_resource,
3975 rte_atomic32_read(&cache_resource->refcnt));
3976 rte_atomic32_inc(&cache_resource->refcnt);
3977 dev_flow->handle->dvh.modify_hdr = cache_resource;
3981 /* Register new modify-header resource. */
3982 cache_resource = rte_calloc(__func__, 1,
3983 sizeof(*cache_resource) + actions_len, 0);
3984 if (!cache_resource)
3985 return rte_flow_error_set(error, ENOMEM,
3986 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3987 "cannot allocate resource memory");
3988 *cache_resource = *resource;
3989 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3990 cache_resource->verbs_action =
3991 mlx5_glue->dv_create_flow_action_modify_header
3992 (sh->ctx, cache_resource->ft_type, ns,
3993 cache_resource->flags, actions_len,
3994 (uint64_t *)cache_resource->actions);
3995 if (!cache_resource->verbs_action) {
3996 rte_free(cache_resource);
3997 return rte_flow_error_set(error, ENOMEM,
3998 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3999 NULL, "cannot create action");
4001 rte_atomic32_init(&cache_resource->refcnt);
4002 rte_atomic32_inc(&cache_resource->refcnt);
4003 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4004 dev_flow->handle->dvh.modify_hdr = cache_resource;
4005 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4006 (void *)cache_resource,
4007 rte_atomic32_read(&cache_resource->refcnt));
4012 * Get DV flow counter by index.
4015 * Pointer to the Ethernet device structure.
4017 * mlx5 flow counter index in the container.
4019 * mlx5 flow counter pool in the container,
4022 * Pointer to the counter, NULL otherwise.
4024 static struct mlx5_flow_counter *
4025 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4027 struct mlx5_flow_counter_pool **ppool)
4029 struct mlx5_priv *priv = dev->data->dev_private;
4030 struct mlx5_pools_container *cont;
4031 struct mlx5_flow_counter_pool *pool;
4032 uint32_t batch = 0, age = 0;
4035 age = MLX_CNT_IS_AGE(idx);
4036 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4037 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4038 idx -= MLX5_CNT_BATCH_OFFSET;
4041 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4042 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4043 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 * Get a pool by devx counter ID.
4054 * Pointer to the counter container.
4056 * The counter devx ID.
4059 * The counter pool pointer if exists, NULL otherwise,
4061 static struct mlx5_flow_counter_pool *
4062 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4065 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4067 for (i = 0; i < n_valid; i++) {
4068 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4069 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4070 MLX5_COUNTERS_PER_POOL;
4072 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4074 * Move the pool to the head, as counter allocate
4075 * always gets the first pool in the container.
4077 if (pool != TAILQ_FIRST(&cont->pool_list)) {
4078 TAILQ_REMOVE(&cont->pool_list, pool, next);
4079 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4088 * Allocate a new memory for the counter values wrapped by all the needed
4092 * Pointer to the Ethernet device structure.
4094 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4097 * The new memory management pointer on success, otherwise NULL and rte_errno
4100 static struct mlx5_counter_stats_mem_mng *
4101 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4103 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4104 (dev->data->dev_private))->sh;
4105 struct mlx5_devx_mkey_attr mkey_attr;
4106 struct mlx5_counter_stats_mem_mng *mem_mng;
4107 volatile struct flow_counter_stats *raw_data;
4108 int size = (sizeof(struct flow_counter_stats) *
4109 MLX5_COUNTERS_PER_POOL +
4110 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4111 sizeof(struct mlx5_counter_stats_mem_mng);
4112 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4119 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4120 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4121 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4122 IBV_ACCESS_LOCAL_WRITE);
4123 if (!mem_mng->umem) {
4128 mkey_attr.addr = (uintptr_t)mem;
4129 mkey_attr.size = size;
4130 mkey_attr.umem_id = mem_mng->umem->umem_id;
4131 mkey_attr.pd = sh->pdn;
4132 mkey_attr.log_entity_size = 0;
4133 mkey_attr.pg_access = 0;
4134 mkey_attr.klm_array = NULL;
4135 mkey_attr.klm_num = 0;
4136 mkey_attr.relaxed_ordering = 1;
4137 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4139 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4144 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4145 raw_data = (volatile struct flow_counter_stats *)mem;
4146 for (i = 0; i < raws_n; ++i) {
4147 mem_mng->raws[i].mem_mng = mem_mng;
4148 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4150 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4155 * Resize a counter container.
4158 * Pointer to the Ethernet device structure.
4160 * Whether the pool is for counter that was allocated by batch command.
4162 * Whether the pool is for Aging counter.
4165 * The new container pointer on success, otherwise NULL and rte_errno is set.
4167 static struct mlx5_pools_container *
4168 flow_dv_container_resize(struct rte_eth_dev *dev,
4169 uint32_t batch, uint32_t age)
4171 struct mlx5_priv *priv = dev->data->dev_private;
4172 struct mlx5_pools_container *cont =
4173 MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4174 struct mlx5_pools_container *new_cont =
4175 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4176 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4177 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4178 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4181 /* Fallback mode has no background thread. Skip the check. */
4182 if (!priv->counter_fallback &&
4183 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4184 /* The last resize still hasn't detected by the host thread. */
4188 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4189 if (!new_cont->pools) {
4194 memcpy(new_cont->pools, cont->pools, cont->n *
4195 sizeof(struct mlx5_flow_counter_pool *));
4197 * Fallback mode query the counter directly, no background query
4198 * resources are needed.
4200 if (!priv->counter_fallback) {
4201 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4202 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4204 rte_free(new_cont->pools);
4207 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4208 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4210 MLX5_CNT_CONTAINER_RESIZE +
4214 * Release the old container pools directly as no background
4215 * thread helps that.
4217 rte_free(cont->pools);
4219 new_cont->n = resize;
4220 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4221 TAILQ_INIT(&new_cont->pool_list);
4222 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4223 new_cont->init_mem_mng = mem_mng;
4225 /* Flip the master container. */
4226 priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4231 * Query a devx flow counter.
4234 * Pointer to the Ethernet device structure.
4236 * Index to the flow counter.
4238 * The statistics value of packets.
4240 * The statistics value of bytes.
4243 * 0 on success, otherwise a negative errno value and rte_errno is set.
4246 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4249 struct mlx5_priv *priv = dev->data->dev_private;
4250 struct mlx5_flow_counter_pool *pool = NULL;
4251 struct mlx5_flow_counter *cnt;
4252 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4255 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4257 if (counter < MLX5_CNT_BATCH_OFFSET) {
4258 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4259 if (priv->counter_fallback)
4260 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4261 0, pkts, bytes, 0, NULL, NULL, 0);
4264 rte_spinlock_lock(&pool->sl);
4266 * The single counters allocation may allocate smaller ID than the
4267 * current allocated in parallel to the host reading.
4268 * In this case the new counter values must be reported as 0.
4270 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4274 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4275 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4276 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4278 rte_spinlock_unlock(&pool->sl);
4283 * Create and initialize a new counter pool.
4286 * Pointer to the Ethernet device structure.
4288 * The devX counter handle.
4290 * Whether the pool is for counter that was allocated by batch command.
4292 * Whether the pool is for counter that was allocated for aging.
4293 * @param[in/out] cont_cur
4294 * Pointer to the container pointer, it will be update in pool resize.
4297 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4299 static struct mlx5_pools_container *
4300 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4301 uint32_t batch, uint32_t age)
4303 struct mlx5_priv *priv = dev->data->dev_private;
4304 struct mlx5_flow_counter_pool *pool;
4305 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4307 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4308 uint32_t size = sizeof(*pool);
4310 if (cont->n == n_valid) {
4311 cont = flow_dv_container_resize(dev, batch, age);
4315 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4316 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4317 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4318 pool = rte_calloc(__func__, 1, size, 0);
4323 pool->min_dcs = dcs;
4324 if (!priv->counter_fallback)
4325 pool->raw = cont->init_mem_mng->raws + n_valid %
4326 MLX5_CNT_CONTAINER_RESIZE;
4327 pool->raw_hw = NULL;
4329 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4330 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4331 rte_spinlock_init(&pool->sl);
4333 * The generation of the new allocated counters in this pool is 0, 2 in
4334 * the pool generation makes all the counters valid for allocation.
4335 * The start and end query generation protect the counters be released
4336 * between the query and update gap period will not be reallocated
4337 * without the last query finished and stats updated to the memory.
4339 rte_atomic64_set(&pool->start_query_gen, 0x2);
4341 * There's no background query thread for fallback mode, set the
4342 * end_query_gen to the maximum value since no need to wait for
4343 * statistics update.
4345 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4347 TAILQ_INIT(&pool->counters);
4348 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4349 pool->index = n_valid;
4350 cont->pools[n_valid] = pool;
4351 /* Pool initialization must be updated before host thread access. */
4353 rte_atomic16_add(&cont->n_valid, 1);
4358 * Update the minimum dcs-id for aged or no-aged counter pool.
4361 * Pointer to the Ethernet device structure.
4363 * Current counter pool.
4365 * Whether the pool is for counter that was allocated by batch command.
4367 * Whether the counter is for aging.
4370 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4371 struct mlx5_flow_counter_pool *pool,
4372 uint32_t batch, uint32_t age)
4374 struct mlx5_priv *priv = dev->data->dev_private;
4375 struct mlx5_flow_counter_pool *other;
4376 struct mlx5_pools_container *cont;
4378 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4379 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4382 if (pool->min_dcs->id < other->min_dcs->id) {
4383 rte_atomic64_set(&other->a64_dcs,
4384 rte_atomic64_read(&pool->a64_dcs));
4386 rte_atomic64_set(&pool->a64_dcs,
4387 rte_atomic64_read(&other->a64_dcs));
4391 * Prepare a new counter and/or a new counter pool.
4394 * Pointer to the Ethernet device structure.
4395 * @param[out] cnt_free
4396 * Where to put the pointer of a new counter.
4398 * Whether the pool is for counter that was allocated by batch command.
4400 * Whether the pool is for counter that was allocated for aging.
4403 * The counter container pointer and @p cnt_free is set on success,
4404 * NULL otherwise and rte_errno is set.
4406 static struct mlx5_pools_container *
4407 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4408 struct mlx5_flow_counter **cnt_free,
4409 uint32_t batch, uint32_t age)
4411 struct mlx5_priv *priv = dev->data->dev_private;
4412 struct mlx5_pools_container *cont;
4413 struct mlx5_flow_counter_pool *pool;
4414 struct mlx5_devx_obj *dcs = NULL;
4415 struct mlx5_flow_counter *cnt;
4418 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4420 /* bulk_bitmap must be 0 for single counter allocation. */
4421 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4424 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4426 cont = flow_dv_pool_create(dev, dcs, batch, age);
4428 mlx5_devx_cmd_destroy(dcs);
4431 pool = TAILQ_FIRST(&cont->pool_list);
4432 } else if (dcs->id < pool->min_dcs->id) {
4433 rte_atomic64_set(&pool->a64_dcs,
4434 (int64_t)(uintptr_t)dcs);
4436 flow_dv_counter_update_min_dcs(dev,
4438 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4439 cnt = MLX5_POOL_GET_CNT(pool, i);
4440 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4441 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4445 /* bulk_bitmap is in 128 counters units. */
4446 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4447 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4449 rte_errno = ENODATA;
4452 cont = flow_dv_pool_create(dev, dcs, batch, age);
4454 mlx5_devx_cmd_destroy(dcs);
4457 pool = TAILQ_FIRST(&cont->pool_list);
4458 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4459 cnt = MLX5_POOL_GET_CNT(pool, i);
4460 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4462 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4467 * Search for existed shared counter.
4470 * Pointer to the relevant counter pool container.
4472 * The shared counter ID to search.
4474 * mlx5 flow counter pool in the container,
4477 * NULL if not existed, otherwise pointer to the shared extend counter.
4479 static struct mlx5_flow_counter_ext *
4480 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4481 struct mlx5_flow_counter_pool **ppool)
4483 static struct mlx5_flow_counter_ext *cnt;
4484 struct mlx5_flow_counter_pool *pool;
4486 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4488 for (i = 0; i < n_valid; i++) {
4489 pool = cont->pools[i];
4490 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4491 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4492 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4494 *ppool = cont->pools[i];
4503 * Allocate a flow counter.
4506 * Pointer to the Ethernet device structure.
4508 * Indicate if this counter is shared with other flows.
4510 * Counter identifier.
4512 * Counter flow group.
4514 * Whether the counter was allocated for aging.
4517 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4520 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4521 uint16_t group, uint32_t age)
4523 struct mlx5_priv *priv = dev->data->dev_private;
4524 struct mlx5_flow_counter_pool *pool = NULL;
4525 struct mlx5_flow_counter *cnt_free = NULL;
4526 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4528 * Currently group 0 flow counter cannot be assigned to a flow if it is
4529 * not the first one in the batch counter allocation, so it is better
4530 * to allocate counters one by one for these flows in a separate
4532 * A counter can be shared between different groups so need to take
4533 * shared counters from the single container.
4535 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4536 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4540 if (!priv->config.devx) {
4541 rte_errno = ENOTSUP;
4545 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4547 if (cnt_ext->ref_cnt + 1 == 0) {
4552 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4553 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4558 /* Pools which has a free counters are in the start. */
4559 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4561 * The free counter reset values must be updated between the
4562 * counter release to the counter allocation, so, at least one
4563 * query must be done in this time. ensure it by saving the
4564 * query generation in the release time.
4565 * The free list is sorted according to the generation - so if
4566 * the first one is not updated, all the others are not
4569 cnt_free = TAILQ_FIRST(&pool->counters);
4570 if (cnt_free && cnt_free->query_gen <
4571 rte_atomic64_read(&pool->end_query_gen))
4576 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4579 pool = TAILQ_FIRST(&cont->pool_list);
4582 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4583 /* Create a DV counter action only in the first time usage. */
4584 if (!cnt_free->action) {
4586 struct mlx5_devx_obj *dcs;
4589 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4590 dcs = pool->min_dcs;
4595 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4597 if (!cnt_free->action) {
4602 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4603 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4604 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4605 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4606 /* Update the counter reset values. */
4607 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4611 cnt_ext->shared = shared;
4612 cnt_ext->ref_cnt = 1;
4615 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4616 /* Start the asynchronous batch query by the host thread. */
4617 mlx5_set_query_alarm(priv->sh);
4618 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4619 if (TAILQ_EMPTY(&pool->counters)) {
4620 /* Move the pool to the end of the container pool list. */
4621 TAILQ_REMOVE(&cont->pool_list, pool, next);
4622 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4628 * Get age param from counter index.
4631 * Pointer to the Ethernet device structure.
4632 * @param[in] counter
4633 * Index to the counter handler.
4636 * The aging parameter specified for the counter index.
4638 static struct mlx5_age_param*
4639 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4642 struct mlx5_flow_counter *cnt;
4643 struct mlx5_flow_counter_pool *pool = NULL;
4645 flow_dv_counter_get_by_idx(dev, counter, &pool);
4646 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4647 cnt = MLX5_POOL_GET_CNT(pool, counter);
4648 return MLX5_CNT_TO_AGE(cnt);
4652 * Remove a flow counter from aged counter list.
4655 * Pointer to the Ethernet device structure.
4656 * @param[in] counter
4657 * Index to the counter handler.
4659 * Pointer to the counter handler.
4662 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4663 uint32_t counter, struct mlx5_flow_counter *cnt)
4665 struct mlx5_age_info *age_info;
4666 struct mlx5_age_param *age_param;
4667 struct mlx5_priv *priv = dev->data->dev_private;
4669 age_info = GET_PORT_AGE_INFO(priv);
4670 age_param = flow_dv_counter_idx_get_age(dev, counter);
4671 if (rte_atomic16_cmpset((volatile uint16_t *)
4673 AGE_CANDIDATE, AGE_FREE)
4676 * We need the lock even it is age timeout,
4677 * since counter may still in process.
4679 rte_spinlock_lock(&age_info->aged_sl);
4680 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4681 rte_spinlock_unlock(&age_info->aged_sl);
4683 rte_atomic16_set(&age_param->state, AGE_FREE);
4686 * Release a flow counter.
4689 * Pointer to the Ethernet device structure.
4690 * @param[in] counter
4691 * Index to the counter handler.
4694 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4696 struct mlx5_flow_counter_pool *pool = NULL;
4697 struct mlx5_flow_counter *cnt;
4698 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4702 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4704 if (counter < MLX5_CNT_BATCH_OFFSET) {
4705 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4706 if (cnt_ext && --cnt_ext->ref_cnt)
4709 if (IS_AGE_POOL(pool))
4710 flow_dv_counter_remove_from_age(dev, counter, cnt);
4711 /* Put the counter in the end - the last updated one. */
4712 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4714 * Counters released between query trigger and handler need
4715 * to wait the next round of query. Since the packets arrive
4716 * in the gap period will not be taken into account to the
4719 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4723 * Verify the @p attributes will be correctly understood by the NIC and store
4724 * them in the @p flow if everything is correct.
4727 * Pointer to dev struct.
4728 * @param[in] attributes
4729 * Pointer to flow attributes
4730 * @param[in] external
4731 * This flow rule is created by request external to PMD.
4733 * Pointer to error structure.
4736 * - 0 on success and non root table.
4737 * - 1 on success and root table.
4738 * - a negative errno value otherwise and rte_errno is set.
4741 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4742 const struct rte_flow_attr *attributes,
4743 bool external __rte_unused,
4744 struct rte_flow_error *error)
4746 struct mlx5_priv *priv = dev->data->dev_private;
4747 uint32_t priority_max = priv->config.flow_prio - 1;
4750 #ifndef HAVE_MLX5DV_DR
4751 if (attributes->group)
4752 return rte_flow_error_set(error, ENOTSUP,
4753 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4755 "groups are not supported");
4759 ret = mlx5_flow_group_to_table(attributes, external,
4760 attributes->group, !!priv->fdb_def_rule,
4765 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4767 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4768 attributes->priority >= priority_max)
4769 return rte_flow_error_set(error, ENOTSUP,
4770 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4772 "priority out of range");
4773 if (attributes->transfer) {
4774 if (!priv->config.dv_esw_en)
4775 return rte_flow_error_set
4777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4778 "E-Switch dr is not supported");
4779 if (!(priv->representor || priv->master))
4780 return rte_flow_error_set
4781 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4782 NULL, "E-Switch configuration can only be"
4783 " done by a master or a representor device");
4784 if (attributes->egress)
4785 return rte_flow_error_set
4787 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4788 "egress is not supported");
4790 if (!(attributes->egress ^ attributes->ingress))
4791 return rte_flow_error_set(error, ENOTSUP,
4792 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4793 "must specify exactly one of "
4794 "ingress or egress");
4799 * Internal validation function. For validating both actions and items.
4802 * Pointer to the rte_eth_dev structure.
4804 * Pointer to the flow attributes.
4806 * Pointer to the list of items.
4807 * @param[in] actions
4808 * Pointer to the list of actions.
4809 * @param[in] external
4810 * This flow rule is created by request external to PMD.
4811 * @param[in] hairpin
4812 * Number of hairpin TX actions, 0 means classic flow.
4814 * Pointer to the error structure.
4817 * 0 on success, a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4821 const struct rte_flow_item items[],
4822 const struct rte_flow_action actions[],
4823 bool external, int hairpin, struct rte_flow_error *error)
4826 uint64_t action_flags = 0;
4827 uint64_t item_flags = 0;
4828 uint64_t last_item = 0;
4829 uint8_t next_protocol = 0xff;
4830 uint16_t ether_type = 0;
4832 uint8_t item_ipv6_proto = 0;
4833 const struct rte_flow_item *gre_item = NULL;
4834 const struct rte_flow_action_raw_decap *decap;
4835 const struct rte_flow_action_raw_encap *encap;
4836 const struct rte_flow_action_rss *rss;
4837 const struct rte_flow_item_tcp nic_tcp_mask = {
4840 .src_port = RTE_BE16(UINT16_MAX),
4841 .dst_port = RTE_BE16(UINT16_MAX),
4844 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4846 .src_addr = RTE_BE32(0xffffffff),
4847 .dst_addr = RTE_BE32(0xffffffff),
4848 .type_of_service = 0xff,
4849 .next_proto_id = 0xff,
4850 .time_to_live = 0xff,
4853 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4856 "\xff\xff\xff\xff\xff\xff\xff\xff"
4857 "\xff\xff\xff\xff\xff\xff\xff\xff",
4859 "\xff\xff\xff\xff\xff\xff\xff\xff"
4860 "\xff\xff\xff\xff\xff\xff\xff\xff",
4861 .vtc_flow = RTE_BE32(0xffffffff),
4866 struct mlx5_priv *priv = dev->data->dev_private;
4867 struct mlx5_dev_config *dev_conf = &priv->config;
4868 uint16_t queue_index = 0xFFFF;
4869 const struct rte_flow_item_vlan *vlan_m = NULL;
4870 int16_t rw_act_num = 0;
4875 ret = flow_dv_validate_attributes(dev, attr, external, error);
4878 is_root = (uint64_t)ret;
4879 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4880 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4881 int type = items->type;
4884 case RTE_FLOW_ITEM_TYPE_VOID:
4886 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4887 ret = flow_dv_validate_item_port_id
4888 (dev, items, attr, item_flags, error);
4891 last_item = MLX5_FLOW_ITEM_PORT_ID;
4893 case RTE_FLOW_ITEM_TYPE_ETH:
4894 ret = mlx5_flow_validate_item_eth(items, item_flags,
4898 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4899 MLX5_FLOW_LAYER_OUTER_L2;
4900 if (items->mask != NULL && items->spec != NULL) {
4902 ((const struct rte_flow_item_eth *)
4905 ((const struct rte_flow_item_eth *)
4907 ether_type = rte_be_to_cpu_16(ether_type);
4912 case RTE_FLOW_ITEM_TYPE_VLAN:
4913 ret = flow_dv_validate_item_vlan(items, item_flags,
4917 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4918 MLX5_FLOW_LAYER_OUTER_VLAN;
4919 if (items->mask != NULL && items->spec != NULL) {
4921 ((const struct rte_flow_item_vlan *)
4922 items->spec)->inner_type;
4924 ((const struct rte_flow_item_vlan *)
4925 items->mask)->inner_type;
4926 ether_type = rte_be_to_cpu_16(ether_type);
4930 /* Store outer VLAN mask for of_push_vlan action. */
4932 vlan_m = items->mask;
4934 case RTE_FLOW_ITEM_TYPE_IPV4:
4935 mlx5_flow_tunnel_ip_check(items, next_protocol,
4936 &item_flags, &tunnel);
4937 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4944 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4945 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4946 if (items->mask != NULL &&
4947 ((const struct rte_flow_item_ipv4 *)
4948 items->mask)->hdr.next_proto_id) {
4950 ((const struct rte_flow_item_ipv4 *)
4951 (items->spec))->hdr.next_proto_id;
4953 ((const struct rte_flow_item_ipv4 *)
4954 (items->mask))->hdr.next_proto_id;
4956 /* Reset for inner layer. */
4957 next_protocol = 0xff;
4960 case RTE_FLOW_ITEM_TYPE_IPV6:
4961 mlx5_flow_tunnel_ip_check(items, next_protocol,
4962 &item_flags, &tunnel);
4963 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4970 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4971 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4972 if (items->mask != NULL &&
4973 ((const struct rte_flow_item_ipv6 *)
4974 items->mask)->hdr.proto) {
4976 ((const struct rte_flow_item_ipv6 *)
4977 items->spec)->hdr.proto;
4979 ((const struct rte_flow_item_ipv6 *)
4980 items->spec)->hdr.proto;
4982 ((const struct rte_flow_item_ipv6 *)
4983 items->mask)->hdr.proto;
4985 /* Reset for inner layer. */
4986 next_protocol = 0xff;
4989 case RTE_FLOW_ITEM_TYPE_TCP:
4990 ret = mlx5_flow_validate_item_tcp
4997 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4998 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5000 case RTE_FLOW_ITEM_TYPE_UDP:
5001 ret = mlx5_flow_validate_item_udp(items, item_flags,
5006 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5007 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5009 case RTE_FLOW_ITEM_TYPE_GRE:
5010 ret = mlx5_flow_validate_item_gre(items, item_flags,
5011 next_protocol, error);
5015 last_item = MLX5_FLOW_LAYER_GRE;
5017 case RTE_FLOW_ITEM_TYPE_NVGRE:
5018 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5023 last_item = MLX5_FLOW_LAYER_NVGRE;
5025 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5026 ret = mlx5_flow_validate_item_gre_key
5027 (items, item_flags, gre_item, error);
5030 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5032 case RTE_FLOW_ITEM_TYPE_VXLAN:
5033 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5037 last_item = MLX5_FLOW_LAYER_VXLAN;
5039 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5040 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5045 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5047 case RTE_FLOW_ITEM_TYPE_GENEVE:
5048 ret = mlx5_flow_validate_item_geneve(items,
5053 last_item = MLX5_FLOW_LAYER_GENEVE;
5055 case RTE_FLOW_ITEM_TYPE_MPLS:
5056 ret = mlx5_flow_validate_item_mpls(dev, items,
5061 last_item = MLX5_FLOW_LAYER_MPLS;
5064 case RTE_FLOW_ITEM_TYPE_MARK:
5065 ret = flow_dv_validate_item_mark(dev, items, attr,
5069 last_item = MLX5_FLOW_ITEM_MARK;
5071 case RTE_FLOW_ITEM_TYPE_META:
5072 ret = flow_dv_validate_item_meta(dev, items, attr,
5076 last_item = MLX5_FLOW_ITEM_METADATA;
5078 case RTE_FLOW_ITEM_TYPE_ICMP:
5079 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5084 last_item = MLX5_FLOW_LAYER_ICMP;
5086 case RTE_FLOW_ITEM_TYPE_ICMP6:
5087 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5092 item_ipv6_proto = IPPROTO_ICMPV6;
5093 last_item = MLX5_FLOW_LAYER_ICMP6;
5095 case RTE_FLOW_ITEM_TYPE_TAG:
5096 ret = flow_dv_validate_item_tag(dev, items,
5100 last_item = MLX5_FLOW_ITEM_TAG;
5102 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5103 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5105 case RTE_FLOW_ITEM_TYPE_GTP:
5106 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5110 last_item = MLX5_FLOW_LAYER_GTP;
5113 return rte_flow_error_set(error, ENOTSUP,
5114 RTE_FLOW_ERROR_TYPE_ITEM,
5115 NULL, "item not supported");
5117 item_flags |= last_item;
5119 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5120 int type = actions->type;
5121 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5122 return rte_flow_error_set(error, ENOTSUP,
5123 RTE_FLOW_ERROR_TYPE_ACTION,
5124 actions, "too many actions");
5126 case RTE_FLOW_ACTION_TYPE_VOID:
5128 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5129 ret = flow_dv_validate_action_port_id(dev,
5136 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5139 case RTE_FLOW_ACTION_TYPE_FLAG:
5140 ret = flow_dv_validate_action_flag(dev, action_flags,
5144 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5145 /* Count all modify-header actions as one. */
5146 if (!(action_flags &
5147 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5149 action_flags |= MLX5_FLOW_ACTION_FLAG |
5150 MLX5_FLOW_ACTION_MARK_EXT;
5152 action_flags |= MLX5_FLOW_ACTION_FLAG;
5155 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5157 case RTE_FLOW_ACTION_TYPE_MARK:
5158 ret = flow_dv_validate_action_mark(dev, actions,
5163 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5164 /* Count all modify-header actions as one. */
5165 if (!(action_flags &
5166 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5168 action_flags |= MLX5_FLOW_ACTION_MARK |
5169 MLX5_FLOW_ACTION_MARK_EXT;
5171 action_flags |= MLX5_FLOW_ACTION_MARK;
5174 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5176 case RTE_FLOW_ACTION_TYPE_SET_META:
5177 ret = flow_dv_validate_action_set_meta(dev, actions,
5182 /* Count all modify-header actions as one action. */
5183 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5185 action_flags |= MLX5_FLOW_ACTION_SET_META;
5186 rw_act_num += MLX5_ACT_NUM_SET_META;
5188 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5189 ret = flow_dv_validate_action_set_tag(dev, actions,
5194 /* Count all modify-header actions as one action. */
5195 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5197 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5198 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5200 case RTE_FLOW_ACTION_TYPE_DROP:
5201 ret = mlx5_flow_validate_action_drop(action_flags,
5205 action_flags |= MLX5_FLOW_ACTION_DROP;
5208 case RTE_FLOW_ACTION_TYPE_QUEUE:
5209 ret = mlx5_flow_validate_action_queue(actions,
5214 queue_index = ((const struct rte_flow_action_queue *)
5215 (actions->conf))->index;
5216 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5219 case RTE_FLOW_ACTION_TYPE_RSS:
5220 rss = actions->conf;
5221 ret = mlx5_flow_validate_action_rss(actions,
5227 if (rss != NULL && rss->queue_num)
5228 queue_index = rss->queue[0];
5229 action_flags |= MLX5_FLOW_ACTION_RSS;
5232 case RTE_FLOW_ACTION_TYPE_COUNT:
5233 ret = flow_dv_validate_action_count(dev, error);
5236 action_flags |= MLX5_FLOW_ACTION_COUNT;
5239 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5240 if (flow_dv_validate_action_pop_vlan(dev,
5246 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5249 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5250 ret = flow_dv_validate_action_push_vlan(dev,
5257 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5260 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5261 ret = flow_dv_validate_action_set_vlan_pcp
5262 (action_flags, actions, error);
5265 /* Count PCP with push_vlan command. */
5266 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5268 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5269 ret = flow_dv_validate_action_set_vlan_vid
5270 (item_flags, action_flags,
5274 /* Count VID with push_vlan command. */
5275 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5276 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5278 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5279 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5280 ret = flow_dv_validate_action_l2_encap(dev,
5286 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5289 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5290 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5291 ret = flow_dv_validate_action_decap(dev, action_flags,
5295 action_flags |= MLX5_FLOW_ACTION_DECAP;
5298 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5299 ret = flow_dv_validate_action_raw_encap_decap
5300 (dev, NULL, actions->conf, attr, &action_flags,
5305 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5306 decap = actions->conf;
5307 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5309 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5313 encap = actions->conf;
5315 ret = flow_dv_validate_action_raw_encap_decap
5317 decap ? decap : &empty_decap, encap,
5318 attr, &action_flags, &actions_n,
5323 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5324 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5325 ret = flow_dv_validate_action_modify_mac(action_flags,
5331 /* Count all modify-header actions as one action. */
5332 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5334 action_flags |= actions->type ==
5335 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5336 MLX5_FLOW_ACTION_SET_MAC_SRC :
5337 MLX5_FLOW_ACTION_SET_MAC_DST;
5339 * Even if the source and destination MAC addresses have
5340 * overlap in the header with 4B alignment, the convert
5341 * function will handle them separately and 4 SW actions
5342 * will be created. And 2 actions will be added each
5343 * time no matter how many bytes of address will be set.
5345 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5347 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5348 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5349 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5355 /* Count all modify-header actions as one action. */
5356 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5358 action_flags |= actions->type ==
5359 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5360 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5361 MLX5_FLOW_ACTION_SET_IPV4_DST;
5362 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5364 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5365 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5366 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5372 if (item_ipv6_proto == IPPROTO_ICMPV6)
5373 return rte_flow_error_set(error, ENOTSUP,
5374 RTE_FLOW_ERROR_TYPE_ACTION,
5376 "Can't change header "
5377 "with ICMPv6 proto");
5378 /* Count all modify-header actions as one action. */
5379 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5381 action_flags |= actions->type ==
5382 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5383 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5384 MLX5_FLOW_ACTION_SET_IPV6_DST;
5385 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5387 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5388 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5389 ret = flow_dv_validate_action_modify_tp(action_flags,
5395 /* Count all modify-header actions as one action. */
5396 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5398 action_flags |= actions->type ==
5399 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5400 MLX5_FLOW_ACTION_SET_TP_SRC :
5401 MLX5_FLOW_ACTION_SET_TP_DST;
5402 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5404 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5405 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5406 ret = flow_dv_validate_action_modify_ttl(action_flags,
5412 /* Count all modify-header actions as one action. */
5413 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5415 action_flags |= actions->type ==
5416 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5417 MLX5_FLOW_ACTION_SET_TTL :
5418 MLX5_FLOW_ACTION_DEC_TTL;
5419 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5421 case RTE_FLOW_ACTION_TYPE_JUMP:
5422 ret = flow_dv_validate_action_jump(actions,
5429 action_flags |= MLX5_FLOW_ACTION_JUMP;
5431 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5432 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5433 ret = flow_dv_validate_action_modify_tcp_seq
5440 /* Count all modify-header actions as one action. */
5441 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5443 action_flags |= actions->type ==
5444 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5445 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5446 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5447 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5449 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5450 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5451 ret = flow_dv_validate_action_modify_tcp_ack
5458 /* Count all modify-header actions as one action. */
5459 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5461 action_flags |= actions->type ==
5462 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5463 MLX5_FLOW_ACTION_INC_TCP_ACK :
5464 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5465 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5467 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5469 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5470 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5471 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5473 case RTE_FLOW_ACTION_TYPE_METER:
5474 ret = mlx5_flow_validate_action_meter(dev,
5480 action_flags |= MLX5_FLOW_ACTION_METER;
5482 /* Meter action will add one more TAG action. */
5483 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5485 case RTE_FLOW_ACTION_TYPE_AGE:
5486 ret = flow_dv_validate_action_age(action_flags,
5491 action_flags |= MLX5_FLOW_ACTION_AGE;
5494 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5495 ret = flow_dv_validate_action_modify_ipv4_dscp
5502 /* Count all modify-header actions as one action. */
5503 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5505 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5506 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5508 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5509 ret = flow_dv_validate_action_modify_ipv6_dscp
5516 /* Count all modify-header actions as one action. */
5517 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5519 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5520 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5523 return rte_flow_error_set(error, ENOTSUP,
5524 RTE_FLOW_ERROR_TYPE_ACTION,
5526 "action not supported");
5530 * Validate the drop action mutual exclusion with other actions.
5531 * Drop action is mutually-exclusive with any other action, except for
5534 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5535 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5536 return rte_flow_error_set(error, EINVAL,
5537 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5538 "Drop action is mutually-exclusive "
5539 "with any other action, except for "
5541 /* Eswitch has few restrictions on using items and actions */
5542 if (attr->transfer) {
5543 if (!mlx5_flow_ext_mreg_supported(dev) &&
5544 action_flags & MLX5_FLOW_ACTION_FLAG)
5545 return rte_flow_error_set(error, ENOTSUP,
5546 RTE_FLOW_ERROR_TYPE_ACTION,
5548 "unsupported action FLAG");
5549 if (!mlx5_flow_ext_mreg_supported(dev) &&
5550 action_flags & MLX5_FLOW_ACTION_MARK)
5551 return rte_flow_error_set(error, ENOTSUP,
5552 RTE_FLOW_ERROR_TYPE_ACTION,
5554 "unsupported action MARK");
5555 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5556 return rte_flow_error_set(error, ENOTSUP,
5557 RTE_FLOW_ERROR_TYPE_ACTION,
5559 "unsupported action QUEUE");
5560 if (action_flags & MLX5_FLOW_ACTION_RSS)
5561 return rte_flow_error_set(error, ENOTSUP,
5562 RTE_FLOW_ERROR_TYPE_ACTION,
5564 "unsupported action RSS");
5565 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5566 return rte_flow_error_set(error, EINVAL,
5567 RTE_FLOW_ERROR_TYPE_ACTION,
5569 "no fate action is found");
5571 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5572 return rte_flow_error_set(error, EINVAL,
5573 RTE_FLOW_ERROR_TYPE_ACTION,
5575 "no fate action is found");
5577 /* Continue validation for Xcap actions.*/
5578 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5579 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5580 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5581 MLX5_FLOW_XCAP_ACTIONS)
5582 return rte_flow_error_set(error, ENOTSUP,
5583 RTE_FLOW_ERROR_TYPE_ACTION,
5584 NULL, "encap and decap "
5585 "combination aren't supported");
5586 if (!attr->transfer && attr->ingress && (action_flags &
5587 MLX5_FLOW_ACTION_ENCAP))
5588 return rte_flow_error_set(error, ENOTSUP,
5589 RTE_FLOW_ERROR_TYPE_ACTION,
5590 NULL, "encap is not supported"
5591 " for ingress traffic");
5593 /* Hairpin flow will add one more TAG action. */
5595 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5596 /* extra metadata enabled: one more TAG action will be add. */
5597 if (dev_conf->dv_flow_en &&
5598 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5599 mlx5_flow_ext_mreg_supported(dev))
5600 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5601 if ((uint32_t)rw_act_num >
5602 flow_dv_modify_hdr_action_max(dev, is_root)) {
5603 return rte_flow_error_set(error, ENOTSUP,
5604 RTE_FLOW_ERROR_TYPE_ACTION,
5605 NULL, "too many header modify"
5606 " actions to support");
5612 * Internal preparation function. Allocates the DV flow size,
5613 * this size is constant.
5616 * Pointer to the rte_eth_dev structure.
5618 * Pointer to the flow attributes.
5620 * Pointer to the list of items.
5621 * @param[in] actions
5622 * Pointer to the list of actions.
5624 * Pointer to the error structure.
5627 * Pointer to mlx5_flow object on success,
5628 * otherwise NULL and rte_errno is set.
5630 static struct mlx5_flow *
5631 flow_dv_prepare(struct rte_eth_dev *dev,
5632 const struct rte_flow_attr *attr __rte_unused,
5633 const struct rte_flow_item items[] __rte_unused,
5634 const struct rte_flow_action actions[] __rte_unused,
5635 struct rte_flow_error *error)
5637 uint32_t handle_idx = 0;
5638 struct mlx5_flow *dev_flow;
5639 struct mlx5_flow_handle *dev_handle;
5640 struct mlx5_priv *priv = dev->data->dev_private;
5642 /* In case of corrupting the memory. */
5643 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5644 rte_flow_error_set(error, ENOSPC,
5645 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5646 "not free temporary device flow");
5649 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5652 rte_flow_error_set(error, ENOMEM,
5653 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5654 "not enough memory to create flow handle");
5657 /* No multi-thread supporting. */
5658 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5659 dev_flow->handle = dev_handle;
5660 dev_flow->handle_idx = handle_idx;
5661 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5663 * The matching value needs to be cleared to 0 before using. In the
5664 * past, it will be automatically cleared when using rte_*alloc
5665 * API. The time consumption will be almost the same as before.
5667 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5668 dev_flow->ingress = attr->ingress;
5669 dev_flow->dv.transfer = attr->transfer;
5673 #ifdef RTE_LIBRTE_MLX5_DEBUG
5675 * Sanity check for match mask and value. Similar to check_valid_spec() in
5676 * kernel driver. If unmasked bit is present in value, it returns failure.
5679 * pointer to match mask buffer.
5680 * @param match_value
5681 * pointer to match value buffer.
5684 * 0 if valid, -EINVAL otherwise.
5687 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5689 uint8_t *m = match_mask;
5690 uint8_t *v = match_value;
5693 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5696 "match_value differs from match_criteria"
5697 " %p[%u] != %p[%u]",
5698 match_value, i, match_mask, i);
5707 * Add match of ip_version.
5711 * @param[in] headers_v
5712 * Values header pointer.
5713 * @param[in] headers_m
5714 * Masks header pointer.
5715 * @param[in] ip_version
5716 * The IP version to set.
5719 flow_dv_set_match_ip_version(uint32_t group,
5725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5729 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5731 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5735 * Add Ethernet item to matcher and to the value.
5737 * @param[in, out] matcher
5739 * @param[in, out] key
5740 * Flow matcher value.
5742 * Flow pattern to translate.
5744 * Item is inner pattern.
5747 flow_dv_translate_item_eth(void *matcher, void *key,
5748 const struct rte_flow_item *item, int inner,
5751 const struct rte_flow_item_eth *eth_m = item->mask;
5752 const struct rte_flow_item_eth *eth_v = item->spec;
5753 const struct rte_flow_item_eth nic_mask = {
5754 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5755 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5756 .type = RTE_BE16(0xffff),
5768 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5770 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5772 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5774 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5776 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5777 ð_m->dst, sizeof(eth_m->dst));
5778 /* The value must be in the range of the mask. */
5779 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5780 for (i = 0; i < sizeof(eth_m->dst); ++i)
5781 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5782 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5783 ð_m->src, sizeof(eth_m->src));
5784 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5785 /* The value must be in the range of the mask. */
5786 for (i = 0; i < sizeof(eth_m->dst); ++i)
5787 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5789 /* When ethertype is present set mask for tagged VLAN. */
5790 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5791 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5792 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5793 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5794 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5796 /* Return here to avoid setting match on ethertype. */
5801 * HW supports match on one Ethertype, the Ethertype following the last
5802 * VLAN tag of the packet (see PRM).
5803 * Set match on ethertype only if ETH header is not followed by VLAN.
5804 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5805 * ethertype, and use ip_version field instead.
5807 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5808 eth_m->type == 0xFFFF) {
5809 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5810 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5811 eth_m->type == 0xFFFF) {
5812 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5814 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5815 rte_be_to_cpu_16(eth_m->type));
5816 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5818 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5823 * Add VLAN item to matcher and to the value.
5825 * @param[in, out] dev_flow
5827 * @param[in, out] matcher
5829 * @param[in, out] key
5830 * Flow matcher value.
5832 * Flow pattern to translate.
5834 * Item is inner pattern.
5837 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5838 void *matcher, void *key,
5839 const struct rte_flow_item *item,
5840 int inner, uint32_t group)
5842 const struct rte_flow_item_vlan *vlan_m = item->mask;
5843 const struct rte_flow_item_vlan *vlan_v = item->spec;
5850 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5852 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5854 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5856 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5858 * This is workaround, masks are not supported,
5859 * and pre-validated.
5862 dev_flow->handle->vf_vlan.tag =
5863 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5866 * When VLAN item exists in flow, mark packet as tagged,
5867 * even if TCI is not specified.
5869 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5870 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5874 vlan_m = &rte_flow_item_vlan_mask;
5875 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5876 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5877 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5878 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5879 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5880 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5881 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5882 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5884 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5885 * ethertype, and use ip_version field instead.
5887 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5888 vlan_m->inner_type == 0xFFFF) {
5889 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5890 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5891 vlan_m->inner_type == 0xFFFF) {
5892 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5894 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5895 rte_be_to_cpu_16(vlan_m->inner_type));
5896 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5897 rte_be_to_cpu_16(vlan_m->inner_type &
5898 vlan_v->inner_type));
5903 * Add IPV4 item to matcher and to the value.
5905 * @param[in, out] matcher
5907 * @param[in, out] key
5908 * Flow matcher value.
5910 * Flow pattern to translate.
5911 * @param[in] item_flags
5912 * Bit-fields that holds the items detected until now.
5914 * Item is inner pattern.
5916 * The group to insert the rule.
5919 flow_dv_translate_item_ipv4(void *matcher, void *key,
5920 const struct rte_flow_item *item,
5921 const uint64_t item_flags,
5922 int inner, uint32_t group)
5924 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5925 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5926 const struct rte_flow_item_ipv4 nic_mask = {
5928 .src_addr = RTE_BE32(0xffffffff),
5929 .dst_addr = RTE_BE32(0xffffffff),
5930 .type_of_service = 0xff,
5931 .next_proto_id = 0xff,
5932 .time_to_live = 0xff,
5942 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5944 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5946 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5948 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5950 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5952 * On outer header (which must contains L2), or inner header with L2,
5953 * set cvlan_tag mask bit to mark this packet as untagged.
5954 * This should be done even if item->spec is empty.
5956 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5957 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5962 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5963 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5964 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5965 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5966 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5967 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5968 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5969 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5970 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5971 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5972 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5973 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5974 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5975 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5976 ipv4_m->hdr.type_of_service);
5977 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5978 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5979 ipv4_m->hdr.type_of_service >> 2);
5980 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5981 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5982 ipv4_m->hdr.next_proto_id);
5983 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5984 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5985 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5986 ipv4_m->hdr.time_to_live);
5987 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5988 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5992 * Add IPV6 item to matcher and to the value.
5994 * @param[in, out] matcher
5996 * @param[in, out] key
5997 * Flow matcher value.
5999 * Flow pattern to translate.
6000 * @param[in] item_flags
6001 * Bit-fields that holds the items detected until now.
6003 * Item is inner pattern.
6005 * The group to insert the rule.
6008 flow_dv_translate_item_ipv6(void *matcher, void *key,
6009 const struct rte_flow_item *item,
6010 const uint64_t item_flags,
6011 int inner, uint32_t group)
6013 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6014 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6015 const struct rte_flow_item_ipv6 nic_mask = {
6018 "\xff\xff\xff\xff\xff\xff\xff\xff"
6019 "\xff\xff\xff\xff\xff\xff\xff\xff",
6021 "\xff\xff\xff\xff\xff\xff\xff\xff"
6022 "\xff\xff\xff\xff\xff\xff\xff\xff",
6023 .vtc_flow = RTE_BE32(0xffffffff),
6030 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6031 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6040 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6042 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6044 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6046 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6048 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6050 * On outer header (which must contains L2), or inner header with L2,
6051 * set cvlan_tag mask bit to mark this packet as untagged.
6052 * This should be done even if item->spec is empty.
6054 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6055 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6060 size = sizeof(ipv6_m->hdr.dst_addr);
6061 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6062 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6063 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6064 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6065 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6066 for (i = 0; i < size; ++i)
6067 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6068 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6069 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6070 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6071 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6072 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6073 for (i = 0; i < size; ++i)
6074 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6076 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6077 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6078 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6079 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6080 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6081 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6084 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6086 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6089 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6091 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6095 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6097 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6098 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6101 ipv6_m->hdr.hop_limits);
6102 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6103 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6107 * Add TCP item to matcher and to the value.
6109 * @param[in, out] matcher
6111 * @param[in, out] key
6112 * Flow matcher value.
6114 * Flow pattern to translate.
6116 * Item is inner pattern.
6119 flow_dv_translate_item_tcp(void *matcher, void *key,
6120 const struct rte_flow_item *item,
6123 const struct rte_flow_item_tcp *tcp_m = item->mask;
6124 const struct rte_flow_item_tcp *tcp_v = item->spec;
6129 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6131 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6133 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6135 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6137 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6138 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6142 tcp_m = &rte_flow_item_tcp_mask;
6143 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6144 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6145 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6146 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6147 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6148 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6149 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6150 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6151 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6152 tcp_m->hdr.tcp_flags);
6153 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6154 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6158 * Add UDP item to matcher and to the value.
6160 * @param[in, out] matcher
6162 * @param[in, out] key
6163 * Flow matcher value.
6165 * Flow pattern to translate.
6167 * Item is inner pattern.
6170 flow_dv_translate_item_udp(void *matcher, void *key,
6171 const struct rte_flow_item *item,
6174 const struct rte_flow_item_udp *udp_m = item->mask;
6175 const struct rte_flow_item_udp *udp_v = item->spec;
6180 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6182 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6184 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6186 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6188 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6189 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6193 udp_m = &rte_flow_item_udp_mask;
6194 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6195 rte_be_to_cpu_16(udp_m->hdr.src_port));
6196 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6197 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6198 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6199 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6200 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6201 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6205 * Add GRE optional Key item to matcher and to the value.
6207 * @param[in, out] matcher
6209 * @param[in, out] key
6210 * Flow matcher value.
6212 * Flow pattern to translate.
6214 * Item is inner pattern.
6217 flow_dv_translate_item_gre_key(void *matcher, void *key,
6218 const struct rte_flow_item *item)
6220 const rte_be32_t *key_m = item->mask;
6221 const rte_be32_t *key_v = item->spec;
6222 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6223 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6224 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6226 /* GRE K bit must be on and should already be validated */
6227 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6228 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6232 key_m = &gre_key_default_mask;
6233 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6234 rte_be_to_cpu_32(*key_m) >> 8);
6235 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6236 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6237 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6238 rte_be_to_cpu_32(*key_m) & 0xFF);
6239 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6240 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6244 * Add GRE item to matcher and to the value.
6246 * @param[in, out] matcher
6248 * @param[in, out] key
6249 * Flow matcher value.
6251 * Flow pattern to translate.
6253 * Item is inner pattern.
6256 flow_dv_translate_item_gre(void *matcher, void *key,
6257 const struct rte_flow_item *item,
6260 const struct rte_flow_item_gre *gre_m = item->mask;
6261 const struct rte_flow_item_gre *gre_v = item->spec;
6264 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6265 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6272 uint16_t s_present:1;
6273 uint16_t k_present:1;
6274 uint16_t rsvd_bit1:1;
6275 uint16_t c_present:1;
6279 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6282 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6284 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6286 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6288 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6290 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6291 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6295 gre_m = &rte_flow_item_gre_mask;
6296 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6297 rte_be_to_cpu_16(gre_m->protocol));
6298 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6299 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6300 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6301 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6302 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6303 gre_crks_rsvd0_ver_m.c_present);
6304 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6305 gre_crks_rsvd0_ver_v.c_present &
6306 gre_crks_rsvd0_ver_m.c_present);
6307 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6308 gre_crks_rsvd0_ver_m.k_present);
6309 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6310 gre_crks_rsvd0_ver_v.k_present &
6311 gre_crks_rsvd0_ver_m.k_present);
6312 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6313 gre_crks_rsvd0_ver_m.s_present);
6314 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6315 gre_crks_rsvd0_ver_v.s_present &
6316 gre_crks_rsvd0_ver_m.s_present);
6320 * Add NVGRE item to matcher and to the value.
6322 * @param[in, out] matcher
6324 * @param[in, out] key
6325 * Flow matcher value.
6327 * Flow pattern to translate.
6329 * Item is inner pattern.
6332 flow_dv_translate_item_nvgre(void *matcher, void *key,
6333 const struct rte_flow_item *item,
6336 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6337 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6338 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6339 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6340 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6341 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6347 /* For NVGRE, GRE header fields must be set with defined values. */
6348 const struct rte_flow_item_gre gre_spec = {
6349 .c_rsvd0_ver = RTE_BE16(0x2000),
6350 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6352 const struct rte_flow_item_gre gre_mask = {
6353 .c_rsvd0_ver = RTE_BE16(0xB000),
6354 .protocol = RTE_BE16(UINT16_MAX),
6356 const struct rte_flow_item gre_item = {
6361 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6365 nvgre_m = &rte_flow_item_nvgre_mask;
6366 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6367 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6368 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6369 memcpy(gre_key_m, tni_flow_id_m, size);
6370 for (i = 0; i < size; ++i)
6371 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6375 * Add VXLAN item to matcher and to the value.
6377 * @param[in, out] matcher
6379 * @param[in, out] key
6380 * Flow matcher value.
6382 * Flow pattern to translate.
6384 * Item is inner pattern.
6387 flow_dv_translate_item_vxlan(void *matcher, void *key,
6388 const struct rte_flow_item *item,
6391 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6392 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6395 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6396 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6404 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6406 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6408 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6410 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6412 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6413 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6414 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6415 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6416 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6421 vxlan_m = &rte_flow_item_vxlan_mask;
6422 size = sizeof(vxlan_m->vni);
6423 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6424 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6425 memcpy(vni_m, vxlan_m->vni, size);
6426 for (i = 0; i < size; ++i)
6427 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6431 * Add VXLAN-GPE item to matcher and to the value.
6433 * @param[in, out] matcher
6435 * @param[in, out] key
6436 * Flow matcher value.
6438 * Flow pattern to translate.
6440 * Item is inner pattern.
6444 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6445 const struct rte_flow_item *item, int inner)
6447 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6448 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6452 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6454 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6460 uint8_t flags_m = 0xff;
6461 uint8_t flags_v = 0xc;
6464 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6466 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6468 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6470 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6472 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6473 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6474 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6475 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6476 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6481 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6482 size = sizeof(vxlan_m->vni);
6483 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6484 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6485 memcpy(vni_m, vxlan_m->vni, size);
6486 for (i = 0; i < size; ++i)
6487 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6488 if (vxlan_m->flags) {
6489 flags_m = vxlan_m->flags;
6490 flags_v = vxlan_v->flags;
6492 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6493 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6494 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6496 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6501 * Add Geneve item to matcher and to the value.
6503 * @param[in, out] matcher
6505 * @param[in, out] key
6506 * Flow matcher value.
6508 * Flow pattern to translate.
6510 * Item is inner pattern.
6514 flow_dv_translate_item_geneve(void *matcher, void *key,
6515 const struct rte_flow_item *item, int inner)
6517 const struct rte_flow_item_geneve *geneve_m = item->mask;
6518 const struct rte_flow_item_geneve *geneve_v = item->spec;
6521 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6522 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6531 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6533 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6535 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6537 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6539 dport = MLX5_UDP_PORT_GENEVE;
6540 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6541 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6542 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6547 geneve_m = &rte_flow_item_geneve_mask;
6548 size = sizeof(geneve_m->vni);
6549 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6550 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6551 memcpy(vni_m, geneve_m->vni, size);
6552 for (i = 0; i < size; ++i)
6553 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6554 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6555 rte_be_to_cpu_16(geneve_m->protocol));
6556 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6557 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6558 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6559 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6560 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6561 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6562 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6563 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6564 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6565 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6566 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6567 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6568 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6572 * Add MPLS item to matcher and to the value.
6574 * @param[in, out] matcher
6576 * @param[in, out] key
6577 * Flow matcher value.
6579 * Flow pattern to translate.
6580 * @param[in] prev_layer
6581 * The protocol layer indicated in previous item.
6583 * Item is inner pattern.
6586 flow_dv_translate_item_mpls(void *matcher, void *key,
6587 const struct rte_flow_item *item,
6588 uint64_t prev_layer,
6591 const uint32_t *in_mpls_m = item->mask;
6592 const uint32_t *in_mpls_v = item->spec;
6593 uint32_t *out_mpls_m = 0;
6594 uint32_t *out_mpls_v = 0;
6595 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6596 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6597 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6599 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6600 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6601 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6603 switch (prev_layer) {
6604 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6605 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6606 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6607 MLX5_UDP_PORT_MPLS);
6609 case MLX5_FLOW_LAYER_GRE:
6610 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6611 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6612 RTE_ETHER_TYPE_MPLS);
6615 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6616 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6623 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6624 switch (prev_layer) {
6625 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6627 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6628 outer_first_mpls_over_udp);
6630 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6631 outer_first_mpls_over_udp);
6633 case MLX5_FLOW_LAYER_GRE:
6635 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6636 outer_first_mpls_over_gre);
6638 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6639 outer_first_mpls_over_gre);
6642 /* Inner MPLS not over GRE is not supported. */
6645 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6649 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6655 if (out_mpls_m && out_mpls_v) {
6656 *out_mpls_m = *in_mpls_m;
6657 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6662 * Add metadata register item to matcher
6664 * @param[in, out] matcher
6666 * @param[in, out] key
6667 * Flow matcher value.
6668 * @param[in] reg_type
6669 * Type of device metadata register
6676 flow_dv_match_meta_reg(void *matcher, void *key,
6677 enum modify_reg reg_type,
6678 uint32_t data, uint32_t mask)
6681 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6683 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6689 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6690 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6693 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6694 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6698 * The metadata register C0 field might be divided into
6699 * source vport index and META item value, we should set
6700 * this field according to specified mask, not as whole one.
6702 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6704 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6705 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6708 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6711 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6712 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6715 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6716 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6719 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6720 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6723 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6724 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6727 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6728 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6731 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6732 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6735 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6736 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6745 * Add MARK item to matcher
6748 * The device to configure through.
6749 * @param[in, out] matcher
6751 * @param[in, out] key
6752 * Flow matcher value.
6754 * Flow pattern to translate.
6757 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6758 void *matcher, void *key,
6759 const struct rte_flow_item *item)
6761 struct mlx5_priv *priv = dev->data->dev_private;
6762 const struct rte_flow_item_mark *mark;
6766 mark = item->mask ? (const void *)item->mask :
6767 &rte_flow_item_mark_mask;
6768 mask = mark->id & priv->sh->dv_mark_mask;
6769 mark = (const void *)item->spec;
6771 value = mark->id & priv->sh->dv_mark_mask & mask;
6773 enum modify_reg reg;
6775 /* Get the metadata register index for the mark. */
6776 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6777 MLX5_ASSERT(reg > 0);
6778 if (reg == REG_C_0) {
6779 struct mlx5_priv *priv = dev->data->dev_private;
6780 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6781 uint32_t shl_c0 = rte_bsf32(msk_c0);
6787 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6792 * Add META item to matcher
6795 * The devich to configure through.
6796 * @param[in, out] matcher
6798 * @param[in, out] key
6799 * Flow matcher value.
6801 * Attributes of flow that includes this item.
6803 * Flow pattern to translate.
6806 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6807 void *matcher, void *key,
6808 const struct rte_flow_attr *attr,
6809 const struct rte_flow_item *item)
6811 const struct rte_flow_item_meta *meta_m;
6812 const struct rte_flow_item_meta *meta_v;
6814 meta_m = (const void *)item->mask;
6816 meta_m = &rte_flow_item_meta_mask;
6817 meta_v = (const void *)item->spec;
6820 uint32_t value = meta_v->data;
6821 uint32_t mask = meta_m->data;
6823 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6827 * In datapath code there is no endianness
6828 * coversions for perfromance reasons, all
6829 * pattern conversions are done in rte_flow.
6831 value = rte_cpu_to_be_32(value);
6832 mask = rte_cpu_to_be_32(mask);
6833 if (reg == REG_C_0) {
6834 struct mlx5_priv *priv = dev->data->dev_private;
6835 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6836 uint32_t shl_c0 = rte_bsf32(msk_c0);
6837 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6838 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6845 MLX5_ASSERT(msk_c0);
6846 MLX5_ASSERT(!(~msk_c0 & mask));
6848 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6853 * Add vport metadata Reg C0 item to matcher
6855 * @param[in, out] matcher
6857 * @param[in, out] key
6858 * Flow matcher value.
6860 * Flow pattern to translate.
6863 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6864 uint32_t value, uint32_t mask)
6866 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6870 * Add tag item to matcher
6873 * The devich to configure through.
6874 * @param[in, out] matcher
6876 * @param[in, out] key
6877 * Flow matcher value.
6879 * Flow pattern to translate.
6882 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6883 void *matcher, void *key,
6884 const struct rte_flow_item *item)
6886 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6887 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6888 uint32_t mask, value;
6891 value = tag_v->data;
6892 mask = tag_m ? tag_m->data : UINT32_MAX;
6893 if (tag_v->id == REG_C_0) {
6894 struct mlx5_priv *priv = dev->data->dev_private;
6895 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6896 uint32_t shl_c0 = rte_bsf32(msk_c0);
6902 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6906 * Add TAG item to matcher
6909 * The devich to configure through.
6910 * @param[in, out] matcher
6912 * @param[in, out] key
6913 * Flow matcher value.
6915 * Flow pattern to translate.
6918 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6919 void *matcher, void *key,
6920 const struct rte_flow_item *item)
6922 const struct rte_flow_item_tag *tag_v = item->spec;
6923 const struct rte_flow_item_tag *tag_m = item->mask;
6924 enum modify_reg reg;
6927 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6928 /* Get the metadata register index for the tag. */
6929 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6930 MLX5_ASSERT(reg > 0);
6931 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6935 * Add source vport match to the specified matcher.
6937 * @param[in, out] matcher
6939 * @param[in, out] key
6940 * Flow matcher value.
6942 * Source vport value to match
6947 flow_dv_translate_item_source_vport(void *matcher, void *key,
6948 int16_t port, uint16_t mask)
6950 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6951 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6953 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6954 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6958 * Translate port-id item to eswitch match on port-id.
6961 * The devich to configure through.
6962 * @param[in, out] matcher
6964 * @param[in, out] key
6965 * Flow matcher value.
6967 * Flow pattern to translate.
6970 * 0 on success, a negative errno value otherwise.
6973 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6974 void *key, const struct rte_flow_item *item)
6976 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6977 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6978 struct mlx5_priv *priv;
6981 mask = pid_m ? pid_m->id : 0xffff;
6982 id = pid_v ? pid_v->id : dev->data->port_id;
6983 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6986 /* Translate to vport field or to metadata, depending on mode. */
6987 if (priv->vport_meta_mask)
6988 flow_dv_translate_item_meta_vport(matcher, key,
6989 priv->vport_meta_tag,
6990 priv->vport_meta_mask);
6992 flow_dv_translate_item_source_vport(matcher, key,
6993 priv->vport_id, mask);
6998 * Add ICMP6 item to matcher and to the value.
7000 * @param[in, out] matcher
7002 * @param[in, out] key
7003 * Flow matcher value.
7005 * Flow pattern to translate.
7007 * Item is inner pattern.
7010 flow_dv_translate_item_icmp6(void *matcher, void *key,
7011 const struct rte_flow_item *item,
7014 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7015 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7018 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7020 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7022 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7024 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7026 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7028 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7030 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7031 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7035 icmp6_m = &rte_flow_item_icmp6_mask;
7037 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7038 * If only the protocol is specified, no need to match the frag.
7040 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7041 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7042 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7043 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7044 icmp6_v->type & icmp6_m->type);
7045 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7046 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7047 icmp6_v->code & icmp6_m->code);
7051 * Add ICMP item to matcher and to the value.
7053 * @param[in, out] matcher
7055 * @param[in, out] key
7056 * Flow matcher value.
7058 * Flow pattern to translate.
7060 * Item is inner pattern.
7063 flow_dv_translate_item_icmp(void *matcher, void *key,
7064 const struct rte_flow_item *item,
7067 const struct rte_flow_item_icmp *icmp_m = item->mask;
7068 const struct rte_flow_item_icmp *icmp_v = item->spec;
7071 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7073 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7075 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7077 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7079 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7081 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7083 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7084 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7088 icmp_m = &rte_flow_item_icmp_mask;
7090 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7091 * If only the protocol is specified, no need to match the frag.
7093 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7094 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7095 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7096 icmp_m->hdr.icmp_type);
7097 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7098 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7099 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7100 icmp_m->hdr.icmp_code);
7101 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7102 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7106 * Add GTP item to matcher and to the value.
7108 * @param[in, out] matcher
7110 * @param[in, out] key
7111 * Flow matcher value.
7113 * Flow pattern to translate.
7115 * Item is inner pattern.
7118 flow_dv_translate_item_gtp(void *matcher, void *key,
7119 const struct rte_flow_item *item, int inner)
7121 const struct rte_flow_item_gtp *gtp_m = item->mask;
7122 const struct rte_flow_item_gtp *gtp_v = item->spec;
7125 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7127 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7128 uint16_t dport = RTE_GTPU_UDP_PORT;
7131 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7133 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7135 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7137 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7139 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7140 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7141 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7146 gtp_m = &rte_flow_item_gtp_mask;
7147 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7148 gtp_m->v_pt_rsv_flags);
7149 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7150 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7151 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7152 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7153 gtp_v->msg_type & gtp_m->msg_type);
7154 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7155 rte_be_to_cpu_32(gtp_m->teid));
7156 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7157 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7160 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7162 #define HEADER_IS_ZERO(match_criteria, headers) \
7163 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7164 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7167 * Calculate flow matcher enable bitmap.
7169 * @param match_criteria
7170 * Pointer to flow matcher criteria.
7173 * Bitmap of enabled fields.
7176 flow_dv_matcher_enable(uint32_t *match_criteria)
7178 uint8_t match_criteria_enable;
7180 match_criteria_enable =
7181 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7182 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7183 match_criteria_enable |=
7184 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7185 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7186 match_criteria_enable |=
7187 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7188 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7189 match_criteria_enable |=
7190 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7191 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7192 match_criteria_enable |=
7193 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7194 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7195 return match_criteria_enable;
7202 * @param[in, out] dev
7203 * Pointer to rte_eth_dev structure.
7204 * @param[in] table_id
7207 * Direction of the table.
7208 * @param[in] transfer
7209 * E-Switch or NIC flow.
7211 * pointer to error structure.
7214 * Returns tables resource based on the index, NULL in case of failed.
7216 static struct mlx5_flow_tbl_resource *
7217 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7218 uint32_t table_id, uint8_t egress,
7220 struct rte_flow_error *error)
7222 struct mlx5_priv *priv = dev->data->dev_private;
7223 struct mlx5_ibv_shared *sh = priv->sh;
7224 struct mlx5_flow_tbl_resource *tbl;
7225 union mlx5_flow_tbl_key table_key = {
7227 .table_id = table_id,
7229 .domain = !!transfer,
7230 .direction = !!egress,
7233 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7235 struct mlx5_flow_tbl_data_entry *tbl_data;
7241 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7243 tbl = &tbl_data->tbl;
7244 rte_atomic32_inc(&tbl->refcnt);
7247 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7249 rte_flow_error_set(error, ENOMEM,
7250 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7252 "cannot allocate flow table data entry");
7255 tbl_data->idx = idx;
7256 tbl = &tbl_data->tbl;
7257 pos = &tbl_data->entry;
7259 domain = sh->fdb_domain;
7261 domain = sh->tx_domain;
7263 domain = sh->rx_domain;
7264 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7266 rte_flow_error_set(error, ENOMEM,
7267 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7268 NULL, "cannot create flow table object");
7269 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7273 * No multi-threads now, but still better to initialize the reference
7274 * count before insert it into the hash list.
7276 rte_atomic32_init(&tbl->refcnt);
7277 /* Jump action reference count is initialized here. */
7278 rte_atomic32_init(&tbl_data->jump.refcnt);
7279 pos->key = table_key.v64;
7280 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7282 rte_flow_error_set(error, -ret,
7283 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7284 "cannot insert flow table data entry");
7285 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7286 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7288 rte_atomic32_inc(&tbl->refcnt);
7293 * Release a flow table.
7296 * Pointer to rte_eth_dev structure.
7298 * Table resource to be released.
7301 * Returns 0 if table was released, else return 1;
7304 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7305 struct mlx5_flow_tbl_resource *tbl)
7307 struct mlx5_priv *priv = dev->data->dev_private;
7308 struct mlx5_ibv_shared *sh = priv->sh;
7309 struct mlx5_flow_tbl_data_entry *tbl_data =
7310 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7314 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7315 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7317 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7319 /* remove the entry from the hash list and free memory. */
7320 mlx5_hlist_remove(sh->flow_tbls, pos);
7321 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7329 * Register the flow matcher.
7331 * @param[in, out] dev
7332 * Pointer to rte_eth_dev structure.
7333 * @param[in, out] matcher
7334 * Pointer to flow matcher.
7335 * @param[in, out] key
7336 * Pointer to flow table key.
7337 * @parm[in, out] dev_flow
7338 * Pointer to the dev_flow.
7340 * pointer to error structure.
7343 * 0 on success otherwise -errno and errno is set.
7346 flow_dv_matcher_register(struct rte_eth_dev *dev,
7347 struct mlx5_flow_dv_matcher *matcher,
7348 union mlx5_flow_tbl_key *key,
7349 struct mlx5_flow *dev_flow,
7350 struct rte_flow_error *error)
7352 struct mlx5_priv *priv = dev->data->dev_private;
7353 struct mlx5_ibv_shared *sh = priv->sh;
7354 struct mlx5_flow_dv_matcher *cache_matcher;
7355 struct mlx5dv_flow_matcher_attr dv_attr = {
7356 .type = IBV_FLOW_ATTR_NORMAL,
7357 .match_mask = (void *)&matcher->mask,
7359 struct mlx5_flow_tbl_resource *tbl;
7360 struct mlx5_flow_tbl_data_entry *tbl_data;
7362 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7363 key->domain, error);
7365 return -rte_errno; /* No need to refill the error info */
7366 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7367 /* Lookup from cache. */
7368 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7369 if (matcher->crc == cache_matcher->crc &&
7370 matcher->priority == cache_matcher->priority &&
7371 !memcmp((const void *)matcher->mask.buf,
7372 (const void *)cache_matcher->mask.buf,
7373 cache_matcher->mask.size)) {
7375 "%s group %u priority %hd use %s "
7376 "matcher %p: refcnt %d++",
7377 key->domain ? "FDB" : "NIC", key->table_id,
7378 cache_matcher->priority,
7379 key->direction ? "tx" : "rx",
7380 (void *)cache_matcher,
7381 rte_atomic32_read(&cache_matcher->refcnt));
7382 rte_atomic32_inc(&cache_matcher->refcnt);
7383 dev_flow->handle->dvh.matcher = cache_matcher;
7384 /* old matcher should not make the table ref++. */
7385 flow_dv_tbl_resource_release(dev, tbl);
7389 /* Register new matcher. */
7390 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7391 if (!cache_matcher) {
7392 flow_dv_tbl_resource_release(dev, tbl);
7393 return rte_flow_error_set(error, ENOMEM,
7394 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7395 "cannot allocate matcher memory");
7397 *cache_matcher = *matcher;
7398 dv_attr.match_criteria_enable =
7399 flow_dv_matcher_enable(cache_matcher->mask.buf);
7400 dv_attr.priority = matcher->priority;
7402 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7403 cache_matcher->matcher_object =
7404 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7405 if (!cache_matcher->matcher_object) {
7406 rte_free(cache_matcher);
7407 #ifdef HAVE_MLX5DV_DR
7408 flow_dv_tbl_resource_release(dev, tbl);
7410 return rte_flow_error_set(error, ENOMEM,
7411 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7412 NULL, "cannot create matcher");
7414 /* Save the table information */
7415 cache_matcher->tbl = tbl;
7416 rte_atomic32_init(&cache_matcher->refcnt);
7417 /* only matcher ref++, table ref++ already done above in get API. */
7418 rte_atomic32_inc(&cache_matcher->refcnt);
7419 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7420 dev_flow->handle->dvh.matcher = cache_matcher;
7421 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7422 key->domain ? "FDB" : "NIC", key->table_id,
7423 cache_matcher->priority,
7424 key->direction ? "tx" : "rx", (void *)cache_matcher,
7425 rte_atomic32_read(&cache_matcher->refcnt));
7430 * Find existing tag resource or create and register a new one.
7432 * @param dev[in, out]
7433 * Pointer to rte_eth_dev structure.
7434 * @param[in, out] tag_be24
7435 * Tag value in big endian then R-shift 8.
7436 * @parm[in, out] dev_flow
7437 * Pointer to the dev_flow.
7439 * pointer to error structure.
7442 * 0 on success otherwise -errno and errno is set.
7445 flow_dv_tag_resource_register
7446 (struct rte_eth_dev *dev,
7448 struct mlx5_flow *dev_flow,
7449 struct rte_flow_error *error)
7451 struct mlx5_priv *priv = dev->data->dev_private;
7452 struct mlx5_ibv_shared *sh = priv->sh;
7453 struct mlx5_flow_dv_tag_resource *cache_resource;
7454 struct mlx5_hlist_entry *entry;
7456 /* Lookup a matching resource from cache. */
7457 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7459 cache_resource = container_of
7460 (entry, struct mlx5_flow_dv_tag_resource, entry);
7461 rte_atomic32_inc(&cache_resource->refcnt);
7462 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7463 dev_flow->dv.tag_resource = cache_resource;
7464 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7465 (void *)cache_resource,
7466 rte_atomic32_read(&cache_resource->refcnt));
7469 /* Register new resource. */
7470 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7471 &dev_flow->handle->dvh.rix_tag);
7472 if (!cache_resource)
7473 return rte_flow_error_set(error, ENOMEM,
7474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7475 "cannot allocate resource memory");
7476 cache_resource->entry.key = (uint64_t)tag_be24;
7477 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7478 if (!cache_resource->action) {
7479 rte_free(cache_resource);
7480 return rte_flow_error_set(error, ENOMEM,
7481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7482 NULL, "cannot create action");
7484 rte_atomic32_init(&cache_resource->refcnt);
7485 rte_atomic32_inc(&cache_resource->refcnt);
7486 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7487 mlx5_glue->destroy_flow_action(cache_resource->action);
7488 rte_free(cache_resource);
7489 return rte_flow_error_set(error, EEXIST,
7490 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7491 NULL, "cannot insert tag");
7493 dev_flow->dv.tag_resource = cache_resource;
7494 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7495 (void *)cache_resource,
7496 rte_atomic32_read(&cache_resource->refcnt));
7504 * Pointer to Ethernet device.
7509 * 1 while a reference on it exists, 0 when freed.
7512 flow_dv_tag_release(struct rte_eth_dev *dev,
7515 struct mlx5_priv *priv = dev->data->dev_private;
7516 struct mlx5_ibv_shared *sh = priv->sh;
7517 struct mlx5_flow_dv_tag_resource *tag;
7519 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7522 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7523 dev->data->port_id, (void *)tag,
7524 rte_atomic32_read(&tag->refcnt));
7525 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7526 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7527 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7528 DRV_LOG(DEBUG, "port %u tag %p: removed",
7529 dev->data->port_id, (void *)tag);
7530 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7537 * Translate port ID action to vport.
7540 * Pointer to rte_eth_dev structure.
7542 * Pointer to the port ID action.
7543 * @param[out] dst_port_id
7544 * The target port ID.
7546 * Pointer to the error structure.
7549 * 0 on success, a negative errno value otherwise and rte_errno is set.
7552 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7553 const struct rte_flow_action *action,
7554 uint32_t *dst_port_id,
7555 struct rte_flow_error *error)
7558 struct mlx5_priv *priv;
7559 const struct rte_flow_action_port_id *conf =
7560 (const struct rte_flow_action_port_id *)action->conf;
7562 port = conf->original ? dev->data->port_id : conf->id;
7563 priv = mlx5_port_to_eswitch_info(port, false);
7565 return rte_flow_error_set(error, -rte_errno,
7566 RTE_FLOW_ERROR_TYPE_ACTION,
7568 "No eswitch info was found for port");
7569 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7571 * This parameter is transferred to
7572 * mlx5dv_dr_action_create_dest_ib_port().
7574 *dst_port_id = priv->ibv_port;
7577 * Legacy mode, no LAG configurations is supported.
7578 * This parameter is transferred to
7579 * mlx5dv_dr_action_create_dest_vport().
7581 *dst_port_id = priv->vport_id;
7587 * Create a counter with aging configuration.
7590 * Pointer to rte_eth_dev structure.
7592 * Pointer to the counter action configuration.
7594 * Pointer to the aging action configuration.
7597 * Index to flow counter on success, 0 otherwise.
7600 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7601 struct mlx5_flow *dev_flow,
7602 const struct rte_flow_action_count *count,
7603 const struct rte_flow_action_age *age)
7606 struct mlx5_age_param *age_param;
7608 counter = flow_dv_counter_alloc(dev,
7609 count ? count->shared : 0,
7610 count ? count->id : 0,
7611 dev_flow->dv.group, !!age);
7612 if (!counter || age == NULL)
7614 age_param = flow_dv_counter_idx_get_age(dev, counter);
7616 * The counter age accuracy may have a bit delay. Have 3/4
7617 * second bias on the timeount in order to let it age in time.
7619 age_param->context = age->context ? age->context :
7620 (void *)(uintptr_t)(dev_flow->flow_idx);
7622 * The counter age accuracy may have a bit delay. Have 3/4
7623 * second bias on the timeount in order to let it age in time.
7625 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7626 /* Set expire time in unit of 0.1 sec. */
7627 age_param->port_id = dev->data->port_id;
7628 age_param->expire = age_param->timeout +
7629 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7630 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7634 * Add Tx queue matcher
7637 * Pointer to the dev struct.
7638 * @param[in, out] matcher
7640 * @param[in, out] key
7641 * Flow matcher value.
7643 * Flow pattern to translate.
7645 * Item is inner pattern.
7648 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7649 void *matcher, void *key,
7650 const struct rte_flow_item *item)
7652 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7653 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7655 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7657 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7658 struct mlx5_txq_ctrl *txq;
7662 queue_m = (const void *)item->mask;
7665 queue_v = (const void *)item->spec;
7668 txq = mlx5_txq_get(dev, queue_v->queue);
7671 queue = txq->obj->sq->id;
7672 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7673 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7674 queue & queue_m->queue);
7675 mlx5_txq_release(dev, queue_v->queue);
7679 * Set the hash fields according to the @p flow information.
7681 * @param[in] dev_flow
7682 * Pointer to the mlx5_flow.
7683 * @param[in] rss_desc
7684 * Pointer to the mlx5_flow_rss_desc.
7687 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7688 struct mlx5_flow_rss_desc *rss_desc)
7690 uint64_t items = dev_flow->handle->layers;
7692 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7694 dev_flow->hash_fields = 0;
7695 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7696 if (rss_desc->level >= 2) {
7697 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7701 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7702 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7703 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7704 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7705 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7706 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7707 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7709 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7711 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7712 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7713 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7714 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7715 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7716 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7717 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7719 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7722 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7723 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7724 if (rss_types & ETH_RSS_UDP) {
7725 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7726 dev_flow->hash_fields |=
7727 IBV_RX_HASH_SRC_PORT_UDP;
7728 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7729 dev_flow->hash_fields |=
7730 IBV_RX_HASH_DST_PORT_UDP;
7732 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7734 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7735 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7736 if (rss_types & ETH_RSS_TCP) {
7737 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7738 dev_flow->hash_fields |=
7739 IBV_RX_HASH_SRC_PORT_TCP;
7740 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7741 dev_flow->hash_fields |=
7742 IBV_RX_HASH_DST_PORT_TCP;
7744 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7750 * Fill the flow with DV spec, lock free
7751 * (mutex should be acquired by caller).
7754 * Pointer to rte_eth_dev structure.
7755 * @param[in, out] dev_flow
7756 * Pointer to the sub flow.
7758 * Pointer to the flow attributes.
7760 * Pointer to the list of items.
7761 * @param[in] actions
7762 * Pointer to the list of actions.
7764 * Pointer to the error structure.
7767 * 0 on success, a negative errno value otherwise and rte_errno is set.
7770 __flow_dv_translate(struct rte_eth_dev *dev,
7771 struct mlx5_flow *dev_flow,
7772 const struct rte_flow_attr *attr,
7773 const struct rte_flow_item items[],
7774 const struct rte_flow_action actions[],
7775 struct rte_flow_error *error)
7777 struct mlx5_priv *priv = dev->data->dev_private;
7778 struct mlx5_dev_config *dev_conf = &priv->config;
7779 struct rte_flow *flow = dev_flow->flow;
7780 struct mlx5_flow_handle *handle = dev_flow->handle;
7781 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7783 [!!priv->flow_nested_idx];
7784 uint64_t item_flags = 0;
7785 uint64_t last_item = 0;
7786 uint64_t action_flags = 0;
7787 uint64_t priority = attr->priority;
7788 struct mlx5_flow_dv_matcher matcher = {
7790 .size = sizeof(matcher.mask.buf),
7794 bool actions_end = false;
7796 struct mlx5_flow_dv_modify_hdr_resource res;
7797 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7798 sizeof(struct mlx5_modification_cmd) *
7799 (MLX5_MAX_MODIFY_NUM + 1)];
7801 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7802 const struct rte_flow_action_count *count = NULL;
7803 const struct rte_flow_action_age *age = NULL;
7804 union flow_dv_attr flow_attr = { .attr = 0 };
7806 union mlx5_flow_tbl_key tbl_key;
7807 uint32_t modify_action_position = UINT32_MAX;
7808 void *match_mask = matcher.mask.buf;
7809 void *match_value = dev_flow->dv.value.buf;
7810 uint8_t next_protocol = 0xff;
7811 struct rte_vlan_hdr vlan = { 0 };
7815 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7816 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7817 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7818 !!priv->fdb_def_rule, &table, error);
7821 dev_flow->dv.group = table;
7823 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7824 if (priority == MLX5_FLOW_PRIO_RSVD)
7825 priority = dev_conf->flow_prio - 1;
7826 /* number of actions must be set to 0 in case of dirty stack. */
7827 mhdr_res->actions_num = 0;
7828 for (; !actions_end ; actions++) {
7829 const struct rte_flow_action_queue *queue;
7830 const struct rte_flow_action_rss *rss;
7831 const struct rte_flow_action *action = actions;
7832 const uint8_t *rss_key;
7833 const struct rte_flow_action_jump *jump_data;
7834 const struct rte_flow_action_meter *mtr;
7835 struct mlx5_flow_tbl_resource *tbl;
7836 uint32_t port_id = 0;
7837 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7838 int action_type = actions->type;
7839 const struct rte_flow_action *found_action = NULL;
7840 struct mlx5_flow_meter *fm = NULL;
7842 switch (action_type) {
7843 case RTE_FLOW_ACTION_TYPE_VOID:
7845 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7846 if (flow_dv_translate_action_port_id(dev, action,
7849 memset(&port_id_resource, 0, sizeof(port_id_resource));
7850 port_id_resource.port_id = port_id;
7851 if (flow_dv_port_id_action_resource_register
7852 (dev, &port_id_resource, dev_flow, error))
7854 MLX5_ASSERT(!handle->rix_port_id_action);
7855 dev_flow->dv.actions[actions_n++] =
7856 dev_flow->dv.port_id_action->action;
7857 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7858 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7860 case RTE_FLOW_ACTION_TYPE_FLAG:
7861 action_flags |= MLX5_FLOW_ACTION_FLAG;
7862 dev_flow->handle->mark = 1;
7863 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7864 struct rte_flow_action_mark mark = {
7865 .id = MLX5_FLOW_MARK_DEFAULT,
7868 if (flow_dv_convert_action_mark(dev, &mark,
7872 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7875 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7877 * Only one FLAG or MARK is supported per device flow
7878 * right now. So the pointer to the tag resource must be
7879 * zero before the register process.
7881 MLX5_ASSERT(!handle->dvh.rix_tag);
7882 if (flow_dv_tag_resource_register(dev, tag_be,
7885 MLX5_ASSERT(dev_flow->dv.tag_resource);
7886 dev_flow->dv.actions[actions_n++] =
7887 dev_flow->dv.tag_resource->action;
7889 case RTE_FLOW_ACTION_TYPE_MARK:
7890 action_flags |= MLX5_FLOW_ACTION_MARK;
7891 dev_flow->handle->mark = 1;
7892 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7893 const struct rte_flow_action_mark *mark =
7894 (const struct rte_flow_action_mark *)
7897 if (flow_dv_convert_action_mark(dev, mark,
7901 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7905 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7906 /* Legacy (non-extensive) MARK action. */
7907 tag_be = mlx5_flow_mark_set
7908 (((const struct rte_flow_action_mark *)
7909 (actions->conf))->id);
7910 MLX5_ASSERT(!handle->dvh.rix_tag);
7911 if (flow_dv_tag_resource_register(dev, tag_be,
7914 MLX5_ASSERT(dev_flow->dv.tag_resource);
7915 dev_flow->dv.actions[actions_n++] =
7916 dev_flow->dv.tag_resource->action;
7918 case RTE_FLOW_ACTION_TYPE_SET_META:
7919 if (flow_dv_convert_action_set_meta
7920 (dev, mhdr_res, attr,
7921 (const struct rte_flow_action_set_meta *)
7922 actions->conf, error))
7924 action_flags |= MLX5_FLOW_ACTION_SET_META;
7926 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7927 if (flow_dv_convert_action_set_tag
7929 (const struct rte_flow_action_set_tag *)
7930 actions->conf, error))
7932 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7934 case RTE_FLOW_ACTION_TYPE_DROP:
7935 action_flags |= MLX5_FLOW_ACTION_DROP;
7936 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7938 case RTE_FLOW_ACTION_TYPE_QUEUE:
7939 queue = actions->conf;
7940 rss_desc->queue_num = 1;
7941 rss_desc->queue[0] = queue->index;
7942 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7943 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7945 case RTE_FLOW_ACTION_TYPE_RSS:
7946 rss = actions->conf;
7947 memcpy(rss_desc->queue, rss->queue,
7948 rss->queue_num * sizeof(uint16_t));
7949 rss_desc->queue_num = rss->queue_num;
7950 /* NULL RSS key indicates default RSS key. */
7951 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7952 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7954 * rss->level and rss.types should be set in advance
7955 * when expanding items for RSS.
7957 action_flags |= MLX5_FLOW_ACTION_RSS;
7958 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7960 case RTE_FLOW_ACTION_TYPE_AGE:
7961 case RTE_FLOW_ACTION_TYPE_COUNT:
7962 if (!dev_conf->devx) {
7963 return rte_flow_error_set
7965 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7967 "count action not supported");
7969 /* Save information first, will apply later. */
7970 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7971 count = action->conf;
7974 action_flags |= MLX5_FLOW_ACTION_COUNT;
7976 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7977 dev_flow->dv.actions[actions_n++] =
7978 priv->sh->pop_vlan_action;
7979 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7981 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7982 if (!(action_flags &
7983 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7984 flow_dev_get_vlan_info_from_items(items, &vlan);
7985 vlan.eth_proto = rte_be_to_cpu_16
7986 ((((const struct rte_flow_action_of_push_vlan *)
7987 actions->conf)->ethertype));
7988 found_action = mlx5_flow_find_action
7990 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7992 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7993 found_action = mlx5_flow_find_action
7995 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7997 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7998 if (flow_dv_create_action_push_vlan
7999 (dev, attr, &vlan, dev_flow, error))
8001 dev_flow->dv.actions[actions_n++] =
8002 dev_flow->dv.push_vlan_res->action;
8003 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8005 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8006 /* of_vlan_push action handled this action */
8007 MLX5_ASSERT(action_flags &
8008 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8010 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8011 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8013 flow_dev_get_vlan_info_from_items(items, &vlan);
8014 mlx5_update_vlan_vid_pcp(actions, &vlan);
8015 /* If no VLAN push - this is a modify header action */
8016 if (flow_dv_convert_action_modify_vlan_vid
8017 (mhdr_res, actions, error))
8019 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8021 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8022 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8023 if (flow_dv_create_action_l2_encap(dev, actions,
8028 dev_flow->dv.actions[actions_n++] =
8029 dev_flow->dv.encap_decap->verbs_action;
8030 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8032 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8033 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8034 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8038 dev_flow->dv.actions[actions_n++] =
8039 dev_flow->dv.encap_decap->verbs_action;
8040 action_flags |= MLX5_FLOW_ACTION_DECAP;
8042 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8043 /* Handle encap with preceding decap. */
8044 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8045 if (flow_dv_create_action_raw_encap
8046 (dev, actions, dev_flow, attr, error))
8048 dev_flow->dv.actions[actions_n++] =
8049 dev_flow->dv.encap_decap->verbs_action;
8051 /* Handle encap without preceding decap. */
8052 if (flow_dv_create_action_l2_encap
8053 (dev, actions, dev_flow, attr->transfer,
8056 dev_flow->dv.actions[actions_n++] =
8057 dev_flow->dv.encap_decap->verbs_action;
8059 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8061 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8062 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8064 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8065 if (flow_dv_create_action_l2_decap
8066 (dev, dev_flow, attr->transfer, error))
8068 dev_flow->dv.actions[actions_n++] =
8069 dev_flow->dv.encap_decap->verbs_action;
8071 /* If decap is followed by encap, handle it at encap. */
8072 action_flags |= MLX5_FLOW_ACTION_DECAP;
8074 case RTE_FLOW_ACTION_TYPE_JUMP:
8075 jump_data = action->conf;
8076 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8078 !!priv->fdb_def_rule,
8082 tbl = flow_dv_tbl_resource_get(dev, table,
8084 attr->transfer, error);
8086 return rte_flow_error_set
8088 RTE_FLOW_ERROR_TYPE_ACTION,
8090 "cannot create jump action.");
8091 if (flow_dv_jump_tbl_resource_register
8092 (dev, tbl, dev_flow, error)) {
8093 flow_dv_tbl_resource_release(dev, tbl);
8094 return rte_flow_error_set
8096 RTE_FLOW_ERROR_TYPE_ACTION,
8098 "cannot create jump action.");
8100 dev_flow->dv.actions[actions_n++] =
8101 dev_flow->dv.jump->action;
8102 action_flags |= MLX5_FLOW_ACTION_JUMP;
8103 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8105 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8106 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8107 if (flow_dv_convert_action_modify_mac
8108 (mhdr_res, actions, error))
8110 action_flags |= actions->type ==
8111 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8112 MLX5_FLOW_ACTION_SET_MAC_SRC :
8113 MLX5_FLOW_ACTION_SET_MAC_DST;
8115 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8116 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8117 if (flow_dv_convert_action_modify_ipv4
8118 (mhdr_res, actions, error))
8120 action_flags |= actions->type ==
8121 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8122 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8123 MLX5_FLOW_ACTION_SET_IPV4_DST;
8125 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8126 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8127 if (flow_dv_convert_action_modify_ipv6
8128 (mhdr_res, actions, error))
8130 action_flags |= actions->type ==
8131 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8132 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8133 MLX5_FLOW_ACTION_SET_IPV6_DST;
8135 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8136 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8137 if (flow_dv_convert_action_modify_tp
8138 (mhdr_res, actions, items,
8139 &flow_attr, dev_flow, !!(action_flags &
8140 MLX5_FLOW_ACTION_DECAP), error))
8142 action_flags |= actions->type ==
8143 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8144 MLX5_FLOW_ACTION_SET_TP_SRC :
8145 MLX5_FLOW_ACTION_SET_TP_DST;
8147 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8148 if (flow_dv_convert_action_modify_dec_ttl
8149 (mhdr_res, items, &flow_attr, dev_flow,
8151 MLX5_FLOW_ACTION_DECAP), error))
8153 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8155 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8156 if (flow_dv_convert_action_modify_ttl
8157 (mhdr_res, actions, items, &flow_attr,
8158 dev_flow, !!(action_flags &
8159 MLX5_FLOW_ACTION_DECAP), error))
8161 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8163 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8164 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8165 if (flow_dv_convert_action_modify_tcp_seq
8166 (mhdr_res, actions, error))
8168 action_flags |= actions->type ==
8169 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8170 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8171 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8174 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8175 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8176 if (flow_dv_convert_action_modify_tcp_ack
8177 (mhdr_res, actions, error))
8179 action_flags |= actions->type ==
8180 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8181 MLX5_FLOW_ACTION_INC_TCP_ACK :
8182 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8184 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8185 if (flow_dv_convert_action_set_reg
8186 (mhdr_res, actions, error))
8188 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8190 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8191 if (flow_dv_convert_action_copy_mreg
8192 (dev, mhdr_res, actions, error))
8194 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8196 case RTE_FLOW_ACTION_TYPE_METER:
8197 mtr = actions->conf;
8199 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8202 return rte_flow_error_set(error,
8204 RTE_FLOW_ERROR_TYPE_ACTION,
8207 "or invalid parameters");
8208 flow->meter = fm->idx;
8210 /* Set the meter action. */
8212 fm = mlx5_ipool_get(priv->sh->ipool
8213 [MLX5_IPOOL_MTR], flow->meter);
8215 return rte_flow_error_set(error,
8217 RTE_FLOW_ERROR_TYPE_ACTION,
8220 "or invalid parameters");
8222 dev_flow->dv.actions[actions_n++] =
8223 fm->mfts->meter_action;
8224 action_flags |= MLX5_FLOW_ACTION_METER;
8226 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8227 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8230 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8232 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8233 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8236 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8238 case RTE_FLOW_ACTION_TYPE_END:
8240 if (mhdr_res->actions_num) {
8241 /* create modify action if needed. */
8242 if (flow_dv_modify_hdr_resource_register
8243 (dev, mhdr_res, dev_flow, error))
8245 dev_flow->dv.actions[modify_action_position] =
8246 handle->dvh.modify_hdr->verbs_action;
8248 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8250 flow_dv_translate_create_counter(dev,
8251 dev_flow, count, age);
8254 return rte_flow_error_set
8256 RTE_FLOW_ERROR_TYPE_ACTION,
8258 "cannot create counter"
8260 dev_flow->dv.actions[actions_n++] =
8261 (flow_dv_counter_get_by_idx(dev,
8262 flow->counter, NULL))->action;
8268 if (mhdr_res->actions_num &&
8269 modify_action_position == UINT32_MAX)
8270 modify_action_position = actions_n++;
8272 dev_flow->dv.actions_n = actions_n;
8273 dev_flow->act_flags = action_flags;
8274 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8275 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8276 int item_type = items->type;
8278 switch (item_type) {
8279 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8280 flow_dv_translate_item_port_id(dev, match_mask,
8281 match_value, items);
8282 last_item = MLX5_FLOW_ITEM_PORT_ID;
8284 case RTE_FLOW_ITEM_TYPE_ETH:
8285 flow_dv_translate_item_eth(match_mask, match_value,
8287 dev_flow->dv.group);
8288 matcher.priority = MLX5_PRIORITY_MAP_L2;
8289 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8290 MLX5_FLOW_LAYER_OUTER_L2;
8292 case RTE_FLOW_ITEM_TYPE_VLAN:
8293 flow_dv_translate_item_vlan(dev_flow,
8294 match_mask, match_value,
8296 dev_flow->dv.group);
8297 matcher.priority = MLX5_PRIORITY_MAP_L2;
8298 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8299 MLX5_FLOW_LAYER_INNER_VLAN) :
8300 (MLX5_FLOW_LAYER_OUTER_L2 |
8301 MLX5_FLOW_LAYER_OUTER_VLAN);
8303 case RTE_FLOW_ITEM_TYPE_IPV4:
8304 mlx5_flow_tunnel_ip_check(items, next_protocol,
8305 &item_flags, &tunnel);
8306 flow_dv_translate_item_ipv4(match_mask, match_value,
8307 items, item_flags, tunnel,
8308 dev_flow->dv.group);
8309 matcher.priority = MLX5_PRIORITY_MAP_L3;
8310 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8311 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8312 if (items->mask != NULL &&
8313 ((const struct rte_flow_item_ipv4 *)
8314 items->mask)->hdr.next_proto_id) {
8316 ((const struct rte_flow_item_ipv4 *)
8317 (items->spec))->hdr.next_proto_id;
8319 ((const struct rte_flow_item_ipv4 *)
8320 (items->mask))->hdr.next_proto_id;
8322 /* Reset for inner layer. */
8323 next_protocol = 0xff;
8326 case RTE_FLOW_ITEM_TYPE_IPV6:
8327 mlx5_flow_tunnel_ip_check(items, next_protocol,
8328 &item_flags, &tunnel);
8329 flow_dv_translate_item_ipv6(match_mask, match_value,
8330 items, item_flags, tunnel,
8331 dev_flow->dv.group);
8332 matcher.priority = MLX5_PRIORITY_MAP_L3;
8333 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8334 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8335 if (items->mask != NULL &&
8336 ((const struct rte_flow_item_ipv6 *)
8337 items->mask)->hdr.proto) {
8339 ((const struct rte_flow_item_ipv6 *)
8340 items->spec)->hdr.proto;
8342 ((const struct rte_flow_item_ipv6 *)
8343 items->mask)->hdr.proto;
8345 /* Reset for inner layer. */
8346 next_protocol = 0xff;
8349 case RTE_FLOW_ITEM_TYPE_TCP:
8350 flow_dv_translate_item_tcp(match_mask, match_value,
8352 matcher.priority = MLX5_PRIORITY_MAP_L4;
8353 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8354 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8356 case RTE_FLOW_ITEM_TYPE_UDP:
8357 flow_dv_translate_item_udp(match_mask, match_value,
8359 matcher.priority = MLX5_PRIORITY_MAP_L4;
8360 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8361 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8363 case RTE_FLOW_ITEM_TYPE_GRE:
8364 flow_dv_translate_item_gre(match_mask, match_value,
8366 matcher.priority = rss_desc->level >= 2 ?
8367 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8368 last_item = MLX5_FLOW_LAYER_GRE;
8370 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8371 flow_dv_translate_item_gre_key(match_mask,
8372 match_value, items);
8373 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8375 case RTE_FLOW_ITEM_TYPE_NVGRE:
8376 flow_dv_translate_item_nvgre(match_mask, match_value,
8378 matcher.priority = rss_desc->level >= 2 ?
8379 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8380 last_item = MLX5_FLOW_LAYER_GRE;
8382 case RTE_FLOW_ITEM_TYPE_VXLAN:
8383 flow_dv_translate_item_vxlan(match_mask, match_value,
8385 matcher.priority = rss_desc->level >= 2 ?
8386 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8387 last_item = MLX5_FLOW_LAYER_VXLAN;
8389 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8390 flow_dv_translate_item_vxlan_gpe(match_mask,
8393 matcher.priority = rss_desc->level >= 2 ?
8394 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8395 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8397 case RTE_FLOW_ITEM_TYPE_GENEVE:
8398 flow_dv_translate_item_geneve(match_mask, match_value,
8400 matcher.priority = rss_desc->level >= 2 ?
8401 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8402 last_item = MLX5_FLOW_LAYER_GENEVE;
8404 case RTE_FLOW_ITEM_TYPE_MPLS:
8405 flow_dv_translate_item_mpls(match_mask, match_value,
8406 items, last_item, tunnel);
8407 matcher.priority = rss_desc->level >= 2 ?
8408 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8409 last_item = MLX5_FLOW_LAYER_MPLS;
8411 case RTE_FLOW_ITEM_TYPE_MARK:
8412 flow_dv_translate_item_mark(dev, match_mask,
8413 match_value, items);
8414 last_item = MLX5_FLOW_ITEM_MARK;
8416 case RTE_FLOW_ITEM_TYPE_META:
8417 flow_dv_translate_item_meta(dev, match_mask,
8418 match_value, attr, items);
8419 last_item = MLX5_FLOW_ITEM_METADATA;
8421 case RTE_FLOW_ITEM_TYPE_ICMP:
8422 flow_dv_translate_item_icmp(match_mask, match_value,
8424 last_item = MLX5_FLOW_LAYER_ICMP;
8426 case RTE_FLOW_ITEM_TYPE_ICMP6:
8427 flow_dv_translate_item_icmp6(match_mask, match_value,
8429 last_item = MLX5_FLOW_LAYER_ICMP6;
8431 case RTE_FLOW_ITEM_TYPE_TAG:
8432 flow_dv_translate_item_tag(dev, match_mask,
8433 match_value, items);
8434 last_item = MLX5_FLOW_ITEM_TAG;
8436 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8437 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8438 match_value, items);
8439 last_item = MLX5_FLOW_ITEM_TAG;
8441 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8442 flow_dv_translate_item_tx_queue(dev, match_mask,
8445 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8447 case RTE_FLOW_ITEM_TYPE_GTP:
8448 flow_dv_translate_item_gtp(match_mask, match_value,
8450 matcher.priority = rss_desc->level >= 2 ?
8451 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8452 last_item = MLX5_FLOW_LAYER_GTP;
8457 item_flags |= last_item;
8460 * When E-Switch mode is enabled, we have two cases where we need to
8461 * set the source port manually.
8462 * The first one, is in case of Nic steering rule, and the second is
8463 * E-Switch rule where no port_id item was found. In both cases
8464 * the source port is set according the current port in use.
8466 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8467 (priv->representor || priv->master)) {
8468 if (flow_dv_translate_item_port_id(dev, match_mask,
8472 #ifdef RTE_LIBRTE_MLX5_DEBUG
8473 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8474 dev_flow->dv.value.buf));
8477 * Layers may be already initialized from prefix flow if this dev_flow
8478 * is the suffix flow.
8480 handle->layers |= item_flags;
8481 if (action_flags & MLX5_FLOW_ACTION_RSS)
8482 flow_dv_hashfields_set(dev_flow, rss_desc);
8483 /* Register matcher. */
8484 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8486 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8488 /* reserved field no needs to be set to 0 here. */
8489 tbl_key.domain = attr->transfer;
8490 tbl_key.direction = attr->egress;
8491 tbl_key.table_id = dev_flow->dv.group;
8492 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8498 * Apply the flow to the NIC, lock free,
8499 * (mutex should be acquired by caller).
8502 * Pointer to the Ethernet device structure.
8503 * @param[in, out] flow
8504 * Pointer to flow structure.
8506 * Pointer to error structure.
8509 * 0 on success, a negative errno value otherwise and rte_errno is set.
8512 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8513 struct rte_flow_error *error)
8515 struct mlx5_flow_dv_workspace *dv;
8516 struct mlx5_flow_handle *dh;
8517 struct mlx5_flow_handle_dv *dv_h;
8518 struct mlx5_flow *dev_flow;
8519 struct mlx5_priv *priv = dev->data->dev_private;
8520 uint32_t handle_idx;
8525 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8526 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8528 dh = dev_flow->handle;
8531 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8533 dv->actions[n++] = priv->sh->esw_drop_action;
8535 struct mlx5_hrxq *drop_hrxq;
8536 drop_hrxq = mlx5_hrxq_drop_new(dev);
8540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8542 "cannot get drop hash queue");
8546 * Drop queues will be released by the specify
8547 * mlx5_hrxq_drop_release() function. Assign
8548 * the special index to hrxq to mark the queue
8549 * has been allocated.
8551 dh->rix_hrxq = UINT32_MAX;
8552 dv->actions[n++] = drop_hrxq->action;
8554 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8555 struct mlx5_hrxq *hrxq;
8557 struct mlx5_flow_rss_desc *rss_desc =
8558 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8559 [!!priv->flow_nested_idx];
8561 MLX5_ASSERT(rss_desc->queue_num);
8562 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8563 MLX5_RSS_HASH_KEY_LEN,
8564 dev_flow->hash_fields,
8566 rss_desc->queue_num);
8568 hrxq_idx = mlx5_hrxq_new
8569 (dev, rss_desc->key,
8570 MLX5_RSS_HASH_KEY_LEN,
8571 dev_flow->hash_fields,
8573 rss_desc->queue_num,
8575 MLX5_FLOW_LAYER_TUNNEL));
8577 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8582 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8583 "cannot get hash queue");
8586 dh->rix_hrxq = hrxq_idx;
8587 dv->actions[n++] = hrxq->action;
8590 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8591 (void *)&dv->value, n,
8594 rte_flow_error_set(error, errno,
8595 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8597 "hardware refuses to create flow");
8600 if (priv->vmwa_context &&
8601 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8603 * The rule contains the VLAN pattern.
8604 * For VF we are going to create VLAN
8605 * interface to make hypervisor set correct
8606 * e-Switch vport context.
8608 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8613 err = rte_errno; /* Save rte_errno before cleanup. */
8614 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8615 handle_idx, dh, next) {
8616 /* hrxq is union, don't clear it if the flag is not set. */
8618 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8619 mlx5_hrxq_drop_release(dev);
8621 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8622 mlx5_hrxq_release(dev, dh->rix_hrxq);
8626 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8627 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8629 rte_errno = err; /* Restore rte_errno. */
8634 * Release the flow matcher.
8637 * Pointer to Ethernet device.
8639 * Pointer to mlx5_flow_handle.
8642 * 1 while a reference on it exists, 0 when freed.
8645 flow_dv_matcher_release(struct rte_eth_dev *dev,
8646 struct mlx5_flow_handle *handle)
8648 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8650 MLX5_ASSERT(matcher->matcher_object);
8651 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8652 dev->data->port_id, (void *)matcher,
8653 rte_atomic32_read(&matcher->refcnt));
8654 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8655 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8656 (matcher->matcher_object));
8657 LIST_REMOVE(matcher, next);
8658 /* table ref-- in release interface. */
8659 flow_dv_tbl_resource_release(dev, matcher->tbl);
8661 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8662 dev->data->port_id, (void *)matcher);
8669 * Release an encap/decap resource.
8672 * Pointer to Ethernet device.
8674 * Pointer to mlx5_flow_handle.
8677 * 1 while a reference on it exists, 0 when freed.
8680 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8681 struct mlx5_flow_handle *handle)
8683 struct mlx5_priv *priv = dev->data->dev_private;
8684 uint32_t idx = handle->dvh.rix_encap_decap;
8685 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8687 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8689 if (!cache_resource)
8691 MLX5_ASSERT(cache_resource->verbs_action);
8692 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8693 (void *)cache_resource,
8694 rte_atomic32_read(&cache_resource->refcnt));
8695 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8696 claim_zero(mlx5_glue->destroy_flow_action
8697 (cache_resource->verbs_action));
8698 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8699 &priv->sh->encaps_decaps, idx,
8700 cache_resource, next);
8701 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8702 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8703 (void *)cache_resource);
8710 * Release an jump to table action resource.
8713 * Pointer to Ethernet device.
8715 * Pointer to mlx5_flow_handle.
8718 * 1 while a reference on it exists, 0 when freed.
8721 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8722 struct mlx5_flow_handle *handle)
8724 struct mlx5_priv *priv = dev->data->dev_private;
8725 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8726 struct mlx5_flow_tbl_data_entry *tbl_data;
8728 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8732 cache_resource = &tbl_data->jump;
8733 MLX5_ASSERT(cache_resource->action);
8734 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8735 (void *)cache_resource,
8736 rte_atomic32_read(&cache_resource->refcnt));
8737 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8738 claim_zero(mlx5_glue->destroy_flow_action
8739 (cache_resource->action));
8740 /* jump action memory free is inside the table release. */
8741 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8742 DRV_LOG(DEBUG, "jump table resource %p: removed",
8743 (void *)cache_resource);
8750 * Release a modify-header resource.
8753 * Pointer to mlx5_flow_handle.
8756 * 1 while a reference on it exists, 0 when freed.
8759 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8761 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8762 handle->dvh.modify_hdr;
8764 MLX5_ASSERT(cache_resource->verbs_action);
8765 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8766 (void *)cache_resource,
8767 rte_atomic32_read(&cache_resource->refcnt));
8768 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8769 claim_zero(mlx5_glue->destroy_flow_action
8770 (cache_resource->verbs_action));
8771 LIST_REMOVE(cache_resource, next);
8772 rte_free(cache_resource);
8773 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8774 (void *)cache_resource);
8781 * Release port ID action resource.
8784 * Pointer to Ethernet device.
8786 * Pointer to mlx5_flow_handle.
8789 * 1 while a reference on it exists, 0 when freed.
8792 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8793 struct mlx5_flow_handle *handle)
8795 struct mlx5_priv *priv = dev->data->dev_private;
8796 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8797 uint32_t idx = handle->rix_port_id_action;
8799 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8801 if (!cache_resource)
8803 MLX5_ASSERT(cache_resource->action);
8804 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8805 (void *)cache_resource,
8806 rte_atomic32_read(&cache_resource->refcnt));
8807 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8808 claim_zero(mlx5_glue->destroy_flow_action
8809 (cache_resource->action));
8810 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8811 &priv->sh->port_id_action_list, idx,
8812 cache_resource, next);
8813 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8814 DRV_LOG(DEBUG, "port id action resource %p: removed",
8815 (void *)cache_resource);
8822 * Release push vlan action resource.
8825 * Pointer to Ethernet device.
8827 * Pointer to mlx5_flow_handle.
8830 * 1 while a reference on it exists, 0 when freed.
8833 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8834 struct mlx5_flow_handle *handle)
8836 struct mlx5_priv *priv = dev->data->dev_private;
8837 uint32_t idx = handle->dvh.rix_push_vlan;
8838 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8840 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8842 if (!cache_resource)
8844 MLX5_ASSERT(cache_resource->action);
8845 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8846 (void *)cache_resource,
8847 rte_atomic32_read(&cache_resource->refcnt));
8848 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8849 claim_zero(mlx5_glue->destroy_flow_action
8850 (cache_resource->action));
8851 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8852 &priv->sh->push_vlan_action_list, idx,
8853 cache_resource, next);
8854 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8855 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8856 (void *)cache_resource);
8863 * Release the fate resource.
8866 * Pointer to Ethernet device.
8868 * Pointer to mlx5_flow_handle.
8871 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8872 struct mlx5_flow_handle *handle)
8874 if (!handle->rix_fate)
8876 if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8877 mlx5_hrxq_drop_release(dev);
8878 else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8879 mlx5_hrxq_release(dev, handle->rix_hrxq);
8880 else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8881 flow_dv_jump_tbl_resource_release(dev, handle);
8882 else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8883 flow_dv_port_id_action_resource_release(dev, handle);
8885 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8886 handle->rix_fate = 0;
8890 * Remove the flow from the NIC but keeps it in memory.
8891 * Lock free, (mutex should be acquired by caller).
8894 * Pointer to Ethernet device.
8895 * @param[in, out] flow
8896 * Pointer to flow structure.
8899 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8901 struct mlx5_flow_handle *dh;
8902 uint32_t handle_idx;
8903 struct mlx5_priv *priv = dev->data->dev_private;
8907 handle_idx = flow->dev_handles;
8908 while (handle_idx) {
8909 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8914 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8917 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8918 dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8919 flow_dv_fate_resource_release(dev, dh);
8920 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8921 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8922 handle_idx = dh->next.next;
8927 * Remove the flow from the NIC and the memory.
8928 * Lock free, (mutex should be acquired by caller).
8931 * Pointer to the Ethernet device structure.
8932 * @param[in, out] flow
8933 * Pointer to flow structure.
8936 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8938 struct mlx5_flow_handle *dev_handle;
8939 struct mlx5_priv *priv = dev->data->dev_private;
8943 __flow_dv_remove(dev, flow);
8944 if (flow->counter) {
8945 flow_dv_counter_release(dev, flow->counter);
8949 struct mlx5_flow_meter *fm;
8951 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8954 mlx5_flow_meter_detach(fm);
8957 while (flow->dev_handles) {
8958 uint32_t tmp_idx = flow->dev_handles;
8960 dev_handle = mlx5_ipool_get(priv->sh->ipool
8961 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8964 flow->dev_handles = dev_handle->next.next;
8965 if (dev_handle->dvh.matcher)
8966 flow_dv_matcher_release(dev, dev_handle);
8967 if (dev_handle->dvh.rix_encap_decap)
8968 flow_dv_encap_decap_resource_release(dev, dev_handle);
8969 if (dev_handle->dvh.modify_hdr)
8970 flow_dv_modify_hdr_resource_release(dev_handle);
8971 if (dev_handle->dvh.rix_push_vlan)
8972 flow_dv_push_vlan_action_resource_release(dev,
8974 if (dev_handle->dvh.rix_tag)
8975 flow_dv_tag_release(dev,
8976 dev_handle->dvh.rix_tag);
8977 flow_dv_fate_resource_release(dev, dev_handle);
8978 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8984 * Query a dv flow rule for its statistics via devx.
8987 * Pointer to Ethernet device.
8989 * Pointer to the sub flow.
8991 * data retrieved by the query.
8993 * Perform verbose error reporting if not NULL.
8996 * 0 on success, a negative errno value otherwise and rte_errno is set.
8999 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9000 void *data, struct rte_flow_error *error)
9002 struct mlx5_priv *priv = dev->data->dev_private;
9003 struct rte_flow_query_count *qc = data;
9005 if (!priv->config.devx)
9006 return rte_flow_error_set(error, ENOTSUP,
9007 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9009 "counters are not supported");
9010 if (flow->counter) {
9011 uint64_t pkts, bytes;
9012 struct mlx5_flow_counter *cnt;
9014 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9016 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9020 return rte_flow_error_set(error, -err,
9021 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9022 NULL, "cannot read counters");
9025 qc->hits = pkts - cnt->hits;
9026 qc->bytes = bytes - cnt->bytes;
9033 return rte_flow_error_set(error, EINVAL,
9034 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9036 "counters are not available");
9042 * @see rte_flow_query()
9046 flow_dv_query(struct rte_eth_dev *dev,
9047 struct rte_flow *flow __rte_unused,
9048 const struct rte_flow_action *actions __rte_unused,
9049 void *data __rte_unused,
9050 struct rte_flow_error *error __rte_unused)
9054 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9055 switch (actions->type) {
9056 case RTE_FLOW_ACTION_TYPE_VOID:
9058 case RTE_FLOW_ACTION_TYPE_COUNT:
9059 ret = flow_dv_query_count(dev, flow, data, error);
9062 return rte_flow_error_set(error, ENOTSUP,
9063 RTE_FLOW_ERROR_TYPE_ACTION,
9065 "action not supported");
9072 * Destroy the meter table set.
9073 * Lock free, (mutex should be acquired by caller).
9076 * Pointer to Ethernet device.
9078 * Pointer to the meter table set.
9084 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9085 struct mlx5_meter_domains_infos *tbl)
9087 struct mlx5_priv *priv = dev->data->dev_private;
9088 struct mlx5_meter_domains_infos *mtd =
9089 (struct mlx5_meter_domains_infos *)tbl;
9091 if (!mtd || !priv->config.dv_flow_en)
9093 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9094 claim_zero(mlx5_glue->dv_destroy_flow
9095 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9096 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9097 claim_zero(mlx5_glue->dv_destroy_flow
9098 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9099 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9100 claim_zero(mlx5_glue->dv_destroy_flow
9101 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9102 if (mtd->egress.color_matcher)
9103 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9104 (mtd->egress.color_matcher));
9105 if (mtd->egress.any_matcher)
9106 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9107 (mtd->egress.any_matcher));
9108 if (mtd->egress.tbl)
9109 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9110 if (mtd->egress.sfx_tbl)
9111 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9112 if (mtd->ingress.color_matcher)
9113 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9114 (mtd->ingress.color_matcher));
9115 if (mtd->ingress.any_matcher)
9116 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9117 (mtd->ingress.any_matcher));
9118 if (mtd->ingress.tbl)
9119 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9120 if (mtd->ingress.sfx_tbl)
9121 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9122 if (mtd->transfer.color_matcher)
9123 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9124 (mtd->transfer.color_matcher));
9125 if (mtd->transfer.any_matcher)
9126 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9127 (mtd->transfer.any_matcher));
9128 if (mtd->transfer.tbl)
9129 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9130 if (mtd->transfer.sfx_tbl)
9131 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9133 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9138 /* Number of meter flow actions, count and jump or count and drop. */
9139 #define METER_ACTIONS 2
9142 * Create specify domain meter table and suffix table.
9145 * Pointer to Ethernet device.
9146 * @param[in,out] mtb
9147 * Pointer to DV meter table set.
9150 * @param[in] transfer
9152 * @param[in] color_reg_c_idx
9153 * Reg C index for color match.
9156 * 0 on success, -1 otherwise and rte_errno is set.
9159 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9160 struct mlx5_meter_domains_infos *mtb,
9161 uint8_t egress, uint8_t transfer,
9162 uint32_t color_reg_c_idx)
9164 struct mlx5_priv *priv = dev->data->dev_private;
9165 struct mlx5_ibv_shared *sh = priv->sh;
9166 struct mlx5_flow_dv_match_params mask = {
9167 .size = sizeof(mask.buf),
9169 struct mlx5_flow_dv_match_params value = {
9170 .size = sizeof(value.buf),
9172 struct mlx5dv_flow_matcher_attr dv_attr = {
9173 .type = IBV_FLOW_ATTR_NORMAL,
9175 .match_criteria_enable = 0,
9176 .match_mask = (void *)&mask,
9178 void *actions[METER_ACTIONS];
9179 struct mlx5_meter_domain_info *dtb;
9180 struct rte_flow_error error;
9184 dtb = &mtb->transfer;
9188 dtb = &mtb->ingress;
9189 /* Create the meter table with METER level. */
9190 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9191 egress, transfer, &error);
9193 DRV_LOG(ERR, "Failed to create meter policer table.");
9196 /* Create the meter suffix table with SUFFIX level. */
9197 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9198 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9199 egress, transfer, &error);
9200 if (!dtb->sfx_tbl) {
9201 DRV_LOG(ERR, "Failed to create meter suffix table.");
9204 /* Create matchers, Any and Color. */
9205 dv_attr.priority = 3;
9206 dv_attr.match_criteria_enable = 0;
9207 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9210 if (!dtb->any_matcher) {
9211 DRV_LOG(ERR, "Failed to create meter"
9212 " policer default matcher.");
9215 dv_attr.priority = 0;
9216 dv_attr.match_criteria_enable =
9217 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9218 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9219 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9220 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9223 if (!dtb->color_matcher) {
9224 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9227 if (mtb->count_actns[RTE_MTR_DROPPED])
9228 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9229 actions[i++] = mtb->drop_actn;
9230 /* Default rule: lowest priority, match any, actions: drop. */
9231 dtb->policer_rules[RTE_MTR_DROPPED] =
9232 mlx5_glue->dv_create_flow(dtb->any_matcher,
9233 (void *)&value, i, actions);
9234 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9235 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9244 * Create the needed meter and suffix tables.
9245 * Lock free, (mutex should be acquired by caller).
9248 * Pointer to Ethernet device.
9250 * Pointer to the flow meter.
9253 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9255 static struct mlx5_meter_domains_infos *
9256 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9257 const struct mlx5_flow_meter *fm)
9259 struct mlx5_priv *priv = dev->data->dev_private;
9260 struct mlx5_meter_domains_infos *mtb;
9264 if (!priv->mtr_en) {
9265 rte_errno = ENOTSUP;
9268 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9270 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9273 /* Create meter count actions */
9274 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9275 struct mlx5_flow_counter *cnt;
9276 if (!fm->policer_stats.cnt[i])
9278 cnt = flow_dv_counter_get_by_idx(dev,
9279 fm->policer_stats.cnt[i], NULL);
9280 mtb->count_actns[i] = cnt->action;
9282 /* Create drop action. */
9283 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9284 if (!mtb->drop_actn) {
9285 DRV_LOG(ERR, "Failed to create drop action.");
9288 /* Egress meter table. */
9289 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9291 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9294 /* Ingress meter table. */
9295 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9297 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9300 /* FDB meter table. */
9301 if (priv->config.dv_esw_en) {
9302 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9303 priv->mtr_color_reg);
9305 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9311 flow_dv_destroy_mtr_tbl(dev, mtb);
9316 * Destroy domain policer rule.
9319 * Pointer to domain table.
9322 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9326 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9327 if (dt->policer_rules[i]) {
9328 claim_zero(mlx5_glue->dv_destroy_flow
9329 (dt->policer_rules[i]));
9330 dt->policer_rules[i] = NULL;
9333 if (dt->jump_actn) {
9334 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9335 dt->jump_actn = NULL;
9340 * Destroy policer rules.
9343 * Pointer to Ethernet device.
9345 * Pointer to flow meter structure.
9347 * Pointer to flow attributes.
9353 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9354 const struct mlx5_flow_meter *fm,
9355 const struct rte_flow_attr *attr)
9357 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9362 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9364 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9366 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9371 * Create specify domain meter policer rule.
9374 * Pointer to flow meter structure.
9376 * Pointer to DV meter table set.
9377 * @param[in] mtr_reg_c
9378 * Color match REG_C.
9381 * 0 on success, -1 otherwise.
9384 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9385 struct mlx5_meter_domain_info *dtb,
9388 struct mlx5_flow_dv_match_params matcher = {
9389 .size = sizeof(matcher.buf),
9391 struct mlx5_flow_dv_match_params value = {
9392 .size = sizeof(value.buf),
9394 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9395 void *actions[METER_ACTIONS];
9398 /* Create jump action. */
9399 if (!dtb->jump_actn)
9401 mlx5_glue->dr_create_flow_action_dest_flow_tbl
9402 (dtb->sfx_tbl->obj);
9403 if (!dtb->jump_actn) {
9404 DRV_LOG(ERR, "Failed to create policer jump action.");
9407 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9410 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9411 rte_col_2_mlx5_col(i), UINT8_MAX);
9412 if (mtb->count_actns[i])
9413 actions[j++] = mtb->count_actns[i];
9414 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9415 actions[j++] = mtb->drop_actn;
9417 actions[j++] = dtb->jump_actn;
9418 dtb->policer_rules[i] =
9419 mlx5_glue->dv_create_flow(dtb->color_matcher,
9422 if (!dtb->policer_rules[i]) {
9423 DRV_LOG(ERR, "Failed to create policer rule.");
9434 * Create policer rules.
9437 * Pointer to Ethernet device.
9439 * Pointer to flow meter structure.
9441 * Pointer to flow attributes.
9444 * 0 on success, -1 otherwise.
9447 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9448 struct mlx5_flow_meter *fm,
9449 const struct rte_flow_attr *attr)
9451 struct mlx5_priv *priv = dev->data->dev_private;
9452 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9456 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9457 priv->mtr_color_reg);
9459 DRV_LOG(ERR, "Failed to create egress policer.");
9463 if (attr->ingress) {
9464 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9465 priv->mtr_color_reg);
9467 DRV_LOG(ERR, "Failed to create ingress policer.");
9471 if (attr->transfer) {
9472 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9473 priv->mtr_color_reg);
9475 DRV_LOG(ERR, "Failed to create transfer policer.");
9481 flow_dv_destroy_policer_rules(dev, fm, attr);
9486 * Query a devx counter.
9489 * Pointer to the Ethernet device structure.
9491 * Index to the flow counter.
9493 * Set to clear the counter statistics.
9495 * The statistics value of packets.
9497 * The statistics value of bytes.
9500 * 0 on success, otherwise return -1.
9503 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9504 uint64_t *pkts, uint64_t *bytes)
9506 struct mlx5_priv *priv = dev->data->dev_private;
9507 struct mlx5_flow_counter *cnt;
9508 uint64_t inn_pkts, inn_bytes;
9511 if (!priv->config.devx)
9514 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9517 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9518 *pkts = inn_pkts - cnt->hits;
9519 *bytes = inn_bytes - cnt->bytes;
9521 cnt->hits = inn_pkts;
9522 cnt->bytes = inn_bytes;
9528 * Get aged-out flows.
9531 * Pointer to the Ethernet device structure.
9532 * @param[in] context
9533 * The address of an array of pointers to the aged-out flows contexts.
9534 * @param[in] nb_contexts
9535 * The length of context array pointers.
9537 * Perform verbose error reporting if not NULL. Initialized in case of
9541 * how many contexts get in success, otherwise negative errno value.
9542 * if nb_contexts is 0, return the amount of all aged contexts.
9543 * if nb_contexts is not 0 , return the amount of aged flows reported
9544 * in the context array.
9545 * @note: only stub for now
9548 flow_get_aged_flows(struct rte_eth_dev *dev,
9550 uint32_t nb_contexts,
9551 struct rte_flow_error *error)
9553 struct mlx5_priv *priv = dev->data->dev_private;
9554 struct mlx5_age_info *age_info;
9555 struct mlx5_age_param *age_param;
9556 struct mlx5_flow_counter *counter;
9559 if (nb_contexts && !context)
9560 return rte_flow_error_set(error, EINVAL,
9561 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9563 "Should assign at least one flow or"
9564 " context to get if nb_contexts != 0");
9565 age_info = GET_PORT_AGE_INFO(priv);
9566 rte_spinlock_lock(&age_info->aged_sl);
9567 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9570 age_param = MLX5_CNT_TO_AGE(counter);
9571 context[nb_flows - 1] = age_param->context;
9572 if (!(--nb_contexts))
9576 rte_spinlock_unlock(&age_info->aged_sl);
9577 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9582 * Mutex-protected thunk to lock-free __flow_dv_translate().
9585 flow_dv_translate(struct rte_eth_dev *dev,
9586 struct mlx5_flow *dev_flow,
9587 const struct rte_flow_attr *attr,
9588 const struct rte_flow_item items[],
9589 const struct rte_flow_action actions[],
9590 struct rte_flow_error *error)
9594 flow_dv_shared_lock(dev);
9595 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9596 flow_dv_shared_unlock(dev);
9601 * Mutex-protected thunk to lock-free __flow_dv_apply().
9604 flow_dv_apply(struct rte_eth_dev *dev,
9605 struct rte_flow *flow,
9606 struct rte_flow_error *error)
9610 flow_dv_shared_lock(dev);
9611 ret = __flow_dv_apply(dev, flow, error);
9612 flow_dv_shared_unlock(dev);
9617 * Mutex-protected thunk to lock-free __flow_dv_remove().
9620 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9622 flow_dv_shared_lock(dev);
9623 __flow_dv_remove(dev, flow);
9624 flow_dv_shared_unlock(dev);
9628 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9631 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9633 flow_dv_shared_lock(dev);
9634 __flow_dv_destroy(dev, flow);
9635 flow_dv_shared_unlock(dev);
9639 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9642 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9646 flow_dv_shared_lock(dev);
9647 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9648 flow_dv_shared_unlock(dev);
9653 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9656 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9658 flow_dv_shared_lock(dev);
9659 flow_dv_counter_release(dev, cnt);
9660 flow_dv_shared_unlock(dev);
9663 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9664 .validate = flow_dv_validate,
9665 .prepare = flow_dv_prepare,
9666 .translate = flow_dv_translate,
9667 .apply = flow_dv_apply,
9668 .remove = flow_dv_remove,
9669 .destroy = flow_dv_destroy,
9670 .query = flow_dv_query,
9671 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9672 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9673 .create_policer_rules = flow_dv_create_policer_rules,
9674 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9675 .counter_alloc = flow_dv_counter_allocate,
9676 .counter_free = flow_dv_counter_free,
9677 .counter_query = flow_dv_counter_query,
9678 .get_aged_flows = flow_get_aged_flows,
9681 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */