drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rx.h"
  36 #include "mlx5_tx.h"
  37 #include "rte_pmd_mlx5.h"
  38
  39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  40
  41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  43 #endif
  44
  45 #ifndef HAVE_MLX5DV_DR_ESWITCH
  46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  48 #endif
  49 #endif
  50
  51 #ifndef HAVE_MLX5DV_DR
  52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  53 #endif
  54
  55 /* VLAN header definitions */
  56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  61
  62 union flow_dv_attr {
  63         struct {
  64                 uint32_t valid:1;
  65                 uint32_t ipv4:1;
  66                 uint32_t ipv6:1;
  67                 uint32_t tcp:1;
  68                 uint32_t udp:1;
  69                 uint32_t reserved:27;
  70         };
  71         uint32_t attr;
  72 };
  73
  74 static int
  75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  76                              struct mlx5_flow_tbl_resource *tbl);
  77
  78 static int
  79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  80                                      uint32_t encap_decap_idx);
  81
  82 static int
  83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  84                                         uint32_t port_id);
  85 static void
  86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  87
  88 static int
  89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  90                                   uint32_t rix_jump);
  91
  92 /**
  93  * Initialize flow attributes structure according to flow items' types.
  94  *
  95  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  96  * mode. For tunnel mode, the items to be modified are the outermost ones.
  97  *
  98  * @param[in] item
  99  *   Pointer to item specification.
 100  * @param[out] attr
 101  *   Pointer to flow attributes structure.
 102  * @param[in] dev_flow
 103  *   Pointer to the sub flow.
 104  * @param[in] tunnel_decap
 105  *   Whether action is after tunnel decapsulation.
 106  */
 107 static void
 108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 109                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 110 {
 111         uint64_t layers = dev_flow->handle->layers;
 112
 113         /*
 114          * If layers is already initialized, it means this dev_flow is the
 115          * suffix flow, the layers flags is set by the prefix flow. Need to
 116          * use the layer flags from prefix flow as the suffix flow may not
 117          * have the user defined items as the flow is split.
 118          */
 119         if (layers) {
 120                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 121                         attr->ipv4 = 1;
 122                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 123                         attr->ipv6 = 1;
 124                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 125                         attr->tcp = 1;
 126                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 127                         attr->udp = 1;
 128                 attr->valid = 1;
 129                 return;
 130         }
 131         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 132                 uint8_t next_protocol = 0xff;
 133                 switch (item->type) {
 134                 case RTE_FLOW_ITEM_TYPE_GRE:
 135                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 137                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 138                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 139                 case RTE_FLOW_ITEM_TYPE_MPLS:
 140                         if (tunnel_decap)
 141                                 attr->attr = 0;
 142                         break;
 143                 case RTE_FLOW_ITEM_TYPE_IPV4:
 144                         if (!attr->ipv6)
 145                                 attr->ipv4 = 1;
 146                         if (item->mask != NULL &&
 147                             ((const struct rte_flow_item_ipv4 *)
 148                             item->mask)->hdr.next_proto_id)
 149                                 next_protocol =
 150                                     ((const struct rte_flow_item_ipv4 *)
 151                                       (item->spec))->hdr.next_proto_id &
 152                                     ((const struct rte_flow_item_ipv4 *)
 153                                       (item->mask))->hdr.next_proto_id;
 154                         if ((next_protocol == IPPROTO_IPIP ||
 155                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 156                                 attr->attr = 0;
 157                         break;
 158                 case RTE_FLOW_ITEM_TYPE_IPV6:
 159                         if (!attr->ipv4)
 160                                 attr->ipv6 = 1;
 161                         if (item->mask != NULL &&
 162                             ((const struct rte_flow_item_ipv6 *)
 163                             item->mask)->hdr.proto)
 164                                 next_protocol =
 165                                     ((const struct rte_flow_item_ipv6 *)
 166                                       (item->spec))->hdr.proto &
 167                                     ((const struct rte_flow_item_ipv6 *)
 168                                       (item->mask))->hdr.proto;
 169                         if ((next_protocol == IPPROTO_IPIP ||
 170                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 171                                 attr->attr = 0;
 172                         break;
 173                 case RTE_FLOW_ITEM_TYPE_UDP:
 174                         if (!attr->tcp)
 175                                 attr->udp = 1;
 176                         break;
 177                 case RTE_FLOW_ITEM_TYPE_TCP:
 178                         if (!attr->udp)
 179                                 attr->tcp = 1;
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         }
 185         attr->valid = 1;
 186 }
 187
 188 struct field_modify_info {
 189         uint32_t size; /* Size of field in protocol header, in bytes. */
 190         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 191         enum mlx5_modification_field id;
 192 };
 193
 194 struct field_modify_info modify_eth[] = {
 195         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 196         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 197         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 198         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 199         {0, 0, 0},
 200 };
 201
 202 struct field_modify_info modify_vlan_out_first_vid[] = {
 203         /* Size in bits !!! */
 204         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 205         {0, 0, 0},
 206 };
 207
 208 struct field_modify_info modify_ipv4[] = {
 209         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 210         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 211         {4, 12, MLX5_MODI_OUT_SIPV4},
 212         {4, 16, MLX5_MODI_OUT_DIPV4},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_ipv6[] = {
 217         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 218         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 219         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 220         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 221         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 222         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 223         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 224         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 225         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 226         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_udp[] = {
 231         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 232         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_tcp[] = {
 237         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 238         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 239         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 240         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 241         {0, 0, 0},
 242 };
 243
 244 static void
 245 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 246                           uint8_t next_protocol, uint64_t *item_flags,
 247                           int *tunnel)
 248 {
 249         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 250                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 251         if (next_protocol == IPPROTO_IPIP) {
 252                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 253                 *tunnel = 1;
 254         }
 255         if (next_protocol == IPPROTO_IPV6) {
 256                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 257                 *tunnel = 1;
 258         }
 259 }
 260
 261 /* Update VLAN's VID/PCP based on input rte_flow_action.
 262  *
 263  * @param[in] action
 264  *   Pointer to struct rte_flow_action.
 265  * @param[out] vlan
 266  *   Pointer to struct rte_vlan_hdr.
 267  */
 268 static void
 269 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 270                          struct rte_vlan_hdr *vlan)
 271 {
 272         uint16_t vlan_tci;
 273         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 274                 vlan_tci =
 275                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 276                                                action->conf)->vlan_pcp;
 277                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 278                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 279                 vlan->vlan_tci |= vlan_tci;
 280         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 281                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 282                 vlan->vlan_tci |= rte_be_to_cpu_16
 283                     (((const struct rte_flow_action_of_set_vlan_vid *)
 284                                              action->conf)->vlan_vid);
 285         }
 286 }
 287
 288 /**
 289  * Fetch 1, 2, 3 or 4 byte field from the byte array
 290  * and return as unsigned integer in host-endian format.
 291  *
 292  * @param[in] data
 293  *   Pointer to data array.
 294  * @param[in] size
 295  *   Size of field to extract.
 296  *
 297  * @return
 298  *   converted field in host endian format.
 299  */
 300 static inline uint32_t
 301 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 302 {
 303         uint32_t ret;
 304
 305         switch (size) {
 306         case 1:
 307                 ret = *data;
 308                 break;
 309         case 2:
 310                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 311                 break;
 312         case 3:
 313                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 314                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 315                 break;
 316         case 4:
 317                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 318                 break;
 319         default:
 320                 MLX5_ASSERT(false);
 321                 ret = 0;
 322                 break;
 323         }
 324         return ret;
 325 }
 326
 327 /**
 328  * Convert modify-header action to DV specification.
 329  *
 330  * Data length of each action is determined by provided field description
 331  * and the item mask. Data bit offset and width of each action is determined
 332  * by provided item mask.
 333  *
 334  * @param[in] item
 335  *   Pointer to item specification.
 336  * @param[in] field
 337  *   Pointer to field modification information.
 338  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 339  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 340  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 341  * @param[in] dcopy
 342  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 343  *   Negative offset value sets the same offset as source offset.
 344  *   size field is ignored, value is taken from source field.
 345  * @param[in,out] resource
 346  *   Pointer to the modify-header resource.
 347  * @param[in] type
 348  *   Type of modification.
 349  * @param[out] error
 350  *   Pointer to the error structure.
 351  *
 352  * @return
 353  *   0 on success, a negative errno value otherwise and rte_errno is set.
 354  */
 355 static int
 356 flow_dv_convert_modify_action(struct rte_flow_item *item,
 357                               struct field_modify_info *field,
 358                               struct field_modify_info *dcopy,
 359                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 360                               uint32_t type, struct rte_flow_error *error)
 361 {
 362         uint32_t i = resource->actions_num;
 363         struct mlx5_modification_cmd *actions = resource->actions;
 364
 365         /*
 366          * The item and mask are provided in big-endian format.
 367          * The fields should be presented as in big-endian format either.
 368          * Mask must be always present, it defines the actual field width.
 369          */
 370         MLX5_ASSERT(item->mask);
 371         MLX5_ASSERT(field->size);
 372         do {
 373                 unsigned int size_b;
 374                 unsigned int off_b;
 375                 uint32_t mask;
 376                 uint32_t data;
 377
 378                 if (i >= MLX5_MAX_MODIFY_NUM)
 379                         return rte_flow_error_set(error, EINVAL,
 380                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 381                                  "too many items to modify");
 382                 /* Fetch variable byte size mask from the array. */
 383                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 384                                            field->offset, field->size);
 385                 if (!mask) {
 386                         ++field;
 387                         continue;
 388                 }
 389                 /* Deduce actual data width in bits from mask value. */
 390                 off_b = rte_bsf32(mask);
 391                 size_b = sizeof(uint32_t) * CHAR_BIT -
 392                          off_b - __builtin_clz(mask);
 393                 MLX5_ASSERT(size_b);
 394                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 395                 actions[i] = (struct mlx5_modification_cmd) {
 396                         .action_type = type,
 397                         .field = field->id,
 398                         .offset = off_b,
 399                         .length = size_b,
 400                 };
 401                 /* Convert entire record to expected big-endian format. */
 402                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 403                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 404                         MLX5_ASSERT(dcopy);
 405                         actions[i].dst_field = dcopy->id;
 406                         actions[i].dst_offset =
 407                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 408                         /* Convert entire record to big-endian format. */
 409                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 410                         ++dcopy;
 411                 } else {
 412                         MLX5_ASSERT(item->spec);
 413                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 414                                                    field->offset, field->size);
 415                         /* Shift out the trailing masked bits from data. */
 416                         data = (data & mask) >> off_b;
 417                         actions[i].data1 = rte_cpu_to_be_32(data);
 418                 }
 419                 ++i;
 420                 ++field;
 421         } while (field->size);
 422         if (resource->actions_num == i)
 423                 return rte_flow_error_set(error, EINVAL,
 424                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 425                                           "invalid modification flow item");
 426         resource->actions_num = i;
 427         return 0;
 428 }
 429
 430 /**
 431  * Convert modify-header set IPv4 address action to DV specification.
 432  *
 433  * @param[in,out] resource
 434  *   Pointer to the modify-header resource.
 435  * @param[in] action
 436  *   Pointer to action specification.
 437  * @param[out] error
 438  *   Pointer to the error structure.
 439  *
 440  * @return
 441  *   0 on success, a negative errno value otherwise and rte_errno is set.
 442  */
 443 static int
 444 flow_dv_convert_action_modify_ipv4
 445                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 446                          const struct rte_flow_action *action,
 447                          struct rte_flow_error *error)
 448 {
 449         const struct rte_flow_action_set_ipv4 *conf =
 450                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 451         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 452         struct rte_flow_item_ipv4 ipv4;
 453         struct rte_flow_item_ipv4 ipv4_mask;
 454
 455         memset(&ipv4, 0, sizeof(ipv4));
 456         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 457         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 458                 ipv4.hdr.src_addr = conf->ipv4_addr;
 459                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 460         } else {
 461                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 462                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 463         }
 464         item.spec = &ipv4;
 465         item.mask = &ipv4_mask;
 466         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 467                                              MLX5_MODIFICATION_TYPE_SET, error);
 468 }
 469
 470 /**
 471  * Convert modify-header set IPv6 address action to DV specification.
 472  *
 473  * @param[in,out] resource
 474  *   Pointer to the modify-header resource.
 475  * @param[in] action
 476  *   Pointer to action specification.
 477  * @param[out] error
 478  *   Pointer to the error structure.
 479  *
 480  * @return
 481  *   0 on success, a negative errno value otherwise and rte_errno is set.
 482  */
 483 static int
 484 flow_dv_convert_action_modify_ipv6
 485                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 486                          const struct rte_flow_action *action,
 487                          struct rte_flow_error *error)
 488 {
 489         const struct rte_flow_action_set_ipv6 *conf =
 490                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 491         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 492         struct rte_flow_item_ipv6 ipv6;
 493         struct rte_flow_item_ipv6 ipv6_mask;
 494
 495         memset(&ipv6, 0, sizeof(ipv6));
 496         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 497         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 498                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 499                        sizeof(ipv6.hdr.src_addr));
 500                 memcpy(&ipv6_mask.hdr.src_addr,
 501                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 502                        sizeof(ipv6.hdr.src_addr));
 503         } else {
 504                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 505                        sizeof(ipv6.hdr.dst_addr));
 506                 memcpy(&ipv6_mask.hdr.dst_addr,
 507                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 508                        sizeof(ipv6.hdr.dst_addr));
 509         }
 510         item.spec = &ipv6;
 511         item.mask = &ipv6_mask;
 512         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 513                                              MLX5_MODIFICATION_TYPE_SET, error);
 514 }
 515
 516 /**
 517  * Convert modify-header set MAC address action to DV specification.
 518  *
 519  * @param[in,out] resource
 520  *   Pointer to the modify-header resource.
 521  * @param[in] action
 522  *   Pointer to action specification.
 523  * @param[out] error
 524  *   Pointer to the error structure.
 525  *
 526  * @return
 527  *   0 on success, a negative errno value otherwise and rte_errno is set.
 528  */
 529 static int
 530 flow_dv_convert_action_modify_mac
 531                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 532                          const struct rte_flow_action *action,
 533                          struct rte_flow_error *error)
 534 {
 535         const struct rte_flow_action_set_mac *conf =
 536                 (const struct rte_flow_action_set_mac *)(action->conf);
 537         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 538         struct rte_flow_item_eth eth;
 539         struct rte_flow_item_eth eth_mask;
 540
 541         memset(&eth, 0, sizeof(eth));
 542         memset(&eth_mask, 0, sizeof(eth_mask));
 543         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 544                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 545                        sizeof(eth.src.addr_bytes));
 546                 memcpy(&eth_mask.src.addr_bytes,
 547                        &rte_flow_item_eth_mask.src.addr_bytes,
 548                        sizeof(eth_mask.src.addr_bytes));
 549         } else {
 550                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 551                        sizeof(eth.dst.addr_bytes));
 552                 memcpy(&eth_mask.dst.addr_bytes,
 553                        &rte_flow_item_eth_mask.dst.addr_bytes,
 554                        sizeof(eth_mask.dst.addr_bytes));
 555         }
 556         item.spec = &eth;
 557         item.mask = &eth_mask;
 558         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 559                                              MLX5_MODIFICATION_TYPE_SET, error);
 560 }
 561
 562 /**
 563  * Convert modify-header set VLAN VID action to DV specification.
 564  *
 565  * @param[in,out] resource
 566  *   Pointer to the modify-header resource.
 567  * @param[in] action
 568  *   Pointer to action specification.
 569  * @param[out] error
 570  *   Pointer to the error structure.
 571  *
 572  * @return
 573  *   0 on success, a negative errno value otherwise and rte_errno is set.
 574  */
 575 static int
 576 flow_dv_convert_action_modify_vlan_vid
 577                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 578                          const struct rte_flow_action *action,
 579                          struct rte_flow_error *error)
 580 {
 581         const struct rte_flow_action_of_set_vlan_vid *conf =
 582                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 583         int i = resource->actions_num;
 584         struct mlx5_modification_cmd *actions = resource->actions;
 585         struct field_modify_info *field = modify_vlan_out_first_vid;
 586
 587         if (i >= MLX5_MAX_MODIFY_NUM)
 588                 return rte_flow_error_set(error, EINVAL,
 589                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 590                          "too many items to modify");
 591         actions[i] = (struct mlx5_modification_cmd) {
 592                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 593                 .field = field->id,
 594                 .length = field->size,
 595                 .offset = field->offset,
 596         };
 597         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 598         actions[i].data1 = conf->vlan_vid;
 599         actions[i].data1 = actions[i].data1 << 16;
 600         resource->actions_num = ++i;
 601         return 0;
 602 }
 603
 604 /**
 605  * Convert modify-header set TP action to DV specification.
 606  *
 607  * @param[in,out] resource
 608  *   Pointer to the modify-header resource.
 609  * @param[in] action
 610  *   Pointer to action specification.
 611  * @param[in] items
 612  *   Pointer to rte_flow_item objects list.
 613  * @param[in] attr
 614  *   Pointer to flow attributes structure.
 615  * @param[in] dev_flow
 616  *   Pointer to the sub flow.
 617  * @param[in] tunnel_decap
 618  *   Whether action is after tunnel decapsulation.
 619  * @param[out] error
 620  *   Pointer to the error structure.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 static int
 626 flow_dv_convert_action_modify_tp
 627                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 628                          const struct rte_flow_action *action,
 629                          const struct rte_flow_item *items,
 630                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 631                          bool tunnel_decap, struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_set_tp *conf =
 634                 (const struct rte_flow_action_set_tp *)(action->conf);
 635         struct rte_flow_item item;
 636         struct rte_flow_item_udp udp;
 637         struct rte_flow_item_udp udp_mask;
 638         struct rte_flow_item_tcp tcp;
 639         struct rte_flow_item_tcp tcp_mask;
 640         struct field_modify_info *field;
 641
 642         if (!attr->valid)
 643                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 644         if (attr->udp) {
 645                 memset(&udp, 0, sizeof(udp));
 646                 memset(&udp_mask, 0, sizeof(udp_mask));
 647                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 648                         udp.hdr.src_port = conf->port;
 649                         udp_mask.hdr.src_port =
 650                                         rte_flow_item_udp_mask.hdr.src_port;
 651                 } else {
 652                         udp.hdr.dst_port = conf->port;
 653                         udp_mask.hdr.dst_port =
 654                                         rte_flow_item_udp_mask.hdr.dst_port;
 655                 }
 656                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 657                 item.spec = &udp;
 658                 item.mask = &udp_mask;
 659                 field = modify_udp;
 660         } else {
 661                 MLX5_ASSERT(attr->tcp);
 662                 memset(&tcp, 0, sizeof(tcp));
 663                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 664                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 665                         tcp.hdr.src_port = conf->port;
 666                         tcp_mask.hdr.src_port =
 667                                         rte_flow_item_tcp_mask.hdr.src_port;
 668                 } else {
 669                         tcp.hdr.dst_port = conf->port;
 670                         tcp_mask.hdr.dst_port =
 671                                         rte_flow_item_tcp_mask.hdr.dst_port;
 672                 }
 673                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 674                 item.spec = &tcp;
 675                 item.mask = &tcp_mask;
 676                 field = modify_tcp;
 677         }
 678         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 679                                              MLX5_MODIFICATION_TYPE_SET, error);
 680 }
 681
 682 /**
 683  * Convert modify-header set TTL action to DV specification.
 684  *
 685  * @param[in,out] resource
 686  *   Pointer to the modify-header resource.
 687  * @param[in] action
 688  *   Pointer to action specification.
 689  * @param[in] items
 690  *   Pointer to rte_flow_item objects list.
 691  * @param[in] attr
 692  *   Pointer to flow attributes structure.
 693  * @param[in] dev_flow
 694  *   Pointer to the sub flow.
 695  * @param[in] tunnel_decap
 696  *   Whether action is after tunnel decapsulation.
 697  * @param[out] error
 698  *   Pointer to the error structure.
 699  *
 700  * @return
 701  *   0 on success, a negative errno value otherwise and rte_errno is set.
 702  */
 703 static int
 704 flow_dv_convert_action_modify_ttl
 705                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 706                          const struct rte_flow_action *action,
 707                          const struct rte_flow_item *items,
 708                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 709                          bool tunnel_decap, struct rte_flow_error *error)
 710 {
 711         const struct rte_flow_action_set_ttl *conf =
 712                 (const struct rte_flow_action_set_ttl *)(action->conf);
 713         struct rte_flow_item item;
 714         struct rte_flow_item_ipv4 ipv4;
 715         struct rte_flow_item_ipv4 ipv4_mask;
 716         struct rte_flow_item_ipv6 ipv6;
 717         struct rte_flow_item_ipv6 ipv6_mask;
 718         struct field_modify_info *field;
 719
 720         if (!attr->valid)
 721                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 722         if (attr->ipv4) {
 723                 memset(&ipv4, 0, sizeof(ipv4));
 724                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 725                 ipv4.hdr.time_to_live = conf->ttl_value;
 726                 ipv4_mask.hdr.time_to_live = 0xFF;
 727                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 728                 item.spec = &ipv4;
 729                 item.mask = &ipv4_mask;
 730                 field = modify_ipv4;
 731         } else {
 732                 MLX5_ASSERT(attr->ipv6);
 733                 memset(&ipv6, 0, sizeof(ipv6));
 734                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 735                 ipv6.hdr.hop_limits = conf->ttl_value;
 736                 ipv6_mask.hdr.hop_limits = 0xFF;
 737                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 738                 item.spec = &ipv6;
 739                 item.mask = &ipv6_mask;
 740                 field = modify_ipv6;
 741         }
 742         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 743                                              MLX5_MODIFICATION_TYPE_SET, error);
 744 }
 745
 746 /**
 747  * Convert modify-header decrement TTL action to DV specification.
 748  *
 749  * @param[in,out] resource
 750  *   Pointer to the modify-header resource.
 751  * @param[in] action
 752  *   Pointer to action specification.
 753  * @param[in] items
 754  *   Pointer to rte_flow_item objects list.
 755  * @param[in] attr
 756  *   Pointer to flow attributes structure.
 757  * @param[in] dev_flow
 758  *   Pointer to the sub flow.
 759  * @param[in] tunnel_decap
 760  *   Whether action is after tunnel decapsulation.
 761  * @param[out] error
 762  *   Pointer to the error structure.
 763  *
 764  * @return
 765  *   0 on success, a negative errno value otherwise and rte_errno is set.
 766  */
 767 static int
 768 flow_dv_convert_action_modify_dec_ttl
 769                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 770                          const struct rte_flow_item *items,
 771                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 772                          bool tunnel_decap, struct rte_flow_error *error)
 773 {
 774         struct rte_flow_item item;
 775         struct rte_flow_item_ipv4 ipv4;
 776         struct rte_flow_item_ipv4 ipv4_mask;
 777         struct rte_flow_item_ipv6 ipv6;
 778         struct rte_flow_item_ipv6 ipv6_mask;
 779         struct field_modify_info *field;
 780
 781         if (!attr->valid)
 782                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 783         if (attr->ipv4) {
 784                 memset(&ipv4, 0, sizeof(ipv4));
 785                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 786                 ipv4.hdr.time_to_live = 0xFF;
 787                 ipv4_mask.hdr.time_to_live = 0xFF;
 788                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 789                 item.spec = &ipv4;
 790                 item.mask = &ipv4_mask;
 791                 field = modify_ipv4;
 792         } else {
 793                 MLX5_ASSERT(attr->ipv6);
 794                 memset(&ipv6, 0, sizeof(ipv6));
 795                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 796                 ipv6.hdr.hop_limits = 0xFF;
 797                 ipv6_mask.hdr.hop_limits = 0xFF;
 798                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 799                 item.spec = &ipv6;
 800                 item.mask = &ipv6_mask;
 801                 field = modify_ipv6;
 802         }
 803         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 804                                              MLX5_MODIFICATION_TYPE_ADD, error);
 805 }
 806
 807 /**
 808  * Convert modify-header increment/decrement TCP Sequence number
 809  * to DV specification.
 810  *
 811  * @param[in,out] resource
 812  *   Pointer to the modify-header resource.
 813  * @param[in] action
 814  *   Pointer to action specification.
 815  * @param[out] error
 816  *   Pointer to the error structure.
 817  *
 818  * @return
 819  *   0 on success, a negative errno value otherwise and rte_errno is set.
 820  */
 821 static int
 822 flow_dv_convert_action_modify_tcp_seq
 823                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 824                          const struct rte_flow_action *action,
 825                          struct rte_flow_error *error)
 826 {
 827         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 828         uint64_t value = rte_be_to_cpu_32(*conf);
 829         struct rte_flow_item item;
 830         struct rte_flow_item_tcp tcp;
 831         struct rte_flow_item_tcp tcp_mask;
 832
 833         memset(&tcp, 0, sizeof(tcp));
 834         memset(&tcp_mask, 0, sizeof(tcp_mask));
 835         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 836                 /*
 837                  * The HW has no decrement operation, only increment operation.
 838                  * To simulate decrement X from Y using increment operation
 839                  * we need to add UINT32_MAX X times to Y.
 840                  * Each adding of UINT32_MAX decrements Y by 1.
 841                  */
 842                 value *= UINT32_MAX;
 843         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 844         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 845         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 846         item.spec = &tcp;
 847         item.mask = &tcp_mask;
 848         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 849                                              MLX5_MODIFICATION_TYPE_ADD, error);
 850 }
 851
 852 /**
 853  * Convert modify-header increment/decrement TCP Acknowledgment number
 854  * to DV specification.
 855  *
 856  * @param[in,out] resource
 857  *   Pointer to the modify-header resource.
 858  * @param[in] action
 859  *   Pointer to action specification.
 860  * @param[out] error
 861  *   Pointer to the error structure.
 862  *
 863  * @return
 864  *   0 on success, a negative errno value otherwise and rte_errno is set.
 865  */
 866 static int
 867 flow_dv_convert_action_modify_tcp_ack
 868                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 869                          const struct rte_flow_action *action,
 870                          struct rte_flow_error *error)
 871 {
 872         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 873         uint64_t value = rte_be_to_cpu_32(*conf);
 874         struct rte_flow_item item;
 875         struct rte_flow_item_tcp tcp;
 876         struct rte_flow_item_tcp tcp_mask;
 877
 878         memset(&tcp, 0, sizeof(tcp));
 879         memset(&tcp_mask, 0, sizeof(tcp_mask));
 880         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 881                 /*
 882                  * The HW has no decrement operation, only increment operation.
 883                  * To simulate decrement X from Y using increment operation
 884                  * we need to add UINT32_MAX X times to Y.
 885                  * Each adding of UINT32_MAX decrements Y by 1.
 886                  */
 887                 value *= UINT32_MAX;
 888         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 889         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 890         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 891         item.spec = &tcp;
 892         item.mask = &tcp_mask;
 893         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 894                                              MLX5_MODIFICATION_TYPE_ADD, error);
 895 }
 896
 897 static enum mlx5_modification_field reg_to_field[] = {
 898         [REG_NON] = MLX5_MODI_OUT_NONE,
 899         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 900         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 901         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 902         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 903         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 904         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 905         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 906         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 907         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 908         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 909 };
 910
 911 /**
 912  * Convert register set to DV specification.
 913  *
 914  * @param[in,out] resource
 915  *   Pointer to the modify-header resource.
 916  * @param[in] action
 917  *   Pointer to action specification.
 918  * @param[out] error
 919  *   Pointer to the error structure.
 920  *
 921  * @return
 922  *   0 on success, a negative errno value otherwise and rte_errno is set.
 923  */
 924 static int
 925 flow_dv_convert_action_set_reg
 926                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 927                          const struct rte_flow_action *action,
 928                          struct rte_flow_error *error)
 929 {
 930         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 931         struct mlx5_modification_cmd *actions = resource->actions;
 932         uint32_t i = resource->actions_num;
 933
 934         if (i >= MLX5_MAX_MODIFY_NUM)
 935                 return rte_flow_error_set(error, EINVAL,
 936                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 937                                           "too many items to modify");
 938         MLX5_ASSERT(conf->id != REG_NON);
 939         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 940         actions[i] = (struct mlx5_modification_cmd) {
 941                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 942                 .field = reg_to_field[conf->id],
 943                 .offset = conf->offset,
 944                 .length = conf->length,
 945         };
 946         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 947         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 948         ++i;
 949         resource->actions_num = i;
 950         return 0;
 951 }
 952
 953 /**
 954  * Convert SET_TAG action to DV specification.
 955  *
 956  * @param[in] dev
 957  *   Pointer to the rte_eth_dev structure.
 958  * @param[in,out] resource
 959  *   Pointer to the modify-header resource.
 960  * @param[in] conf
 961  *   Pointer to action specification.
 962  * @param[out] error
 963  *   Pointer to the error structure.
 964  *
 965  * @return
 966  *   0 on success, a negative errno value otherwise and rte_errno is set.
 967  */
 968 static int
 969 flow_dv_convert_action_set_tag
 970                         (struct rte_eth_dev *dev,
 971                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 972                          const struct rte_flow_action_set_tag *conf,
 973                          struct rte_flow_error *error)
 974 {
 975         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 976         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 977         struct rte_flow_item item = {
 978                 .spec = &data,
 979                 .mask = &mask,
 980         };
 981         struct field_modify_info reg_c_x[] = {
 982                 [1] = {0, 0, 0},
 983         };
 984         enum mlx5_modification_field reg_type;
 985         int ret;
 986
 987         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
 988         if (ret < 0)
 989                 return ret;
 990         MLX5_ASSERT(ret != REG_NON);
 991         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
 992         reg_type = reg_to_field[ret];
 993         MLX5_ASSERT(reg_type > 0);
 994         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
 995         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
 996                                              MLX5_MODIFICATION_TYPE_SET, error);
 997 }
 998
 999 /**
1000  * Convert internal COPY_REG action to DV specification.
1001  *
1002  * @param[in] dev
1003  *   Pointer to the rte_eth_dev structure.
1004  * @param[in,out] res
1005  *   Pointer to the modify-header resource.
1006  * @param[in] action
1007  *   Pointer to action specification.
1008  * @param[out] error
1009  *   Pointer to the error structure.
1010  *
1011  * @return
1012  *   0 on success, a negative errno value otherwise and rte_errno is set.
1013  */
1014 static int
1015 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1016                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1017                                  const struct rte_flow_action *action,
1018                                  struct rte_flow_error *error)
1019 {
1020         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1021         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1022         struct rte_flow_item item = {
1023                 .spec = NULL,
1024                 .mask = &mask,
1025         };
1026         struct field_modify_info reg_src[] = {
1027                 {4, 0, reg_to_field[conf->src]},
1028                 {0, 0, 0},
1029         };
1030         struct field_modify_info reg_dst = {
1031                 .offset = 0,
1032                 .id = reg_to_field[conf->dst],
1033         };
1034         /* Adjust reg_c[0] usage according to reported mask. */
1035         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1036                 struct mlx5_priv *priv = dev->data->dev_private;
1037                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1038
1039                 MLX5_ASSERT(reg_c0);
1040                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1041                 if (conf->dst == REG_C_0) {
1042                         /* Copy to reg_c[0], within mask only. */
1043                         reg_dst.offset = rte_bsf32(reg_c0);
1044                         /*
1045                          * Mask is ignoring the enianness, because
1046                          * there is no conversion in datapath.
1047                          */
1048 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1049                         /* Copy from destination lower bits to reg_c[0]. */
1050                         mask = reg_c0 >> reg_dst.offset;
1051 #else
1052                         /* Copy from destination upper bits to reg_c[0]. */
1053                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1054                                           rte_fls_u32(reg_c0));
1055 #endif
1056                 } else {
1057                         mask = rte_cpu_to_be_32(reg_c0);
1058 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1059                         /* Copy from reg_c[0] to destination lower bits. */
1060                         reg_dst.offset = 0;
1061 #else
1062                         /* Copy from reg_c[0] to destination upper bits. */
1063                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1064                                          (rte_fls_u32(reg_c0) -
1065                                           rte_bsf32(reg_c0));
1066 #endif
1067                 }
1068         }
1069         return flow_dv_convert_modify_action(&item,
1070                                              reg_src, &reg_dst, res,
1071                                              MLX5_MODIFICATION_TYPE_COPY,
1072                                              error);
1073 }
1074
1075 /**
1076  * Convert MARK action to DV specification. This routine is used
1077  * in extensive metadata only and requires metadata register to be
1078  * handled. In legacy mode hardware tag resource is engaged.
1079  *
1080  * @param[in] dev
1081  *   Pointer to the rte_eth_dev structure.
1082  * @param[in] conf
1083  *   Pointer to MARK action specification.
1084  * @param[in,out] resource
1085  *   Pointer to the modify-header resource.
1086  * @param[out] error
1087  *   Pointer to the error structure.
1088  *
1089  * @return
1090  *   0 on success, a negative errno value otherwise and rte_errno is set.
1091  */
1092 static int
1093 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1094                             const struct rte_flow_action_mark *conf,
1095                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1096                             struct rte_flow_error *error)
1097 {
1098         struct mlx5_priv *priv = dev->data->dev_private;
1099         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1100                                            priv->sh->dv_mark_mask);
1101         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1102         struct rte_flow_item item = {
1103                 .spec = &data,
1104                 .mask = &mask,
1105         };
1106         struct field_modify_info reg_c_x[] = {
1107                 [1] = {0, 0, 0},
1108         };
1109         int reg;
1110
1111         if (!mask)
1112                 return rte_flow_error_set(error, EINVAL,
1113                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1114                                           NULL, "zero mark action mask");
1115         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1116         if (reg < 0)
1117                 return reg;
1118         MLX5_ASSERT(reg > 0);
1119         if (reg == REG_C_0) {
1120                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1121                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1122
1123                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1124                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1125                 mask = rte_cpu_to_be_32(mask << shl_c0);
1126         }
1127         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1128         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1129                                              MLX5_MODIFICATION_TYPE_SET, error);
1130 }
1131
1132 /**
1133  * Get metadata register index for specified steering domain.
1134  *
1135  * @param[in] dev
1136  *   Pointer to the rte_eth_dev structure.
1137  * @param[in] attr
1138  *   Attributes of flow to determine steering domain.
1139  * @param[out] error
1140  *   Pointer to the error structure.
1141  *
1142  * @return
1143  *   positive index on success, a negative errno value otherwise
1144  *   and rte_errno is set.
1145  */
1146 static enum modify_reg
1147 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1148                          const struct rte_flow_attr *attr,
1149                          struct rte_flow_error *error)
1150 {
1151         int reg =
1152                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1153                                           MLX5_METADATA_FDB :
1154                                             attr->egress ?
1155                                             MLX5_METADATA_TX :
1156                                             MLX5_METADATA_RX, 0, error);
1157         if (reg < 0)
1158                 return rte_flow_error_set(error,
1159                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1160                                           NULL, "unavailable "
1161                                           "metadata register");
1162         return reg;
1163 }
1164
1165 /**
1166  * Convert SET_META action to DV specification.
1167  *
1168  * @param[in] dev
1169  *   Pointer to the rte_eth_dev structure.
1170  * @param[in,out] resource
1171  *   Pointer to the modify-header resource.
1172  * @param[in] attr
1173  *   Attributes of flow that includes this item.
1174  * @param[in] conf
1175  *   Pointer to action specification.
1176  * @param[out] error
1177  *   Pointer to the error structure.
1178  *
1179  * @return
1180  *   0 on success, a negative errno value otherwise and rte_errno is set.
1181  */
1182 static int
1183 flow_dv_convert_action_set_meta
1184                         (struct rte_eth_dev *dev,
1185                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1186                          const struct rte_flow_attr *attr,
1187                          const struct rte_flow_action_set_meta *conf,
1188                          struct rte_flow_error *error)
1189 {
1190         uint32_t data = conf->data;
1191         uint32_t mask = conf->mask;
1192         struct rte_flow_item item = {
1193                 .spec = &data,
1194                 .mask = &mask,
1195         };
1196         struct field_modify_info reg_c_x[] = {
1197                 [1] = {0, 0, 0},
1198         };
1199         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1200
1201         if (reg < 0)
1202                 return reg;
1203         MLX5_ASSERT(reg != REG_NON);
1204         /*
1205          * In datapath code there is no endianness
1206          * coversions for perfromance reasons, all
1207          * pattern conversions are done in rte_flow.
1208          */
1209         if (reg == REG_C_0) {
1210                 struct mlx5_priv *priv = dev->data->dev_private;
1211                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1212                 uint32_t shl_c0;
1213
1214                 MLX5_ASSERT(msk_c0);
1215 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1216                 shl_c0 = rte_bsf32(msk_c0);
1217 #else
1218                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1219 #endif
1220                 mask <<= shl_c0;
1221                 data <<= shl_c0;
1222                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1223         }
1224         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1225         /* The routine expects parameters in memory as big-endian ones. */
1226         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1227                                              MLX5_MODIFICATION_TYPE_SET, error);
1228 }
1229
1230 /**
1231  * Convert modify-header set IPv4 DSCP action to DV specification.
1232  *
1233  * @param[in,out] resource
1234  *   Pointer to the modify-header resource.
1235  * @param[in] action
1236  *   Pointer to action specification.
1237  * @param[out] error
1238  *   Pointer to the error structure.
1239  *
1240  * @return
1241  *   0 on success, a negative errno value otherwise and rte_errno is set.
1242  */
1243 static int
1244 flow_dv_convert_action_modify_ipv4_dscp
1245                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1246                          const struct rte_flow_action *action,
1247                          struct rte_flow_error *error)
1248 {
1249         const struct rte_flow_action_set_dscp *conf =
1250                 (const struct rte_flow_action_set_dscp *)(action->conf);
1251         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1252         struct rte_flow_item_ipv4 ipv4;
1253         struct rte_flow_item_ipv4 ipv4_mask;
1254
1255         memset(&ipv4, 0, sizeof(ipv4));
1256         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1257         ipv4.hdr.type_of_service = conf->dscp;
1258         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1259         item.spec = &ipv4;
1260         item.mask = &ipv4_mask;
1261         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1262                                              MLX5_MODIFICATION_TYPE_SET, error);
1263 }
1264
1265 /**
1266  * Convert modify-header set IPv6 DSCP action to DV specification.
1267  *
1268  * @param[in,out] resource
1269  *   Pointer to the modify-header resource.
1270  * @param[in] action
1271  *   Pointer to action specification.
1272  * @param[out] error
1273  *   Pointer to the error structure.
1274  *
1275  * @return
1276  *   0 on success, a negative errno value otherwise and rte_errno is set.
1277  */
1278 static int
1279 flow_dv_convert_action_modify_ipv6_dscp
1280                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1281                          const struct rte_flow_action *action,
1282                          struct rte_flow_error *error)
1283 {
1284         const struct rte_flow_action_set_dscp *conf =
1285                 (const struct rte_flow_action_set_dscp *)(action->conf);
1286         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1287         struct rte_flow_item_ipv6 ipv6;
1288         struct rte_flow_item_ipv6 ipv6_mask;
1289
1290         memset(&ipv6, 0, sizeof(ipv6));
1291         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1292         /*
1293          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1294          * rdma-core only accept the DSCP bits byte aligned start from
1295          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1296          * bits in IPv6 case as rdma-core requires byte aligned value.
1297          */
1298         ipv6.hdr.vtc_flow = conf->dscp;
1299         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1300         item.spec = &ipv6;
1301         item.mask = &ipv6_mask;
1302         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1303                                              MLX5_MODIFICATION_TYPE_SET, error);
1304 }
1305
1306 static int
1307 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1308 {
1309         switch (field) {
1310         case RTE_FLOW_FIELD_START:
1311                 return 32;
1312         case RTE_FLOW_FIELD_MAC_DST:
1313         case RTE_FLOW_FIELD_MAC_SRC:
1314                 return 48;
1315         case RTE_FLOW_FIELD_VLAN_TYPE:
1316                 return 16;
1317         case RTE_FLOW_FIELD_VLAN_ID:
1318                 return 12;
1319         case RTE_FLOW_FIELD_MAC_TYPE:
1320                 return 16;
1321         case RTE_FLOW_FIELD_IPV4_DSCP:
1322                 return 6;
1323         case RTE_FLOW_FIELD_IPV4_TTL:
1324                 return 8;
1325         case RTE_FLOW_FIELD_IPV4_SRC:
1326         case RTE_FLOW_FIELD_IPV4_DST:
1327                 return 32;
1328         case RTE_FLOW_FIELD_IPV6_DSCP:
1329                 return 6;
1330         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1331                 return 8;
1332         case RTE_FLOW_FIELD_IPV6_SRC:
1333         case RTE_FLOW_FIELD_IPV6_DST:
1334                 return 128;
1335         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1336         case RTE_FLOW_FIELD_TCP_PORT_DST:
1337                 return 16;
1338         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1339         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1340                 return 32;
1341         case RTE_FLOW_FIELD_TCP_FLAGS:
1342                 return 6;
1343         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1344         case RTE_FLOW_FIELD_UDP_PORT_DST:
1345                 return 16;
1346         case RTE_FLOW_FIELD_VXLAN_VNI:
1347         case RTE_FLOW_FIELD_GENEVE_VNI:
1348                 return 24;
1349         case RTE_FLOW_FIELD_GTP_TEID:
1350         case RTE_FLOW_FIELD_TAG:
1351                 return 32;
1352         case RTE_FLOW_FIELD_MARK:
1353                 return 24;
1354         case RTE_FLOW_FIELD_META:
1355                 return 32;
1356         case RTE_FLOW_FIELD_POINTER:
1357         case RTE_FLOW_FIELD_VALUE:
1358                 return 64;
1359         default:
1360                 MLX5_ASSERT(false);
1361         }
1362         return 0;
1363 }
1364
1365 static void
1366 mlx5_flow_field_id_to_modify_info
1367                 (const struct rte_flow_action_modify_data *data,
1368                  struct field_modify_info *info,
1369                  uint32_t *mask, uint32_t *value,
1370                  uint32_t width, uint32_t dst_width,
1371                  struct rte_eth_dev *dev,
1372                  const struct rte_flow_attr *attr,
1373                  struct rte_flow_error *error)
1374 {
1375         uint32_t idx = 0;
1376         uint64_t val = 0;
1377         switch (data->field) {
1378         case RTE_FLOW_FIELD_START:
1379                 /* not supported yet */
1380                 MLX5_ASSERT(false);
1381                 break;
1382         case RTE_FLOW_FIELD_MAC_DST:
1383                 if (mask) {
1384                         if (data->offset < 32) {
1385                                 info[idx] = (struct field_modify_info){4, 0,
1386                                                 MLX5_MODI_OUT_DMAC_47_16};
1387                                 if (width < 32) {
1388                                         mask[idx] =
1389                                                 rte_cpu_to_be_32(0xffffffff >>
1390                                                                  (32 - width));
1391                                         width = 0;
1392                                 } else {
1393                                         mask[idx] = RTE_BE32(0xffffffff);
1394                                         width -= 32;
1395                                 }
1396                                 if (!width)
1397                                         break;
1398                                 ++idx;
1399                         }
1400                         info[idx] = (struct field_modify_info){2, 4 * idx,
1401                                                 MLX5_MODI_OUT_DMAC_15_0};
1402                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1403                 } else {
1404                         if (data->offset < 32)
1405                                 info[idx++] = (struct field_modify_info){4, 0,
1406                                                 MLX5_MODI_OUT_DMAC_47_16};
1407                         info[idx] = (struct field_modify_info){2, 0,
1408                                                 MLX5_MODI_OUT_DMAC_15_0};
1409                 }
1410                 break;
1411         case RTE_FLOW_FIELD_MAC_SRC:
1412                 if (mask) {
1413                         if (data->offset < 32) {
1414                                 info[idx] = (struct field_modify_info){4, 0,
1415                                                 MLX5_MODI_OUT_SMAC_47_16};
1416                                 if (width < 32) {
1417                                         mask[idx] =
1418                                                 rte_cpu_to_be_32(0xffffffff >>
1419                                                                 (32 - width));
1420                                         width = 0;
1421                                 } else {
1422                                         mask[idx] = RTE_BE32(0xffffffff);
1423                                         width -= 32;
1424                                 }
1425                                 if (!width)
1426                                         break;
1427                                 ++idx;
1428                         }
1429                         info[idx] = (struct field_modify_info){2, 4 * idx,
1430                                                 MLX5_MODI_OUT_SMAC_15_0};
1431                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1432                 } else {
1433                         if (data->offset < 32)
1434                                 info[idx++] = (struct field_modify_info){4, 0,
1435                                                 MLX5_MODI_OUT_SMAC_47_16};
1436                         info[idx] = (struct field_modify_info){2, 0,
1437                                                 MLX5_MODI_OUT_SMAC_15_0};
1438                 }
1439                 break;
1440         case RTE_FLOW_FIELD_VLAN_TYPE:
1441                 /* not supported yet */
1442                 break;
1443         case RTE_FLOW_FIELD_VLAN_ID:
1444                 info[idx] = (struct field_modify_info){2, 0,
1445                                         MLX5_MODI_OUT_FIRST_VID};
1446                 if (mask)
1447                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1448                 break;
1449         case RTE_FLOW_FIELD_MAC_TYPE:
1450                 info[idx] = (struct field_modify_info){2, 0,
1451                                         MLX5_MODI_OUT_ETHERTYPE};
1452                 if (mask)
1453                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV4_DSCP:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IP_DSCP};
1458                 if (mask)
1459                         mask[idx] = 0x3f >> (6 - width);
1460                 break;
1461         case RTE_FLOW_FIELD_IPV4_TTL:
1462                 info[idx] = (struct field_modify_info){1, 0,
1463                                         MLX5_MODI_OUT_IPV4_TTL};
1464                 if (mask)
1465                         mask[idx] = 0xff >> (8 - width);
1466                 break;
1467         case RTE_FLOW_FIELD_IPV4_SRC:
1468                 info[idx] = (struct field_modify_info){4, 0,
1469                                         MLX5_MODI_OUT_SIPV4};
1470                 if (mask)
1471                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1472                                                      (32 - width));
1473                 break;
1474         case RTE_FLOW_FIELD_IPV4_DST:
1475                 info[idx] = (struct field_modify_info){4, 0,
1476                                         MLX5_MODI_OUT_DIPV4};
1477                 if (mask)
1478                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1479                                                      (32 - width));
1480                 break;
1481         case RTE_FLOW_FIELD_IPV6_DSCP:
1482                 info[idx] = (struct field_modify_info){1, 0,
1483                                         MLX5_MODI_OUT_IP_DSCP};
1484                 if (mask)
1485                         mask[idx] = 0x3f >> (6 - width);
1486                 break;
1487         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1488                 info[idx] = (struct field_modify_info){1, 0,
1489                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1490                 if (mask)
1491                         mask[idx] = 0xff >> (8 - width);
1492                 break;
1493         case RTE_FLOW_FIELD_IPV6_SRC:
1494                 if (mask) {
1495                         if (data->offset < 32) {
1496                                 info[idx] = (struct field_modify_info){4,
1497                                                 4 * idx,
1498                                                 MLX5_MODI_OUT_SIPV6_31_0};
1499                                 if (width < 32) {
1500                                         mask[idx] =
1501                                                 rte_cpu_to_be_32(0xffffffff >>
1502                                                                  (32 - width));
1503                                         width = 0;
1504                                 } else {
1505                                         mask[idx] = RTE_BE32(0xffffffff);
1506                                         width -= 32;
1507                                 }
1508                                 if (!width)
1509                                         break;
1510                                 ++idx;
1511                         }
1512                         if (data->offset < 64) {
1513                                 info[idx] = (struct field_modify_info){4,
1514                                                 4 * idx,
1515                                                 MLX5_MODI_OUT_SIPV6_63_32};
1516                                 if (width < 32) {
1517                                         mask[idx] =
1518                                                 rte_cpu_to_be_32(0xffffffff >>
1519                                                                  (32 - width));
1520                                         width = 0;
1521                                 } else {
1522                                         mask[idx] = RTE_BE32(0xffffffff);
1523                                         width -= 32;
1524                                 }
1525                                 if (!width)
1526                                         break;
1527                                 ++idx;
1528                         }
1529                         if (data->offset < 96) {
1530                                 info[idx] = (struct field_modify_info){4,
1531                                                 4 * idx,
1532                                                 MLX5_MODI_OUT_SIPV6_95_64};
1533                                 if (width < 32) {
1534                                         mask[idx] =
1535                                                 rte_cpu_to_be_32(0xffffffff >>
1536                                                                  (32 - width));
1537                                         width = 0;
1538                                 } else {
1539                                         mask[idx] = RTE_BE32(0xffffffff);
1540                                         width -= 32;
1541                                 }
1542                                 if (!width)
1543                                         break;
1544                                 ++idx;
1545                         }
1546                         info[idx] = (struct field_modify_info){4, 4 * idx,
1547                                                 MLX5_MODI_OUT_SIPV6_127_96};
1548                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1549                                                      (32 - width));
1550                 } else {
1551                         if (data->offset < 32)
1552                                 info[idx++] = (struct field_modify_info){4, 0,
1553                                                 MLX5_MODI_OUT_SIPV6_31_0};
1554                         if (data->offset < 64)
1555                                 info[idx++] = (struct field_modify_info){4, 0,
1556                                                 MLX5_MODI_OUT_SIPV6_63_32};
1557                         if (data->offset < 96)
1558                                 info[idx++] = (struct field_modify_info){4, 0,
1559                                                 MLX5_MODI_OUT_SIPV6_95_64};
1560                         if (data->offset < 128)
1561                                 info[idx++] = (struct field_modify_info){4, 0,
1562                                                 MLX5_MODI_OUT_SIPV6_127_96};
1563                 }
1564                 break;
1565         case RTE_FLOW_FIELD_IPV6_DST:
1566                 if (mask) {
1567                         if (data->offset < 32) {
1568                                 info[idx] = (struct field_modify_info){4,
1569                                                 4 * idx,
1570                                                 MLX5_MODI_OUT_DIPV6_31_0};
1571                                 if (width < 32) {
1572                                         mask[idx] =
1573                                                 rte_cpu_to_be_32(0xffffffff >>
1574                                                                  (32 - width));
1575                                         width = 0;
1576                                 } else {
1577                                         mask[idx] = RTE_BE32(0xffffffff);
1578                                         width -= 32;
1579                                 }
1580                                 if (!width)
1581                                         break;
1582                                 ++idx;
1583                         }
1584                         if (data->offset < 64) {
1585                                 info[idx] = (struct field_modify_info){4,
1586                                                 4 * idx,
1587                                                 MLX5_MODI_OUT_DIPV6_63_32};
1588                                 if (width < 32) {
1589                                         mask[idx] =
1590                                                 rte_cpu_to_be_32(0xffffffff >>
1591                                                                  (32 - width));
1592                                         width = 0;
1593                                 } else {
1594                                         mask[idx] = RTE_BE32(0xffffffff);
1595                                         width -= 32;
1596                                 }
1597                                 if (!width)
1598                                         break;
1599                                 ++idx;
1600                         }
1601                         if (data->offset < 96) {
1602                                 info[idx] = (struct field_modify_info){4,
1603                                                 4 * idx,
1604                                                 MLX5_MODI_OUT_DIPV6_95_64};
1605                                 if (width < 32) {
1606                                         mask[idx] =
1607                                                 rte_cpu_to_be_32(0xffffffff >>
1608                                                                  (32 - width));
1609                                         width = 0;
1610                                 } else {
1611                                         mask[idx] = RTE_BE32(0xffffffff);
1612                                         width -= 32;
1613                                 }
1614                                 if (!width)
1615                                         break;
1616                                 ++idx;
1617                         }
1618                         info[idx] = (struct field_modify_info){4, 4 * idx,
1619                                                 MLX5_MODI_OUT_DIPV6_127_96};
1620                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1621                                                      (32 - width));
1622                 } else {
1623                         if (data->offset < 32)
1624                                 info[idx++] = (struct field_modify_info){4, 0,
1625                                                 MLX5_MODI_OUT_DIPV6_31_0};
1626                         if (data->offset < 64)
1627                                 info[idx++] = (struct field_modify_info){4, 0,
1628                                                 MLX5_MODI_OUT_DIPV6_63_32};
1629                         if (data->offset < 96)
1630                                 info[idx++] = (struct field_modify_info){4, 0,
1631                                                 MLX5_MODI_OUT_DIPV6_95_64};
1632                         if (data->offset < 128)
1633                                 info[idx++] = (struct field_modify_info){4, 0,
1634                                                 MLX5_MODI_OUT_DIPV6_127_96};
1635                 }
1636                 break;
1637         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1638                 info[idx] = (struct field_modify_info){2, 0,
1639                                         MLX5_MODI_OUT_TCP_SPORT};
1640                 if (mask)
1641                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1642                 break;
1643         case RTE_FLOW_FIELD_TCP_PORT_DST:
1644                 info[idx] = (struct field_modify_info){2, 0,
1645                                         MLX5_MODI_OUT_TCP_DPORT};
1646                 if (mask)
1647                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1648                 break;
1649         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1650                 info[idx] = (struct field_modify_info){4, 0,
1651                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1652                 if (mask)
1653                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1654                                                      (32 - width));
1655                 break;
1656         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1657                 info[idx] = (struct field_modify_info){4, 0,
1658                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1659                 if (mask)
1660                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1661                                                      (32 - width));
1662                 break;
1663         case RTE_FLOW_FIELD_TCP_FLAGS:
1664                 info[idx] = (struct field_modify_info){1, 0,
1665                                         MLX5_MODI_OUT_TCP_FLAGS};
1666                 if (mask)
1667                         mask[idx] = 0x3f >> (6 - width);
1668                 break;
1669         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1670                 info[idx] = (struct field_modify_info){2, 0,
1671                                         MLX5_MODI_OUT_UDP_SPORT};
1672                 if (mask)
1673                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1674                 break;
1675         case RTE_FLOW_FIELD_UDP_PORT_DST:
1676                 info[idx] = (struct field_modify_info){2, 0,
1677                                         MLX5_MODI_OUT_UDP_DPORT};
1678                 if (mask)
1679                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1680                 break;
1681         case RTE_FLOW_FIELD_VXLAN_VNI:
1682                 /* not supported yet */
1683                 break;
1684         case RTE_FLOW_FIELD_GENEVE_VNI:
1685                 /* not supported yet*/
1686                 break;
1687         case RTE_FLOW_FIELD_GTP_TEID:
1688                 info[idx] = (struct field_modify_info){4, 0,
1689                                         MLX5_MODI_GTP_TEID};
1690                 if (mask)
1691                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1692                                                      (32 - width));
1693                 break;
1694         case RTE_FLOW_FIELD_TAG:
1695                 {
1696                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1697                                                    data->level, error);
1698                         if (reg < 0)
1699                                 return;
1700                         MLX5_ASSERT(reg != REG_NON);
1701                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1702                         info[idx] = (struct field_modify_info){4, 0,
1703                                                 reg_to_field[reg]};
1704                         if (mask)
1705                                 mask[idx] =
1706                                         rte_cpu_to_be_32(0xffffffff >>
1707                                                          (32 - width));
1708                 }
1709                 break;
1710         case RTE_FLOW_FIELD_MARK:
1711                 {
1712                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1713                                                        0, error);
1714                         if (reg < 0)
1715                                 return;
1716                         MLX5_ASSERT(reg != REG_NON);
1717                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1718                         info[idx] = (struct field_modify_info){4, 0,
1719                                                 reg_to_field[reg]};
1720                         if (mask)
1721                                 mask[idx] =
1722                                         rte_cpu_to_be_32(0xffffffff >>
1723                                                          (32 - width));
1724                 }
1725                 break;
1726         case RTE_FLOW_FIELD_META:
1727                 {
1728                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1729                         if (reg < 0)
1730                                 return;
1731                         MLX5_ASSERT(reg != REG_NON);
1732                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1733                         info[idx] = (struct field_modify_info){4, 0,
1734                                                 reg_to_field[reg]};
1735                         if (mask)
1736                                 mask[idx] =
1737                                         rte_cpu_to_be_32(0xffffffff >>
1738                                                          (32 - width));
1739                 }
1740                 break;
1741         case RTE_FLOW_FIELD_POINTER:
1742         case RTE_FLOW_FIELD_VALUE:
1743                 if (data->field == RTE_FLOW_FIELD_POINTER)
1744                         memcpy(&val, (void *)(uintptr_t)data->value,
1745                                sizeof(uint64_t));
1746                 else
1747                         val = data->value;
1748                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1749                         if (mask[idx]) {
1750                                 if (dst_width > 16) {
1751                                         value[idx] = rte_cpu_to_be_32(val);
1752                                         val >>= 32;
1753                                 } else if (dst_width > 8) {
1754                                         value[idx] = rte_cpu_to_be_16(val);
1755                                         val >>= 16;
1756                                 } else {
1757                                         value[idx] = (uint8_t)val;
1758                                         val >>= 8;
1759                                 }
1760                                 if (!val)
1761                                         break;
1762                         }
1763                 }
1764                 break;
1765         default:
1766                 MLX5_ASSERT(false);
1767                 break;
1768         }
1769 }
1770
1771 /**
1772  * Convert modify_field action to DV specification.
1773  *
1774  * @param[in] dev
1775  *   Pointer to the rte_eth_dev structure.
1776  * @param[in,out] resource
1777  *   Pointer to the modify-header resource.
1778  * @param[in] action
1779  *   Pointer to action specification.
1780  * @param[in] attr
1781  *   Attributes of flow that includes this item.
1782  * @param[out] error
1783  *   Pointer to the error structure.
1784  *
1785  * @return
1786  *   0 on success, a negative errno value otherwise and rte_errno is set.
1787  */
1788 static int
1789 flow_dv_convert_action_modify_field
1790                         (struct rte_eth_dev *dev,
1791                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1792                          const struct rte_flow_action *action,
1793                          const struct rte_flow_attr *attr,
1794                          struct rte_flow_error *error)
1795 {
1796         const struct rte_flow_action_modify_field *conf =
1797                 (const struct rte_flow_action_modify_field *)(action->conf);
1798         struct rte_flow_item item;
1799         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1800                                                                 {0, 0, 0} };
1801         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1802                                                                 {0, 0, 0} };
1803         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1804         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1805         uint32_t type;
1806         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1807
1808         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1809                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1810                 type = MLX5_MODIFICATION_TYPE_SET;
1811                 /** For SET fill the destination field (field) first. */
1812                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1813                         value, conf->width, dst_width, dev, attr, error);
1814                 /** Then copy immediate value from source as per mask. */
1815                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1816                         value, conf->width, dst_width, dev, attr, error);
1817                 item.spec = &value;
1818         } else {
1819                 type = MLX5_MODIFICATION_TYPE_COPY;
1820                 /** For COPY fill the destination field (dcopy) without mask. */
1821                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1822                         value, conf->width, dst_width, dev, attr, error);
1823                 /** Then construct the source field (field) with mask. */
1824                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1825                         value, conf->width, dst_width, dev, attr, error);
1826         }
1827         item.mask = &mask;
1828         return flow_dv_convert_modify_action(&item,
1829                         field, dcopy, resource, type, error);
1830 }
1831
1832 /**
1833  * Validate MARK item.
1834  *
1835  * @param[in] dev
1836  *   Pointer to the rte_eth_dev structure.
1837  * @param[in] item
1838  *   Item specification.
1839  * @param[in] attr
1840  *   Attributes of flow that includes this item.
1841  * @param[out] error
1842  *   Pointer to error structure.
1843  *
1844  * @return
1845  *   0 on success, a negative errno value otherwise and rte_errno is set.
1846  */
1847 static int
1848 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1849                            const struct rte_flow_item *item,
1850                            const struct rte_flow_attr *attr __rte_unused,
1851                            struct rte_flow_error *error)
1852 {
1853         struct mlx5_priv *priv = dev->data->dev_private;
1854         struct mlx5_dev_config *config = &priv->config;
1855         const struct rte_flow_item_mark *spec = item->spec;
1856         const struct rte_flow_item_mark *mask = item->mask;
1857         const struct rte_flow_item_mark nic_mask = {
1858                 .id = priv->sh->dv_mark_mask,
1859         };
1860         int ret;
1861
1862         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1863                 return rte_flow_error_set(error, ENOTSUP,
1864                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1865                                           "extended metadata feature"
1866                                           " isn't enabled");
1867         if (!mlx5_flow_ext_mreg_supported(dev))
1868                 return rte_flow_error_set(error, ENOTSUP,
1869                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1870                                           "extended metadata register"
1871                                           " isn't supported");
1872         if (!nic_mask.id)
1873                 return rte_flow_error_set(error, ENOTSUP,
1874                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1875                                           "extended metadata register"
1876                                           " isn't available");
1877         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1878         if (ret < 0)
1879                 return ret;
1880         if (!spec)
1881                 return rte_flow_error_set(error, EINVAL,
1882                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1883                                           item->spec,
1884                                           "data cannot be empty");
1885         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1886                 return rte_flow_error_set(error, EINVAL,
1887                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1888                                           &spec->id,
1889                                           "mark id exceeds the limit");
1890         if (!mask)
1891                 mask = &nic_mask;
1892         if (!mask->id)
1893                 return rte_flow_error_set(error, EINVAL,
1894                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1895                                         "mask cannot be zero");
1896
1897         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1898                                         (const uint8_t *)&nic_mask,
1899                                         sizeof(struct rte_flow_item_mark),
1900                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1901         if (ret < 0)
1902                 return ret;
1903         return 0;
1904 }
1905
1906 /**
1907  * Validate META item.
1908  *
1909  * @param[in] dev
1910  *   Pointer to the rte_eth_dev structure.
1911  * @param[in] item
1912  *   Item specification.
1913  * @param[in] attr
1914  *   Attributes of flow that includes this item.
1915  * @param[out] error
1916  *   Pointer to error structure.
1917  *
1918  * @return
1919  *   0 on success, a negative errno value otherwise and rte_errno is set.
1920  */
1921 static int
1922 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1923                            const struct rte_flow_item *item,
1924                            const struct rte_flow_attr *attr,
1925                            struct rte_flow_error *error)
1926 {
1927         struct mlx5_priv *priv = dev->data->dev_private;
1928         struct mlx5_dev_config *config = &priv->config;
1929         const struct rte_flow_item_meta *spec = item->spec;
1930         const struct rte_flow_item_meta *mask = item->mask;
1931         struct rte_flow_item_meta nic_mask = {
1932                 .data = UINT32_MAX
1933         };
1934         int reg;
1935         int ret;
1936
1937         if (!spec)
1938                 return rte_flow_error_set(error, EINVAL,
1939                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1940                                           item->spec,
1941                                           "data cannot be empty");
1942         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1943                 if (!mlx5_flow_ext_mreg_supported(dev))
1944                         return rte_flow_error_set(error, ENOTSUP,
1945                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1946                                           "extended metadata register"
1947                                           " isn't supported");
1948                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1949                 if (reg < 0)
1950                         return reg;
1951                 if (reg == REG_NON)
1952                         return rte_flow_error_set(error, ENOTSUP,
1953                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1954                                         "unavalable extended metadata register");
1955                 if (reg == REG_B)
1956                         return rte_flow_error_set(error, ENOTSUP,
1957                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1958                                           "match on reg_b "
1959                                           "isn't supported");
1960                 if (reg != REG_A)
1961                         nic_mask.data = priv->sh->dv_meta_mask;
1962         } else {
1963                 if (attr->transfer)
1964                         return rte_flow_error_set(error, ENOTSUP,
1965                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1966                                         "extended metadata feature "
1967                                         "should be enabled when "
1968                                         "meta item is requested "
1969                                         "with e-switch mode ");
1970                 if (attr->ingress)
1971                         return rte_flow_error_set(error, ENOTSUP,
1972                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1973                                         "match on metadata for ingress "
1974                                         "is not supported in legacy "
1975                                         "metadata mode");
1976         }
1977         if (!mask)
1978                 mask = &rte_flow_item_meta_mask;
1979         if (!mask->data)
1980                 return rte_flow_error_set(error, EINVAL,
1981                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1982                                         "mask cannot be zero");
1983
1984         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1985                                         (const uint8_t *)&nic_mask,
1986                                         sizeof(struct rte_flow_item_meta),
1987                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988         return ret;
1989 }
1990
1991 /**
1992  * Validate TAG item.
1993  *
1994  * @param[in] dev
1995  *   Pointer to the rte_eth_dev structure.
1996  * @param[in] item
1997  *   Item specification.
1998  * @param[in] attr
1999  *   Attributes of flow that includes this item.
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2008                           const struct rte_flow_item *item,
2009                           const struct rte_flow_attr *attr __rte_unused,
2010                           struct rte_flow_error *error)
2011 {
2012         const struct rte_flow_item_tag *spec = item->spec;
2013         const struct rte_flow_item_tag *mask = item->mask;
2014         const struct rte_flow_item_tag nic_mask = {
2015                 .data = RTE_BE32(UINT32_MAX),
2016                 .index = 0xff,
2017         };
2018         int ret;
2019
2020         if (!mlx5_flow_ext_mreg_supported(dev))
2021                 return rte_flow_error_set(error, ENOTSUP,
2022                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2023                                           "extensive metadata register"
2024                                           " isn't supported");
2025         if (!spec)
2026                 return rte_flow_error_set(error, EINVAL,
2027                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2028                                           item->spec,
2029                                           "data cannot be empty");
2030         if (!mask)
2031                 mask = &rte_flow_item_tag_mask;
2032         if (!mask->data)
2033                 return rte_flow_error_set(error, EINVAL,
2034                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2035                                         "mask cannot be zero");
2036
2037         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2038                                         (const uint8_t *)&nic_mask,
2039                                         sizeof(struct rte_flow_item_tag),
2040                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2041         if (ret < 0)
2042                 return ret;
2043         if (mask->index != 0xff)
2044                 return rte_flow_error_set(error, EINVAL,
2045                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2046                                           "partial mask for tag index"
2047                                           " is not supported");
2048         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2049         if (ret < 0)
2050                 return ret;
2051         MLX5_ASSERT(ret != REG_NON);
2052         return 0;
2053 }
2054
2055 /**
2056  * Validate vport item.
2057  *
2058  * @param[in] dev
2059  *   Pointer to the rte_eth_dev structure.
2060  * @param[in] item
2061  *   Item specification.
2062  * @param[in] attr
2063  *   Attributes of flow that includes this item.
2064  * @param[in] item_flags
2065  *   Bit-fields that holds the items detected until now.
2066  * @param[out] error
2067  *   Pointer to error structure.
2068  *
2069  * @return
2070  *   0 on success, a negative errno value otherwise and rte_errno is set.
2071  */
2072 static int
2073 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2074                               const struct rte_flow_item *item,
2075                               const struct rte_flow_attr *attr,
2076                               uint64_t item_flags,
2077                               struct rte_flow_error *error)
2078 {
2079         const struct rte_flow_item_port_id *spec = item->spec;
2080         const struct rte_flow_item_port_id *mask = item->mask;
2081         const struct rte_flow_item_port_id switch_mask = {
2082                         .id = 0xffffffff,
2083         };
2084         struct mlx5_priv *esw_priv;
2085         struct mlx5_priv *dev_priv;
2086         int ret;
2087
2088         if (!attr->transfer)
2089                 return rte_flow_error_set(error, EINVAL,
2090                                           RTE_FLOW_ERROR_TYPE_ITEM,
2091                                           NULL,
2092                                           "match on port id is valid only"
2093                                           " when transfer flag is enabled");
2094         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2095                 return rte_flow_error_set(error, ENOTSUP,
2096                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2097                                           "multiple source ports are not"
2098                                           " supported");
2099         if (!mask)
2100                 mask = &switch_mask;
2101         if (mask->id != 0xffffffff)
2102                 return rte_flow_error_set(error, ENOTSUP,
2103                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2104                                            mask,
2105                                            "no support for partial mask on"
2106                                            " \"id\" field");
2107         ret = mlx5_flow_item_acceptable
2108                                 (item, (const uint8_t *)mask,
2109                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2110                                  sizeof(struct rte_flow_item_port_id),
2111                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2112         if (ret)
2113                 return ret;
2114         if (!spec)
2115                 return 0;
2116         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2117         if (!esw_priv)
2118                 return rte_flow_error_set(error, rte_errno,
2119                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2120                                           "failed to obtain E-Switch info for"
2121                                           " port");
2122         dev_priv = mlx5_dev_to_eswitch_info(dev);
2123         if (!dev_priv)
2124                 return rte_flow_error_set(error, rte_errno,
2125                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2126                                           NULL,
2127                                           "failed to obtain E-Switch info");
2128         if (esw_priv->domain_id != dev_priv->domain_id)
2129                 return rte_flow_error_set(error, EINVAL,
2130                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2131                                           "cannot match on a port from a"
2132                                           " different E-Switch");
2133         return 0;
2134 }
2135
2136 /**
2137  * Validate VLAN item.
2138  *
2139  * @param[in] item
2140  *   Item specification.
2141  * @param[in] item_flags
2142  *   Bit-fields that holds the items detected until now.
2143  * @param[in] dev
2144  *   Ethernet device flow is being created on.
2145  * @param[out] error
2146  *   Pointer to error structure.
2147  *
2148  * @return
2149  *   0 on success, a negative errno value otherwise and rte_errno is set.
2150  */
2151 static int
2152 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2153                            uint64_t item_flags,
2154                            struct rte_eth_dev *dev,
2155                            struct rte_flow_error *error)
2156 {
2157         const struct rte_flow_item_vlan *mask = item->mask;
2158         const struct rte_flow_item_vlan nic_mask = {
2159                 .tci = RTE_BE16(UINT16_MAX),
2160                 .inner_type = RTE_BE16(UINT16_MAX),
2161                 .has_more_vlan = 1,
2162         };
2163         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2164         int ret;
2165         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2166                                         MLX5_FLOW_LAYER_INNER_L4) :
2167                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2168                                         MLX5_FLOW_LAYER_OUTER_L4);
2169         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2170                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2171
2172         if (item_flags & vlanm)
2173                 return rte_flow_error_set(error, EINVAL,
2174                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2175                                           "multiple VLAN layers not supported");
2176         else if ((item_flags & l34m) != 0)
2177                 return rte_flow_error_set(error, EINVAL,
2178                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2179                                           "VLAN cannot follow L3/L4 layer");
2180         if (!mask)
2181                 mask = &rte_flow_item_vlan_mask;
2182         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2183                                         (const uint8_t *)&nic_mask,
2184                                         sizeof(struct rte_flow_item_vlan),
2185                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2186         if (ret)
2187                 return ret;
2188         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2189                 struct mlx5_priv *priv = dev->data->dev_private;
2190
2191                 if (priv->vmwa_context) {
2192                         /*
2193                          * Non-NULL context means we have a virtual machine
2194                          * and SR-IOV enabled, we have to create VLAN interface
2195                          * to make hypervisor to setup E-Switch vport
2196                          * context correctly. We avoid creating the multiple
2197                          * VLAN interfaces, so we cannot support VLAN tag mask.
2198                          */
2199                         return rte_flow_error_set(error, EINVAL,
2200                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2201                                                   item,
2202                                                   "VLAN tag mask is not"
2203                                                   " supported in virtual"
2204                                                   " environment");
2205                 }
2206         }
2207         return 0;
2208 }
2209
2210 /*
2211  * GTP flags are contained in 1 byte of the format:
2212  * -------------------------------------------
2213  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2214  * |-----------------------------------------|
2215  * | value | Version | PT | Res | E | S | PN |
2216  * -------------------------------------------
2217  *
2218  * Matching is supported only for GTP flags E, S, PN.
2219  */
2220 #define MLX5_GTP_FLAGS_MASK     0x07
2221
2222 /**
2223  * Validate GTP item.
2224  *
2225  * @param[in] dev
2226  *   Pointer to the rte_eth_dev structure.
2227  * @param[in] item
2228  *   Item specification.
2229  * @param[in] item_flags
2230  *   Bit-fields that holds the items detected until now.
2231  * @param[out] error
2232  *   Pointer to error structure.
2233  *
2234  * @return
2235  *   0 on success, a negative errno value otherwise and rte_errno is set.
2236  */
2237 static int
2238 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2239                           const struct rte_flow_item *item,
2240                           uint64_t item_flags,
2241                           struct rte_flow_error *error)
2242 {
2243         struct mlx5_priv *priv = dev->data->dev_private;
2244         const struct rte_flow_item_gtp *spec = item->spec;
2245         const struct rte_flow_item_gtp *mask = item->mask;
2246         const struct rte_flow_item_gtp nic_mask = {
2247                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2248                 .msg_type = 0xff,
2249                 .teid = RTE_BE32(0xffffffff),
2250         };
2251
2252         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2253                 return rte_flow_error_set(error, ENOTSUP,
2254                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2255                                           "GTP support is not enabled");
2256         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2257                 return rte_flow_error_set(error, ENOTSUP,
2258                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2259                                           "multiple tunnel layers not"
2260                                           " supported");
2261         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2264                                           "no outer UDP layer found");
2265         if (!mask)
2266                 mask = &rte_flow_item_gtp_mask;
2267         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2268                 return rte_flow_error_set(error, ENOTSUP,
2269                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2270                                           "Match is supported for GTP"
2271                                           " flags only");
2272         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2273                                          (const uint8_t *)&nic_mask,
2274                                          sizeof(struct rte_flow_item_gtp),
2275                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2276 }
2277
2278 /**
2279  * Validate GTP PSC item.
2280  *
2281  * @param[in] item
2282  *   Item specification.
2283  * @param[in] last_item
2284  *   Previous validated item in the pattern items.
2285  * @param[in] gtp_item
2286  *   Previous GTP item specification.
2287  * @param[in] attr
2288  *   Pointer to flow attributes.
2289  * @param[out] error
2290  *   Pointer to error structure.
2291  *
2292  * @return
2293  *   0 on success, a negative errno value otherwise and rte_errno is set.
2294  */
2295 static int
2296 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2297                               uint64_t last_item,
2298                               const struct rte_flow_item *gtp_item,
2299                               const struct rte_flow_attr *attr,
2300                               struct rte_flow_error *error)
2301 {
2302         const struct rte_flow_item_gtp *gtp_spec;
2303         const struct rte_flow_item_gtp *gtp_mask;
2304         const struct rte_flow_item_gtp_psc *spec;
2305         const struct rte_flow_item_gtp_psc *mask;
2306         const struct rte_flow_item_gtp_psc nic_mask = {
2307                 .pdu_type = 0xFF,
2308                 .qfi = 0xFF,
2309         };
2310
2311         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2312                 return rte_flow_error_set
2313                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2314                          "GTP PSC item must be preceded with GTP item");
2315         gtp_spec = gtp_item->spec;
2316         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2317         /* GTP spec and E flag is requested to match zero. */
2318         if (gtp_spec &&
2319                 (gtp_mask->v_pt_rsv_flags &
2320                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2321                 return rte_flow_error_set
2322                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2323                          "GTP E flag must be 1 to match GTP PSC");
2324         /* Check the flow is not created in group zero. */
2325         if (!attr->transfer && !attr->group)
2326                 return rte_flow_error_set
2327                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2328                          "GTP PSC is not supported for group 0");
2329         /* GTP spec is here and E flag is requested to match zero. */
2330         if (!item->spec)
2331                 return 0;
2332         spec = item->spec;
2333         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2334         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2335                 return rte_flow_error_set
2336                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2337                          "PDU type should be smaller than 16");
2338         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2339                                          (const uint8_t *)&nic_mask,
2340                                          sizeof(struct rte_flow_item_gtp_psc),
2341                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2342 }
2343
2344 /**
2345  * Validate IPV4 item.
2346  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2347  * add specific validation of fragment_offset field,
2348  *
2349  * @param[in] item
2350  *   Item specification.
2351  * @param[in] item_flags
2352  *   Bit-fields that holds the items detected until now.
2353  * @param[out] error
2354  *   Pointer to error structure.
2355  *
2356  * @return
2357  *   0 on success, a negative errno value otherwise and rte_errno is set.
2358  */
2359 static int
2360 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2361                            uint64_t item_flags,
2362                            uint64_t last_item,
2363                            uint16_t ether_type,
2364                            struct rte_flow_error *error)
2365 {
2366         int ret;
2367         const struct rte_flow_item_ipv4 *spec = item->spec;
2368         const struct rte_flow_item_ipv4 *last = item->last;
2369         const struct rte_flow_item_ipv4 *mask = item->mask;
2370         rte_be16_t fragment_offset_spec = 0;
2371         rte_be16_t fragment_offset_last = 0;
2372         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2373                 .hdr = {
2374                         .src_addr = RTE_BE32(0xffffffff),
2375                         .dst_addr = RTE_BE32(0xffffffff),
2376                         .type_of_service = 0xff,
2377                         .fragment_offset = RTE_BE16(0xffff),
2378                         .next_proto_id = 0xff,
2379                         .time_to_live = 0xff,
2380                 },
2381         };
2382
2383         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2384                                            ether_type, &nic_ipv4_mask,
2385                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2386         if (ret < 0)
2387                 return ret;
2388         if (spec && mask)
2389                 fragment_offset_spec = spec->hdr.fragment_offset &
2390                                        mask->hdr.fragment_offset;
2391         if (!fragment_offset_spec)
2392                 return 0;
2393         /*
2394          * spec and mask are valid, enforce using full mask to make sure the
2395          * complete value is used correctly.
2396          */
2397         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2398                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2399                 return rte_flow_error_set(error, EINVAL,
2400                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2401                                           item, "must use full mask for"
2402                                           " fragment_offset");
2403         /*
2404          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2405          * indicating this is 1st fragment of fragmented packet.
2406          * This is not yet supported in MLX5, return appropriate error message.
2407          */
2408         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2409                 return rte_flow_error_set(error, ENOTSUP,
2410                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2411                                           "match on first fragment not "
2412                                           "supported");
2413         if (fragment_offset_spec && !last)
2414                 return rte_flow_error_set(error, ENOTSUP,
2415                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2416                                           "specified value not supported");
2417         /* spec and last are valid, validate the specified range. */
2418         fragment_offset_last = last->hdr.fragment_offset &
2419                                mask->hdr.fragment_offset;
2420         /*
2421          * Match on fragment_offset spec 0x2001 and last 0x3fff
2422          * means MF is 1 and frag-offset is > 0.
2423          * This packet is fragment 2nd and onward, excluding last.
2424          * This is not yet supported in MLX5, return appropriate
2425          * error message.
2426          */
2427         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2428             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2429                 return rte_flow_error_set(error, ENOTSUP,
2430                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2431                                           last, "match on following "
2432                                           "fragments not supported");
2433         /*
2434          * Match on fragment_offset spec 0x0001 and last 0x1fff
2435          * means MF is 0 and frag-offset is > 0.
2436          * This packet is last fragment of fragmented packet.
2437          * This is not yet supported in MLX5, return appropriate
2438          * error message.
2439          */
2440         if (fragment_offset_spec == RTE_BE16(1) &&
2441             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2442                 return rte_flow_error_set(error, ENOTSUP,
2443                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2444                                           last, "match on last "
2445                                           "fragment not supported");
2446         /*
2447          * Match on fragment_offset spec 0x0001 and last 0x3fff
2448          * means MF and/or frag-offset is not 0.
2449          * This is a fragmented packet.
2450          * Other range values are invalid and rejected.
2451          */
2452         if (!(fragment_offset_spec == RTE_BE16(1) &&
2453               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2454                 return rte_flow_error_set(error, ENOTSUP,
2455                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2456                                           "specified range not supported");
2457         return 0;
2458 }
2459
2460 /**
2461  * Validate IPV6 fragment extension item.
2462  *
2463  * @param[in] item
2464  *   Item specification.
2465  * @param[in] item_flags
2466  *   Bit-fields that holds the items detected until now.
2467  * @param[out] error
2468  *   Pointer to error structure.
2469  *
2470  * @return
2471  *   0 on success, a negative errno value otherwise and rte_errno is set.
2472  */
2473 static int
2474 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2475                                     uint64_t item_flags,
2476                                     struct rte_flow_error *error)
2477 {
2478         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2479         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2480         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2481         rte_be16_t frag_data_spec = 0;
2482         rte_be16_t frag_data_last = 0;
2483         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2484         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2485                                       MLX5_FLOW_LAYER_OUTER_L4;
2486         int ret = 0;
2487         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2488                 .hdr = {
2489                         .next_header = 0xff,
2490                         .frag_data = RTE_BE16(0xffff),
2491                 },
2492         };
2493
2494         if (item_flags & l4m)
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "ipv6 fragment extension item cannot "
2498                                           "follow L4 item.");
2499         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2500             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2501                 return rte_flow_error_set(error, EINVAL,
2502                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2503                                           "ipv6 fragment extension item must "
2504                                           "follow ipv6 item");
2505         if (spec && mask)
2506                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2507         if (!frag_data_spec)
2508                 return 0;
2509         /*
2510          * spec and mask are valid, enforce using full mask to make sure the
2511          * complete value is used correctly.
2512          */
2513         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2514                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2515                 return rte_flow_error_set(error, EINVAL,
2516                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2517                                           item, "must use full mask for"
2518                                           " frag_data");
2519         /*
2520          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2521          * This is 1st fragment of fragmented packet.
2522          */
2523         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2524                 return rte_flow_error_set(error, ENOTSUP,
2525                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2526                                           "match on first fragment not "
2527                                           "supported");
2528         if (frag_data_spec && !last)
2529                 return rte_flow_error_set(error, EINVAL,
2530                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2531                                           "specified value not supported");
2532         ret = mlx5_flow_item_acceptable
2533                                 (item, (const uint8_t *)mask,
2534                                  (const uint8_t *)&nic_mask,
2535                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2536                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2537         if (ret)
2538                 return ret;
2539         /* spec and last are valid, validate the specified range. */
2540         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2541         /*
2542          * Match on frag_data spec 0x0009 and last 0xfff9
2543          * means M is 1 and frag-offset is > 0.
2544          * This packet is fragment 2nd and onward, excluding last.
2545          * This is not yet supported in MLX5, return appropriate
2546          * error message.
2547          */
2548         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2549                                        RTE_IPV6_EHDR_MF_MASK) &&
2550             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2551                 return rte_flow_error_set(error, ENOTSUP,
2552                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2553                                           last, "match on following "
2554                                           "fragments not supported");
2555         /*
2556          * Match on frag_data spec 0x0008 and last 0xfff8
2557          * means M is 0 and frag-offset is > 0.
2558          * This packet is last fragment of fragmented packet.
2559          * This is not yet supported in MLX5, return appropriate
2560          * error message.
2561          */
2562         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2563             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2564                 return rte_flow_error_set(error, ENOTSUP,
2565                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2566                                           last, "match on last "
2567                                           "fragment not supported");
2568         /* Other range values are invalid and rejected. */
2569         return rte_flow_error_set(error, EINVAL,
2570                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2571                                   "specified range not supported");
2572 }
2573
2574 /**
2575  * Validate the pop VLAN action.
2576  *
2577  * @param[in] dev
2578  *   Pointer to the rte_eth_dev structure.
2579  * @param[in] action_flags
2580  *   Holds the actions detected until now.
2581  * @param[in] action
2582  *   Pointer to the pop vlan action.
2583  * @param[in] item_flags
2584  *   The items found in this flow rule.
2585  * @param[in] attr
2586  *   Pointer to flow attributes.
2587  * @param[out] error
2588  *   Pointer to error structure.
2589  *
2590  * @return
2591  *   0 on success, a negative errno value otherwise and rte_errno is set.
2592  */
2593 static int
2594 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2595                                  uint64_t action_flags,
2596                                  const struct rte_flow_action *action,
2597                                  uint64_t item_flags,
2598                                  const struct rte_flow_attr *attr,
2599                                  struct rte_flow_error *error)
2600 {
2601         const struct mlx5_priv *priv = dev->data->dev_private;
2602
2603         (void)action;
2604         (void)attr;
2605         if (!priv->sh->pop_vlan_action)
2606                 return rte_flow_error_set(error, ENOTSUP,
2607                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2608                                           NULL,
2609                                           "pop vlan action is not supported");
2610         if (attr->egress)
2611                 return rte_flow_error_set(error, ENOTSUP,
2612                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2613                                           NULL,
2614                                           "pop vlan action not supported for "
2615                                           "egress");
2616         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2617                 return rte_flow_error_set(error, ENOTSUP,
2618                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2619                                           "no support for multiple VLAN "
2620                                           "actions");
2621         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2622         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2623             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2624                 return rte_flow_error_set(error, ENOTSUP,
2625                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2626                                           NULL,
2627                                           "cannot pop vlan after decap without "
2628                                           "match on inner vlan in the flow");
2629         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2630         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2631             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2632                 return rte_flow_error_set(error, ENOTSUP,
2633                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2634                                           NULL,
2635                                           "cannot pop vlan without a "
2636                                           "match on (outer) vlan in the flow");
2637         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2638                 return rte_flow_error_set(error, EINVAL,
2639                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2640                                           "wrong action order, port_id should "
2641                                           "be after pop VLAN action");
2642         if (!attr->transfer && priv->representor)
2643                 return rte_flow_error_set(error, ENOTSUP,
2644                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2645                                           "pop vlan action for VF representor "
2646                                           "not supported on NIC table");
2647         return 0;
2648 }
2649
2650 /**
2651  * Get VLAN default info from vlan match info.
2652  *
2653  * @param[in] items
2654  *   the list of item specifications.
2655  * @param[out] vlan
2656  *   pointer VLAN info to fill to.
2657  *
2658  * @return
2659  *   0 on success, a negative errno value otherwise and rte_errno is set.
2660  */
2661 static void
2662 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2663                                   struct rte_vlan_hdr *vlan)
2664 {
2665         const struct rte_flow_item_vlan nic_mask = {
2666                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2667                                 MLX5DV_FLOW_VLAN_VID_MASK),
2668                 .inner_type = RTE_BE16(0xffff),
2669         };
2670
2671         if (items == NULL)
2672                 return;
2673         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2674                 int type = items->type;
2675
2676                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2677                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2678                         break;
2679         }
2680         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2681                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2682                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2683
2684                 /* If VLAN item in pattern doesn't contain data, return here. */
2685                 if (!vlan_v)
2686                         return;
2687                 if (!vlan_m)
2688                         vlan_m = &nic_mask;
2689                 /* Only full match values are accepted */
2690                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2691                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2692                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2693                         vlan->vlan_tci |=
2694                                 rte_be_to_cpu_16(vlan_v->tci &
2695                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2696                 }
2697                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2698                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2699                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2700                         vlan->vlan_tci |=
2701                                 rte_be_to_cpu_16(vlan_v->tci &
2702                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2703                 }
2704                 if (vlan_m->inner_type == nic_mask.inner_type)
2705                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2706                                                            vlan_m->inner_type);
2707         }
2708 }
2709
2710 /**
2711  * Validate the push VLAN action.
2712  *
2713  * @param[in] dev
2714  *   Pointer to the rte_eth_dev structure.
2715  * @param[in] action_flags
2716  *   Holds the actions detected until now.
2717  * @param[in] item_flags
2718  *   The items found in this flow rule.
2719  * @param[in] action
2720  *   Pointer to the action structure.
2721  * @param[in] attr
2722  *   Pointer to flow attributes
2723  * @param[out] error
2724  *   Pointer to error structure.
2725  *
2726  * @return
2727  *   0 on success, a negative errno value otherwise and rte_errno is set.
2728  */
2729 static int
2730 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2731                                   uint64_t action_flags,
2732                                   const struct rte_flow_item_vlan *vlan_m,
2733                                   const struct rte_flow_action *action,
2734                                   const struct rte_flow_attr *attr,
2735                                   struct rte_flow_error *error)
2736 {
2737         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2738         const struct mlx5_priv *priv = dev->data->dev_private;
2739
2740         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2741             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2742                 return rte_flow_error_set(error, EINVAL,
2743                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2744                                           "invalid vlan ethertype");
2745         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2746                 return rte_flow_error_set(error, EINVAL,
2747                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2748                                           "wrong action order, port_id should "
2749                                           "be after push VLAN");
2750         if (!attr->transfer && priv->representor)
2751                 return rte_flow_error_set(error, ENOTSUP,
2752                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2753                                           "push vlan action for VF representor "
2754                                           "not supported on NIC table");
2755         if (vlan_m &&
2756             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2757             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2758                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2759             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2760             !(mlx5_flow_find_action
2761                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2762                 return rte_flow_error_set(error, EINVAL,
2763                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2764                                           "not full match mask on VLAN PCP and "
2765                                           "there is no of_set_vlan_pcp action, "
2766                                           "push VLAN action cannot figure out "
2767                                           "PCP value");
2768         if (vlan_m &&
2769             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2770             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2771                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2772             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2773             !(mlx5_flow_find_action
2774                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2775                 return rte_flow_error_set(error, EINVAL,
2776                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2777                                           "not full match mask on VLAN VID and "
2778                                           "there is no of_set_vlan_vid action, "
2779                                           "push VLAN action cannot figure out "
2780                                           "VID value");
2781         (void)attr;
2782         return 0;
2783 }
2784
2785 /**
2786  * Validate the set VLAN PCP.
2787  *
2788  * @param[in] action_flags
2789  *   Holds the actions detected until now.
2790  * @param[in] actions
2791  *   Pointer to the list of actions remaining in the flow rule.
2792  * @param[out] error
2793  *   Pointer to error structure.
2794  *
2795  * @return
2796  *   0 on success, a negative errno value otherwise and rte_errno is set.
2797  */
2798 static int
2799 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2800                                      const struct rte_flow_action actions[],
2801                                      struct rte_flow_error *error)
2802 {
2803         const struct rte_flow_action *action = actions;
2804         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2805
2806         if (conf->vlan_pcp > 7)
2807                 return rte_flow_error_set(error, EINVAL,
2808                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2809                                           "VLAN PCP value is too big");
2810         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2811                 return rte_flow_error_set(error, ENOTSUP,
2812                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2813                                           "set VLAN PCP action must follow "
2814                                           "the push VLAN action");
2815         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2816                 return rte_flow_error_set(error, ENOTSUP,
2817                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2818                                           "Multiple VLAN PCP modification are "
2819                                           "not supported");
2820         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2821                 return rte_flow_error_set(error, EINVAL,
2822                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2823                                           "wrong action order, port_id should "
2824                                           "be after set VLAN PCP");
2825         return 0;
2826 }
2827
2828 /**
2829  * Validate the set VLAN VID.
2830  *
2831  * @param[in] item_flags
2832  *   Holds the items detected in this rule.
2833  * @param[in] action_flags
2834  *   Holds the actions detected until now.
2835  * @param[in] actions
2836  *   Pointer to the list of actions remaining in the flow rule.
2837  * @param[out] error
2838  *   Pointer to error structure.
2839  *
2840  * @return
2841  *   0 on success, a negative errno value otherwise and rte_errno is set.
2842  */
2843 static int
2844 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2845                                      uint64_t action_flags,
2846                                      const struct rte_flow_action actions[],
2847                                      struct rte_flow_error *error)
2848 {
2849         const struct rte_flow_action *action = actions;
2850         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2851
2852         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2853                 return rte_flow_error_set(error, EINVAL,
2854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2855                                           "VLAN VID value is too big");
2856         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2857             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2858                 return rte_flow_error_set(error, ENOTSUP,
2859                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2860                                           "set VLAN VID action must follow push"
2861                                           " VLAN action or match on VLAN item");
2862         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2863                 return rte_flow_error_set(error, ENOTSUP,
2864                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2865                                           "Multiple VLAN VID modifications are "
2866                                           "not supported");
2867         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2868                 return rte_flow_error_set(error, EINVAL,
2869                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2870                                           "wrong action order, port_id should "
2871                                           "be after set VLAN VID");
2872         return 0;
2873 }
2874
2875 /*
2876  * Validate the FLAG action.
2877  *
2878  * @param[in] dev
2879  *   Pointer to the rte_eth_dev structure.
2880  * @param[in] action_flags
2881  *   Holds the actions detected until now.
2882  * @param[in] attr
2883  *   Pointer to flow attributes
2884  * @param[out] error
2885  *   Pointer to error structure.
2886  *
2887  * @return
2888  *   0 on success, a negative errno value otherwise and rte_errno is set.
2889  */
2890 static int
2891 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2892                              uint64_t action_flags,
2893                              const struct rte_flow_attr *attr,
2894                              struct rte_flow_error *error)
2895 {
2896         struct mlx5_priv *priv = dev->data->dev_private;
2897         struct mlx5_dev_config *config = &priv->config;
2898         int ret;
2899
2900         /* Fall back if no extended metadata register support. */
2901         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2902                 return mlx5_flow_validate_action_flag(action_flags, attr,
2903                                                       error);
2904         /* Extensive metadata mode requires registers. */
2905         if (!mlx5_flow_ext_mreg_supported(dev))
2906                 return rte_flow_error_set(error, ENOTSUP,
2907                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2908                                           "no metadata registers "
2909                                           "to support flag action");
2910         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2911                 return rte_flow_error_set(error, ENOTSUP,
2912                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2913                                           "extended metadata register"
2914                                           " isn't available");
2915         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2916         if (ret < 0)
2917                 return ret;
2918         MLX5_ASSERT(ret > 0);
2919         if (action_flags & MLX5_FLOW_ACTION_MARK)
2920                 return rte_flow_error_set(error, EINVAL,
2921                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2922                                           "can't mark and flag in same flow");
2923         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2924                 return rte_flow_error_set(error, EINVAL,
2925                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2926                                           "can't have 2 flag"
2927                                           " actions in same flow");
2928         return 0;
2929 }
2930
2931 /**
2932  * Validate MARK action.
2933  *
2934  * @param[in] dev
2935  *   Pointer to the rte_eth_dev structure.
2936  * @param[in] action
2937  *   Pointer to action.
2938  * @param[in] action_flags
2939  *   Holds the actions detected until now.
2940  * @param[in] attr
2941  *   Pointer to flow attributes
2942  * @param[out] error
2943  *   Pointer to error structure.
2944  *
2945  * @return
2946  *   0 on success, a negative errno value otherwise and rte_errno is set.
2947  */
2948 static int
2949 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2950                              const struct rte_flow_action *action,
2951                              uint64_t action_flags,
2952                              const struct rte_flow_attr *attr,
2953                              struct rte_flow_error *error)
2954 {
2955         struct mlx5_priv *priv = dev->data->dev_private;
2956         struct mlx5_dev_config *config = &priv->config;
2957         const struct rte_flow_action_mark *mark = action->conf;
2958         int ret;
2959
2960         if (is_tunnel_offload_active(dev))
2961                 return rte_flow_error_set(error, ENOTSUP,
2962                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2963                                           "no mark action "
2964                                           "if tunnel offload active");
2965         /* Fall back if no extended metadata register support. */
2966         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2967                 return mlx5_flow_validate_action_mark(action, action_flags,
2968                                                       attr, error);
2969         /* Extensive metadata mode requires registers. */
2970         if (!mlx5_flow_ext_mreg_supported(dev))
2971                 return rte_flow_error_set(error, ENOTSUP,
2972                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2973                                           "no metadata registers "
2974                                           "to support mark action");
2975         if (!priv->sh->dv_mark_mask)
2976                 return rte_flow_error_set(error, ENOTSUP,
2977                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2978                                           "extended metadata register"
2979                                           " isn't available");
2980         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2981         if (ret < 0)
2982                 return ret;
2983         MLX5_ASSERT(ret > 0);
2984         if (!mark)
2985                 return rte_flow_error_set(error, EINVAL,
2986                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2987                                           "configuration cannot be null");
2988         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2989                 return rte_flow_error_set(error, EINVAL,
2990                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2991                                           &mark->id,
2992                                           "mark id exceeds the limit");
2993         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2994                 return rte_flow_error_set(error, EINVAL,
2995                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2996                                           "can't flag and mark in same flow");
2997         if (action_flags & MLX5_FLOW_ACTION_MARK)
2998                 return rte_flow_error_set(error, EINVAL,
2999                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3000                                           "can't have 2 mark actions in same"
3001                                           " flow");
3002         return 0;
3003 }
3004
3005 /**
3006  * Validate SET_META action.
3007  *
3008  * @param[in] dev
3009  *   Pointer to the rte_eth_dev structure.
3010  * @param[in] action
3011  *   Pointer to the action structure.
3012  * @param[in] action_flags
3013  *   Holds the actions detected until now.
3014  * @param[in] attr
3015  *   Pointer to flow attributes
3016  * @param[out] error
3017  *   Pointer to error structure.
3018  *
3019  * @return
3020  *   0 on success, a negative errno value otherwise and rte_errno is set.
3021  */
3022 static int
3023 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3024                                  const struct rte_flow_action *action,
3025                                  uint64_t action_flags __rte_unused,
3026                                  const struct rte_flow_attr *attr,
3027                                  struct rte_flow_error *error)
3028 {
3029         const struct rte_flow_action_set_meta *conf;
3030         uint32_t nic_mask = UINT32_MAX;
3031         int reg;
3032
3033         if (!mlx5_flow_ext_mreg_supported(dev))
3034                 return rte_flow_error_set(error, ENOTSUP,
3035                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3036                                           "extended metadata register"
3037                                           " isn't supported");
3038         reg = flow_dv_get_metadata_reg(dev, attr, error);
3039         if (reg < 0)
3040                 return reg;
3041         if (reg == REG_NON)
3042                 return rte_flow_error_set(error, ENOTSUP,
3043                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3044                                           "unavalable extended metadata register");
3045         if (reg != REG_A && reg != REG_B) {
3046                 struct mlx5_priv *priv = dev->data->dev_private;
3047
3048                 nic_mask = priv->sh->dv_meta_mask;
3049         }
3050         if (!(action->conf))
3051                 return rte_flow_error_set(error, EINVAL,
3052                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3053                                           "configuration cannot be null");
3054         conf = (const struct rte_flow_action_set_meta *)action->conf;
3055         if (!conf->mask)
3056                 return rte_flow_error_set(error, EINVAL,
3057                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3058                                           "zero mask doesn't have any effect");
3059         if (conf->mask & ~nic_mask)
3060                 return rte_flow_error_set(error, EINVAL,
3061                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3062                                           "meta data must be within reg C0");
3063         return 0;
3064 }
3065
3066 /**
3067  * Validate SET_TAG action.
3068  *
3069  * @param[in] dev
3070  *   Pointer to the rte_eth_dev structure.
3071  * @param[in] action
3072  *   Pointer to the action structure.
3073  * @param[in] action_flags
3074  *   Holds the actions detected until now.
3075  * @param[in] attr
3076  *   Pointer to flow attributes
3077  * @param[out] error
3078  *   Pointer to error structure.
3079  *
3080  * @return
3081  *   0 on success, a negative errno value otherwise and rte_errno is set.
3082  */
3083 static int
3084 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3085                                 const struct rte_flow_action *action,
3086                                 uint64_t action_flags,
3087                                 const struct rte_flow_attr *attr,
3088                                 struct rte_flow_error *error)
3089 {
3090         const struct rte_flow_action_set_tag *conf;
3091         const uint64_t terminal_action_flags =
3092                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3093                 MLX5_FLOW_ACTION_RSS;
3094         int ret;
3095
3096         if (!mlx5_flow_ext_mreg_supported(dev))
3097                 return rte_flow_error_set(error, ENOTSUP,
3098                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3099                                           "extensive metadata register"
3100                                           " isn't supported");
3101         if (!(action->conf))
3102                 return rte_flow_error_set(error, EINVAL,
3103                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3104                                           "configuration cannot be null");
3105         conf = (const struct rte_flow_action_set_tag *)action->conf;
3106         if (!conf->mask)
3107                 return rte_flow_error_set(error, EINVAL,
3108                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3109                                           "zero mask doesn't have any effect");
3110         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3111         if (ret < 0)
3112                 return ret;
3113         if (!attr->transfer && attr->ingress &&
3114             (action_flags & terminal_action_flags))
3115                 return rte_flow_error_set(error, EINVAL,
3116                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3117                                           "set_tag has no effect"
3118                                           " with terminal actions");
3119         return 0;
3120 }
3121
3122 /**
3123  * Validate count action.
3124  *
3125  * @param[in] dev
3126  *   Pointer to rte_eth_dev structure.
3127  * @param[in] action
3128  *   Pointer to the action structure.
3129  * @param[in] action_flags
3130  *   Holds the actions detected until now.
3131  * @param[out] error
3132  *   Pointer to error structure.
3133  *
3134  * @return
3135  *   0 on success, a negative errno value otherwise and rte_errno is set.
3136  */
3137 static int
3138 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3139                               const struct rte_flow_action *action,
3140                               uint64_t action_flags,
3141                               struct rte_flow_error *error)
3142 {
3143         struct mlx5_priv *priv = dev->data->dev_private;
3144         const struct rte_flow_action_count *count;
3145
3146         if (!priv->config.devx)
3147                 goto notsup_err;
3148         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3149                 return rte_flow_error_set(error, EINVAL,
3150                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3151                                           "duplicate count actions set");
3152         count = (const struct rte_flow_action_count *)action->conf;
3153         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3154             !priv->sh->flow_hit_aso_en)
3155                 return rte_flow_error_set(error, EINVAL,
3156                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157                                           "old age and shared count combination is not supported");
3158 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3159         return 0;
3160 #endif
3161 notsup_err:
3162         return rte_flow_error_set
3163                       (error, ENOTSUP,
3164                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3165                        NULL,
3166                        "count action not supported");
3167 }
3168
3169 /**
3170  * Validate the L2 encap action.
3171  *
3172  * @param[in] dev
3173  *   Pointer to the rte_eth_dev structure.
3174  * @param[in] action_flags
3175  *   Holds the actions detected until now.
3176  * @param[in] action
3177  *   Pointer to the action structure.
3178  * @param[in] attr
3179  *   Pointer to flow attributes.
3180  * @param[out] error
3181  *   Pointer to error structure.
3182  *
3183  * @return
3184  *   0 on success, a negative errno value otherwise and rte_errno is set.
3185  */
3186 static int
3187 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3188                                  uint64_t action_flags,
3189                                  const struct rte_flow_action *action,
3190                                  const struct rte_flow_attr *attr,
3191                                  struct rte_flow_error *error)
3192 {
3193         const struct mlx5_priv *priv = dev->data->dev_private;
3194
3195         if (!(action->conf))
3196                 return rte_flow_error_set(error, EINVAL,
3197                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3198                                           "configuration cannot be null");
3199         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3200                 return rte_flow_error_set(error, EINVAL,
3201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3202                                           "can only have a single encap action "
3203                                           "in a flow");
3204         if (!attr->transfer && priv->representor)
3205                 return rte_flow_error_set(error, ENOTSUP,
3206                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3207                                           "encap action for VF representor "
3208                                           "not supported on NIC table");
3209         return 0;
3210 }
3211
3212 /**
3213  * Validate a decap action.
3214  *
3215  * @param[in] dev
3216  *   Pointer to the rte_eth_dev structure.
3217  * @param[in] action_flags
3218  *   Holds the actions detected until now.
3219  * @param[in] action
3220  *   Pointer to the action structure.
3221  * @param[in] item_flags
3222  *   Holds the items detected.
3223  * @param[in] attr
3224  *   Pointer to flow attributes
3225  * @param[out] error
3226  *   Pointer to error structure.
3227  *
3228  * @return
3229  *   0 on success, a negative errno value otherwise and rte_errno is set.
3230  */
3231 static int
3232 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3233                               uint64_t action_flags,
3234                               const struct rte_flow_action *action,
3235                               const uint64_t item_flags,
3236                               const struct rte_flow_attr *attr,
3237                               struct rte_flow_error *error)
3238 {
3239         const struct mlx5_priv *priv = dev->data->dev_private;
3240
3241         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3242             !priv->config.decap_en)
3243                 return rte_flow_error_set(error, ENOTSUP,
3244                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3245                                           "decap is not enabled");
3246         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3247                 return rte_flow_error_set(error, ENOTSUP,
3248                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3249                                           action_flags &
3250                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3251                                           "have a single decap action" : "decap "
3252                                           "after encap is not supported");
3253         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3254                 return rte_flow_error_set(error, EINVAL,
3255                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3256                                           "can't have decap action after"
3257                                           " modify action");
3258         if (attr->egress)
3259                 return rte_flow_error_set(error, ENOTSUP,
3260                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3261                                           NULL,
3262                                           "decap action not supported for "
3263                                           "egress");
3264         if (!attr->transfer && priv->representor)
3265                 return rte_flow_error_set(error, ENOTSUP,
3266                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3267                                           "decap action for VF representor "
3268                                           "not supported on NIC table");
3269         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3270             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3271                 return rte_flow_error_set(error, ENOTSUP,
3272                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3273                                 "VXLAN item should be present for VXLAN decap");
3274         return 0;
3275 }
3276
3277 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3278
3279 /**
3280  * Validate the raw encap and decap actions.
3281  *
3282  * @param[in] dev
3283  *   Pointer to the rte_eth_dev structure.
3284  * @param[in] decap
3285  *   Pointer to the decap action.
3286  * @param[in] encap
3287  *   Pointer to the encap action.
3288  * @param[in] attr
3289  *   Pointer to flow attributes
3290  * @param[in/out] action_flags
3291  *   Holds the actions detected until now.
3292  * @param[out] actions_n
3293  *   pointer to the number of actions counter.
3294  * @param[in] action
3295  *   Pointer to the action structure.
3296  * @param[in] item_flags
3297  *   Holds the items detected.
3298  * @param[out] error
3299  *   Pointer to error structure.
3300  *
3301  * @return
3302  *   0 on success, a negative errno value otherwise and rte_errno is set.
3303  */
3304 static int
3305 flow_dv_validate_action_raw_encap_decap
3306         (struct rte_eth_dev *dev,
3307          const struct rte_flow_action_raw_decap *decap,
3308          const struct rte_flow_action_raw_encap *encap,
3309          const struct rte_flow_attr *attr, uint64_t *action_flags,
3310          int *actions_n, const struct rte_flow_action *action,
3311          uint64_t item_flags, struct rte_flow_error *error)
3312 {
3313         const struct mlx5_priv *priv = dev->data->dev_private;
3314         int ret;
3315
3316         if (encap && (!encap->size || !encap->data))
3317                 return rte_flow_error_set(error, EINVAL,
3318                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3319                                           "raw encap data cannot be empty");
3320         if (decap && encap) {
3321                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3322                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3323                         /* L3 encap. */
3324                         decap = NULL;
3325                 else if (encap->size <=
3326                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3327                            decap->size >
3328                            MLX5_ENCAPSULATION_DECISION_SIZE)
3329                         /* L3 decap. */
3330                         encap = NULL;
3331                 else if (encap->size >
3332                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3333                            decap->size >
3334                            MLX5_ENCAPSULATION_DECISION_SIZE)
3335                         /* 2 L2 actions: encap and decap. */
3336                         ;
3337                 else
3338                         return rte_flow_error_set(error,
3339                                 ENOTSUP,
3340                                 RTE_FLOW_ERROR_TYPE_ACTION,
3341                                 NULL, "unsupported too small "
3342                                 "raw decap and too small raw "
3343                                 "encap combination");
3344         }
3345         if (decap) {
3346                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3347                                                     item_flags, attr, error);
3348                 if (ret < 0)
3349                         return ret;
3350                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3351                 ++(*actions_n);
3352         }
3353         if (encap) {
3354                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3355                         return rte_flow_error_set(error, ENOTSUP,
3356                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3357                                                   NULL,
3358                                                   "small raw encap size");
3359                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3360                         return rte_flow_error_set(error, EINVAL,
3361                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3362                                                   NULL,
3363                                                   "more than one encap action");
3364                 if (!attr->transfer && priv->representor)
3365                         return rte_flow_error_set
3366                                         (error, ENOTSUP,
3367                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368                                          "encap action for VF representor "
3369                                          "not supported on NIC table");
3370                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3371                 ++(*actions_n);
3372         }
3373         return 0;
3374 }
3375
3376 /**
3377  * Match encap_decap resource.
3378  *
3379  * @param list
3380  *   Pointer to the hash list.
3381  * @param entry
3382  *   Pointer to exist resource entry object.
3383  * @param key
3384  *   Key of the new entry.
3385  * @param ctx_cb
3386  *   Pointer to new encap_decap resource.
3387  *
3388  * @return
3389  *   0 on matching, none-zero otherwise.
3390  */
3391 int
3392 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3393                              struct mlx5_hlist_entry *entry,
3394                              uint64_t key __rte_unused, void *cb_ctx)
3395 {
3396         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3397         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3398         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3399
3400         cache_resource = container_of(entry,
3401                                       struct mlx5_flow_dv_encap_decap_resource,
3402                                       entry);
3403         if (resource->reformat_type == cache_resource->reformat_type &&
3404             resource->ft_type == cache_resource->ft_type &&
3405             resource->flags == cache_resource->flags &&
3406             resource->size == cache_resource->size &&
3407             !memcmp((const void *)resource->buf,
3408                     (const void *)cache_resource->buf,
3409                     resource->size))
3410                 return 0;
3411         return -1;
3412 }
3413
3414 /**
3415  * Allocate encap_decap resource.
3416  *
3417  * @param list
3418  *   Pointer to the hash list.
3419  * @param entry
3420  *   Pointer to exist resource entry object.
3421  * @param ctx_cb
3422  *   Pointer to new encap_decap resource.
3423  *
3424  * @return
3425  *   0 on matching, none-zero otherwise.
3426  */
3427 struct mlx5_hlist_entry *
3428 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3429                               uint64_t key __rte_unused,
3430                               void *cb_ctx)
3431 {
3432         struct mlx5_dev_ctx_shared *sh = list->ctx;
3433         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3434         struct mlx5dv_dr_domain *domain;
3435         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3436         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3437         uint32_t idx;
3438         int ret;
3439
3440         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3441                 domain = sh->fdb_domain;
3442         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3443                 domain = sh->rx_domain;
3444         else
3445                 domain = sh->tx_domain;
3446         /* Register new encap/decap resource. */
3447         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3448                                        &idx);
3449         if (!cache_resource) {
3450                 rte_flow_error_set(ctx->error, ENOMEM,
3451                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3452                                    "cannot allocate resource memory");
3453                 return NULL;
3454         }
3455         *cache_resource = *resource;
3456         cache_resource->idx = idx;
3457         ret = mlx5_flow_os_create_flow_action_packet_reformat
3458                                         (sh->ctx, domain, cache_resource,
3459                                          &cache_resource->action);
3460         if (ret) {
3461                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3462                 rte_flow_error_set(ctx->error, ENOMEM,
3463                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3464                                    NULL, "cannot create action");
3465                 return NULL;
3466         }
3467
3468         return &cache_resource->entry;
3469 }
3470
3471 /**
3472  * Find existing encap/decap resource or create and register a new one.
3473  *
3474  * @param[in, out] dev
3475  *   Pointer to rte_eth_dev structure.
3476  * @param[in, out] resource
3477  *   Pointer to encap/decap resource.
3478  * @parm[in, out] dev_flow
3479  *   Pointer to the dev_flow.
3480  * @param[out] error
3481  *   pointer to error structure.
3482  *
3483  * @return
3484  *   0 on success otherwise -errno and errno is set.
3485  */
3486 static int
3487 flow_dv_encap_decap_resource_register
3488                         (struct rte_eth_dev *dev,
3489                          struct mlx5_flow_dv_encap_decap_resource *resource,
3490                          struct mlx5_flow *dev_flow,
3491                          struct rte_flow_error *error)
3492 {
3493         struct mlx5_priv *priv = dev->data->dev_private;
3494         struct mlx5_dev_ctx_shared *sh = priv->sh;
3495         struct mlx5_hlist_entry *entry;
3496         union {
3497                 struct {
3498                         uint32_t ft_type:8;
3499                         uint32_t refmt_type:8;
3500                         /*
3501                          * Header reformat actions can be shared between
3502                          * non-root tables. One bit to indicate non-root
3503                          * table or not.
3504                          */
3505                         uint32_t is_root:1;
3506                         uint32_t reserve:15;
3507                 };
3508                 uint32_t v32;
3509         } encap_decap_key = {
3510                 {
3511                         .ft_type = resource->ft_type,
3512                         .refmt_type = resource->reformat_type,
3513                         .is_root = !!dev_flow->dv.group,
3514                         .reserve = 0,
3515                 }
3516         };
3517         struct mlx5_flow_cb_ctx ctx = {
3518                 .error = error,
3519                 .data = resource,
3520         };
3521         uint64_t key64;
3522
3523         resource->flags = dev_flow->dv.group ? 0 : 1;
3524         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3525                                  sizeof(encap_decap_key.v32), 0);
3526         if (resource->reformat_type !=
3527             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3528             resource->size)
3529                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3530         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3531         if (!entry)
3532                 return -rte_errno;
3533         resource = container_of(entry, typeof(*resource), entry);
3534         dev_flow->dv.encap_decap = resource;
3535         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3536         return 0;
3537 }
3538
3539 /**
3540  * Find existing table jump resource or create and register a new one.
3541  *
3542  * @param[in, out] dev
3543  *   Pointer to rte_eth_dev structure.
3544  * @param[in, out] tbl
3545  *   Pointer to flow table resource.
3546  * @parm[in, out] dev_flow
3547  *   Pointer to the dev_flow.
3548  * @param[out] error
3549  *   pointer to error structure.
3550  *
3551  * @return
3552  *   0 on success otherwise -errno and errno is set.
3553  */
3554 static int
3555 flow_dv_jump_tbl_resource_register
3556                         (struct rte_eth_dev *dev __rte_unused,
3557                          struct mlx5_flow_tbl_resource *tbl,
3558                          struct mlx5_flow *dev_flow,
3559                          struct rte_flow_error *error __rte_unused)
3560 {
3561         struct mlx5_flow_tbl_data_entry *tbl_data =
3562                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3563
3564         MLX5_ASSERT(tbl);
3565         MLX5_ASSERT(tbl_data->jump.action);
3566         dev_flow->handle->rix_jump = tbl_data->idx;
3567         dev_flow->dv.jump = &tbl_data->jump;
3568         return 0;
3569 }
3570
3571 int
3572 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3573                          struct mlx5_cache_entry *entry, void *cb_ctx)
3574 {
3575         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3576         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3577         struct mlx5_flow_dv_port_id_action_resource *res =
3578                         container_of(entry, typeof(*res), entry);
3579
3580         return ref->port_id != res->port_id;
3581 }
3582
3583 struct mlx5_cache_entry *
3584 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3585                           struct mlx5_cache_entry *entry __rte_unused,
3586                           void *cb_ctx)
3587 {
3588         struct mlx5_dev_ctx_shared *sh = list->ctx;
3589         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3590         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3591         struct mlx5_flow_dv_port_id_action_resource *cache;
3592         uint32_t idx;
3593         int ret;
3594
3595         /* Register new port id action resource. */
3596         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3597         if (!cache) {
3598                 rte_flow_error_set(ctx->error, ENOMEM,
3599                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3600                                    "cannot allocate port_id action cache memory");
3601                 return NULL;
3602         }
3603         *cache = *ref;
3604         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3605                                                         ref->port_id,
3606                                                         &cache->action);
3607         if (ret) {
3608                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3609                 rte_flow_error_set(ctx->error, ENOMEM,
3610                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3611                                    "cannot create action");
3612                 return NULL;
3613         }
3614         cache->idx = idx;
3615         return &cache->entry;
3616 }
3617
3618 /**
3619  * Find existing table port ID resource or create and register a new one.
3620  *
3621  * @param[in, out] dev
3622  *   Pointer to rte_eth_dev structure.
3623  * @param[in, out] resource
3624  *   Pointer to port ID action resource.
3625  * @parm[in, out] dev_flow
3626  *   Pointer to the dev_flow.
3627  * @param[out] error
3628  *   pointer to error structure.
3629  *
3630  * @return
3631  *   0 on success otherwise -errno and errno is set.
3632  */
3633 static int
3634 flow_dv_port_id_action_resource_register
3635                         (struct rte_eth_dev *dev,
3636                          struct mlx5_flow_dv_port_id_action_resource *resource,
3637                          struct mlx5_flow *dev_flow,
3638                          struct rte_flow_error *error)
3639 {
3640         struct mlx5_priv *priv = dev->data->dev_private;
3641         struct mlx5_cache_entry *entry;
3642         struct mlx5_flow_dv_port_id_action_resource *cache;
3643         struct mlx5_flow_cb_ctx ctx = {
3644                 .error = error,
3645                 .data = resource,
3646         };
3647
3648         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3649         if (!entry)
3650                 return -rte_errno;
3651         cache = container_of(entry, typeof(*cache), entry);
3652         dev_flow->dv.port_id_action = cache;
3653         dev_flow->handle->rix_port_id_action = cache->idx;
3654         return 0;
3655 }
3656
3657 int
3658 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3659                          struct mlx5_cache_entry *entry, void *cb_ctx)
3660 {
3661         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3662         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3663         struct mlx5_flow_dv_push_vlan_action_resource *res =
3664                         container_of(entry, typeof(*res), entry);
3665
3666         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3667 }
3668
3669 struct mlx5_cache_entry *
3670 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3671                           struct mlx5_cache_entry *entry __rte_unused,
3672                           void *cb_ctx)
3673 {
3674         struct mlx5_dev_ctx_shared *sh = list->ctx;
3675         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3676         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3677         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3678         struct mlx5dv_dr_domain *domain;
3679         uint32_t idx;
3680         int ret;
3681
3682         /* Register new port id action resource. */
3683         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3684         if (!cache) {
3685                 rte_flow_error_set(ctx->error, ENOMEM,
3686                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3687                                    "cannot allocate push_vlan action cache memory");
3688                 return NULL;
3689         }
3690         *cache = *ref;
3691         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3692                 domain = sh->fdb_domain;
3693         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3694                 domain = sh->rx_domain;
3695         else
3696                 domain = sh->tx_domain;
3697         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3698                                                         &cache->action);
3699         if (ret) {
3700                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3701                 rte_flow_error_set(ctx->error, ENOMEM,
3702                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3703                                    "cannot create push vlan action");
3704                 return NULL;
3705         }
3706         cache->idx = idx;
3707         return &cache->entry;
3708 }
3709
3710 /**
3711  * Find existing push vlan resource or create and register a new one.
3712  *
3713  * @param [in, out] dev
3714  *   Pointer to rte_eth_dev structure.
3715  * @param[in, out] resource
3716  *   Pointer to port ID action resource.
3717  * @parm[in, out] dev_flow
3718  *   Pointer to the dev_flow.
3719  * @param[out] error
3720  *   pointer to error structure.
3721  *
3722  * @return
3723  *   0 on success otherwise -errno and errno is set.
3724  */
3725 static int
3726 flow_dv_push_vlan_action_resource_register
3727                        (struct rte_eth_dev *dev,
3728                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3729                         struct mlx5_flow *dev_flow,
3730                         struct rte_flow_error *error)
3731 {
3732         struct mlx5_priv *priv = dev->data->dev_private;
3733         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3734         struct mlx5_cache_entry *entry;
3735         struct mlx5_flow_cb_ctx ctx = {
3736                 .error = error,
3737                 .data = resource,
3738         };
3739
3740         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3741         if (!entry)
3742                 return -rte_errno;
3743         cache = container_of(entry, typeof(*cache), entry);
3744
3745         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3746         dev_flow->dv.push_vlan_res = cache;
3747         return 0;
3748 }
3749
3750 /**
3751  * Get the size of specific rte_flow_item_type hdr size
3752  *
3753  * @param[in] item_type
3754  *   Tested rte_flow_item_type.
3755  *
3756  * @return
3757  *   sizeof struct item_type, 0 if void or irrelevant.
3758  */
3759 static size_t
3760 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3761 {
3762         size_t retval;
3763
3764         switch (item_type) {
3765         case RTE_FLOW_ITEM_TYPE_ETH:
3766                 retval = sizeof(struct rte_ether_hdr);
3767                 break;
3768         case RTE_FLOW_ITEM_TYPE_VLAN:
3769                 retval = sizeof(struct rte_vlan_hdr);
3770                 break;
3771         case RTE_FLOW_ITEM_TYPE_IPV4:
3772                 retval = sizeof(struct rte_ipv4_hdr);
3773                 break;
3774         case RTE_FLOW_ITEM_TYPE_IPV6:
3775                 retval = sizeof(struct rte_ipv6_hdr);
3776                 break;
3777         case RTE_FLOW_ITEM_TYPE_UDP:
3778                 retval = sizeof(struct rte_udp_hdr);
3779                 break;
3780         case RTE_FLOW_ITEM_TYPE_TCP:
3781                 retval = sizeof(struct rte_tcp_hdr);
3782                 break;
3783         case RTE_FLOW_ITEM_TYPE_VXLAN:
3784         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3785                 retval = sizeof(struct rte_vxlan_hdr);
3786                 break;
3787         case RTE_FLOW_ITEM_TYPE_GRE:
3788         case RTE_FLOW_ITEM_TYPE_NVGRE:
3789                 retval = sizeof(struct rte_gre_hdr);
3790                 break;
3791         case RTE_FLOW_ITEM_TYPE_MPLS:
3792                 retval = sizeof(struct rte_mpls_hdr);
3793                 break;
3794         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3795         default:
3796                 retval = 0;
3797                 break;
3798         }
3799         return retval;
3800 }
3801
3802 #define MLX5_ENCAP_IPV4_VERSION         0x40
3803 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3804 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3805 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3806 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3807 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3808 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3809
3810 /**
3811  * Convert the encap action data from list of rte_flow_item to raw buffer
3812  *
3813  * @param[in] items
3814  *   Pointer to rte_flow_item objects list.
3815  * @param[out] buf
3816  *   Pointer to the output buffer.
3817  * @param[out] size
3818  *   Pointer to the output buffer size.
3819  * @param[out] error
3820  *   Pointer to the error structure.
3821  *
3822  * @return
3823  *   0 on success, a negative errno value otherwise and rte_errno is set.
3824  */
3825 static int
3826 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3827                            size_t *size, struct rte_flow_error *error)
3828 {
3829         struct rte_ether_hdr *eth = NULL;
3830         struct rte_vlan_hdr *vlan = NULL;
3831         struct rte_ipv4_hdr *ipv4 = NULL;
3832         struct rte_ipv6_hdr *ipv6 = NULL;
3833         struct rte_udp_hdr *udp = NULL;
3834         struct rte_vxlan_hdr *vxlan = NULL;
3835         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3836         struct rte_gre_hdr *gre = NULL;
3837         size_t len;
3838         size_t temp_size = 0;
3839
3840         if (!items)
3841                 return rte_flow_error_set(error, EINVAL,
3842                                           RTE_FLOW_ERROR_TYPE_ACTION,
3843                                           NULL, "invalid empty data");
3844         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3845                 len = flow_dv_get_item_hdr_len(items->type);
3846                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3847                         return rte_flow_error_set(error, EINVAL,
3848                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3849                                                   (void *)items->type,
3850                                                   "items total size is too big"
3851                                                   " for encap action");
3852                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3853                 switch (items->type) {
3854                 case RTE_FLOW_ITEM_TYPE_ETH:
3855                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3856                         break;
3857                 case RTE_FLOW_ITEM_TYPE_VLAN:
3858                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3859                         if (!eth)
3860                                 return rte_flow_error_set(error, EINVAL,
3861                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3862                                                 (void *)items->type,
3863                                                 "eth header not found");
3864                         if (!eth->ether_type)
3865                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3866                         break;
3867                 case RTE_FLOW_ITEM_TYPE_IPV4:
3868                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3869                         if (!vlan && !eth)
3870                                 return rte_flow_error_set(error, EINVAL,
3871                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3872                                                 (void *)items->type,
3873                                                 "neither eth nor vlan"
3874                                                 " header found");
3875                         if (vlan && !vlan->eth_proto)
3876                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3877                         else if (eth && !eth->ether_type)
3878                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3879                         if (!ipv4->version_ihl)
3880                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3881                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3882                         if (!ipv4->time_to_live)
3883                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3884                         break;
3885                 case RTE_FLOW_ITEM_TYPE_IPV6:
3886                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3887                         if (!vlan && !eth)
3888                                 return rte_flow_error_set(error, EINVAL,
3889                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3890                                                 (void *)items->type,
3891                                                 "neither eth nor vlan"
3892                                                 " header found");
3893                         if (vlan && !vlan->eth_proto)
3894                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3895                         else if (eth && !eth->ether_type)
3896                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3897                         if (!ipv6->vtc_flow)
3898                                 ipv6->vtc_flow =
3899                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3900                         if (!ipv6->hop_limits)
3901                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3902                         break;
3903                 case RTE_FLOW_ITEM_TYPE_UDP:
3904                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3905                         if (!ipv4 && !ipv6)
3906                                 return rte_flow_error_set(error, EINVAL,
3907                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3908                                                 (void *)items->type,
3909                                                 "ip header not found");
3910                         if (ipv4 && !ipv4->next_proto_id)
3911                                 ipv4->next_proto_id = IPPROTO_UDP;
3912                         else if (ipv6 && !ipv6->proto)
3913                                 ipv6->proto = IPPROTO_UDP;
3914                         break;
3915                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3916                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3917                         if (!udp)
3918                                 return rte_flow_error_set(error, EINVAL,
3919                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3920                                                 (void *)items->type,
3921                                                 "udp header not found");
3922                         if (!udp->dst_port)
3923                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3924                         if (!vxlan->vx_flags)
3925                                 vxlan->vx_flags =
3926                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3927                         break;
3928                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3929                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3930                         if (!udp)
3931                                 return rte_flow_error_set(error, EINVAL,
3932                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                 (void *)items->type,
3934                                                 "udp header not found");
3935                         if (!vxlan_gpe->proto)
3936                                 return rte_flow_error_set(error, EINVAL,
3937                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3938                                                 (void *)items->type,
3939                                                 "next protocol not found");
3940                         if (!udp->dst_port)
3941                                 udp->dst_port =
3942                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3943                         if (!vxlan_gpe->vx_flags)
3944                                 vxlan_gpe->vx_flags =
3945                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3946                         break;
3947                 case RTE_FLOW_ITEM_TYPE_GRE:
3948                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3949                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3950                         if (!gre->proto)
3951                                 return rte_flow_error_set(error, EINVAL,
3952                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3953                                                 (void *)items->type,
3954                                                 "next protocol not found");
3955                         if (!ipv4 && !ipv6)
3956                                 return rte_flow_error_set(error, EINVAL,
3957                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3958                                                 (void *)items->type,
3959                                                 "ip header not found");
3960                         if (ipv4 && !ipv4->next_proto_id)
3961                                 ipv4->next_proto_id = IPPROTO_GRE;
3962                         else if (ipv6 && !ipv6->proto)
3963                                 ipv6->proto = IPPROTO_GRE;
3964                         break;
3965                 case RTE_FLOW_ITEM_TYPE_VOID:
3966                         break;
3967                 default:
3968                         return rte_flow_error_set(error, EINVAL,
3969                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3970                                                   (void *)items->type,
3971                                                   "unsupported item type");
3972                         break;
3973                 }
3974                 temp_size += len;
3975         }
3976         *size = temp_size;
3977         return 0;
3978 }
3979
3980 static int
3981 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3982 {
3983         struct rte_ether_hdr *eth = NULL;
3984         struct rte_vlan_hdr *vlan = NULL;
3985         struct rte_ipv6_hdr *ipv6 = NULL;
3986         struct rte_udp_hdr *udp = NULL;
3987         char *next_hdr;
3988         uint16_t proto;
3989
3990         eth = (struct rte_ether_hdr *)data;
3991         next_hdr = (char *)(eth + 1);
3992         proto = RTE_BE16(eth->ether_type);
3993
3994         /* VLAN skipping */
3995         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3996                 vlan = (struct rte_vlan_hdr *)next_hdr;
3997                 proto = RTE_BE16(vlan->eth_proto);
3998                 next_hdr += sizeof(struct rte_vlan_hdr);
3999         }
4000
4001         /* HW calculates IPv4 csum. no need to proceed */
4002         if (proto == RTE_ETHER_TYPE_IPV4)
4003                 return 0;
4004
4005         /* non IPv4/IPv6 header. not supported */
4006         if (proto != RTE_ETHER_TYPE_IPV6) {
4007                 return rte_flow_error_set(error, ENOTSUP,
4008                                           RTE_FLOW_ERROR_TYPE_ACTION,
4009                                           NULL, "Cannot offload non IPv4/IPv6");
4010         }
4011
4012         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4013
4014         /* ignore non UDP */
4015         if (ipv6->proto != IPPROTO_UDP)
4016                 return 0;
4017
4018         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4019         udp->dgram_cksum = 0;
4020
4021         return 0;
4022 }
4023
4024 /**
4025  * Convert L2 encap action to DV specification.
4026  *
4027  * @param[in] dev
4028  *   Pointer to rte_eth_dev structure.
4029  * @param[in] action
4030  *   Pointer to action structure.
4031  * @param[in, out] dev_flow
4032  *   Pointer to the mlx5_flow.
4033  * @param[in] transfer
4034  *   Mark if the flow is E-Switch flow.
4035  * @param[out] error
4036  *   Pointer to the error structure.
4037  *
4038  * @return
4039  *   0 on success, a negative errno value otherwise and rte_errno is set.
4040  */
4041 static int
4042 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4043                                const struct rte_flow_action *action,
4044                                struct mlx5_flow *dev_flow,
4045                                uint8_t transfer,
4046                                struct rte_flow_error *error)
4047 {
4048         const struct rte_flow_item *encap_data;
4049         const struct rte_flow_action_raw_encap *raw_encap_data;
4050         struct mlx5_flow_dv_encap_decap_resource res = {
4051                 .reformat_type =
4052                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4053                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4054                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4055         };
4056
4057         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4058                 raw_encap_data =
4059                         (const struct rte_flow_action_raw_encap *)action->conf;
4060                 res.size = raw_encap_data->size;
4061                 memcpy(res.buf, raw_encap_data->data, res.size);
4062         } else {
4063                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4064                         encap_data =
4065                                 ((const struct rte_flow_action_vxlan_encap *)
4066                                                 action->conf)->definition;
4067                 else
4068                         encap_data =
4069                                 ((const struct rte_flow_action_nvgre_encap *)
4070                                                 action->conf)->definition;
4071                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4072                                                &res.size, error))
4073                         return -rte_errno;
4074         }
4075         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4076                 return -rte_errno;
4077         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4078                 return rte_flow_error_set(error, EINVAL,
4079                                           RTE_FLOW_ERROR_TYPE_ACTION,
4080                                           NULL, "can't create L2 encap action");
4081         return 0;
4082 }
4083
4084 /**
4085  * Convert L2 decap action to DV specification.
4086  *
4087  * @param[in] dev
4088  *   Pointer to rte_eth_dev structure.
4089  * @param[in, out] dev_flow
4090  *   Pointer to the mlx5_flow.
4091  * @param[in] transfer
4092  *   Mark if the flow is E-Switch flow.
4093  * @param[out] error
4094  *   Pointer to the error structure.
4095  *
4096  * @return
4097  *   0 on success, a negative errno value otherwise and rte_errno is set.
4098  */
4099 static int
4100 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4101                                struct mlx5_flow *dev_flow,
4102                                uint8_t transfer,
4103                                struct rte_flow_error *error)
4104 {
4105         struct mlx5_flow_dv_encap_decap_resource res = {
4106                 .size = 0,
4107                 .reformat_type =
4108                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4109                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4110                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4111         };
4112
4113         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4114                 return rte_flow_error_set(error, EINVAL,
4115                                           RTE_FLOW_ERROR_TYPE_ACTION,
4116                                           NULL, "can't create L2 decap action");
4117         return 0;
4118 }
4119
4120 /**
4121  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4122  *
4123  * @param[in] dev
4124  *   Pointer to rte_eth_dev structure.
4125  * @param[in] action
4126  *   Pointer to action structure.
4127  * @param[in, out] dev_flow
4128  *   Pointer to the mlx5_flow.
4129  * @param[in] attr
4130  *   Pointer to the flow attributes.
4131  * @param[out] error
4132  *   Pointer to the error structure.
4133  *
4134  * @return
4135  *   0 on success, a negative errno value otherwise and rte_errno is set.
4136  */
4137 static int
4138 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4139                                 const struct rte_flow_action *action,
4140                                 struct mlx5_flow *dev_flow,
4141                                 const struct rte_flow_attr *attr,
4142                                 struct rte_flow_error *error)
4143 {
4144         const struct rte_flow_action_raw_encap *encap_data;
4145         struct mlx5_flow_dv_encap_decap_resource res;
4146
4147         memset(&res, 0, sizeof(res));
4148         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4149         res.size = encap_data->size;
4150         memcpy(res.buf, encap_data->data, res.size);
4151         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4152                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4153                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4154         if (attr->transfer)
4155                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4156         else
4157                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4158                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4159         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4160                 return rte_flow_error_set(error, EINVAL,
4161                                           RTE_FLOW_ERROR_TYPE_ACTION,
4162                                           NULL, "can't create encap action");
4163         return 0;
4164 }
4165
4166 /**
4167  * Create action push VLAN.
4168  *
4169  * @param[in] dev
4170  *   Pointer to rte_eth_dev structure.
4171  * @param[in] attr
4172  *   Pointer to the flow attributes.
4173  * @param[in] vlan
4174  *   Pointer to the vlan to push to the Ethernet header.
4175  * @param[in, out] dev_flow
4176  *   Pointer to the mlx5_flow.
4177  * @param[out] error
4178  *   Pointer to the error structure.
4179  *
4180  * @return
4181  *   0 on success, a negative errno value otherwise and rte_errno is set.
4182  */
4183 static int
4184 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4185                                 const struct rte_flow_attr *attr,
4186                                 const struct rte_vlan_hdr *vlan,
4187                                 struct mlx5_flow *dev_flow,
4188                                 struct rte_flow_error *error)
4189 {
4190         struct mlx5_flow_dv_push_vlan_action_resource res;
4191
4192         memset(&res, 0, sizeof(res));
4193         res.vlan_tag =
4194                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4195                                  vlan->vlan_tci);
4196         if (attr->transfer)
4197                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4198         else
4199                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4200                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4201         return flow_dv_push_vlan_action_resource_register
4202                                             (dev, &res, dev_flow, error);
4203 }
4204
4205 /**
4206  * Validate the modify-header actions.
4207  *
4208  * @param[in] action_flags
4209  *   Holds the actions detected until now.
4210  * @param[in] action
4211  *   Pointer to the modify action.
4212  * @param[out] error
4213  *   Pointer to error structure.
4214  *
4215  * @return
4216  *   0 on success, a negative errno value otherwise and rte_errno is set.
4217  */
4218 static int
4219 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4220                                    const struct rte_flow_action *action,
4221                                    struct rte_flow_error *error)
4222 {
4223         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4224                 return rte_flow_error_set(error, EINVAL,
4225                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4226                                           NULL, "action configuration not set");
4227         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4228                 return rte_flow_error_set(error, EINVAL,
4229                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4230                                           "can't have encap action before"
4231                                           " modify action");
4232         return 0;
4233 }
4234
4235 /**
4236  * Validate the modify-header MAC address actions.
4237  *
4238  * @param[in] action_flags
4239  *   Holds the actions detected until now.
4240  * @param[in] action
4241  *   Pointer to the modify action.
4242  * @param[in] item_flags
4243  *   Holds the items detected.
4244  * @param[out] error
4245  *   Pointer to error structure.
4246  *
4247  * @return
4248  *   0 on success, a negative errno value otherwise and rte_errno is set.
4249  */
4250 static int
4251 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4252                                    const struct rte_flow_action *action,
4253                                    const uint64_t item_flags,
4254                                    struct rte_flow_error *error)
4255 {
4256         int ret = 0;
4257
4258         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4259         if (!ret) {
4260                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4261                         return rte_flow_error_set(error, EINVAL,
4262                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4263                                                   NULL,
4264                                                   "no L2 item in pattern");
4265         }
4266         return ret;
4267 }
4268
4269 /**
4270  * Validate the modify-header IPv4 address actions.
4271  *
4272  * @param[in] action_flags
4273  *   Holds the actions detected until now.
4274  * @param[in] action
4275  *   Pointer to the modify action.
4276  * @param[in] item_flags
4277  *   Holds the items detected.
4278  * @param[out] error
4279  *   Pointer to error structure.
4280  *
4281  * @return
4282  *   0 on success, a negative errno value otherwise and rte_errno is set.
4283  */
4284 static int
4285 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4286                                     const struct rte_flow_action *action,
4287                                     const uint64_t item_flags,
4288                                     struct rte_flow_error *error)
4289 {
4290         int ret = 0;
4291         uint64_t layer;
4292
4293         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4294         if (!ret) {
4295                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4296                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4297                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4298                 if (!(item_flags & layer))
4299                         return rte_flow_error_set(error, EINVAL,
4300                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4301                                                   NULL,
4302                                                   "no ipv4 item in pattern");
4303         }
4304         return ret;
4305 }
4306
4307 /**
4308  * Validate the modify-header IPv6 address actions.
4309  *
4310  * @param[in] action_flags
4311  *   Holds the actions detected until now.
4312  * @param[in] action
4313  *   Pointer to the modify action.
4314  * @param[in] item_flags
4315  *   Holds the items detected.
4316  * @param[out] error
4317  *   Pointer to error structure.
4318  *
4319  * @return
4320  *   0 on success, a negative errno value otherwise and rte_errno is set.
4321  */
4322 static int
4323 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4324                                     const struct rte_flow_action *action,
4325                                     const uint64_t item_flags,
4326                                     struct rte_flow_error *error)
4327 {
4328         int ret = 0;
4329         uint64_t layer;
4330
4331         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4332         if (!ret) {
4333                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4334                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4335                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4336                 if (!(item_flags & layer))
4337                         return rte_flow_error_set(error, EINVAL,
4338                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4339                                                   NULL,
4340                                                   "no ipv6 item in pattern");
4341         }
4342         return ret;
4343 }
4344
4345 /**
4346  * Validate the modify-header TP actions.
4347  *
4348  * @param[in] action_flags
4349  *   Holds the actions detected until now.
4350  * @param[in] action
4351  *   Pointer to the modify action.
4352  * @param[in] item_flags
4353  *   Holds the items detected.
4354  * @param[out] error
4355  *   Pointer to error structure.
4356  *
4357  * @return
4358  *   0 on success, a negative errno value otherwise and rte_errno is set.
4359  */
4360 static int
4361 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4362                                   const struct rte_flow_action *action,
4363                                   const uint64_t item_flags,
4364                                   struct rte_flow_error *error)
4365 {
4366         int ret = 0;
4367         uint64_t layer;
4368
4369         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4370         if (!ret) {
4371                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4372                                  MLX5_FLOW_LAYER_INNER_L4 :
4373                                  MLX5_FLOW_LAYER_OUTER_L4;
4374                 if (!(item_flags & layer))
4375                         return rte_flow_error_set(error, EINVAL,
4376                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4377                                                   NULL, "no transport layer "
4378                                                   "in pattern");
4379         }
4380         return ret;
4381 }
4382
4383 /**
4384  * Validate the modify-header actions of increment/decrement
4385  * TCP Sequence-number.
4386  *
4387  * @param[in] action_flags
4388  *   Holds the actions detected until now.
4389  * @param[in] action
4390  *   Pointer to the modify action.
4391  * @param[in] item_flags
4392  *   Holds the items detected.
4393  * @param[out] error
4394  *   Pointer to error structure.
4395  *
4396  * @return
4397  *   0 on success, a negative errno value otherwise and rte_errno is set.
4398  */
4399 static int
4400 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4401                                        const struct rte_flow_action *action,
4402                                        const uint64_t item_flags,
4403                                        struct rte_flow_error *error)
4404 {
4405         int ret = 0;
4406         uint64_t layer;
4407
4408         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4409         if (!ret) {
4410                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4411                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4412                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4413                 if (!(item_flags & layer))
4414                         return rte_flow_error_set(error, EINVAL,
4415                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4416                                                   NULL, "no TCP item in"
4417                                                   " pattern");
4418                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4419                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4420                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4421                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4422                         return rte_flow_error_set(error, EINVAL,
4423                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4424                                                   NULL,
4425                                                   "cannot decrease and increase"
4426                                                   " TCP sequence number"
4427                                                   " at the same time");
4428         }
4429         return ret;
4430 }
4431
4432 /**
4433  * Validate the modify-header actions of increment/decrement
4434  * TCP Acknowledgment number.
4435  *
4436  * @param[in] action_flags
4437  *   Holds the actions detected until now.
4438  * @param[in] action
4439  *   Pointer to the modify action.
4440  * @param[in] item_flags
4441  *   Holds the items detected.
4442  * @param[out] error
4443  *   Pointer to error structure.
4444  *
4445  * @return
4446  *   0 on success, a negative errno value otherwise and rte_errno is set.
4447  */
4448 static int
4449 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4450                                        const struct rte_flow_action *action,
4451                                        const uint64_t item_flags,
4452                                        struct rte_flow_error *error)
4453 {
4454         int ret = 0;
4455         uint64_t layer;
4456
4457         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4458         if (!ret) {
4459                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4460                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4461                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4462                 if (!(item_flags & layer))
4463                         return rte_flow_error_set(error, EINVAL,
4464                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4465                                                   NULL, "no TCP item in"
4466                                                   " pattern");
4467                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4468                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4469                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4470                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4471                         return rte_flow_error_set(error, EINVAL,
4472                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4473                                                   NULL,
4474                                                   "cannot decrease and increase"
4475                                                   " TCP acknowledgment number"
4476                                                   " at the same time");
4477         }
4478         return ret;
4479 }
4480
4481 /**
4482  * Validate the modify-header TTL actions.
4483  *
4484  * @param[in] action_flags
4485  *   Holds the actions detected until now.
4486  * @param[in] action
4487  *   Pointer to the modify action.
4488  * @param[in] item_flags
4489  *   Holds the items detected.
4490  * @param[out] error
4491  *   Pointer to error structure.
4492  *
4493  * @return
4494  *   0 on success, a negative errno value otherwise and rte_errno is set.
4495  */
4496 static int
4497 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4498                                    const struct rte_flow_action *action,
4499                                    const uint64_t item_flags,
4500                                    struct rte_flow_error *error)
4501 {
4502         int ret = 0;
4503         uint64_t layer;
4504
4505         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4506         if (!ret) {
4507                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4508                                  MLX5_FLOW_LAYER_INNER_L3 :
4509                                  MLX5_FLOW_LAYER_OUTER_L3;
4510                 if (!(item_flags & layer))
4511                         return rte_flow_error_set(error, EINVAL,
4512                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4513                                                   NULL,
4514                                                   "no IP protocol in pattern");
4515         }
4516         return ret;
4517 }
4518
4519 /**
4520  * Validate the generic modify field actions.
4521  * @param[in] dev
4522  *   Pointer to the rte_eth_dev structure.
4523  * @param[in] action_flags
4524  *   Holds the actions detected until now.
4525  * @param[in] action
4526  *   Pointer to the modify action.
4527  * @param[in] attr
4528  *   Pointer to the flow attributes.
4529  * @param[out] error
4530  *   Pointer to error structure.
4531  *
4532  * @return
4533  *   Number of header fields to modify (0 or more) on success,
4534  *   a negative errno value otherwise and rte_errno is set.
4535  */
4536 static int
4537 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4538                                    const uint64_t action_flags,
4539                                    const struct rte_flow_action *action,
4540                                    const struct rte_flow_attr *attr,
4541                                    struct rte_flow_error *error)
4542 {
4543         int ret = 0;
4544         struct mlx5_priv *priv = dev->data->dev_private;
4545         struct mlx5_dev_config *config = &priv->config;
4546         const struct rte_flow_action_modify_field *action_modify_field =
4547                 action->conf;
4548         uint32_t dst_width =
4549                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4550         uint32_t src_width =
4551                 mlx5_flow_item_field_width(action_modify_field->src.field);
4552
4553         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4554         if (ret)
4555                 return ret;
4556
4557         if (action_modify_field->width == 0)
4558                 return rte_flow_error_set(error, EINVAL,
4559                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4560                                 "no bits are requested to be modified");
4561         else if (action_modify_field->width > dst_width ||
4562                  action_modify_field->width > src_width)
4563                 return rte_flow_error_set(error, EINVAL,
4564                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4565                                 "cannot modify more bits than"
4566                                 " the width of a field");
4567         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4568             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4569                 if ((action_modify_field->dst.offset +
4570                      action_modify_field->width > dst_width) ||
4571                     (action_modify_field->dst.offset % 32))
4572                         return rte_flow_error_set(error, EINVAL,
4573                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4574                                         "destination offset is too big"
4575                                         " or not aligned to 4 bytes");
4576                 if (action_modify_field->dst.level &&
4577                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4578                         return rte_flow_error_set(error, ENOTSUP,
4579                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4580                                         "inner header fields modification"
4581                                         " is not supported");
4582         }
4583         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4584             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4585                 if (!attr->transfer && !attr->group)
4586                         return rte_flow_error_set(error, ENOTSUP,
4587                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4588                                         "modify field action is not"
4589                                         " supported for group 0");
4590                 if ((action_modify_field->src.offset +
4591                      action_modify_field->width > src_width) ||
4592                     (action_modify_field->src.offset % 32))
4593                         return rte_flow_error_set(error, EINVAL,
4594                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4595                                         "source offset is too big"
4596                                         " or not aligned to 4 bytes");
4597                 if (action_modify_field->src.level &&
4598                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4599                         return rte_flow_error_set(error, ENOTSUP,
4600                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4601                                         "inner header fields modification"
4602                                         " is not supported");
4603         }
4604         if (action_modify_field->dst.field ==
4605             action_modify_field->src.field)
4606                 return rte_flow_error_set(error, EINVAL,
4607                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4608                                 "source and destination fields"
4609                                 " cannot be the same");
4610         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4611             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4612                 return rte_flow_error_set(error, EINVAL,
4613                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4614                                 "immediate value or a pointer to it"
4615                                 " cannot be used as a destination");
4616         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4617             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4618                 return rte_flow_error_set(error, ENOTSUP,
4619                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4620                                 "modifications of an arbitrary"
4621                                 " place in a packet is not supported");
4622         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4623             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4624                 return rte_flow_error_set(error, ENOTSUP,
4625                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4626                                 "modifications of the 802.1Q Tag"
4627                                 " Identifier is not supported");
4628         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4629             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4630                 return rte_flow_error_set(error, ENOTSUP,
4631                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4632                                 "modifications of the VXLAN Network"
4633                                 " Identifier is not supported");
4634         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4635             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4636                 return rte_flow_error_set(error, ENOTSUP,
4637                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4638                                 "modifications of the GENEVE Network"
4639                                 " Identifier is not supported");
4640         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4641             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4642             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4643             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4644                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4645                     !mlx5_flow_ext_mreg_supported(dev))
4646                         return rte_flow_error_set(error, ENOTSUP,
4647                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4648                                         "cannot modify mark or metadata without"
4649                                         " extended metadata register support");
4650         }
4651         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4652                 return rte_flow_error_set(error, ENOTSUP,
4653                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4654                                 "add and sub operations"
4655                                 " are not supported");
4656         return (action_modify_field->width / 32) +
4657                !!(action_modify_field->width % 32);
4658 }
4659
4660 /**
4661  * Validate jump action.
4662  *
4663  * @param[in] action
4664  *   Pointer to the jump action.
4665  * @param[in] action_flags
4666  *   Holds the actions detected until now.
4667  * @param[in] attributes
4668  *   Pointer to flow attributes
4669  * @param[in] external
4670  *   Action belongs to flow rule created by request external to PMD.
4671  * @param[out] error
4672  *   Pointer to error structure.
4673  *
4674  * @return
4675  *   0 on success, a negative errno value otherwise and rte_errno is set.
4676  */
4677 static int
4678 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4679                              const struct mlx5_flow_tunnel *tunnel,
4680                              const struct rte_flow_action *action,
4681                              uint64_t action_flags,
4682                              const struct rte_flow_attr *attributes,
4683                              bool external, struct rte_flow_error *error)
4684 {
4685         uint32_t target_group, table;
4686         int ret = 0;
4687         struct flow_grp_info grp_info = {
4688                 .external = !!external,
4689                 .transfer = !!attributes->transfer,
4690                 .fdb_def_rule = 1,
4691                 .std_tbl_fix = 0
4692         };
4693         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4694                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4695                 return rte_flow_error_set(error, EINVAL,
4696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4697                                           "can't have 2 fate actions in"
4698                                           " same flow");
4699         if (action_flags & MLX5_FLOW_ACTION_METER)
4700                 return rte_flow_error_set(error, ENOTSUP,
4701                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4702                                           "jump with meter not support");
4703         if (!action->conf)
4704                 return rte_flow_error_set(error, EINVAL,
4705                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4706                                           NULL, "action configuration not set");
4707         target_group =
4708                 ((const struct rte_flow_action_jump *)action->conf)->group;
4709         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4710                                        &grp_info, error);
4711         if (ret)
4712                 return ret;
4713         if (attributes->group == target_group &&
4714             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4715                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4716                 return rte_flow_error_set(error, EINVAL,
4717                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4718                                           "target group must be other than"
4719                                           " the current flow group");
4720         return 0;
4721 }
4722
4723 /*
4724  * Validate the port_id action.
4725  *
4726  * @param[in] dev
4727  *   Pointer to rte_eth_dev structure.
4728  * @param[in] action_flags
4729  *   Bit-fields that holds the actions detected until now.
4730  * @param[in] action
4731  *   Port_id RTE action structure.
4732  * @param[in] attr
4733  *   Attributes of flow that includes this action.
4734  * @param[out] error
4735  *   Pointer to error structure.
4736  *
4737  * @return
4738  *   0 on success, a negative errno value otherwise and rte_errno is set.
4739  */
4740 static int
4741 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4742                                 uint64_t action_flags,
4743                                 const struct rte_flow_action *action,
4744                                 const struct rte_flow_attr *attr,
4745                                 struct rte_flow_error *error)
4746 {
4747         const struct rte_flow_action_port_id *port_id;
4748         struct mlx5_priv *act_priv;
4749         struct mlx5_priv *dev_priv;
4750         uint16_t port;
4751
4752         if (!attr->transfer)
4753                 return rte_flow_error_set(error, ENOTSUP,
4754                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4755                                           NULL,
4756                                           "port id action is valid in transfer"
4757                                           " mode only");
4758         if (!action || !action->conf)
4759                 return rte_flow_error_set(error, ENOTSUP,
4760                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4761                                           NULL,
4762                                           "port id action parameters must be"
4763                                           " specified");
4764         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4765                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4766                 return rte_flow_error_set(error, EINVAL,
4767                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4768                                           "can have only one fate actions in"
4769                                           " a flow");
4770         dev_priv = mlx5_dev_to_eswitch_info(dev);
4771         if (!dev_priv)
4772                 return rte_flow_error_set(error, rte_errno,
4773                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4774                                           NULL,
4775                                           "failed to obtain E-Switch info");
4776         port_id = action->conf;
4777         port = port_id->original ? dev->data->port_id : port_id->id;
4778         act_priv = mlx5_port_to_eswitch_info(port, false);
4779         if (!act_priv)
4780                 return rte_flow_error_set
4781                                 (error, rte_errno,
4782                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4783                                  "failed to obtain E-Switch port id for port");
4784         if (act_priv->domain_id != dev_priv->domain_id)
4785                 return rte_flow_error_set
4786                                 (error, EINVAL,
4787                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4788                                  "port does not belong to"
4789                                  " E-Switch being configured");
4790         return 0;
4791 }
4792
4793 /**
4794  * Get the maximum number of modify header actions.
4795  *
4796  * @param dev
4797  *   Pointer to rte_eth_dev structure.
4798  * @param flags
4799  *   Flags bits to check if root level.
4800  *
4801  * @return
4802  *   Max number of modify header actions device can support.
4803  */
4804 static inline unsigned int
4805 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4806                               uint64_t flags)
4807 {
4808         /*
4809          * There's no way to directly query the max capacity from FW.
4810          * The maximal value on root table should be assumed to be supported.
4811          */
4812         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4813                 return MLX5_MAX_MODIFY_NUM;
4814         else
4815                 return MLX5_ROOT_TBL_MODIFY_NUM;
4816 }
4817
4818 /**
4819  * Validate the meter action.
4820  *
4821  * @param[in] dev
4822  *   Pointer to rte_eth_dev structure.
4823  * @param[in] action_flags
4824  *   Bit-fields that holds the actions detected until now.
4825  * @param[in] action
4826  *   Pointer to the meter action.
4827  * @param[in] attr
4828  *   Attributes of flow that includes this action.
4829  * @param[out] error
4830  *   Pointer to error structure.
4831  *
4832  * @return
4833  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4834  */
4835 static int
4836 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4837                                 uint64_t action_flags,
4838                                 const struct rte_flow_action *action,
4839                                 const struct rte_flow_attr *attr,
4840                                 struct rte_flow_error *error)
4841 {
4842         struct mlx5_priv *priv = dev->data->dev_private;
4843         const struct rte_flow_action_meter *am = action->conf;
4844         struct mlx5_flow_meter_info *fm;
4845
4846         if (!am)
4847                 return rte_flow_error_set(error, EINVAL,
4848                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4849                                           "meter action conf is NULL");
4850
4851         if (action_flags & MLX5_FLOW_ACTION_METER)
4852                 return rte_flow_error_set(error, ENOTSUP,
4853                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4854                                           "meter chaining not support");
4855         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4856                 return rte_flow_error_set(error, ENOTSUP,
4857                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4858                                           "meter with jump not support");
4859         if (!priv->mtr_en)
4860                 return rte_flow_error_set(error, ENOTSUP,
4861                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4862                                           NULL,
4863                                           "meter action not supported");
4864         fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4865         if (!fm)
4866                 return rte_flow_error_set(error, EINVAL,
4867                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4868                                           "Meter not found");
4869         /* aso meter can always be shared by different domains */
4870         if (fm->ref_cnt && !priv->sh->meter_aso_en &&
4871             !(fm->transfer == attr->transfer ||
4872               (!fm->ingress && !attr->ingress && attr->egress) ||
4873               (!fm->egress && !attr->egress && attr->ingress)))
4874                 return rte_flow_error_set(error, EINVAL,
4875                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4876                                           "Flow attributes are either invalid "
4877                                           "or have a conflict with current "
4878                                           "meter attributes");
4879         return 0;
4880 }
4881
4882 /**
4883  * Validate the age action.
4884  *
4885  * @param[in] action_flags
4886  *   Holds the actions detected until now.
4887  * @param[in] action
4888  *   Pointer to the age action.
4889  * @param[in] dev
4890  *   Pointer to the Ethernet device structure.
4891  * @param[out] error
4892  *   Pointer to error structure.
4893  *
4894  * @return
4895  *   0 on success, a negative errno value otherwise and rte_errno is set.
4896  */
4897 static int
4898 flow_dv_validate_action_age(uint64_t action_flags,
4899                             const struct rte_flow_action *action,
4900                             struct rte_eth_dev *dev,
4901                             struct rte_flow_error *error)
4902 {
4903         struct mlx5_priv *priv = dev->data->dev_private;
4904         const struct rte_flow_action_age *age = action->conf;
4905
4906         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4907             !priv->sh->aso_age_mng))
4908                 return rte_flow_error_set(error, ENOTSUP,
4909                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4910                                           NULL,
4911                                           "age action not supported");
4912         if (!(action->conf))
4913                 return rte_flow_error_set(error, EINVAL,
4914                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4915                                           "configuration cannot be null");
4916         if (!(age->timeout))
4917                 return rte_flow_error_set(error, EINVAL,
4918                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4919                                           "invalid timeout value 0");
4920         if (action_flags & MLX5_FLOW_ACTION_AGE)
4921                 return rte_flow_error_set(error, EINVAL,
4922                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4923                                           "duplicate age actions set");
4924         return 0;
4925 }
4926
4927 /**
4928  * Validate the modify-header IPv4 DSCP actions.
4929  *
4930  * @param[in] action_flags
4931  *   Holds the actions detected until now.
4932  * @param[in] action
4933  *   Pointer to the modify action.
4934  * @param[in] item_flags
4935  *   Holds the items detected.
4936  * @param[out] error
4937  *   Pointer to error structure.
4938  *
4939  * @return
4940  *   0 on success, a negative errno value otherwise and rte_errno is set.
4941  */
4942 static int
4943 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4944                                          const struct rte_flow_action *action,
4945                                          const uint64_t item_flags,
4946                                          struct rte_flow_error *error)
4947 {
4948         int ret = 0;
4949
4950         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4951         if (!ret) {
4952                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4953                         return rte_flow_error_set(error, EINVAL,
4954                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4955                                                   NULL,
4956                                                   "no ipv4 item in pattern");
4957         }
4958         return ret;
4959 }
4960
4961 /**
4962  * Validate the modify-header IPv6 DSCP actions.
4963  *
4964  * @param[in] action_flags
4965  *   Holds the actions detected until now.
4966  * @param[in] action
4967  *   Pointer to the modify action.
4968  * @param[in] item_flags
4969  *   Holds the items detected.
4970  * @param[out] error
4971  *   Pointer to error structure.
4972  *
4973  * @return
4974  *   0 on success, a negative errno value otherwise and rte_errno is set.
4975  */
4976 static int
4977 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4978                                          const struct rte_flow_action *action,
4979                                          const uint64_t item_flags,
4980                                          struct rte_flow_error *error)
4981 {
4982         int ret = 0;
4983
4984         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4985         if (!ret) {
4986                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4987                         return rte_flow_error_set(error, EINVAL,
4988                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4989                                                   NULL,
4990                                                   "no ipv6 item in pattern");
4991         }
4992         return ret;
4993 }
4994
4995 /**
4996  * Match modify-header resource.
4997  *
4998  * @param list
4999  *   Pointer to the hash list.
5000  * @param entry
5001  *   Pointer to exist resource entry object.
5002  * @param key
5003  *   Key of the new entry.
5004  * @param ctx
5005  *   Pointer to new modify-header resource.
5006  *
5007  * @return
5008  *   0 on matching, non-zero otherwise.
5009  */
5010 int
5011 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5012                         struct mlx5_hlist_entry *entry,
5013                         uint64_t key __rte_unused, void *cb_ctx)
5014 {
5015         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5016         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5017         struct mlx5_flow_dv_modify_hdr_resource *resource =
5018                         container_of(entry, typeof(*resource), entry);
5019         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5020
5021         key_len += ref->actions_num * sizeof(ref->actions[0]);
5022         return ref->actions_num != resource->actions_num ||
5023                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5024 }
5025
5026 struct mlx5_hlist_entry *
5027 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5028                          void *cb_ctx)
5029 {
5030         struct mlx5_dev_ctx_shared *sh = list->ctx;
5031         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5032         struct mlx5dv_dr_domain *ns;
5033         struct mlx5_flow_dv_modify_hdr_resource *entry;
5034         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5035         int ret;
5036         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5037         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5038
5039         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5040                             SOCKET_ID_ANY);
5041         if (!entry) {
5042                 rte_flow_error_set(ctx->error, ENOMEM,
5043                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5044                                    "cannot allocate resource memory");
5045                 return NULL;
5046         }
5047         rte_memcpy(&entry->ft_type,
5048                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5049                    key_len + data_len);
5050         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5051                 ns = sh->fdb_domain;
5052         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5053                 ns = sh->tx_domain;
5054         else
5055                 ns = sh->rx_domain;
5056         ret = mlx5_flow_os_create_flow_action_modify_header
5057                                         (sh->ctx, ns, entry,
5058                                          data_len, &entry->action);
5059         if (ret) {
5060                 mlx5_free(entry);
5061                 rte_flow_error_set(ctx->error, ENOMEM,
5062                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5063                                    NULL, "cannot create modification action");
5064                 return NULL;
5065         }
5066         return &entry->entry;
5067 }
5068
5069 /**
5070  * Validate the sample action.
5071  *
5072  * @param[in, out] action_flags
5073  *   Holds the actions detected until now.
5074  * @param[in] action
5075  *   Pointer to the sample action.
5076  * @param[in] dev
5077  *   Pointer to the Ethernet device structure.
5078  * @param[in] attr
5079  *   Attributes of flow that includes this action.
5080  * @param[in] item_flags
5081  *   Holds the items detected.
5082  * @param[in] rss
5083  *   Pointer to the RSS action.
5084  * @param[out] sample_rss
5085  *   Pointer to the RSS action in sample action list.
5086  * @param[out] count
5087  *   Pointer to the COUNT action in sample action list.
5088  * @param[out] fdb_mirror_limit
5089  *   Pointer to the FDB mirror limitation flag.
5090  * @param[out] error
5091  *   Pointer to error structure.
5092  *
5093  * @return
5094  *   0 on success, a negative errno value otherwise and rte_errno is set.
5095  */
5096 static int
5097 flow_dv_validate_action_sample(uint64_t *action_flags,
5098                                const struct rte_flow_action *action,
5099                                struct rte_eth_dev *dev,
5100                                const struct rte_flow_attr *attr,
5101                                uint64_t item_flags,
5102                                const struct rte_flow_action_rss *rss,
5103                                const struct rte_flow_action_rss **sample_rss,
5104                                const struct rte_flow_action_count **count,
5105                                int *fdb_mirror_limit,
5106                                struct rte_flow_error *error)
5107 {
5108         struct mlx5_priv *priv = dev->data->dev_private;
5109         struct mlx5_dev_config *dev_conf = &priv->config;
5110         const struct rte_flow_action_sample *sample = action->conf;
5111         const struct rte_flow_action *act;
5112         uint64_t sub_action_flags = 0;
5113         uint16_t queue_index = 0xFFFF;
5114         int actions_n = 0;
5115         int ret;
5116
5117         if (!sample)
5118                 return rte_flow_error_set(error, EINVAL,
5119                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5120                                           "configuration cannot be NULL");
5121         if (sample->ratio == 0)
5122                 return rte_flow_error_set(error, EINVAL,
5123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5124                                           "ratio value starts from 1");
5125         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5126                 return rte_flow_error_set(error, ENOTSUP,
5127                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5128                                           NULL,
5129                                           "sample action not supported");
5130         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5131                 return rte_flow_error_set(error, EINVAL,
5132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5133                                           "Multiple sample actions not "
5134                                           "supported");
5135         if (*action_flags & MLX5_FLOW_ACTION_METER)
5136                 return rte_flow_error_set(error, EINVAL,
5137                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5138                                           "wrong action order, meter should "
5139                                           "be after sample action");
5140         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5141                 return rte_flow_error_set(error, EINVAL,
5142                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5143                                           "wrong action order, jump should "
5144                                           "be after sample action");
5145         act = sample->actions;
5146         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5147                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5148                         return rte_flow_error_set(error, ENOTSUP,
5149                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5150                                                   act, "too many actions");
5151                 switch (act->type) {
5152                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5153                         ret = mlx5_flow_validate_action_queue(act,
5154                                                               sub_action_flags,
5155                                                               dev,
5156                                                               attr, error);
5157                         if (ret < 0)
5158                                 return ret;
5159                         queue_index = ((const struct rte_flow_action_queue *)
5160                                                         (act->conf))->index;
5161                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5162                         ++actions_n;
5163                         break;
5164                 case RTE_FLOW_ACTION_TYPE_RSS:
5165                         *sample_rss = act->conf;
5166                         ret = mlx5_flow_validate_action_rss(act,
5167                                                             sub_action_flags,
5168                                                             dev, attr,
5169                                                             item_flags,
5170                                                             error);
5171                         if (ret < 0)
5172                                 return ret;
5173                         if (rss && *sample_rss &&
5174                             ((*sample_rss)->level != rss->level ||
5175                             (*sample_rss)->types != rss->types))
5176                                 return rte_flow_error_set(error, ENOTSUP,
5177                                         RTE_FLOW_ERROR_TYPE_ACTION,
5178                                         NULL,
5179                                         "Can't use the different RSS types "
5180                                         "or level in the same flow");
5181                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5182                                 queue_index = (*sample_rss)->queue[0];
5183                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5184                         ++actions_n;
5185                         break;
5186                 case RTE_FLOW_ACTION_TYPE_MARK:
5187                         ret = flow_dv_validate_action_mark(dev, act,
5188                                                            sub_action_flags,
5189                                                            attr, error);
5190                         if (ret < 0)
5191                                 return ret;
5192                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5193                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5194                                                 MLX5_FLOW_ACTION_MARK_EXT;
5195                         else
5196                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5197                         ++actions_n;
5198                         break;
5199                 case RTE_FLOW_ACTION_TYPE_COUNT:
5200                         ret = flow_dv_validate_action_count
5201                                 (dev, act,
5202                                  *action_flags | sub_action_flags,
5203                                  error);
5204                         if (ret < 0)
5205                                 return ret;
5206                         *count = act->conf;
5207                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5208                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5209                         ++actions_n;
5210                         break;
5211                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5212                         ret = flow_dv_validate_action_port_id(dev,
5213                                                               sub_action_flags,
5214                                                               act,
5215                                                               attr,
5216                                                               error);
5217                         if (ret)
5218                                 return ret;
5219                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5223                         ret = flow_dv_validate_action_raw_encap_decap
5224                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5225                                  &actions_n, action, item_flags, error);
5226                         if (ret < 0)
5227                                 return ret;
5228                         ++actions_n;
5229                         break;
5230                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5231                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5232                         ret = flow_dv_validate_action_l2_encap(dev,
5233                                                                sub_action_flags,
5234                                                                act, attr,
5235                                                                error);
5236                         if (ret < 0)
5237                                 return ret;
5238                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5239                         ++actions_n;
5240                         break;
5241                 default:
5242                         return rte_flow_error_set(error, ENOTSUP,
5243                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5244                                                   NULL,
5245                                                   "Doesn't support optional "
5246                                                   "action");
5247                 }
5248         }
5249         if (attr->ingress && !attr->transfer) {
5250                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5251                                           MLX5_FLOW_ACTION_RSS)))
5252                         return rte_flow_error_set(error, EINVAL,
5253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5254                                                   NULL,
5255                                                   "Ingress must has a dest "
5256                                                   "QUEUE for Sample");
5257         } else if (attr->egress && !attr->transfer) {
5258                 return rte_flow_error_set(error, ENOTSUP,
5259                                           RTE_FLOW_ERROR_TYPE_ACTION,
5260                                           NULL,
5261                                           "Sample Only support Ingress "
5262                                           "or E-Switch");
5263         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5264                 MLX5_ASSERT(attr->transfer);
5265                 if (sample->ratio > 1)
5266                         return rte_flow_error_set(error, ENOTSUP,
5267                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5268                                                   NULL,
5269                                                   "E-Switch doesn't support "
5270                                                   "any optional action "
5271                                                   "for sampling");
5272                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5273                         return rte_flow_error_set(error, ENOTSUP,
5274                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5275                                                   NULL,
5276                                                   "unsupported action QUEUE");
5277                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5278                         return rte_flow_error_set(error, ENOTSUP,
5279                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5280                                                   NULL,
5281                                                   "unsupported action QUEUE");
5282                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5283                         return rte_flow_error_set(error, EINVAL,
5284                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5285                                                   NULL,
5286                                                   "E-Switch must has a dest "
5287                                                   "port for mirroring");
5288                 if (!priv->config.hca_attr.reg_c_preserve &&
5289                      priv->representor_id != -1)
5290                         *fdb_mirror_limit = 1;
5291         }
5292         /* Continue validation for Xcap actions.*/
5293         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5294             (queue_index == 0xFFFF ||
5295              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5296                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5297                      MLX5_FLOW_XCAP_ACTIONS)
5298                         return rte_flow_error_set(error, ENOTSUP,
5299                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5300                                                   NULL, "encap and decap "
5301                                                   "combination aren't "
5302                                                   "supported");
5303                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5304                                                         MLX5_FLOW_ACTION_ENCAP))
5305                         return rte_flow_error_set(error, ENOTSUP,
5306                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5307                                                   NULL, "encap is not supported"
5308                                                   " for ingress traffic");
5309         }
5310         return 0;
5311 }
5312
5313 /**
5314  * Find existing modify-header resource or create and register a new one.
5315  *
5316  * @param dev[in, out]
5317  *   Pointer to rte_eth_dev structure.
5318  * @param[in, out] resource
5319  *   Pointer to modify-header resource.
5320  * @parm[in, out] dev_flow
5321  *   Pointer to the dev_flow.
5322  * @param[out] error
5323  *   pointer to error structure.
5324  *
5325  * @return
5326  *   0 on success otherwise -errno and errno is set.
5327  */
5328 static int
5329 flow_dv_modify_hdr_resource_register
5330                         (struct rte_eth_dev *dev,
5331                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5332                          struct mlx5_flow *dev_flow,
5333                          struct rte_flow_error *error)
5334 {
5335         struct mlx5_priv *priv = dev->data->dev_private;
5336         struct mlx5_dev_ctx_shared *sh = priv->sh;
5337         uint32_t key_len = sizeof(*resource) -
5338                            offsetof(typeof(*resource), ft_type) +
5339                            resource->actions_num * sizeof(resource->actions[0]);
5340         struct mlx5_hlist_entry *entry;
5341         struct mlx5_flow_cb_ctx ctx = {
5342                 .error = error,
5343                 .data = resource,
5344         };
5345         uint64_t key64;
5346
5347         resource->flags = dev_flow->dv.group ? 0 :
5348                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5349         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5350                                     resource->flags))
5351                 return rte_flow_error_set(error, EOVERFLOW,
5352                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5353                                           "too many modify header items");
5354         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5355         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5356         if (!entry)
5357                 return -rte_errno;
5358         resource = container_of(entry, typeof(*resource), entry);
5359         dev_flow->handle->dvh.modify_hdr = resource;
5360         return 0;
5361 }
5362
5363 /**
5364  * Get DV flow counter by index.
5365  *
5366  * @param[in] dev
5367  *   Pointer to the Ethernet device structure.
5368  * @param[in] idx
5369  *   mlx5 flow counter index in the container.
5370  * @param[out] ppool
5371  *   mlx5 flow counter pool in the container,
5372  *
5373  * @return
5374  *   Pointer to the counter, NULL otherwise.
5375  */
5376 static struct mlx5_flow_counter *
5377 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5378                            uint32_t idx,
5379                            struct mlx5_flow_counter_pool **ppool)
5380 {
5381         struct mlx5_priv *priv = dev->data->dev_private;
5382         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5383         struct mlx5_flow_counter_pool *pool;
5384
5385         /* Decrease to original index and clear shared bit. */
5386         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5387         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5388         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5389         MLX5_ASSERT(pool);
5390         if (ppool)
5391                 *ppool = pool;
5392         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5393 }
5394
5395 /**
5396  * Check the devx counter belongs to the pool.
5397  *
5398  * @param[in] pool
5399  *   Pointer to the counter pool.
5400  * @param[in] id
5401  *   The counter devx ID.
5402  *
5403  * @return
5404  *   True if counter belongs to the pool, false otherwise.
5405  */
5406 static bool
5407 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5408 {
5409         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5410                    MLX5_COUNTERS_PER_POOL;
5411
5412         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5413                 return true;
5414         return false;
5415 }
5416
5417 /**
5418  * Get a pool by devx counter ID.
5419  *
5420  * @param[in] cmng
5421  *   Pointer to the counter management.
5422  * @param[in] id
5423  *   The counter devx ID.
5424  *
5425  * @return
5426  *   The counter pool pointer if exists, NULL otherwise,
5427  */
5428 static struct mlx5_flow_counter_pool *
5429 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5430 {
5431         uint32_t i;
5432         struct mlx5_flow_counter_pool *pool = NULL;
5433
5434         rte_spinlock_lock(&cmng->pool_update_sl);
5435         /* Check last used pool. */
5436         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5437             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5438                 pool = cmng->pools[cmng->last_pool_idx];
5439                 goto out;
5440         }
5441         /* ID out of range means no suitable pool in the container. */
5442         if (id > cmng->max_id || id < cmng->min_id)
5443                 goto out;
5444         /*
5445          * Find the pool from the end of the container, since mostly counter
5446          * ID is sequence increasing, and the last pool should be the needed
5447          * one.
5448          */
5449         i = cmng->n_valid;
5450         while (i--) {
5451                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5452
5453                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5454                         pool = pool_tmp;
5455                         break;
5456                 }
5457         }
5458 out:
5459         rte_spinlock_unlock(&cmng->pool_update_sl);
5460         return pool;
5461 }
5462
5463 /**
5464  * Resize a counter container.
5465  *
5466  * @param[in] dev
5467  *   Pointer to the Ethernet device structure.
5468  *
5469  * @return
5470  *   0 on success, otherwise negative errno value and rte_errno is set.
5471  */
5472 static int
5473 flow_dv_container_resize(struct rte_eth_dev *dev)
5474 {
5475         struct mlx5_priv *priv = dev->data->dev_private;
5476         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5477         void *old_pools = cmng->pools;
5478         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5479         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5480         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5481
5482         if (!pools) {
5483                 rte_errno = ENOMEM;
5484                 return -ENOMEM;
5485         }
5486         if (old_pools)
5487                 memcpy(pools, old_pools, cmng->n *
5488                                        sizeof(struct mlx5_flow_counter_pool *));
5489         cmng->n = resize;
5490         cmng->pools = pools;
5491         if (old_pools)
5492                 mlx5_free(old_pools);
5493         return 0;
5494 }
5495
5496 /**
5497  * Query a devx flow counter.
5498  *
5499  * @param[in] dev
5500  *   Pointer to the Ethernet device structure.
5501  * @param[in] cnt
5502  *   Index to the flow counter.
5503  * @param[out] pkts
5504  *   The statistics value of packets.
5505  * @param[out] bytes
5506  *   The statistics value of bytes.
5507  *
5508  * @return
5509  *   0 on success, otherwise a negative errno value and rte_errno is set.
5510  */
5511 static inline int
5512 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5513                      uint64_t *bytes)
5514 {
5515         struct mlx5_priv *priv = dev->data->dev_private;
5516         struct mlx5_flow_counter_pool *pool = NULL;
5517         struct mlx5_flow_counter *cnt;
5518         int offset;
5519
5520         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5521         MLX5_ASSERT(pool);
5522         if (priv->sh->cmng.counter_fallback)
5523                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5524                                         0, pkts, bytes, 0, NULL, NULL, 0);
5525         rte_spinlock_lock(&pool->sl);
5526         if (!pool->raw) {
5527                 *pkts = 0;
5528                 *bytes = 0;
5529         } else {
5530                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5531                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5532                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5533         }
5534         rte_spinlock_unlock(&pool->sl);
5535         return 0;
5536 }
5537
5538 /**
5539  * Create and initialize a new counter pool.
5540  *
5541  * @param[in] dev
5542  *   Pointer to the Ethernet device structure.
5543  * @param[out] dcs
5544  *   The devX counter handle.
5545  * @param[in] age
5546  *   Whether the pool is for counter that was allocated for aging.
5547  * @param[in/out] cont_cur
5548  *   Pointer to the container pointer, it will be update in pool resize.
5549  *
5550  * @return
5551  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5552  */
5553 static struct mlx5_flow_counter_pool *
5554 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5555                     uint32_t age)
5556 {
5557         struct mlx5_priv *priv = dev->data->dev_private;
5558         struct mlx5_flow_counter_pool *pool;
5559         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5560         bool fallback = priv->sh->cmng.counter_fallback;
5561         uint32_t size = sizeof(*pool);
5562
5563         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5564         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5565         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5566         if (!pool) {
5567                 rte_errno = ENOMEM;
5568                 return NULL;
5569         }
5570         pool->raw = NULL;
5571         pool->is_aged = !!age;
5572         pool->query_gen = 0;
5573         pool->min_dcs = dcs;
5574         rte_spinlock_init(&pool->sl);
5575         rte_spinlock_init(&pool->csl);
5576         TAILQ_INIT(&pool->counters[0]);
5577         TAILQ_INIT(&pool->counters[1]);
5578         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5579         rte_spinlock_lock(&cmng->pool_update_sl);
5580         pool->index = cmng->n_valid;
5581         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5582                 mlx5_free(pool);
5583                 rte_spinlock_unlock(&cmng->pool_update_sl);
5584                 return NULL;
5585         }
5586         cmng->pools[pool->index] = pool;
5587         cmng->n_valid++;
5588         if (unlikely(fallback)) {
5589                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5590
5591                 if (base < cmng->min_id)
5592                         cmng->min_id = base;
5593                 if (base > cmng->max_id)
5594                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5595                 cmng->last_pool_idx = pool->index;
5596         }
5597         rte_spinlock_unlock(&cmng->pool_update_sl);
5598         return pool;
5599 }
5600
5601 /**
5602  * Prepare a new counter and/or a new counter pool.
5603  *
5604  * @param[in] dev
5605  *   Pointer to the Ethernet device structure.
5606  * @param[out] cnt_free
5607  *   Where to put the pointer of a new counter.
5608  * @param[in] age
5609  *   Whether the pool is for counter that was allocated for aging.
5610  *
5611  * @return
5612  *   The counter pool pointer and @p cnt_free is set on success,
5613  *   NULL otherwise and rte_errno is set.
5614  */
5615 static struct mlx5_flow_counter_pool *
5616 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5617                              struct mlx5_flow_counter **cnt_free,
5618                              uint32_t age)
5619 {
5620         struct mlx5_priv *priv = dev->data->dev_private;
5621         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5622         struct mlx5_flow_counter_pool *pool;
5623         struct mlx5_counters tmp_tq;
5624         struct mlx5_devx_obj *dcs = NULL;
5625         struct mlx5_flow_counter *cnt;
5626         enum mlx5_counter_type cnt_type =
5627                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5628         bool fallback = priv->sh->cmng.counter_fallback;
5629         uint32_t i;
5630
5631         if (fallback) {
5632                 /* bulk_bitmap must be 0 for single counter allocation. */
5633                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5634                 if (!dcs)
5635                         return NULL;
5636                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5637                 if (!pool) {
5638                         pool = flow_dv_pool_create(dev, dcs, age);
5639                         if (!pool) {
5640                                 mlx5_devx_cmd_destroy(dcs);
5641                                 return NULL;
5642                         }
5643                 }
5644                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5645                 cnt = MLX5_POOL_GET_CNT(pool, i);
5646                 cnt->pool = pool;
5647                 cnt->dcs_when_free = dcs;
5648                 *cnt_free = cnt;
5649                 return pool;
5650         }
5651         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5652         if (!dcs) {
5653                 rte_errno = ENODATA;
5654                 return NULL;
5655         }
5656         pool = flow_dv_pool_create(dev, dcs, age);
5657         if (!pool) {
5658                 mlx5_devx_cmd_destroy(dcs);
5659                 return NULL;
5660         }
5661         TAILQ_INIT(&tmp_tq);
5662         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5663                 cnt = MLX5_POOL_GET_CNT(pool, i);
5664                 cnt->pool = pool;
5665                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5666         }
5667         rte_spinlock_lock(&cmng->csl[cnt_type]);
5668         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5669         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5670         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5671         (*cnt_free)->pool = pool;
5672         return pool;
5673 }
5674
5675 /**
5676  * Allocate a flow counter.
5677  *
5678  * @param[in] dev
5679  *   Pointer to the Ethernet device structure.
5680  * @param[in] age
5681  *   Whether the counter was allocated for aging.
5682  *
5683  * @return
5684  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5685  */
5686 static uint32_t
5687 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5688 {
5689         struct mlx5_priv *priv = dev->data->dev_private;
5690         struct mlx5_flow_counter_pool *pool = NULL;
5691         struct mlx5_flow_counter *cnt_free = NULL;
5692         bool fallback = priv->sh->cmng.counter_fallback;
5693         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5694         enum mlx5_counter_type cnt_type =
5695                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5696         uint32_t cnt_idx;
5697
5698         if (!priv->config.devx) {
5699                 rte_errno = ENOTSUP;
5700                 return 0;
5701         }
5702         /* Get free counters from container. */
5703         rte_spinlock_lock(&cmng->csl[cnt_type]);
5704         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5705         if (cnt_free)
5706                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5707         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5708         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5709                 goto err;
5710         pool = cnt_free->pool;
5711         if (fallback)
5712                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5713         /* Create a DV counter action only in the first time usage. */
5714         if (!cnt_free->action) {
5715                 uint16_t offset;
5716                 struct mlx5_devx_obj *dcs;
5717                 int ret;
5718
5719                 if (!fallback) {
5720                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5721                         dcs = pool->min_dcs;
5722                 } else {
5723                         offset = 0;
5724                         dcs = cnt_free->dcs_when_free;
5725                 }
5726                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5727                                                             &cnt_free->action);
5728                 if (ret) {
5729                         rte_errno = errno;
5730                         goto err;
5731                 }
5732         }
5733         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5734                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5735         /* Update the counter reset values. */
5736         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5737                                  &cnt_free->bytes))
5738                 goto err;
5739         if (!fallback && !priv->sh->cmng.query_thread_on)
5740                 /* Start the asynchronous batch query by the host thread. */
5741                 mlx5_set_query_alarm(priv->sh);
5742         return cnt_idx;
5743 err:
5744         if (cnt_free) {
5745                 cnt_free->pool = pool;
5746                 if (fallback)
5747                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5748                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5749                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5750                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5751         }
5752         return 0;
5753 }
5754
5755 /**
5756  * Allocate a shared flow counter.
5757  *
5758  * @param[in] ctx
5759  *   Pointer to the shared counter configuration.
5760  * @param[in] data
5761  *   Pointer to save the allocated counter index.
5762  *
5763  * @return
5764  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5765  */
5766
5767 static int32_t
5768 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5769 {
5770         struct mlx5_shared_counter_conf *conf = ctx;
5771         struct rte_eth_dev *dev = conf->dev;
5772         struct mlx5_flow_counter *cnt;
5773
5774         data->dword = flow_dv_counter_alloc(dev, 0);
5775         data->dword |= MLX5_CNT_SHARED_OFFSET;
5776         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5777         cnt->shared_info.id = conf->id;
5778         return 0;
5779 }
5780
5781 /**
5782  * Get a shared flow counter.
5783  *
5784  * @param[in] dev
5785  *   Pointer to the Ethernet device structure.
5786  * @param[in] id
5787  *   Counter identifier.
5788  *
5789  * @return
5790  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5791  */
5792 static uint32_t
5793 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5794 {
5795         struct mlx5_priv *priv = dev->data->dev_private;
5796         struct mlx5_shared_counter_conf conf = {
5797                 .dev = dev,
5798                 .id = id,
5799         };
5800         union mlx5_l3t_data data = {
5801                 .dword = 0,
5802         };
5803
5804         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5805                                flow_dv_counter_alloc_shared_cb, &conf);
5806         return data.dword;
5807 }
5808
5809 /**
5810  * Get age param from counter index.
5811  *
5812  * @param[in] dev
5813  *   Pointer to the Ethernet device structure.
5814  * @param[in] counter
5815  *   Index to the counter handler.
5816  *
5817  * @return
5818  *   The aging parameter specified for the counter index.
5819  */
5820 static struct mlx5_age_param*
5821 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5822                                 uint32_t counter)
5823 {
5824         struct mlx5_flow_counter *cnt;
5825         struct mlx5_flow_counter_pool *pool = NULL;
5826
5827         flow_dv_counter_get_by_idx(dev, counter, &pool);
5828         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5829         cnt = MLX5_POOL_GET_CNT(pool, counter);
5830         return MLX5_CNT_TO_AGE(cnt);
5831 }
5832
5833 /**
5834  * Remove a flow counter from aged counter list.
5835  *
5836  * @param[in] dev
5837  *   Pointer to the Ethernet device structure.
5838  * @param[in] counter
5839  *   Index to the counter handler.
5840  * @param[in] cnt
5841  *   Pointer to the counter handler.
5842  */
5843 static void
5844 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5845                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5846 {
5847         struct mlx5_age_info *age_info;
5848         struct mlx5_age_param *age_param;
5849         struct mlx5_priv *priv = dev->data->dev_private;
5850         uint16_t expected = AGE_CANDIDATE;
5851
5852         age_info = GET_PORT_AGE_INFO(priv);
5853         age_param = flow_dv_counter_idx_get_age(dev, counter);
5854         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5855                                          AGE_FREE, false, __ATOMIC_RELAXED,
5856                                          __ATOMIC_RELAXED)) {
5857                 /**
5858                  * We need the lock even it is age timeout,
5859                  * since counter may still in process.
5860                  */
5861                 rte_spinlock_lock(&age_info->aged_sl);
5862                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5863                 rte_spinlock_unlock(&age_info->aged_sl);
5864                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5865         }
5866 }
5867
5868 /**
5869  * Release a flow counter.
5870  *
5871  * @param[in] dev
5872  *   Pointer to the Ethernet device structure.
5873  * @param[in] counter
5874  *   Index to the counter handler.
5875  */
5876 static void
5877 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5878 {
5879         struct mlx5_priv *priv = dev->data->dev_private;
5880         struct mlx5_flow_counter_pool *pool = NULL;
5881         struct mlx5_flow_counter *cnt;
5882         enum mlx5_counter_type cnt_type;
5883
5884         if (!counter)
5885                 return;
5886         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5887         MLX5_ASSERT(pool);
5888         if (IS_SHARED_CNT(counter) &&
5889             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5890                 return;
5891         if (pool->is_aged)
5892                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5893         cnt->pool = pool;
5894         /*
5895          * Put the counter back to list to be updated in none fallback mode.
5896          * Currently, we are using two list alternately, while one is in query,
5897          * add the freed counter to the other list based on the pool query_gen
5898          * value. After query finishes, add counter the list to the global
5899          * container counter list. The list changes while query starts. In
5900          * this case, lock will not be needed as query callback and release
5901          * function both operate with the different list.
5902          *
5903          */
5904         if (!priv->sh->cmng.counter_fallback) {
5905                 rte_spinlock_lock(&pool->csl);
5906                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5907                 rte_spinlock_unlock(&pool->csl);
5908         } else {
5909                 cnt->dcs_when_free = cnt->dcs_when_active;
5910                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5911                                            MLX5_COUNTER_TYPE_ORIGIN;
5912                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5913                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5914                                   cnt, next);
5915                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5916         }
5917 }
5918
5919 /**
5920  * Resize a meter id container.
5921  *
5922  * @param[in] dev
5923  *   Pointer to the Ethernet device structure.
5924  *
5925  * @return
5926  *   0 on success, otherwise negative errno value and rte_errno is set.
5927  */
5928 static int
5929 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5930 {
5931         struct mlx5_priv *priv = dev->data->dev_private;
5932         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5933         void *old_pools = mtrmng->pools;
5934         uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5935         uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5936         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5937
5938         if (!pools) {
5939                 rte_errno = ENOMEM;
5940                 return -ENOMEM;
5941         }
5942         if (!mtrmng->n)
5943                 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
5944                         mlx5_free(pools);
5945                         return -ENOMEM;
5946                 }
5947         if (old_pools)
5948                 memcpy(pools, old_pools, mtrmng->n *
5949                                        sizeof(struct mlx5_aso_mtr_pool *));
5950         mtrmng->n = resize;
5951         mtrmng->pools = pools;
5952         if (old_pools)
5953                 mlx5_free(old_pools);
5954         return 0;
5955 }
5956
5957 /**
5958  * Prepare a new meter and/or a new meter pool.
5959  *
5960  * @param[in] dev
5961  *   Pointer to the Ethernet device structure.
5962  * @param[out] mtr_free
5963  *   Where to put the pointer of a new meter.g.
5964  *
5965  * @return
5966  *   The meter pool pointer and @mtr_free is set on success,
5967  *   NULL otherwise and rte_errno is set.
5968  */
5969 static struct mlx5_aso_mtr_pool *
5970 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5971                              struct mlx5_aso_mtr **mtr_free)
5972 {
5973         struct mlx5_priv *priv = dev->data->dev_private;
5974         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5975         struct mlx5_aso_mtr_pool *pool = NULL;
5976         struct mlx5_devx_obj *dcs = NULL;
5977         uint32_t i;
5978         uint32_t log_obj_size;
5979
5980         log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
5981         dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
5982                         priv->sh->pdn, log_obj_size);
5983         if (!dcs) {
5984                 rte_errno = ENODATA;
5985                 return NULL;
5986         }
5987         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
5988         if (!pool) {
5989                 rte_errno = ENOMEM;
5990                 claim_zero(mlx5_devx_cmd_destroy(dcs));
5991                 return NULL;
5992         }
5993         pool->devx_obj = dcs;
5994         pool->index = mtrmng->n_valid;
5995         if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
5996                 mlx5_free(pool);
5997                 claim_zero(mlx5_devx_cmd_destroy(dcs));
5998                 return NULL;
5999         }
6000         mtrmng->pools[pool->index] = pool;
6001         mtrmng->n_valid++;
6002         for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6003                 pool->mtrs[i].offset = i;
6004                 LIST_INSERT_HEAD(&mtrmng->meters,
6005                                                 &pool->mtrs[i], next);
6006         }
6007         pool->mtrs[0].offset = 0;
6008         *mtr_free = &pool->mtrs[0];
6009         return pool;
6010 }
6011
6012 /**
6013  * Release a flow meter into pool.
6014  *
6015  * @param[in] dev
6016  *   Pointer to the Ethernet device structure.
6017  * @param[in] mtr_idx
6018  *   Index to aso flow meter.
6019  */
6020 static void
6021 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6022 {
6023         struct mlx5_priv *priv = dev->data->dev_private;
6024         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6025         struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6026
6027         MLX5_ASSERT(aso_mtr);
6028         rte_spinlock_lock(&mtrmng->mtrsl);
6029         memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6030         aso_mtr->state = ASO_METER_FREE;
6031         LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6032         rte_spinlock_unlock(&mtrmng->mtrsl);
6033 }
6034
6035 /**
6036  * Allocate a aso flow meter.
6037  *
6038  * @param[in] dev
6039  *   Pointer to the Ethernet device structure.
6040  *
6041  * @return
6042  *   Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6043  */
6044 static uint32_t
6045 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6046 {
6047         struct mlx5_priv *priv = dev->data->dev_private;
6048         struct mlx5_aso_mtr *mtr_free = NULL;
6049         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6050         struct mlx5_aso_mtr_pool *pool;
6051         uint32_t mtr_idx = 0;
6052
6053         if (!priv->config.devx) {
6054                 rte_errno = ENOTSUP;
6055                 return 0;
6056         }
6057         /* Allocate the flow meter memory. */
6058         /* Get free meters from management. */
6059         rte_spinlock_lock(&mtrmng->mtrsl);
6060         mtr_free = LIST_FIRST(&mtrmng->meters);
6061         if (mtr_free)
6062                 LIST_REMOVE(mtr_free, next);
6063         if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6064                 rte_spinlock_unlock(&mtrmng->mtrsl);
6065                 return 0;
6066         }
6067         mtr_free->state = ASO_METER_WAIT;
6068         rte_spinlock_unlock(&mtrmng->mtrsl);
6069         pool = container_of(mtr_free,
6070                         struct mlx5_aso_mtr_pool,
6071                         mtrs[mtr_free->offset]);
6072         mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6073         if (!mtr_free->fm.meter_action) {
6074 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6075                 struct rte_flow_error error;
6076                 uint8_t reg_id;
6077
6078                 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6079                 mtr_free->fm.meter_action =
6080                         mlx5_glue->dv_create_flow_action_aso
6081                                                 (priv->sh->rx_domain,
6082                                                  pool->devx_obj->obj,
6083                                                  mtr_free->offset,
6084                                                  (1 << MLX5_FLOW_COLOR_GREEN),
6085                                                  reg_id - REG_C_0);
6086 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6087                 if (!mtr_free->fm.meter_action) {
6088                         flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6089                         return 0;
6090                 }
6091         }
6092         return mtr_idx;
6093 }
6094
6095 /**
6096  * Verify the @p attributes will be correctly understood by the NIC and store
6097  * them in the @p flow if everything is correct.
6098  *
6099  * @param[in] dev
6100  *   Pointer to dev struct.
6101  * @param[in] attributes
6102  *   Pointer to flow attributes
6103  * @param[in] external
6104  *   This flow rule is created by request external to PMD.
6105  * @param[out] error
6106  *   Pointer to error structure.
6107  *
6108  * @return
6109  *   - 0 on success and non root table.
6110  *   - 1 on success and root table.
6111  *   - a negative errno value otherwise and rte_errno is set.
6112  */
6113 static int
6114 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6115                             const struct mlx5_flow_tunnel *tunnel,
6116                             const struct rte_flow_attr *attributes,
6117                             const struct flow_grp_info *grp_info,
6118                             struct rte_flow_error *error)
6119 {
6120         struct mlx5_priv *priv = dev->data->dev_private;
6121         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6122         int ret = 0;
6123
6124 #ifndef HAVE_MLX5DV_DR
6125         RTE_SET_USED(tunnel);
6126         RTE_SET_USED(grp_info);
6127         if (attributes->group)
6128                 return rte_flow_error_set(error, ENOTSUP,
6129                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6130                                           NULL,
6131                                           "groups are not supported");
6132 #else
6133         uint32_t table = 0;
6134
6135         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6136                                        grp_info, error);
6137         if (ret)
6138                 return ret;
6139         if (!table)
6140                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6141 #endif
6142         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6143             attributes->priority > lowest_priority)
6144                 return rte_flow_error_set(error, ENOTSUP,
6145                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6146                                           NULL,
6147                                           "priority out of range");
6148         if (attributes->transfer) {
6149                 if (!priv->config.dv_esw_en)
6150                         return rte_flow_error_set
6151                                 (error, ENOTSUP,
6152                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6153                                  "E-Switch dr is not supported");
6154                 if (!(priv->representor || priv->master))
6155                         return rte_flow_error_set
6156                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6157                                  NULL, "E-Switch configuration can only be"
6158                                  " done by a master or a representor device");
6159                 if (attributes->egress)
6160                         return rte_flow_error_set
6161                                 (error, ENOTSUP,
6162                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6163                                  "egress is not supported");
6164         }
6165         if (!(attributes->egress ^ attributes->ingress))
6166                 return rte_flow_error_set(error, ENOTSUP,
6167                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6168                                           "must specify exactly one of "
6169                                           "ingress or egress");
6170         return ret;
6171 }
6172
6173 /**
6174  * Internal validation function. For validating both actions and items.
6175  *
6176  * @param[in] dev
6177  *   Pointer to the rte_eth_dev structure.
6178  * @param[in] attr
6179  *   Pointer to the flow attributes.
6180  * @param[in] items
6181  *   Pointer to the list of items.
6182  * @param[in] actions
6183  *   Pointer to the list of actions.
6184  * @param[in] external
6185  *   This flow rule is created by request external to PMD.
6186  * @param[in] hairpin
6187  *   Number of hairpin TX actions, 0 means classic flow.
6188  * @param[out] error
6189  *   Pointer to the error structure.
6190  *
6191  * @return
6192  *   0 on success, a negative errno value otherwise and rte_errno is set.
6193  */
6194 static int
6195 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6196                  const struct rte_flow_item items[],
6197                  const struct rte_flow_action actions[],
6198                  bool external, int hairpin, struct rte_flow_error *error)
6199 {
6200         int ret;
6201         uint64_t action_flags = 0;
6202         uint64_t item_flags = 0;
6203         uint64_t last_item = 0;
6204         uint8_t next_protocol = 0xff;
6205         uint16_t ether_type = 0;
6206         int actions_n = 0;
6207         uint8_t item_ipv6_proto = 0;
6208         int fdb_mirror_limit = 0;
6209         int modify_after_mirror = 0;
6210         const struct rte_flow_item *geneve_item = NULL;
6211         const struct rte_flow_item *gre_item = NULL;
6212         const struct rte_flow_item *gtp_item = NULL;
6213         const struct rte_flow_action_raw_decap *decap;
6214         const struct rte_flow_action_raw_encap *encap;
6215         const struct rte_flow_action_rss *rss = NULL;
6216         const struct rte_flow_action_rss *sample_rss = NULL;
6217         const struct rte_flow_action_count *count = NULL;
6218         const struct rte_flow_action_count *sample_count = NULL;
6219         const struct rte_flow_item_tcp nic_tcp_mask = {
6220                 .hdr = {
6221                         .tcp_flags = 0xFF,
6222                         .src_port = RTE_BE16(UINT16_MAX),
6223                         .dst_port = RTE_BE16(UINT16_MAX),
6224                 }
6225         };
6226         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6227                 .hdr = {
6228                         .src_addr =
6229                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6230                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6231                         .dst_addr =
6232                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6233                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6234                         .vtc_flow = RTE_BE32(0xffffffff),
6235                         .proto = 0xff,
6236                         .hop_limits = 0xff,
6237                 },
6238                 .has_frag_ext = 1,
6239         };
6240         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6241                 .hdr = {
6242                         .common = {
6243                                 .u32 =
6244                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6245                                         .type = 0xFF,
6246                                         }).u32),
6247                         },
6248                         .dummy[0] = 0xffffffff,
6249                 },
6250         };
6251         struct mlx5_priv *priv = dev->data->dev_private;
6252         struct mlx5_dev_config *dev_conf = &priv->config;
6253         uint16_t queue_index = 0xFFFF;
6254         const struct rte_flow_item_vlan *vlan_m = NULL;
6255         uint32_t rw_act_num = 0;
6256         uint64_t is_root;
6257         const struct mlx5_flow_tunnel *tunnel;
6258         struct flow_grp_info grp_info = {
6259                 .external = !!external,
6260                 .transfer = !!attr->transfer,
6261                 .fdb_def_rule = !!priv->fdb_def_rule,
6262         };
6263         const struct rte_eth_hairpin_conf *conf;
6264
6265         if (items == NULL)
6266                 return -1;
6267         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6268                 tunnel = flow_items_to_tunnel(items);
6269                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6270                                 MLX5_FLOW_ACTION_DECAP;
6271         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6272                 tunnel = flow_actions_to_tunnel(actions);
6273                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6274         } else {
6275                 tunnel = NULL;
6276         }
6277         if (tunnel && priv->representor)
6278                 return rte_flow_error_set(error, ENOTSUP,
6279                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6280                                           "decap not supported "
6281                                           "for VF representor");
6282         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6283                                 (dev, tunnel, attr, items, actions);
6284         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6285         if (ret < 0)
6286                 return ret;
6287         is_root = (uint64_t)ret;
6288         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6289                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6290                 int type = items->type;
6291
6292                 if (!mlx5_flow_os_item_supported(type))
6293                         return rte_flow_error_set(error, ENOTSUP,
6294                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6295                                                   NULL, "item not supported");
6296                 switch (type) {
6297                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6298                         if (items[0].type != (typeof(items[0].type))
6299                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6300                                 return rte_flow_error_set
6301                                                 (error, EINVAL,
6302                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6303                                                 NULL, "MLX5 private items "
6304                                                 "must be the first");
6305                         break;
6306                 case RTE_FLOW_ITEM_TYPE_VOID:
6307                         break;
6308                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6309                         ret = flow_dv_validate_item_port_id
6310                                         (dev, items, attr, item_flags, error);
6311                         if (ret < 0)
6312                                 return ret;
6313                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6314                         break;
6315                 case RTE_FLOW_ITEM_TYPE_ETH:
6316                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6317                                                           true, error);
6318                         if (ret < 0)
6319                                 return ret;
6320                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6321                                              MLX5_FLOW_LAYER_OUTER_L2;
6322                         if (items->mask != NULL && items->spec != NULL) {
6323                                 ether_type =
6324                                         ((const struct rte_flow_item_eth *)
6325                                          items->spec)->type;
6326                                 ether_type &=
6327                                         ((const struct rte_flow_item_eth *)
6328                                          items->mask)->type;
6329                                 ether_type = rte_be_to_cpu_16(ether_type);
6330                         } else {
6331                                 ether_type = 0;
6332                         }
6333                         break;
6334                 case RTE_FLOW_ITEM_TYPE_VLAN:
6335                         ret = flow_dv_validate_item_vlan(items, item_flags,
6336                                                          dev, error);
6337                         if (ret < 0)
6338                                 return ret;
6339                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6340                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6341                         if (items->mask != NULL && items->spec != NULL) {
6342                                 ether_type =
6343                                         ((const struct rte_flow_item_vlan *)
6344                                          items->spec)->inner_type;
6345                                 ether_type &=
6346                                         ((const struct rte_flow_item_vlan *)
6347                                          items->mask)->inner_type;
6348                                 ether_type = rte_be_to_cpu_16(ether_type);
6349                         } else {
6350                                 ether_type = 0;
6351                         }
6352                         /* Store outer VLAN mask for of_push_vlan action. */
6353                         if (!tunnel)
6354                                 vlan_m = items->mask;
6355                         break;
6356                 case RTE_FLOW_ITEM_TYPE_IPV4:
6357                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6358                                                   &item_flags, &tunnel);
6359                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6360                                                          last_item, ether_type,
6361                                                          error);
6362                         if (ret < 0)
6363                                 return ret;
6364                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6365                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6366                         if (items->mask != NULL &&
6367                             ((const struct rte_flow_item_ipv4 *)
6368                              items->mask)->hdr.next_proto_id) {
6369                                 next_protocol =
6370                                         ((const struct rte_flow_item_ipv4 *)
6371                                          (items->spec))->hdr.next_proto_id;
6372                                 next_protocol &=
6373                                         ((const struct rte_flow_item_ipv4 *)
6374                                          (items->mask))->hdr.next_proto_id;
6375                         } else {
6376                                 /* Reset for inner layer. */
6377                                 next_protocol = 0xff;
6378                         }
6379                         break;
6380                 case RTE_FLOW_ITEM_TYPE_IPV6:
6381                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6382                                                   &item_flags, &tunnel);
6383                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6384                                                            last_item,
6385                                                            ether_type,
6386                                                            &nic_ipv6_mask,
6387                                                            error);
6388                         if (ret < 0)
6389                                 return ret;
6390                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6391                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6392                         if (items->mask != NULL &&
6393                             ((const struct rte_flow_item_ipv6 *)
6394                              items->mask)->hdr.proto) {
6395                                 item_ipv6_proto =
6396                                         ((const struct rte_flow_item_ipv6 *)
6397                                          items->spec)->hdr.proto;
6398                                 next_protocol =
6399                                         ((const struct rte_flow_item_ipv6 *)
6400                                          items->spec)->hdr.proto;
6401                                 next_protocol &=
6402                                         ((const struct rte_flow_item_ipv6 *)
6403                                          items->mask)->hdr.proto;
6404                         } else {
6405                                 /* Reset for inner layer. */
6406                                 next_protocol = 0xff;
6407                         }
6408                         break;
6409                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6410                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6411                                                                   item_flags,
6412                                                                   error);
6413                         if (ret < 0)
6414                                 return ret;
6415                         last_item = tunnel ?
6416                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6417                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6418                         if (items->mask != NULL &&
6419                             ((const struct rte_flow_item_ipv6_frag_ext *)
6420                              items->mask)->hdr.next_header) {
6421                                 next_protocol =
6422                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6423                                  items->spec)->hdr.next_header;
6424                                 next_protocol &=
6425                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6426                                  items->mask)->hdr.next_header;
6427                         } else {
6428                                 /* Reset for inner layer. */
6429                                 next_protocol = 0xff;
6430                         }
6431                         break;
6432                 case RTE_FLOW_ITEM_TYPE_TCP:
6433                         ret = mlx5_flow_validate_item_tcp
6434                                                 (items, item_flags,
6435                                                  next_protocol,
6436                                                  &nic_tcp_mask,
6437                                                  error);
6438                         if (ret < 0)
6439                                 return ret;
6440                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6441                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6442                         break;
6443                 case RTE_FLOW_ITEM_TYPE_UDP:
6444                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6445                                                           next_protocol,
6446                                                           error);
6447                         if (ret < 0)
6448                                 return ret;
6449                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6450                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6451                         break;
6452                 case RTE_FLOW_ITEM_TYPE_GRE:
6453                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6454                                                           next_protocol, error);
6455                         if (ret < 0)
6456                                 return ret;
6457                         gre_item = items;
6458                         last_item = MLX5_FLOW_LAYER_GRE;
6459                         break;
6460                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6461                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6462                                                             next_protocol,
6463                                                             error);
6464                         if (ret < 0)
6465                                 return ret;
6466                         last_item = MLX5_FLOW_LAYER_NVGRE;
6467                         break;
6468                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6469                         ret = mlx5_flow_validate_item_gre_key
6470                                 (items, item_flags, gre_item, error);
6471                         if (ret < 0)
6472                                 return ret;
6473                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6474                         break;
6475                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6476                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6477                                                             error);
6478                         if (ret < 0)
6479                                 return ret;
6480                         last_item = MLX5_FLOW_LAYER_VXLAN;
6481                         break;
6482                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6483                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6484                                                                 item_flags, dev,
6485                                                                 error);
6486                         if (ret < 0)
6487                                 return ret;
6488                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6489                         break;
6490                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6491                         ret = mlx5_flow_validate_item_geneve(items,
6492                                                              item_flags, dev,
6493                                                              error);
6494                         if (ret < 0)
6495                                 return ret;
6496                         geneve_item = items;
6497                         last_item = MLX5_FLOW_LAYER_GENEVE;
6498                         break;
6499                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6500                         ret = mlx5_flow_validate_item_geneve_opt(items,
6501                                                                  last_item,
6502                                                                  geneve_item,
6503                                                                  dev,
6504                                                                  error);
6505                         if (ret < 0)
6506                                 return ret;
6507                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6508                         break;
6509                 case RTE_FLOW_ITEM_TYPE_MPLS:
6510                         ret = mlx5_flow_validate_item_mpls(dev, items,
6511                                                            item_flags,
6512                                                            last_item, error);
6513                         if (ret < 0)
6514                                 return ret;
6515                         last_item = MLX5_FLOW_LAYER_MPLS;
6516                         break;
6517
6518                 case RTE_FLOW_ITEM_TYPE_MARK:
6519                         ret = flow_dv_validate_item_mark(dev, items, attr,
6520                                                          error);
6521                         if (ret < 0)
6522                                 return ret;
6523                         last_item = MLX5_FLOW_ITEM_MARK;
6524                         break;
6525                 case RTE_FLOW_ITEM_TYPE_META:
6526                         ret = flow_dv_validate_item_meta(dev, items, attr,
6527                                                          error);
6528                         if (ret < 0)
6529                                 return ret;
6530                         last_item = MLX5_FLOW_ITEM_METADATA;
6531                         break;
6532                 case RTE_FLOW_ITEM_TYPE_ICMP:
6533                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6534                                                            next_protocol,
6535                                                            error);
6536                         if (ret < 0)
6537                                 return ret;
6538                         last_item = MLX5_FLOW_LAYER_ICMP;
6539                         break;
6540                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6541                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6542                                                             next_protocol,
6543                                                             error);
6544                         if (ret < 0)
6545                                 return ret;
6546                         item_ipv6_proto = IPPROTO_ICMPV6;
6547                         last_item = MLX5_FLOW_LAYER_ICMP6;
6548                         break;
6549                 case RTE_FLOW_ITEM_TYPE_TAG:
6550                         ret = flow_dv_validate_item_tag(dev, items,
6551                                                         attr, error);
6552                         if (ret < 0)
6553                                 return ret;
6554                         last_item = MLX5_FLOW_ITEM_TAG;
6555                         break;
6556                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6557                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6558                         break;
6559                 case RTE_FLOW_ITEM_TYPE_GTP:
6560                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6561                                                         error);
6562                         if (ret < 0)
6563                                 return ret;
6564                         gtp_item = items;
6565                         last_item = MLX5_FLOW_LAYER_GTP;
6566                         break;
6567                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6568                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6569                                                             gtp_item, attr,
6570                                                             error);
6571                         if (ret < 0)
6572                                 return ret;
6573                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6574                         break;
6575                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6576                         /* Capacity will be checked in the translate stage. */
6577                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6578                                                             last_item,
6579                                                             ether_type,
6580                                                             &nic_ecpri_mask,
6581                                                             error);
6582                         if (ret < 0)
6583                                 return ret;
6584                         last_item = MLX5_FLOW_LAYER_ECPRI;
6585                         break;
6586                 default:
6587                         return rte_flow_error_set(error, ENOTSUP,
6588                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6589                                                   NULL, "item not supported");
6590                 }
6591                 item_flags |= last_item;
6592         }
6593         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6594                 int type = actions->type;
6595
6596                 if (!mlx5_flow_os_action_supported(type))
6597                         return rte_flow_error_set(error, ENOTSUP,
6598                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6599                                                   actions,
6600                                                   "action not supported");
6601                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6602                         return rte_flow_error_set(error, ENOTSUP,
6603                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6604                                                   actions, "too many actions");
6605                 switch (type) {
6606                 case RTE_FLOW_ACTION_TYPE_VOID:
6607                         break;
6608                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6609                         ret = flow_dv_validate_action_port_id(dev,
6610                                                               action_flags,
6611                                                               actions,
6612                                                               attr,
6613                                                               error);
6614                         if (ret)
6615                                 return ret;
6616                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6617                         ++actions_n;
6618                         break;
6619                 case RTE_FLOW_ACTION_TYPE_FLAG:
6620                         ret = flow_dv_validate_action_flag(dev, action_flags,
6621                                                            attr, error);
6622                         if (ret < 0)
6623                                 return ret;
6624                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6625                                 /* Count all modify-header actions as one. */
6626                                 if (!(action_flags &
6627                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6628                                         ++actions_n;
6629                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6630                                                 MLX5_FLOW_ACTION_MARK_EXT;
6631                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6632                                         modify_after_mirror = 1;
6633
6634                         } else {
6635                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6636                                 ++actions_n;
6637                         }
6638                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6639                         break;
6640                 case RTE_FLOW_ACTION_TYPE_MARK:
6641                         ret = flow_dv_validate_action_mark(dev, actions,
6642                                                            action_flags,
6643                                                            attr, error);
6644                         if (ret < 0)
6645                                 return ret;
6646                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6647                                 /* Count all modify-header actions as one. */
6648                                 if (!(action_flags &
6649                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6650                                         ++actions_n;
6651                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6652                                                 MLX5_FLOW_ACTION_MARK_EXT;
6653                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6654                                         modify_after_mirror = 1;
6655                         } else {
6656                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6657                                 ++actions_n;
6658                         }
6659                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6660                         break;
6661                 case RTE_FLOW_ACTION_TYPE_SET_META:
6662                         ret = flow_dv_validate_action_set_meta(dev, actions,
6663                                                                action_flags,
6664                                                                attr, error);
6665                         if (ret < 0)
6666                                 return ret;
6667                         /* Count all modify-header actions as one action. */
6668                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6669                                 ++actions_n;
6670                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6671                                 modify_after_mirror = 1;
6672                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6673                         rw_act_num += MLX5_ACT_NUM_SET_META;
6674                         break;
6675                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6676                         ret = flow_dv_validate_action_set_tag(dev, actions,
6677                                                               action_flags,
6678                                                               attr, error);
6679                         if (ret < 0)
6680                                 return ret;
6681                         /* Count all modify-header actions as one action. */
6682                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6683                                 ++actions_n;
6684                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6685                                 modify_after_mirror = 1;
6686                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6687                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6688                         break;
6689                 case RTE_FLOW_ACTION_TYPE_DROP:
6690                         ret = mlx5_flow_validate_action_drop(action_flags,
6691                                                              attr, error);
6692                         if (ret < 0)
6693                                 return ret;
6694                         action_flags |= MLX5_FLOW_ACTION_DROP;
6695                         ++actions_n;
6696                         break;
6697                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6698                         ret = mlx5_flow_validate_action_queue(actions,
6699                                                               action_flags, dev,
6700                                                               attr, error);
6701                         if (ret < 0)
6702                                 return ret;
6703                         queue_index = ((const struct rte_flow_action_queue *)
6704                                                         (actions->conf))->index;
6705                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6706                         ++actions_n;
6707                         break;
6708                 case RTE_FLOW_ACTION_TYPE_RSS:
6709                         rss = actions->conf;
6710                         ret = mlx5_flow_validate_action_rss(actions,
6711                                                             action_flags, dev,
6712                                                             attr, item_flags,
6713                                                             error);
6714                         if (ret < 0)
6715                                 return ret;
6716                         if (rss && sample_rss &&
6717                             (sample_rss->level != rss->level ||
6718                             sample_rss->types != rss->types))
6719                                 return rte_flow_error_set(error, ENOTSUP,
6720                                         RTE_FLOW_ERROR_TYPE_ACTION,
6721                                         NULL,
6722                                         "Can't use the different RSS types "
6723                                         "or level in the same flow");
6724                         if (rss != NULL && rss->queue_num)
6725                                 queue_index = rss->queue[0];
6726                         action_flags |= MLX5_FLOW_ACTION_RSS;
6727                         ++actions_n;
6728                         break;
6729                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6730                         ret =
6731                         mlx5_flow_validate_action_default_miss(action_flags,
6732                                         attr, error);
6733                         if (ret < 0)
6734                                 return ret;
6735                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6736                         ++actions_n;
6737                         break;
6738                 case RTE_FLOW_ACTION_TYPE_COUNT:
6739                         ret = flow_dv_validate_action_count(dev, actions,
6740                                                             action_flags,
6741                                                             error);
6742                         if (ret < 0)
6743                                 return ret;
6744                         count = actions->conf;
6745                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6746                         ++actions_n;
6747                         break;
6748                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6749                         if (flow_dv_validate_action_pop_vlan(dev,
6750                                                              action_flags,
6751                                                              actions,
6752                                                              item_flags, attr,
6753                                                              error))
6754                                 return -rte_errno;
6755                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6756                                 modify_after_mirror = 1;
6757                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6758                         ++actions_n;
6759                         break;
6760                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6761                         ret = flow_dv_validate_action_push_vlan(dev,
6762                                                                 action_flags,
6763                                                                 vlan_m,
6764                                                                 actions, attr,
6765                                                                 error);
6766                         if (ret < 0)
6767                                 return ret;
6768                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6769                                 modify_after_mirror = 1;
6770                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6771                         ++actions_n;
6772                         break;
6773                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6774                         ret = flow_dv_validate_action_set_vlan_pcp
6775                                                 (action_flags, actions, error);
6776                         if (ret < 0)
6777                                 return ret;
6778                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6779                                 modify_after_mirror = 1;
6780                         /* Count PCP with push_vlan command. */
6781                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6782                         break;
6783                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6784                         ret = flow_dv_validate_action_set_vlan_vid
6785                                                 (item_flags, action_flags,
6786                                                  actions, error);
6787                         if (ret < 0)
6788                                 return ret;
6789                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6790                                 modify_after_mirror = 1;
6791                         /* Count VID with push_vlan command. */
6792                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6793                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6794                         break;
6795                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6796                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6797                         ret = flow_dv_validate_action_l2_encap(dev,
6798                                                                action_flags,
6799                                                                actions, attr,
6800                                                                error);
6801                         if (ret < 0)
6802                                 return ret;
6803                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6804                         ++actions_n;
6805                         break;
6806                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6807                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6808                         ret = flow_dv_validate_action_decap(dev, action_flags,
6809                                                             actions, item_flags,
6810                                                             attr, error);
6811                         if (ret < 0)
6812                                 return ret;
6813                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6814                                 modify_after_mirror = 1;
6815                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6816                         ++actions_n;
6817                         break;
6818                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6819                         ret = flow_dv_validate_action_raw_encap_decap
6820                                 (dev, NULL, actions->conf, attr, &action_flags,
6821                                  &actions_n, actions, item_flags, error);
6822                         if (ret < 0)
6823                                 return ret;
6824                         break;
6825                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6826                         decap = actions->conf;
6827                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6828                                 ;
6829                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6830                                 encap = NULL;
6831                                 actions--;
6832                         } else {
6833                                 encap = actions->conf;
6834                         }
6835                         ret = flow_dv_validate_action_raw_encap_decap
6836                                            (dev,
6837                                             decap ? decap : &empty_decap, encap,
6838                                             attr, &action_flags, &actions_n,
6839                                             actions, item_flags, error);
6840                         if (ret < 0)
6841                                 return ret;
6842                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6843                             (action_flags & MLX5_FLOW_ACTION_DECAP))
6844                                 modify_after_mirror = 1;
6845                         break;
6846                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6847                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6848                         ret = flow_dv_validate_action_modify_mac(action_flags,
6849                                                                  actions,
6850                                                                  item_flags,
6851                                                                  error);
6852                         if (ret < 0)
6853                                 return ret;
6854                         /* Count all modify-header actions as one action. */
6855                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6856                                 ++actions_n;
6857                         action_flags |= actions->type ==
6858                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6859                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6860                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6861                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6862                                 modify_after_mirror = 1;
6863                         /*
6864                          * Even if the source and destination MAC addresses have
6865                          * overlap in the header with 4B alignment, the convert
6866                          * function will handle them separately and 4 SW actions
6867                          * will be created. And 2 actions will be added each
6868                          * time no matter how many bytes of address will be set.
6869                          */
6870                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6871                         break;
6872                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6873                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6874                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6875                                                                   actions,
6876                                                                   item_flags,
6877                                                                   error);
6878                         if (ret < 0)
6879                                 return ret;
6880                         /* Count all modify-header actions as one action. */
6881                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6882                                 ++actions_n;
6883                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6884                                 modify_after_mirror = 1;
6885                         action_flags |= actions->type ==
6886                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6887                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6888                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6889                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6890                         break;
6891                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6892                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6893                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6894                                                                   actions,
6895                                                                   item_flags,
6896                                                                   error);
6897                         if (ret < 0)
6898                                 return ret;
6899                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6900                                 return rte_flow_error_set(error, ENOTSUP,
6901                                         RTE_FLOW_ERROR_TYPE_ACTION,
6902                                         actions,
6903                                         "Can't change header "
6904                                         "with ICMPv6 proto");
6905                         /* Count all modify-header actions as one action. */
6906                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6907                                 ++actions_n;
6908                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6909                                 modify_after_mirror = 1;
6910                         action_flags |= actions->type ==
6911                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6912                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6913                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6914                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6915                         break;
6916                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6917                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6918                         ret = flow_dv_validate_action_modify_tp(action_flags,
6919                                                                 actions,
6920                                                                 item_flags,
6921                                                                 error);
6922                         if (ret < 0)
6923                                 return ret;
6924                         /* Count all modify-header actions as one action. */
6925                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6926                                 ++actions_n;
6927                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6928                                 modify_after_mirror = 1;
6929                         action_flags |= actions->type ==
6930                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6931                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6932                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6933                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6934                         break;
6935                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6936                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6937                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6938                                                                  actions,
6939                                                                  item_flags,
6940                                                                  error);
6941                         if (ret < 0)
6942                                 return ret;
6943                         /* Count all modify-header actions as one action. */
6944                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6945                                 ++actions_n;
6946                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6947                                 modify_after_mirror = 1;
6948                         action_flags |= actions->type ==
6949                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6950                                                 MLX5_FLOW_ACTION_SET_TTL :
6951                                                 MLX5_FLOW_ACTION_DEC_TTL;
6952                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6953                         break;
6954                 case RTE_FLOW_ACTION_TYPE_JUMP:
6955                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6956                                                            action_flags,
6957                                                            attr, external,
6958                                                            error);
6959                         if (ret)
6960                                 return ret;
6961                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6962                             fdb_mirror_limit)
6963                                 return rte_flow_error_set(error, EINVAL,
6964                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6965                                                   NULL,
6966                                                   "sample and jump action combination is not supported");
6967                         ++actions_n;
6968                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6969                         break;
6970                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6971                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6972                         ret = flow_dv_validate_action_modify_tcp_seq
6973                                                                 (action_flags,
6974                                                                  actions,
6975                                                                  item_flags,
6976                                                                  error);
6977                         if (ret < 0)
6978                                 return ret;
6979                         /* Count all modify-header actions as one action. */
6980                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6981                                 ++actions_n;
6982                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6983                                 modify_after_mirror = 1;
6984                         action_flags |= actions->type ==
6985                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6986                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6987                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6988                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6989                         break;
6990                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6991                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6992                         ret = flow_dv_validate_action_modify_tcp_ack
6993                                                                 (action_flags,
6994                                                                  actions,
6995                                                                  item_flags,
6996                                                                  error);
6997                         if (ret < 0)
6998                                 return ret;
6999                         /* Count all modify-header actions as one action. */
7000                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7001                                 ++actions_n;
7002                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7003                                 modify_after_mirror = 1;
7004                         action_flags |= actions->type ==
7005                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7006                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
7007                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7008                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7009                         break;
7010                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7011                         break;
7012                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7013                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7014                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7015                         break;
7016                 case RTE_FLOW_ACTION_TYPE_METER:
7017                         ret = mlx5_flow_validate_action_meter(dev,
7018                                                               action_flags,
7019                                                               actions, attr,
7020                                                               error);
7021                         if (ret < 0)
7022                                 return ret;
7023                         action_flags |= MLX5_FLOW_ACTION_METER;
7024                         ++actions_n;
7025                         /* Meter action will add one more TAG action. */
7026                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7027                         break;
7028                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7029                         if (!attr->transfer && !attr->group)
7030                                 return rte_flow_error_set(error, ENOTSUP,
7031                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7032                                                                            NULL,
7033                           "Shared ASO age action is not supported for group 0");
7034                         action_flags |= MLX5_FLOW_ACTION_AGE;
7035                         ++actions_n;
7036                         break;
7037                 case RTE_FLOW_ACTION_TYPE_AGE:
7038                         ret = flow_dv_validate_action_age(action_flags,
7039                                                           actions, dev,
7040                                                           error);
7041                         if (ret < 0)
7042                                 return ret;
7043                         /*
7044                          * Validate the regular AGE action (using counter)
7045                          * mutual exclusion with share counter actions.
7046                          */
7047                         if (!priv->sh->flow_hit_aso_en) {
7048                                 if (count && count->shared)
7049                                         return rte_flow_error_set
7050                                                 (error, EINVAL,
7051                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7052                                                 NULL,
7053                                                 "old age and shared count combination is not supported");
7054                                 if (sample_count)
7055                                         return rte_flow_error_set
7056                                                 (error, EINVAL,
7057                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7058                                                 NULL,
7059                                                 "old age action and count must be in the same sub flow");
7060                         }
7061                         action_flags |= MLX5_FLOW_ACTION_AGE;
7062                         ++actions_n;
7063                         break;
7064                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7065                         ret = flow_dv_validate_action_modify_ipv4_dscp
7066                                                          (action_flags,
7067                                                           actions,
7068                                                           item_flags,
7069                                                           error);
7070                         if (ret < 0)
7071                                 return ret;
7072                         /* Count all modify-header actions as one action. */
7073                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7074                                 ++actions_n;
7075                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7076                                 modify_after_mirror = 1;
7077                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7078                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7079                         break;
7080                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7081                         ret = flow_dv_validate_action_modify_ipv6_dscp
7082                                                                 (action_flags,
7083                                                                  actions,
7084                                                                  item_flags,
7085                                                                  error);
7086                         if (ret < 0)
7087                                 return ret;
7088                         /* Count all modify-header actions as one action. */
7089                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7090                                 ++actions_n;
7091                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7092                                 modify_after_mirror = 1;
7093                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7094                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7095                         break;
7096                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7097                         ret = flow_dv_validate_action_sample(&action_flags,
7098                                                              actions, dev,
7099                                                              attr, item_flags,
7100                                                              rss, &sample_rss,
7101                                                              &sample_count,
7102                                                              &fdb_mirror_limit,
7103                                                              error);
7104                         if (ret < 0)
7105                                 return ret;
7106                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7107                         ++actions_n;
7108                         break;
7109                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7110                         if (actions[0].type != (typeof(actions[0].type))
7111                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7112                                 return rte_flow_error_set
7113                                                 (error, EINVAL,
7114                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7115                                                 NULL, "MLX5 private action "
7116                                                 "must be the first");
7117
7118                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7119                         break;
7120                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7121                         ret = flow_dv_validate_action_modify_field(dev,
7122                                                                    action_flags,
7123                                                                    actions,
7124                                                                    attr,
7125                                                                    error);
7126                         if (ret < 0)
7127                                 return ret;
7128                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7129                                 modify_after_mirror = 1;
7130                         /* Count all modify-header actions as one action. */
7131                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7132                                 ++actions_n;
7133                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7134                         rw_act_num += ret;
7135                         break;
7136                 default:
7137                         return rte_flow_error_set(error, ENOTSUP,
7138                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7139                                                   actions,
7140                                                   "action not supported");
7141                 }
7142         }
7143         /*
7144          * Validate actions in flow rules
7145          * - Explicit decap action is prohibited by the tunnel offload API.
7146          * - Drop action in tunnel steer rule is prohibited by the API.
7147          * - Application cannot use MARK action because it's value can mask
7148          *   tunnel default miss nitification.
7149          * - JUMP in tunnel match rule has no support in current PMD
7150          *   implementation.
7151          * - TAG & META are reserved for future uses.
7152          */
7153         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7154                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
7155                                             MLX5_FLOW_ACTION_MARK     |
7156                                             MLX5_FLOW_ACTION_SET_TAG  |
7157                                             MLX5_FLOW_ACTION_SET_META |
7158                                             MLX5_FLOW_ACTION_DROP;
7159
7160                 if (action_flags & bad_actions_mask)
7161                         return rte_flow_error_set
7162                                         (error, EINVAL,
7163                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7164                                         "Invalid RTE action in tunnel "
7165                                         "set decap rule");
7166                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7167                         return rte_flow_error_set
7168                                         (error, EINVAL,
7169                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7170                                         "tunnel set decap rule must terminate "
7171                                         "with JUMP");
7172                 if (!attr->ingress)
7173                         return rte_flow_error_set
7174                                         (error, EINVAL,
7175                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7176                                         "tunnel flows for ingress traffic only");
7177         }
7178         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7179                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7180                                             MLX5_FLOW_ACTION_MARK    |
7181                                             MLX5_FLOW_ACTION_SET_TAG |
7182                                             MLX5_FLOW_ACTION_SET_META;
7183
7184                 if (action_flags & bad_actions_mask)
7185                         return rte_flow_error_set
7186                                         (error, EINVAL,
7187                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7188                                         "Invalid RTE action in tunnel "
7189                                         "set match rule");
7190         }
7191         /*
7192          * Validate the drop action mutual exclusion with other actions.
7193          * Drop action is mutually-exclusive with any other action, except for
7194          * Count action.
7195          * Drop action compatibility with tunnel offload was already validated.
7196          */
7197         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7198                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7199         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7200             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7201                 return rte_flow_error_set(error, EINVAL,
7202                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7203                                           "Drop action is mutually-exclusive "
7204                                           "with any other action, except for "
7205                                           "Count action");
7206         /* Eswitch has few restrictions on using items and actions */
7207         if (attr->transfer) {
7208                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7209                     action_flags & MLX5_FLOW_ACTION_FLAG)
7210                         return rte_flow_error_set(error, ENOTSUP,
7211                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7212                                                   NULL,
7213                                                   "unsupported action FLAG");
7214                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7215                     action_flags & MLX5_FLOW_ACTION_MARK)
7216                         return rte_flow_error_set(error, ENOTSUP,
7217                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7218                                                   NULL,
7219                                                   "unsupported action MARK");
7220                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7221                         return rte_flow_error_set(error, ENOTSUP,
7222                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7223                                                   NULL,
7224                                                   "unsupported action QUEUE");
7225                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7226                         return rte_flow_error_set(error, ENOTSUP,
7227                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7228                                                   NULL,
7229                                                   "unsupported action RSS");
7230                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7231                         return rte_flow_error_set(error, EINVAL,
7232                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7233                                                   actions,
7234                                                   "no fate action is found");
7235         } else {
7236                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7237                         return rte_flow_error_set(error, EINVAL,
7238                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7239                                                   actions,
7240                                                   "no fate action is found");
7241         }
7242         /*
7243          * Continue validation for Xcap and VLAN actions.
7244          * If hairpin is working in explicit TX rule mode, there is no actions
7245          * splitting and the validation of hairpin ingress flow should be the
7246          * same as other standard flows.
7247          */
7248         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7249                              MLX5_FLOW_VLAN_ACTIONS)) &&
7250             (queue_index == 0xFFFF ||
7251              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7252              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7253              conf->tx_explicit != 0))) {
7254                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7255                     MLX5_FLOW_XCAP_ACTIONS)
7256                         return rte_flow_error_set(error, ENOTSUP,
7257                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7258                                                   NULL, "encap and decap "
7259                                                   "combination aren't supported");
7260                 if (!attr->transfer && attr->ingress) {
7261                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7262                                 return rte_flow_error_set
7263                                                 (error, ENOTSUP,
7264                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7265                                                  NULL, "encap is not supported"
7266                                                  " for ingress traffic");
7267                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7268                                 return rte_flow_error_set
7269                                                 (error, ENOTSUP,
7270                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7271                                                  NULL, "push VLAN action not "
7272                                                  "supported for ingress");
7273                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7274                                         MLX5_FLOW_VLAN_ACTIONS)
7275                                 return rte_flow_error_set
7276                                                 (error, ENOTSUP,
7277                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7278                                                  NULL, "no support for "
7279                                                  "multiple VLAN actions");
7280                 }
7281         }
7282         /*
7283          * Hairpin flow will add one more TAG action in TX implicit mode.
7284          * In TX explicit mode, there will be no hairpin flow ID.
7285          */
7286         if (hairpin > 0)
7287                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7288         /* extra metadata enabled: one more TAG action will be add. */
7289         if (dev_conf->dv_flow_en &&
7290             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7291             mlx5_flow_ext_mreg_supported(dev))
7292                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7293         if (rw_act_num >
7294                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7295                 return rte_flow_error_set(error, ENOTSUP,
7296                                           RTE_FLOW_ERROR_TYPE_ACTION,
7297                                           NULL, "too many header modify"
7298                                           " actions to support");
7299         }
7300         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7301         if (fdb_mirror_limit && modify_after_mirror)
7302                 return rte_flow_error_set(error, EINVAL,
7303                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7304                                 "sample before modify action is not supported");
7305         return 0;
7306 }
7307
7308 /**
7309  * Internal preparation function. Allocates the DV flow size,
7310  * this size is constant.
7311  *
7312  * @param[in] dev
7313  *   Pointer to the rte_eth_dev structure.
7314  * @param[in] attr
7315  *   Pointer to the flow attributes.
7316  * @param[in] items
7317  *   Pointer to the list of items.
7318  * @param[in] actions
7319  *   Pointer to the list of actions.
7320  * @param[out] error
7321  *   Pointer to the error structure.
7322  *
7323  * @return
7324  *   Pointer to mlx5_flow object on success,
7325  *   otherwise NULL and rte_errno is set.
7326  */
7327 static struct mlx5_flow *
7328 flow_dv_prepare(struct rte_eth_dev *dev,
7329                 const struct rte_flow_attr *attr __rte_unused,
7330                 const struct rte_flow_item items[] __rte_unused,
7331                 const struct rte_flow_action actions[] __rte_unused,
7332                 struct rte_flow_error *error)
7333 {
7334         uint32_t handle_idx = 0;
7335         struct mlx5_flow *dev_flow;
7336         struct mlx5_flow_handle *dev_handle;
7337         struct mlx5_priv *priv = dev->data->dev_private;
7338         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7339
7340         MLX5_ASSERT(wks);
7341         /* In case of corrupting the memory. */
7342         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7343                 rte_flow_error_set(error, ENOSPC,
7344                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7345                                    "not free temporary device flow");
7346                 return NULL;
7347         }
7348         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7349                                    &handle_idx);
7350         if (!dev_handle) {
7351                 rte_flow_error_set(error, ENOMEM,
7352                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7353                                    "not enough memory to create flow handle");
7354                 return NULL;
7355         }
7356         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7357         dev_flow = &wks->flows[wks->flow_idx++];
7358         memset(dev_flow, 0, sizeof(*dev_flow));
7359         dev_flow->handle = dev_handle;
7360         dev_flow->handle_idx = handle_idx;
7361         /*
7362          * In some old rdma-core releases, before continuing, a check of the
7363          * length of matching parameter will be done at first. It needs to use
7364          * the length without misc4 param. If the flow has misc4 support, then
7365          * the length needs to be adjusted accordingly. Each param member is
7366          * aligned with a 64B boundary naturally.
7367          */
7368         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7369                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7370         dev_flow->ingress = attr->ingress;
7371         dev_flow->dv.transfer = attr->transfer;
7372         return dev_flow;
7373 }
7374
7375 #ifdef RTE_LIBRTE_MLX5_DEBUG
7376 /**
7377  * Sanity check for match mask and value. Similar to check_valid_spec() in
7378  * kernel driver. If unmasked bit is present in value, it returns failure.
7379  *
7380  * @param match_mask
7381  *   pointer to match mask buffer.
7382  * @param match_value
7383  *   pointer to match value buffer.
7384  *
7385  * @return
7386  *   0 if valid, -EINVAL otherwise.
7387  */
7388 static int
7389 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7390 {
7391         uint8_t *m = match_mask;
7392         uint8_t *v = match_value;
7393         unsigned int i;
7394
7395         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7396                 if (v[i] & ~m[i]) {
7397                         DRV_LOG(ERR,
7398                                 "match_value differs from match_criteria"
7399                                 " %p[%u] != %p[%u]",
7400                                 match_value, i, match_mask, i);
7401                         return -EINVAL;
7402                 }
7403         }
7404         return 0;
7405 }
7406 #endif
7407
7408 /**
7409  * Add match of ip_version.
7410  *
7411  * @param[in] group
7412  *   Flow group.
7413  * @param[in] headers_v
7414  *   Values header pointer.
7415  * @param[in] headers_m
7416  *   Masks header pointer.
7417  * @param[in] ip_version
7418  *   The IP version to set.
7419  */
7420 static inline void
7421 flow_dv_set_match_ip_version(uint32_t group,
7422                              void *headers_v,
7423                              void *headers_m,
7424                              uint8_t ip_version)
7425 {
7426         if (group == 0)
7427                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7428         else
7429                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7430                          ip_version);
7431         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7432         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7433         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7434 }
7435
7436 /**
7437  * Add Ethernet item to matcher and to the value.
7438  *
7439  * @param[in, out] matcher
7440  *   Flow matcher.
7441  * @param[in, out] key
7442  *   Flow matcher value.
7443  * @param[in] item
7444  *   Flow pattern to translate.
7445  * @param[in] inner
7446  *   Item is inner pattern.
7447  */
7448 static void
7449 flow_dv_translate_item_eth(void *matcher, void *key,
7450                            const struct rte_flow_item *item, int inner,
7451                            uint32_t group)
7452 {
7453         const struct rte_flow_item_eth *eth_m = item->mask;
7454         const struct rte_flow_item_eth *eth_v = item->spec;
7455         const struct rte_flow_item_eth nic_mask = {
7456                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7457                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7458                 .type = RTE_BE16(0xffff),
7459                 .has_vlan = 0,
7460         };
7461         void *hdrs_m;
7462         void *hdrs_v;
7463         char *l24_v;
7464         unsigned int i;
7465
7466         if (!eth_v)
7467                 return;
7468         if (!eth_m)
7469                 eth_m = &nic_mask;
7470         if (inner) {
7471                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7472                                          inner_headers);
7473                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7474         } else {
7475                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7476                                          outer_headers);
7477                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7478         }
7479         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7480                &eth_m->dst, sizeof(eth_m->dst));
7481         /* The value must be in the range of the mask. */
7482         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7483         for (i = 0; i < sizeof(eth_m->dst); ++i)
7484                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7485         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7486                &eth_m->src, sizeof(eth_m->src));
7487         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7488         /* The value must be in the range of the mask. */
7489         for (i = 0; i < sizeof(eth_m->dst); ++i)
7490                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7491         /*
7492          * HW supports match on one Ethertype, the Ethertype following the last
7493          * VLAN tag of the packet (see PRM).
7494          * Set match on ethertype only if ETH header is not followed by VLAN.
7495          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7496          * ethertype, and use ip_version field instead.
7497          * eCPRI over Ether layer will use type value 0xAEFE.
7498          */
7499         if (eth_m->type == 0xFFFF) {
7500                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7501                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7502                 switch (eth_v->type) {
7503                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7504                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7505                         return;
7506                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7507                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7508                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7509                         return;
7510                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7511                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7512                         return;
7513                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7514                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7515                         return;
7516                 default:
7517                         break;
7518                 }
7519         }
7520         if (eth_m->has_vlan) {
7521                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7522                 if (eth_v->has_vlan) {
7523                         /*
7524                          * Here, when also has_more_vlan field in VLAN item is
7525                          * not set, only single-tagged packets will be matched.
7526                          */
7527                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7528                         return;
7529                 }
7530         }
7531         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7532                  rte_be_to_cpu_16(eth_m->type));
7533         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7534         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7535 }
7536
7537 /**
7538  * Add VLAN item to matcher and to the value.
7539  *
7540  * @param[in, out] dev_flow
7541  *   Flow descriptor.
7542  * @param[in, out] matcher
7543  *   Flow matcher.
7544  * @param[in, out] key
7545  *   Flow matcher value.
7546  * @param[in] item
7547  *   Flow pattern to translate.
7548  * @param[in] inner
7549  *   Item is inner pattern.
7550  */
7551 static void
7552 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7553                             void *matcher, void *key,
7554                             const struct rte_flow_item *item,
7555                             int inner, uint32_t group)
7556 {
7557         const struct rte_flow_item_vlan *vlan_m = item->mask;
7558         const struct rte_flow_item_vlan *vlan_v = item->spec;
7559         void *hdrs_m;
7560         void *hdrs_v;
7561         uint16_t tci_m;
7562         uint16_t tci_v;
7563
7564         if (inner) {
7565                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7566                                          inner_headers);
7567                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7568         } else {
7569                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7570                                          outer_headers);
7571                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7572                 /*
7573                  * This is workaround, masks are not supported,
7574                  * and pre-validated.
7575                  */
7576                 if (vlan_v)
7577                         dev_flow->handle->vf_vlan.tag =
7578                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7579         }
7580         /*
7581          * When VLAN item exists in flow, mark packet as tagged,
7582          * even if TCI is not specified.
7583          */
7584         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7585                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7586                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7587         }
7588         if (!vlan_v)
7589                 return;
7590         if (!vlan_m)
7591                 vlan_m = &rte_flow_item_vlan_mask;
7592         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7593         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7594         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7595         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7596         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7597         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7598         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7599         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7600         /*
7601          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7602          * ethertype, and use ip_version field instead.
7603          */
7604         if (vlan_m->inner_type == 0xFFFF) {
7605                 switch (vlan_v->inner_type) {
7606                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7607                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7608                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7609                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7610                         return;
7611                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7612                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7613                         return;
7614                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7615                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7616                         return;
7617                 default:
7618                         break;
7619                 }
7620         }
7621         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7622                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7623                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7624                 /* Only one vlan_tag bit can be set. */
7625                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7626                 return;
7627         }
7628         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7629                  rte_be_to_cpu_16(vlan_m->inner_type));
7630         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7631                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7632 }
7633
7634 /**
7635  * Add IPV4 item to matcher and to the value.
7636  *
7637  * @param[in, out] matcher
7638  *   Flow matcher.
7639  * @param[in, out] key
7640  *   Flow matcher value.
7641  * @param[in] item
7642  *   Flow pattern to translate.
7643  * @param[in] inner
7644  *   Item is inner pattern.
7645  * @param[in] group
7646  *   The group to insert the rule.
7647  */
7648 static void
7649 flow_dv_translate_item_ipv4(void *matcher, void *key,
7650                             const struct rte_flow_item *item,
7651                             int inner, uint32_t group)
7652 {
7653         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7654         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7655         const struct rte_flow_item_ipv4 nic_mask = {
7656                 .hdr = {
7657                         .src_addr = RTE_BE32(0xffffffff),
7658                         .dst_addr = RTE_BE32(0xffffffff),
7659                         .type_of_service = 0xff,
7660                         .next_proto_id = 0xff,
7661                         .time_to_live = 0xff,
7662                 },
7663         };
7664         void *headers_m;
7665         void *headers_v;
7666         char *l24_m;
7667         char *l24_v;
7668         uint8_t tos;
7669
7670         if (inner) {
7671                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7672                                          inner_headers);
7673                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7674         } else {
7675                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7676                                          outer_headers);
7677                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7678         }
7679         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7680         if (!ipv4_v)
7681                 return;
7682         if (!ipv4_m)
7683                 ipv4_m = &nic_mask;
7684         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7685                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7686         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7687                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7688         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7689         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7690         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7691                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7692         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7693                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7694         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7695         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7696         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7697         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7698                  ipv4_m->hdr.type_of_service);
7699         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7700         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7701                  ipv4_m->hdr.type_of_service >> 2);
7702         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7703         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7704                  ipv4_m->hdr.next_proto_id);
7705         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7706                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7707         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7708                  ipv4_m->hdr.time_to_live);
7709         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7710                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7711         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7712                  !!(ipv4_m->hdr.fragment_offset));
7713         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7714                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7715 }
7716
7717 /**
7718  * Add IPV6 item to matcher and to the value.
7719  *
7720  * @param[in, out] matcher
7721  *   Flow matcher.
7722  * @param[in, out] key
7723  *   Flow matcher value.
7724  * @param[in] item
7725  *   Flow pattern to translate.
7726  * @param[in] inner
7727  *   Item is inner pattern.
7728  * @param[in] group
7729  *   The group to insert the rule.
7730  */
7731 static void
7732 flow_dv_translate_item_ipv6(void *matcher, void *key,
7733                             const struct rte_flow_item *item,
7734                             int inner, uint32_t group)
7735 {
7736         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7737         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7738         const struct rte_flow_item_ipv6 nic_mask = {
7739                 .hdr = {
7740                         .src_addr =
7741                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7742                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7743                         .dst_addr =
7744                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7745                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7746                         .vtc_flow = RTE_BE32(0xffffffff),
7747                         .proto = 0xff,
7748                         .hop_limits = 0xff,
7749                 },
7750         };
7751         void *headers_m;
7752         void *headers_v;
7753         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7754         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7755         char *l24_m;
7756         char *l24_v;
7757         uint32_t vtc_m;
7758         uint32_t vtc_v;
7759         int i;
7760         int size;
7761
7762         if (inner) {
7763                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7764                                          inner_headers);
7765                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7766         } else {
7767                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7768                                          outer_headers);
7769                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7770         }
7771         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7772         if (!ipv6_v)
7773                 return;
7774         if (!ipv6_m)
7775                 ipv6_m = &nic_mask;
7776         size = sizeof(ipv6_m->hdr.dst_addr);
7777         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7778                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7779         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7780                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7781         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7782         for (i = 0; i < size; ++i)
7783                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7784         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7785                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7786         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7787                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7788         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7789         for (i = 0; i < size; ++i)
7790                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7791         /* TOS. */
7792         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7793         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7794         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7795         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7796         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7798         /* Label. */
7799         if (inner) {
7800                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7801                          vtc_m);
7802                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7803                          vtc_v);
7804         } else {
7805                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7806                          vtc_m);
7807                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7808                          vtc_v);
7809         }
7810         /* Protocol. */
7811         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7812                  ipv6_m->hdr.proto);
7813         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7814                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7815         /* Hop limit. */
7816         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7817                  ipv6_m->hdr.hop_limits);
7818         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7819                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7820         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7821                  !!(ipv6_m->has_frag_ext));
7822         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7823                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7824 }
7825
7826 /**
7827  * Add IPV6 fragment extension item to matcher and to the value.
7828  *
7829  * @param[in, out] matcher
7830  *   Flow matcher.
7831  * @param[in, out] key
7832  *   Flow matcher value.
7833  * @param[in] item
7834  *   Flow pattern to translate.
7835  * @param[in] inner
7836  *   Item is inner pattern.
7837  */
7838 static void
7839 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7840                                      const struct rte_flow_item *item,
7841                                      int inner)
7842 {
7843         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7844         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7845         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7846                 .hdr = {
7847                         .next_header = 0xff,
7848                         .frag_data = RTE_BE16(0xffff),
7849                 },
7850         };
7851         void *headers_m;
7852         void *headers_v;
7853
7854         if (inner) {
7855                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7856                                          inner_headers);
7857                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7858         } else {
7859                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7860                                          outer_headers);
7861                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7862         }
7863         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7864         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7865         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7866         if (!ipv6_frag_ext_v)
7867                 return;
7868         if (!ipv6_frag_ext_m)
7869                 ipv6_frag_ext_m = &nic_mask;
7870         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7871                  ipv6_frag_ext_m->hdr.next_header);
7872         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7873                  ipv6_frag_ext_v->hdr.next_header &
7874                  ipv6_frag_ext_m->hdr.next_header);
7875 }
7876
7877 /**
7878  * Add TCP item to matcher and to the value.
7879  *
7880  * @param[in, out] matcher
7881  *   Flow matcher.
7882  * @param[in, out] key
7883  *   Flow matcher value.
7884  * @param[in] item
7885  *   Flow pattern to translate.
7886  * @param[in] inner
7887  *   Item is inner pattern.
7888  */
7889 static void
7890 flow_dv_translate_item_tcp(void *matcher, void *key,
7891                            const struct rte_flow_item *item,
7892                            int inner)
7893 {
7894         const struct rte_flow_item_tcp *tcp_m = item->mask;
7895         const struct rte_flow_item_tcp *tcp_v = item->spec;
7896         void *headers_m;
7897         void *headers_v;
7898
7899         if (inner) {
7900                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7901                                          inner_headers);
7902                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7903         } else {
7904                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7905                                          outer_headers);
7906                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7907         }
7908         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7909         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7910         if (!tcp_v)
7911                 return;
7912         if (!tcp_m)
7913                 tcp_m = &rte_flow_item_tcp_mask;
7914         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7915                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7916         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7917                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7918         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7919                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7920         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7921                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7922         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7923                  tcp_m->hdr.tcp_flags);
7924         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7925                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7926 }
7927
7928 /**
7929  * Add UDP item to matcher and to the value.
7930  *
7931  * @param[in, out] matcher
7932  *   Flow matcher.
7933  * @param[in, out] key
7934  *   Flow matcher value.
7935  * @param[in] item
7936  *   Flow pattern to translate.
7937  * @param[in] inner
7938  *   Item is inner pattern.
7939  */
7940 static void
7941 flow_dv_translate_item_udp(void *matcher, void *key,
7942                            const struct rte_flow_item *item,
7943                            int inner)
7944 {
7945         const struct rte_flow_item_udp *udp_m = item->mask;
7946         const struct rte_flow_item_udp *udp_v = item->spec;
7947         void *headers_m;
7948         void *headers_v;
7949
7950         if (inner) {
7951                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7952                                          inner_headers);
7953                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7954         } else {
7955                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7956                                          outer_headers);
7957                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7958         }
7959         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7960         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7961         if (!udp_v)
7962                 return;
7963         if (!udp_m)
7964                 udp_m = &rte_flow_item_udp_mask;
7965         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7966                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7967         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7968                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7969         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7970                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7971         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7972                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7973 }
7974
7975 /**
7976  * Add GRE optional Key item to matcher and to the value.
7977  *
7978  * @param[in, out] matcher
7979  *   Flow matcher.
7980  * @param[in, out] key
7981  *   Flow matcher value.
7982  * @param[in] item
7983  *   Flow pattern to translate.
7984  * @param[in] inner
7985  *   Item is inner pattern.
7986  */
7987 static void
7988 flow_dv_translate_item_gre_key(void *matcher, void *key,
7989                                    const struct rte_flow_item *item)
7990 {
7991         const rte_be32_t *key_m = item->mask;
7992         const rte_be32_t *key_v = item->spec;
7993         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7994         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7995         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7996
7997         /* GRE K bit must be on and should already be validated */
7998         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7999         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8000         if (!key_v)
8001                 return;
8002         if (!key_m)
8003                 key_m = &gre_key_default_mask;
8004         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8005                  rte_be_to_cpu_32(*key_m) >> 8);
8006         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8007                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8008         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8009                  rte_be_to_cpu_32(*key_m) & 0xFF);
8010         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8011                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8012 }
8013
8014 /**
8015  * Add GRE item to matcher and to the value.
8016  *
8017  * @param[in, out] matcher
8018  *   Flow matcher.
8019  * @param[in, out] key
8020  *   Flow matcher value.
8021  * @param[in] item
8022  *   Flow pattern to translate.
8023  * @param[in] inner
8024  *   Item is inner pattern.
8025  */
8026 static void
8027 flow_dv_translate_item_gre(void *matcher, void *key,
8028                            const struct rte_flow_item *item,
8029                            int inner)
8030 {
8031         const struct rte_flow_item_gre *gre_m = item->mask;
8032         const struct rte_flow_item_gre *gre_v = item->spec;
8033         void *headers_m;
8034         void *headers_v;
8035         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8036         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8037         struct {
8038                 union {
8039                         __extension__
8040                         struct {
8041                                 uint16_t version:3;
8042                                 uint16_t rsvd0:9;
8043                                 uint16_t s_present:1;
8044                                 uint16_t k_present:1;
8045                                 uint16_t rsvd_bit1:1;
8046                                 uint16_t c_present:1;
8047                         };
8048                         uint16_t value;
8049                 };
8050         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8051
8052         if (inner) {
8053                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8054                                          inner_headers);
8055                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8056         } else {
8057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8058                                          outer_headers);
8059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8060         }
8061         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8062         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8063         if (!gre_v)
8064                 return;
8065         if (!gre_m)
8066                 gre_m = &rte_flow_item_gre_mask;
8067         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8068                  rte_be_to_cpu_16(gre_m->protocol));
8069         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8070                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8071         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8072         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8073         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8074                  gre_crks_rsvd0_ver_m.c_present);
8075         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8076                  gre_crks_rsvd0_ver_v.c_present &
8077                  gre_crks_rsvd0_ver_m.c_present);
8078         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8079                  gre_crks_rsvd0_ver_m.k_present);
8080         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8081                  gre_crks_rsvd0_ver_v.k_present &
8082                  gre_crks_rsvd0_ver_m.k_present);
8083         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8084                  gre_crks_rsvd0_ver_m.s_present);
8085         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8086                  gre_crks_rsvd0_ver_v.s_present &
8087                  gre_crks_rsvd0_ver_m.s_present);
8088 }
8089
8090 /**
8091  * Add NVGRE item to matcher and to the value.
8092  *
8093  * @param[in, out] matcher
8094  *   Flow matcher.
8095  * @param[in, out] key
8096  *   Flow matcher value.
8097  * @param[in] item
8098  *   Flow pattern to translate.
8099  * @param[in] inner
8100  *   Item is inner pattern.
8101  */
8102 static void
8103 flow_dv_translate_item_nvgre(void *matcher, void *key,
8104                              const struct rte_flow_item *item,
8105                              int inner)
8106 {
8107         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8108         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8109         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8110         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8111         const char *tni_flow_id_m;
8112         const char *tni_flow_id_v;
8113         char *gre_key_m;
8114         char *gre_key_v;
8115         int size;
8116         int i;
8117
8118         /* For NVGRE, GRE header fields must be set with defined values. */
8119         const struct rte_flow_item_gre gre_spec = {
8120                 .c_rsvd0_ver = RTE_BE16(0x2000),
8121                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8122         };
8123         const struct rte_flow_item_gre gre_mask = {
8124                 .c_rsvd0_ver = RTE_BE16(0xB000),
8125                 .protocol = RTE_BE16(UINT16_MAX),
8126         };
8127         const struct rte_flow_item gre_item = {
8128                 .spec = &gre_spec,
8129                 .mask = &gre_mask,
8130                 .last = NULL,
8131         };
8132         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8133         if (!nvgre_v)
8134                 return;
8135         if (!nvgre_m)
8136                 nvgre_m = &rte_flow_item_nvgre_mask;
8137         tni_flow_id_m = (const char *)nvgre_m->tni;
8138         tni_flow_id_v = (const char *)nvgre_v->tni;
8139         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8140         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8141         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8142         memcpy(gre_key_m, tni_flow_id_m, size);
8143         for (i = 0; i < size; ++i)
8144                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8145 }
8146
8147 /**
8148  * Add VXLAN item to matcher and to the value.
8149  *
8150  * @param[in, out] matcher
8151  *   Flow matcher.
8152  * @param[in, out] key
8153  *   Flow matcher value.
8154  * @param[in] item
8155  *   Flow pattern to translate.
8156  * @param[in] inner
8157  *   Item is inner pattern.
8158  */
8159 static void
8160 flow_dv_translate_item_vxlan(void *matcher, void *key,
8161                              const struct rte_flow_item *item,
8162                              int inner)
8163 {
8164         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8165         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8166         void *headers_m;
8167         void *headers_v;
8168         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8169         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8170         char *vni_m;
8171         char *vni_v;
8172         uint16_t dport;
8173         int size;
8174         int i;
8175
8176         if (inner) {
8177                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8178                                          inner_headers);
8179                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8180         } else {
8181                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8182                                          outer_headers);
8183                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8184         }
8185         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8186                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8187         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8188                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8189                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8190         }
8191         if (!vxlan_v)
8192                 return;
8193         if (!vxlan_m)
8194                 vxlan_m = &rte_flow_item_vxlan_mask;
8195         size = sizeof(vxlan_m->vni);
8196         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8197         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8198         memcpy(vni_m, vxlan_m->vni, size);
8199         for (i = 0; i < size; ++i)
8200                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8201 }
8202
8203 /**
8204  * Add VXLAN-GPE item to matcher and to the value.
8205  *
8206  * @param[in, out] matcher
8207  *   Flow matcher.
8208  * @param[in, out] key
8209  *   Flow matcher value.
8210  * @param[in] item
8211  *   Flow pattern to translate.
8212  * @param[in] inner
8213  *   Item is inner pattern.
8214  */
8215
8216 static void
8217 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8218                                  const struct rte_flow_item *item, int inner)
8219 {
8220         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8221         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8222         void *headers_m;
8223         void *headers_v;
8224         void *misc_m =
8225                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8226         void *misc_v =
8227                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8228         char *vni_m;
8229         char *vni_v;
8230         uint16_t dport;
8231         int size;
8232         int i;
8233         uint8_t flags_m = 0xff;
8234         uint8_t flags_v = 0xc;
8235
8236         if (inner) {
8237                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8238                                          inner_headers);
8239                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8240         } else {
8241                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8242                                          outer_headers);
8243                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8244         }
8245         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8246                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8247         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8248                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8249                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8250         }
8251         if (!vxlan_v)
8252                 return;
8253         if (!vxlan_m)
8254                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8255         size = sizeof(vxlan_m->vni);
8256         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8257         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8258         memcpy(vni_m, vxlan_m->vni, size);
8259         for (i = 0; i < size; ++i)
8260                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8261         if (vxlan_m->flags) {
8262                 flags_m = vxlan_m->flags;
8263                 flags_v = vxlan_v->flags;
8264         }
8265         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8266         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8267         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8268                  vxlan_m->protocol);
8269         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8270                  vxlan_v->protocol);
8271 }
8272
8273 /**
8274  * Add Geneve item to matcher and to the value.
8275  *
8276  * @param[in, out] matcher
8277  *   Flow matcher.
8278  * @param[in, out] key
8279  *   Flow matcher value.
8280  * @param[in] item
8281  *   Flow pattern to translate.
8282  * @param[in] inner
8283  *   Item is inner pattern.
8284  */
8285
8286 static void
8287 flow_dv_translate_item_geneve(void *matcher, void *key,
8288                               const struct rte_flow_item *item, int inner)
8289 {
8290         const struct rte_flow_item_geneve *geneve_m = item->mask;
8291         const struct rte_flow_item_geneve *geneve_v = item->spec;
8292         void *headers_m;
8293         void *headers_v;
8294         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8295         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8296         uint16_t dport;
8297         uint16_t gbhdr_m;
8298         uint16_t gbhdr_v;
8299         char *vni_m;
8300         char *vni_v;
8301         size_t size, i;
8302
8303         if (inner) {
8304                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8305                                          inner_headers);
8306                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8307         } else {
8308                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8309                                          outer_headers);
8310                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8311         }
8312         dport = MLX5_UDP_PORT_GENEVE;
8313         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8314                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8315                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8316         }
8317         if (!geneve_v)
8318                 return;
8319         if (!geneve_m)
8320                 geneve_m = &rte_flow_item_geneve_mask;
8321         size = sizeof(geneve_m->vni);
8322         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8323         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8324         memcpy(vni_m, geneve_m->vni, size);
8325         for (i = 0; i < size; ++i)
8326                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8327         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8328                  rte_be_to_cpu_16(geneve_m->protocol));
8329         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8330                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8331         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8332         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8333         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8334                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8335         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8336                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8337         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8338                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8339         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8340                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8341                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8342 }
8343
8344 /**
8345  * Create Geneve TLV option resource.
8346  *
8347  * @param dev[in, out]
8348  *   Pointer to rte_eth_dev structure.
8349  * @param[in, out] tag_be24
8350  *   Tag value in big endian then R-shift 8.
8351  * @parm[in, out] dev_flow
8352  *   Pointer to the dev_flow.
8353  * @param[out] error
8354  *   pointer to error structure.
8355  *
8356  * @return
8357  *   0 on success otherwise -errno and errno is set.
8358  */
8359
8360 int
8361 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8362                                              const struct rte_flow_item *item,
8363                                              struct rte_flow_error *error)
8364 {
8365         struct mlx5_priv *priv = dev->data->dev_private;
8366         struct mlx5_dev_ctx_shared *sh = priv->sh;
8367         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8368                         sh->geneve_tlv_option_resource;
8369         struct mlx5_devx_obj *obj;
8370         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8371         int ret = 0;
8372
8373         if (!geneve_opt_v)
8374                 return -1;
8375         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8376         if (geneve_opt_resource != NULL) {
8377                 if (geneve_opt_resource->option_class ==
8378                         geneve_opt_v->option_class &&
8379                         geneve_opt_resource->option_type ==
8380                         geneve_opt_v->option_type &&
8381                         geneve_opt_resource->length ==
8382                         geneve_opt_v->option_len) {
8383                         /* We already have GENVE TLV option obj allocated. */
8384                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8385                                            __ATOMIC_RELAXED);
8386                 } else {
8387                         ret = rte_flow_error_set(error, ENOMEM,
8388                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8389                                 "Only one GENEVE TLV option supported");
8390                         goto exit;
8391                 }
8392         } else {
8393                 /* Create a GENEVE TLV object and resource. */
8394                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8395                                 geneve_opt_v->option_class,
8396                                 geneve_opt_v->option_type,
8397                                 geneve_opt_v->option_len);
8398                 if (!obj) {
8399                         ret = rte_flow_error_set(error, ENODATA,
8400                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8401                                 "Failed to create GENEVE TLV Devx object");
8402                         goto exit;
8403                 }
8404                 sh->geneve_tlv_option_resource =
8405                                 mlx5_malloc(MLX5_MEM_ZERO,
8406                                                 sizeof(*geneve_opt_resource),
8407                                                 0, SOCKET_ID_ANY);
8408                 if (!sh->geneve_tlv_option_resource) {
8409                         claim_zero(mlx5_devx_cmd_destroy(obj));
8410                         ret = rte_flow_error_set(error, ENOMEM,
8411                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8412                                 "GENEVE TLV object memory allocation failed");
8413                         goto exit;
8414                 }
8415                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8416                 geneve_opt_resource->obj = obj;
8417                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8418                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8419                 geneve_opt_resource->length = geneve_opt_v->option_len;
8420                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8421                                 __ATOMIC_RELAXED);
8422         }
8423 exit:
8424         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8425         return ret;
8426 }
8427
8428 /**
8429  * Add Geneve TLV option item to matcher.
8430  *
8431  * @param[in, out] dev
8432  *   Pointer to rte_eth_dev structure.
8433  * @param[in, out] matcher
8434  *   Flow matcher.
8435  * @param[in, out] key
8436  *   Flow matcher value.
8437  * @param[in] item
8438  *   Flow pattern to translate.
8439  * @param[out] error
8440  *   Pointer to error structure.
8441  */
8442 static int
8443 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8444                                   void *key, const struct rte_flow_item *item,
8445                                   struct rte_flow_error *error)
8446 {
8447         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8448         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8449         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8450         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8451         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8452                         misc_parameters_3);
8453         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8454         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8455         int ret = 0;
8456
8457         if (!geneve_opt_v)
8458                 return -1;
8459         if (!geneve_opt_m)
8460                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8461         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8462                                                            error);
8463         if (ret) {
8464                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8465                 return ret;
8466         }
8467         /*
8468          * Set the option length in GENEVE header if not requested.
8469          * The GENEVE TLV option length is expressed by the option length field
8470          * in the GENEVE header.
8471          * If the option length was not requested but the GENEVE TLV option item
8472          * is present we set the option length field implicitly.
8473          */
8474         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8475                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8476                          MLX5_GENEVE_OPTLEN_MASK);
8477                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8478                          geneve_opt_v->option_len + 1);
8479         }
8480         /* Set the data. */
8481         if (geneve_opt_v->data) {
8482                 memcpy(&opt_data_key, geneve_opt_v->data,
8483                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8484                                 sizeof(opt_data_key)));
8485                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8486                                 sizeof(opt_data_key));
8487                 memcpy(&opt_data_mask, geneve_opt_m->data,
8488                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8489                                 sizeof(opt_data_mask)));
8490                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8491                                 sizeof(opt_data_mask));
8492                 MLX5_SET(fte_match_set_misc3, misc3_m,
8493                                 geneve_tlv_option_0_data,
8494                                 rte_be_to_cpu_32(opt_data_mask));
8495                 MLX5_SET(fte_match_set_misc3, misc3_v,
8496                                 geneve_tlv_option_0_data,
8497                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8498         }
8499         return ret;
8500 }
8501
8502 /**
8503  * Add MPLS item to matcher and to the value.
8504  *
8505  * @param[in, out] matcher
8506  *   Flow matcher.
8507  * @param[in, out] key
8508  *   Flow matcher value.
8509  * @param[in] item
8510  *   Flow pattern to translate.
8511  * @param[in] prev_layer
8512  *   The protocol layer indicated in previous item.
8513  * @param[in] inner
8514  *   Item is inner pattern.
8515  */
8516 static void
8517 flow_dv_translate_item_mpls(void *matcher, void *key,
8518                             const struct rte_flow_item *item,
8519                             uint64_t prev_layer,
8520                             int inner)
8521 {
8522         const uint32_t *in_mpls_m = item->mask;
8523         const uint32_t *in_mpls_v = item->spec;
8524         uint32_t *out_mpls_m = 0;
8525         uint32_t *out_mpls_v = 0;
8526         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8527         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8528         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8529                                      misc_parameters_2);
8530         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8531         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8532         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8533
8534         switch (prev_layer) {
8535         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8536                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8537                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8538                          MLX5_UDP_PORT_MPLS);
8539                 break;
8540         case MLX5_FLOW_LAYER_GRE:
8541                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8542                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8543                          RTE_ETHER_TYPE_MPLS);
8544                 break;
8545         default:
8546                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8547                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8548                          IPPROTO_MPLS);
8549                 break;
8550         }
8551         if (!in_mpls_v)
8552                 return;
8553         if (!in_mpls_m)
8554                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8555         switch (prev_layer) {
8556         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8557                 out_mpls_m =
8558                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8559                                                  outer_first_mpls_over_udp);
8560                 out_mpls_v =
8561                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8562                                                  outer_first_mpls_over_udp);
8563                 break;
8564         case MLX5_FLOW_LAYER_GRE:
8565                 out_mpls_m =
8566                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8567                                                  outer_first_mpls_over_gre);
8568                 out_mpls_v =
8569                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8570                                                  outer_first_mpls_over_gre);
8571                 break;
8572         default:
8573                 /* Inner MPLS not over GRE is not supported. */
8574                 if (!inner) {
8575                         out_mpls_m =
8576                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8577                                                          misc2_m,
8578                                                          outer_first_mpls);
8579                         out_mpls_v =
8580                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8581                                                          misc2_v,
8582                                                          outer_first_mpls);
8583                 }
8584                 break;
8585         }
8586         if (out_mpls_m && out_mpls_v) {
8587                 *out_mpls_m = *in_mpls_m;
8588                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8589         }
8590 }
8591
8592 /**
8593  * Add metadata register item to matcher
8594  *
8595  * @param[in, out] matcher
8596  *   Flow matcher.
8597  * @param[in, out] key
8598  *   Flow matcher value.
8599  * @param[in] reg_type
8600  *   Type of device metadata register
8601  * @param[in] value
8602  *   Register value
8603  * @param[in] mask
8604  *   Register mask
8605  */
8606 static void
8607 flow_dv_match_meta_reg(void *matcher, void *key,
8608                        enum modify_reg reg_type,
8609                        uint32_t data, uint32_t mask)
8610 {
8611         void *misc2_m =
8612                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8613         void *misc2_v =
8614                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8615         uint32_t temp;
8616
8617         data &= mask;
8618         switch (reg_type) {
8619         case REG_A:
8620                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8621                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8622                 break;
8623         case REG_B:
8624                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8625                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8626                 break;
8627         case REG_C_0:
8628                 /*
8629                  * The metadata register C0 field might be divided into
8630                  * source vport index and META item value, we should set
8631                  * this field according to specified mask, not as whole one.
8632                  */
8633                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8634                 temp |= mask;
8635                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8636                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8637                 temp &= ~mask;
8638                 temp |= data;
8639                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8640                 break;
8641         case REG_C_1:
8642                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8643                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8644                 break;
8645         case REG_C_2:
8646                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8647                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8648                 break;
8649         case REG_C_3:
8650                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8651                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8652                 break;
8653         case REG_C_4:
8654                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8655                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8656                 break;
8657         case REG_C_5:
8658                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8659                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8660                 break;
8661         case REG_C_6:
8662                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8663                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8664                 break;
8665         case REG_C_7:
8666                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8667                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8668                 break;
8669         default:
8670                 MLX5_ASSERT(false);
8671                 break;
8672         }
8673 }
8674
8675 /**
8676  * Add MARK item to matcher
8677  *
8678  * @param[in] dev
8679  *   The device to configure through.
8680  * @param[in, out] matcher
8681  *   Flow matcher.
8682  * @param[in, out] key
8683  *   Flow matcher value.
8684  * @param[in] item
8685  *   Flow pattern to translate.
8686  */
8687 static void
8688 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8689                             void *matcher, void *key,
8690                             const struct rte_flow_item *item)
8691 {
8692         struct mlx5_priv *priv = dev->data->dev_private;
8693         const struct rte_flow_item_mark *mark;
8694         uint32_t value;
8695         uint32_t mask;
8696
8697         mark = item->mask ? (const void *)item->mask :
8698                             &rte_flow_item_mark_mask;
8699         mask = mark->id & priv->sh->dv_mark_mask;
8700         mark = (const void *)item->spec;
8701         MLX5_ASSERT(mark);
8702         value = mark->id & priv->sh->dv_mark_mask & mask;
8703         if (mask) {
8704                 enum modify_reg reg;
8705
8706                 /* Get the metadata register index for the mark. */
8707                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8708                 MLX5_ASSERT(reg > 0);
8709                 if (reg == REG_C_0) {
8710                         struct mlx5_priv *priv = dev->data->dev_private;
8711                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8712                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8713
8714                         mask &= msk_c0;
8715                         mask <<= shl_c0;
8716                         value <<= shl_c0;
8717                 }
8718                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8719         }
8720 }
8721
8722 /**
8723  * Add META item to matcher
8724  *
8725  * @param[in] dev
8726  *   The devich to configure through.
8727  * @param[in, out] matcher
8728  *   Flow matcher.
8729  * @param[in, out] key
8730  *   Flow matcher value.
8731  * @param[in] attr
8732  *   Attributes of flow that includes this item.
8733  * @param[in] item
8734  *   Flow pattern to translate.
8735  */
8736 static void
8737 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8738                             void *matcher, void *key,
8739                             const struct rte_flow_attr *attr,
8740                             const struct rte_flow_item *item)
8741 {
8742         const struct rte_flow_item_meta *meta_m;
8743         const struct rte_flow_item_meta *meta_v;
8744
8745         meta_m = (const void *)item->mask;
8746         if (!meta_m)
8747                 meta_m = &rte_flow_item_meta_mask;
8748         meta_v = (const void *)item->spec;
8749         if (meta_v) {
8750                 int reg;
8751                 uint32_t value = meta_v->data;
8752                 uint32_t mask = meta_m->data;
8753
8754                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8755                 if (reg < 0)
8756                         return;
8757                 MLX5_ASSERT(reg != REG_NON);
8758                 /*
8759                  * In datapath code there is no endianness
8760                  * coversions for perfromance reasons, all
8761                  * pattern conversions are done in rte_flow.
8762                  */
8763                 value = rte_cpu_to_be_32(value);
8764                 mask = rte_cpu_to_be_32(mask);
8765                 if (reg == REG_C_0) {
8766                         struct mlx5_priv *priv = dev->data->dev_private;
8767                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8768                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8769 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8770                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8771
8772                         value >>= shr_c0;
8773                         mask >>= shr_c0;
8774 #endif
8775                         value <<= shl_c0;
8776                         mask <<= shl_c0;
8777                         MLX5_ASSERT(msk_c0);
8778                         MLX5_ASSERT(!(~msk_c0 & mask));
8779                 }
8780                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8781         }
8782 }
8783
8784 /**
8785  * Add vport metadata Reg C0 item to matcher
8786  *
8787  * @param[in, out] matcher
8788  *   Flow matcher.
8789  * @param[in, out] key
8790  *   Flow matcher value.
8791  * @param[in] reg
8792  *   Flow pattern to translate.
8793  */
8794 static void
8795 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8796                                   uint32_t value, uint32_t mask)
8797 {
8798         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8799 }
8800
8801 /**
8802  * Add tag item to matcher
8803  *
8804  * @param[in] dev
8805  *   The devich to configure through.
8806  * @param[in, out] matcher
8807  *   Flow matcher.
8808  * @param[in, out] key
8809  *   Flow matcher value.
8810  * @param[in] item
8811  *   Flow pattern to translate.
8812  */
8813 static void
8814 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8815                                 void *matcher, void *key,
8816                                 const struct rte_flow_item *item)
8817 {
8818         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8819         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8820         uint32_t mask, value;
8821
8822         MLX5_ASSERT(tag_v);
8823         value = tag_v->data;
8824         mask = tag_m ? tag_m->data : UINT32_MAX;
8825         if (tag_v->id == REG_C_0) {
8826                 struct mlx5_priv *priv = dev->data->dev_private;
8827                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8828                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8829
8830                 mask &= msk_c0;
8831                 mask <<= shl_c0;
8832                 value <<= shl_c0;
8833         }
8834         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8835 }
8836
8837 /**
8838  * Add TAG item to matcher
8839  *
8840  * @param[in] dev
8841  *   The devich to configure through.
8842  * @param[in, out] matcher
8843  *   Flow matcher.
8844  * @param[in, out] key
8845  *   Flow matcher value.
8846  * @param[in] item
8847  *   Flow pattern to translate.
8848  */
8849 static void
8850 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8851                            void *matcher, void *key,
8852                            const struct rte_flow_item *item)
8853 {
8854         const struct rte_flow_item_tag *tag_v = item->spec;
8855         const struct rte_flow_item_tag *tag_m = item->mask;
8856         enum modify_reg reg;
8857
8858         MLX5_ASSERT(tag_v);
8859         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8860         /* Get the metadata register index for the tag. */
8861         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8862         MLX5_ASSERT(reg > 0);
8863         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8864 }
8865
8866 /**
8867  * Add source vport match to the specified matcher.
8868  *
8869  * @param[in, out] matcher
8870  *   Flow matcher.
8871  * @param[in, out] key
8872  *   Flow matcher value.
8873  * @param[in] port
8874  *   Source vport value to match
8875  * @param[in] mask
8876  *   Mask
8877  */
8878 static void
8879 flow_dv_translate_item_source_vport(void *matcher, void *key,
8880                                     int16_t port, uint16_t mask)
8881 {
8882         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8883         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8884
8885         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8886         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8887 }
8888
8889 /**
8890  * Translate port-id item to eswitch match on  port-id.
8891  *
8892  * @param[in] dev
8893  *   The devich to configure through.
8894  * @param[in, out] matcher
8895  *   Flow matcher.
8896  * @param[in, out] key
8897  *   Flow matcher value.
8898  * @param[in] item
8899  *   Flow pattern to translate.
8900  * @param[in]
8901  *   Flow attributes.
8902  *
8903  * @return
8904  *   0 on success, a negative errno value otherwise.
8905  */
8906 static int
8907 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8908                                void *key, const struct rte_flow_item *item,
8909                                const struct rte_flow_attr *attr)
8910 {
8911         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8912         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8913         struct mlx5_priv *priv;
8914         uint16_t mask, id;
8915
8916         mask = pid_m ? pid_m->id : 0xffff;
8917         id = pid_v ? pid_v->id : dev->data->port_id;
8918         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8919         if (!priv)
8920                 return -rte_errno;
8921         /*
8922          * Translate to vport field or to metadata, depending on mode.
8923          * Kernel can use either misc.source_port or half of C0 metadata
8924          * register.
8925          */
8926         if (priv->vport_meta_mask) {
8927                 /*
8928                  * Provide the hint for SW steering library
8929                  * to insert the flow into ingress domain and
8930                  * save the extra vport match.
8931                  */
8932                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8933                     priv->pf_bond < 0 && attr->transfer)
8934                         flow_dv_translate_item_source_vport
8935                                 (matcher, key, priv->vport_id, mask);
8936                 /*
8937                  * We should always set the vport metadata register,
8938                  * otherwise the SW steering library can drop
8939                  * the rule if wire vport metadata value is not zero,
8940                  * it depends on kernel configuration.
8941                  */
8942                 flow_dv_translate_item_meta_vport(matcher, key,
8943                                                   priv->vport_meta_tag,
8944                                                   priv->vport_meta_mask);
8945         } else {
8946                 flow_dv_translate_item_source_vport(matcher, key,
8947                                                     priv->vport_id, mask);
8948         }
8949         return 0;
8950 }
8951
8952 /**
8953  * Add ICMP6 item to matcher and to the value.
8954  *
8955  * @param[in, out] matcher
8956  *   Flow matcher.
8957  * @param[in, out] key
8958  *   Flow matcher value.
8959  * @param[in] item
8960  *   Flow pattern to translate.
8961  * @param[in] inner
8962  *   Item is inner pattern.
8963  */
8964 static void
8965 flow_dv_translate_item_icmp6(void *matcher, void *key,
8966                               const struct rte_flow_item *item,
8967                               int inner)
8968 {
8969         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8970         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8971         void *headers_m;
8972         void *headers_v;
8973         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8974                                      misc_parameters_3);
8975         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8976         if (inner) {
8977                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8978                                          inner_headers);
8979                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8980         } else {
8981                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8982                                          outer_headers);
8983                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8984         }
8985         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8986         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8987         if (!icmp6_v)
8988                 return;
8989         if (!icmp6_m)
8990                 icmp6_m = &rte_flow_item_icmp6_mask;
8991         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8992         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8993                  icmp6_v->type & icmp6_m->type);
8994         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8995         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8996                  icmp6_v->code & icmp6_m->code);
8997 }
8998
8999 /**
9000  * Add ICMP item to matcher and to the value.
9001  *
9002  * @param[in, out] matcher
9003  *   Flow matcher.
9004  * @param[in, out] key
9005  *   Flow matcher value.
9006  * @param[in] item
9007  *   Flow pattern to translate.
9008  * @param[in] inner
9009  *   Item is inner pattern.
9010  */
9011 static void
9012 flow_dv_translate_item_icmp(void *matcher, void *key,
9013                             const struct rte_flow_item *item,
9014                             int inner)
9015 {
9016         const struct rte_flow_item_icmp *icmp_m = item->mask;
9017         const struct rte_flow_item_icmp *icmp_v = item->spec;
9018         uint32_t icmp_header_data_m = 0;
9019         uint32_t icmp_header_data_v = 0;
9020         void *headers_m;
9021         void *headers_v;
9022         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9023                                      misc_parameters_3);
9024         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9025         if (inner) {
9026                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9027                                          inner_headers);
9028                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9029         } else {
9030                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9031                                          outer_headers);
9032                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9033         }
9034         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9035         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9036         if (!icmp_v)
9037                 return;
9038         if (!icmp_m)
9039                 icmp_m = &rte_flow_item_icmp_mask;
9040         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9041                  icmp_m->hdr.icmp_type);
9042         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9043                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9044         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9045                  icmp_m->hdr.icmp_code);
9046         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9047                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9048         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9049         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9050         if (icmp_header_data_m) {
9051                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9052                 icmp_header_data_v |=
9053                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9054                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9055                          icmp_header_data_m);
9056                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9057                          icmp_header_data_v & icmp_header_data_m);
9058         }
9059 }
9060
9061 /**
9062  * Add GTP item to matcher and to the value.
9063  *
9064  * @param[in, out] matcher
9065  *   Flow matcher.
9066  * @param[in, out] key
9067  *   Flow matcher value.
9068  * @param[in] item
9069  *   Flow pattern to translate.
9070  * @param[in] inner
9071  *   Item is inner pattern.
9072  */
9073 static void
9074 flow_dv_translate_item_gtp(void *matcher, void *key,
9075                            const struct rte_flow_item *item, int inner)
9076 {
9077         const struct rte_flow_item_gtp *gtp_m = item->mask;
9078         const struct rte_flow_item_gtp *gtp_v = item->spec;
9079         void *headers_m;
9080         void *headers_v;
9081         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9082                                      misc_parameters_3);
9083         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9084         uint16_t dport = RTE_GTPU_UDP_PORT;
9085
9086         if (inner) {
9087                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9088                                          inner_headers);
9089                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9090         } else {
9091                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9092                                          outer_headers);
9093                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9094         }
9095         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9096                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9097                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9098         }
9099         if (!gtp_v)
9100                 return;
9101         if (!gtp_m)
9102                 gtp_m = &rte_flow_item_gtp_mask;
9103         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9104                  gtp_m->v_pt_rsv_flags);
9105         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9106                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9107         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9108         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9109                  gtp_v->msg_type & gtp_m->msg_type);
9110         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9111                  rte_be_to_cpu_32(gtp_m->teid));
9112         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9113                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9114 }
9115
9116 /**
9117  * Add GTP PSC item to matcher.
9118  *
9119  * @param[in, out] matcher
9120  *   Flow matcher.
9121  * @param[in, out] key
9122  *   Flow matcher value.
9123  * @param[in] item
9124  *   Flow pattern to translate.
9125  */
9126 static int
9127 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9128                                const struct rte_flow_item *item)
9129 {
9130         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9131         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9132         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9133                         misc_parameters_3);
9134         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9135         union {
9136                 uint32_t w32;
9137                 struct {
9138                         uint16_t seq_num;
9139                         uint8_t npdu_num;
9140                         uint8_t next_ext_header_type;
9141                 };
9142         } dw_2;
9143         uint8_t gtp_flags;
9144
9145         /* Always set E-flag match on one, regardless of GTP item settings. */
9146         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9147         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9148         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9149         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9150         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9151         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9152         /*Set next extension header type. */
9153         dw_2.seq_num = 0;
9154         dw_2.npdu_num = 0;
9155         dw_2.next_ext_header_type = 0xff;
9156         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9157                  rte_cpu_to_be_32(dw_2.w32));
9158         dw_2.seq_num = 0;
9159         dw_2.npdu_num = 0;
9160         dw_2.next_ext_header_type = 0x85;
9161         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9162                  rte_cpu_to_be_32(dw_2.w32));
9163         if (gtp_psc_v) {
9164                 union {
9165                         uint32_t w32;
9166                         struct {
9167                                 uint8_t len;
9168                                 uint8_t type_flags;
9169                                 uint8_t qfi;
9170                                 uint8_t reserved;
9171                         };
9172                 } dw_0;
9173
9174                 /*Set extension header PDU type and Qos. */
9175                 if (!gtp_psc_m)
9176                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9177                 dw_0.w32 = 0;
9178                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9179                 dw_0.qfi = gtp_psc_m->qfi;
9180                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9181                          rte_cpu_to_be_32(dw_0.w32));
9182                 dw_0.w32 = 0;
9183                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9184                                                         gtp_psc_m->pdu_type);
9185                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9186                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9187                          rte_cpu_to_be_32(dw_0.w32));
9188         }
9189         return 0;
9190 }
9191
9192 /**
9193  * Add eCPRI item to matcher and to the value.
9194  *
9195  * @param[in] dev
9196  *   The devich to configure through.
9197  * @param[in, out] matcher
9198  *   Flow matcher.
9199  * @param[in, out] key
9200  *   Flow matcher value.
9201  * @param[in] item
9202  *   Flow pattern to translate.
9203  * @param[in] samples
9204  *   Sample IDs to be used in the matching.
9205  */
9206 static void
9207 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9208                              void *key, const struct rte_flow_item *item)
9209 {
9210         struct mlx5_priv *priv = dev->data->dev_private;
9211         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9212         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9213         struct rte_ecpri_common_hdr common;
9214         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9215                                      misc_parameters_4);
9216         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9217         uint32_t *samples;
9218         void *dw_m;
9219         void *dw_v;
9220
9221         if (!ecpri_v)
9222                 return;
9223         if (!ecpri_m)
9224                 ecpri_m = &rte_flow_item_ecpri_mask;
9225         /*
9226          * Maximal four DW samples are supported in a single matching now.
9227          * Two are used now for a eCPRI matching:
9228          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9229          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9230          *    if any.
9231          */
9232         if (!ecpri_m->hdr.common.u32)
9233                 return;
9234         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9235         /* Need to take the whole DW as the mask to fill the entry. */
9236         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9237                             prog_sample_field_value_0);
9238         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9239                             prog_sample_field_value_0);
9240         /* Already big endian (network order) in the header. */
9241         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9242         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9243         /* Sample#0, used for matching type, offset 0. */
9244         MLX5_SET(fte_match_set_misc4, misc4_m,
9245                  prog_sample_field_id_0, samples[0]);
9246         /* It makes no sense to set the sample ID in the mask field. */
9247         MLX5_SET(fte_match_set_misc4, misc4_v,
9248                  prog_sample_field_id_0, samples[0]);
9249         /*
9250          * Checking if message body part needs to be matched.
9251          * Some wildcard rules only matching type field should be supported.
9252          */
9253         if (ecpri_m->hdr.dummy[0]) {
9254                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9255                 switch (common.type) {
9256                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9257                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9258                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9259                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9260                                             prog_sample_field_value_1);
9261                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9262                                             prog_sample_field_value_1);
9263                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9264                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9265                                             ecpri_m->hdr.dummy[0];
9266                         /* Sample#1, to match message body, offset 4. */
9267                         MLX5_SET(fte_match_set_misc4, misc4_m,
9268                                  prog_sample_field_id_1, samples[1]);
9269                         MLX5_SET(fte_match_set_misc4, misc4_v,
9270                                  prog_sample_field_id_1, samples[1]);
9271                         break;
9272                 default:
9273                         /* Others, do not match any sample ID. */
9274                         break;
9275                 }
9276         }
9277 }
9278
9279 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9280
9281 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9282         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9283                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9284
9285 /**
9286  * Calculate flow matcher enable bitmap.
9287  *
9288  * @param match_criteria
9289  *   Pointer to flow matcher criteria.
9290  *
9291  * @return
9292  *   Bitmap of enabled fields.
9293  */
9294 static uint8_t
9295 flow_dv_matcher_enable(uint32_t *match_criteria)
9296 {
9297         uint8_t match_criteria_enable;
9298
9299         match_criteria_enable =
9300                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9301                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9302         match_criteria_enable |=
9303                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9304                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9305         match_criteria_enable |=
9306                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9307                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9308         match_criteria_enable |=
9309                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9310                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9311         match_criteria_enable |=
9312                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9313                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9314         match_criteria_enable |=
9315                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9316                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9317         return match_criteria_enable;
9318 }
9319
9320 struct mlx5_hlist_entry *
9321 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9322 {
9323         struct mlx5_dev_ctx_shared *sh = list->ctx;
9324         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9325         struct rte_eth_dev *dev = ctx->dev;
9326         struct mlx5_flow_tbl_data_entry *tbl_data;
9327         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9328         struct rte_flow_error *error = ctx->error;
9329         union mlx5_flow_tbl_key key = { .v64 = key64 };
9330         struct mlx5_flow_tbl_resource *tbl;
9331         void *domain;
9332         uint32_t idx = 0;
9333         int ret;
9334
9335         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9336         if (!tbl_data) {
9337                 rte_flow_error_set(error, ENOMEM,
9338                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9339                                    NULL,
9340                                    "cannot allocate flow table data entry");
9341                 return NULL;
9342         }
9343         tbl_data->idx = idx;
9344         tbl_data->tunnel = tt_prm->tunnel;
9345         tbl_data->group_id = tt_prm->group_id;
9346         tbl_data->external = !!tt_prm->external;
9347         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9348         tbl_data->is_egress = !!key.is_egress;
9349         tbl_data->is_transfer = !!key.is_fdb;
9350         tbl_data->dummy = !!key.dummy;
9351         tbl_data->level = key.level;
9352         tbl_data->id = key.id;
9353         tbl = &tbl_data->tbl;
9354         if (key.dummy)
9355                 return &tbl_data->entry;
9356         if (key.is_fdb)
9357                 domain = sh->fdb_domain;
9358         else if (key.is_egress)
9359                 domain = sh->tx_domain;
9360         else
9361                 domain = sh->rx_domain;
9362         ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
9363         if (ret) {
9364                 rte_flow_error_set(error, ENOMEM,
9365                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9366                                    NULL, "cannot create flow table object");
9367                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9368                 return NULL;
9369         }
9370         if (key.level != 0) {
9371                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9372                                         (tbl->obj, &tbl_data->jump.action);
9373                 if (ret) {
9374                         rte_flow_error_set(error, ENOMEM,
9375                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9376                                            NULL,
9377                                            "cannot create flow jump action");
9378                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9379                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9380                         return NULL;
9381                 }
9382         }
9383         MKSTR(matcher_name, "%s_%s_%u_%u_matcher_cache",
9384               key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
9385               key.level, key.id);
9386         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9387                              flow_dv_matcher_create_cb,
9388                              flow_dv_matcher_match_cb,
9389                              flow_dv_matcher_remove_cb);
9390         return &tbl_data->entry;
9391 }
9392
9393 int
9394 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9395                      struct mlx5_hlist_entry *entry, uint64_t key64,
9396                      void *cb_ctx __rte_unused)
9397 {
9398         struct mlx5_flow_tbl_data_entry *tbl_data =
9399                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9400         union mlx5_flow_tbl_key key = { .v64 = key64 };
9401
9402         return tbl_data->level != key.level ||
9403                tbl_data->id != key.id ||
9404                tbl_data->dummy != key.dummy ||
9405                tbl_data->is_transfer != !!key.is_fdb ||
9406                tbl_data->is_egress != !!key.is_egress;
9407 }
9408
9409 /**
9410  * Get a flow table.
9411  *
9412  * @param[in, out] dev
9413  *   Pointer to rte_eth_dev structure.
9414  * @param[in] table_level
9415  *   Table level to use.
9416  * @param[in] egress
9417  *   Direction of the table.
9418  * @param[in] transfer
9419  *   E-Switch or NIC flow.
9420  * @param[in] dummy
9421  *   Dummy entry for dv API.
9422  * @param[in] table_id
9423  *   Table id to use.
9424  * @param[out] error
9425  *   pointer to error structure.
9426  *
9427  * @return
9428  *   Returns tables resource based on the index, NULL in case of failed.
9429  */
9430 struct mlx5_flow_tbl_resource *
9431 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9432                          uint32_t table_level, uint8_t egress,
9433                          uint8_t transfer,
9434                          bool external,
9435                          const struct mlx5_flow_tunnel *tunnel,
9436                          uint32_t group_id, uint8_t dummy,
9437                          uint32_t table_id,
9438                          struct rte_flow_error *error)
9439 {
9440         struct mlx5_priv *priv = dev->data->dev_private;
9441         union mlx5_flow_tbl_key table_key = {
9442                 {
9443                         .level = table_level,
9444                         .id = table_id,
9445                         .reserved = 0,
9446                         .dummy = !!dummy,
9447                         .is_fdb = !!transfer,
9448                         .is_egress = !!egress,
9449                 }
9450         };
9451         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9452                 .tunnel = tunnel,
9453                 .group_id = group_id,
9454                 .external = external,
9455         };
9456         struct mlx5_flow_cb_ctx ctx = {
9457                 .dev = dev,
9458                 .error = error,
9459                 .data = &tt_prm,
9460         };
9461         struct mlx5_hlist_entry *entry;
9462         struct mlx5_flow_tbl_data_entry *tbl_data;
9463
9464         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9465         if (!entry) {
9466                 rte_flow_error_set(error, ENOMEM,
9467                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9468                                    "cannot get table");
9469                 return NULL;
9470         }
9471         DRV_LOG(DEBUG, "table_level %u table_id %u "
9472                 "tunnel %u group %u registered.",
9473                 table_level, table_id,
9474                 tunnel ? tunnel->tunnel_id : 0, group_id);
9475         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9476         return &tbl_data->tbl;
9477 }
9478
9479 void
9480 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9481                       struct mlx5_hlist_entry *entry)
9482 {
9483         struct mlx5_dev_ctx_shared *sh = list->ctx;
9484         struct mlx5_flow_tbl_data_entry *tbl_data =
9485                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9486
9487         MLX5_ASSERT(entry && sh);
9488         if (tbl_data->jump.action)
9489                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9490         if (tbl_data->tbl.obj)
9491                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9492         if (tbl_data->tunnel_offload && tbl_data->external) {
9493                 struct mlx5_hlist_entry *he;
9494                 struct mlx5_hlist *tunnel_grp_hash;
9495                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9496                 union tunnel_tbl_key tunnel_key = {
9497                         .tunnel_id = tbl_data->tunnel ?
9498                                         tbl_data->tunnel->tunnel_id : 0,
9499                         .group = tbl_data->group_id
9500                 };
9501                 uint32_t table_level = tbl_data->level;
9502
9503                 tunnel_grp_hash = tbl_data->tunnel ?
9504                                         tbl_data->tunnel->groups :
9505                                         thub->groups;
9506                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9507                 if (he)
9508                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9509                 DRV_LOG(DEBUG,
9510                         "table_level %u id %u tunnel %u group %u released.",
9511                         table_level,
9512                         tbl_data->id,
9513                         tbl_data->tunnel ?
9514                         tbl_data->tunnel->tunnel_id : 0,
9515                         tbl_data->group_id);
9516         }
9517         mlx5_cache_list_destroy(&tbl_data->matchers);
9518         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9519 }
9520
9521 /**
9522  * Release a flow table.
9523  *
9524  * @param[in] sh
9525  *   Pointer to device shared structure.
9526  * @param[in] tbl
9527  *   Table resource to be released.
9528  *
9529  * @return
9530  *   Returns 0 if table was released, else return 1;
9531  */
9532 static int
9533 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9534                              struct mlx5_flow_tbl_resource *tbl)
9535 {
9536         struct mlx5_flow_tbl_data_entry *tbl_data =
9537                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9538
9539         if (!tbl)
9540                 return 0;
9541         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9542 }
9543
9544 int
9545 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9546                          struct mlx5_cache_entry *entry, void *cb_ctx)
9547 {
9548         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9549         struct mlx5_flow_dv_matcher *ref = ctx->data;
9550         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9551                                                         entry);
9552
9553         return cur->crc != ref->crc ||
9554                cur->priority != ref->priority ||
9555                memcmp((const void *)cur->mask.buf,
9556                       (const void *)ref->mask.buf, ref->mask.size);
9557 }
9558
9559 struct mlx5_cache_entry *
9560 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9561                           struct mlx5_cache_entry *entry __rte_unused,
9562                           void *cb_ctx)
9563 {
9564         struct mlx5_dev_ctx_shared *sh = list->ctx;
9565         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9566         struct mlx5_flow_dv_matcher *ref = ctx->data;
9567         struct mlx5_flow_dv_matcher *cache;
9568         struct mlx5dv_flow_matcher_attr dv_attr = {
9569                 .type = IBV_FLOW_ATTR_NORMAL,
9570                 .match_mask = (void *)&ref->mask,
9571         };
9572         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9573                                                             typeof(*tbl), tbl);
9574         int ret;
9575
9576         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9577         if (!cache) {
9578                 rte_flow_error_set(ctx->error, ENOMEM,
9579                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9580                                    "cannot create matcher");
9581                 return NULL;
9582         }
9583         *cache = *ref;
9584         dv_attr.match_criteria_enable =
9585                 flow_dv_matcher_enable(cache->mask.buf);
9586         dv_attr.priority = ref->priority;
9587         if (tbl->is_egress)
9588                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9589         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9590                                                &cache->matcher_object);
9591         if (ret) {
9592                 mlx5_free(cache);
9593                 rte_flow_error_set(ctx->error, ENOMEM,
9594                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9595                                    "cannot create matcher");
9596                 return NULL;
9597         }
9598         return &cache->entry;
9599 }
9600
9601 /**
9602  * Register the flow matcher.
9603  *
9604  * @param[in, out] dev
9605  *   Pointer to rte_eth_dev structure.
9606  * @param[in, out] matcher
9607  *   Pointer to flow matcher.
9608  * @param[in, out] key
9609  *   Pointer to flow table key.
9610  * @parm[in, out] dev_flow
9611  *   Pointer to the dev_flow.
9612  * @param[out] error
9613  *   pointer to error structure.
9614  *
9615  * @return
9616  *   0 on success otherwise -errno and errno is set.
9617  */
9618 static int
9619 flow_dv_matcher_register(struct rte_eth_dev *dev,
9620                          struct mlx5_flow_dv_matcher *ref,
9621                          union mlx5_flow_tbl_key *key,
9622                          struct mlx5_flow *dev_flow,
9623                          const struct mlx5_flow_tunnel *tunnel,
9624                          uint32_t group_id,
9625                          struct rte_flow_error *error)
9626 {
9627         struct mlx5_cache_entry *entry;
9628         struct mlx5_flow_dv_matcher *cache;
9629         struct mlx5_flow_tbl_resource *tbl;
9630         struct mlx5_flow_tbl_data_entry *tbl_data;
9631         struct mlx5_flow_cb_ctx ctx = {
9632                 .error = error,
9633                 .data = ref,
9634         };
9635
9636         /**
9637          * tunnel offload API requires this registration for cases when
9638          * tunnel match rule was inserted before tunnel set rule.
9639          */
9640         tbl = flow_dv_tbl_resource_get(dev, key->level,
9641                                        key->is_egress, key->is_fdb,
9642                                        dev_flow->external, tunnel,
9643                                        group_id, 0, key->id, error);
9644         if (!tbl)
9645                 return -rte_errno;      /* No need to refill the error info */
9646         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9647         ref->tbl = tbl;
9648         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9649         if (!entry) {
9650                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9651                 return rte_flow_error_set(error, ENOMEM,
9652                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9653                                           "cannot allocate ref memory");
9654         }
9655         cache = container_of(entry, typeof(*cache), entry);
9656         dev_flow->handle->dvh.matcher = cache;
9657         return 0;
9658 }
9659
9660 struct mlx5_hlist_entry *
9661 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9662 {
9663         struct mlx5_dev_ctx_shared *sh = list->ctx;
9664         struct rte_flow_error *error = ctx;
9665         struct mlx5_flow_dv_tag_resource *entry;
9666         uint32_t idx = 0;
9667         int ret;
9668
9669         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9670         if (!entry) {
9671                 rte_flow_error_set(error, ENOMEM,
9672                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9673                                    "cannot allocate resource memory");
9674                 return NULL;
9675         }
9676         entry->idx = idx;
9677         entry->tag_id = key;
9678         ret = mlx5_flow_os_create_flow_action_tag(key,
9679                                                   &entry->action);
9680         if (ret) {
9681                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9682                 rte_flow_error_set(error, ENOMEM,
9683                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9684                                    NULL, "cannot create action");
9685                 return NULL;
9686         }
9687         return &entry->entry;
9688 }
9689
9690 int
9691 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9692                      struct mlx5_hlist_entry *entry, uint64_t key,
9693                      void *cb_ctx __rte_unused)
9694 {
9695         struct mlx5_flow_dv_tag_resource *tag =
9696                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9697
9698         return key != tag->tag_id;
9699 }
9700
9701 /**
9702  * Find existing tag resource or create and register a new one.
9703  *
9704  * @param dev[in, out]
9705  *   Pointer to rte_eth_dev structure.
9706  * @param[in, out] tag_be24
9707  *   Tag value in big endian then R-shift 8.
9708  * @parm[in, out] dev_flow
9709  *   Pointer to the dev_flow.
9710  * @param[out] error
9711  *   pointer to error structure.
9712  *
9713  * @return
9714  *   0 on success otherwise -errno and errno is set.
9715  */
9716 static int
9717 flow_dv_tag_resource_register
9718                         (struct rte_eth_dev *dev,
9719                          uint32_t tag_be24,
9720                          struct mlx5_flow *dev_flow,
9721                          struct rte_flow_error *error)
9722 {
9723         struct mlx5_priv *priv = dev->data->dev_private;
9724         struct mlx5_flow_dv_tag_resource *cache_resource;
9725         struct mlx5_hlist_entry *entry;
9726
9727         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9728         if (entry) {
9729                 cache_resource = container_of
9730                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9731                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9732                 dev_flow->dv.tag_resource = cache_resource;
9733                 return 0;
9734         }
9735         return -rte_errno;
9736 }
9737
9738 void
9739 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9740                       struct mlx5_hlist_entry *entry)
9741 {
9742         struct mlx5_dev_ctx_shared *sh = list->ctx;
9743         struct mlx5_flow_dv_tag_resource *tag =
9744                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9745
9746         MLX5_ASSERT(tag && sh && tag->action);
9747         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9748         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9749         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9750 }
9751
9752 /**
9753  * Release the tag.
9754  *
9755  * @param dev
9756  *   Pointer to Ethernet device.
9757  * @param tag_idx
9758  *   Tag index.
9759  *
9760  * @return
9761  *   1 while a reference on it exists, 0 when freed.
9762  */
9763 static int
9764 flow_dv_tag_release(struct rte_eth_dev *dev,
9765                     uint32_t tag_idx)
9766 {
9767         struct mlx5_priv *priv = dev->data->dev_private;
9768         struct mlx5_flow_dv_tag_resource *tag;
9769
9770         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9771         if (!tag)
9772                 return 0;
9773         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9774                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9775         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9776 }
9777
9778 /**
9779  * Translate port ID action to vport.
9780  *
9781  * @param[in] dev
9782  *   Pointer to rte_eth_dev structure.
9783  * @param[in] action
9784  *   Pointer to the port ID action.
9785  * @param[out] dst_port_id
9786  *   The target port ID.
9787  * @param[out] error
9788  *   Pointer to the error structure.
9789  *
9790  * @return
9791  *   0 on success, a negative errno value otherwise and rte_errno is set.
9792  */
9793 static int
9794 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9795                                  const struct rte_flow_action *action,
9796                                  uint32_t *dst_port_id,
9797                                  struct rte_flow_error *error)
9798 {
9799         uint32_t port;
9800         struct mlx5_priv *priv;
9801         const struct rte_flow_action_port_id *conf =
9802                         (const struct rte_flow_action_port_id *)action->conf;
9803
9804         port = conf->original ? dev->data->port_id : conf->id;
9805         priv = mlx5_port_to_eswitch_info(port, false);
9806         if (!priv)
9807                 return rte_flow_error_set(error, -rte_errno,
9808                                           RTE_FLOW_ERROR_TYPE_ACTION,
9809                                           NULL,
9810                                           "No eswitch info was found for port");
9811 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9812         /*
9813          * This parameter is transferred to
9814          * mlx5dv_dr_action_create_dest_ib_port().
9815          */
9816         *dst_port_id = priv->dev_port;
9817 #else
9818         /*
9819          * Legacy mode, no LAG configurations is supported.
9820          * This parameter is transferred to
9821          * mlx5dv_dr_action_create_dest_vport().
9822          */
9823         *dst_port_id = priv->vport_id;
9824 #endif
9825         return 0;
9826 }
9827
9828 /**
9829  * Create a counter with aging configuration.
9830  *
9831  * @param[in] dev
9832  *   Pointer to rte_eth_dev structure.
9833  * @param[out] count
9834  *   Pointer to the counter action configuration.
9835  * @param[in] age
9836  *   Pointer to the aging action configuration.
9837  *
9838  * @return
9839  *   Index to flow counter on success, 0 otherwise.
9840  */
9841 static uint32_t
9842 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9843                                 struct mlx5_flow *dev_flow,
9844                                 const struct rte_flow_action_count *count,
9845                                 const struct rte_flow_action_age *age)
9846 {
9847         uint32_t counter;
9848         struct mlx5_age_param *age_param;
9849
9850         if (count && count->shared)
9851                 counter = flow_dv_counter_get_shared(dev, count->id);
9852         else
9853                 counter = flow_dv_counter_alloc(dev, !!age);
9854         if (!counter || age == NULL)
9855                 return counter;
9856         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9857         age_param->context = age->context ? age->context :
9858                 (void *)(uintptr_t)(dev_flow->flow_idx);
9859         age_param->timeout = age->timeout;
9860         age_param->port_id = dev->data->port_id;
9861         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9862         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9863         return counter;
9864 }
9865
9866 /**
9867  * Add Tx queue matcher
9868  *
9869  * @param[in] dev
9870  *   Pointer to the dev struct.
9871  * @param[in, out] matcher
9872  *   Flow matcher.
9873  * @param[in, out] key
9874  *   Flow matcher value.
9875  * @param[in] item
9876  *   Flow pattern to translate.
9877  * @param[in] inner
9878  *   Item is inner pattern.
9879  */
9880 static void
9881 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9882                                 void *matcher, void *key,
9883                                 const struct rte_flow_item *item)
9884 {
9885         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9886         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9887         void *misc_m =
9888                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9889         void *misc_v =
9890                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9891         struct mlx5_txq_ctrl *txq;
9892         uint32_t queue;
9893
9894
9895         queue_m = (const void *)item->mask;
9896         if (!queue_m)
9897                 return;
9898         queue_v = (const void *)item->spec;
9899         if (!queue_v)
9900                 return;
9901         txq = mlx5_txq_get(dev, queue_v->queue);
9902         if (!txq)
9903                 return;
9904         queue = txq->obj->sq->id;
9905         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9906         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9907                  queue & queue_m->queue);
9908         mlx5_txq_release(dev, queue_v->queue);
9909 }
9910
9911 /**
9912  * Set the hash fields according to the @p flow information.
9913  *
9914  * @param[in] dev_flow
9915  *   Pointer to the mlx5_flow.
9916  * @param[in] rss_desc
9917  *   Pointer to the mlx5_flow_rss_desc.
9918  */
9919 static void
9920 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9921                        struct mlx5_flow_rss_desc *rss_desc)
9922 {
9923         uint64_t items = dev_flow->handle->layers;
9924         int rss_inner = 0;
9925         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9926
9927         dev_flow->hash_fields = 0;
9928 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9929         if (rss_desc->level >= 2) {
9930                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9931                 rss_inner = 1;
9932         }
9933 #endif
9934         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9935             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9936                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9937                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9938                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9939                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9940                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9941                         else
9942                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9943                 }
9944         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9945                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9946                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9947                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9948                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9949                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9950                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9951                         else
9952                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9953                 }
9954         }
9955         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9956             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9957                 if (rss_types & ETH_RSS_UDP) {
9958                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9959                                 dev_flow->hash_fields |=
9960                                                 IBV_RX_HASH_SRC_PORT_UDP;
9961                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9962                                 dev_flow->hash_fields |=
9963                                                 IBV_RX_HASH_DST_PORT_UDP;
9964                         else
9965                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9966                 }
9967         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9968                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9969                 if (rss_types & ETH_RSS_TCP) {
9970                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9971                                 dev_flow->hash_fields |=
9972                                                 IBV_RX_HASH_SRC_PORT_TCP;
9973                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9974                                 dev_flow->hash_fields |=
9975                                                 IBV_RX_HASH_DST_PORT_TCP;
9976                         else
9977                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9978                 }
9979         }
9980 }
9981
9982 /**
9983  * Prepare an Rx Hash queue.
9984  *
9985  * @param dev
9986  *   Pointer to Ethernet device.
9987  * @param[in] dev_flow
9988  *   Pointer to the mlx5_flow.
9989  * @param[in] rss_desc
9990  *   Pointer to the mlx5_flow_rss_desc.
9991  * @param[out] hrxq_idx
9992  *   Hash Rx queue index.
9993  *
9994  * @return
9995  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9996  */
9997 static struct mlx5_hrxq *
9998 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9999                      struct mlx5_flow *dev_flow,
10000                      struct mlx5_flow_rss_desc *rss_desc,
10001                      uint32_t *hrxq_idx)
10002 {
10003         struct mlx5_priv *priv = dev->data->dev_private;
10004         struct mlx5_flow_handle *dh = dev_flow->handle;
10005         struct mlx5_hrxq *hrxq;
10006
10007         MLX5_ASSERT(rss_desc->queue_num);
10008         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10009         rss_desc->hash_fields = dev_flow->hash_fields;
10010         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10011         rss_desc->shared_rss = 0;
10012         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10013         if (!*hrxq_idx)
10014                 return NULL;
10015         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10016                               *hrxq_idx);
10017         return hrxq;
10018 }
10019
10020 /**
10021  * Release sample sub action resource.
10022  *
10023  * @param[in, out] dev
10024  *   Pointer to rte_eth_dev structure.
10025  * @param[in] act_res
10026  *   Pointer to sample sub action resource.
10027  */
10028 static void
10029 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10030                                    struct mlx5_flow_sub_actions_idx *act_res)
10031 {
10032         if (act_res->rix_hrxq) {
10033                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10034                 act_res->rix_hrxq = 0;
10035         }
10036         if (act_res->rix_encap_decap) {
10037                 flow_dv_encap_decap_resource_release(dev,
10038                                                      act_res->rix_encap_decap);
10039                 act_res->rix_encap_decap = 0;
10040         }
10041         if (act_res->rix_port_id_action) {
10042                 flow_dv_port_id_action_resource_release(dev,
10043                                                 act_res->rix_port_id_action);
10044                 act_res->rix_port_id_action = 0;
10045         }
10046         if (act_res->rix_tag) {
10047                 flow_dv_tag_release(dev, act_res->rix_tag);
10048                 act_res->rix_tag = 0;
10049         }
10050         if (act_res->rix_jump) {
10051                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10052                 act_res->rix_jump = 0;
10053         }
10054 }
10055
10056 int
10057 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10058                         struct mlx5_cache_entry *entry, void *cb_ctx)
10059 {
10060         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10061         struct rte_eth_dev *dev = ctx->dev;
10062         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10063         struct mlx5_flow_dv_sample_resource *cache_resource =
10064                         container_of(entry, typeof(*cache_resource), entry);
10065
10066         if (resource->ratio == cache_resource->ratio &&
10067             resource->ft_type == cache_resource->ft_type &&
10068             resource->ft_id == cache_resource->ft_id &&
10069             resource->set_action == cache_resource->set_action &&
10070             !memcmp((void *)&resource->sample_act,
10071                     (void *)&cache_resource->sample_act,
10072                     sizeof(struct mlx5_flow_sub_actions_list))) {
10073                 /*
10074                  * Existing sample action should release the prepared
10075                  * sub-actions reference counter.
10076                  */
10077                 flow_dv_sample_sub_actions_release(dev,
10078                                                 &resource->sample_idx);
10079                 return 0;
10080         }
10081         return 1;
10082 }
10083
10084 struct mlx5_cache_entry *
10085 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10086                          struct mlx5_cache_entry *entry __rte_unused,
10087                          void *cb_ctx)
10088 {
10089         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10090         struct rte_eth_dev *dev = ctx->dev;
10091         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10092         void **sample_dv_actions = resource->sub_actions;
10093         struct mlx5_flow_dv_sample_resource *cache_resource;
10094         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10095         struct mlx5_priv *priv = dev->data->dev_private;
10096         struct mlx5_dev_ctx_shared *sh = priv->sh;
10097         struct mlx5_flow_tbl_resource *tbl;
10098         uint32_t idx = 0;
10099         const uint32_t next_ft_step = 1;
10100         uint32_t next_ft_id = resource->ft_id + next_ft_step;
10101         uint8_t is_egress = 0;
10102         uint8_t is_transfer = 0;
10103         struct rte_flow_error *error = ctx->error;
10104
10105         /* Register new sample resource. */
10106         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10107         if (!cache_resource) {
10108                 rte_flow_error_set(error, ENOMEM,
10109                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10110                                           NULL,
10111                                           "cannot allocate resource memory");
10112                 return NULL;
10113         }
10114         *cache_resource = *resource;
10115         /* Create normal path table level */
10116         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10117                 is_transfer = 1;
10118         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10119                 is_egress = 1;
10120         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10121                                         is_egress, is_transfer,
10122                                         true, NULL, 0, 0, 0, error);
10123         if (!tbl) {
10124                 rte_flow_error_set(error, ENOMEM,
10125                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10126                                           NULL,
10127                                           "fail to create normal path table "
10128                                           "for sample");
10129                 goto error;
10130         }
10131         cache_resource->normal_path_tbl = tbl;
10132         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10133                 if (!sh->default_miss_action) {
10134                         rte_flow_error_set(error, ENOMEM,
10135                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10136                                                 NULL,
10137                                                 "default miss action was not "
10138                                                 "created");
10139                         goto error;
10140                 }
10141                 sample_dv_actions[resource->sample_act.actions_num++] =
10142                                                 sh->default_miss_action;
10143         }
10144         /* Create a DR sample action */
10145         sampler_attr.sample_ratio = cache_resource->ratio;
10146         sampler_attr.default_next_table = tbl->obj;
10147         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10148         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10149                                                         &sample_dv_actions[0];
10150         sampler_attr.action = cache_resource->set_action;
10151         if (mlx5_os_flow_dr_create_flow_action_sampler
10152                         (&sampler_attr, &cache_resource->verbs_action)) {
10153                 rte_flow_error_set(error, ENOMEM,
10154                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10155                                         NULL, "cannot create sample action");
10156                 goto error;
10157         }
10158         cache_resource->idx = idx;
10159         cache_resource->dev = dev;
10160         return &cache_resource->entry;
10161 error:
10162         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10163                 flow_dv_sample_sub_actions_release(dev,
10164                                                    &cache_resource->sample_idx);
10165         if (cache_resource->normal_path_tbl)
10166                 flow_dv_tbl_resource_release(MLX5_SH(dev),
10167                                 cache_resource->normal_path_tbl);
10168         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10169         return NULL;
10170
10171 }
10172
10173 /**
10174  * Find existing sample resource or create and register a new one.
10175  *
10176  * @param[in, out] dev
10177  *   Pointer to rte_eth_dev structure.
10178  * @param[in] resource
10179  *   Pointer to sample resource.
10180  * @parm[in, out] dev_flow
10181  *   Pointer to the dev_flow.
10182  * @param[out] error
10183  *   pointer to error structure.
10184  *
10185  * @return
10186  *   0 on success otherwise -errno and errno is set.
10187  */
10188 static int
10189 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10190                          struct mlx5_flow_dv_sample_resource *resource,
10191                          struct mlx5_flow *dev_flow,
10192                          struct rte_flow_error *error)
10193 {
10194         struct mlx5_flow_dv_sample_resource *cache_resource;
10195         struct mlx5_cache_entry *entry;
10196         struct mlx5_priv *priv = dev->data->dev_private;
10197         struct mlx5_flow_cb_ctx ctx = {
10198                 .dev = dev,
10199                 .error = error,
10200                 .data = resource,
10201         };
10202
10203         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10204         if (!entry)
10205                 return -rte_errno;
10206         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10207         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10208         dev_flow->dv.sample_res = cache_resource;
10209         return 0;
10210 }
10211
10212 int
10213 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10214                             struct mlx5_cache_entry *entry, void *cb_ctx)
10215 {
10216         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10217         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10218         struct rte_eth_dev *dev = ctx->dev;
10219         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10220                         container_of(entry, typeof(*cache_resource), entry);
10221         uint32_t idx = 0;
10222
10223         if (resource->num_of_dest == cache_resource->num_of_dest &&
10224             resource->ft_type == cache_resource->ft_type &&
10225             !memcmp((void *)cache_resource->sample_act,
10226                     (void *)resource->sample_act,
10227                    (resource->num_of_dest *
10228                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10229                 /*
10230                  * Existing sample action should release the prepared
10231                  * sub-actions reference counter.
10232                  */
10233                 for (idx = 0; idx < resource->num_of_dest; idx++)
10234                         flow_dv_sample_sub_actions_release(dev,
10235                                         &resource->sample_idx[idx]);
10236                 return 0;
10237         }
10238         return 1;
10239 }
10240
10241 struct mlx5_cache_entry *
10242 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10243                          struct mlx5_cache_entry *entry __rte_unused,
10244                          void *cb_ctx)
10245 {
10246         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10247         struct rte_eth_dev *dev = ctx->dev;
10248         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10249         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10250         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10251         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10252         struct mlx5_priv *priv = dev->data->dev_private;
10253         struct mlx5_dev_ctx_shared *sh = priv->sh;
10254         struct mlx5_flow_sub_actions_list *sample_act;
10255         struct mlx5dv_dr_domain *domain;
10256         uint32_t idx = 0, res_idx = 0;
10257         struct rte_flow_error *error = ctx->error;
10258         uint64_t action_flags;
10259         int ret;
10260
10261         /* Register new destination array resource. */
10262         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10263                                             &res_idx);
10264         if (!cache_resource) {
10265                 rte_flow_error_set(error, ENOMEM,
10266                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10267                                           NULL,
10268                                           "cannot allocate resource memory");
10269                 return NULL;
10270         }
10271         *cache_resource = *resource;
10272         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10273                 domain = sh->fdb_domain;
10274         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10275                 domain = sh->rx_domain;
10276         else
10277                 domain = sh->tx_domain;
10278         for (idx = 0; idx < resource->num_of_dest; idx++) {
10279                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10280                                  mlx5_malloc(MLX5_MEM_ZERO,
10281                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10282                                  0, SOCKET_ID_ANY);
10283                 if (!dest_attr[idx]) {
10284                         rte_flow_error_set(error, ENOMEM,
10285                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10286                                            NULL,
10287                                            "cannot allocate resource memory");
10288                         goto error;
10289                 }
10290                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10291                 sample_act = &resource->sample_act[idx];
10292                 action_flags = sample_act->action_flags;
10293                 switch (action_flags) {
10294                 case MLX5_FLOW_ACTION_QUEUE:
10295                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10296                         break;
10297                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10298                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10299                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10300                         dest_attr[idx]->dest_reformat->reformat =
10301                                         sample_act->dr_encap_action;
10302                         dest_attr[idx]->dest_reformat->dest =
10303                                         sample_act->dr_port_id_action;
10304                         break;
10305                 case MLX5_FLOW_ACTION_PORT_ID:
10306                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10307                         break;
10308                 case MLX5_FLOW_ACTION_JUMP:
10309                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10310                         break;
10311                 default:
10312                         rte_flow_error_set(error, EINVAL,
10313                                            RTE_FLOW_ERROR_TYPE_ACTION,
10314                                            NULL,
10315                                            "unsupported actions type");
10316                         goto error;
10317                 }
10318         }
10319         /* create a dest array actioin */
10320         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10321                                                 (domain,
10322                                                  cache_resource->num_of_dest,
10323                                                  dest_attr,
10324                                                  &cache_resource->action);
10325         if (ret) {
10326                 rte_flow_error_set(error, ENOMEM,
10327                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10328                                    NULL,
10329                                    "cannot create destination array action");
10330                 goto error;
10331         }
10332         cache_resource->idx = res_idx;
10333         cache_resource->dev = dev;
10334         for (idx = 0; idx < resource->num_of_dest; idx++)
10335                 mlx5_free(dest_attr[idx]);
10336         return &cache_resource->entry;
10337 error:
10338         for (idx = 0; idx < resource->num_of_dest; idx++) {
10339                 flow_dv_sample_sub_actions_release(dev,
10340                                 &cache_resource->sample_idx[idx]);
10341                 if (dest_attr[idx])
10342                         mlx5_free(dest_attr[idx]);
10343         }
10344
10345         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10346         return NULL;
10347 }
10348
10349 /**
10350  * Find existing destination array resource or create and register a new one.
10351  *
10352  * @param[in, out] dev
10353  *   Pointer to rte_eth_dev structure.
10354  * @param[in] resource
10355  *   Pointer to destination array resource.
10356  * @parm[in, out] dev_flow
10357  *   Pointer to the dev_flow.
10358  * @param[out] error
10359  *   pointer to error structure.
10360  *
10361  * @return
10362  *   0 on success otherwise -errno and errno is set.
10363  */
10364 static int
10365 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10366                          struct mlx5_flow_dv_dest_array_resource *resource,
10367                          struct mlx5_flow *dev_flow,
10368                          struct rte_flow_error *error)
10369 {
10370         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10371         struct mlx5_priv *priv = dev->data->dev_private;
10372         struct mlx5_cache_entry *entry;
10373         struct mlx5_flow_cb_ctx ctx = {
10374                 .dev = dev,
10375                 .error = error,
10376                 .data = resource,
10377         };
10378
10379         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10380         if (!entry)
10381                 return -rte_errno;
10382         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10383         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10384         dev_flow->dv.dest_array_res = cache_resource;
10385         return 0;
10386 }
10387
10388 /**
10389  * Convert Sample action to DV specification.
10390  *
10391  * @param[in] dev
10392  *   Pointer to rte_eth_dev structure.
10393  * @param[in] action
10394  *   Pointer to sample action structure.
10395  * @param[in, out] dev_flow
10396  *   Pointer to the mlx5_flow.
10397  * @param[in] attr
10398  *   Pointer to the flow attributes.
10399  * @param[in, out] num_of_dest
10400  *   Pointer to the num of destination.
10401  * @param[in, out] sample_actions
10402  *   Pointer to sample actions list.
10403  * @param[in, out] res
10404  *   Pointer to sample resource.
10405  * @param[out] error
10406  *   Pointer to the error structure.
10407  *
10408  * @return
10409  *   0 on success, a negative errno value otherwise and rte_errno is set.
10410  */
10411 static int
10412 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10413                                 const struct rte_flow_action_sample *action,
10414                                 struct mlx5_flow *dev_flow,
10415                                 const struct rte_flow_attr *attr,
10416                                 uint32_t *num_of_dest,
10417                                 void **sample_actions,
10418                                 struct mlx5_flow_dv_sample_resource *res,
10419                                 struct rte_flow_error *error)
10420 {
10421         struct mlx5_priv *priv = dev->data->dev_private;
10422         const struct rte_flow_action *sub_actions;
10423         struct mlx5_flow_sub_actions_list *sample_act;
10424         struct mlx5_flow_sub_actions_idx *sample_idx;
10425         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10426         struct rte_flow *flow = dev_flow->flow;
10427         struct mlx5_flow_rss_desc *rss_desc;
10428         uint64_t action_flags = 0;
10429
10430         MLX5_ASSERT(wks);
10431         rss_desc = &wks->rss_desc;
10432         sample_act = &res->sample_act;
10433         sample_idx = &res->sample_idx;
10434         res->ratio = action->ratio;
10435         sub_actions = action->actions;
10436         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10437                 int type = sub_actions->type;
10438                 uint32_t pre_rix = 0;
10439                 void *pre_r;
10440                 switch (type) {
10441                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10442                 {
10443                         const struct rte_flow_action_queue *queue;
10444                         struct mlx5_hrxq *hrxq;
10445                         uint32_t hrxq_idx;
10446
10447                         queue = sub_actions->conf;
10448                         rss_desc->queue_num = 1;
10449                         rss_desc->queue[0] = queue->index;
10450                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10451                                                     rss_desc, &hrxq_idx);
10452                         if (!hrxq)
10453                                 return rte_flow_error_set
10454                                         (error, rte_errno,
10455                                          RTE_FLOW_ERROR_TYPE_ACTION,
10456                                          NULL,
10457                                          "cannot create fate queue");
10458                         sample_act->dr_queue_action = hrxq->action;
10459                         sample_idx->rix_hrxq = hrxq_idx;
10460                         sample_actions[sample_act->actions_num++] =
10461                                                 hrxq->action;
10462                         (*num_of_dest)++;
10463                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10464                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10465                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10466                         dev_flow->handle->fate_action =
10467                                         MLX5_FLOW_FATE_QUEUE;
10468                         break;
10469                 }
10470                 case RTE_FLOW_ACTION_TYPE_RSS:
10471                 {
10472                         struct mlx5_hrxq *hrxq;
10473                         uint32_t hrxq_idx;
10474                         const struct rte_flow_action_rss *rss;
10475                         const uint8_t *rss_key;
10476
10477                         rss = sub_actions->conf;
10478                         memcpy(rss_desc->queue, rss->queue,
10479                                rss->queue_num * sizeof(uint16_t));
10480                         rss_desc->queue_num = rss->queue_num;
10481                         /* NULL RSS key indicates default RSS key. */
10482                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10483                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10484                         /*
10485                          * rss->level and rss.types should be set in advance
10486                          * when expanding items for RSS.
10487                          */
10488                         flow_dv_hashfields_set(dev_flow, rss_desc);
10489                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10490                                                     rss_desc, &hrxq_idx);
10491                         if (!hrxq)
10492                                 return rte_flow_error_set
10493                                         (error, rte_errno,
10494                                          RTE_FLOW_ERROR_TYPE_ACTION,
10495                                          NULL,
10496                                          "cannot create fate queue");
10497                         sample_act->dr_queue_action = hrxq->action;
10498                         sample_idx->rix_hrxq = hrxq_idx;
10499                         sample_actions[sample_act->actions_num++] =
10500                                                 hrxq->action;
10501                         (*num_of_dest)++;
10502                         action_flags |= MLX5_FLOW_ACTION_RSS;
10503                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10504                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10505                         dev_flow->handle->fate_action =
10506                                         MLX5_FLOW_FATE_QUEUE;
10507                         break;
10508                 }
10509                 case RTE_FLOW_ACTION_TYPE_MARK:
10510                 {
10511                         uint32_t tag_be = mlx5_flow_mark_set
10512                                 (((const struct rte_flow_action_mark *)
10513                                 (sub_actions->conf))->id);
10514
10515                         dev_flow->handle->mark = 1;
10516                         pre_rix = dev_flow->handle->dvh.rix_tag;
10517                         /* Save the mark resource before sample */
10518                         pre_r = dev_flow->dv.tag_resource;
10519                         if (flow_dv_tag_resource_register(dev, tag_be,
10520                                                   dev_flow, error))
10521                                 return -rte_errno;
10522                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10523                         sample_act->dr_tag_action =
10524                                 dev_flow->dv.tag_resource->action;
10525                         sample_idx->rix_tag =
10526                                 dev_flow->handle->dvh.rix_tag;
10527                         sample_actions[sample_act->actions_num++] =
10528                                                 sample_act->dr_tag_action;
10529                         /* Recover the mark resource after sample */
10530                         dev_flow->dv.tag_resource = pre_r;
10531                         dev_flow->handle->dvh.rix_tag = pre_rix;
10532                         action_flags |= MLX5_FLOW_ACTION_MARK;
10533                         break;
10534                 }
10535                 case RTE_FLOW_ACTION_TYPE_COUNT:
10536                 {
10537                         if (!flow->counter) {
10538                                 flow->counter =
10539                                         flow_dv_translate_create_counter(dev,
10540                                                 dev_flow, sub_actions->conf,
10541                                                 0);
10542                                 if (!flow->counter)
10543                                         return rte_flow_error_set
10544                                                 (error, rte_errno,
10545                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10546                                                 NULL,
10547                                                 "cannot create counter"
10548                                                 " object.");
10549                         }
10550                         sample_act->dr_cnt_action =
10551                                   (flow_dv_counter_get_by_idx(dev,
10552                                   flow->counter, NULL))->action;
10553                         sample_actions[sample_act->actions_num++] =
10554                                                 sample_act->dr_cnt_action;
10555                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10556                         break;
10557                 }
10558                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10559                 {
10560                         struct mlx5_flow_dv_port_id_action_resource
10561                                         port_id_resource;
10562                         uint32_t port_id = 0;
10563
10564                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10565                         /* Save the port id resource before sample */
10566                         pre_rix = dev_flow->handle->rix_port_id_action;
10567                         pre_r = dev_flow->dv.port_id_action;
10568                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10569                                                              &port_id, error))
10570                                 return -rte_errno;
10571                         port_id_resource.port_id = port_id;
10572                         if (flow_dv_port_id_action_resource_register
10573                             (dev, &port_id_resource, dev_flow, error))
10574                                 return -rte_errno;
10575                         sample_act->dr_port_id_action =
10576                                 dev_flow->dv.port_id_action->action;
10577                         sample_idx->rix_port_id_action =
10578                                 dev_flow->handle->rix_port_id_action;
10579                         sample_actions[sample_act->actions_num++] =
10580                                                 sample_act->dr_port_id_action;
10581                         /* Recover the port id resource after sample */
10582                         dev_flow->dv.port_id_action = pre_r;
10583                         dev_flow->handle->rix_port_id_action = pre_rix;
10584                         (*num_of_dest)++;
10585                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10586                         break;
10587                 }
10588                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10589                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10590                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10591                         /* Save the encap resource before sample */
10592                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10593                         pre_r = dev_flow->dv.encap_decap;
10594                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10595                                                            dev_flow,
10596                                                            attr->transfer,
10597                                                            error))
10598                                 return -rte_errno;
10599                         sample_act->dr_encap_action =
10600                                 dev_flow->dv.encap_decap->action;
10601                         sample_idx->rix_encap_decap =
10602                                 dev_flow->handle->dvh.rix_encap_decap;
10603                         sample_actions[sample_act->actions_num++] =
10604                                                 sample_act->dr_encap_action;
10605                         /* Recover the encap resource after sample */
10606                         dev_flow->dv.encap_decap = pre_r;
10607                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10608                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10609                         break;
10610                 default:
10611                         return rte_flow_error_set(error, EINVAL,
10612                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10613                                 NULL,
10614                                 "Not support for sampler action");
10615                 }
10616         }
10617         sample_act->action_flags = action_flags;
10618         res->ft_id = dev_flow->dv.group;
10619         if (attr->transfer) {
10620                 union {
10621                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10622                         uint64_t set_action;
10623                 } action_ctx = { .set_action = 0 };
10624
10625                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10626                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10627                          MLX5_MODIFICATION_TYPE_SET);
10628                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10629                          MLX5_MODI_META_REG_C_0);
10630                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10631                          priv->vport_meta_tag);
10632                 res->set_action = action_ctx.set_action;
10633         } else if (attr->ingress) {
10634                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10635         } else {
10636                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10637         }
10638         return 0;
10639 }
10640
10641 /**
10642  * Convert Sample action to DV specification.
10643  *
10644  * @param[in] dev
10645  *   Pointer to rte_eth_dev structure.
10646  * @param[in, out] dev_flow
10647  *   Pointer to the mlx5_flow.
10648  * @param[in] num_of_dest
10649  *   The num of destination.
10650  * @param[in, out] res
10651  *   Pointer to sample resource.
10652  * @param[in, out] mdest_res
10653  *   Pointer to destination array resource.
10654  * @param[in] sample_actions
10655  *   Pointer to sample path actions list.
10656  * @param[in] action_flags
10657  *   Holds the actions detected until now.
10658  * @param[out] error
10659  *   Pointer to the error structure.
10660  *
10661  * @return
10662  *   0 on success, a negative errno value otherwise and rte_errno is set.
10663  */
10664 static int
10665 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10666                              struct mlx5_flow *dev_flow,
10667                              uint32_t num_of_dest,
10668                              struct mlx5_flow_dv_sample_resource *res,
10669                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10670                              void **sample_actions,
10671                              uint64_t action_flags,
10672                              struct rte_flow_error *error)
10673 {
10674         /* update normal path action resource into last index of array */
10675         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10676         struct mlx5_flow_sub_actions_list *sample_act =
10677                                         &mdest_res->sample_act[dest_index];
10678         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10679         struct mlx5_flow_rss_desc *rss_desc;
10680         uint32_t normal_idx = 0;
10681         struct mlx5_hrxq *hrxq;
10682         uint32_t hrxq_idx;
10683
10684         MLX5_ASSERT(wks);
10685         rss_desc = &wks->rss_desc;
10686         if (num_of_dest > 1) {
10687                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10688                         /* Handle QP action for mirroring */
10689                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10690                                                     rss_desc, &hrxq_idx);
10691                         if (!hrxq)
10692                                 return rte_flow_error_set
10693                                      (error, rte_errno,
10694                                       RTE_FLOW_ERROR_TYPE_ACTION,
10695                                       NULL,
10696                                       "cannot create rx queue");
10697                         normal_idx++;
10698                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10699                         sample_act->dr_queue_action = hrxq->action;
10700                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10701                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10702                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10703                 }
10704                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10705                         normal_idx++;
10706                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10707                                 dev_flow->handle->dvh.rix_encap_decap;
10708                         sample_act->dr_encap_action =
10709                                 dev_flow->dv.encap_decap->action;
10710                         dev_flow->handle->dvh.rix_encap_decap = 0;
10711                 }
10712                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10713                         normal_idx++;
10714                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10715                                 dev_flow->handle->rix_port_id_action;
10716                         sample_act->dr_port_id_action =
10717                                 dev_flow->dv.port_id_action->action;
10718                         dev_flow->handle->rix_port_id_action = 0;
10719                 }
10720                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10721                         normal_idx++;
10722                         mdest_res->sample_idx[dest_index].rix_jump =
10723                                 dev_flow->handle->rix_jump;
10724                         sample_act->dr_jump_action =
10725                                 dev_flow->dv.jump->action;
10726                         dev_flow->handle->rix_jump = 0;
10727                 }
10728                 sample_act->actions_num = normal_idx;
10729                 /* update sample action resource into first index of array */
10730                 mdest_res->ft_type = res->ft_type;
10731                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10732                                 sizeof(struct mlx5_flow_sub_actions_idx));
10733                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10734                                 sizeof(struct mlx5_flow_sub_actions_list));
10735                 mdest_res->num_of_dest = num_of_dest;
10736                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10737                                                          dev_flow, error))
10738                         return rte_flow_error_set(error, EINVAL,
10739                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10740                                                   NULL, "can't create sample "
10741                                                   "action");
10742         } else {
10743                 res->sub_actions = sample_actions;
10744                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10745                         return rte_flow_error_set(error, EINVAL,
10746                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10747                                                   NULL,
10748                                                   "can't create sample action");
10749         }
10750         return 0;
10751 }
10752
10753 /**
10754  * Remove an ASO age action from age actions list.
10755  *
10756  * @param[in] dev
10757  *   Pointer to the Ethernet device structure.
10758  * @param[in] age
10759  *   Pointer to the aso age action handler.
10760  */
10761 static void
10762 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10763                                 struct mlx5_aso_age_action *age)
10764 {
10765         struct mlx5_age_info *age_info;
10766         struct mlx5_age_param *age_param = &age->age_params;
10767         struct mlx5_priv *priv = dev->data->dev_private;
10768         uint16_t expected = AGE_CANDIDATE;
10769
10770         age_info = GET_PORT_AGE_INFO(priv);
10771         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10772                                          AGE_FREE, false, __ATOMIC_RELAXED,
10773                                          __ATOMIC_RELAXED)) {
10774                 /**
10775                  * We need the lock even it is age timeout,
10776                  * since age action may still in process.
10777                  */
10778                 rte_spinlock_lock(&age_info->aged_sl);
10779                 LIST_REMOVE(age, next);
10780                 rte_spinlock_unlock(&age_info->aged_sl);
10781                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10782         }
10783 }
10784
10785 /**
10786  * Release an ASO age action.
10787  *
10788  * @param[in] dev
10789  *   Pointer to the Ethernet device structure.
10790  * @param[in] age_idx
10791  *   Index of ASO age action to release.
10792  * @param[in] flow
10793  *   True if the release operation is during flow destroy operation.
10794  *   False if the release operation is during action destroy operation.
10795  *
10796  * @return
10797  *   0 when age action was removed, otherwise the number of references.
10798  */
10799 static int
10800 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10801 {
10802         struct mlx5_priv *priv = dev->data->dev_private;
10803         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10804         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10805         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10806
10807         if (!ret) {
10808                 flow_dv_aso_age_remove_from_age(dev, age);
10809                 rte_spinlock_lock(&mng->free_sl);
10810                 LIST_INSERT_HEAD(&mng->free, age, next);
10811                 rte_spinlock_unlock(&mng->free_sl);
10812         }
10813         return ret;
10814 }
10815
10816 /**
10817  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10818  *
10819  * @param[in] dev
10820  *   Pointer to the Ethernet device structure.
10821  *
10822  * @return
10823  *   0 on success, otherwise negative errno value and rte_errno is set.
10824  */
10825 static int
10826 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10827 {
10828         struct mlx5_priv *priv = dev->data->dev_private;
10829         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10830         void *old_pools = mng->pools;
10831         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10832         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10833         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10834
10835         if (!pools) {
10836                 rte_errno = ENOMEM;
10837                 return -ENOMEM;
10838         }
10839         if (old_pools) {
10840                 memcpy(pools, old_pools,
10841                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10842                 mlx5_free(old_pools);
10843         } else {
10844                 /* First ASO flow hit allocation - starting ASO data-path. */
10845                 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
10846
10847                 if (ret) {
10848                         mlx5_free(pools);
10849                         return ret;
10850                 }
10851         }
10852         mng->n = resize;
10853         mng->pools = pools;
10854         return 0;
10855 }
10856
10857 /**
10858  * Create and initialize a new ASO aging pool.
10859  *
10860  * @param[in] dev
10861  *   Pointer to the Ethernet device structure.
10862  * @param[out] age_free
10863  *   Where to put the pointer of a new age action.
10864  *
10865  * @return
10866  *   The age actions pool pointer and @p age_free is set on success,
10867  *   NULL otherwise and rte_errno is set.
10868  */
10869 static struct mlx5_aso_age_pool *
10870 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10871                         struct mlx5_aso_age_action **age_free)
10872 {
10873         struct mlx5_priv *priv = dev->data->dev_private;
10874         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10875         struct mlx5_aso_age_pool *pool = NULL;
10876         struct mlx5_devx_obj *obj = NULL;
10877         uint32_t i;
10878
10879         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10880                                                     priv->sh->pdn);
10881         if (!obj) {
10882                 rte_errno = ENODATA;
10883                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10884                 return NULL;
10885         }
10886         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10887         if (!pool) {
10888                 claim_zero(mlx5_devx_cmd_destroy(obj));
10889                 rte_errno = ENOMEM;
10890                 return NULL;
10891         }
10892         pool->flow_hit_aso_obj = obj;
10893         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10894         rte_spinlock_lock(&mng->resize_sl);
10895         pool->index = mng->next;
10896         /* Resize pools array if there is no room for the new pool in it. */
10897         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10898                 claim_zero(mlx5_devx_cmd_destroy(obj));
10899                 mlx5_free(pool);
10900                 rte_spinlock_unlock(&mng->resize_sl);
10901                 return NULL;
10902         }
10903         mng->pools[pool->index] = pool;
10904         mng->next++;
10905         rte_spinlock_unlock(&mng->resize_sl);
10906         /* Assign the first action in the new pool, the rest go to free list. */
10907         *age_free = &pool->actions[0];
10908         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10909                 pool->actions[i].offset = i;
10910                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10911         }
10912         return pool;
10913 }
10914
10915 /**
10916  * Allocate a ASO aging bit.
10917  *
10918  * @param[in] dev
10919  *   Pointer to the Ethernet device structure.
10920  * @param[out] error
10921  *   Pointer to the error structure.
10922  *
10923  * @return
10924  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10925  */
10926 static uint32_t
10927 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10928 {
10929         struct mlx5_priv *priv = dev->data->dev_private;
10930         const struct mlx5_aso_age_pool *pool;
10931         struct mlx5_aso_age_action *age_free = NULL;
10932         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10933
10934         MLX5_ASSERT(mng);
10935         /* Try to get the next free age action bit. */
10936         rte_spinlock_lock(&mng->free_sl);
10937         age_free = LIST_FIRST(&mng->free);
10938         if (age_free) {
10939                 LIST_REMOVE(age_free, next);
10940         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10941                 rte_spinlock_unlock(&mng->free_sl);
10942                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10943                                    NULL, "failed to create ASO age pool");
10944                 return 0; /* 0 is an error. */
10945         }
10946         rte_spinlock_unlock(&mng->free_sl);
10947         pool = container_of
10948           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10949                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10950                                                                        actions);
10951         if (!age_free->dr_action) {
10952                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10953                                                  error);
10954
10955                 if (reg_c < 0) {
10956                         rte_flow_error_set(error, rte_errno,
10957                                            RTE_FLOW_ERROR_TYPE_ACTION,
10958                                            NULL, "failed to get reg_c "
10959                                            "for ASO flow hit");
10960                         return 0; /* 0 is an error. */
10961                 }
10962 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10963                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10964                                 (priv->sh->rx_domain,
10965                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10966                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10967                                  (reg_c - REG_C_0));
10968 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10969                 if (!age_free->dr_action) {
10970                         rte_errno = errno;
10971                         rte_spinlock_lock(&mng->free_sl);
10972                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10973                         rte_spinlock_unlock(&mng->free_sl);
10974                         rte_flow_error_set(error, rte_errno,
10975                                            RTE_FLOW_ERROR_TYPE_ACTION,
10976                                            NULL, "failed to create ASO "
10977                                            "flow hit action");
10978                         return 0; /* 0 is an error. */
10979                 }
10980         }
10981         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10982         return pool->index | ((age_free->offset + 1) << 16);
10983 }
10984
10985 /**
10986  * Create a age action using ASO mechanism.
10987  *
10988  * @param[in] dev
10989  *   Pointer to rte_eth_dev structure.
10990  * @param[in] age
10991  *   Pointer to the aging action configuration.
10992  * @param[out] error
10993  *   Pointer to the error structure.
10994  *
10995  * @return
10996  *   Index to flow counter on success, 0 otherwise.
10997  */
10998 static uint32_t
10999 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
11000                                  const struct rte_flow_action_age *age,
11001                                  struct rte_flow_error *error)
11002 {
11003         uint32_t age_idx = 0;
11004         struct mlx5_aso_age_action *aso_age;
11005
11006         age_idx = flow_dv_aso_age_alloc(dev, error);
11007         if (!age_idx)
11008                 return 0;
11009         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11010         aso_age->age_params.context = age->context;
11011         aso_age->age_params.timeout = age->timeout;
11012         aso_age->age_params.port_id = dev->data->port_id;
11013         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11014                          __ATOMIC_RELAXED);
11015         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11016                          __ATOMIC_RELAXED);
11017         return age_idx;
11018 }
11019
11020 /**
11021  * Fill the flow with DV spec, lock free
11022  * (mutex should be acquired by caller).
11023  *
11024  * @param[in] dev
11025  *   Pointer to rte_eth_dev structure.
11026  * @param[in, out] dev_flow
11027  *   Pointer to the sub flow.
11028  * @param[in] attr
11029  *   Pointer to the flow attributes.
11030  * @param[in] items
11031  *   Pointer to the list of items.
11032  * @param[in] actions
11033  *   Pointer to the list of actions.
11034  * @param[out] error
11035  *   Pointer to the error structure.
11036  *
11037  * @return
11038  *   0 on success, a negative errno value otherwise and rte_errno is set.
11039  */
11040 static int
11041 flow_dv_translate(struct rte_eth_dev *dev,
11042                   struct mlx5_flow *dev_flow,
11043                   const struct rte_flow_attr *attr,
11044                   const struct rte_flow_item items[],
11045                   const struct rte_flow_action actions[],
11046                   struct rte_flow_error *error)
11047 {
11048         struct mlx5_priv *priv = dev->data->dev_private;
11049         struct mlx5_dev_config *dev_conf = &priv->config;
11050         struct rte_flow *flow = dev_flow->flow;
11051         struct mlx5_flow_handle *handle = dev_flow->handle;
11052         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11053         struct mlx5_flow_rss_desc *rss_desc;
11054         uint64_t item_flags = 0;
11055         uint64_t last_item = 0;
11056         uint64_t action_flags = 0;
11057         struct mlx5_flow_dv_matcher matcher = {
11058                 .mask = {
11059                         .size = sizeof(matcher.mask.buf) -
11060                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11061                 },
11062         };
11063         int actions_n = 0;
11064         bool actions_end = false;
11065         union {
11066                 struct mlx5_flow_dv_modify_hdr_resource res;
11067                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11068                             sizeof(struct mlx5_modification_cmd) *
11069                             (MLX5_MAX_MODIFY_NUM + 1)];
11070         } mhdr_dummy;
11071         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11072         const struct rte_flow_action_count *count = NULL;
11073         const struct rte_flow_action_age *age = NULL;
11074         union flow_dv_attr flow_attr = { .attr = 0 };
11075         uint32_t tag_be;
11076         union mlx5_flow_tbl_key tbl_key;
11077         uint32_t modify_action_position = UINT32_MAX;
11078         void *match_mask = matcher.mask.buf;
11079         void *match_value = dev_flow->dv.value.buf;
11080         uint8_t next_protocol = 0xff;
11081         struct rte_vlan_hdr vlan = { 0 };
11082         struct mlx5_flow_dv_dest_array_resource mdest_res;
11083         struct mlx5_flow_dv_sample_resource sample_res;
11084         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11085         const struct rte_flow_action_sample *sample = NULL;
11086         struct mlx5_flow_sub_actions_list *sample_act;
11087         uint32_t sample_act_pos = UINT32_MAX;
11088         uint32_t num_of_dest = 0;
11089         int tmp_actions_n = 0;
11090         uint32_t table;
11091         int ret = 0;
11092         const struct mlx5_flow_tunnel *tunnel;
11093         struct flow_grp_info grp_info = {
11094                 .external = !!dev_flow->external,
11095                 .transfer = !!attr->transfer,
11096                 .fdb_def_rule = !!priv->fdb_def_rule,
11097                 .skip_scale = dev_flow->skip_scale &
11098                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11099         };
11100
11101         if (!wks)
11102                 return rte_flow_error_set(error, ENOMEM,
11103                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11104                                           NULL,
11105                                           "failed to push flow workspace");
11106         rss_desc = &wks->rss_desc;
11107         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11108         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11109         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11110                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11111         /* update normal path action resource into last index of array */
11112         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11113         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11114                  flow_items_to_tunnel(items) :
11115                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11116                  flow_actions_to_tunnel(actions) :
11117                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
11118         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11119                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11120         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11121                                 (dev, tunnel, attr, items, actions);
11122         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11123                                        &grp_info, error);
11124         if (ret)
11125                 return ret;
11126         dev_flow->dv.group = table;
11127         if (attr->transfer)
11128                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11129         /* number of actions must be set to 0 in case of dirty stack. */
11130         mhdr_res->actions_num = 0;
11131         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11132                 /*
11133                  * do not add decap action if match rule drops packet
11134                  * HW rejects rules with decap & drop
11135                  *
11136                  * if tunnel match rule was inserted before matching tunnel set
11137                  * rule flow table used in the match rule must be registered.
11138                  * current implementation handles that in the
11139                  * flow_dv_match_register() at the function end.
11140                  */
11141                 bool add_decap = true;
11142                 const struct rte_flow_action *ptr = actions;
11143
11144                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11145                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11146                                 add_decap = false;
11147                                 break;
11148                         }
11149                 }
11150                 if (add_decap) {
11151                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11152                                                            attr->transfer,
11153                                                            error))
11154                                 return -rte_errno;
11155                         dev_flow->dv.actions[actions_n++] =
11156                                         dev_flow->dv.encap_decap->action;
11157                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11158                 }
11159         }
11160         for (; !actions_end ; actions++) {
11161                 const struct rte_flow_action_queue *queue;
11162                 const struct rte_flow_action_rss *rss;
11163                 const struct rte_flow_action *action = actions;
11164                 const uint8_t *rss_key;
11165                 struct mlx5_flow_tbl_resource *tbl;
11166                 struct mlx5_aso_age_action *age_act;
11167                 uint32_t port_id = 0;
11168                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11169                 int action_type = actions->type;
11170                 const struct rte_flow_action *found_action = NULL;
11171                 uint32_t jump_group = 0;
11172
11173                 if (!mlx5_flow_os_action_supported(action_type))
11174                         return rte_flow_error_set(error, ENOTSUP,
11175                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11176                                                   actions,
11177                                                   "action not supported");
11178                 switch (action_type) {
11179                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11180                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11181                         break;
11182                 case RTE_FLOW_ACTION_TYPE_VOID:
11183                         break;
11184                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11185                         if (flow_dv_translate_action_port_id(dev, action,
11186                                                              &port_id, error))
11187                                 return -rte_errno;
11188                         port_id_resource.port_id = port_id;
11189                         MLX5_ASSERT(!handle->rix_port_id_action);
11190                         if (flow_dv_port_id_action_resource_register
11191                             (dev, &port_id_resource, dev_flow, error))
11192                                 return -rte_errno;
11193                         dev_flow->dv.actions[actions_n++] =
11194                                         dev_flow->dv.port_id_action->action;
11195                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11196                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11197                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11198                         num_of_dest++;
11199                         break;
11200                 case RTE_FLOW_ACTION_TYPE_FLAG:
11201                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11202                         dev_flow->handle->mark = 1;
11203                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11204                                 struct rte_flow_action_mark mark = {
11205                                         .id = MLX5_FLOW_MARK_DEFAULT,
11206                                 };
11207
11208                                 if (flow_dv_convert_action_mark(dev, &mark,
11209                                                                 mhdr_res,
11210                                                                 error))
11211                                         return -rte_errno;
11212                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11213                                 break;
11214                         }
11215                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11216                         /*
11217                          * Only one FLAG or MARK is supported per device flow
11218                          * right now. So the pointer to the tag resource must be
11219                          * zero before the register process.
11220                          */
11221                         MLX5_ASSERT(!handle->dvh.rix_tag);
11222                         if (flow_dv_tag_resource_register(dev, tag_be,
11223                                                           dev_flow, error))
11224                                 return -rte_errno;
11225                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11226                         dev_flow->dv.actions[actions_n++] =
11227                                         dev_flow->dv.tag_resource->action;
11228                         break;
11229                 case RTE_FLOW_ACTION_TYPE_MARK:
11230                         action_flags |= MLX5_FLOW_ACTION_MARK;
11231                         dev_flow->handle->mark = 1;
11232                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11233                                 const struct rte_flow_action_mark *mark =
11234                                         (const struct rte_flow_action_mark *)
11235                                                 actions->conf;
11236
11237                                 if (flow_dv_convert_action_mark(dev, mark,
11238                                                                 mhdr_res,
11239                                                                 error))
11240                                         return -rte_errno;
11241                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11242                                 break;
11243                         }
11244                         /* Fall-through */
11245                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11246                         /* Legacy (non-extensive) MARK action. */
11247                         tag_be = mlx5_flow_mark_set
11248                               (((const struct rte_flow_action_mark *)
11249                                (actions->conf))->id);
11250                         MLX5_ASSERT(!handle->dvh.rix_tag);
11251                         if (flow_dv_tag_resource_register(dev, tag_be,
11252                                                           dev_flow, error))
11253                                 return -rte_errno;
11254                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11255                         dev_flow->dv.actions[actions_n++] =
11256                                         dev_flow->dv.tag_resource->action;
11257                         break;
11258                 case RTE_FLOW_ACTION_TYPE_SET_META:
11259                         if (flow_dv_convert_action_set_meta
11260                                 (dev, mhdr_res, attr,
11261                                  (const struct rte_flow_action_set_meta *)
11262                                   actions->conf, error))
11263                                 return -rte_errno;
11264                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11265                         break;
11266                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11267                         if (flow_dv_convert_action_set_tag
11268                                 (dev, mhdr_res,
11269                                  (const struct rte_flow_action_set_tag *)
11270                                   actions->conf, error))
11271                                 return -rte_errno;
11272                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11273                         break;
11274                 case RTE_FLOW_ACTION_TYPE_DROP:
11275                         action_flags |= MLX5_FLOW_ACTION_DROP;
11276                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11277                         break;
11278                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11279                         queue = actions->conf;
11280                         rss_desc->queue_num = 1;
11281                         rss_desc->queue[0] = queue->index;
11282                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11283                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11284                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11285                         num_of_dest++;
11286                         break;
11287                 case RTE_FLOW_ACTION_TYPE_RSS:
11288                         rss = actions->conf;
11289                         memcpy(rss_desc->queue, rss->queue,
11290                                rss->queue_num * sizeof(uint16_t));
11291                         rss_desc->queue_num = rss->queue_num;
11292                         /* NULL RSS key indicates default RSS key. */
11293                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11294                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11295                         /*
11296                          * rss->level and rss.types should be set in advance
11297                          * when expanding items for RSS.
11298                          */
11299                         action_flags |= MLX5_FLOW_ACTION_RSS;
11300                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11301                                 MLX5_FLOW_FATE_SHARED_RSS :
11302                                 MLX5_FLOW_FATE_QUEUE;
11303                         break;
11304                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11305                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11306                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11307                         __atomic_fetch_add(&age_act->refcnt, 1,
11308                                            __ATOMIC_RELAXED);
11309                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11310                         action_flags |= MLX5_FLOW_ACTION_AGE;
11311                         break;
11312                 case RTE_FLOW_ACTION_TYPE_AGE:
11313                         if (priv->sh->flow_hit_aso_en && attr->group) {
11314                                 /*
11315                                  * Create one shared age action, to be used
11316                                  * by all sub-flows.
11317                                  */
11318                                 if (!flow->age) {
11319                                         flow->age =
11320                                                 flow_dv_translate_create_aso_age
11321                                                         (dev, action->conf,
11322                                                          error);
11323                                         if (!flow->age)
11324                                                 return rte_flow_error_set
11325                                                 (error, rte_errno,
11326                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11327                                                  NULL,
11328                                                  "can't create ASO age action");
11329                                 }
11330                                 dev_flow->dv.actions[actions_n++] =
11331                                           (flow_aso_age_get_by_idx
11332                                                 (dev, flow->age))->dr_action;
11333                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11334                                 break;
11335                         }
11336                         /* Fall-through */
11337                 case RTE_FLOW_ACTION_TYPE_COUNT:
11338                         if (!dev_conf->devx) {
11339                                 return rte_flow_error_set
11340                                               (error, ENOTSUP,
11341                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11342                                                NULL,
11343                                                "count action not supported");
11344                         }
11345                         /* Save information first, will apply later. */
11346                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11347                                 count = action->conf;
11348                         else
11349                                 age = action->conf;
11350                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11351                         break;
11352                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11353                         dev_flow->dv.actions[actions_n++] =
11354                                                 priv->sh->pop_vlan_action;
11355                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11356                         break;
11357                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11358                         if (!(action_flags &
11359                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11360                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11361                         vlan.eth_proto = rte_be_to_cpu_16
11362                              ((((const struct rte_flow_action_of_push_vlan *)
11363                                                    actions->conf)->ethertype));
11364                         found_action = mlx5_flow_find_action
11365                                         (actions + 1,
11366                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11367                         if (found_action)
11368                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11369                         found_action = mlx5_flow_find_action
11370                                         (actions + 1,
11371                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11372                         if (found_action)
11373                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11374                         if (flow_dv_create_action_push_vlan
11375                                             (dev, attr, &vlan, dev_flow, error))
11376                                 return -rte_errno;
11377                         dev_flow->dv.actions[actions_n++] =
11378                                         dev_flow->dv.push_vlan_res->action;
11379                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11380                         break;
11381                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11382                         /* of_vlan_push action handled this action */
11383                         MLX5_ASSERT(action_flags &
11384                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11385                         break;
11386                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11387                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11388                                 break;
11389                         flow_dev_get_vlan_info_from_items(items, &vlan);
11390                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11391                         /* If no VLAN push - this is a modify header action */
11392                         if (flow_dv_convert_action_modify_vlan_vid
11393                                                 (mhdr_res, actions, error))
11394                                 return -rte_errno;
11395                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11396                         break;
11397                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11398                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11399                         if (flow_dv_create_action_l2_encap(dev, actions,
11400                                                            dev_flow,
11401                                                            attr->transfer,
11402                                                            error))
11403                                 return -rte_errno;
11404                         dev_flow->dv.actions[actions_n++] =
11405                                         dev_flow->dv.encap_decap->action;
11406                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11407                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11408                                 sample_act->action_flags |=
11409                                                         MLX5_FLOW_ACTION_ENCAP;
11410                         break;
11411                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11412                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11413                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11414                                                            attr->transfer,
11415                                                            error))
11416                                 return -rte_errno;
11417                         dev_flow->dv.actions[actions_n++] =
11418                                         dev_flow->dv.encap_decap->action;
11419                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11420                         break;
11421                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11422                         /* Handle encap with preceding decap. */
11423                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11424                                 if (flow_dv_create_action_raw_encap
11425                                         (dev, actions, dev_flow, attr, error))
11426                                         return -rte_errno;
11427                                 dev_flow->dv.actions[actions_n++] =
11428                                         dev_flow->dv.encap_decap->action;
11429                         } else {
11430                                 /* Handle encap without preceding decap. */
11431                                 if (flow_dv_create_action_l2_encap
11432                                     (dev, actions, dev_flow, attr->transfer,
11433                                      error))
11434                                         return -rte_errno;
11435                                 dev_flow->dv.actions[actions_n++] =
11436                                         dev_flow->dv.encap_decap->action;
11437                         }
11438                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11439                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11440                                 sample_act->action_flags |=
11441                                                         MLX5_FLOW_ACTION_ENCAP;
11442                         break;
11443                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11444                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11445                                 ;
11446                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11447                                 if (flow_dv_create_action_l2_decap
11448                                     (dev, dev_flow, attr->transfer, error))
11449                                         return -rte_errno;
11450                                 dev_flow->dv.actions[actions_n++] =
11451                                         dev_flow->dv.encap_decap->action;
11452                         }
11453                         /* If decap is followed by encap, handle it at encap. */
11454                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11455                         break;
11456                 case RTE_FLOW_ACTION_TYPE_JUMP:
11457                         jump_group = ((const struct rte_flow_action_jump *)
11458                                                         action->conf)->group;
11459                         grp_info.std_tbl_fix = 0;
11460                         if (dev_flow->skip_scale &
11461                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11462                                 grp_info.skip_scale = 1;
11463                         else
11464                                 grp_info.skip_scale = 0;
11465                         ret = mlx5_flow_group_to_table(dev, tunnel,
11466                                                        jump_group,
11467                                                        &table,
11468                                                        &grp_info, error);
11469                         if (ret)
11470                                 return ret;
11471                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11472                                                        attr->transfer,
11473                                                        !!dev_flow->external,
11474                                                        tunnel, jump_group, 0,
11475                                                        0, error);
11476                         if (!tbl)
11477                                 return rte_flow_error_set
11478                                                 (error, errno,
11479                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11480                                                  NULL,
11481                                                  "cannot create jump action.");
11482                         if (flow_dv_jump_tbl_resource_register
11483                             (dev, tbl, dev_flow, error)) {
11484                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11485                                 return rte_flow_error_set
11486                                                 (error, errno,
11487                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11488                                                  NULL,
11489                                                  "cannot create jump action.");
11490                         }
11491                         dev_flow->dv.actions[actions_n++] =
11492                                         dev_flow->dv.jump->action;
11493                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11494                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11495                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11496                         num_of_dest++;
11497                         break;
11498                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11499                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11500                         if (flow_dv_convert_action_modify_mac
11501                                         (mhdr_res, actions, error))
11502                                 return -rte_errno;
11503                         action_flags |= actions->type ==
11504                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11505                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11506                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11507                         break;
11508                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11509                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11510                         if (flow_dv_convert_action_modify_ipv4
11511                                         (mhdr_res, actions, error))
11512                                 return -rte_errno;
11513                         action_flags |= actions->type ==
11514                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11515                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11516                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11517                         break;
11518                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11519                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11520                         if (flow_dv_convert_action_modify_ipv6
11521                                         (mhdr_res, actions, error))
11522                                 return -rte_errno;
11523                         action_flags |= actions->type ==
11524                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11525                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11526                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11527                         break;
11528                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11529                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11530                         if (flow_dv_convert_action_modify_tp
11531                                         (mhdr_res, actions, items,
11532                                          &flow_attr, dev_flow, !!(action_flags &
11533                                          MLX5_FLOW_ACTION_DECAP), error))
11534                                 return -rte_errno;
11535                         action_flags |= actions->type ==
11536                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11537                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11538                                         MLX5_FLOW_ACTION_SET_TP_DST;
11539                         break;
11540                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11541                         if (flow_dv_convert_action_modify_dec_ttl
11542                                         (mhdr_res, items, &flow_attr, dev_flow,
11543                                          !!(action_flags &
11544                                          MLX5_FLOW_ACTION_DECAP), error))
11545                                 return -rte_errno;
11546                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11547                         break;
11548                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11549                         if (flow_dv_convert_action_modify_ttl
11550                                         (mhdr_res, actions, items, &flow_attr,
11551                                          dev_flow, !!(action_flags &
11552                                          MLX5_FLOW_ACTION_DECAP), error))
11553                                 return -rte_errno;
11554                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11555                         break;
11556                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11557                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11558                         if (flow_dv_convert_action_modify_tcp_seq
11559                                         (mhdr_res, actions, error))
11560                                 return -rte_errno;
11561                         action_flags |= actions->type ==
11562                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11563                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11564                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11565                         break;
11566
11567                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11568                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11569                         if (flow_dv_convert_action_modify_tcp_ack
11570                                         (mhdr_res, actions, error))
11571                                 return -rte_errno;
11572                         action_flags |= actions->type ==
11573                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11574                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11575                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11576                         break;
11577                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11578                         if (flow_dv_convert_action_set_reg
11579                                         (mhdr_res, actions, error))
11580                                 return -rte_errno;
11581                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11582                         break;
11583                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11584                         if (flow_dv_convert_action_copy_mreg
11585                                         (dev, mhdr_res, actions, error))
11586                                 return -rte_errno;
11587                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11588                         break;
11589                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11590                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11591                         dev_flow->handle->fate_action =
11592                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11593                         break;
11594                 case RTE_FLOW_ACTION_TYPE_METER:
11595                         if (!wks->fm)
11596                                 return rte_flow_error_set(error, rte_errno,
11597                                         RTE_FLOW_ERROR_TYPE_ACTION,
11598                                         NULL, "Failed to get meter in flow.");
11599                         /* Set the meter action. */
11600                         dev_flow->dv.actions[actions_n++] =
11601                                 wks->fm->meter_action;
11602                         action_flags |= MLX5_FLOW_ACTION_METER;
11603                         break;
11604                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11605                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11606                                                               actions, error))
11607                                 return -rte_errno;
11608                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11609                         break;
11610                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11611                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11612                                                               actions, error))
11613                                 return -rte_errno;
11614                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11615                         break;
11616                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11617                         sample_act_pos = actions_n;
11618                         sample = (const struct rte_flow_action_sample *)
11619                                  action->conf;
11620                         actions_n++;
11621                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11622                         /* put encap action into group if work with port id */
11623                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11624                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11625                                 sample_act->action_flags |=
11626                                                         MLX5_FLOW_ACTION_ENCAP;
11627                         break;
11628                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11629                         if (flow_dv_convert_action_modify_field
11630                                         (dev, mhdr_res, actions, attr, error))
11631                                 return -rte_errno;
11632                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11633                         break;
11634                 case RTE_FLOW_ACTION_TYPE_END:
11635                         actions_end = true;
11636                         if (mhdr_res->actions_num) {
11637                                 /* create modify action if needed. */
11638                                 if (flow_dv_modify_hdr_resource_register
11639                                         (dev, mhdr_res, dev_flow, error))
11640                                         return -rte_errno;
11641                                 dev_flow->dv.actions[modify_action_position] =
11642                                         handle->dvh.modify_hdr->action;
11643                         }
11644                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11645                                 /*
11646                                  * Create one count action, to be used
11647                                  * by all sub-flows.
11648                                  */
11649                                 if (!flow->counter) {
11650                                         flow->counter =
11651                                                 flow_dv_translate_create_counter
11652                                                         (dev, dev_flow, count,
11653                                                          age);
11654                                         if (!flow->counter)
11655                                                 return rte_flow_error_set
11656                                                 (error, rte_errno,
11657                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11658                                                  NULL, "cannot create counter"
11659                                                  " object.");
11660                                 }
11661                                 dev_flow->dv.actions[actions_n] =
11662                                           (flow_dv_counter_get_by_idx(dev,
11663                                           flow->counter, NULL))->action;
11664                                 actions_n++;
11665                         }
11666                 default:
11667                         break;
11668                 }
11669                 if (mhdr_res->actions_num &&
11670                     modify_action_position == UINT32_MAX)
11671                         modify_action_position = actions_n++;
11672         }
11673         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11674                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11675                 int item_type = items->type;
11676
11677                 if (!mlx5_flow_os_item_supported(item_type))
11678                         return rte_flow_error_set(error, ENOTSUP,
11679                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11680                                                   NULL, "item not supported");
11681                 switch (item_type) {
11682                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11683                         flow_dv_translate_item_port_id
11684                                 (dev, match_mask, match_value, items, attr);
11685                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11686                         break;
11687                 case RTE_FLOW_ITEM_TYPE_ETH:
11688                         flow_dv_translate_item_eth(match_mask, match_value,
11689                                                    items, tunnel,
11690                                                    dev_flow->dv.group);
11691                         matcher.priority = action_flags &
11692                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11693                                         !dev_flow->external ?
11694                                         MLX5_PRIORITY_MAP_L3 :
11695                                         MLX5_PRIORITY_MAP_L2;
11696                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11697                                              MLX5_FLOW_LAYER_OUTER_L2;
11698                         break;
11699                 case RTE_FLOW_ITEM_TYPE_VLAN:
11700                         flow_dv_translate_item_vlan(dev_flow,
11701                                                     match_mask, match_value,
11702                                                     items, tunnel,
11703                                                     dev_flow->dv.group);
11704                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11705                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11706                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11707                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11708                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11709                         break;
11710                 case RTE_FLOW_ITEM_TYPE_IPV4:
11711                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11712                                                   &item_flags, &tunnel);
11713                         flow_dv_translate_item_ipv4(match_mask, match_value,
11714                                                     items, tunnel,
11715                                                     dev_flow->dv.group);
11716                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11717                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11718                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11719                         if (items->mask != NULL &&
11720                             ((const struct rte_flow_item_ipv4 *)
11721                              items->mask)->hdr.next_proto_id) {
11722                                 next_protocol =
11723                                         ((const struct rte_flow_item_ipv4 *)
11724                                          (items->spec))->hdr.next_proto_id;
11725                                 next_protocol &=
11726                                         ((const struct rte_flow_item_ipv4 *)
11727                                          (items->mask))->hdr.next_proto_id;
11728                         } else {
11729                                 /* Reset for inner layer. */
11730                                 next_protocol = 0xff;
11731                         }
11732                         break;
11733                 case RTE_FLOW_ITEM_TYPE_IPV6:
11734                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11735                                                   &item_flags, &tunnel);
11736                         flow_dv_translate_item_ipv6(match_mask, match_value,
11737                                                     items, tunnel,
11738                                                     dev_flow->dv.group);
11739                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11740                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11741                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11742                         if (items->mask != NULL &&
11743                             ((const struct rte_flow_item_ipv6 *)
11744                              items->mask)->hdr.proto) {
11745                                 next_protocol =
11746                                         ((const struct rte_flow_item_ipv6 *)
11747                                          items->spec)->hdr.proto;
11748                                 next_protocol &=
11749                                         ((const struct rte_flow_item_ipv6 *)
11750                                          items->mask)->hdr.proto;
11751                         } else {
11752                                 /* Reset for inner layer. */
11753                                 next_protocol = 0xff;
11754                         }
11755                         break;
11756                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11757                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11758                                                              match_value,
11759                                                              items, tunnel);
11760                         last_item = tunnel ?
11761                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11762                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11763                         if (items->mask != NULL &&
11764                             ((const struct rte_flow_item_ipv6_frag_ext *)
11765                              items->mask)->hdr.next_header) {
11766                                 next_protocol =
11767                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11768                                  items->spec)->hdr.next_header;
11769                                 next_protocol &=
11770                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11771                                  items->mask)->hdr.next_header;
11772                         } else {
11773                                 /* Reset for inner layer. */
11774                                 next_protocol = 0xff;
11775                         }
11776                         break;
11777                 case RTE_FLOW_ITEM_TYPE_TCP:
11778                         flow_dv_translate_item_tcp(match_mask, match_value,
11779                                                    items, tunnel);
11780                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11781                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11782                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11783                         break;
11784                 case RTE_FLOW_ITEM_TYPE_UDP:
11785                         flow_dv_translate_item_udp(match_mask, match_value,
11786                                                    items, tunnel);
11787                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11788                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11789                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11790                         break;
11791                 case RTE_FLOW_ITEM_TYPE_GRE:
11792                         flow_dv_translate_item_gre(match_mask, match_value,
11793                                                    items, tunnel);
11794                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11795                         last_item = MLX5_FLOW_LAYER_GRE;
11796                         break;
11797                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11798                         flow_dv_translate_item_gre_key(match_mask,
11799                                                        match_value, items);
11800                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11801                         break;
11802                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11803                         flow_dv_translate_item_nvgre(match_mask, match_value,
11804                                                      items, tunnel);
11805                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11806                         last_item = MLX5_FLOW_LAYER_GRE;
11807                         break;
11808                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11809                         flow_dv_translate_item_vxlan(match_mask, match_value,
11810                                                      items, tunnel);
11811                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11812                         last_item = MLX5_FLOW_LAYER_VXLAN;
11813                         break;
11814                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11815                         flow_dv_translate_item_vxlan_gpe(match_mask,
11816                                                          match_value, items,
11817                                                          tunnel);
11818                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11819                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11820                         break;
11821                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11822                         flow_dv_translate_item_geneve(match_mask, match_value,
11823                                                       items, tunnel);
11824                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11825                         last_item = MLX5_FLOW_LAYER_GENEVE;
11826                         break;
11827                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11828                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11829                                                           match_value,
11830                                                           items, error);
11831                         if (ret)
11832                                 return rte_flow_error_set(error, -ret,
11833                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11834                                         "cannot create GENEVE TLV option");
11835                         flow->geneve_tlv_option = 1;
11836                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11837                         break;
11838                 case RTE_FLOW_ITEM_TYPE_MPLS:
11839                         flow_dv_translate_item_mpls(match_mask, match_value,
11840                                                     items, last_item, tunnel);
11841                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11842                         last_item = MLX5_FLOW_LAYER_MPLS;
11843                         break;
11844                 case RTE_FLOW_ITEM_TYPE_MARK:
11845                         flow_dv_translate_item_mark(dev, match_mask,
11846                                                     match_value, items);
11847                         last_item = MLX5_FLOW_ITEM_MARK;
11848                         break;
11849                 case RTE_FLOW_ITEM_TYPE_META:
11850                         flow_dv_translate_item_meta(dev, match_mask,
11851                                                     match_value, attr, items);
11852                         last_item = MLX5_FLOW_ITEM_METADATA;
11853                         break;
11854                 case RTE_FLOW_ITEM_TYPE_ICMP:
11855                         flow_dv_translate_item_icmp(match_mask, match_value,
11856                                                     items, tunnel);
11857                         last_item = MLX5_FLOW_LAYER_ICMP;
11858                         break;
11859                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11860                         flow_dv_translate_item_icmp6(match_mask, match_value,
11861                                                       items, tunnel);
11862                         last_item = MLX5_FLOW_LAYER_ICMP6;
11863                         break;
11864                 case RTE_FLOW_ITEM_TYPE_TAG:
11865                         flow_dv_translate_item_tag(dev, match_mask,
11866                                                    match_value, items);
11867                         last_item = MLX5_FLOW_ITEM_TAG;
11868                         break;
11869                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11870                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11871                                                         match_value, items);
11872                         last_item = MLX5_FLOW_ITEM_TAG;
11873                         break;
11874                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11875                         flow_dv_translate_item_tx_queue(dev, match_mask,
11876                                                         match_value,
11877                                                         items);
11878                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11879                         break;
11880                 case RTE_FLOW_ITEM_TYPE_GTP:
11881                         flow_dv_translate_item_gtp(match_mask, match_value,
11882                                                    items, tunnel);
11883                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11884                         last_item = MLX5_FLOW_LAYER_GTP;
11885                         break;
11886                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11887                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11888                                                           match_value,
11889                                                           items);
11890                         if (ret)
11891                                 return rte_flow_error_set(error, -ret,
11892                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11893                                         "cannot create GTP PSC item");
11894                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11895                         break;
11896                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11897                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11898                                 /* Create it only the first time to be used. */
11899                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11900                                 if (ret)
11901                                         return rte_flow_error_set
11902                                                 (error, -ret,
11903                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11904                                                 NULL,
11905                                                 "cannot create eCPRI parser");
11906                         }
11907                         /* Adjust the length matcher and device flow value. */
11908                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11909                         dev_flow->dv.value.size =
11910                                         MLX5_ST_SZ_BYTES(fte_match_param);
11911                         flow_dv_translate_item_ecpri(dev, match_mask,
11912                                                      match_value, items);
11913                         /* No other protocol should follow eCPRI layer. */
11914                         last_item = MLX5_FLOW_LAYER_ECPRI;
11915                         break;
11916                 default:
11917                         break;
11918                 }
11919                 item_flags |= last_item;
11920         }
11921         /*
11922          * When E-Switch mode is enabled, we have two cases where we need to
11923          * set the source port manually.
11924          * The first one, is in case of Nic steering rule, and the second is
11925          * E-Switch rule where no port_id item was found. In both cases
11926          * the source port is set according the current port in use.
11927          */
11928         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11929             (priv->representor || priv->master)) {
11930                 if (flow_dv_translate_item_port_id(dev, match_mask,
11931                                                    match_value, NULL, attr))
11932                         return -rte_errno;
11933         }
11934 #ifdef RTE_LIBRTE_MLX5_DEBUG
11935         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11936                                               dev_flow->dv.value.buf));
11937 #endif
11938         /*
11939          * Layers may be already initialized from prefix flow if this dev_flow
11940          * is the suffix flow.
11941          */
11942         handle->layers |= item_flags;
11943         if (action_flags & MLX5_FLOW_ACTION_RSS)
11944                 flow_dv_hashfields_set(dev_flow, rss_desc);
11945         /* If has RSS action in the sample action, the Sample/Mirror resource
11946          * should be registered after the hash filed be update.
11947          */
11948         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11949                 ret = flow_dv_translate_action_sample(dev,
11950                                                       sample,
11951                                                       dev_flow, attr,
11952                                                       &num_of_dest,
11953                                                       sample_actions,
11954                                                       &sample_res,
11955                                                       error);
11956                 if (ret < 0)
11957                         return ret;
11958                 ret = flow_dv_create_action_sample(dev,
11959                                                    dev_flow,
11960                                                    num_of_dest,
11961                                                    &sample_res,
11962                                                    &mdest_res,
11963                                                    sample_actions,
11964                                                    action_flags,
11965                                                    error);
11966                 if (ret < 0)
11967                         return rte_flow_error_set
11968                                                 (error, rte_errno,
11969                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11970                                                 NULL,
11971                                                 "cannot create sample action");
11972                 if (num_of_dest > 1) {
11973                         dev_flow->dv.actions[sample_act_pos] =
11974                         dev_flow->dv.dest_array_res->action;
11975                 } else {
11976                         dev_flow->dv.actions[sample_act_pos] =
11977                         dev_flow->dv.sample_res->verbs_action;
11978                 }
11979         }
11980         /*
11981          * For multiple destination (sample action with ratio=1), the encap
11982          * action and port id action will be combined into group action.
11983          * So need remove the original these actions in the flow and only
11984          * use the sample action instead of.
11985          */
11986         if (num_of_dest > 1 &&
11987             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11988                 int i;
11989                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11990
11991                 for (i = 0; i < actions_n; i++) {
11992                         if ((sample_act->dr_encap_action &&
11993                                 sample_act->dr_encap_action ==
11994                                 dev_flow->dv.actions[i]) ||
11995                                 (sample_act->dr_port_id_action &&
11996                                 sample_act->dr_port_id_action ==
11997                                 dev_flow->dv.actions[i]) ||
11998                                 (sample_act->dr_jump_action &&
11999                                 sample_act->dr_jump_action ==
12000                                 dev_flow->dv.actions[i]))
12001                                 continue;
12002                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12003                 }
12004                 memcpy((void *)dev_flow->dv.actions,
12005                                 (void *)temp_actions,
12006                                 tmp_actions_n * sizeof(void *));
12007                 actions_n = tmp_actions_n;
12008         }
12009         dev_flow->dv.actions_n = actions_n;
12010         dev_flow->act_flags = action_flags;
12011         /* Register matcher. */
12012         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12013                                     matcher.mask.size);
12014         matcher.priority = mlx5_get_matcher_priority(dev, attr,
12015                                         matcher.priority);
12016         /* reserved field no needs to be set to 0 here. */
12017         tbl_key.is_fdb = attr->transfer;
12018         tbl_key.is_egress = attr->egress;
12019         tbl_key.level = dev_flow->dv.group;
12020         tbl_key.id = dev_flow->dv.table_id;
12021         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12022                                      tunnel, attr->group, error))
12023                 return -rte_errno;
12024         return 0;
12025 }
12026
12027 /**
12028  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12029  * and tunnel.
12030  *
12031  * @param[in, out] action
12032  *   Shred RSS action holding hash RX queue objects.
12033  * @param[in] hash_fields
12034  *   Defines combination of packet fields to participate in RX hash.
12035  * @param[in] tunnel
12036  *   Tunnel type
12037  * @param[in] hrxq_idx
12038  *   Hash RX queue index to set.
12039  *
12040  * @return
12041  *   0 on success, otherwise negative errno value.
12042  */
12043 static int
12044 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12045                               const uint64_t hash_fields,
12046                               uint32_t hrxq_idx)
12047 {
12048         uint32_t *hrxqs = action->hrxq;
12049
12050         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12051         case MLX5_RSS_HASH_IPV4:
12052                 /* fall-through. */
12053         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12054                 /* fall-through. */
12055         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12056                 hrxqs[0] = hrxq_idx;
12057                 return 0;
12058         case MLX5_RSS_HASH_IPV4_TCP:
12059                 /* fall-through. */
12060         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12061                 /* fall-through. */
12062         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12063                 hrxqs[1] = hrxq_idx;
12064                 return 0;
12065         case MLX5_RSS_HASH_IPV4_UDP:
12066                 /* fall-through. */
12067         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12068                 /* fall-through. */
12069         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12070                 hrxqs[2] = hrxq_idx;
12071                 return 0;
12072         case MLX5_RSS_HASH_IPV6:
12073                 /* fall-through. */
12074         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12075                 /* fall-through. */
12076         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12077                 hrxqs[3] = hrxq_idx;
12078                 return 0;
12079         case MLX5_RSS_HASH_IPV6_TCP:
12080                 /* fall-through. */
12081         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12082                 /* fall-through. */
12083         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12084                 hrxqs[4] = hrxq_idx;
12085                 return 0;
12086         case MLX5_RSS_HASH_IPV6_UDP:
12087                 /* fall-through. */
12088         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12089                 /* fall-through. */
12090         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12091                 hrxqs[5] = hrxq_idx;
12092                 return 0;
12093         case MLX5_RSS_HASH_NONE:
12094                 hrxqs[6] = hrxq_idx;
12095                 return 0;
12096         default:
12097                 return -1;
12098         }
12099 }
12100
12101 /**
12102  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12103  * and tunnel.
12104  *
12105  * @param[in] dev
12106  *   Pointer to the Ethernet device structure.
12107  * @param[in] idx
12108  *   Shared RSS action ID holding hash RX queue objects.
12109  * @param[in] hash_fields
12110  *   Defines combination of packet fields to participate in RX hash.
12111  * @param[in] tunnel
12112  *   Tunnel type
12113  *
12114  * @return
12115  *   Valid hash RX queue index, otherwise 0.
12116  */
12117 static uint32_t
12118 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12119                                  const uint64_t hash_fields)
12120 {
12121         struct mlx5_priv *priv = dev->data->dev_private;
12122         struct mlx5_shared_action_rss *shared_rss =
12123             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12124         const uint32_t *hrxqs = shared_rss->hrxq;
12125
12126         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12127         case MLX5_RSS_HASH_IPV4:
12128                 /* fall-through. */
12129         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12130                 /* fall-through. */
12131         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12132                 return hrxqs[0];
12133         case MLX5_RSS_HASH_IPV4_TCP:
12134                 /* fall-through. */
12135         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12136                 /* fall-through. */
12137         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12138                 return hrxqs[1];
12139         case MLX5_RSS_HASH_IPV4_UDP:
12140                 /* fall-through. */
12141         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12142                 /* fall-through. */
12143         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12144                 return hrxqs[2];
12145         case MLX5_RSS_HASH_IPV6:
12146                 /* fall-through. */
12147         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12148                 /* fall-through. */
12149         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12150                 return hrxqs[3];
12151         case MLX5_RSS_HASH_IPV6_TCP:
12152                 /* fall-through. */
12153         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12154                 /* fall-through. */
12155         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12156                 return hrxqs[4];
12157         case MLX5_RSS_HASH_IPV6_UDP:
12158                 /* fall-through. */
12159         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12160                 /* fall-through. */
12161         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12162                 return hrxqs[5];
12163         case MLX5_RSS_HASH_NONE:
12164                 return hrxqs[6];
12165         default:
12166                 return 0;
12167         }
12168
12169 }
12170
12171 /**
12172  * Apply the flow to the NIC, lock free,
12173  * (mutex should be acquired by caller).
12174  *
12175  * @param[in] dev
12176  *   Pointer to the Ethernet device structure.
12177  * @param[in, out] flow
12178  *   Pointer to flow structure.
12179  * @param[out] error
12180  *   Pointer to error structure.
12181  *
12182  * @return
12183  *   0 on success, a negative errno value otherwise and rte_errno is set.
12184  */
12185 static int
12186 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12187               struct rte_flow_error *error)
12188 {
12189         struct mlx5_flow_dv_workspace *dv;
12190         struct mlx5_flow_handle *dh;
12191         struct mlx5_flow_handle_dv *dv_h;
12192         struct mlx5_flow *dev_flow;
12193         struct mlx5_priv *priv = dev->data->dev_private;
12194         uint32_t handle_idx;
12195         int n;
12196         int err;
12197         int idx;
12198         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12199         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12200
12201         MLX5_ASSERT(wks);
12202         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12203                 dev_flow = &wks->flows[idx];
12204                 dv = &dev_flow->dv;
12205                 dh = dev_flow->handle;
12206                 dv_h = &dh->dvh;
12207                 n = dv->actions_n;
12208                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12209                         if (dv->transfer) {
12210                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12211                                 dv->actions[n++] = priv->sh->dr_drop_action;
12212                         } else {
12213 #ifdef HAVE_MLX5DV_DR
12214                                 /* DR supports drop action placeholder. */
12215                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12216                                 dv->actions[n++] = priv->sh->dr_drop_action;
12217 #else
12218                                 /* For DV we use the explicit drop queue. */
12219                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12220                                 dv->actions[n++] =
12221                                                 priv->drop_queue.hrxq->action;
12222 #endif
12223                         }
12224                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12225                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12226                         struct mlx5_hrxq *hrxq;
12227                         uint32_t hrxq_idx;
12228
12229                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12230                                                     &hrxq_idx);
12231                         if (!hrxq) {
12232                                 rte_flow_error_set
12233                                         (error, rte_errno,
12234                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12235                                          "cannot get hash queue");
12236                                 goto error;
12237                         }
12238                         dh->rix_hrxq = hrxq_idx;
12239                         dv->actions[n++] = hrxq->action;
12240                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12241                         struct mlx5_hrxq *hrxq = NULL;
12242                         uint32_t hrxq_idx;
12243
12244                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12245                                                 rss_desc->shared_rss,
12246                                                 dev_flow->hash_fields);
12247                         if (hrxq_idx)
12248                                 hrxq = mlx5_ipool_get
12249                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12250                                          hrxq_idx);
12251                         if (!hrxq) {
12252                                 rte_flow_error_set
12253                                         (error, rte_errno,
12254                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12255                                          "cannot get hash queue");
12256                                 goto error;
12257                         }
12258                         dh->rix_srss = rss_desc->shared_rss;
12259                         dv->actions[n++] = hrxq->action;
12260                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12261                         if (!priv->sh->default_miss_action) {
12262                                 rte_flow_error_set
12263                                         (error, rte_errno,
12264                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12265                                          "default miss action not be created.");
12266                                 goto error;
12267                         }
12268                         dv->actions[n++] = priv->sh->default_miss_action;
12269                 }
12270                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12271                                                (void *)&dv->value, n,
12272                                                dv->actions, &dh->drv_flow);
12273                 if (err) {
12274                         rte_flow_error_set(error, errno,
12275                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12276                                            NULL,
12277                                            "hardware refuses to create flow");
12278                         goto error;
12279                 }
12280                 if (priv->vmwa_context &&
12281                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12282                         /*
12283                          * The rule contains the VLAN pattern.
12284                          * For VF we are going to create VLAN
12285                          * interface to make hypervisor set correct
12286                          * e-Switch vport context.
12287                          */
12288                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12289                 }
12290         }
12291         return 0;
12292 error:
12293         err = rte_errno; /* Save rte_errno before cleanup. */
12294         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12295                        handle_idx, dh, next) {
12296                 /* hrxq is union, don't clear it if the flag is not set. */
12297                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12298                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12299                         dh->rix_hrxq = 0;
12300                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12301                         dh->rix_srss = 0;
12302                 }
12303                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12304                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12305         }
12306         rte_errno = err; /* Restore rte_errno. */
12307         return -rte_errno;
12308 }
12309
12310 void
12311 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12312                           struct mlx5_cache_entry *entry)
12313 {
12314         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12315                                                           entry);
12316
12317         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12318         mlx5_free(cache);
12319 }
12320
12321 /**
12322  * Release the flow matcher.
12323  *
12324  * @param dev
12325  *   Pointer to Ethernet device.
12326  * @param port_id
12327  *   Index to port ID action resource.
12328  *
12329  * @return
12330  *   1 while a reference on it exists, 0 when freed.
12331  */
12332 static int
12333 flow_dv_matcher_release(struct rte_eth_dev *dev,
12334                         struct mlx5_flow_handle *handle)
12335 {
12336         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12337         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12338                                                             typeof(*tbl), tbl);
12339         int ret;
12340
12341         MLX5_ASSERT(matcher->matcher_object);
12342         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12343         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12344         return ret;
12345 }
12346
12347 /**
12348  * Release encap_decap resource.
12349  *
12350  * @param list
12351  *   Pointer to the hash list.
12352  * @param entry
12353  *   Pointer to exist resource entry object.
12354  */
12355 void
12356 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12357                               struct mlx5_hlist_entry *entry)
12358 {
12359         struct mlx5_dev_ctx_shared *sh = list->ctx;
12360         struct mlx5_flow_dv_encap_decap_resource *res =
12361                 container_of(entry, typeof(*res), entry);
12362
12363         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12364         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12365 }
12366
12367 /**
12368  * Release an encap/decap resource.
12369  *
12370  * @param dev
12371  *   Pointer to Ethernet device.
12372  * @param encap_decap_idx
12373  *   Index of encap decap resource.
12374  *
12375  * @return
12376  *   1 while a reference on it exists, 0 when freed.
12377  */
12378 static int
12379 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12380                                      uint32_t encap_decap_idx)
12381 {
12382         struct mlx5_priv *priv = dev->data->dev_private;
12383         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12384
12385         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12386                                         encap_decap_idx);
12387         if (!cache_resource)
12388                 return 0;
12389         MLX5_ASSERT(cache_resource->action);
12390         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12391                                      &cache_resource->entry);
12392 }
12393
12394 /**
12395  * Release an jump to table action resource.
12396  *
12397  * @param dev
12398  *   Pointer to Ethernet device.
12399  * @param rix_jump
12400  *   Index to the jump action resource.
12401  *
12402  * @return
12403  *   1 while a reference on it exists, 0 when freed.
12404  */
12405 static int
12406 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12407                                   uint32_t rix_jump)
12408 {
12409         struct mlx5_priv *priv = dev->data->dev_private;
12410         struct mlx5_flow_tbl_data_entry *tbl_data;
12411
12412         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12413                                   rix_jump);
12414         if (!tbl_data)
12415                 return 0;
12416         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12417 }
12418
12419 void
12420 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12421                          struct mlx5_hlist_entry *entry)
12422 {
12423         struct mlx5_flow_dv_modify_hdr_resource *res =
12424                 container_of(entry, typeof(*res), entry);
12425
12426         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12427         mlx5_free(entry);
12428 }
12429
12430 /**
12431  * Release a modify-header resource.
12432  *
12433  * @param dev
12434  *   Pointer to Ethernet device.
12435  * @param handle
12436  *   Pointer to mlx5_flow_handle.
12437  *
12438  * @return
12439  *   1 while a reference on it exists, 0 when freed.
12440  */
12441 static int
12442 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12443                                     struct mlx5_flow_handle *handle)
12444 {
12445         struct mlx5_priv *priv = dev->data->dev_private;
12446         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12447
12448         MLX5_ASSERT(entry->action);
12449         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12450 }
12451
12452 void
12453 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12454                           struct mlx5_cache_entry *entry)
12455 {
12456         struct mlx5_dev_ctx_shared *sh = list->ctx;
12457         struct mlx5_flow_dv_port_id_action_resource *cache =
12458                         container_of(entry, typeof(*cache), entry);
12459
12460         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12461         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12462 }
12463
12464 /**
12465  * Release port ID action resource.
12466  *
12467  * @param dev
12468  *   Pointer to Ethernet device.
12469  * @param handle
12470  *   Pointer to mlx5_flow_handle.
12471  *
12472  * @return
12473  *   1 while a reference on it exists, 0 when freed.
12474  */
12475 static int
12476 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12477                                         uint32_t port_id)
12478 {
12479         struct mlx5_priv *priv = dev->data->dev_private;
12480         struct mlx5_flow_dv_port_id_action_resource *cache;
12481
12482         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12483         if (!cache)
12484                 return 0;
12485         MLX5_ASSERT(cache->action);
12486         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12487                                      &cache->entry);
12488 }
12489
12490 /**
12491  * Release shared RSS action resource.
12492  *
12493  * @param dev
12494  *   Pointer to Ethernet device.
12495  * @param srss
12496  *   Shared RSS action index.
12497  */
12498 static void
12499 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12500 {
12501         struct mlx5_priv *priv = dev->data->dev_private;
12502         struct mlx5_shared_action_rss *shared_rss;
12503
12504         shared_rss = mlx5_ipool_get
12505                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12506         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12507 }
12508
12509 void
12510 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12511                             struct mlx5_cache_entry *entry)
12512 {
12513         struct mlx5_dev_ctx_shared *sh = list->ctx;
12514         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12515                         container_of(entry, typeof(*cache), entry);
12516
12517         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12518         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12519 }
12520
12521 /**
12522  * Release push vlan action resource.
12523  *
12524  * @param dev
12525  *   Pointer to Ethernet device.
12526  * @param handle
12527  *   Pointer to mlx5_flow_handle.
12528  *
12529  * @return
12530  *   1 while a reference on it exists, 0 when freed.
12531  */
12532 static int
12533 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12534                                           struct mlx5_flow_handle *handle)
12535 {
12536         struct mlx5_priv *priv = dev->data->dev_private;
12537         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12538         uint32_t idx = handle->dvh.rix_push_vlan;
12539
12540         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12541         if (!cache)
12542                 return 0;
12543         MLX5_ASSERT(cache->action);
12544         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12545                                      &cache->entry);
12546 }
12547
12548 /**
12549  * Release the fate resource.
12550  *
12551  * @param dev
12552  *   Pointer to Ethernet device.
12553  * @param handle
12554  *   Pointer to mlx5_flow_handle.
12555  */
12556 static void
12557 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12558                                struct mlx5_flow_handle *handle)
12559 {
12560         if (!handle->rix_fate)
12561                 return;
12562         switch (handle->fate_action) {
12563         case MLX5_FLOW_FATE_QUEUE:
12564                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12565                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12566                 break;
12567         case MLX5_FLOW_FATE_JUMP:
12568                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12569                 break;
12570         case MLX5_FLOW_FATE_PORT_ID:
12571                 flow_dv_port_id_action_resource_release(dev,
12572                                 handle->rix_port_id_action);
12573                 break;
12574         default:
12575                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12576                 break;
12577         }
12578         handle->rix_fate = 0;
12579 }
12580
12581 void
12582 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12583                          struct mlx5_cache_entry *entry)
12584 {
12585         struct mlx5_flow_dv_sample_resource *cache_resource =
12586                         container_of(entry, typeof(*cache_resource), entry);
12587         struct rte_eth_dev *dev = cache_resource->dev;
12588         struct mlx5_priv *priv = dev->data->dev_private;
12589
12590         if (cache_resource->verbs_action)
12591                 claim_zero(mlx5_flow_os_destroy_flow_action
12592                                 (cache_resource->verbs_action));
12593         if (cache_resource->normal_path_tbl)
12594                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12595                         cache_resource->normal_path_tbl);
12596         flow_dv_sample_sub_actions_release(dev,
12597                                 &cache_resource->sample_idx);
12598         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12599                         cache_resource->idx);
12600         DRV_LOG(DEBUG, "sample resource %p: removed",
12601                 (void *)cache_resource);
12602 }
12603
12604 /**
12605  * Release an sample resource.
12606  *
12607  * @param dev
12608  *   Pointer to Ethernet device.
12609  * @param handle
12610  *   Pointer to mlx5_flow_handle.
12611  *
12612  * @return
12613  *   1 while a reference on it exists, 0 when freed.
12614  */
12615 static int
12616 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12617                                      struct mlx5_flow_handle *handle)
12618 {
12619         struct mlx5_priv *priv = dev->data->dev_private;
12620         struct mlx5_flow_dv_sample_resource *cache_resource;
12621
12622         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12623                          handle->dvh.rix_sample);
12624         if (!cache_resource)
12625                 return 0;
12626         MLX5_ASSERT(cache_resource->verbs_action);
12627         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12628                                      &cache_resource->entry);
12629 }
12630
12631 void
12632 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12633                              struct mlx5_cache_entry *entry)
12634 {
12635         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12636                         container_of(entry, typeof(*cache_resource), entry);
12637         struct rte_eth_dev *dev = cache_resource->dev;
12638         struct mlx5_priv *priv = dev->data->dev_private;
12639         uint32_t i = 0;
12640
12641         MLX5_ASSERT(cache_resource->action);
12642         if (cache_resource->action)
12643                 claim_zero(mlx5_flow_os_destroy_flow_action
12644                                         (cache_resource->action));
12645         for (; i < cache_resource->num_of_dest; i++)
12646                 flow_dv_sample_sub_actions_release(dev,
12647                                 &cache_resource->sample_idx[i]);
12648         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12649                         cache_resource->idx);
12650         DRV_LOG(DEBUG, "destination array resource %p: removed",
12651                 (void *)cache_resource);
12652 }
12653
12654 /**
12655  * Release an destination array resource.
12656  *
12657  * @param dev
12658  *   Pointer to Ethernet device.
12659  * @param handle
12660  *   Pointer to mlx5_flow_handle.
12661  *
12662  * @return
12663  *   1 while a reference on it exists, 0 when freed.
12664  */
12665 static int
12666 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12667                                     struct mlx5_flow_handle *handle)
12668 {
12669         struct mlx5_priv *priv = dev->data->dev_private;
12670         struct mlx5_flow_dv_dest_array_resource *cache;
12671
12672         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12673                                handle->dvh.rix_dest_array);
12674         if (!cache)
12675                 return 0;
12676         MLX5_ASSERT(cache->action);
12677         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12678                                      &cache->entry);
12679 }
12680
12681 static void
12682 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12683 {
12684         struct mlx5_priv *priv = dev->data->dev_private;
12685         struct mlx5_dev_ctx_shared *sh = priv->sh;
12686         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12687                                 sh->geneve_tlv_option_resource;
12688         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12689         if (geneve_opt_resource) {
12690                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12691                                          __ATOMIC_RELAXED))) {
12692                         claim_zero(mlx5_devx_cmd_destroy
12693                                         (geneve_opt_resource->obj));
12694                         mlx5_free(sh->geneve_tlv_option_resource);
12695                         sh->geneve_tlv_option_resource = NULL;
12696                 }
12697         }
12698         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12699 }
12700
12701 /**
12702  * Remove the flow from the NIC but keeps it in memory.
12703  * Lock free, (mutex should be acquired by caller).
12704  *
12705  * @param[in] dev
12706  *   Pointer to Ethernet device.
12707  * @param[in, out] flow
12708  *   Pointer to flow structure.
12709  */
12710 static void
12711 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12712 {
12713         struct mlx5_flow_handle *dh;
12714         uint32_t handle_idx;
12715         struct mlx5_priv *priv = dev->data->dev_private;
12716
12717         if (!flow)
12718                 return;
12719         handle_idx = flow->dev_handles;
12720         while (handle_idx) {
12721                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12722                                     handle_idx);
12723                 if (!dh)
12724                         return;
12725                 if (dh->drv_flow) {
12726                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12727                         dh->drv_flow = NULL;
12728                 }
12729                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12730                         flow_dv_fate_resource_release(dev, dh);
12731                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12732                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12733                 handle_idx = dh->next.next;
12734         }
12735 }
12736
12737 /**
12738  * Remove the flow from the NIC and the memory.
12739  * Lock free, (mutex should be acquired by caller).
12740  *
12741  * @param[in] dev
12742  *   Pointer to the Ethernet device structure.
12743  * @param[in, out] flow
12744  *   Pointer to flow structure.
12745  */
12746 static void
12747 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12748 {
12749         struct mlx5_flow_handle *dev_handle;
12750         struct mlx5_priv *priv = dev->data->dev_private;
12751         struct mlx5_flow_meter_info *fm = NULL;
12752         uint32_t srss = 0;
12753
12754         if (!flow)
12755                 return;
12756         flow_dv_remove(dev, flow);
12757         if (flow->counter) {
12758                 flow_dv_counter_free(dev, flow->counter);
12759                 flow->counter = 0;
12760         }
12761         if (flow->meter) {
12762                 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12763                 if (fm)
12764                         mlx5_flow_meter_detach(priv, fm);
12765                 flow->meter = 0;
12766         }
12767         if (flow->age)
12768                 flow_dv_aso_age_release(dev, flow->age);
12769         if (flow->geneve_tlv_option) {
12770                 flow_dv_geneve_tlv_option_resource_release(dev);
12771                 flow->geneve_tlv_option = 0;
12772         }
12773         while (flow->dev_handles) {
12774                 uint32_t tmp_idx = flow->dev_handles;
12775
12776                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12777                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12778                 if (!dev_handle)
12779                         return;
12780                 flow->dev_handles = dev_handle->next.next;
12781                 if (dev_handle->dvh.matcher)
12782                         flow_dv_matcher_release(dev, dev_handle);
12783                 if (dev_handle->dvh.rix_sample)
12784                         flow_dv_sample_resource_release(dev, dev_handle);
12785                 if (dev_handle->dvh.rix_dest_array)
12786                         flow_dv_dest_array_resource_release(dev, dev_handle);
12787                 if (dev_handle->dvh.rix_encap_decap)
12788                         flow_dv_encap_decap_resource_release(dev,
12789                                 dev_handle->dvh.rix_encap_decap);
12790                 if (dev_handle->dvh.modify_hdr)
12791                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12792                 if (dev_handle->dvh.rix_push_vlan)
12793                         flow_dv_push_vlan_action_resource_release(dev,
12794                                                                   dev_handle);
12795                 if (dev_handle->dvh.rix_tag)
12796                         flow_dv_tag_release(dev,
12797                                             dev_handle->dvh.rix_tag);
12798                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12799                         flow_dv_fate_resource_release(dev, dev_handle);
12800                 else if (!srss)
12801                         srss = dev_handle->rix_srss;
12802                 if (fm && dev_handle->is_meter_flow_id &&
12803                     dev_handle->split_flow_id)
12804                         mlx5_ipool_free(fm->flow_ipool,
12805                                         dev_handle->split_flow_id);
12806                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12807                            tmp_idx);
12808         }
12809         if (srss)
12810                 flow_dv_shared_rss_action_release(dev, srss);
12811 }
12812
12813 /**
12814  * Release array of hash RX queue objects.
12815  * Helper function.
12816  *
12817  * @param[in] dev
12818  *   Pointer to the Ethernet device structure.
12819  * @param[in, out] hrxqs
12820  *   Array of hash RX queue objects.
12821  *
12822  * @return
12823  *   Total number of references to hash RX queue objects in *hrxqs* array
12824  *   after this operation.
12825  */
12826 static int
12827 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12828                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12829 {
12830         size_t i;
12831         int remaining = 0;
12832
12833         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12834                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12835
12836                 if (!ret)
12837                         (*hrxqs)[i] = 0;
12838                 remaining += ret;
12839         }
12840         return remaining;
12841 }
12842
12843 /**
12844  * Release all hash RX queue objects representing shared RSS action.
12845  *
12846  * @param[in] dev
12847  *   Pointer to the Ethernet device structure.
12848  * @param[in, out] action
12849  *   Shared RSS action to remove hash RX queue objects from.
12850  *
12851  * @return
12852  *   Total number of references to hash RX queue objects stored in *action*
12853  *   after this operation.
12854  *   Expected to be 0 if no external references held.
12855  */
12856 static int
12857 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12858                                  struct mlx5_shared_action_rss *shared_rss)
12859 {
12860         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12861 }
12862
12863 /**
12864  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12865  * user input.
12866  *
12867  * Only one hash value is available for one L3+L4 combination:
12868  * for example:
12869  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12870  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12871  * same slot in mlx5_rss_hash_fields.
12872  *
12873  * @param[in] rss
12874  *   Pointer to the shared action RSS conf.
12875  * @param[in, out] hash_field
12876  *   hash_field variable needed to be adjusted.
12877  *
12878  * @return
12879  *   void
12880  */
12881 static void
12882 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12883                                      uint64_t *hash_field)
12884 {
12885         uint64_t rss_types = rss->origin.types;
12886
12887         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12888         case MLX5_RSS_HASH_IPV4:
12889                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12890                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12891                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12892                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12893                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12894                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12895                         else
12896                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12897                 }
12898                 return;
12899         case MLX5_RSS_HASH_IPV6:
12900                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12901                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12902                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12903                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12904                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12905                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12906                         else
12907                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12908                 }
12909                 return;
12910         case MLX5_RSS_HASH_IPV4_UDP:
12911                 /* fall-through. */
12912         case MLX5_RSS_HASH_IPV6_UDP:
12913                 if (rss_types & ETH_RSS_UDP) {
12914                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12915                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12916                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12917                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12918                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12919                         else
12920                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12921                 }
12922                 return;
12923         case MLX5_RSS_HASH_IPV4_TCP:
12924                 /* fall-through. */
12925         case MLX5_RSS_HASH_IPV6_TCP:
12926                 if (rss_types & ETH_RSS_TCP) {
12927                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12928                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12929                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12930                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12931                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12932                         else
12933                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12934                 }
12935                 return;
12936         default:
12937                 return;
12938         }
12939 }
12940
12941 /**
12942  * Setup shared RSS action.
12943  * Prepare set of hash RX queue objects sufficient to handle all valid
12944  * hash_fields combinations (see enum ibv_rx_hash_fields).
12945  *
12946  * @param[in] dev
12947  *   Pointer to the Ethernet device structure.
12948  * @param[in] action_idx
12949  *   Shared RSS action ipool index.
12950  * @param[in, out] action
12951  *   Partially initialized shared RSS action.
12952  * @param[out] error
12953  *   Perform verbose error reporting if not NULL. Initialized in case of
12954  *   error only.
12955  *
12956  * @return
12957  *   0 on success, otherwise negative errno value.
12958  */
12959 static int
12960 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12961                            uint32_t action_idx,
12962                            struct mlx5_shared_action_rss *shared_rss,
12963                            struct rte_flow_error *error)
12964 {
12965         struct mlx5_flow_rss_desc rss_desc = { 0 };
12966         size_t i;
12967         int err;
12968
12969         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12970                 return rte_flow_error_set(error, rte_errno,
12971                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12972                                           "cannot setup indirection table");
12973         }
12974         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12975         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12976         rss_desc.const_q = shared_rss->origin.queue;
12977         rss_desc.queue_num = shared_rss->origin.queue_num;
12978         /* Set non-zero value to indicate a shared RSS. */
12979         rss_desc.shared_rss = action_idx;
12980         rss_desc.ind_tbl = shared_rss->ind_tbl;
12981         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12982                 uint32_t hrxq_idx;
12983                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12984                 int tunnel = 0;
12985
12986                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12987                 if (shared_rss->origin.level > 1) {
12988                         hash_fields |= IBV_RX_HASH_INNER;
12989                         tunnel = 1;
12990                 }
12991                 rss_desc.tunnel = tunnel;
12992                 rss_desc.hash_fields = hash_fields;
12993                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12994                 if (!hrxq_idx) {
12995                         rte_flow_error_set
12996                                 (error, rte_errno,
12997                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12998                                  "cannot get hash queue");
12999                         goto error_hrxq_new;
13000                 }
13001                 err = __flow_dv_action_rss_hrxq_set
13002                         (shared_rss, hash_fields, hrxq_idx);
13003                 MLX5_ASSERT(!err);
13004         }
13005         return 0;
13006 error_hrxq_new:
13007         err = rte_errno;
13008         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13009         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13010                 shared_rss->ind_tbl = NULL;
13011         rte_errno = err;
13012         return -rte_errno;
13013 }
13014
13015 /**
13016  * Create shared RSS action.
13017  *
13018  * @param[in] dev
13019  *   Pointer to the Ethernet device structure.
13020  * @param[in] conf
13021  *   Shared action configuration.
13022  * @param[in] rss
13023  *   RSS action specification used to create shared action.
13024  * @param[out] error
13025  *   Perform verbose error reporting if not NULL. Initialized in case of
13026  *   error only.
13027  *
13028  * @return
13029  *   A valid shared action ID in case of success, 0 otherwise and
13030  *   rte_errno is set.
13031  */
13032 static uint32_t
13033 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13034                             const struct rte_flow_indir_action_conf *conf,
13035                             const struct rte_flow_action_rss *rss,
13036                             struct rte_flow_error *error)
13037 {
13038         struct mlx5_priv *priv = dev->data->dev_private;
13039         struct mlx5_shared_action_rss *shared_rss = NULL;
13040         void *queue = NULL;
13041         struct rte_flow_action_rss *origin;
13042         const uint8_t *rss_key;
13043         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13044         uint32_t idx;
13045
13046         RTE_SET_USED(conf);
13047         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13048                             0, SOCKET_ID_ANY);
13049         shared_rss = mlx5_ipool_zmalloc
13050                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13051         if (!shared_rss || !queue) {
13052                 rte_flow_error_set(error, ENOMEM,
13053                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13054                                    "cannot allocate resource memory");
13055                 goto error_rss_init;
13056         }
13057         if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13058                 rte_flow_error_set(error, E2BIG,
13059                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13060                                    "rss action number out of range");
13061                 goto error_rss_init;
13062         }
13063         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13064                                           sizeof(*shared_rss->ind_tbl),
13065                                           0, SOCKET_ID_ANY);
13066         if (!shared_rss->ind_tbl) {
13067                 rte_flow_error_set(error, ENOMEM,
13068                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13069                                    "cannot allocate resource memory");
13070                 goto error_rss_init;
13071         }
13072         memcpy(queue, rss->queue, queue_size);
13073         shared_rss->ind_tbl->queues = queue;
13074         shared_rss->ind_tbl->queues_n = rss->queue_num;
13075         origin = &shared_rss->origin;
13076         origin->func = rss->func;
13077         origin->level = rss->level;
13078         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13079         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13080         /* NULL RSS key indicates default RSS key. */
13081         rss_key = !rss->key ? rss_hash_default_key : rss->key;
13082         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13083         origin->key = &shared_rss->key[0];
13084         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13085         origin->queue = queue;
13086         origin->queue_num = rss->queue_num;
13087         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13088                 goto error_rss_init;
13089         rte_spinlock_init(&shared_rss->action_rss_sl);
13090         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13091         rte_spinlock_lock(&priv->shared_act_sl);
13092         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13093                      &priv->rss_shared_actions, idx, shared_rss, next);
13094         rte_spinlock_unlock(&priv->shared_act_sl);
13095         return idx;
13096 error_rss_init:
13097         if (shared_rss) {
13098                 if (shared_rss->ind_tbl)
13099                         mlx5_free(shared_rss->ind_tbl);
13100                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13101                                 idx);
13102         }
13103         if (queue)
13104                 mlx5_free(queue);
13105         return 0;
13106 }
13107
13108 /**
13109  * Destroy the shared RSS action.
13110  * Release related hash RX queue objects.
13111  *
13112  * @param[in] dev
13113  *   Pointer to the Ethernet device structure.
13114  * @param[in] idx
13115  *   The shared RSS action object ID to be removed.
13116  * @param[out] error
13117  *   Perform verbose error reporting if not NULL. Initialized in case of
13118  *   error only.
13119  *
13120  * @return
13121  *   0 on success, otherwise negative errno value.
13122  */
13123 static int
13124 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13125                              struct rte_flow_error *error)
13126 {
13127         struct mlx5_priv *priv = dev->data->dev_private;
13128         struct mlx5_shared_action_rss *shared_rss =
13129             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13130         uint32_t old_refcnt = 1;
13131         int remaining;
13132         uint16_t *queue = NULL;
13133
13134         if (!shared_rss)
13135                 return rte_flow_error_set(error, EINVAL,
13136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13137                                           "invalid shared action");
13138         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13139         if (remaining)
13140                 return rte_flow_error_set(error, EBUSY,
13141                                           RTE_FLOW_ERROR_TYPE_ACTION,
13142                                           NULL,
13143                                           "shared rss hrxq has references");
13144         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13145                                          0, 0, __ATOMIC_ACQUIRE,
13146                                          __ATOMIC_RELAXED))
13147                 return rte_flow_error_set(error, EBUSY,
13148                                           RTE_FLOW_ERROR_TYPE_ACTION,
13149                                           NULL,
13150                                           "shared rss has references");
13151         queue = shared_rss->ind_tbl->queues;
13152         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13153         if (remaining)
13154                 return rte_flow_error_set(error, EBUSY,
13155                                           RTE_FLOW_ERROR_TYPE_ACTION,
13156                                           NULL,
13157                                           "shared rss indirection table has"
13158                                           " references");
13159         mlx5_free(queue);
13160         rte_spinlock_lock(&priv->shared_act_sl);
13161         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13162                      &priv->rss_shared_actions, idx, shared_rss, next);
13163         rte_spinlock_unlock(&priv->shared_act_sl);
13164         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13165                         idx);
13166         return 0;
13167 }
13168
13169 /**
13170  * Create indirect action, lock free,
13171  * (mutex should be acquired by caller).
13172  * Dispatcher for action type specific call.
13173  *
13174  * @param[in] dev
13175  *   Pointer to the Ethernet device structure.
13176  * @param[in] conf
13177  *   Shared action configuration.
13178  * @param[in] action
13179  *   Action specification used to create indirect action.
13180  * @param[out] error
13181  *   Perform verbose error reporting if not NULL. Initialized in case of
13182  *   error only.
13183  *
13184  * @return
13185  *   A valid shared action handle in case of success, NULL otherwise and
13186  *   rte_errno is set.
13187  */
13188 static struct rte_flow_action_handle *
13189 flow_dv_action_create(struct rte_eth_dev *dev,
13190                       const struct rte_flow_indir_action_conf *conf,
13191                       const struct rte_flow_action *action,
13192                       struct rte_flow_error *err)
13193 {
13194         uint32_t idx = 0;
13195         uint32_t ret = 0;
13196
13197         switch (action->type) {
13198         case RTE_FLOW_ACTION_TYPE_RSS:
13199                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13200                 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13201                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13202                 break;
13203         case RTE_FLOW_ACTION_TYPE_AGE:
13204                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13205                 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13206                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13207                 if (ret) {
13208                         struct mlx5_aso_age_action *aso_age =
13209                                               flow_aso_age_get_by_idx(dev, ret);
13210
13211                         if (!aso_age->age_params.context)
13212                                 aso_age->age_params.context =
13213                                                          (void *)(uintptr_t)idx;
13214                 }
13215                 break;
13216         default:
13217                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13218                                    NULL, "action type not supported");
13219                 break;
13220         }
13221         return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13222 }
13223
13224 /**
13225  * Destroy the indirect action.
13226  * Release action related resources on the NIC and the memory.
13227  * Lock free, (mutex should be acquired by caller).
13228  * Dispatcher for action type specific call.
13229  *
13230  * @param[in] dev
13231  *   Pointer to the Ethernet device structure.
13232  * @param[in] handle
13233  *   The indirect action object handle to be removed.
13234  * @param[out] error
13235  *   Perform verbose error reporting if not NULL. Initialized in case of
13236  *   error only.
13237  *
13238  * @return
13239  *   0 on success, otherwise negative errno value.
13240  */
13241 static int
13242 flow_dv_action_destroy(struct rte_eth_dev *dev,
13243                        struct rte_flow_action_handle *handle,
13244                        struct rte_flow_error *error)
13245 {
13246         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13247         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13248         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13249         int ret;
13250
13251         switch (type) {
13252         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13253                 return __flow_dv_action_rss_release(dev, idx, error);
13254         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13255                 ret = flow_dv_aso_age_release(dev, idx);
13256                 if (ret)
13257                         /*
13258                          * In this case, the last flow has a reference will
13259                          * actually release the age action.
13260                          */
13261                         DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13262                                 " released with references %d.", idx, ret);
13263                 return 0;
13264         default:
13265                 return rte_flow_error_set(error, ENOTSUP,
13266                                           RTE_FLOW_ERROR_TYPE_ACTION,
13267                                           NULL,
13268                                           "action type not supported");
13269         }
13270 }
13271
13272 /**
13273  * Updates in place shared RSS action configuration.
13274  *
13275  * @param[in] dev
13276  *   Pointer to the Ethernet device structure.
13277  * @param[in] idx
13278  *   The shared RSS action object ID to be updated.
13279  * @param[in] action_conf
13280  *   RSS action specification used to modify *shared_rss*.
13281  * @param[out] error
13282  *   Perform verbose error reporting if not NULL. Initialized in case of
13283  *   error only.
13284  *
13285  * @return
13286  *   0 on success, otherwise negative errno value.
13287  * @note: currently only support update of RSS queues.
13288  */
13289 static int
13290 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13291                             const struct rte_flow_action_rss *action_conf,
13292                             struct rte_flow_error *error)
13293 {
13294         struct mlx5_priv *priv = dev->data->dev_private;
13295         struct mlx5_shared_action_rss *shared_rss =
13296             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13297         int ret = 0;
13298         void *queue = NULL;
13299         uint16_t *queue_old = NULL;
13300         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13301
13302         if (!shared_rss)
13303                 return rte_flow_error_set(error, EINVAL,
13304                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13305                                           "invalid shared action to update");
13306         if (priv->obj_ops.ind_table_modify == NULL)
13307                 return rte_flow_error_set(error, ENOTSUP,
13308                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13309                                           "cannot modify indirection table");
13310         queue = mlx5_malloc(MLX5_MEM_ZERO,
13311                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13312                             0, SOCKET_ID_ANY);
13313         if (!queue)
13314                 return rte_flow_error_set(error, ENOMEM,
13315                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13316                                           NULL,
13317                                           "cannot allocate resource memory");
13318         memcpy(queue, action_conf->queue, queue_size);
13319         MLX5_ASSERT(shared_rss->ind_tbl);
13320         rte_spinlock_lock(&shared_rss->action_rss_sl);
13321         queue_old = shared_rss->ind_tbl->queues;
13322         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13323                                         queue, action_conf->queue_num, true);
13324         if (ret) {
13325                 mlx5_free(queue);
13326                 ret = rte_flow_error_set(error, rte_errno,
13327                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13328                                           "cannot update indirection table");
13329         } else {
13330                 mlx5_free(queue_old);
13331                 shared_rss->origin.queue = queue;
13332                 shared_rss->origin.queue_num = action_conf->queue_num;
13333         }
13334         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13335         return ret;
13336 }
13337
13338 /**
13339  * Updates in place shared action configuration, lock free,
13340  * (mutex should be acquired by caller).
13341  *
13342  * @param[in] dev
13343  *   Pointer to the Ethernet device structure.
13344  * @param[in] handle
13345  *   The indirect action object handle to be updated.
13346  * @param[in] update
13347  *   Action specification used to modify the action pointed by *handle*.
13348  *   *update* could be of same type with the action pointed by the *handle*
13349  *   handle argument, or some other structures like a wrapper, depending on
13350  *   the indirect action type.
13351  * @param[out] error
13352  *   Perform verbose error reporting if not NULL. Initialized in case of
13353  *   error only.
13354  *
13355  * @return
13356  *   0 on success, otherwise negative errno value.
13357  */
13358 static int
13359 flow_dv_action_update(struct rte_eth_dev *dev,
13360                         struct rte_flow_action_handle *handle,
13361                         const void *update,
13362                         struct rte_flow_error *err)
13363 {
13364         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13365         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13366         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13367         const void *action_conf;
13368
13369         switch (type) {
13370         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13371                 action_conf = ((const struct rte_flow_action *)update)->conf;
13372                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13373         default:
13374                 return rte_flow_error_set(err, ENOTSUP,
13375                                           RTE_FLOW_ERROR_TYPE_ACTION,
13376                                           NULL,
13377                                           "action type update not supported");
13378         }
13379 }
13380
13381 static int
13382 flow_dv_action_query(struct rte_eth_dev *dev,
13383                      const struct rte_flow_action_handle *handle, void *data,
13384                      struct rte_flow_error *error)
13385 {
13386         struct mlx5_age_param *age_param;
13387         struct rte_flow_query_age *resp;
13388         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13389         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13390         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13391
13392         switch (type) {
13393         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13394                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13395                 resp = data;
13396                 resp->aged = __atomic_load_n(&age_param->state,
13397                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13398                                                                           1 : 0;
13399                 resp->sec_since_last_hit_valid = !resp->aged;
13400                 if (resp->sec_since_last_hit_valid)
13401                         resp->sec_since_last_hit = __atomic_load_n
13402                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13403                 return 0;
13404         default:
13405                 return rte_flow_error_set(error, ENOTSUP,
13406                                           RTE_FLOW_ERROR_TYPE_ACTION,
13407                                           NULL,
13408                                           "action type query not supported");
13409         }
13410 }
13411
13412 /**
13413  * Query a dv flow  rule for its statistics via devx.
13414  *
13415  * @param[in] dev
13416  *   Pointer to Ethernet device.
13417  * @param[in] flow
13418  *   Pointer to the sub flow.
13419  * @param[out] data
13420  *   data retrieved by the query.
13421  * @param[out] error
13422  *   Perform verbose error reporting if not NULL.
13423  *
13424  * @return
13425  *   0 on success, a negative errno value otherwise and rte_errno is set.
13426  */
13427 static int
13428 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13429                     void *data, struct rte_flow_error *error)
13430 {
13431         struct mlx5_priv *priv = dev->data->dev_private;
13432         struct rte_flow_query_count *qc = data;
13433
13434         if (!priv->config.devx)
13435                 return rte_flow_error_set(error, ENOTSUP,
13436                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13437                                           NULL,
13438                                           "counters are not supported");
13439         if (flow->counter) {
13440                 uint64_t pkts, bytes;
13441                 struct mlx5_flow_counter *cnt;
13442
13443                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13444                                                  NULL);
13445                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13446                                                &bytes);
13447
13448                 if (err)
13449                         return rte_flow_error_set(error, -err,
13450                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13451                                         NULL, "cannot read counters");
13452                 qc->hits_set = 1;
13453                 qc->bytes_set = 1;
13454                 qc->hits = pkts - cnt->hits;
13455                 qc->bytes = bytes - cnt->bytes;
13456                 if (qc->reset) {
13457                         cnt->hits = pkts;
13458                         cnt->bytes = bytes;
13459                 }
13460                 return 0;
13461         }
13462         return rte_flow_error_set(error, EINVAL,
13463                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13464                                   NULL,
13465                                   "counters are not available");
13466 }
13467
13468 /**
13469  * Query a flow rule AGE action for aging information.
13470  *
13471  * @param[in] dev
13472  *   Pointer to Ethernet device.
13473  * @param[in] flow
13474  *   Pointer to the sub flow.
13475  * @param[out] data
13476  *   data retrieved by the query.
13477  * @param[out] error
13478  *   Perform verbose error reporting if not NULL.
13479  *
13480  * @return
13481  *   0 on success, a negative errno value otherwise and rte_errno is set.
13482  */
13483 static int
13484 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13485                   void *data, struct rte_flow_error *error)
13486 {
13487         struct rte_flow_query_age *resp = data;
13488         struct mlx5_age_param *age_param;
13489
13490         if (flow->age) {
13491                 struct mlx5_aso_age_action *act =
13492                                      flow_aso_age_get_by_idx(dev, flow->age);
13493
13494                 age_param = &act->age_params;
13495         } else if (flow->counter) {
13496                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13497
13498                 if (!age_param || !age_param->timeout)
13499                         return rte_flow_error_set
13500                                         (error, EINVAL,
13501                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13502                                          NULL, "cannot read age data");
13503         } else {
13504                 return rte_flow_error_set(error, EINVAL,
13505                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13506                                           NULL, "age data not available");
13507         }
13508         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13509                                      AGE_TMOUT ? 1 : 0;
13510         resp->sec_since_last_hit_valid = !resp->aged;
13511         if (resp->sec_since_last_hit_valid)
13512                 resp->sec_since_last_hit = __atomic_load_n
13513                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13514         return 0;
13515 }
13516
13517 /**
13518  * Query a flow.
13519  *
13520  * @see rte_flow_query()
13521  * @see rte_flow_ops
13522  */
13523 static int
13524 flow_dv_query(struct rte_eth_dev *dev,
13525               struct rte_flow *flow __rte_unused,
13526               const struct rte_flow_action *actions __rte_unused,
13527               void *data __rte_unused,
13528               struct rte_flow_error *error __rte_unused)
13529 {
13530         int ret = -EINVAL;
13531
13532         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13533                 switch (actions->type) {
13534                 case RTE_FLOW_ACTION_TYPE_VOID:
13535                         break;
13536                 case RTE_FLOW_ACTION_TYPE_COUNT:
13537                         ret = flow_dv_query_count(dev, flow, data, error);
13538                         break;
13539                 case RTE_FLOW_ACTION_TYPE_AGE:
13540                         ret = flow_dv_query_age(dev, flow, data, error);
13541                         break;
13542                 default:
13543                         return rte_flow_error_set(error, ENOTSUP,
13544                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13545                                                   actions,
13546                                                   "action not supported");
13547                 }
13548         }
13549         return ret;
13550 }
13551
13552 /**
13553  * Destroy the meter table set.
13554  * Lock free, (mutex should be acquired by caller).
13555  *
13556  * @param[in] dev
13557  *   Pointer to Ethernet device.
13558  * @param[in] tbl
13559  *   Pointer to the meter table set.
13560  *
13561  * @return
13562  *   Always 0.
13563  */
13564 static int
13565 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13566                         struct mlx5_meter_domains_infos *tbl)
13567 {
13568         struct mlx5_priv *priv = dev->data->dev_private;
13569         struct mlx5_meter_domains_infos *mtd =
13570                                 (struct mlx5_meter_domains_infos *)tbl;
13571
13572         if (!mtd || !priv->config.dv_flow_en)
13573                 return 0;
13574         if (mtd->egress.tbl)
13575                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13576         if (mtd->egress.sfx_tbl)
13577                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13578         if (mtd->ingress.tbl)
13579                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13580         if (mtd->ingress.sfx_tbl)
13581                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13582                                              mtd->ingress.sfx_tbl);
13583         if (mtd->transfer.tbl)
13584                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13585         if (mtd->transfer.sfx_tbl)
13586                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13587                                              mtd->transfer.sfx_tbl);
13588         mlx5_free(mtd);
13589         return 0;
13590 }
13591
13592 /* Number of meter flow actions, count and jump or count and drop. */
13593 #define METER_ACTIONS 2
13594
13595 /**
13596  * Create specify domain meter table and suffix table.
13597  *
13598  * @param[in] dev
13599  *   Pointer to Ethernet device.
13600  * @param[in,out] mtb
13601  *   Pointer to DV meter table set.
13602  * @param[in] egress
13603  *   Table attribute.
13604  * @param[in] transfer
13605  *   Table attribute.
13606  *
13607  * @return
13608  *   0 on success, -1 otherwise.
13609  */
13610 static int
13611 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13612                            struct mlx5_meter_domains_infos *mtb,
13613                            uint8_t egress, uint8_t transfer)
13614 {
13615         struct rte_flow_error error;
13616         struct mlx5_meter_domain_info *dtb;
13617
13618         if (transfer)
13619                 dtb = &mtb->transfer;
13620         else if (egress)
13621                 dtb = &mtb->egress;
13622         else
13623                 dtb = &mtb->ingress;
13624         /* Create the meter table with METER level. */
13625         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13626                                             egress, transfer, false, NULL, 0,
13627                                             0, 0, &error);
13628         if (!dtb->tbl) {
13629                 DRV_LOG(ERR, "Failed to create meter policer table.");
13630                 return -1;
13631         }
13632         /* Create the meter suffix table with SUFFIX level. */
13633         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13634                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13635                                             egress, transfer, false, NULL, 0,
13636                                             0, 0, &error);
13637         if (!dtb->sfx_tbl) {
13638                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13639                 return -1;
13640         }
13641         return 0;
13642 }
13643
13644 /**
13645  * Create the needed meter and suffix tables.
13646  * Lock free, (mutex should be acquired by caller).
13647  *
13648  * @param[in] dev
13649  *   Pointer to Ethernet device.
13650  *
13651  * @return
13652  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13653  */
13654 static struct mlx5_meter_domains_infos *
13655 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13656 {
13657         struct mlx5_priv *priv = dev->data->dev_private;
13658         struct mlx5_meter_domains_infos *mtb;
13659         int ret;
13660
13661         if (!priv->mtr_en) {
13662                 rte_errno = ENOTSUP;
13663                 return NULL;
13664         }
13665         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13666         if (!mtb) {
13667                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13668                 return NULL;
13669         }
13670         /* Egress meter table. */
13671         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13672         if (ret) {
13673                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13674                 goto error_exit;
13675         }
13676         /* Ingress meter table. */
13677         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13678         if (ret) {
13679                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13680                 goto error_exit;
13681         }
13682         /* FDB meter table. */
13683         if (priv->config.dv_esw_en) {
13684                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13685                 if (ret) {
13686                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13687                         goto error_exit;
13688                 }
13689         }
13690         return mtb;
13691 error_exit:
13692         flow_dv_destroy_mtr_tbl(dev, mtb);
13693         return NULL;
13694 }
13695
13696 /**
13697  * Validate the batch counter support in root table.
13698  *
13699  * Create a simple flow with invalid counter and drop action on root table to
13700  * validate if batch counter with offset on root table is supported or not.
13701  *
13702  * @param[in] dev
13703  *   Pointer to rte_eth_dev structure.
13704  *
13705  * @return
13706  *   0 on success, a negative errno value otherwise and rte_errno is set.
13707  */
13708 int
13709 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13710 {
13711         struct mlx5_priv *priv = dev->data->dev_private;
13712         struct mlx5_dev_ctx_shared *sh = priv->sh;
13713         struct mlx5_flow_dv_match_params mask = {
13714                 .size = sizeof(mask.buf),
13715         };
13716         struct mlx5_flow_dv_match_params value = {
13717                 .size = sizeof(value.buf),
13718         };
13719         struct mlx5dv_flow_matcher_attr dv_attr = {
13720                 .type = IBV_FLOW_ATTR_NORMAL,
13721                 .priority = 0,
13722                 .match_criteria_enable = 0,
13723                 .match_mask = (void *)&mask,
13724         };
13725         void *actions[2] = { 0 };
13726         struct mlx5_flow_tbl_resource *tbl = NULL;
13727         struct mlx5_devx_obj *dcs = NULL;
13728         void *matcher = NULL;
13729         void *flow = NULL;
13730         int ret = -1;
13731
13732         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
13733                                         0, 0, 0, NULL);
13734         if (!tbl)
13735                 goto err;
13736         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13737         if (!dcs)
13738                 goto err;
13739         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13740                                                     &actions[0]);
13741         if (ret)
13742                 goto err;
13743         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13744                                           priv->drop_queue.hrxq->action;
13745         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13746         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13747                                                &matcher);
13748         if (ret)
13749                 goto err;
13750         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13751                                        actions, &flow);
13752 err:
13753         /*
13754          * If batch counter with offset is not supported, the driver will not
13755          * validate the invalid offset value, flow create should success.
13756          * In this case, it means batch counter is not supported in root table.
13757          *
13758          * Otherwise, if flow create is failed, counter offset is supported.
13759          */
13760         if (flow) {
13761                 DRV_LOG(INFO, "Batch counter is not supported in root "
13762                               "table. Switch to fallback mode.");
13763                 rte_errno = ENOTSUP;
13764                 ret = -rte_errno;
13765                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13766         } else {
13767                 /* Check matcher to make sure validate fail at flow create. */
13768                 if (!matcher || (matcher && errno != EINVAL))
13769                         DRV_LOG(ERR, "Unexpected error in counter offset "
13770                                      "support detection");
13771                 ret = 0;
13772         }
13773         if (actions[0])
13774                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13775         if (matcher)
13776                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13777         if (tbl)
13778                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13779         if (dcs)
13780                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13781         return ret;
13782 }
13783
13784 /**
13785  * Query a devx counter.
13786  *
13787  * @param[in] dev
13788  *   Pointer to the Ethernet device structure.
13789  * @param[in] cnt
13790  *   Index to the flow counter.
13791  * @param[in] clear
13792  *   Set to clear the counter statistics.
13793  * @param[out] pkts
13794  *   The statistics value of packets.
13795  * @param[out] bytes
13796  *   The statistics value of bytes.
13797  *
13798  * @return
13799  *   0 on success, otherwise return -1.
13800  */
13801 static int
13802 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13803                       uint64_t *pkts, uint64_t *bytes)
13804 {
13805         struct mlx5_priv *priv = dev->data->dev_private;
13806         struct mlx5_flow_counter *cnt;
13807         uint64_t inn_pkts, inn_bytes;
13808         int ret;
13809
13810         if (!priv->config.devx)
13811                 return -1;
13812
13813         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13814         if (ret)
13815                 return -1;
13816         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13817         *pkts = inn_pkts - cnt->hits;
13818         *bytes = inn_bytes - cnt->bytes;
13819         if (clear) {
13820                 cnt->hits = inn_pkts;
13821                 cnt->bytes = inn_bytes;
13822         }
13823         return 0;
13824 }
13825
13826 /**
13827  * Get aged-out flows.
13828  *
13829  * @param[in] dev
13830  *   Pointer to the Ethernet device structure.
13831  * @param[in] context
13832  *   The address of an array of pointers to the aged-out flows contexts.
13833  * @param[in] nb_contexts
13834  *   The length of context array pointers.
13835  * @param[out] error
13836  *   Perform verbose error reporting if not NULL. Initialized in case of
13837  *   error only.
13838  *
13839  * @return
13840  *   how many contexts get in success, otherwise negative errno value.
13841  *   if nb_contexts is 0, return the amount of all aged contexts.
13842  *   if nb_contexts is not 0 , return the amount of aged flows reported
13843  *   in the context array.
13844  * @note: only stub for now
13845  */
13846 static int
13847 flow_get_aged_flows(struct rte_eth_dev *dev,
13848                     void **context,
13849                     uint32_t nb_contexts,
13850                     struct rte_flow_error *error)
13851 {
13852         struct mlx5_priv *priv = dev->data->dev_private;
13853         struct mlx5_age_info *age_info;
13854         struct mlx5_age_param *age_param;
13855         struct mlx5_flow_counter *counter;
13856         struct mlx5_aso_age_action *act;
13857         int nb_flows = 0;
13858
13859         if (nb_contexts && !context)
13860                 return rte_flow_error_set(error, EINVAL,
13861                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13862                                           NULL, "empty context");
13863         age_info = GET_PORT_AGE_INFO(priv);
13864         rte_spinlock_lock(&age_info->aged_sl);
13865         LIST_FOREACH(act, &age_info->aged_aso, next) {
13866                 nb_flows++;
13867                 if (nb_contexts) {
13868                         context[nb_flows - 1] =
13869                                                 act->age_params.context;
13870                         if (!(--nb_contexts))
13871                                 break;
13872                 }
13873         }
13874         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13875                 nb_flows++;
13876                 if (nb_contexts) {
13877                         age_param = MLX5_CNT_TO_AGE(counter);
13878                         context[nb_flows - 1] = age_param->context;
13879                         if (!(--nb_contexts))
13880                                 break;
13881                 }
13882         }
13883         rte_spinlock_unlock(&age_info->aged_sl);
13884         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13885         return nb_flows;
13886 }
13887
13888 /*
13889  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13890  */
13891 static uint32_t
13892 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13893 {
13894         return flow_dv_counter_alloc(dev, 0);
13895 }
13896
13897 /**
13898  * Validate indirect action.
13899  * Dispatcher for action type specific validation.
13900  *
13901  * @param[in] dev
13902  *   Pointer to the Ethernet device structure.
13903  * @param[in] conf
13904  *   Shared action configuration.
13905  * @param[in] action
13906  *   The indirect action object to validate.
13907  * @param[out] error
13908  *   Perform verbose error reporting if not NULL. Initialized in case of
13909  *   error only.
13910  *
13911  * @return
13912  *   0 on success, otherwise negative errno value.
13913  */
13914 static int
13915 flow_dv_action_validate(struct rte_eth_dev *dev,
13916                         const struct rte_flow_indir_action_conf *conf,
13917                         const struct rte_flow_action *action,
13918                         struct rte_flow_error *err)
13919 {
13920         struct mlx5_priv *priv = dev->data->dev_private;
13921
13922         RTE_SET_USED(conf);
13923         switch (action->type) {
13924         case RTE_FLOW_ACTION_TYPE_RSS:
13925                 /*
13926                  * priv->obj_ops is set according to driver capabilities.
13927                  * When DevX capabilities are
13928                  * sufficient, it is set to devx_obj_ops.
13929                  * Otherwise, it is set to ibv_obj_ops.
13930                  * ibv_obj_ops doesn't support ind_table_modify operation.
13931                  * In this case the shared RSS action can't be used.
13932                  */
13933                 if (priv->obj_ops.ind_table_modify == NULL)
13934                         return rte_flow_error_set
13935                                         (err, ENOTSUP,
13936                                          RTE_FLOW_ERROR_TYPE_ACTION,
13937                                          NULL,
13938                                          "shared RSS action not supported");
13939                 return mlx5_validate_action_rss(dev, action, err);
13940         case RTE_FLOW_ACTION_TYPE_AGE:
13941                 if (!priv->sh->aso_age_mng)
13942                         return rte_flow_error_set(err, ENOTSUP,
13943                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13944                                                 NULL,
13945                                              "shared age action not supported");
13946                 return flow_dv_validate_action_age(0, action, dev, err);
13947         default:
13948                 return rte_flow_error_set(err, ENOTSUP,
13949                                           RTE_FLOW_ERROR_TYPE_ACTION,
13950                                           NULL,
13951                                           "action type not supported");
13952         }
13953 }
13954
13955 static int
13956 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13957 {
13958         struct mlx5_priv *priv = dev->data->dev_private;
13959         int ret = 0;
13960
13961         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13962                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13963                                                 flags);
13964                 if (ret != 0)
13965                         return ret;
13966         }
13967         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13968                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13969                 if (ret != 0)
13970                         return ret;
13971         }
13972         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13973                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13974                 if (ret != 0)
13975                         return ret;
13976         }
13977         return 0;
13978 }
13979
13980 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13981         .validate = flow_dv_validate,
13982         .prepare = flow_dv_prepare,
13983         .translate = flow_dv_translate,
13984         .apply = flow_dv_apply,
13985         .remove = flow_dv_remove,
13986         .destroy = flow_dv_destroy,
13987         .query = flow_dv_query,
13988         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13989         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13990         .create_meter = flow_dv_mtr_alloc,
13991         .free_meter = flow_dv_aso_mtr_release_to_pool,
13992         .counter_alloc = flow_dv_counter_allocate,
13993         .counter_free = flow_dv_counter_free,
13994         .counter_query = flow_dv_counter_query,
13995         .get_aged_flows = flow_get_aged_flows,
13996         .action_validate = flow_dv_action_validate,
13997         .action_create = flow_dv_action_create,
13998         .action_destroy = flow_dv_action_destroy,
13999         .action_update = flow_dv_action_update,
14000         .action_query = flow_dv_action_query,
14001         .sync_domain = flow_dv_sync_domain,
14002 };
14003
14004 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14005