drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36
  37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  38
  39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  41 #endif
  42
  43 #ifndef HAVE_MLX5DV_DR_ESWITCH
  44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  46 #endif
  47 #endif
  48
  49 #ifndef HAVE_MLX5DV_DR
  50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  51 #endif
  52
  53 /* VLAN header definitions */
  54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  59
  60 union flow_dv_attr {
  61         struct {
  62                 uint32_t valid:1;
  63                 uint32_t ipv4:1;
  64                 uint32_t ipv6:1;
  65                 uint32_t tcp:1;
  66                 uint32_t udp:1;
  67                 uint32_t reserved:27;
  68         };
  69         uint32_t attr;
  70 };
  71
  72 static int
  73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  74                              struct mlx5_flow_tbl_resource *tbl);
  75
  76 static int
  77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
  78
  79 /**
  80  * Initialize flow attributes structure according to flow items' types.
  81  *
  82  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  83  * mode. For tunnel mode, the items to be modified are the outermost ones.
  84  *
  85  * @param[in] item
  86  *   Pointer to item specification.
  87  * @param[out] attr
  88  *   Pointer to flow attributes structure.
  89  * @param[in] dev_flow
  90  *   Pointer to the sub flow.
  91  * @param[in] tunnel_decap
  92  *   Whether action is after tunnel decapsulation.
  93  */
  94 static void
  95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  96                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  97 {
  98         uint64_t layers = dev_flow->handle->layers;
  99
 100         /*
 101          * If layers is already initialized, it means this dev_flow is the
 102          * suffix flow, the layers flags is set by the prefix flow. Need to
 103          * use the layer flags from prefix flow as the suffix flow may not
 104          * have the user defined items as the flow is split.
 105          */
 106         if (layers) {
 107                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 108                         attr->ipv4 = 1;
 109                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 110                         attr->ipv6 = 1;
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 112                         attr->tcp = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 114                         attr->udp = 1;
 115                 attr->valid = 1;
 116                 return;
 117         }
 118         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 119                 uint8_t next_protocol = 0xff;
 120                 switch (item->type) {
 121                 case RTE_FLOW_ITEM_TYPE_GRE:
 122                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 123                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 125                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 126                 case RTE_FLOW_ITEM_TYPE_MPLS:
 127                         if (tunnel_decap)
 128                                 attr->attr = 0;
 129                         break;
 130                 case RTE_FLOW_ITEM_TYPE_IPV4:
 131                         if (!attr->ipv6)
 132                                 attr->ipv4 = 1;
 133                         if (item->mask != NULL &&
 134                             ((const struct rte_flow_item_ipv4 *)
 135                             item->mask)->hdr.next_proto_id)
 136                                 next_protocol =
 137                                     ((const struct rte_flow_item_ipv4 *)
 138                                       (item->spec))->hdr.next_proto_id &
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->mask))->hdr.next_proto_id;
 141                         if ((next_protocol == IPPROTO_IPIP ||
 142                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 143                                 attr->attr = 0;
 144                         break;
 145                 case RTE_FLOW_ITEM_TYPE_IPV6:
 146                         if (!attr->ipv4)
 147                                 attr->ipv6 = 1;
 148                         if (item->mask != NULL &&
 149                             ((const struct rte_flow_item_ipv6 *)
 150                             item->mask)->hdr.proto)
 151                                 next_protocol =
 152                                     ((const struct rte_flow_item_ipv6 *)
 153                                       (item->spec))->hdr.proto &
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->mask))->hdr.proto;
 156                         if ((next_protocol == IPPROTO_IPIP ||
 157                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 158                                 attr->attr = 0;
 159                         break;
 160                 case RTE_FLOW_ITEM_TYPE_UDP:
 161                         if (!attr->tcp)
 162                                 attr->udp = 1;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_TCP:
 165                         if (!attr->udp)
 166                                 attr->tcp = 1;
 167                         break;
 168                 default:
 169                         break;
 170                 }
 171         }
 172         attr->valid = 1;
 173 }
 174
 175 /**
 176  * Convert rte_mtr_color to mlx5 color.
 177  *
 178  * @param[in] rcol
 179  *   rte_mtr_color.
 180  *
 181  * @return
 182  *   mlx5 color.
 183  */
 184 static int
 185 rte_col_2_mlx5_col(enum rte_color rcol)
 186 {
 187         switch (rcol) {
 188         case RTE_COLOR_GREEN:
 189                 return MLX5_FLOW_COLOR_GREEN;
 190         case RTE_COLOR_YELLOW:
 191                 return MLX5_FLOW_COLOR_YELLOW;
 192         case RTE_COLOR_RED:
 193                 return MLX5_FLOW_COLOR_RED;
 194         default:
 195                 break;
 196         }
 197         return MLX5_FLOW_COLOR_UNDEFINED;
 198 }
 199
 200 struct field_modify_info {
 201         uint32_t size; /* Size of field in protocol header, in bytes. */
 202         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 203         enum mlx5_modification_field id;
 204 };
 205
 206 struct field_modify_info modify_eth[] = {
 207         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 208         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 209         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 210         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 211         {0, 0, 0},
 212 };
 213
 214 struct field_modify_info modify_vlan_out_first_vid[] = {
 215         /* Size in bits !!! */
 216         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_ipv4[] = {
 221         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 222         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 223         {4, 12, MLX5_MODI_OUT_SIPV4},
 224         {4, 16, MLX5_MODI_OUT_DIPV4},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv6[] = {
 229         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 231         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 232         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 233         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 234         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 235         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 236         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 237         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 238         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 239         {0, 0, 0},
 240 };
 241
 242 struct field_modify_info modify_udp[] = {
 243         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 244         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_tcp[] = {
 249         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 251         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 252         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 253         {0, 0, 0},
 254 };
 255
 256 static void
 257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 258                           uint8_t next_protocol, uint64_t *item_flags,
 259                           int *tunnel)
 260 {
 261         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 262                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 263         if (next_protocol == IPPROTO_IPIP) {
 264                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 265                 *tunnel = 1;
 266         }
 267         if (next_protocol == IPPROTO_IPV6) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 269                 *tunnel = 1;
 270         }
 271 }
 272
 273 /**
 274  * Acquire the synchronizing object to protect multithreaded access
 275  * to shared dv context. Lock occurs only if context is actually
 276  * shared, i.e. we have multiport IB device and representors are
 277  * created.
 278  *
 279  * @param[in] dev
 280  *   Pointer to the rte_eth_dev structure.
 281  */
 282 static void
 283 flow_dv_shared_lock(struct rte_eth_dev *dev)
 284 {
 285         struct mlx5_priv *priv = dev->data->dev_private;
 286         struct mlx5_dev_ctx_shared *sh = priv->sh;
 287
 288         if (sh->dv_refcnt > 1) {
 289                 int ret;
 290
 291                 ret = pthread_mutex_lock(&sh->dv_mutex);
 292                 MLX5_ASSERT(!ret);
 293                 (void)ret;
 294         }
 295 }
 296
 297 static void
 298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 299 {
 300         struct mlx5_priv *priv = dev->data->dev_private;
 301         struct mlx5_dev_ctx_shared *sh = priv->sh;
 302
 303         if (sh->dv_refcnt > 1) {
 304                 int ret;
 305
 306                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 307                 MLX5_ASSERT(!ret);
 308                 (void)ret;
 309         }
 310 }
 311
 312 /* Update VLAN's VID/PCP based on input rte_flow_action.
 313  *
 314  * @param[in] action
 315  *   Pointer to struct rte_flow_action.
 316  * @param[out] vlan
 317  *   Pointer to struct rte_vlan_hdr.
 318  */
 319 static void
 320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 321                          struct rte_vlan_hdr *vlan)
 322 {
 323         uint16_t vlan_tci;
 324         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 325                 vlan_tci =
 326                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 327                                                action->conf)->vlan_pcp;
 328                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 329                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 330                 vlan->vlan_tci |= vlan_tci;
 331         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 332                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 333                 vlan->vlan_tci |= rte_be_to_cpu_16
 334                     (((const struct rte_flow_action_of_set_vlan_vid *)
 335                                              action->conf)->vlan_vid);
 336         }
 337 }
 338
 339 /**
 340  * Fetch 1, 2, 3 or 4 byte field from the byte array
 341  * and return as unsigned integer in host-endian format.
 342  *
 343  * @param[in] data
 344  *   Pointer to data array.
 345  * @param[in] size
 346  *   Size of field to extract.
 347  *
 348  * @return
 349  *   converted field in host endian format.
 350  */
 351 static inline uint32_t
 352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 353 {
 354         uint32_t ret;
 355
 356         switch (size) {
 357         case 1:
 358                 ret = *data;
 359                 break;
 360         case 2:
 361                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 362                 break;
 363         case 3:
 364                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 365                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 366                 break;
 367         case 4:
 368                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 369                 break;
 370         default:
 371                 MLX5_ASSERT(false);
 372                 ret = 0;
 373                 break;
 374         }
 375         return ret;
 376 }
 377
 378 /**
 379  * Convert modify-header action to DV specification.
 380  *
 381  * Data length of each action is determined by provided field description
 382  * and the item mask. Data bit offset and width of each action is determined
 383  * by provided item mask.
 384  *
 385  * @param[in] item
 386  *   Pointer to item specification.
 387  * @param[in] field
 388  *   Pointer to field modification information.
 389  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 390  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 392  * @param[in] dcopy
 393  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 394  *   Negative offset value sets the same offset as source offset.
 395  *   size field is ignored, value is taken from source field.
 396  * @param[in,out] resource
 397  *   Pointer to the modify-header resource.
 398  * @param[in] type
 399  *   Type of modification.
 400  * @param[out] error
 401  *   Pointer to the error structure.
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 static int
 407 flow_dv_convert_modify_action(struct rte_flow_item *item,
 408                               struct field_modify_info *field,
 409                               struct field_modify_info *dcopy,
 410                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 411                               uint32_t type, struct rte_flow_error *error)
 412 {
 413         uint32_t i = resource->actions_num;
 414         struct mlx5_modification_cmd *actions = resource->actions;
 415
 416         /*
 417          * The item and mask are provided in big-endian format.
 418          * The fields should be presented as in big-endian format either.
 419          * Mask must be always present, it defines the actual field width.
 420          */
 421         MLX5_ASSERT(item->mask);
 422         MLX5_ASSERT(field->size);
 423         do {
 424                 unsigned int size_b;
 425                 unsigned int off_b;
 426                 uint32_t mask;
 427                 uint32_t data;
 428
 429                 if (i >= MLX5_MAX_MODIFY_NUM)
 430                         return rte_flow_error_set(error, EINVAL,
 431                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 432                                  "too many items to modify");
 433                 /* Fetch variable byte size mask from the array. */
 434                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 435                                            field->offset, field->size);
 436                 if (!mask) {
 437                         ++field;
 438                         continue;
 439                 }
 440                 /* Deduce actual data width in bits from mask value. */
 441                 off_b = rte_bsf32(mask);
 442                 size_b = sizeof(uint32_t) * CHAR_BIT -
 443                          off_b - __builtin_clz(mask);
 444                 MLX5_ASSERT(size_b);
 445                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 446                 actions[i] = (struct mlx5_modification_cmd) {
 447                         .action_type = type,
 448                         .field = field->id,
 449                         .offset = off_b,
 450                         .length = size_b,
 451                 };
 452                 /* Convert entire record to expected big-endian format. */
 453                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 454                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 455                         MLX5_ASSERT(dcopy);
 456                         actions[i].dst_field = dcopy->id;
 457                         actions[i].dst_offset =
 458                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 459                         /* Convert entire record to big-endian format. */
 460                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 461                 } else {
 462                         MLX5_ASSERT(item->spec);
 463                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 464                                                    field->offset, field->size);
 465                         /* Shift out the trailing masked bits from data. */
 466                         data = (data & mask) >> off_b;
 467                         actions[i].data1 = rte_cpu_to_be_32(data);
 468                 }
 469                 ++i;
 470                 ++field;
 471         } while (field->size);
 472         if (resource->actions_num == i)
 473                 return rte_flow_error_set(error, EINVAL,
 474                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 475                                           "invalid modification flow item");
 476         resource->actions_num = i;
 477         return 0;
 478 }
 479
 480 /**
 481  * Convert modify-header set IPv4 address action to DV specification.
 482  *
 483  * @param[in,out] resource
 484  *   Pointer to the modify-header resource.
 485  * @param[in] action
 486  *   Pointer to action specification.
 487  * @param[out] error
 488  *   Pointer to the error structure.
 489  *
 490  * @return
 491  *   0 on success, a negative errno value otherwise and rte_errno is set.
 492  */
 493 static int
 494 flow_dv_convert_action_modify_ipv4
 495                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 496                          const struct rte_flow_action *action,
 497                          struct rte_flow_error *error)
 498 {
 499         const struct rte_flow_action_set_ipv4 *conf =
 500                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 501         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 502         struct rte_flow_item_ipv4 ipv4;
 503         struct rte_flow_item_ipv4 ipv4_mask;
 504
 505         memset(&ipv4, 0, sizeof(ipv4));
 506         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 507         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 508                 ipv4.hdr.src_addr = conf->ipv4_addr;
 509                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 510         } else {
 511                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 512                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 513         }
 514         item.spec = &ipv4;
 515         item.mask = &ipv4_mask;
 516         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 517                                              MLX5_MODIFICATION_TYPE_SET, error);
 518 }
 519
 520 /**
 521  * Convert modify-header set IPv6 address action to DV specification.
 522  *
 523  * @param[in,out] resource
 524  *   Pointer to the modify-header resource.
 525  * @param[in] action
 526  *   Pointer to action specification.
 527  * @param[out] error
 528  *   Pointer to the error structure.
 529  *
 530  * @return
 531  *   0 on success, a negative errno value otherwise and rte_errno is set.
 532  */
 533 static int
 534 flow_dv_convert_action_modify_ipv6
 535                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 536                          const struct rte_flow_action *action,
 537                          struct rte_flow_error *error)
 538 {
 539         const struct rte_flow_action_set_ipv6 *conf =
 540                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 541         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 542         struct rte_flow_item_ipv6 ipv6;
 543         struct rte_flow_item_ipv6 ipv6_mask;
 544
 545         memset(&ipv6, 0, sizeof(ipv6));
 546         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 547         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 548                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 549                        sizeof(ipv6.hdr.src_addr));
 550                 memcpy(&ipv6_mask.hdr.src_addr,
 551                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 552                        sizeof(ipv6.hdr.src_addr));
 553         } else {
 554                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.dst_addr));
 556                 memcpy(&ipv6_mask.hdr.dst_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 558                        sizeof(ipv6.hdr.dst_addr));
 559         }
 560         item.spec = &ipv6;
 561         item.mask = &ipv6_mask;
 562         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 563                                              MLX5_MODIFICATION_TYPE_SET, error);
 564 }
 565
 566 /**
 567  * Convert modify-header set MAC address action to DV specification.
 568  *
 569  * @param[in,out] resource
 570  *   Pointer to the modify-header resource.
 571  * @param[in] action
 572  *   Pointer to action specification.
 573  * @param[out] error
 574  *   Pointer to the error structure.
 575  *
 576  * @return
 577  *   0 on success, a negative errno value otherwise and rte_errno is set.
 578  */
 579 static int
 580 flow_dv_convert_action_modify_mac
 581                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 582                          const struct rte_flow_action *action,
 583                          struct rte_flow_error *error)
 584 {
 585         const struct rte_flow_action_set_mac *conf =
 586                 (const struct rte_flow_action_set_mac *)(action->conf);
 587         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 588         struct rte_flow_item_eth eth;
 589         struct rte_flow_item_eth eth_mask;
 590
 591         memset(&eth, 0, sizeof(eth));
 592         memset(&eth_mask, 0, sizeof(eth_mask));
 593         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 594                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 595                        sizeof(eth.src.addr_bytes));
 596                 memcpy(&eth_mask.src.addr_bytes,
 597                        &rte_flow_item_eth_mask.src.addr_bytes,
 598                        sizeof(eth_mask.src.addr_bytes));
 599         } else {
 600                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.dst.addr_bytes));
 602                 memcpy(&eth_mask.dst.addr_bytes,
 603                        &rte_flow_item_eth_mask.dst.addr_bytes,
 604                        sizeof(eth_mask.dst.addr_bytes));
 605         }
 606         item.spec = &eth;
 607         item.mask = &eth_mask;
 608         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 609                                              MLX5_MODIFICATION_TYPE_SET, error);
 610 }
 611
 612 /**
 613  * Convert modify-header set VLAN VID action to DV specification.
 614  *
 615  * @param[in,out] resource
 616  *   Pointer to the modify-header resource.
 617  * @param[in] action
 618  *   Pointer to action specification.
 619  * @param[out] error
 620  *   Pointer to the error structure.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 static int
 626 flow_dv_convert_action_modify_vlan_vid
 627                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 628                          const struct rte_flow_action *action,
 629                          struct rte_flow_error *error)
 630 {
 631         const struct rte_flow_action_of_set_vlan_vid *conf =
 632                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 633         int i = resource->actions_num;
 634         struct mlx5_modification_cmd *actions = resource->actions;
 635         struct field_modify_info *field = modify_vlan_out_first_vid;
 636
 637         if (i >= MLX5_MAX_MODIFY_NUM)
 638                 return rte_flow_error_set(error, EINVAL,
 639                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 640                          "too many items to modify");
 641         actions[i] = (struct mlx5_modification_cmd) {
 642                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 643                 .field = field->id,
 644                 .length = field->size,
 645                 .offset = field->offset,
 646         };
 647         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 648         actions[i].data1 = conf->vlan_vid;
 649         actions[i].data1 = actions[i].data1 << 16;
 650         resource->actions_num = ++i;
 651         return 0;
 652 }
 653
 654 /**
 655  * Convert modify-header set TP action to DV specification.
 656  *
 657  * @param[in,out] resource
 658  *   Pointer to the modify-header resource.
 659  * @param[in] action
 660  *   Pointer to action specification.
 661  * @param[in] items
 662  *   Pointer to rte_flow_item objects list.
 663  * @param[in] attr
 664  *   Pointer to flow attributes structure.
 665  * @param[in] dev_flow
 666  *   Pointer to the sub flow.
 667  * @param[in] tunnel_decap
 668  *   Whether action is after tunnel decapsulation.
 669  * @param[out] error
 670  *   Pointer to the error structure.
 671  *
 672  * @return
 673  *   0 on success, a negative errno value otherwise and rte_errno is set.
 674  */
 675 static int
 676 flow_dv_convert_action_modify_tp
 677                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 678                          const struct rte_flow_action *action,
 679                          const struct rte_flow_item *items,
 680                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 681                          bool tunnel_decap, struct rte_flow_error *error)
 682 {
 683         const struct rte_flow_action_set_tp *conf =
 684                 (const struct rte_flow_action_set_tp *)(action->conf);
 685         struct rte_flow_item item;
 686         struct rte_flow_item_udp udp;
 687         struct rte_flow_item_udp udp_mask;
 688         struct rte_flow_item_tcp tcp;
 689         struct rte_flow_item_tcp tcp_mask;
 690         struct field_modify_info *field;
 691
 692         if (!attr->valid)
 693                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 694         if (attr->udp) {
 695                 memset(&udp, 0, sizeof(udp));
 696                 memset(&udp_mask, 0, sizeof(udp_mask));
 697                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 698                         udp.hdr.src_port = conf->port;
 699                         udp_mask.hdr.src_port =
 700                                         rte_flow_item_udp_mask.hdr.src_port;
 701                 } else {
 702                         udp.hdr.dst_port = conf->port;
 703                         udp_mask.hdr.dst_port =
 704                                         rte_flow_item_udp_mask.hdr.dst_port;
 705                 }
 706                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 707                 item.spec = &udp;
 708                 item.mask = &udp_mask;
 709                 field = modify_udp;
 710         } else {
 711                 MLX5_ASSERT(attr->tcp);
 712                 memset(&tcp, 0, sizeof(tcp));
 713                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 714                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 715                         tcp.hdr.src_port = conf->port;
 716                         tcp_mask.hdr.src_port =
 717                                         rte_flow_item_tcp_mask.hdr.src_port;
 718                 } else {
 719                         tcp.hdr.dst_port = conf->port;
 720                         tcp_mask.hdr.dst_port =
 721                                         rte_flow_item_tcp_mask.hdr.dst_port;
 722                 }
 723                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 724                 item.spec = &tcp;
 725                 item.mask = &tcp_mask;
 726                 field = modify_tcp;
 727         }
 728         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 729                                              MLX5_MODIFICATION_TYPE_SET, error);
 730 }
 731
 732 /**
 733  * Convert modify-header set TTL action to DV specification.
 734  *
 735  * @param[in,out] resource
 736  *   Pointer to the modify-header resource.
 737  * @param[in] action
 738  *   Pointer to action specification.
 739  * @param[in] items
 740  *   Pointer to rte_flow_item objects list.
 741  * @param[in] attr
 742  *   Pointer to flow attributes structure.
 743  * @param[in] dev_flow
 744  *   Pointer to the sub flow.
 745  * @param[in] tunnel_decap
 746  *   Whether action is after tunnel decapsulation.
 747  * @param[out] error
 748  *   Pointer to the error structure.
 749  *
 750  * @return
 751  *   0 on success, a negative errno value otherwise and rte_errno is set.
 752  */
 753 static int
 754 flow_dv_convert_action_modify_ttl
 755                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 756                          const struct rte_flow_action *action,
 757                          const struct rte_flow_item *items,
 758                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 759                          bool tunnel_decap, struct rte_flow_error *error)
 760 {
 761         const struct rte_flow_action_set_ttl *conf =
 762                 (const struct rte_flow_action_set_ttl *)(action->conf);
 763         struct rte_flow_item item;
 764         struct rte_flow_item_ipv4 ipv4;
 765         struct rte_flow_item_ipv4 ipv4_mask;
 766         struct rte_flow_item_ipv6 ipv6;
 767         struct rte_flow_item_ipv6 ipv6_mask;
 768         struct field_modify_info *field;
 769
 770         if (!attr->valid)
 771                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 772         if (attr->ipv4) {
 773                 memset(&ipv4, 0, sizeof(ipv4));
 774                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 775                 ipv4.hdr.time_to_live = conf->ttl_value;
 776                 ipv4_mask.hdr.time_to_live = 0xFF;
 777                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 778                 item.spec = &ipv4;
 779                 item.mask = &ipv4_mask;
 780                 field = modify_ipv4;
 781         } else {
 782                 MLX5_ASSERT(attr->ipv6);
 783                 memset(&ipv6, 0, sizeof(ipv6));
 784                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 785                 ipv6.hdr.hop_limits = conf->ttl_value;
 786                 ipv6_mask.hdr.hop_limits = 0xFF;
 787                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 788                 item.spec = &ipv6;
 789                 item.mask = &ipv6_mask;
 790                 field = modify_ipv6;
 791         }
 792         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 793                                              MLX5_MODIFICATION_TYPE_SET, error);
 794 }
 795
 796 /**
 797  * Convert modify-header decrement TTL action to DV specification.
 798  *
 799  * @param[in,out] resource
 800  *   Pointer to the modify-header resource.
 801  * @param[in] action
 802  *   Pointer to action specification.
 803  * @param[in] items
 804  *   Pointer to rte_flow_item objects list.
 805  * @param[in] attr
 806  *   Pointer to flow attributes structure.
 807  * @param[in] dev_flow
 808  *   Pointer to the sub flow.
 809  * @param[in] tunnel_decap
 810  *   Whether action is after tunnel decapsulation.
 811  * @param[out] error
 812  *   Pointer to the error structure.
 813  *
 814  * @return
 815  *   0 on success, a negative errno value otherwise and rte_errno is set.
 816  */
 817 static int
 818 flow_dv_convert_action_modify_dec_ttl
 819                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 820                          const struct rte_flow_item *items,
 821                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 822                          bool tunnel_decap, struct rte_flow_error *error)
 823 {
 824         struct rte_flow_item item;
 825         struct rte_flow_item_ipv4 ipv4;
 826         struct rte_flow_item_ipv4 ipv4_mask;
 827         struct rte_flow_item_ipv6 ipv6;
 828         struct rte_flow_item_ipv6 ipv6_mask;
 829         struct field_modify_info *field;
 830
 831         if (!attr->valid)
 832                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 833         if (attr->ipv4) {
 834                 memset(&ipv4, 0, sizeof(ipv4));
 835                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 836                 ipv4.hdr.time_to_live = 0xFF;
 837                 ipv4_mask.hdr.time_to_live = 0xFF;
 838                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 839                 item.spec = &ipv4;
 840                 item.mask = &ipv4_mask;
 841                 field = modify_ipv4;
 842         } else {
 843                 MLX5_ASSERT(attr->ipv6);
 844                 memset(&ipv6, 0, sizeof(ipv6));
 845                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 846                 ipv6.hdr.hop_limits = 0xFF;
 847                 ipv6_mask.hdr.hop_limits = 0xFF;
 848                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 849                 item.spec = &ipv6;
 850                 item.mask = &ipv6_mask;
 851                 field = modify_ipv6;
 852         }
 853         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 854                                              MLX5_MODIFICATION_TYPE_ADD, error);
 855 }
 856
 857 /**
 858  * Convert modify-header increment/decrement TCP Sequence number
 859  * to DV specification.
 860  *
 861  * @param[in,out] resource
 862  *   Pointer to the modify-header resource.
 863  * @param[in] action
 864  *   Pointer to action specification.
 865  * @param[out] error
 866  *   Pointer to the error structure.
 867  *
 868  * @return
 869  *   0 on success, a negative errno value otherwise and rte_errno is set.
 870  */
 871 static int
 872 flow_dv_convert_action_modify_tcp_seq
 873                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 874                          const struct rte_flow_action *action,
 875                          struct rte_flow_error *error)
 876 {
 877         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 878         uint64_t value = rte_be_to_cpu_32(*conf);
 879         struct rte_flow_item item;
 880         struct rte_flow_item_tcp tcp;
 881         struct rte_flow_item_tcp tcp_mask;
 882
 883         memset(&tcp, 0, sizeof(tcp));
 884         memset(&tcp_mask, 0, sizeof(tcp_mask));
 885         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 886                 /*
 887                  * The HW has no decrement operation, only increment operation.
 888                  * To simulate decrement X from Y using increment operation
 889                  * we need to add UINT32_MAX X times to Y.
 890                  * Each adding of UINT32_MAX decrements Y by 1.
 891                  */
 892                 value *= UINT32_MAX;
 893         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 894         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 895         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 896         item.spec = &tcp;
 897         item.mask = &tcp_mask;
 898         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 899                                              MLX5_MODIFICATION_TYPE_ADD, error);
 900 }
 901
 902 /**
 903  * Convert modify-header increment/decrement TCP Acknowledgment number
 904  * to DV specification.
 905  *
 906  * @param[in,out] resource
 907  *   Pointer to the modify-header resource.
 908  * @param[in] action
 909  *   Pointer to action specification.
 910  * @param[out] error
 911  *   Pointer to the error structure.
 912  *
 913  * @return
 914  *   0 on success, a negative errno value otherwise and rte_errno is set.
 915  */
 916 static int
 917 flow_dv_convert_action_modify_tcp_ack
 918                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 919                          const struct rte_flow_action *action,
 920                          struct rte_flow_error *error)
 921 {
 922         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 923         uint64_t value = rte_be_to_cpu_32(*conf);
 924         struct rte_flow_item item;
 925         struct rte_flow_item_tcp tcp;
 926         struct rte_flow_item_tcp tcp_mask;
 927
 928         memset(&tcp, 0, sizeof(tcp));
 929         memset(&tcp_mask, 0, sizeof(tcp_mask));
 930         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 931                 /*
 932                  * The HW has no decrement operation, only increment operation.
 933                  * To simulate decrement X from Y using increment operation
 934                  * we need to add UINT32_MAX X times to Y.
 935                  * Each adding of UINT32_MAX decrements Y by 1.
 936                  */
 937                 value *= UINT32_MAX;
 938         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 939         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 940         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 941         item.spec = &tcp;
 942         item.mask = &tcp_mask;
 943         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 944                                              MLX5_MODIFICATION_TYPE_ADD, error);
 945 }
 946
 947 static enum mlx5_modification_field reg_to_field[] = {
 948         [REG_NONE] = MLX5_MODI_OUT_NONE,
 949         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 950         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 951         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 952         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 953         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 954         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 955         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 956         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 957         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 958         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 959 };
 960
 961 /**
 962  * Convert register set to DV specification.
 963  *
 964  * @param[in,out] resource
 965  *   Pointer to the modify-header resource.
 966  * @param[in] action
 967  *   Pointer to action specification.
 968  * @param[out] error
 969  *   Pointer to the error structure.
 970  *
 971  * @return
 972  *   0 on success, a negative errno value otherwise and rte_errno is set.
 973  */
 974 static int
 975 flow_dv_convert_action_set_reg
 976                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 977                          const struct rte_flow_action *action,
 978                          struct rte_flow_error *error)
 979 {
 980         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 981         struct mlx5_modification_cmd *actions = resource->actions;
 982         uint32_t i = resource->actions_num;
 983
 984         if (i >= MLX5_MAX_MODIFY_NUM)
 985                 return rte_flow_error_set(error, EINVAL,
 986                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 987                                           "too many items to modify");
 988         MLX5_ASSERT(conf->id != REG_NONE);
 989         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 990         actions[i] = (struct mlx5_modification_cmd) {
 991                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 992                 .field = reg_to_field[conf->id],
 993         };
 994         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 995         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 996         ++i;
 997         resource->actions_num = i;
 998         return 0;
 999 }
1000
1001 /**
1002  * Convert SET_TAG action to DV specification.
1003  *
1004  * @param[in] dev
1005  *   Pointer to the rte_eth_dev structure.
1006  * @param[in,out] resource
1007  *   Pointer to the modify-header resource.
1008  * @param[in] conf
1009  *   Pointer to action specification.
1010  * @param[out] error
1011  *   Pointer to the error structure.
1012  *
1013  * @return
1014  *   0 on success, a negative errno value otherwise and rte_errno is set.
1015  */
1016 static int
1017 flow_dv_convert_action_set_tag
1018                         (struct rte_eth_dev *dev,
1019                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1020                          const struct rte_flow_action_set_tag *conf,
1021                          struct rte_flow_error *error)
1022 {
1023         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025         struct rte_flow_item item = {
1026                 .spec = &data,
1027                 .mask = &mask,
1028         };
1029         struct field_modify_info reg_c_x[] = {
1030                 [1] = {0, 0, 0},
1031         };
1032         enum mlx5_modification_field reg_type;
1033         int ret;
1034
1035         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1036         if (ret < 0)
1037                 return ret;
1038         MLX5_ASSERT(ret != REG_NONE);
1039         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040         reg_type = reg_to_field[ret];
1041         MLX5_ASSERT(reg_type > 0);
1042         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044                                              MLX5_MODIFICATION_TYPE_SET, error);
1045 }
1046
1047 /**
1048  * Convert internal COPY_REG action to DV specification.
1049  *
1050  * @param[in] dev
1051  *   Pointer to the rte_eth_dev structure.
1052  * @param[in,out] res
1053  *   Pointer to the modify-header resource.
1054  * @param[in] action
1055  *   Pointer to action specification.
1056  * @param[out] error
1057  *   Pointer to the error structure.
1058  *
1059  * @return
1060  *   0 on success, a negative errno value otherwise and rte_errno is set.
1061  */
1062 static int
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1065                                  const struct rte_flow_action *action,
1066                                  struct rte_flow_error *error)
1067 {
1068         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070         struct rte_flow_item item = {
1071                 .spec = NULL,
1072                 .mask = &mask,
1073         };
1074         struct field_modify_info reg_src[] = {
1075                 {4, 0, reg_to_field[conf->src]},
1076                 {0, 0, 0},
1077         };
1078         struct field_modify_info reg_dst = {
1079                 .offset = 0,
1080                 .id = reg_to_field[conf->dst],
1081         };
1082         /* Adjust reg_c[0] usage according to reported mask. */
1083         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084                 struct mlx5_priv *priv = dev->data->dev_private;
1085                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1086
1087                 MLX5_ASSERT(reg_c0);
1088                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089                 if (conf->dst == REG_C_0) {
1090                         /* Copy to reg_c[0], within mask only. */
1091                         reg_dst.offset = rte_bsf32(reg_c0);
1092                         /*
1093                          * Mask is ignoring the enianness, because
1094                          * there is no conversion in datapath.
1095                          */
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097                         /* Copy from destination lower bits to reg_c[0]. */
1098                         mask = reg_c0 >> reg_dst.offset;
1099 #else
1100                         /* Copy from destination upper bits to reg_c[0]. */
1101                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102                                           rte_fls_u32(reg_c0));
1103 #endif
1104                 } else {
1105                         mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107                         /* Copy from reg_c[0] to destination lower bits. */
1108                         reg_dst.offset = 0;
1109 #else
1110                         /* Copy from reg_c[0] to destination upper bits. */
1111                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112                                          (rte_fls_u32(reg_c0) -
1113                                           rte_bsf32(reg_c0));
1114 #endif
1115                 }
1116         }
1117         return flow_dv_convert_modify_action(&item,
1118                                              reg_src, &reg_dst, res,
1119                                              MLX5_MODIFICATION_TYPE_COPY,
1120                                              error);
1121 }
1122
1123 /**
1124  * Convert MARK action to DV specification. This routine is used
1125  * in extensive metadata only and requires metadata register to be
1126  * handled. In legacy mode hardware tag resource is engaged.
1127  *
1128  * @param[in] dev
1129  *   Pointer to the rte_eth_dev structure.
1130  * @param[in] conf
1131  *   Pointer to MARK action specification.
1132  * @param[in,out] resource
1133  *   Pointer to the modify-header resource.
1134  * @param[out] error
1135  *   Pointer to the error structure.
1136  *
1137  * @return
1138  *   0 on success, a negative errno value otherwise and rte_errno is set.
1139  */
1140 static int
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142                             const struct rte_flow_action_mark *conf,
1143                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1144                             struct rte_flow_error *error)
1145 {
1146         struct mlx5_priv *priv = dev->data->dev_private;
1147         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148                                            priv->sh->dv_mark_mask);
1149         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150         struct rte_flow_item item = {
1151                 .spec = &data,
1152                 .mask = &mask,
1153         };
1154         struct field_modify_info reg_c_x[] = {
1155                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1156                 {0, 0, 0},
1157         };
1158         int reg;
1159
1160         if (!mask)
1161                 return rte_flow_error_set(error, EINVAL,
1162                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1163                                           NULL, "zero mark action mask");
1164         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1165         if (reg < 0)
1166                 return reg;
1167         MLX5_ASSERT(reg > 0);
1168         if (reg == REG_C_0) {
1169                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1170                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1171
1172                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1173                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1174                 mask = rte_cpu_to_be_32(mask << shl_c0);
1175         }
1176         reg_c_x[0].id = reg_to_field[reg];
1177         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1178                                              MLX5_MODIFICATION_TYPE_SET, error);
1179 }
1180
1181 /**
1182  * Get metadata register index for specified steering domain.
1183  *
1184  * @param[in] dev
1185  *   Pointer to the rte_eth_dev structure.
1186  * @param[in] attr
1187  *   Attributes of flow to determine steering domain.
1188  * @param[out] error
1189  *   Pointer to the error structure.
1190  *
1191  * @return
1192  *   positive index on success, a negative errno value otherwise
1193  *   and rte_errno is set.
1194  */
1195 static enum modify_reg
1196 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1197                          const struct rte_flow_attr *attr,
1198                          struct rte_flow_error *error)
1199 {
1200         int reg =
1201                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1202                                           MLX5_METADATA_FDB :
1203                                             attr->egress ?
1204                                             MLX5_METADATA_TX :
1205                                             MLX5_METADATA_RX, 0, error);
1206         if (reg < 0)
1207                 return rte_flow_error_set(error,
1208                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1209                                           NULL, "unavailable "
1210                                           "metadata register");
1211         return reg;
1212 }
1213
1214 /**
1215  * Convert SET_META action to DV specification.
1216  *
1217  * @param[in] dev
1218  *   Pointer to the rte_eth_dev structure.
1219  * @param[in,out] resource
1220  *   Pointer to the modify-header resource.
1221  * @param[in] attr
1222  *   Attributes of flow that includes this item.
1223  * @param[in] conf
1224  *   Pointer to action specification.
1225  * @param[out] error
1226  *   Pointer to the error structure.
1227  *
1228  * @return
1229  *   0 on success, a negative errno value otherwise and rte_errno is set.
1230  */
1231 static int
1232 flow_dv_convert_action_set_meta
1233                         (struct rte_eth_dev *dev,
1234                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1235                          const struct rte_flow_attr *attr,
1236                          const struct rte_flow_action_set_meta *conf,
1237                          struct rte_flow_error *error)
1238 {
1239         uint32_t data = conf->data;
1240         uint32_t mask = conf->mask;
1241         struct rte_flow_item item = {
1242                 .spec = &data,
1243                 .mask = &mask,
1244         };
1245         struct field_modify_info reg_c_x[] = {
1246                 [1] = {0, 0, 0},
1247         };
1248         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1249
1250         if (reg < 0)
1251                 return reg;
1252         /*
1253          * In datapath code there is no endianness
1254          * coversions for perfromance reasons, all
1255          * pattern conversions are done in rte_flow.
1256          */
1257         if (reg == REG_C_0) {
1258                 struct mlx5_priv *priv = dev->data->dev_private;
1259                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1260                 uint32_t shl_c0;
1261
1262                 MLX5_ASSERT(msk_c0);
1263 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1264                 shl_c0 = rte_bsf32(msk_c0);
1265 #else
1266                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1267 #endif
1268                 mask <<= shl_c0;
1269                 data <<= shl_c0;
1270                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1271         }
1272         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1273         /* The routine expects parameters in memory as big-endian ones. */
1274         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1275                                              MLX5_MODIFICATION_TYPE_SET, error);
1276 }
1277
1278 /**
1279  * Convert modify-header set IPv4 DSCP action to DV specification.
1280  *
1281  * @param[in,out] resource
1282  *   Pointer to the modify-header resource.
1283  * @param[in] action
1284  *   Pointer to action specification.
1285  * @param[out] error
1286  *   Pointer to the error structure.
1287  *
1288  * @return
1289  *   0 on success, a negative errno value otherwise and rte_errno is set.
1290  */
1291 static int
1292 flow_dv_convert_action_modify_ipv4_dscp
1293                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1294                          const struct rte_flow_action *action,
1295                          struct rte_flow_error *error)
1296 {
1297         const struct rte_flow_action_set_dscp *conf =
1298                 (const struct rte_flow_action_set_dscp *)(action->conf);
1299         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1300         struct rte_flow_item_ipv4 ipv4;
1301         struct rte_flow_item_ipv4 ipv4_mask;
1302
1303         memset(&ipv4, 0, sizeof(ipv4));
1304         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1305         ipv4.hdr.type_of_service = conf->dscp;
1306         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1307         item.spec = &ipv4;
1308         item.mask = &ipv4_mask;
1309         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1310                                              MLX5_MODIFICATION_TYPE_SET, error);
1311 }
1312
1313 /**
1314  * Convert modify-header set IPv6 DSCP action to DV specification.
1315  *
1316  * @param[in,out] resource
1317  *   Pointer to the modify-header resource.
1318  * @param[in] action
1319  *   Pointer to action specification.
1320  * @param[out] error
1321  *   Pointer to the error structure.
1322  *
1323  * @return
1324  *   0 on success, a negative errno value otherwise and rte_errno is set.
1325  */
1326 static int
1327 flow_dv_convert_action_modify_ipv6_dscp
1328                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1329                          const struct rte_flow_action *action,
1330                          struct rte_flow_error *error)
1331 {
1332         const struct rte_flow_action_set_dscp *conf =
1333                 (const struct rte_flow_action_set_dscp *)(action->conf);
1334         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1335         struct rte_flow_item_ipv6 ipv6;
1336         struct rte_flow_item_ipv6 ipv6_mask;
1337
1338         memset(&ipv6, 0, sizeof(ipv6));
1339         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1340         /*
1341          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1342          * rdma-core only accept the DSCP bits byte aligned start from
1343          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1344          * bits in IPv6 case as rdma-core requires byte aligned value.
1345          */
1346         ipv6.hdr.vtc_flow = conf->dscp;
1347         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1348         item.spec = &ipv6;
1349         item.mask = &ipv6_mask;
1350         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1351                                              MLX5_MODIFICATION_TYPE_SET, error);
1352 }
1353
1354 /**
1355  * Validate MARK item.
1356  *
1357  * @param[in] dev
1358  *   Pointer to the rte_eth_dev structure.
1359  * @param[in] item
1360  *   Item specification.
1361  * @param[in] attr
1362  *   Attributes of flow that includes this item.
1363  * @param[out] error
1364  *   Pointer to error structure.
1365  *
1366  * @return
1367  *   0 on success, a negative errno value otherwise and rte_errno is set.
1368  */
1369 static int
1370 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1371                            const struct rte_flow_item *item,
1372                            const struct rte_flow_attr *attr __rte_unused,
1373                            struct rte_flow_error *error)
1374 {
1375         struct mlx5_priv *priv = dev->data->dev_private;
1376         struct mlx5_dev_config *config = &priv->config;
1377         const struct rte_flow_item_mark *spec = item->spec;
1378         const struct rte_flow_item_mark *mask = item->mask;
1379         const struct rte_flow_item_mark nic_mask = {
1380                 .id = priv->sh->dv_mark_mask,
1381         };
1382         int ret;
1383
1384         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1385                 return rte_flow_error_set(error, ENOTSUP,
1386                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1387                                           "extended metadata feature"
1388                                           " isn't enabled");
1389         if (!mlx5_flow_ext_mreg_supported(dev))
1390                 return rte_flow_error_set(error, ENOTSUP,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1392                                           "extended metadata register"
1393                                           " isn't supported");
1394         if (!nic_mask.id)
1395                 return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't available");
1399         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1400         if (ret < 0)
1401                 return ret;
1402         if (!spec)
1403                 return rte_flow_error_set(error, EINVAL,
1404                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1405                                           item->spec,
1406                                           "data cannot be empty");
1407         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1408                 return rte_flow_error_set(error, EINVAL,
1409                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1410                                           &spec->id,
1411                                           "mark id exceeds the limit");
1412         if (!mask)
1413                 mask = &nic_mask;
1414         if (!mask->id)
1415                 return rte_flow_error_set(error, EINVAL,
1416                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1417                                         "mask cannot be zero");
1418
1419         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1420                                         (const uint8_t *)&nic_mask,
1421                                         sizeof(struct rte_flow_item_mark),
1422                                         error);
1423         if (ret < 0)
1424                 return ret;
1425         return 0;
1426 }
1427
1428 /**
1429  * Validate META item.
1430  *
1431  * @param[in] dev
1432  *   Pointer to the rte_eth_dev structure.
1433  * @param[in] item
1434  *   Item specification.
1435  * @param[in] attr
1436  *   Attributes of flow that includes this item.
1437  * @param[out] error
1438  *   Pointer to error structure.
1439  *
1440  * @return
1441  *   0 on success, a negative errno value otherwise and rte_errno is set.
1442  */
1443 static int
1444 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1445                            const struct rte_flow_item *item,
1446                            const struct rte_flow_attr *attr,
1447                            struct rte_flow_error *error)
1448 {
1449         struct mlx5_priv *priv = dev->data->dev_private;
1450         struct mlx5_dev_config *config = &priv->config;
1451         const struct rte_flow_item_meta *spec = item->spec;
1452         const struct rte_flow_item_meta *mask = item->mask;
1453         struct rte_flow_item_meta nic_mask = {
1454                 .data = UINT32_MAX
1455         };
1456         int reg;
1457         int ret;
1458
1459         if (!spec)
1460                 return rte_flow_error_set(error, EINVAL,
1461                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1462                                           item->spec,
1463                                           "data cannot be empty");
1464         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1465                 if (!mlx5_flow_ext_mreg_supported(dev))
1466                         return rte_flow_error_set(error, ENOTSUP,
1467                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1468                                           "extended metadata register"
1469                                           " isn't supported");
1470                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1471                 if (reg < 0)
1472                         return reg;
1473                 if (reg == REG_B)
1474                         return rte_flow_error_set(error, ENOTSUP,
1475                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1476                                           "match on reg_b "
1477                                           "isn't supported");
1478                 if (reg != REG_A)
1479                         nic_mask.data = priv->sh->dv_meta_mask;
1480         } else if (attr->transfer) {
1481                 return rte_flow_error_set(error, ENOTSUP,
1482                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1483                                         "extended metadata feature "
1484                                         "should be enabled when "
1485                                         "meta item is requested "
1486                                         "with e-switch mode ");
1487         }
1488         if (!mask)
1489                 mask = &rte_flow_item_meta_mask;
1490         if (!mask->data)
1491                 return rte_flow_error_set(error, EINVAL,
1492                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493                                         "mask cannot be zero");
1494
1495         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496                                         (const uint8_t *)&nic_mask,
1497                                         sizeof(struct rte_flow_item_meta),
1498                                         error);
1499         return ret;
1500 }
1501
1502 /**
1503  * Validate TAG item.
1504  *
1505  * @param[in] dev
1506  *   Pointer to the rte_eth_dev structure.
1507  * @param[in] item
1508  *   Item specification.
1509  * @param[in] attr
1510  *   Attributes of flow that includes this item.
1511  * @param[out] error
1512  *   Pointer to error structure.
1513  *
1514  * @return
1515  *   0 on success, a negative errno value otherwise and rte_errno is set.
1516  */
1517 static int
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519                           const struct rte_flow_item *item,
1520                           const struct rte_flow_attr *attr __rte_unused,
1521                           struct rte_flow_error *error)
1522 {
1523         const struct rte_flow_item_tag *spec = item->spec;
1524         const struct rte_flow_item_tag *mask = item->mask;
1525         const struct rte_flow_item_tag nic_mask = {
1526                 .data = RTE_BE32(UINT32_MAX),
1527                 .index = 0xff,
1528         };
1529         int ret;
1530
1531         if (!mlx5_flow_ext_mreg_supported(dev))
1532                 return rte_flow_error_set(error, ENOTSUP,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1534                                           "extensive metadata register"
1535                                           " isn't supported");
1536         if (!spec)
1537                 return rte_flow_error_set(error, EINVAL,
1538                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1539                                           item->spec,
1540                                           "data cannot be empty");
1541         if (!mask)
1542                 mask = &rte_flow_item_tag_mask;
1543         if (!mask->data)
1544                 return rte_flow_error_set(error, EINVAL,
1545                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546                                         "mask cannot be zero");
1547
1548         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549                                         (const uint8_t *)&nic_mask,
1550                                         sizeof(struct rte_flow_item_tag),
1551                                         error);
1552         if (ret < 0)
1553                 return ret;
1554         if (mask->index != 0xff)
1555                 return rte_flow_error_set(error, EINVAL,
1556                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557                                           "partial mask for tag index"
1558                                           " is not supported");
1559         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1560         if (ret < 0)
1561                 return ret;
1562         MLX5_ASSERT(ret != REG_NONE);
1563         return 0;
1564 }
1565
1566 /**
1567  * Validate vport item.
1568  *
1569  * @param[in] dev
1570  *   Pointer to the rte_eth_dev structure.
1571  * @param[in] item
1572  *   Item specification.
1573  * @param[in] attr
1574  *   Attributes of flow that includes this item.
1575  * @param[in] item_flags
1576  *   Bit-fields that holds the items detected until now.
1577  * @param[out] error
1578  *   Pointer to error structure.
1579  *
1580  * @return
1581  *   0 on success, a negative errno value otherwise and rte_errno is set.
1582  */
1583 static int
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585                               const struct rte_flow_item *item,
1586                               const struct rte_flow_attr *attr,
1587                               uint64_t item_flags,
1588                               struct rte_flow_error *error)
1589 {
1590         const struct rte_flow_item_port_id *spec = item->spec;
1591         const struct rte_flow_item_port_id *mask = item->mask;
1592         const struct rte_flow_item_port_id switch_mask = {
1593                         .id = 0xffffffff,
1594         };
1595         struct mlx5_priv *esw_priv;
1596         struct mlx5_priv *dev_priv;
1597         int ret;
1598
1599         if (!attr->transfer)
1600                 return rte_flow_error_set(error, EINVAL,
1601                                           RTE_FLOW_ERROR_TYPE_ITEM,
1602                                           NULL,
1603                                           "match on port id is valid only"
1604                                           " when transfer flag is enabled");
1605         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606                 return rte_flow_error_set(error, ENOTSUP,
1607                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1608                                           "multiple source ports are not"
1609                                           " supported");
1610         if (!mask)
1611                 mask = &switch_mask;
1612         if (mask->id != 0xffffffff)
1613                 return rte_flow_error_set(error, ENOTSUP,
1614                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1615                                            mask,
1616                                            "no support for partial mask on"
1617                                            " \"id\" field");
1618         ret = mlx5_flow_item_acceptable
1619                                 (item, (const uint8_t *)mask,
1620                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1621                                  sizeof(struct rte_flow_item_port_id),
1622                                  error);
1623         if (ret)
1624                 return ret;
1625         if (!spec)
1626                 return 0;
1627         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1628         if (!esw_priv)
1629                 return rte_flow_error_set(error, rte_errno,
1630                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631                                           "failed to obtain E-Switch info for"
1632                                           " port");
1633         dev_priv = mlx5_dev_to_eswitch_info(dev);
1634         if (!dev_priv)
1635                 return rte_flow_error_set(error, rte_errno,
1636                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1637                                           NULL,
1638                                           "failed to obtain E-Switch info");
1639         if (esw_priv->domain_id != dev_priv->domain_id)
1640                 return rte_flow_error_set(error, EINVAL,
1641                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642                                           "cannot match on a port from a"
1643                                           " different E-Switch");
1644         return 0;
1645 }
1646
1647 /**
1648  * Validate VLAN item.
1649  *
1650  * @param[in] item
1651  *   Item specification.
1652  * @param[in] item_flags
1653  *   Bit-fields that holds the items detected until now.
1654  * @param[in] dev
1655  *   Ethernet device flow is being created on.
1656  * @param[out] error
1657  *   Pointer to error structure.
1658  *
1659  * @return
1660  *   0 on success, a negative errno value otherwise and rte_errno is set.
1661  */
1662 static int
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664                            uint64_t item_flags,
1665                            struct rte_eth_dev *dev,
1666                            struct rte_flow_error *error)
1667 {
1668         const struct rte_flow_item_vlan *mask = item->mask;
1669         const struct rte_flow_item_vlan nic_mask = {
1670                 .tci = RTE_BE16(UINT16_MAX),
1671                 .inner_type = RTE_BE16(UINT16_MAX),
1672         };
1673         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1674         int ret;
1675         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676                                         MLX5_FLOW_LAYER_INNER_L4) :
1677                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1678                                         MLX5_FLOW_LAYER_OUTER_L4);
1679         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1681
1682         if (item_flags & vlanm)
1683                 return rte_flow_error_set(error, EINVAL,
1684                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1685                                           "multiple VLAN layers not supported");
1686         else if ((item_flags & l34m) != 0)
1687                 return rte_flow_error_set(error, EINVAL,
1688                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1689                                           "VLAN cannot follow L3/L4 layer");
1690         if (!mask)
1691                 mask = &rte_flow_item_vlan_mask;
1692         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693                                         (const uint8_t *)&nic_mask,
1694                                         sizeof(struct rte_flow_item_vlan),
1695                                         error);
1696         if (ret)
1697                 return ret;
1698         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699                 struct mlx5_priv *priv = dev->data->dev_private;
1700
1701                 if (priv->vmwa_context) {
1702                         /*
1703                          * Non-NULL context means we have a virtual machine
1704                          * and SR-IOV enabled, we have to create VLAN interface
1705                          * to make hypervisor to setup E-Switch vport
1706                          * context correctly. We avoid creating the multiple
1707                          * VLAN interfaces, so we cannot support VLAN tag mask.
1708                          */
1709                         return rte_flow_error_set(error, EINVAL,
1710                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1711                                                   item,
1712                                                   "VLAN tag mask is not"
1713                                                   " supported in virtual"
1714                                                   " environment");
1715                 }
1716         }
1717         return 0;
1718 }
1719
1720 /*
1721  * GTP flags are contained in 1 byte of the format:
1722  * -------------------------------------------
1723  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1724  * |-----------------------------------------|
1725  * | value | Version | PT | Res | E | S | PN |
1726  * -------------------------------------------
1727  *
1728  * Matching is supported only for GTP flags E, S, PN.
1729  */
1730 #define MLX5_GTP_FLAGS_MASK     0x07
1731
1732 /**
1733  * Validate GTP item.
1734  *
1735  * @param[in] dev
1736  *   Pointer to the rte_eth_dev structure.
1737  * @param[in] item
1738  *   Item specification.
1739  * @param[in] item_flags
1740  *   Bit-fields that holds the items detected until now.
1741  * @param[out] error
1742  *   Pointer to error structure.
1743  *
1744  * @return
1745  *   0 on success, a negative errno value otherwise and rte_errno is set.
1746  */
1747 static int
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749                           const struct rte_flow_item *item,
1750                           uint64_t item_flags,
1751                           struct rte_flow_error *error)
1752 {
1753         struct mlx5_priv *priv = dev->data->dev_private;
1754         const struct rte_flow_item_gtp *spec = item->spec;
1755         const struct rte_flow_item_gtp *mask = item->mask;
1756         const struct rte_flow_item_gtp nic_mask = {
1757                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1758                 .msg_type = 0xff,
1759                 .teid = RTE_BE32(0xffffffff),
1760         };
1761
1762         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763                 return rte_flow_error_set(error, ENOTSUP,
1764                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1765                                           "GTP support is not enabled");
1766         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767                 return rte_flow_error_set(error, ENOTSUP,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "multiple tunnel layers not"
1770                                           " supported");
1771         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772                 return rte_flow_error_set(error, EINVAL,
1773                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1774                                           "no outer UDP layer found");
1775         if (!mask)
1776                 mask = &rte_flow_item_gtp_mask;
1777         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778                 return rte_flow_error_set(error, ENOTSUP,
1779                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1780                                           "Match is supported for GTP"
1781                                           " flags only");
1782         return mlx5_flow_item_acceptable
1783                 (item, (const uint8_t *)mask,
1784                  (const uint8_t *)&nic_mask,
1785                  sizeof(struct rte_flow_item_gtp),
1786                  error);
1787 }
1788
1789 /**
1790  * Validate the pop VLAN action.
1791  *
1792  * @param[in] dev
1793  *   Pointer to the rte_eth_dev structure.
1794  * @param[in] action_flags
1795  *   Holds the actions detected until now.
1796  * @param[in] action
1797  *   Pointer to the pop vlan action.
1798  * @param[in] item_flags
1799  *   The items found in this flow rule.
1800  * @param[in] attr
1801  *   Pointer to flow attributes.
1802  * @param[out] error
1803  *   Pointer to error structure.
1804  *
1805  * @return
1806  *   0 on success, a negative errno value otherwise and rte_errno is set.
1807  */
1808 static int
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810                                  uint64_t action_flags,
1811                                  const struct rte_flow_action *action,
1812                                  uint64_t item_flags,
1813                                  const struct rte_flow_attr *attr,
1814                                  struct rte_flow_error *error)
1815 {
1816         const struct mlx5_priv *priv = dev->data->dev_private;
1817
1818         (void)action;
1819         (void)attr;
1820         if (!priv->sh->pop_vlan_action)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1823                                           NULL,
1824                                           "pop vlan action is not supported");
1825         if (attr->egress)
1826                 return rte_flow_error_set(error, ENOTSUP,
1827                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1828                                           NULL,
1829                                           "pop vlan action not supported for "
1830                                           "egress");
1831         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1834                                           "no support for multiple VLAN "
1835                                           "actions");
1836         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1837         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1838             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1841                                           NULL,
1842                                           "cannot pop vlan after decap without "
1843                                           "match on inner vlan in the flow");
1844         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1845         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1846             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847                 return rte_flow_error_set(error, ENOTSUP,
1848                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1849                                           NULL,
1850                                           "cannot pop vlan without a "
1851                                           "match on (outer) vlan in the flow");
1852         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1853                 return rte_flow_error_set(error, EINVAL,
1854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1855                                           "wrong action order, port_id should "
1856                                           "be after pop VLAN action");
1857         if (!attr->transfer && priv->representor)
1858                 return rte_flow_error_set(error, ENOTSUP,
1859                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1860                                           "pop vlan action for VF representor "
1861                                           "not supported on NIC table");
1862         return 0;
1863 }
1864
1865 /**
1866  * Get VLAN default info from vlan match info.
1867  *
1868  * @param[in] items
1869  *   the list of item specifications.
1870  * @param[out] vlan
1871  *   pointer VLAN info to fill to.
1872  *
1873  * @return
1874  *   0 on success, a negative errno value otherwise and rte_errno is set.
1875  */
1876 static void
1877 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1878                                   struct rte_vlan_hdr *vlan)
1879 {
1880         const struct rte_flow_item_vlan nic_mask = {
1881                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1882                                 MLX5DV_FLOW_VLAN_VID_MASK),
1883                 .inner_type = RTE_BE16(0xffff),
1884         };
1885
1886         if (items == NULL)
1887                 return;
1888         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1889                 int type = items->type;
1890
1891                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1892                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1893                         break;
1894         }
1895         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1896                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1897                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1898
1899                 /* If VLAN item in pattern doesn't contain data, return here. */
1900                 if (!vlan_v)
1901                         return;
1902                 if (!vlan_m)
1903                         vlan_m = &nic_mask;
1904                 /* Only full match values are accepted */
1905                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1906                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1907                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1908                         vlan->vlan_tci |=
1909                                 rte_be_to_cpu_16(vlan_v->tci &
1910                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1911                 }
1912                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1913                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1914                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1915                         vlan->vlan_tci |=
1916                                 rte_be_to_cpu_16(vlan_v->tci &
1917                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1918                 }
1919                 if (vlan_m->inner_type == nic_mask.inner_type)
1920                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1921                                                            vlan_m->inner_type);
1922         }
1923 }
1924
1925 /**
1926  * Validate the push VLAN action.
1927  *
1928  * @param[in] dev
1929  *   Pointer to the rte_eth_dev structure.
1930  * @param[in] action_flags
1931  *   Holds the actions detected until now.
1932  * @param[in] item_flags
1933  *   The items found in this flow rule.
1934  * @param[in] action
1935  *   Pointer to the action structure.
1936  * @param[in] attr
1937  *   Pointer to flow attributes
1938  * @param[out] error
1939  *   Pointer to error structure.
1940  *
1941  * @return
1942  *   0 on success, a negative errno value otherwise and rte_errno is set.
1943  */
1944 static int
1945 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1946                                   uint64_t action_flags,
1947                                   const struct rte_flow_item_vlan *vlan_m,
1948                                   const struct rte_flow_action *action,
1949                                   const struct rte_flow_attr *attr,
1950                                   struct rte_flow_error *error)
1951 {
1952         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1953         const struct mlx5_priv *priv = dev->data->dev_private;
1954
1955         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1956             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "invalid vlan ethertype");
1960         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961                 return rte_flow_error_set(error, EINVAL,
1962                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1963                                           "wrong action order, port_id should "
1964                                           "be after push VLAN");
1965         if (!attr->transfer && priv->representor)
1966                 return rte_flow_error_set(error, ENOTSUP,
1967                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968                                           "push vlan action for VF representor "
1969                                           "not supported on NIC table");
1970         if (vlan_m &&
1971             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975             !(mlx5_flow_find_action
1976                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977                 return rte_flow_error_set(error, EINVAL,
1978                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1979                                           "not full match mask on VLAN PCP and "
1980                                           "there is no of_set_vlan_pcp action, "
1981                                           "push VLAN action cannot figure out "
1982                                           "PCP value");
1983         if (vlan_m &&
1984             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988             !(mlx5_flow_find_action
1989                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990                 return rte_flow_error_set(error, EINVAL,
1991                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1992                                           "not full match mask on VLAN VID and "
1993                                           "there is no of_set_vlan_vid action, "
1994                                           "push VLAN action cannot figure out "
1995                                           "VID value");
1996         (void)attr;
1997         return 0;
1998 }
1999
2000 /**
2001  * Validate the set VLAN PCP.
2002  *
2003  * @param[in] action_flags
2004  *   Holds the actions detected until now.
2005  * @param[in] actions
2006  *   Pointer to the list of actions remaining in the flow rule.
2007  * @param[out] error
2008  *   Pointer to error structure.
2009  *
2010  * @return
2011  *   0 on success, a negative errno value otherwise and rte_errno is set.
2012  */
2013 static int
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015                                      const struct rte_flow_action actions[],
2016                                      struct rte_flow_error *error)
2017 {
2018         const struct rte_flow_action *action = actions;
2019         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2020
2021         if (conf->vlan_pcp > 7)
2022                 return rte_flow_error_set(error, EINVAL,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "VLAN PCP value is too big");
2025         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026                 return rte_flow_error_set(error, ENOTSUP,
2027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2028                                           "set VLAN PCP action must follow "
2029                                           "the push VLAN action");
2030         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031                 return rte_flow_error_set(error, ENOTSUP,
2032                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2033                                           "Multiple VLAN PCP modification are "
2034                                           "not supported");
2035         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2038                                           "wrong action order, port_id should "
2039                                           "be after set VLAN PCP");
2040         return 0;
2041 }
2042
2043 /**
2044  * Validate the set VLAN VID.
2045  *
2046  * @param[in] item_flags
2047  *   Holds the items detected in this rule.
2048  * @param[in] action_flags
2049  *   Holds the actions detected until now.
2050  * @param[in] actions
2051  *   Pointer to the list of actions remaining in the flow rule.
2052  * @param[out] error
2053  *   Pointer to error structure.
2054  *
2055  * @return
2056  *   0 on success, a negative errno value otherwise and rte_errno is set.
2057  */
2058 static int
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060                                      uint64_t action_flags,
2061                                      const struct rte_flow_action actions[],
2062                                      struct rte_flow_error *error)
2063 {
2064         const struct rte_flow_action *action = actions;
2065         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2066
2067         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068                 return rte_flow_error_set(error, EINVAL,
2069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2070                                           "VLAN VID value is too big");
2071         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073                 return rte_flow_error_set(error, ENOTSUP,
2074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2075                                           "set VLAN VID action must follow push"
2076                                           " VLAN action or match on VLAN item");
2077         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078                 return rte_flow_error_set(error, ENOTSUP,
2079                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2080                                           "Multiple VLAN VID modifications are "
2081                                           "not supported");
2082         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083                 return rte_flow_error_set(error, EINVAL,
2084                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2085                                           "wrong action order, port_id should "
2086                                           "be after set VLAN VID");
2087         return 0;
2088 }
2089
2090 /*
2091  * Validate the FLAG action.
2092  *
2093  * @param[in] dev
2094  *   Pointer to the rte_eth_dev structure.
2095  * @param[in] action_flags
2096  *   Holds the actions detected until now.
2097  * @param[in] attr
2098  *   Pointer to flow attributes
2099  * @param[out] error
2100  *   Pointer to error structure.
2101  *
2102  * @return
2103  *   0 on success, a negative errno value otherwise and rte_errno is set.
2104  */
2105 static int
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107                              uint64_t action_flags,
2108                              const struct rte_flow_attr *attr,
2109                              struct rte_flow_error *error)
2110 {
2111         struct mlx5_priv *priv = dev->data->dev_private;
2112         struct mlx5_dev_config *config = &priv->config;
2113         int ret;
2114
2115         /* Fall back if no extended metadata register support. */
2116         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117                 return mlx5_flow_validate_action_flag(action_flags, attr,
2118                                                       error);
2119         /* Extensive metadata mode requires registers. */
2120         if (!mlx5_flow_ext_mreg_supported(dev))
2121                 return rte_flow_error_set(error, ENOTSUP,
2122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123                                           "no metadata registers "
2124                                           "to support flag action");
2125         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126                 return rte_flow_error_set(error, ENOTSUP,
2127                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128                                           "extended metadata register"
2129                                           " isn't available");
2130         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2131         if (ret < 0)
2132                 return ret;
2133         MLX5_ASSERT(ret > 0);
2134         if (action_flags & MLX5_FLOW_ACTION_MARK)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't mark and flag in same flow");
2138         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2141                                           "can't have 2 flag"
2142                                           " actions in same flow");
2143         return 0;
2144 }
2145
2146 /**
2147  * Validate MARK action.
2148  *
2149  * @param[in] dev
2150  *   Pointer to the rte_eth_dev structure.
2151  * @param[in] action
2152  *   Pointer to action.
2153  * @param[in] action_flags
2154  *   Holds the actions detected until now.
2155  * @param[in] attr
2156  *   Pointer to flow attributes
2157  * @param[out] error
2158  *   Pointer to error structure.
2159  *
2160  * @return
2161  *   0 on success, a negative errno value otherwise and rte_errno is set.
2162  */
2163 static int
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165                              const struct rte_flow_action *action,
2166                              uint64_t action_flags,
2167                              const struct rte_flow_attr *attr,
2168                              struct rte_flow_error *error)
2169 {
2170         struct mlx5_priv *priv = dev->data->dev_private;
2171         struct mlx5_dev_config *config = &priv->config;
2172         const struct rte_flow_action_mark *mark = action->conf;
2173         int ret;
2174
2175         /* Fall back if no extended metadata register support. */
2176         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177                 return mlx5_flow_validate_action_mark(action, action_flags,
2178                                                       attr, error);
2179         /* Extensive metadata mode requires registers. */
2180         if (!mlx5_flow_ext_mreg_supported(dev))
2181                 return rte_flow_error_set(error, ENOTSUP,
2182                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183                                           "no metadata registers "
2184                                           "to support mark action");
2185         if (!priv->sh->dv_mark_mask)
2186                 return rte_flow_error_set(error, ENOTSUP,
2187                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188                                           "extended metadata register"
2189                                           " isn't available");
2190         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2191         if (ret < 0)
2192                 return ret;
2193         MLX5_ASSERT(ret > 0);
2194         if (!mark)
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2197                                           "configuration cannot be null");
2198         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199                 return rte_flow_error_set(error, EINVAL,
2200                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2201                                           &mark->id,
2202                                           "mark id exceeds the limit");
2203         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't flag and mark in same flow");
2207         if (action_flags & MLX5_FLOW_ACTION_MARK)
2208                 return rte_flow_error_set(error, EINVAL,
2209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210                                           "can't have 2 mark actions in same"
2211                                           " flow");
2212         return 0;
2213 }
2214
2215 /**
2216  * Validate SET_META action.
2217  *
2218  * @param[in] dev
2219  *   Pointer to the rte_eth_dev structure.
2220  * @param[in] action
2221  *   Pointer to the action structure.
2222  * @param[in] action_flags
2223  *   Holds the actions detected until now.
2224  * @param[in] attr
2225  *   Pointer to flow attributes
2226  * @param[out] error
2227  *   Pointer to error structure.
2228  *
2229  * @return
2230  *   0 on success, a negative errno value otherwise and rte_errno is set.
2231  */
2232 static int
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234                                  const struct rte_flow_action *action,
2235                                  uint64_t action_flags __rte_unused,
2236                                  const struct rte_flow_attr *attr,
2237                                  struct rte_flow_error *error)
2238 {
2239         const struct rte_flow_action_set_meta *conf;
2240         uint32_t nic_mask = UINT32_MAX;
2241         int reg;
2242
2243         if (!mlx5_flow_ext_mreg_supported(dev))
2244                 return rte_flow_error_set(error, ENOTSUP,
2245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2246                                           "extended metadata register"
2247                                           " isn't supported");
2248         reg = flow_dv_get_metadata_reg(dev, attr, error);
2249         if (reg < 0)
2250                 return reg;
2251         if (reg != REG_A && reg != REG_B) {
2252                 struct mlx5_priv *priv = dev->data->dev_private;
2253
2254                 nic_mask = priv->sh->dv_meta_mask;
2255         }
2256         if (!(action->conf))
2257                 return rte_flow_error_set(error, EINVAL,
2258                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2259                                           "configuration cannot be null");
2260         conf = (const struct rte_flow_action_set_meta *)action->conf;
2261         if (!conf->mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "zero mask doesn't have any effect");
2265         if (conf->mask & ~nic_mask)
2266                 return rte_flow_error_set(error, EINVAL,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "meta data must be within reg C0");
2269         return 0;
2270 }
2271
2272 /**
2273  * Validate SET_TAG action.
2274  *
2275  * @param[in] dev
2276  *   Pointer to the rte_eth_dev structure.
2277  * @param[in] action
2278  *   Pointer to the action structure.
2279  * @param[in] action_flags
2280  *   Holds the actions detected until now.
2281  * @param[in] attr
2282  *   Pointer to flow attributes
2283  * @param[out] error
2284  *   Pointer to error structure.
2285  *
2286  * @return
2287  *   0 on success, a negative errno value otherwise and rte_errno is set.
2288  */
2289 static int
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291                                 const struct rte_flow_action *action,
2292                                 uint64_t action_flags,
2293                                 const struct rte_flow_attr *attr,
2294                                 struct rte_flow_error *error)
2295 {
2296         const struct rte_flow_action_set_tag *conf;
2297         const uint64_t terminal_action_flags =
2298                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299                 MLX5_FLOW_ACTION_RSS;
2300         int ret;
2301
2302         if (!mlx5_flow_ext_mreg_supported(dev))
2303                 return rte_flow_error_set(error, ENOTSUP,
2304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2305                                           "extensive metadata register"
2306                                           " isn't supported");
2307         if (!(action->conf))
2308                 return rte_flow_error_set(error, EINVAL,
2309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2310                                           "configuration cannot be null");
2311         conf = (const struct rte_flow_action_set_tag *)action->conf;
2312         if (!conf->mask)
2313                 return rte_flow_error_set(error, EINVAL,
2314                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2315                                           "zero mask doesn't have any effect");
2316         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2317         if (ret < 0)
2318                 return ret;
2319         if (!attr->transfer && attr->ingress &&
2320             (action_flags & terminal_action_flags))
2321                 return rte_flow_error_set(error, EINVAL,
2322                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2323                                           "set_tag has no effect"
2324                                           " with terminal actions");
2325         return 0;
2326 }
2327
2328 /**
2329  * Validate count action.
2330  *
2331  * @param[in] dev
2332  *   Pointer to rte_eth_dev structure.
2333  * @param[out] error
2334  *   Pointer to error structure.
2335  *
2336  * @return
2337  *   0 on success, a negative errno value otherwise and rte_errno is set.
2338  */
2339 static int
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341                               struct rte_flow_error *error)
2342 {
2343         struct mlx5_priv *priv = dev->data->dev_private;
2344
2345         if (!priv->config.devx)
2346                 goto notsup_err;
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2348         return 0;
2349 #endif
2350 notsup_err:
2351         return rte_flow_error_set
2352                       (error, ENOTSUP,
2353                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2354                        NULL,
2355                        "count action not supported");
2356 }
2357
2358 /**
2359  * Validate the L2 encap action.
2360  *
2361  * @param[in] dev
2362  *   Pointer to the rte_eth_dev structure.
2363  * @param[in] action_flags
2364  *   Holds the actions detected until now.
2365  * @param[in] action
2366  *   Pointer to the action structure.
2367  * @param[in] attr
2368  *   Pointer to flow attributes.
2369  * @param[out] error
2370  *   Pointer to error structure.
2371  *
2372  * @return
2373  *   0 on success, a negative errno value otherwise and rte_errno is set.
2374  */
2375 static int
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377                                  uint64_t action_flags,
2378                                  const struct rte_flow_action *action,
2379                                  const struct rte_flow_attr *attr,
2380                                  struct rte_flow_error *error)
2381 {
2382         const struct mlx5_priv *priv = dev->data->dev_private;
2383
2384         if (!(action->conf))
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2387                                           "configuration cannot be null");
2388         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389                 return rte_flow_error_set(error, EINVAL,
2390                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391                                           "can only have a single encap action "
2392                                           "in a flow");
2393         if (!attr->transfer && priv->representor)
2394                 return rte_flow_error_set(error, ENOTSUP,
2395                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396                                           "encap action for VF representor "
2397                                           "not supported on NIC table");
2398         return 0;
2399 }
2400
2401 /**
2402  * Validate a decap action.
2403  *
2404  * @param[in] dev
2405  *   Pointer to the rte_eth_dev structure.
2406  * @param[in] action_flags
2407  *   Holds the actions detected until now.
2408  * @param[in] attr
2409  *   Pointer to flow attributes
2410  * @param[out] error
2411  *   Pointer to error structure.
2412  *
2413  * @return
2414  *   0 on success, a negative errno value otherwise and rte_errno is set.
2415  */
2416 static int
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418                               uint64_t action_flags,
2419                               const struct rte_flow_attr *attr,
2420                               struct rte_flow_error *error)
2421 {
2422         const struct mlx5_priv *priv = dev->data->dev_private;
2423
2424         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425             !priv->config.decap_en)
2426                 return rte_flow_error_set(error, ENOTSUP,
2427                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428                                           "decap is not enabled");
2429         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430                 return rte_flow_error_set(error, ENOTSUP,
2431                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2432                                           action_flags &
2433                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2434                                           "have a single decap action" : "decap "
2435                                           "after encap is not supported");
2436         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437                 return rte_flow_error_set(error, EINVAL,
2438                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439                                           "can't have decap action after"
2440                                           " modify action");
2441         if (attr->egress)
2442                 return rte_flow_error_set(error, ENOTSUP,
2443                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2444                                           NULL,
2445                                           "decap action not supported for "
2446                                           "egress");
2447         if (!attr->transfer && priv->representor)
2448                 return rte_flow_error_set(error, ENOTSUP,
2449                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450                                           "decap action for VF representor "
2451                                           "not supported on NIC table");
2452         return 0;
2453 }
2454
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2456
2457 /**
2458  * Validate the raw encap and decap actions.
2459  *
2460  * @param[in] dev
2461  *   Pointer to the rte_eth_dev structure.
2462  * @param[in] decap
2463  *   Pointer to the decap action.
2464  * @param[in] encap
2465  *   Pointer to the encap action.
2466  * @param[in] attr
2467  *   Pointer to flow attributes
2468  * @param[in/out] action_flags
2469  *   Holds the actions detected until now.
2470  * @param[out] actions_n
2471  *   pointer to the number of actions counter.
2472  * @param[out] error
2473  *   Pointer to error structure.
2474  *
2475  * @return
2476  *   0 on success, a negative errno value otherwise and rte_errno is set.
2477  */
2478 static int
2479 flow_dv_validate_action_raw_encap_decap
2480         (struct rte_eth_dev *dev,
2481          const struct rte_flow_action_raw_decap *decap,
2482          const struct rte_flow_action_raw_encap *encap,
2483          const struct rte_flow_attr *attr, uint64_t *action_flags,
2484          int *actions_n, struct rte_flow_error *error)
2485 {
2486         const struct mlx5_priv *priv = dev->data->dev_private;
2487         int ret;
2488
2489         if (encap && (!encap->size || !encap->data))
2490                 return rte_flow_error_set(error, EINVAL,
2491                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492                                           "raw encap data cannot be empty");
2493         if (decap && encap) {
2494                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2496                         /* L3 encap. */
2497                         decap = NULL;
2498                 else if (encap->size <=
2499                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2500                            decap->size >
2501                            MLX5_ENCAPSULATION_DECISION_SIZE)
2502                         /* L3 decap. */
2503                         encap = NULL;
2504                 else if (encap->size >
2505                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2506                            decap->size >
2507                            MLX5_ENCAPSULATION_DECISION_SIZE)
2508                         /* 2 L2 actions: encap and decap. */
2509                         ;
2510                 else
2511                         return rte_flow_error_set(error,
2512                                 ENOTSUP,
2513                                 RTE_FLOW_ERROR_TYPE_ACTION,
2514                                 NULL, "unsupported too small "
2515                                 "raw decap and too small raw "
2516                                 "encap combination");
2517         }
2518         if (decap) {
2519                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2520                                                     error);
2521                 if (ret < 0)
2522                         return ret;
2523                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2524                 ++(*actions_n);
2525         }
2526         if (encap) {
2527                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528                         return rte_flow_error_set(error, ENOTSUP,
2529                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2530                                                   NULL,
2531                                                   "small raw encap size");
2532                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533                         return rte_flow_error_set(error, EINVAL,
2534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2535                                                   NULL,
2536                                                   "more than one encap action");
2537                 if (!attr->transfer && priv->representor)
2538                         return rte_flow_error_set
2539                                         (error, ENOTSUP,
2540                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541                                          "encap action for VF representor "
2542                                          "not supported on NIC table");
2543                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2544                 ++(*actions_n);
2545         }
2546         return 0;
2547 }
2548
2549 /**
2550  * Find existing encap/decap resource or create and register a new one.
2551  *
2552  * @param[in, out] dev
2553  *   Pointer to rte_eth_dev structure.
2554  * @param[in, out] resource
2555  *   Pointer to encap/decap resource.
2556  * @parm[in, out] dev_flow
2557  *   Pointer to the dev_flow.
2558  * @param[out] error
2559  *   pointer to error structure.
2560  *
2561  * @return
2562  *   0 on success otherwise -errno and errno is set.
2563  */
2564 static int
2565 flow_dv_encap_decap_resource_register
2566                         (struct rte_eth_dev *dev,
2567                          struct mlx5_flow_dv_encap_decap_resource *resource,
2568                          struct mlx5_flow *dev_flow,
2569                          struct rte_flow_error *error)
2570 {
2571         struct mlx5_priv *priv = dev->data->dev_private;
2572         struct mlx5_dev_ctx_shared *sh = priv->sh;
2573         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574         struct mlx5dv_dr_domain *domain;
2575         uint32_t idx = 0;
2576         int ret;
2577
2578         resource->flags = dev_flow->dv.group ? 0 : 1;
2579         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580                 domain = sh->fdb_domain;
2581         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582                 domain = sh->rx_domain;
2583         else
2584                 domain = sh->tx_domain;
2585         /* Lookup a matching resource from cache. */
2586         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587                       cache_resource, next) {
2588                 if (resource->reformat_type == cache_resource->reformat_type &&
2589                     resource->ft_type == cache_resource->ft_type &&
2590                     resource->flags == cache_resource->flags &&
2591                     resource->size == cache_resource->size &&
2592                     !memcmp((const void *)resource->buf,
2593                             (const void *)cache_resource->buf,
2594                             resource->size)) {
2595                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596                                 (void *)cache_resource,
2597                                 rte_atomic32_read(&cache_resource->refcnt));
2598                         rte_atomic32_inc(&cache_resource->refcnt);
2599                         dev_flow->handle->dvh.rix_encap_decap = idx;
2600                         dev_flow->dv.encap_decap = cache_resource;
2601                         return 0;
2602                 }
2603         }
2604         /* Register new encap/decap resource. */
2605         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606                                        &dev_flow->handle->dvh.rix_encap_decap);
2607         if (!cache_resource)
2608                 return rte_flow_error_set(error, ENOMEM,
2609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610                                           "cannot allocate resource memory");
2611         *cache_resource = *resource;
2612         ret = mlx5_flow_os_create_flow_action_packet_reformat
2613                                         (sh->ctx, domain, cache_resource,
2614                                          &cache_resource->action);
2615         if (ret) {
2616                 mlx5_free(cache_resource);
2617                 return rte_flow_error_set(error, ENOMEM,
2618                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619                                           NULL, "cannot create action");
2620         }
2621         rte_atomic32_init(&cache_resource->refcnt);
2622         rte_atomic32_inc(&cache_resource->refcnt);
2623         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2625                      next);
2626         dev_flow->dv.encap_decap = cache_resource;
2627         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628                 (void *)cache_resource,
2629                 rte_atomic32_read(&cache_resource->refcnt));
2630         return 0;
2631 }
2632
2633 /**
2634  * Find existing table jump resource or create and register a new one.
2635  *
2636  * @param[in, out] dev
2637  *   Pointer to rte_eth_dev structure.
2638  * @param[in, out] tbl
2639  *   Pointer to flow table resource.
2640  * @parm[in, out] dev_flow
2641  *   Pointer to the dev_flow.
2642  * @param[out] error
2643  *   pointer to error structure.
2644  *
2645  * @return
2646  *   0 on success otherwise -errno and errno is set.
2647  */
2648 static int
2649 flow_dv_jump_tbl_resource_register
2650                         (struct rte_eth_dev *dev __rte_unused,
2651                          struct mlx5_flow_tbl_resource *tbl,
2652                          struct mlx5_flow *dev_flow,
2653                          struct rte_flow_error *error)
2654 {
2655         struct mlx5_flow_tbl_data_entry *tbl_data =
2656                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2657         int cnt, ret;
2658
2659         MLX5_ASSERT(tbl);
2660         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2661         if (!cnt) {
2662                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663                                 (tbl->obj, &tbl_data->jump.action);
2664                 if (ret)
2665                         return rte_flow_error_set(error, ENOMEM,
2666                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667                                         NULL, "cannot create jump action");
2668                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         } else {
2671                 /* old jump should not make the table ref++. */
2672                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673                 MLX5_ASSERT(tbl_data->jump.action);
2674                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675                         (void *)&tbl_data->jump, cnt);
2676         }
2677         rte_atomic32_inc(&tbl_data->jump.refcnt);
2678         dev_flow->handle->rix_jump = tbl_data->idx;
2679         dev_flow->dv.jump = &tbl_data->jump;
2680         return 0;
2681 }
2682
2683 /**
2684  * Find existing default miss resource or create and register a new one.
2685  *
2686  * @param[in, out] dev
2687  *   Pointer to rte_eth_dev structure.
2688  * @param[out] error
2689  *   pointer to error structure.
2690  *
2691  * @return
2692  *   0 on success otherwise -errno and errno is set.
2693  */
2694 static int
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696                 struct rte_flow_error *error)
2697 {
2698         struct mlx5_priv *priv = dev->data->dev_private;
2699         struct mlx5_dev_ctx_shared *sh = priv->sh;
2700         struct mlx5_flow_default_miss_resource *cache_resource =
2701                         &sh->default_miss;
2702         int cnt = rte_atomic32_read(&cache_resource->refcnt);
2703
2704         if (!cnt) {
2705                 MLX5_ASSERT(cache_resource->action);
2706                 cache_resource->action =
2707                 mlx5_glue->dr_create_flow_action_default_miss();
2708                 if (!cache_resource->action)
2709                         return rte_flow_error_set(error, ENOMEM,
2710                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711                                         "cannot create default miss action");
2712                 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713                                 (void *)cache_resource->action, cnt);
2714         }
2715         rte_atomic32_inc(&cache_resource->refcnt);
2716         return 0;
2717 }
2718
2719 /**
2720  * Find existing table port ID resource or create and register a new one.
2721  *
2722  * @param[in, out] dev
2723  *   Pointer to rte_eth_dev structure.
2724  * @param[in, out] resource
2725  *   Pointer to port ID action resource.
2726  * @parm[in, out] dev_flow
2727  *   Pointer to the dev_flow.
2728  * @param[out] error
2729  *   pointer to error structure.
2730  *
2731  * @return
2732  *   0 on success otherwise -errno and errno is set.
2733  */
2734 static int
2735 flow_dv_port_id_action_resource_register
2736                         (struct rte_eth_dev *dev,
2737                          struct mlx5_flow_dv_port_id_action_resource *resource,
2738                          struct mlx5_flow *dev_flow,
2739                          struct rte_flow_error *error)
2740 {
2741         struct mlx5_priv *priv = dev->data->dev_private;
2742         struct mlx5_dev_ctx_shared *sh = priv->sh;
2743         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2744         uint32_t idx = 0;
2745         int ret;
2746
2747         /* Lookup a matching resource from cache. */
2748         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749                       idx, cache_resource, next) {
2750                 if (resource->port_id == cache_resource->port_id) {
2751                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2752                                 "refcnt %d++",
2753                                 (void *)cache_resource,
2754                                 rte_atomic32_read(&cache_resource->refcnt));
2755                         rte_atomic32_inc(&cache_resource->refcnt);
2756                         dev_flow->handle->rix_port_id_action = idx;
2757                         dev_flow->dv.port_id_action = cache_resource;
2758                         return 0;
2759                 }
2760         }
2761         /* Register new port id action resource. */
2762         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763                                        &dev_flow->handle->rix_port_id_action);
2764         if (!cache_resource)
2765                 return rte_flow_error_set(error, ENOMEM,
2766                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767                                           "cannot allocate resource memory");
2768         *cache_resource = *resource;
2769         ret = mlx5_flow_os_create_flow_action_dest_port
2770                                 (priv->sh->fdb_domain, resource->port_id,
2771                                  &cache_resource->action);
2772         if (ret) {
2773                 mlx5_free(cache_resource);
2774                 return rte_flow_error_set(error, ENOMEM,
2775                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776                                           NULL, "cannot create action");
2777         }
2778         rte_atomic32_init(&cache_resource->refcnt);
2779         rte_atomic32_inc(&cache_resource->refcnt);
2780         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781                      dev_flow->handle->rix_port_id_action, cache_resource,
2782                      next);
2783         dev_flow->dv.port_id_action = cache_resource;
2784         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785                 (void *)cache_resource,
2786                 rte_atomic32_read(&cache_resource->refcnt));
2787         return 0;
2788 }
2789
2790 /**
2791  * Find existing push vlan resource or create and register a new one.
2792  *
2793  * @param [in, out] dev
2794  *   Pointer to rte_eth_dev structure.
2795  * @param[in, out] resource
2796  *   Pointer to port ID action resource.
2797  * @parm[in, out] dev_flow
2798  *   Pointer to the dev_flow.
2799  * @param[out] error
2800  *   pointer to error structure.
2801  *
2802  * @return
2803  *   0 on success otherwise -errno and errno is set.
2804  */
2805 static int
2806 flow_dv_push_vlan_action_resource_register
2807                        (struct rte_eth_dev *dev,
2808                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809                         struct mlx5_flow *dev_flow,
2810                         struct rte_flow_error *error)
2811 {
2812         struct mlx5_priv *priv = dev->data->dev_private;
2813         struct mlx5_dev_ctx_shared *sh = priv->sh;
2814         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815         struct mlx5dv_dr_domain *domain;
2816         uint32_t idx = 0;
2817         int ret;
2818
2819         /* Lookup a matching resource from cache. */
2820         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                       sh->push_vlan_action_list, idx, cache_resource, next) {
2822                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823                     resource->ft_type == cache_resource->ft_type) {
2824                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2825                                 "refcnt %d++",
2826                                 (void *)cache_resource,
2827                                 rte_atomic32_read(&cache_resource->refcnt));
2828                         rte_atomic32_inc(&cache_resource->refcnt);
2829                         dev_flow->handle->dvh.rix_push_vlan = idx;
2830                         dev_flow->dv.push_vlan_res = cache_resource;
2831                         return 0;
2832                 }
2833         }
2834         /* Register new push_vlan action resource. */
2835         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836                                        &dev_flow->handle->dvh.rix_push_vlan);
2837         if (!cache_resource)
2838                 return rte_flow_error_set(error, ENOMEM,
2839                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840                                           "cannot allocate resource memory");
2841         *cache_resource = *resource;
2842         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843                 domain = sh->fdb_domain;
2844         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845                 domain = sh->rx_domain;
2846         else
2847                 domain = sh->tx_domain;
2848         ret = mlx5_flow_os_create_flow_action_push_vlan
2849                                         (domain, resource->vlan_tag,
2850                                          &cache_resource->action);
2851         if (ret) {
2852                 mlx5_free(cache_resource);
2853                 return rte_flow_error_set(error, ENOMEM,
2854                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855                                           NULL, "cannot create action");
2856         }
2857         rte_atomic32_init(&cache_resource->refcnt);
2858         rte_atomic32_inc(&cache_resource->refcnt);
2859         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860                      &sh->push_vlan_action_list,
2861                      dev_flow->handle->dvh.rix_push_vlan,
2862                      cache_resource, next);
2863         dev_flow->dv.push_vlan_res = cache_resource;
2864         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865                 (void *)cache_resource,
2866                 rte_atomic32_read(&cache_resource->refcnt));
2867         return 0;
2868 }
2869 /**
2870  * Get the size of specific rte_flow_item_type hdr size
2871  *
2872  * @param[in] item_type
2873  *   Tested rte_flow_item_type.
2874  *
2875  * @return
2876  *   sizeof struct item_type, 0 if void or irrelevant.
2877  */
2878 static size_t
2879 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2880 {
2881         size_t retval;
2882
2883         switch (item_type) {
2884         case RTE_FLOW_ITEM_TYPE_ETH:
2885                 retval = sizeof(struct rte_ether_hdr);
2886                 break;
2887         case RTE_FLOW_ITEM_TYPE_VLAN:
2888                 retval = sizeof(struct rte_vlan_hdr);
2889                 break;
2890         case RTE_FLOW_ITEM_TYPE_IPV4:
2891                 retval = sizeof(struct rte_ipv4_hdr);
2892                 break;
2893         case RTE_FLOW_ITEM_TYPE_IPV6:
2894                 retval = sizeof(struct rte_ipv6_hdr);
2895                 break;
2896         case RTE_FLOW_ITEM_TYPE_UDP:
2897                 retval = sizeof(struct rte_udp_hdr);
2898                 break;
2899         case RTE_FLOW_ITEM_TYPE_TCP:
2900                 retval = sizeof(struct rte_tcp_hdr);
2901                 break;
2902         case RTE_FLOW_ITEM_TYPE_VXLAN:
2903         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2904                 retval = sizeof(struct rte_vxlan_hdr);
2905                 break;
2906         case RTE_FLOW_ITEM_TYPE_GRE:
2907         case RTE_FLOW_ITEM_TYPE_NVGRE:
2908                 retval = sizeof(struct rte_gre_hdr);
2909                 break;
2910         case RTE_FLOW_ITEM_TYPE_MPLS:
2911                 retval = sizeof(struct rte_mpls_hdr);
2912                 break;
2913         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2914         default:
2915                 retval = 0;
2916                 break;
2917         }
2918         return retval;
2919 }
2920
2921 #define MLX5_ENCAP_IPV4_VERSION         0x40
2922 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2923 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2924 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2925 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2926 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2927 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2928
2929 /**
2930  * Convert the encap action data from list of rte_flow_item to raw buffer
2931  *
2932  * @param[in] items
2933  *   Pointer to rte_flow_item objects list.
2934  * @param[out] buf
2935  *   Pointer to the output buffer.
2936  * @param[out] size
2937  *   Pointer to the output buffer size.
2938  * @param[out] error
2939  *   Pointer to the error structure.
2940  *
2941  * @return
2942  *   0 on success, a negative errno value otherwise and rte_errno is set.
2943  */
2944 static int
2945 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2946                            size_t *size, struct rte_flow_error *error)
2947 {
2948         struct rte_ether_hdr *eth = NULL;
2949         struct rte_vlan_hdr *vlan = NULL;
2950         struct rte_ipv4_hdr *ipv4 = NULL;
2951         struct rte_ipv6_hdr *ipv6 = NULL;
2952         struct rte_udp_hdr *udp = NULL;
2953         struct rte_vxlan_hdr *vxlan = NULL;
2954         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2955         struct rte_gre_hdr *gre = NULL;
2956         size_t len;
2957         size_t temp_size = 0;
2958
2959         if (!items)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION,
2962                                           NULL, "invalid empty data");
2963         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2964                 len = flow_dv_get_item_hdr_len(items->type);
2965                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2966                         return rte_flow_error_set(error, EINVAL,
2967                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2968                                                   (void *)items->type,
2969                                                   "items total size is too big"
2970                                                   " for encap action");
2971                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2972                 switch (items->type) {
2973                 case RTE_FLOW_ITEM_TYPE_ETH:
2974                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2975                         break;
2976                 case RTE_FLOW_ITEM_TYPE_VLAN:
2977                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2978                         if (!eth)
2979                                 return rte_flow_error_set(error, EINVAL,
2980                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2981                                                 (void *)items->type,
2982                                                 "eth header not found");
2983                         if (!eth->ether_type)
2984                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2985                         break;
2986                 case RTE_FLOW_ITEM_TYPE_IPV4:
2987                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2988                         if (!vlan && !eth)
2989                                 return rte_flow_error_set(error, EINVAL,
2990                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2991                                                 (void *)items->type,
2992                                                 "neither eth nor vlan"
2993                                                 " header found");
2994                         if (vlan && !vlan->eth_proto)
2995                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2996                         else if (eth && !eth->ether_type)
2997                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2998                         if (!ipv4->version_ihl)
2999                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3000                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3001                         if (!ipv4->time_to_live)
3002                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3003                         break;
3004                 case RTE_FLOW_ITEM_TYPE_IPV6:
3005                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3006                         if (!vlan && !eth)
3007                                 return rte_flow_error_set(error, EINVAL,
3008                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3009                                                 (void *)items->type,
3010                                                 "neither eth nor vlan"
3011                                                 " header found");
3012                         if (vlan && !vlan->eth_proto)
3013                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3014                         else if (eth && !eth->ether_type)
3015                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3016                         if (!ipv6->vtc_flow)
3017                                 ipv6->vtc_flow =
3018                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3019                         if (!ipv6->hop_limits)
3020                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3021                         break;
3022                 case RTE_FLOW_ITEM_TYPE_UDP:
3023                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3024                         if (!ipv4 && !ipv6)
3025                                 return rte_flow_error_set(error, EINVAL,
3026                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3027                                                 (void *)items->type,
3028                                                 "ip header not found");
3029                         if (ipv4 && !ipv4->next_proto_id)
3030                                 ipv4->next_proto_id = IPPROTO_UDP;
3031                         else if (ipv6 && !ipv6->proto)
3032                                 ipv6->proto = IPPROTO_UDP;
3033                         break;
3034                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3035                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3036                         if (!udp)
3037                                 return rte_flow_error_set(error, EINVAL,
3038                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3039                                                 (void *)items->type,
3040                                                 "udp header not found");
3041                         if (!udp->dst_port)
3042                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3043                         if (!vxlan->vx_flags)
3044                                 vxlan->vx_flags =
3045                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3046                         break;
3047                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3048                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3049                         if (!udp)
3050                                 return rte_flow_error_set(error, EINVAL,
3051                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3052                                                 (void *)items->type,
3053                                                 "udp header not found");
3054                         if (!vxlan_gpe->proto)
3055                                 return rte_flow_error_set(error, EINVAL,
3056                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3057                                                 (void *)items->type,
3058                                                 "next protocol not found");
3059                         if (!udp->dst_port)
3060                                 udp->dst_port =
3061                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3062                         if (!vxlan_gpe->vx_flags)
3063                                 vxlan_gpe->vx_flags =
3064                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3065                         break;
3066                 case RTE_FLOW_ITEM_TYPE_GRE:
3067                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3068                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3069                         if (!gre->proto)
3070                                 return rte_flow_error_set(error, EINVAL,
3071                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3072                                                 (void *)items->type,
3073                                                 "next protocol not found");
3074                         if (!ipv4 && !ipv6)
3075                                 return rte_flow_error_set(error, EINVAL,
3076                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3077                                                 (void *)items->type,
3078                                                 "ip header not found");
3079                         if (ipv4 && !ipv4->next_proto_id)
3080                                 ipv4->next_proto_id = IPPROTO_GRE;
3081                         else if (ipv6 && !ipv6->proto)
3082                                 ipv6->proto = IPPROTO_GRE;
3083                         break;
3084                 case RTE_FLOW_ITEM_TYPE_VOID:
3085                         break;
3086                 default:
3087                         return rte_flow_error_set(error, EINVAL,
3088                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3089                                                   (void *)items->type,
3090                                                   "unsupported item type");
3091                         break;
3092                 }
3093                 temp_size += len;
3094         }
3095         *size = temp_size;
3096         return 0;
3097 }
3098
3099 static int
3100 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3101 {
3102         struct rte_ether_hdr *eth = NULL;
3103         struct rte_vlan_hdr *vlan = NULL;
3104         struct rte_ipv6_hdr *ipv6 = NULL;
3105         struct rte_udp_hdr *udp = NULL;
3106         char *next_hdr;
3107         uint16_t proto;
3108
3109         eth = (struct rte_ether_hdr *)data;
3110         next_hdr = (char *)(eth + 1);
3111         proto = RTE_BE16(eth->ether_type);
3112
3113         /* VLAN skipping */
3114         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3115                 vlan = (struct rte_vlan_hdr *)next_hdr;
3116                 proto = RTE_BE16(vlan->eth_proto);
3117                 next_hdr += sizeof(struct rte_vlan_hdr);
3118         }
3119
3120         /* HW calculates IPv4 csum. no need to proceed */
3121         if (proto == RTE_ETHER_TYPE_IPV4)
3122                 return 0;
3123
3124         /* non IPv4/IPv6 header. not supported */
3125         if (proto != RTE_ETHER_TYPE_IPV6) {
3126                 return rte_flow_error_set(error, ENOTSUP,
3127                                           RTE_FLOW_ERROR_TYPE_ACTION,
3128                                           NULL, "Cannot offload non IPv4/IPv6");
3129         }
3130
3131         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3132
3133         /* ignore non UDP */
3134         if (ipv6->proto != IPPROTO_UDP)
3135                 return 0;
3136
3137         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3138         udp->dgram_cksum = 0;
3139
3140         return 0;
3141 }
3142
3143 /**
3144  * Convert L2 encap action to DV specification.
3145  *
3146  * @param[in] dev
3147  *   Pointer to rte_eth_dev structure.
3148  * @param[in] action
3149  *   Pointer to action structure.
3150  * @param[in, out] dev_flow
3151  *   Pointer to the mlx5_flow.
3152  * @param[in] transfer
3153  *   Mark if the flow is E-Switch flow.
3154  * @param[out] error
3155  *   Pointer to the error structure.
3156  *
3157  * @return
3158  *   0 on success, a negative errno value otherwise and rte_errno is set.
3159  */
3160 static int
3161 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3162                                const struct rte_flow_action *action,
3163                                struct mlx5_flow *dev_flow,
3164                                uint8_t transfer,
3165                                struct rte_flow_error *error)
3166 {
3167         const struct rte_flow_item *encap_data;
3168         const struct rte_flow_action_raw_encap *raw_encap_data;
3169         struct mlx5_flow_dv_encap_decap_resource res = {
3170                 .reformat_type =
3171                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3172                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3173                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3174         };
3175
3176         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3177                 raw_encap_data =
3178                         (const struct rte_flow_action_raw_encap *)action->conf;
3179                 res.size = raw_encap_data->size;
3180                 memcpy(res.buf, raw_encap_data->data, res.size);
3181         } else {
3182                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3183                         encap_data =
3184                                 ((const struct rte_flow_action_vxlan_encap *)
3185                                                 action->conf)->definition;
3186                 else
3187                         encap_data =
3188                                 ((const struct rte_flow_action_nvgre_encap *)
3189                                                 action->conf)->definition;
3190                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3191                                                &res.size, error))
3192                         return -rte_errno;
3193         }
3194         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3195                 return -rte_errno;
3196         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3197                 return rte_flow_error_set(error, EINVAL,
3198                                           RTE_FLOW_ERROR_TYPE_ACTION,
3199                                           NULL, "can't create L2 encap action");
3200         return 0;
3201 }
3202
3203 /**
3204  * Convert L2 decap action to DV specification.
3205  *
3206  * @param[in] dev
3207  *   Pointer to rte_eth_dev structure.
3208  * @param[in, out] dev_flow
3209  *   Pointer to the mlx5_flow.
3210  * @param[in] transfer
3211  *   Mark if the flow is E-Switch flow.
3212  * @param[out] error
3213  *   Pointer to the error structure.
3214  *
3215  * @return
3216  *   0 on success, a negative errno value otherwise and rte_errno is set.
3217  */
3218 static int
3219 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3220                                struct mlx5_flow *dev_flow,
3221                                uint8_t transfer,
3222                                struct rte_flow_error *error)
3223 {
3224         struct mlx5_flow_dv_encap_decap_resource res = {
3225                 .size = 0,
3226                 .reformat_type =
3227                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3228                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3229                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3230         };
3231
3232         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3233                 return rte_flow_error_set(error, EINVAL,
3234                                           RTE_FLOW_ERROR_TYPE_ACTION,
3235                                           NULL, "can't create L2 decap action");
3236         return 0;
3237 }
3238
3239 /**
3240  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3241  *
3242  * @param[in] dev
3243  *   Pointer to rte_eth_dev structure.
3244  * @param[in] action
3245  *   Pointer to action structure.
3246  * @param[in, out] dev_flow
3247  *   Pointer to the mlx5_flow.
3248  * @param[in] attr
3249  *   Pointer to the flow attributes.
3250  * @param[out] error
3251  *   Pointer to the error structure.
3252  *
3253  * @return
3254  *   0 on success, a negative errno value otherwise and rte_errno is set.
3255  */
3256 static int
3257 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3258                                 const struct rte_flow_action *action,
3259                                 struct mlx5_flow *dev_flow,
3260                                 const struct rte_flow_attr *attr,
3261                                 struct rte_flow_error *error)
3262 {
3263         const struct rte_flow_action_raw_encap *encap_data;
3264         struct mlx5_flow_dv_encap_decap_resource res;
3265
3266         memset(&res, 0, sizeof(res));
3267         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3268         res.size = encap_data->size;
3269         memcpy(res.buf, encap_data->data, res.size);
3270         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3271                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3272                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3273         if (attr->transfer)
3274                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3275         else
3276                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3277                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3278         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ACTION,
3281                                           NULL, "can't create encap action");
3282         return 0;
3283 }
3284
3285 /**
3286  * Create action push VLAN.
3287  *
3288  * @param[in] dev
3289  *   Pointer to rte_eth_dev structure.
3290  * @param[in] attr
3291  *   Pointer to the flow attributes.
3292  * @param[in] vlan
3293  *   Pointer to the vlan to push to the Ethernet header.
3294  * @param[in, out] dev_flow
3295  *   Pointer to the mlx5_flow.
3296  * @param[out] error
3297  *   Pointer to the error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3304                                 const struct rte_flow_attr *attr,
3305                                 const struct rte_vlan_hdr *vlan,
3306                                 struct mlx5_flow *dev_flow,
3307                                 struct rte_flow_error *error)
3308 {
3309         struct mlx5_flow_dv_push_vlan_action_resource res;
3310
3311         memset(&res, 0, sizeof(res));
3312         res.vlan_tag =
3313                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3314                                  vlan->vlan_tci);
3315         if (attr->transfer)
3316                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3317         else
3318                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3319                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3320         return flow_dv_push_vlan_action_resource_register
3321                                             (dev, &res, dev_flow, error);
3322 }
3323
3324 /**
3325  * Validate the modify-header actions.
3326  *
3327  * @param[in] action_flags
3328  *   Holds the actions detected until now.
3329  * @param[in] action
3330  *   Pointer to the modify action.
3331  * @param[out] error
3332  *   Pointer to error structure.
3333  *
3334  * @return
3335  *   0 on success, a negative errno value otherwise and rte_errno is set.
3336  */
3337 static int
3338 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3339                                    const struct rte_flow_action *action,
3340                                    struct rte_flow_error *error)
3341 {
3342         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3343                 return rte_flow_error_set(error, EINVAL,
3344                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3345                                           NULL, "action configuration not set");
3346         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347                 return rte_flow_error_set(error, EINVAL,
3348                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349                                           "can't have encap action before"
3350                                           " modify action");
3351         return 0;
3352 }
3353
3354 /**
3355  * Validate the modify-header MAC address actions.
3356  *
3357  * @param[in] action_flags
3358  *   Holds the actions detected until now.
3359  * @param[in] action
3360  *   Pointer to the modify action.
3361  * @param[in] item_flags
3362  *   Holds the items detected.
3363  * @param[out] error
3364  *   Pointer to error structure.
3365  *
3366  * @return
3367  *   0 on success, a negative errno value otherwise and rte_errno is set.
3368  */
3369 static int
3370 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3371                                    const struct rte_flow_action *action,
3372                                    const uint64_t item_flags,
3373                                    struct rte_flow_error *error)
3374 {
3375         int ret = 0;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3380                         return rte_flow_error_set(error, EINVAL,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "no L2 item in pattern");
3384         }
3385         return ret;
3386 }
3387
3388 /**
3389  * Validate the modify-header IPv4 address actions.
3390  *
3391  * @param[in] action_flags
3392  *   Holds the actions detected until now.
3393  * @param[in] action
3394  *   Pointer to the modify action.
3395  * @param[in] item_flags
3396  *   Holds the items detected.
3397  * @param[out] error
3398  *   Pointer to error structure.
3399  *
3400  * @return
3401  *   0 on success, a negative errno value otherwise and rte_errno is set.
3402  */
3403 static int
3404 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3405                                     const struct rte_flow_action *action,
3406                                     const uint64_t item_flags,
3407                                     struct rte_flow_error *error)
3408 {
3409         int ret = 0;
3410         uint64_t layer;
3411
3412         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3413         if (!ret) {
3414                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3416                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3417                 if (!(item_flags & layer))
3418                         return rte_flow_error_set(error, EINVAL,
3419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3420                                                   NULL,
3421                                                   "no ipv4 item in pattern");
3422         }
3423         return ret;
3424 }
3425
3426 /**
3427  * Validate the modify-header IPv6 address actions.
3428  *
3429  * @param[in] action_flags
3430  *   Holds the actions detected until now.
3431  * @param[in] action
3432  *   Pointer to the modify action.
3433  * @param[in] item_flags
3434  *   Holds the items detected.
3435  * @param[out] error
3436  *   Pointer to error structure.
3437  *
3438  * @return
3439  *   0 on success, a negative errno value otherwise and rte_errno is set.
3440  */
3441 static int
3442 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3443                                     const struct rte_flow_action *action,
3444                                     const uint64_t item_flags,
3445                                     struct rte_flow_error *error)
3446 {
3447         int ret = 0;
3448         uint64_t layer;
3449
3450         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3451         if (!ret) {
3452                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3454                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3455                 if (!(item_flags & layer))
3456                         return rte_flow_error_set(error, EINVAL,
3457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3458                                                   NULL,
3459                                                   "no ipv6 item in pattern");
3460         }
3461         return ret;
3462 }
3463
3464 /**
3465  * Validate the modify-header TP actions.
3466  *
3467  * @param[in] action_flags
3468  *   Holds the actions detected until now.
3469  * @param[in] action
3470  *   Pointer to the modify action.
3471  * @param[in] item_flags
3472  *   Holds the items detected.
3473  * @param[out] error
3474  *   Pointer to error structure.
3475  *
3476  * @return
3477  *   0 on success, a negative errno value otherwise and rte_errno is set.
3478  */
3479 static int
3480 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3481                                   const struct rte_flow_action *action,
3482                                   const uint64_t item_flags,
3483                                   struct rte_flow_error *error)
3484 {
3485         int ret = 0;
3486         uint64_t layer;
3487
3488         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3489         if (!ret) {
3490                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3491                                  MLX5_FLOW_LAYER_INNER_L4 :
3492                                  MLX5_FLOW_LAYER_OUTER_L4;
3493                 if (!(item_flags & layer))
3494                         return rte_flow_error_set(error, EINVAL,
3495                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3496                                                   NULL, "no transport layer "
3497                                                   "in pattern");
3498         }
3499         return ret;
3500 }
3501
3502 /**
3503  * Validate the modify-header actions of increment/decrement
3504  * TCP Sequence-number.
3505  *
3506  * @param[in] action_flags
3507  *   Holds the actions detected until now.
3508  * @param[in] action
3509  *   Pointer to the modify action.
3510  * @param[in] item_flags
3511  *   Holds the items detected.
3512  * @param[out] error
3513  *   Pointer to error structure.
3514  *
3515  * @return
3516  *   0 on success, a negative errno value otherwise and rte_errno is set.
3517  */
3518 static int
3519 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3520                                        const struct rte_flow_action *action,
3521                                        const uint64_t item_flags,
3522                                        struct rte_flow_error *error)
3523 {
3524         int ret = 0;
3525         uint64_t layer;
3526
3527         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3528         if (!ret) {
3529                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3530                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3531                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3532                 if (!(item_flags & layer))
3533                         return rte_flow_error_set(error, EINVAL,
3534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3535                                                   NULL, "no TCP item in"
3536                                                   " pattern");
3537                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3538                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3539                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3540                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3541                         return rte_flow_error_set(error, EINVAL,
3542                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3543                                                   NULL,
3544                                                   "cannot decrease and increase"
3545                                                   " TCP sequence number"
3546                                                   " at the same time");
3547         }
3548         return ret;
3549 }
3550
3551 /**
3552  * Validate the modify-header actions of increment/decrement
3553  * TCP Acknowledgment number.
3554  *
3555  * @param[in] action_flags
3556  *   Holds the actions detected until now.
3557  * @param[in] action
3558  *   Pointer to the modify action.
3559  * @param[in] item_flags
3560  *   Holds the items detected.
3561  * @param[out] error
3562  *   Pointer to error structure.
3563  *
3564  * @return
3565  *   0 on success, a negative errno value otherwise and rte_errno is set.
3566  */
3567 static int
3568 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3569                                        const struct rte_flow_action *action,
3570                                        const uint64_t item_flags,
3571                                        struct rte_flow_error *error)
3572 {
3573         int ret = 0;
3574         uint64_t layer;
3575
3576         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3577         if (!ret) {
3578                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3580                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581                 if (!(item_flags & layer))
3582                         return rte_flow_error_set(error, EINVAL,
3583                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3584                                                   NULL, "no TCP item in"
3585                                                   " pattern");
3586                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3587                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3588                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3589                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3590                         return rte_flow_error_set(error, EINVAL,
3591                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3592                                                   NULL,
3593                                                   "cannot decrease and increase"
3594                                                   " TCP acknowledgment number"
3595                                                   " at the same time");
3596         }
3597         return ret;
3598 }
3599
3600 /**
3601  * Validate the modify-header TTL actions.
3602  *
3603  * @param[in] action_flags
3604  *   Holds the actions detected until now.
3605  * @param[in] action
3606  *   Pointer to the modify action.
3607  * @param[in] item_flags
3608  *   Holds the items detected.
3609  * @param[out] error
3610  *   Pointer to error structure.
3611  *
3612  * @return
3613  *   0 on success, a negative errno value otherwise and rte_errno is set.
3614  */
3615 static int
3616 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3617                                    const struct rte_flow_action *action,
3618                                    const uint64_t item_flags,
3619                                    struct rte_flow_error *error)
3620 {
3621         int ret = 0;
3622         uint64_t layer;
3623
3624         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3625         if (!ret) {
3626                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3627                                  MLX5_FLOW_LAYER_INNER_L3 :
3628                                  MLX5_FLOW_LAYER_OUTER_L3;
3629                 if (!(item_flags & layer))
3630                         return rte_flow_error_set(error, EINVAL,
3631                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3632                                                   NULL,
3633                                                   "no IP protocol in pattern");
3634         }
3635         return ret;
3636 }
3637
3638 /**
3639  * Validate jump action.
3640  *
3641  * @param[in] action
3642  *   Pointer to the jump action.
3643  * @param[in] action_flags
3644  *   Holds the actions detected until now.
3645  * @param[in] attributes
3646  *   Pointer to flow attributes
3647  * @param[in] external
3648  *   Action belongs to flow rule created by request external to PMD.
3649  * @param[out] error
3650  *   Pointer to error structure.
3651  *
3652  * @return
3653  *   0 on success, a negative errno value otherwise and rte_errno is set.
3654  */
3655 static int
3656 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3657                              uint64_t action_flags,
3658                              const struct rte_flow_attr *attributes,
3659                              bool external, struct rte_flow_error *error)
3660 {
3661         uint32_t target_group, table;
3662         int ret = 0;
3663
3664         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3665                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3666                 return rte_flow_error_set(error, EINVAL,
3667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668                                           "can't have 2 fate actions in"
3669                                           " same flow");
3670         if (action_flags & MLX5_FLOW_ACTION_METER)
3671                 return rte_flow_error_set(error, ENOTSUP,
3672                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673                                           "jump with meter not support");
3674         if (!action->conf)
3675                 return rte_flow_error_set(error, EINVAL,
3676                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3677                                           NULL, "action configuration not set");
3678         target_group =
3679                 ((const struct rte_flow_action_jump *)action->conf)->group;
3680         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3681                                        true, &table, error);
3682         if (ret)
3683                 return ret;
3684         if (attributes->group == target_group)
3685                 return rte_flow_error_set(error, EINVAL,
3686                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687                                           "target group must be other than"
3688                                           " the current flow group");
3689         return 0;
3690 }
3691
3692 /*
3693  * Validate the port_id action.
3694  *
3695  * @param[in] dev
3696  *   Pointer to rte_eth_dev structure.
3697  * @param[in] action_flags
3698  *   Bit-fields that holds the actions detected until now.
3699  * @param[in] action
3700  *   Port_id RTE action structure.
3701  * @param[in] attr
3702  *   Attributes of flow that includes this action.
3703  * @param[out] error
3704  *   Pointer to error structure.
3705  *
3706  * @return
3707  *   0 on success, a negative errno value otherwise and rte_errno is set.
3708  */
3709 static int
3710 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3711                                 uint64_t action_flags,
3712                                 const struct rte_flow_action *action,
3713                                 const struct rte_flow_attr *attr,
3714                                 struct rte_flow_error *error)
3715 {
3716         const struct rte_flow_action_port_id *port_id;
3717         struct mlx5_priv *act_priv;
3718         struct mlx5_priv *dev_priv;
3719         uint16_t port;
3720
3721         if (!attr->transfer)
3722                 return rte_flow_error_set(error, ENOTSUP,
3723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3724                                           NULL,
3725                                           "port id action is valid in transfer"
3726                                           " mode only");
3727         if (!action || !action->conf)
3728                 return rte_flow_error_set(error, ENOTSUP,
3729                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3730                                           NULL,
3731                                           "port id action parameters must be"
3732                                           " specified");
3733         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3734                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3735                 return rte_flow_error_set(error, EINVAL,
3736                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3737                                           "can have only one fate actions in"
3738                                           " a flow");
3739         dev_priv = mlx5_dev_to_eswitch_info(dev);
3740         if (!dev_priv)
3741                 return rte_flow_error_set(error, rte_errno,
3742                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3743                                           NULL,
3744                                           "failed to obtain E-Switch info");
3745         port_id = action->conf;
3746         port = port_id->original ? dev->data->port_id : port_id->id;
3747         act_priv = mlx5_port_to_eswitch_info(port, false);
3748         if (!act_priv)
3749                 return rte_flow_error_set
3750                                 (error, rte_errno,
3751                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3752                                  "failed to obtain E-Switch port id for port");
3753         if (act_priv->domain_id != dev_priv->domain_id)
3754                 return rte_flow_error_set
3755                                 (error, EINVAL,
3756                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3757                                  "port does not belong to"
3758                                  " E-Switch being configured");
3759         return 0;
3760 }
3761
3762 /**
3763  * Get the maximum number of modify header actions.
3764  *
3765  * @param dev
3766  *   Pointer to rte_eth_dev structure.
3767  * @param flags
3768  *   Flags bits to check if root level.
3769  *
3770  * @return
3771  *   Max number of modify header actions device can support.
3772  */
3773 static inline unsigned int
3774 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3775                               uint64_t flags)
3776 {
3777         /*
3778          * There's no way to directly query the max capacity from FW.
3779          * The maximal value on root table should be assumed to be supported.
3780          */
3781         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3782                 return MLX5_MAX_MODIFY_NUM;
3783         else
3784                 return MLX5_ROOT_TBL_MODIFY_NUM;
3785 }
3786
3787 /**
3788  * Validate the meter action.
3789  *
3790  * @param[in] dev
3791  *   Pointer to rte_eth_dev structure.
3792  * @param[in] action_flags
3793  *   Bit-fields that holds the actions detected until now.
3794  * @param[in] action
3795  *   Pointer to the meter action.
3796  * @param[in] attr
3797  *   Attributes of flow that includes this action.
3798  * @param[out] error
3799  *   Pointer to error structure.
3800  *
3801  * @return
3802  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3803  */
3804 static int
3805 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3806                                 uint64_t action_flags,
3807                                 const struct rte_flow_action *action,
3808                                 const struct rte_flow_attr *attr,
3809                                 struct rte_flow_error *error)
3810 {
3811         struct mlx5_priv *priv = dev->data->dev_private;
3812         const struct rte_flow_action_meter *am = action->conf;
3813         struct mlx5_flow_meter *fm;
3814
3815         if (!am)
3816                 return rte_flow_error_set(error, EINVAL,
3817                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3818                                           "meter action conf is NULL");
3819
3820         if (action_flags & MLX5_FLOW_ACTION_METER)
3821                 return rte_flow_error_set(error, ENOTSUP,
3822                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823                                           "meter chaining not support");
3824         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3825                 return rte_flow_error_set(error, ENOTSUP,
3826                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827                                           "meter with jump not support");
3828         if (!priv->mtr_en)
3829                 return rte_flow_error_set(error, ENOTSUP,
3830                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3831                                           NULL,
3832                                           "meter action not supported");
3833         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3834         if (!fm)
3835                 return rte_flow_error_set(error, EINVAL,
3836                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3837                                           "Meter not found");
3838         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3839               (!fm->ingress && !attr->ingress && attr->egress) ||
3840               (!fm->egress && !attr->egress && attr->ingress))))
3841                 return rte_flow_error_set(error, EINVAL,
3842                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3843                                           "Flow attributes are either invalid "
3844                                           "or have a conflict with current "
3845                                           "meter attributes");
3846         return 0;
3847 }
3848
3849 /**
3850  * Validate the age action.
3851  *
3852  * @param[in] action_flags
3853  *   Holds the actions detected until now.
3854  * @param[in] action
3855  *   Pointer to the age action.
3856  * @param[in] dev
3857  *   Pointer to the Ethernet device structure.
3858  * @param[out] error
3859  *   Pointer to error structure.
3860  *
3861  * @return
3862  *   0 on success, a negative errno value otherwise and rte_errno is set.
3863  */
3864 static int
3865 flow_dv_validate_action_age(uint64_t action_flags,
3866                             const struct rte_flow_action *action,
3867                             struct rte_eth_dev *dev,
3868                             struct rte_flow_error *error)
3869 {
3870         struct mlx5_priv *priv = dev->data->dev_private;
3871         const struct rte_flow_action_age *age = action->conf;
3872
3873         if (!priv->config.devx || priv->counter_fallback)
3874                 return rte_flow_error_set(error, ENOTSUP,
3875                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3876                                           NULL,
3877                                           "age action not supported");
3878         if (!(action->conf))
3879                 return rte_flow_error_set(error, EINVAL,
3880                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3881                                           "configuration cannot be null");
3882         if (age->timeout >= UINT16_MAX / 2 / 10)
3883                 return rte_flow_error_set(error, ENOTSUP,
3884                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3885                                           "Max age time: 3275 seconds");
3886         if (action_flags & MLX5_FLOW_ACTION_AGE)
3887                 return rte_flow_error_set(error, EINVAL,
3888                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3889                                           "Duplicate age ctions set");
3890         return 0;
3891 }
3892
3893 /**
3894  * Validate the modify-header IPv4 DSCP actions.
3895  *
3896  * @param[in] action_flags
3897  *   Holds the actions detected until now.
3898  * @param[in] action
3899  *   Pointer to the modify action.
3900  * @param[in] item_flags
3901  *   Holds the items detected.
3902  * @param[out] error
3903  *   Pointer to error structure.
3904  *
3905  * @return
3906  *   0 on success, a negative errno value otherwise and rte_errno is set.
3907  */
3908 static int
3909 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3910                                          const struct rte_flow_action *action,
3911                                          const uint64_t item_flags,
3912                                          struct rte_flow_error *error)
3913 {
3914         int ret = 0;
3915
3916         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3917         if (!ret) {
3918                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3919                         return rte_flow_error_set(error, EINVAL,
3920                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3921                                                   NULL,
3922                                                   "no ipv4 item in pattern");
3923         }
3924         return ret;
3925 }
3926
3927 /**
3928  * Validate the modify-header IPv6 DSCP actions.
3929  *
3930  * @param[in] action_flags
3931  *   Holds the actions detected until now.
3932  * @param[in] action
3933  *   Pointer to the modify action.
3934  * @param[in] item_flags
3935  *   Holds the items detected.
3936  * @param[out] error
3937  *   Pointer to error structure.
3938  *
3939  * @return
3940  *   0 on success, a negative errno value otherwise and rte_errno is set.
3941  */
3942 static int
3943 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3944                                          const struct rte_flow_action *action,
3945                                          const uint64_t item_flags,
3946                                          struct rte_flow_error *error)
3947 {
3948         int ret = 0;
3949
3950         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3951         if (!ret) {
3952                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3953                         return rte_flow_error_set(error, EINVAL,
3954                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3955                                                   NULL,
3956                                                   "no ipv6 item in pattern");
3957         }
3958         return ret;
3959 }
3960
3961 /**
3962  * Find existing modify-header resource or create and register a new one.
3963  *
3964  * @param dev[in, out]
3965  *   Pointer to rte_eth_dev structure.
3966  * @param[in, out] resource
3967  *   Pointer to modify-header resource.
3968  * @parm[in, out] dev_flow
3969  *   Pointer to the dev_flow.
3970  * @param[out] error
3971  *   pointer to error structure.
3972  *
3973  * @return
3974  *   0 on success otherwise -errno and errno is set.
3975  */
3976 static int
3977 flow_dv_modify_hdr_resource_register
3978                         (struct rte_eth_dev *dev,
3979                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3980                          struct mlx5_flow *dev_flow,
3981                          struct rte_flow_error *error)
3982 {
3983         struct mlx5_priv *priv = dev->data->dev_private;
3984         struct mlx5_dev_ctx_shared *sh = priv->sh;
3985         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3986         struct mlx5dv_dr_domain *ns;
3987         uint32_t actions_len;
3988         int ret;
3989
3990         resource->flags = dev_flow->dv.group ? 0 :
3991                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3992         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3993                                     resource->flags))
3994                 return rte_flow_error_set(error, EOVERFLOW,
3995                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996                                           "too many modify header items");
3997         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3998                 ns = sh->fdb_domain;
3999         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4000                 ns = sh->tx_domain;
4001         else
4002                 ns = sh->rx_domain;
4003         /* Lookup a matching resource from cache. */
4004         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4005         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4006                 if (resource->ft_type == cache_resource->ft_type &&
4007                     resource->actions_num == cache_resource->actions_num &&
4008                     resource->flags == cache_resource->flags &&
4009                     !memcmp((const void *)resource->actions,
4010                             (const void *)cache_resource->actions,
4011                             actions_len)) {
4012                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4013                                 (void *)cache_resource,
4014                                 rte_atomic32_read(&cache_resource->refcnt));
4015                         rte_atomic32_inc(&cache_resource->refcnt);
4016                         dev_flow->handle->dvh.modify_hdr = cache_resource;
4017                         return 0;
4018                 }
4019         }
4020         /* Register new modify-header resource. */
4021         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4022                                     sizeof(*cache_resource) + actions_len, 0,
4023                                     SOCKET_ID_ANY);
4024         if (!cache_resource)
4025                 return rte_flow_error_set(error, ENOMEM,
4026                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4027                                           "cannot allocate resource memory");
4028         *cache_resource = *resource;
4029         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4030         ret = mlx5_flow_os_create_flow_action_modify_header
4031                                         (sh->ctx, ns, cache_resource,
4032                                          actions_len, &cache_resource->action);
4033         if (ret) {
4034                 mlx5_free(cache_resource);
4035                 return rte_flow_error_set(error, ENOMEM,
4036                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4037                                           NULL, "cannot create action");
4038         }
4039         rte_atomic32_init(&cache_resource->refcnt);
4040         rte_atomic32_inc(&cache_resource->refcnt);
4041         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4042         dev_flow->handle->dvh.modify_hdr = cache_resource;
4043         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4044                 (void *)cache_resource,
4045                 rte_atomic32_read(&cache_resource->refcnt));
4046         return 0;
4047 }
4048
4049 /**
4050  * Get DV flow counter by index.
4051  *
4052  * @param[in] dev
4053  *   Pointer to the Ethernet device structure.
4054  * @param[in] idx
4055  *   mlx5 flow counter index in the container.
4056  * @param[out] ppool
4057  *   mlx5 flow counter pool in the container,
4058  *
4059  * @return
4060  *   Pointer to the counter, NULL otherwise.
4061  */
4062 static struct mlx5_flow_counter *
4063 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4064                            uint32_t idx,
4065                            struct mlx5_flow_counter_pool **ppool)
4066 {
4067         struct mlx5_priv *priv = dev->data->dev_private;
4068         struct mlx5_pools_container *cont;
4069         struct mlx5_flow_counter_pool *pool;
4070         uint32_t batch = 0, age = 0;
4071
4072         idx--;
4073         age = MLX_CNT_IS_AGE(idx);
4074         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4075         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4076                 idx -= MLX5_CNT_BATCH_OFFSET;
4077                 batch = 1;
4078         }
4079         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4080         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4081         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4082         MLX5_ASSERT(pool);
4083         if (ppool)
4084                 *ppool = pool;
4085         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4086 }
4087
4088 /**
4089  * Check the devx counter belongs to the pool.
4090  *
4091  * @param[in] pool
4092  *   Pointer to the counter pool.
4093  * @param[in] id
4094  *   The counter devx ID.
4095  *
4096  * @return
4097  *   True if counter belongs to the pool, false otherwise.
4098  */
4099 static bool
4100 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4101 {
4102         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4103                    MLX5_COUNTERS_PER_POOL;
4104
4105         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4106                 return true;
4107         return false;
4108 }
4109
4110 /**
4111  * Get a pool by devx counter ID.
4112  *
4113  * @param[in] cont
4114  *   Pointer to the counter container.
4115  * @param[in] id
4116  *   The counter devx ID.
4117  *
4118  * @return
4119  *   The counter pool pointer if exists, NULL otherwise,
4120  */
4121 static struct mlx5_flow_counter_pool *
4122 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4123 {
4124         uint32_t i;
4125
4126         /* Check last used pool. */
4127         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4128             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4129                 return cont->pools[cont->last_pool_idx];
4130         /* ID out of range means no suitable pool in the container. */
4131         if (id > cont->max_id || id < cont->min_id)
4132                 return NULL;
4133         /*
4134          * Find the pool from the end of the container, since mostly counter
4135          * ID is sequence increasing, and the last pool should be the needed
4136          * one.
4137          */
4138         i = rte_atomic16_read(&cont->n_valid);
4139         while (i--) {
4140                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4141
4142                 if (flow_dv_is_counter_in_pool(pool, id))
4143                         return pool;
4144         }
4145         return NULL;
4146 }
4147
4148 /**
4149  * Allocate a new memory for the counter values wrapped by all the needed
4150  * management.
4151  *
4152  * @param[in] dev
4153  *   Pointer to the Ethernet device structure.
4154  * @param[in] raws_n
4155  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4156  *
4157  * @return
4158  *   The new memory management pointer on success, otherwise NULL and rte_errno
4159  *   is set.
4160  */
4161 static struct mlx5_counter_stats_mem_mng *
4162 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4163 {
4164         struct mlx5_priv *priv = dev->data->dev_private;
4165         struct mlx5_dev_ctx_shared *sh = priv->sh;
4166         struct mlx5_devx_mkey_attr mkey_attr;
4167         struct mlx5_counter_stats_mem_mng *mem_mng;
4168         volatile struct flow_counter_stats *raw_data;
4169         int size = (sizeof(struct flow_counter_stats) *
4170                         MLX5_COUNTERS_PER_POOL +
4171                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4172                         sizeof(struct mlx5_counter_stats_mem_mng);
4173         size_t pgsize = rte_mem_page_size();
4174         if (pgsize == (size_t)-1) {
4175                 DRV_LOG(ERR, "Failed to get mem page size");
4176                 rte_errno = ENOMEM;
4177                 return NULL;
4178         }
4179         uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4180                                   SOCKET_ID_ANY);
4181         int i;
4182
4183         if (!mem) {
4184                 rte_errno = ENOMEM;
4185                 return NULL;
4186         }
4187         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4188         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4189         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4190                                                  IBV_ACCESS_LOCAL_WRITE);
4191         if (!mem_mng->umem) {
4192                 rte_errno = errno;
4193                 mlx5_free(mem);
4194                 return NULL;
4195         }
4196         mkey_attr.addr = (uintptr_t)mem;
4197         mkey_attr.size = size;
4198         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4199         mkey_attr.pd = sh->pdn;
4200         mkey_attr.log_entity_size = 0;
4201         mkey_attr.pg_access = 0;
4202         mkey_attr.klm_array = NULL;
4203         mkey_attr.klm_num = 0;
4204         if (priv->config.hca_attr.relaxed_ordering_write &&
4205                 priv->config.hca_attr.relaxed_ordering_read  &&
4206                 !haswell_broadwell_cpu)
4207                 mkey_attr.relaxed_ordering = 1;
4208         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4209         if (!mem_mng->dm) {
4210                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4211                 rte_errno = errno;
4212                 mlx5_free(mem);
4213                 return NULL;
4214         }
4215         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4216         raw_data = (volatile struct flow_counter_stats *)mem;
4217         for (i = 0; i < raws_n; ++i) {
4218                 mem_mng->raws[i].mem_mng = mem_mng;
4219                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4220         }
4221         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4222         return mem_mng;
4223 }
4224
4225 /**
4226  * Resize a counter container.
4227  *
4228  * @param[in] dev
4229  *   Pointer to the Ethernet device structure.
4230  * @param[in] batch
4231  *   Whether the pool is for counter that was allocated by batch command.
4232  * @param[in] age
4233  *   Whether the pool is for Aging counter.
4234  *
4235  * @return
4236  *   0 on success, otherwise negative errno value and rte_errno is set.
4237  */
4238 static int
4239 flow_dv_container_resize(struct rte_eth_dev *dev,
4240                                 uint32_t batch, uint32_t age)
4241 {
4242         struct mlx5_priv *priv = dev->data->dev_private;
4243         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4244                                                                age);
4245         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4246         void *old_pools = cont->pools;
4247         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4248         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4249         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4250
4251         if (!pools) {
4252                 rte_errno = ENOMEM;
4253                 return -ENOMEM;
4254         }
4255         if (old_pools)
4256                 memcpy(pools, old_pools, cont->n *
4257                                        sizeof(struct mlx5_flow_counter_pool *));
4258         /*
4259          * Fallback mode query the counter directly, no background query
4260          * resources are needed.
4261          */
4262         if (!priv->counter_fallback) {
4263                 int i;
4264
4265                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4266                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4267                 if (!mem_mng) {
4268                         mlx5_free(pools);
4269                         return -ENOMEM;
4270                 }
4271                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4272                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4273                                          mem_mng->raws +
4274                                          MLX5_CNT_CONTAINER_RESIZE +
4275                                          i, next);
4276         }
4277         rte_spinlock_lock(&cont->resize_sl);
4278         cont->n = resize;
4279         cont->mem_mng = mem_mng;
4280         cont->pools = pools;
4281         rte_spinlock_unlock(&cont->resize_sl);
4282         if (old_pools)
4283                 mlx5_free(old_pools);
4284         return 0;
4285 }
4286
4287 /**
4288  * Query a devx flow counter.
4289  *
4290  * @param[in] dev
4291  *   Pointer to the Ethernet device structure.
4292  * @param[in] cnt
4293  *   Index to the flow counter.
4294  * @param[out] pkts
4295  *   The statistics value of packets.
4296  * @param[out] bytes
4297  *   The statistics value of bytes.
4298  *
4299  * @return
4300  *   0 on success, otherwise a negative errno value and rte_errno is set.
4301  */
4302 static inline int
4303 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4304                      uint64_t *bytes)
4305 {
4306         struct mlx5_priv *priv = dev->data->dev_private;
4307         struct mlx5_flow_counter_pool *pool = NULL;
4308         struct mlx5_flow_counter *cnt;
4309         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4310         int offset;
4311
4312         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4313         MLX5_ASSERT(pool);
4314         if (counter < MLX5_CNT_BATCH_OFFSET) {
4315                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4316                 if (priv->counter_fallback)
4317                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4318                                         0, pkts, bytes, 0, NULL, NULL, 0);
4319         }
4320
4321         rte_spinlock_lock(&pool->sl);
4322         /*
4323          * The single counters allocation may allocate smaller ID than the
4324          * current allocated in parallel to the host reading.
4325          * In this case the new counter values must be reported as 0.
4326          */
4327         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4328                 *pkts = 0;
4329                 *bytes = 0;
4330         } else {
4331                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4332                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4333                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4334         }
4335         rte_spinlock_unlock(&pool->sl);
4336         return 0;
4337 }
4338
4339 /**
4340  * Create and initialize a new counter pool.
4341  *
4342  * @param[in] dev
4343  *   Pointer to the Ethernet device structure.
4344  * @param[out] dcs
4345  *   The devX counter handle.
4346  * @param[in] batch
4347  *   Whether the pool is for counter that was allocated by batch command.
4348  * @param[in] age
4349  *   Whether the pool is for counter that was allocated for aging.
4350  * @param[in/out] cont_cur
4351  *   Pointer to the container pointer, it will be update in pool resize.
4352  *
4353  * @return
4354  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4355  */
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4358                     uint32_t batch, uint32_t age)
4359 {
4360         struct mlx5_priv *priv = dev->data->dev_private;
4361         struct mlx5_flow_counter_pool *pool;
4362         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4363                                                                age);
4364         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4365         uint32_t size = sizeof(*pool);
4366
4367         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4368                 return NULL;
4369         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4370         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4371         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4372         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4373         if (!pool) {
4374                 rte_errno = ENOMEM;
4375                 return NULL;
4376         }
4377         pool->min_dcs = dcs;
4378         if (!priv->counter_fallback)
4379                 pool->raw = cont->mem_mng->raws + n_valid %
4380                                                       MLX5_CNT_CONTAINER_RESIZE;
4381         pool->raw_hw = NULL;
4382         pool->type = 0;
4383         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4384         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4385         pool->query_gen = 0;
4386         rte_spinlock_init(&pool->sl);
4387         TAILQ_INIT(&pool->counters[0]);
4388         TAILQ_INIT(&pool->counters[1]);
4389         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4390         pool->index = n_valid;
4391         cont->pools[n_valid] = pool;
4392         if (!batch) {
4393                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4394
4395                 if (base < cont->min_id)
4396                         cont->min_id = base;
4397                 if (base > cont->max_id)
4398                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4399                 cont->last_pool_idx = pool->index;
4400         }
4401         /* Pool initialization must be updated before host thread access. */
4402         rte_cio_wmb();
4403         rte_atomic16_add(&cont->n_valid, 1);
4404         return pool;
4405 }
4406
4407 /**
4408  * Prepare a new counter and/or a new counter pool.
4409  *
4410  * @param[in] dev
4411  *   Pointer to the Ethernet device structure.
4412  * @param[out] cnt_free
4413  *   Where to put the pointer of a new counter.
4414  * @param[in] batch
4415  *   Whether the pool is for counter that was allocated by batch command.
4416  * @param[in] age
4417  *   Whether the pool is for counter that was allocated for aging.
4418  *
4419  * @return
4420  *   The counter pool pointer and @p cnt_free is set on success,
4421  *   NULL otherwise and rte_errno is set.
4422  */
4423 static struct mlx5_flow_counter_pool *
4424 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4425                              struct mlx5_flow_counter **cnt_free,
4426                              uint32_t batch, uint32_t age)
4427 {
4428         struct mlx5_priv *priv = dev->data->dev_private;
4429         struct mlx5_pools_container *cont;
4430         struct mlx5_flow_counter_pool *pool;
4431         struct mlx5_counters tmp_tq;
4432         struct mlx5_devx_obj *dcs = NULL;
4433         struct mlx5_flow_counter *cnt;
4434         uint32_t add2other;
4435         uint32_t i;
4436
4437         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4438         if (!batch) {
4439 retry:
4440                 add2other = 0;
4441                 /* bulk_bitmap must be 0 for single counter allocation. */
4442                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4443                 if (!dcs)
4444                         return NULL;
4445                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4446                 /* Check if counter belongs to exist pool ID range. */
4447                 if (!pool) {
4448                         pool = flow_dv_find_pool_by_id
4449                                (MLX5_CNT_CONTAINER
4450                                (priv->sh, batch, (age ^ 0x1)), dcs->id);
4451                         /*
4452                          * Pool eixsts, counter will be added to the other
4453                          * container, need to reallocate it later.
4454                          */
4455                         if (pool) {
4456                                 add2other = 1;
4457                         } else {
4458                                 pool = flow_dv_pool_create(dev, dcs, batch,
4459                                                            age);
4460                                 if (!pool) {
4461                                         mlx5_devx_cmd_destroy(dcs);
4462                                         return NULL;
4463                                 }
4464                         }
4465                 }
4466                 if (dcs->id < pool->min_dcs->id)
4467                         rte_atomic64_set(&pool->a64_dcs,
4468                                          (int64_t)(uintptr_t)dcs);
4469                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4470                 cnt = MLX5_POOL_GET_CNT(pool, i);
4471                 cnt->pool = pool;
4472                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4473                 if (add2other) {
4474                         TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4475                                           cnt, next);
4476                         goto retry;
4477                 }
4478                 *cnt_free = cnt;
4479                 return pool;
4480         }
4481         /* bulk_bitmap is in 128 counters units. */
4482         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4483                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4484         if (!dcs) {
4485                 rte_errno = ENODATA;
4486                 return NULL;
4487         }
4488         pool = flow_dv_pool_create(dev, dcs, batch, age);
4489         if (!pool) {
4490                 mlx5_devx_cmd_destroy(dcs);
4491                 return NULL;
4492         }
4493         TAILQ_INIT(&tmp_tq);
4494         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4495                 cnt = MLX5_POOL_GET_CNT(pool, i);
4496                 cnt->pool = pool;
4497                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4498         }
4499         rte_spinlock_lock(&cont->csl);
4500         TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4501         rte_spinlock_unlock(&cont->csl);
4502         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4503         (*cnt_free)->pool = pool;
4504         return pool;
4505 }
4506
4507 /**
4508  * Search for existed shared counter.
4509  *
4510  * @param[in] dev
4511  *   Pointer to the Ethernet device structure.
4512  * @param[in] id
4513  *   The shared counter ID to search.
4514  * @param[out] ppool
4515  *   mlx5 flow counter pool in the container,
4516  *
4517  * @return
4518  *   NULL if not existed, otherwise pointer to the shared extend counter.
4519  */
4520 static struct mlx5_flow_counter_ext *
4521 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4522                               struct mlx5_flow_counter_pool **ppool)
4523 {
4524         struct mlx5_priv *priv = dev->data->dev_private;
4525         union mlx5_l3t_data data;
4526         uint32_t cnt_idx;
4527
4528         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4529                 return NULL;
4530         cnt_idx = data.dword;
4531         /*
4532          * Shared counters don't have age info. The counter extend is after
4533          * the counter datat structure.
4534          */
4535         return (struct mlx5_flow_counter_ext *)
4536                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4537 }
4538
4539 /**
4540  * Allocate a flow counter.
4541  *
4542  * @param[in] dev
4543  *   Pointer to the Ethernet device structure.
4544  * @param[in] shared
4545  *   Indicate if this counter is shared with other flows.
4546  * @param[in] id
4547  *   Counter identifier.
4548  * @param[in] group
4549  *   Counter flow group.
4550  * @param[in] age
4551  *   Whether the counter was allocated for aging.
4552  *
4553  * @return
4554  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4555  */
4556 static uint32_t
4557 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4558                       uint16_t group, uint32_t age)
4559 {
4560         struct mlx5_priv *priv = dev->data->dev_private;
4561         struct mlx5_flow_counter_pool *pool = NULL;
4562         struct mlx5_flow_counter *cnt_free = NULL;
4563         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4564         /*
4565          * Currently group 0 flow counter cannot be assigned to a flow if it is
4566          * not the first one in the batch counter allocation, so it is better
4567          * to allocate counters one by one for these flows in a separate
4568          * container.
4569          * A counter can be shared between different groups so need to take
4570          * shared counters from the single container.
4571          */
4572         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4573         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4574                                                                age);
4575         uint32_t cnt_idx;
4576
4577         if (!priv->config.devx) {
4578                 rte_errno = ENOTSUP;
4579                 return 0;
4580         }
4581         if (shared) {
4582                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4583                 if (cnt_ext) {
4584                         if (cnt_ext->ref_cnt + 1 == 0) {
4585                                 rte_errno = E2BIG;
4586                                 return 0;
4587                         }
4588                         cnt_ext->ref_cnt++;
4589                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4590                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4591                                   + 1;
4592                         return cnt_idx;
4593                 }
4594         }
4595         /* Get free counters from container. */
4596         rte_spinlock_lock(&cont->csl);
4597         cnt_free = TAILQ_FIRST(&cont->counters);
4598         if (cnt_free)
4599                 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4600         rte_spinlock_unlock(&cont->csl);
4601         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4602                                                        batch, age))
4603                 goto err;
4604         pool = cnt_free->pool;
4605         if (!batch)
4606                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4607         /* Create a DV counter action only in the first time usage. */
4608         if (!cnt_free->action) {
4609                 uint16_t offset;
4610                 struct mlx5_devx_obj *dcs;
4611                 int ret;
4612
4613                 if (batch) {
4614                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4615                         dcs = pool->min_dcs;
4616                 } else {
4617                         offset = 0;
4618                         dcs = cnt_ext->dcs;
4619                 }
4620                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4621                                                             &cnt_free->action);
4622                 if (ret) {
4623                         rte_errno = errno;
4624                         goto err;
4625                 }
4626         }
4627         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4628                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4629         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4630         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4631         /* Update the counter reset values. */
4632         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4633                                  &cnt_free->bytes))
4634                 goto err;
4635         if (cnt_ext) {
4636                 cnt_ext->shared = shared;
4637                 cnt_ext->ref_cnt = 1;
4638                 cnt_ext->id = id;
4639                 if (shared) {
4640                         union mlx5_l3t_data data;
4641
4642                         data.dword = cnt_idx;
4643                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4644                                 return 0;
4645                 }
4646         }
4647         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4648                 /* Start the asynchronous batch query by the host thread. */
4649                 mlx5_set_query_alarm(priv->sh);
4650         return cnt_idx;
4651 err:
4652         if (cnt_free) {
4653                 cnt_free->pool = pool;
4654                 rte_spinlock_lock(&cont->csl);
4655                 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4656                 rte_spinlock_unlock(&cont->csl);
4657         }
4658         return 0;
4659 }
4660
4661 /**
4662  * Get age param from counter index.
4663  *
4664  * @param[in] dev
4665  *   Pointer to the Ethernet device structure.
4666  * @param[in] counter
4667  *   Index to the counter handler.
4668  *
4669  * @return
4670  *   The aging parameter specified for the counter index.
4671  */
4672 static struct mlx5_age_param*
4673 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4674                                 uint32_t counter)
4675 {
4676         struct mlx5_flow_counter *cnt;
4677         struct mlx5_flow_counter_pool *pool = NULL;
4678
4679         flow_dv_counter_get_by_idx(dev, counter, &pool);
4680         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4681         cnt = MLX5_POOL_GET_CNT(pool, counter);
4682         return MLX5_CNT_TO_AGE(cnt);
4683 }
4684
4685 /**
4686  * Remove a flow counter from aged counter list.
4687  *
4688  * @param[in] dev
4689  *   Pointer to the Ethernet device structure.
4690  * @param[in] counter
4691  *   Index to the counter handler.
4692  * @param[in] cnt
4693  *   Pointer to the counter handler.
4694  */
4695 static void
4696 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4697                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4698 {
4699         struct mlx5_age_info *age_info;
4700         struct mlx5_age_param *age_param;
4701         struct mlx5_priv *priv = dev->data->dev_private;
4702
4703         age_info = GET_PORT_AGE_INFO(priv);
4704         age_param = flow_dv_counter_idx_get_age(dev, counter);
4705         if (rte_atomic16_cmpset((volatile uint16_t *)
4706                         &age_param->state,
4707                         AGE_CANDIDATE, AGE_FREE)
4708                         != AGE_CANDIDATE) {
4709                 /**
4710                  * We need the lock even it is age timeout,
4711                  * since counter may still in process.
4712                  */
4713                 rte_spinlock_lock(&age_info->aged_sl);
4714                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4715                 rte_spinlock_unlock(&age_info->aged_sl);
4716         }
4717         rte_atomic16_set(&age_param->state, AGE_FREE);
4718 }
4719 /**
4720  * Release a flow counter.
4721  *
4722  * @param[in] dev
4723  *   Pointer to the Ethernet device structure.
4724  * @param[in] counter
4725  *   Index to the counter handler.
4726  */
4727 static void
4728 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4729 {
4730         struct mlx5_priv *priv = dev->data->dev_private;
4731         struct mlx5_flow_counter_pool *pool = NULL;
4732         struct mlx5_flow_counter *cnt;
4733         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4734
4735         if (!counter)
4736                 return;
4737         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4738         MLX5_ASSERT(pool);
4739         if (counter < MLX5_CNT_BATCH_OFFSET) {
4740                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4741                 if (cnt_ext) {
4742                         if (--cnt_ext->ref_cnt)
4743                                 return;
4744                         if (cnt_ext->shared)
4745                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4746                                                      cnt_ext->id);
4747                 }
4748         }
4749         if (IS_AGE_POOL(pool))
4750                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4751         cnt->pool = pool;
4752         /*
4753          * Put the counter back to list to be updated in none fallback mode.
4754          * Currently, we are using two list alternately, while one is in query,
4755          * add the freed counter to the other list based on the pool query_gen
4756          * value. After query finishes, add counter the list to the global
4757          * container counter list. The list changes while query starts. In
4758          * this case, lock will not be needed as query callback and release
4759          * function both operate with the different list.
4760          *
4761          */
4762         if (!priv->counter_fallback)
4763                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4764         else
4765                 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4766                                   (priv->sh, 0, 0))->counters),
4767                                   cnt, next);
4768 }
4769
4770 /**
4771  * Verify the @p attributes will be correctly understood by the NIC and store
4772  * them in the @p flow if everything is correct.
4773  *
4774  * @param[in] dev
4775  *   Pointer to dev struct.
4776  * @param[in] attributes
4777  *   Pointer to flow attributes
4778  * @param[in] external
4779  *   This flow rule is created by request external to PMD.
4780  * @param[out] error
4781  *   Pointer to error structure.
4782  *
4783  * @return
4784  *   - 0 on success and non root table.
4785  *   - 1 on success and root table.
4786  *   - a negative errno value otherwise and rte_errno is set.
4787  */
4788 static int
4789 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4790                             const struct rte_flow_attr *attributes,
4791                             bool external __rte_unused,
4792                             struct rte_flow_error *error)
4793 {
4794         struct mlx5_priv *priv = dev->data->dev_private;
4795         uint32_t priority_max = priv->config.flow_prio - 1;
4796         int ret = 0;
4797
4798 #ifndef HAVE_MLX5DV_DR
4799         if (attributes->group)
4800                 return rte_flow_error_set(error, ENOTSUP,
4801                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4802                                           NULL,
4803                                           "groups are not supported");
4804 #else
4805         uint32_t table = 0;
4806
4807         ret = mlx5_flow_group_to_table(attributes, external,
4808                                        attributes->group, !!priv->fdb_def_rule,
4809                                        &table, error);
4810         if (ret)
4811                 return ret;
4812         if (!table)
4813                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4814 #endif
4815         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4816             attributes->priority >= priority_max)
4817                 return rte_flow_error_set(error, ENOTSUP,
4818                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4819                                           NULL,
4820                                           "priority out of range");
4821         if (attributes->transfer) {
4822                 if (!priv->config.dv_esw_en)
4823                         return rte_flow_error_set
4824                                 (error, ENOTSUP,
4825                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4826                                  "E-Switch dr is not supported");
4827                 if (!(priv->representor || priv->master))
4828                         return rte_flow_error_set
4829                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4830                                  NULL, "E-Switch configuration can only be"
4831                                  " done by a master or a representor device");
4832                 if (attributes->egress)
4833                         return rte_flow_error_set
4834                                 (error, ENOTSUP,
4835                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4836                                  "egress is not supported");
4837         }
4838         if (!(attributes->egress ^ attributes->ingress))
4839                 return rte_flow_error_set(error, ENOTSUP,
4840                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4841                                           "must specify exactly one of "
4842                                           "ingress or egress");
4843         return ret;
4844 }
4845
4846 /**
4847  * Internal validation function. For validating both actions and items.
4848  *
4849  * @param[in] dev
4850  *   Pointer to the rte_eth_dev structure.
4851  * @param[in] attr
4852  *   Pointer to the flow attributes.
4853  * @param[in] items
4854  *   Pointer to the list of items.
4855  * @param[in] actions
4856  *   Pointer to the list of actions.
4857  * @param[in] external
4858  *   This flow rule is created by request external to PMD.
4859  * @param[in] hairpin
4860  *   Number of hairpin TX actions, 0 means classic flow.
4861  * @param[out] error
4862  *   Pointer to the error structure.
4863  *
4864  * @return
4865  *   0 on success, a negative errno value otherwise and rte_errno is set.
4866  */
4867 static int
4868 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4869                  const struct rte_flow_item items[],
4870                  const struct rte_flow_action actions[],
4871                  bool external, int hairpin, struct rte_flow_error *error)
4872 {
4873         int ret;
4874         uint64_t action_flags = 0;
4875         uint64_t item_flags = 0;
4876         uint64_t last_item = 0;
4877         uint8_t next_protocol = 0xff;
4878         uint16_t ether_type = 0;
4879         int actions_n = 0;
4880         uint8_t item_ipv6_proto = 0;
4881         const struct rte_flow_item *gre_item = NULL;
4882         const struct rte_flow_action_raw_decap *decap;
4883         const struct rte_flow_action_raw_encap *encap;
4884         const struct rte_flow_action_rss *rss;
4885         const struct rte_flow_item_tcp nic_tcp_mask = {
4886                 .hdr = {
4887                         .tcp_flags = 0xFF,
4888                         .src_port = RTE_BE16(UINT16_MAX),
4889                         .dst_port = RTE_BE16(UINT16_MAX),
4890                 }
4891         };
4892         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4893                 .hdr = {
4894                         .src_addr = RTE_BE32(0xffffffff),
4895                         .dst_addr = RTE_BE32(0xffffffff),
4896                         .type_of_service = 0xff,
4897                         .next_proto_id = 0xff,
4898                         .time_to_live = 0xff,
4899                 },
4900         };
4901         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4902                 .hdr = {
4903                         .src_addr =
4904                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4905                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4906                         .dst_addr =
4907                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4908                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4909                         .vtc_flow = RTE_BE32(0xffffffff),
4910                         .proto = 0xff,
4911                         .hop_limits = 0xff,
4912                 },
4913         };
4914         const struct rte_flow_item_ecpri nic_ecpri_mask = {
4915                 .hdr = {
4916                         .common = {
4917                                 .u32 =
4918                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
4919                                         .type = 0xFF,
4920                                         }).u32),
4921                         },
4922                         .dummy[0] = 0xffffffff,
4923                 },
4924         };
4925         struct mlx5_priv *priv = dev->data->dev_private;
4926         struct mlx5_dev_config *dev_conf = &priv->config;
4927         uint16_t queue_index = 0xFFFF;
4928         const struct rte_flow_item_vlan *vlan_m = NULL;
4929         int16_t rw_act_num = 0;
4930         uint64_t is_root;
4931
4932         if (items == NULL)
4933                 return -1;
4934         ret = flow_dv_validate_attributes(dev, attr, external, error);
4935         if (ret < 0)
4936                 return ret;
4937         is_root = (uint64_t)ret;
4938         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4939                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4940                 int type = items->type;
4941
4942                 if (!mlx5_flow_os_item_supported(type))
4943                         return rte_flow_error_set(error, ENOTSUP,
4944                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4945                                                   NULL, "item not supported");
4946                 switch (type) {
4947                 case RTE_FLOW_ITEM_TYPE_VOID:
4948                         break;
4949                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4950                         ret = flow_dv_validate_item_port_id
4951                                         (dev, items, attr, item_flags, error);
4952                         if (ret < 0)
4953                                 return ret;
4954                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4955                         break;
4956                 case RTE_FLOW_ITEM_TYPE_ETH:
4957                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4958                                                           error);
4959                         if (ret < 0)
4960                                 return ret;
4961                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4962                                              MLX5_FLOW_LAYER_OUTER_L2;
4963                         if (items->mask != NULL && items->spec != NULL) {
4964                                 ether_type =
4965                                         ((const struct rte_flow_item_eth *)
4966                                          items->spec)->type;
4967                                 ether_type &=
4968                                         ((const struct rte_flow_item_eth *)
4969                                          items->mask)->type;
4970                                 ether_type = rte_be_to_cpu_16(ether_type);
4971                         } else {
4972                                 ether_type = 0;
4973                         }
4974                         break;
4975                 case RTE_FLOW_ITEM_TYPE_VLAN:
4976                         ret = flow_dv_validate_item_vlan(items, item_flags,
4977                                                          dev, error);
4978                         if (ret < 0)
4979                                 return ret;
4980                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4981                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4982                         if (items->mask != NULL && items->spec != NULL) {
4983                                 ether_type =
4984                                         ((const struct rte_flow_item_vlan *)
4985                                          items->spec)->inner_type;
4986                                 ether_type &=
4987                                         ((const struct rte_flow_item_vlan *)
4988                                          items->mask)->inner_type;
4989                                 ether_type = rte_be_to_cpu_16(ether_type);
4990                         } else {
4991                                 ether_type = 0;
4992                         }
4993                         /* Store outer VLAN mask for of_push_vlan action. */
4994                         if (!tunnel)
4995                                 vlan_m = items->mask;
4996                         break;
4997                 case RTE_FLOW_ITEM_TYPE_IPV4:
4998                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4999                                                   &item_flags, &tunnel);
5000                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5001                                                            last_item,
5002                                                            ether_type,
5003                                                            &nic_ipv4_mask,
5004                                                            error);
5005                         if (ret < 0)
5006                                 return ret;
5007                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5008                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5009                         if (items->mask != NULL &&
5010                             ((const struct rte_flow_item_ipv4 *)
5011                              items->mask)->hdr.next_proto_id) {
5012                                 next_protocol =
5013                                         ((const struct rte_flow_item_ipv4 *)
5014                                          (items->spec))->hdr.next_proto_id;
5015                                 next_protocol &=
5016                                         ((const struct rte_flow_item_ipv4 *)
5017                                          (items->mask))->hdr.next_proto_id;
5018                         } else {
5019                                 /* Reset for inner layer. */
5020                                 next_protocol = 0xff;
5021                         }
5022                         break;
5023                 case RTE_FLOW_ITEM_TYPE_IPV6:
5024                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5025                                                   &item_flags, &tunnel);
5026                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5027                                                            last_item,
5028                                                            ether_type,
5029                                                            &nic_ipv6_mask,
5030                                                            error);
5031                         if (ret < 0)
5032                                 return ret;
5033                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5034                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5035                         if (items->mask != NULL &&
5036                             ((const struct rte_flow_item_ipv6 *)
5037                              items->mask)->hdr.proto) {
5038                                 item_ipv6_proto =
5039                                         ((const struct rte_flow_item_ipv6 *)
5040                                          items->spec)->hdr.proto;
5041                                 next_protocol =
5042                                         ((const struct rte_flow_item_ipv6 *)
5043                                          items->spec)->hdr.proto;
5044                                 next_protocol &=
5045                                         ((const struct rte_flow_item_ipv6 *)
5046                                          items->mask)->hdr.proto;
5047                         } else {
5048                                 /* Reset for inner layer. */
5049                                 next_protocol = 0xff;
5050                         }
5051                         break;
5052                 case RTE_FLOW_ITEM_TYPE_TCP:
5053                         ret = mlx5_flow_validate_item_tcp
5054                                                 (items, item_flags,
5055                                                  next_protocol,
5056                                                  &nic_tcp_mask,
5057                                                  error);
5058                         if (ret < 0)
5059                                 return ret;
5060                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5061                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5062                         break;
5063                 case RTE_FLOW_ITEM_TYPE_UDP:
5064                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5065                                                           next_protocol,
5066                                                           error);
5067                         if (ret < 0)
5068                                 return ret;
5069                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5070                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5071                         break;
5072                 case RTE_FLOW_ITEM_TYPE_GRE:
5073                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5074                                                           next_protocol, error);
5075                         if (ret < 0)
5076                                 return ret;
5077                         gre_item = items;
5078                         last_item = MLX5_FLOW_LAYER_GRE;
5079                         break;
5080                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5081                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5082                                                             next_protocol,
5083                                                             error);
5084                         if (ret < 0)
5085                                 return ret;
5086                         last_item = MLX5_FLOW_LAYER_NVGRE;
5087                         break;
5088                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5089                         ret = mlx5_flow_validate_item_gre_key
5090                                 (items, item_flags, gre_item, error);
5091                         if (ret < 0)
5092                                 return ret;
5093                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5094                         break;
5095                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5096                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5097                                                             error);
5098                         if (ret < 0)
5099                                 return ret;
5100                         last_item = MLX5_FLOW_LAYER_VXLAN;
5101                         break;
5102                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5103                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5104                                                                 item_flags, dev,
5105                                                                 error);
5106                         if (ret < 0)
5107                                 return ret;
5108                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5109                         break;
5110                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5111                         ret = mlx5_flow_validate_item_geneve(items,
5112                                                              item_flags, dev,
5113                                                              error);
5114                         if (ret < 0)
5115                                 return ret;
5116                         last_item = MLX5_FLOW_LAYER_GENEVE;
5117                         break;
5118                 case RTE_FLOW_ITEM_TYPE_MPLS:
5119                         ret = mlx5_flow_validate_item_mpls(dev, items,
5120                                                            item_flags,
5121                                                            last_item, error);
5122                         if (ret < 0)
5123                                 return ret;
5124                         last_item = MLX5_FLOW_LAYER_MPLS;
5125                         break;
5126
5127                 case RTE_FLOW_ITEM_TYPE_MARK:
5128                         ret = flow_dv_validate_item_mark(dev, items, attr,
5129                                                          error);
5130                         if (ret < 0)
5131                                 return ret;
5132                         last_item = MLX5_FLOW_ITEM_MARK;
5133                         break;
5134                 case RTE_FLOW_ITEM_TYPE_META:
5135                         ret = flow_dv_validate_item_meta(dev, items, attr,
5136                                                          error);
5137                         if (ret < 0)
5138                                 return ret;
5139                         last_item = MLX5_FLOW_ITEM_METADATA;
5140                         break;
5141                 case RTE_FLOW_ITEM_TYPE_ICMP:
5142                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5143                                                            next_protocol,
5144                                                            error);
5145                         if (ret < 0)
5146                                 return ret;
5147                         last_item = MLX5_FLOW_LAYER_ICMP;
5148                         break;
5149                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5150                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5151                                                             next_protocol,
5152                                                             error);
5153                         if (ret < 0)
5154                                 return ret;
5155                         item_ipv6_proto = IPPROTO_ICMPV6;
5156                         last_item = MLX5_FLOW_LAYER_ICMP6;
5157                         break;
5158                 case RTE_FLOW_ITEM_TYPE_TAG:
5159                         ret = flow_dv_validate_item_tag(dev, items,
5160                                                         attr, error);
5161                         if (ret < 0)
5162                                 return ret;
5163                         last_item = MLX5_FLOW_ITEM_TAG;
5164                         break;
5165                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5166                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5167                         break;
5168                 case RTE_FLOW_ITEM_TYPE_GTP:
5169                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5170                                                         error);
5171                         if (ret < 0)
5172                                 return ret;
5173                         last_item = MLX5_FLOW_LAYER_GTP;
5174                         break;
5175                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5176                         /* Capacity will be checked in the translate stage. */
5177                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5178                                                             last_item,
5179                                                             ether_type,
5180                                                             &nic_ecpri_mask,
5181                                                             error);
5182                         if (ret < 0)
5183                                 return ret;
5184                         last_item = MLX5_FLOW_LAYER_ECPRI;
5185                         break;
5186                 default:
5187                         return rte_flow_error_set(error, ENOTSUP,
5188                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5189                                                   NULL, "item not supported");
5190                 }
5191                 item_flags |= last_item;
5192         }
5193         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5194                 int type = actions->type;
5195
5196                 if (!mlx5_flow_os_action_supported(type))
5197                         return rte_flow_error_set(error, ENOTSUP,
5198                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5199                                                   actions,
5200                                                   "action not supported");
5201                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5202                         return rte_flow_error_set(error, ENOTSUP,
5203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5204                                                   actions, "too many actions");
5205                 switch (type) {
5206                 case RTE_FLOW_ACTION_TYPE_VOID:
5207                         break;
5208                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5209                         ret = flow_dv_validate_action_port_id(dev,
5210                                                               action_flags,
5211                                                               actions,
5212                                                               attr,
5213                                                               error);
5214                         if (ret)
5215                                 return ret;
5216                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5217                         ++actions_n;
5218                         break;
5219                 case RTE_FLOW_ACTION_TYPE_FLAG:
5220                         ret = flow_dv_validate_action_flag(dev, action_flags,
5221                                                            attr, error);
5222                         if (ret < 0)
5223                                 return ret;
5224                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5225                                 /* Count all modify-header actions as one. */
5226                                 if (!(action_flags &
5227                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5228                                         ++actions_n;
5229                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5230                                                 MLX5_FLOW_ACTION_MARK_EXT;
5231                         } else {
5232                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5233                                 ++actions_n;
5234                         }
5235                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5236                         break;
5237                 case RTE_FLOW_ACTION_TYPE_MARK:
5238                         ret = flow_dv_validate_action_mark(dev, actions,
5239                                                            action_flags,
5240                                                            attr, error);
5241                         if (ret < 0)
5242                                 return ret;
5243                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5244                                 /* Count all modify-header actions as one. */
5245                                 if (!(action_flags &
5246                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5247                                         ++actions_n;
5248                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5249                                                 MLX5_FLOW_ACTION_MARK_EXT;
5250                         } else {
5251                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5252                                 ++actions_n;
5253                         }
5254                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5255                         break;
5256                 case RTE_FLOW_ACTION_TYPE_SET_META:
5257                         ret = flow_dv_validate_action_set_meta(dev, actions,
5258                                                                action_flags,
5259                                                                attr, error);
5260                         if (ret < 0)
5261                                 return ret;
5262                         /* Count all modify-header actions as one action. */
5263                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5264                                 ++actions_n;
5265                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5266                         rw_act_num += MLX5_ACT_NUM_SET_META;
5267                         break;
5268                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5269                         ret = flow_dv_validate_action_set_tag(dev, actions,
5270                                                               action_flags,
5271                                                               attr, error);
5272                         if (ret < 0)
5273                                 return ret;
5274                         /* Count all modify-header actions as one action. */
5275                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5276                                 ++actions_n;
5277                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5278                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5279                         break;
5280                 case RTE_FLOW_ACTION_TYPE_DROP:
5281                         ret = mlx5_flow_validate_action_drop(action_flags,
5282                                                              attr, error);
5283                         if (ret < 0)
5284                                 return ret;
5285                         action_flags |= MLX5_FLOW_ACTION_DROP;
5286                         ++actions_n;
5287                         break;
5288                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5289                         ret = mlx5_flow_validate_action_queue(actions,
5290                                                               action_flags, dev,
5291                                                               attr, error);
5292                         if (ret < 0)
5293                                 return ret;
5294                         queue_index = ((const struct rte_flow_action_queue *)
5295                                                         (actions->conf))->index;
5296                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5297                         ++actions_n;
5298                         break;
5299                 case RTE_FLOW_ACTION_TYPE_RSS:
5300                         rss = actions->conf;
5301                         ret = mlx5_flow_validate_action_rss(actions,
5302                                                             action_flags, dev,
5303                                                             attr, item_flags,
5304                                                             error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         if (rss != NULL && rss->queue_num)
5308                                 queue_index = rss->queue[0];
5309                         action_flags |= MLX5_FLOW_ACTION_RSS;
5310                         ++actions_n;
5311                         break;
5312                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5313                         ret =
5314                         mlx5_flow_validate_action_default_miss(action_flags,
5315                                         attr, error);
5316                         if (ret < 0)
5317                                 return ret;
5318                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5319                         ++actions_n;
5320                         break;
5321                 case RTE_FLOW_ACTION_TYPE_COUNT:
5322                         ret = flow_dv_validate_action_count(dev, error);
5323                         if (ret < 0)
5324                                 return ret;
5325                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5326                         ++actions_n;
5327                         break;
5328                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5329                         if (flow_dv_validate_action_pop_vlan(dev,
5330                                                              action_flags,
5331                                                              actions,
5332                                                              item_flags, attr,
5333                                                              error))
5334                                 return -rte_errno;
5335                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5336                         ++actions_n;
5337                         break;
5338                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5339                         ret = flow_dv_validate_action_push_vlan(dev,
5340                                                                 action_flags,
5341                                                                 vlan_m,
5342                                                                 actions, attr,
5343                                                                 error);
5344                         if (ret < 0)
5345                                 return ret;
5346                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5347                         ++actions_n;
5348                         break;
5349                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5350                         ret = flow_dv_validate_action_set_vlan_pcp
5351                                                 (action_flags, actions, error);
5352                         if (ret < 0)
5353                                 return ret;
5354                         /* Count PCP with push_vlan command. */
5355                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5356                         break;
5357                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5358                         ret = flow_dv_validate_action_set_vlan_vid
5359                                                 (item_flags, action_flags,
5360                                                  actions, error);
5361                         if (ret < 0)
5362                                 return ret;
5363                         /* Count VID with push_vlan command. */
5364                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5365                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5366                         break;
5367                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5368                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5369                         ret = flow_dv_validate_action_l2_encap(dev,
5370                                                                action_flags,
5371                                                                actions, attr,
5372                                                                error);
5373                         if (ret < 0)
5374                                 return ret;
5375                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5376                         ++actions_n;
5377                         break;
5378                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5379                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5380                         ret = flow_dv_validate_action_decap(dev, action_flags,
5381                                                             attr, error);
5382                         if (ret < 0)
5383                                 return ret;
5384                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5385                         ++actions_n;
5386                         break;
5387                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5388                         ret = flow_dv_validate_action_raw_encap_decap
5389                                 (dev, NULL, actions->conf, attr, &action_flags,
5390                                  &actions_n, error);
5391                         if (ret < 0)
5392                                 return ret;
5393                         break;
5394                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5395                         decap = actions->conf;
5396                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5397                                 ;
5398                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5399                                 encap = NULL;
5400                                 actions--;
5401                         } else {
5402                                 encap = actions->conf;
5403                         }
5404                         ret = flow_dv_validate_action_raw_encap_decap
5405                                            (dev,
5406                                             decap ? decap : &empty_decap, encap,
5407                                             attr, &action_flags, &actions_n,
5408                                             error);
5409                         if (ret < 0)
5410                                 return ret;
5411                         break;
5412                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5413                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5414                         ret = flow_dv_validate_action_modify_mac(action_flags,
5415                                                                  actions,
5416                                                                  item_flags,
5417                                                                  error);
5418                         if (ret < 0)
5419                                 return ret;
5420                         /* Count all modify-header actions as one action. */
5421                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5422                                 ++actions_n;
5423                         action_flags |= actions->type ==
5424                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5425                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5426                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5427                         /*
5428                          * Even if the source and destination MAC addresses have
5429                          * overlap in the header with 4B alignment, the convert
5430                          * function will handle them separately and 4 SW actions
5431                          * will be created. And 2 actions will be added each
5432                          * time no matter how many bytes of address will be set.
5433                          */
5434                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5435                         break;
5436                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5437                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5438                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5439                                                                   actions,
5440                                                                   item_flags,
5441                                                                   error);
5442                         if (ret < 0)
5443                                 return ret;
5444                         /* Count all modify-header actions as one action. */
5445                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5446                                 ++actions_n;
5447                         action_flags |= actions->type ==
5448                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5449                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5450                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5451                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5452                         break;
5453                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5454                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5455                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5456                                                                   actions,
5457                                                                   item_flags,
5458                                                                   error);
5459                         if (ret < 0)
5460                                 return ret;
5461                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5462                                 return rte_flow_error_set(error, ENOTSUP,
5463                                         RTE_FLOW_ERROR_TYPE_ACTION,
5464                                         actions,
5465                                         "Can't change header "
5466                                         "with ICMPv6 proto");
5467                         /* Count all modify-header actions as one action. */
5468                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5469                                 ++actions_n;
5470                         action_flags |= actions->type ==
5471                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5472                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5473                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5474                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5475                         break;
5476                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5477                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5478                         ret = flow_dv_validate_action_modify_tp(action_flags,
5479                                                                 actions,
5480                                                                 item_flags,
5481                                                                 error);
5482                         if (ret < 0)
5483                                 return ret;
5484                         /* Count all modify-header actions as one action. */
5485                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5486                                 ++actions_n;
5487                         action_flags |= actions->type ==
5488                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5489                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5490                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5491                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5492                         break;
5493                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5494                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5495                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5496                                                                  actions,
5497                                                                  item_flags,
5498                                                                  error);
5499                         if (ret < 0)
5500                                 return ret;
5501                         /* Count all modify-header actions as one action. */
5502                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5503                                 ++actions_n;
5504                         action_flags |= actions->type ==
5505                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5506                                                 MLX5_FLOW_ACTION_SET_TTL :
5507                                                 MLX5_FLOW_ACTION_DEC_TTL;
5508                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5509                         break;
5510                 case RTE_FLOW_ACTION_TYPE_JUMP:
5511                         ret = flow_dv_validate_action_jump(actions,
5512                                                            action_flags,
5513                                                            attr, external,
5514                                                            error);
5515                         if (ret)
5516                                 return ret;
5517                         ++actions_n;
5518                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5519                         break;
5520                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5521                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5522                         ret = flow_dv_validate_action_modify_tcp_seq
5523                                                                 (action_flags,
5524                                                                  actions,
5525                                                                  item_flags,
5526                                                                  error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         /* Count all modify-header actions as one action. */
5530                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5531                                 ++actions_n;
5532                         action_flags |= actions->type ==
5533                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5534                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5535                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5536                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5537                         break;
5538                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5539                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5540                         ret = flow_dv_validate_action_modify_tcp_ack
5541                                                                 (action_flags,
5542                                                                  actions,
5543                                                                  item_flags,
5544                                                                  error);
5545                         if (ret < 0)
5546                                 return ret;
5547                         /* Count all modify-header actions as one action. */
5548                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5549                                 ++actions_n;
5550                         action_flags |= actions->type ==
5551                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5552                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5553                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5554                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5555                         break;
5556                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5557                         break;
5558                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5559                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5560                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5561                         break;
5562                 case RTE_FLOW_ACTION_TYPE_METER:
5563                         ret = mlx5_flow_validate_action_meter(dev,
5564                                                               action_flags,
5565                                                               actions, attr,
5566                                                               error);
5567                         if (ret < 0)
5568                                 return ret;
5569                         action_flags |= MLX5_FLOW_ACTION_METER;
5570                         ++actions_n;
5571                         /* Meter action will add one more TAG action. */
5572                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5573                         break;
5574                 case RTE_FLOW_ACTION_TYPE_AGE:
5575                         ret = flow_dv_validate_action_age(action_flags,
5576                                                           actions, dev,
5577                                                           error);
5578                         if (ret < 0)
5579                                 return ret;
5580                         action_flags |= MLX5_FLOW_ACTION_AGE;
5581                         ++actions_n;
5582                         break;
5583                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5584                         ret = flow_dv_validate_action_modify_ipv4_dscp
5585                                                          (action_flags,
5586                                                           actions,
5587                                                           item_flags,
5588                                                           error);
5589                         if (ret < 0)
5590                                 return ret;
5591                         /* Count all modify-header actions as one action. */
5592                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5593                                 ++actions_n;
5594                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5595                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5596                         break;
5597                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5598                         ret = flow_dv_validate_action_modify_ipv6_dscp
5599                                                                 (action_flags,
5600                                                                  actions,
5601                                                                  item_flags,
5602                                                                  error);
5603                         if (ret < 0)
5604                                 return ret;
5605                         /* Count all modify-header actions as one action. */
5606                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5607                                 ++actions_n;
5608                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5609                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5610                         break;
5611                 default:
5612                         return rte_flow_error_set(error, ENOTSUP,
5613                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5614                                                   actions,
5615                                                   "action not supported");
5616                 }
5617         }
5618         /*
5619          * Validate the drop action mutual exclusion with other actions.
5620          * Drop action is mutually-exclusive with any other action, except for
5621          * Count action.
5622          */
5623         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5624             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5625                 return rte_flow_error_set(error, EINVAL,
5626                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5627                                           "Drop action is mutually-exclusive "
5628                                           "with any other action, except for "
5629                                           "Count action");
5630         /* Eswitch has few restrictions on using items and actions */
5631         if (attr->transfer) {
5632                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5633                     action_flags & MLX5_FLOW_ACTION_FLAG)
5634                         return rte_flow_error_set(error, ENOTSUP,
5635                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5636                                                   NULL,
5637                                                   "unsupported action FLAG");
5638                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5639                     action_flags & MLX5_FLOW_ACTION_MARK)
5640                         return rte_flow_error_set(error, ENOTSUP,
5641                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5642                                                   NULL,
5643                                                   "unsupported action MARK");
5644                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5645                         return rte_flow_error_set(error, ENOTSUP,
5646                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5647                                                   NULL,
5648                                                   "unsupported action QUEUE");
5649                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5650                         return rte_flow_error_set(error, ENOTSUP,
5651                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5652                                                   NULL,
5653                                                   "unsupported action RSS");
5654                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5655                         return rte_flow_error_set(error, EINVAL,
5656                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5657                                                   actions,
5658                                                   "no fate action is found");
5659         } else {
5660                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5661                         return rte_flow_error_set(error, EINVAL,
5662                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5663                                                   actions,
5664                                                   "no fate action is found");
5665         }
5666         /* Continue validation for Xcap and VLAN actions.*/
5667         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
5668                              MLX5_FLOW_VLAN_ACTIONS)) &&
5669             (queue_index == 0xFFFF ||
5670              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5671                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5672                     MLX5_FLOW_XCAP_ACTIONS)
5673                         return rte_flow_error_set(error, ENOTSUP,
5674                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5675                                                   NULL, "encap and decap "
5676                                                   "combination aren't supported");
5677                 if (!attr->transfer && attr->ingress) {
5678                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
5679                                 return rte_flow_error_set
5680                                                 (error, ENOTSUP,
5681                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5682                                                  NULL, "encap is not supported"
5683                                                  " for ingress traffic");
5684                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5685                                 return rte_flow_error_set
5686                                                 (error, ENOTSUP,
5687                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5688                                                  NULL, "push VLAN action not "
5689                                                  "supported for ingress");
5690                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
5691                                         MLX5_FLOW_VLAN_ACTIONS)
5692                                 return rte_flow_error_set
5693                                                 (error, ENOTSUP,
5694                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5695                                                  NULL, "no support for "
5696                                                  "multiple VLAN actions");
5697                 }
5698         }
5699         /* Hairpin flow will add one more TAG action. */
5700         if (hairpin > 0)
5701                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5702         /* extra metadata enabled: one more TAG action will be add. */
5703         if (dev_conf->dv_flow_en &&
5704             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5705             mlx5_flow_ext_mreg_supported(dev))
5706                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5707         if ((uint32_t)rw_act_num >
5708                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5709                 return rte_flow_error_set(error, ENOTSUP,
5710                                           RTE_FLOW_ERROR_TYPE_ACTION,
5711                                           NULL, "too many header modify"
5712                                           " actions to support");
5713         }
5714         return 0;
5715 }
5716
5717 /**
5718  * Internal preparation function. Allocates the DV flow size,
5719  * this size is constant.
5720  *
5721  * @param[in] dev
5722  *   Pointer to the rte_eth_dev structure.
5723  * @param[in] attr
5724  *   Pointer to the flow attributes.
5725  * @param[in] items
5726  *   Pointer to the list of items.
5727  * @param[in] actions
5728  *   Pointer to the list of actions.
5729  * @param[out] error
5730  *   Pointer to the error structure.
5731  *
5732  * @return
5733  *   Pointer to mlx5_flow object on success,
5734  *   otherwise NULL and rte_errno is set.
5735  */
5736 static struct mlx5_flow *
5737 flow_dv_prepare(struct rte_eth_dev *dev,
5738                 const struct rte_flow_attr *attr __rte_unused,
5739                 const struct rte_flow_item items[] __rte_unused,
5740                 const struct rte_flow_action actions[] __rte_unused,
5741                 struct rte_flow_error *error)
5742 {
5743         uint32_t handle_idx = 0;
5744         struct mlx5_flow *dev_flow;
5745         struct mlx5_flow_handle *dev_handle;
5746         struct mlx5_priv *priv = dev->data->dev_private;
5747
5748         /* In case of corrupting the memory. */
5749         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5750                 rte_flow_error_set(error, ENOSPC,
5751                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5752                                    "not free temporary device flow");
5753                 return NULL;
5754         }
5755         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5756                                    &handle_idx);
5757         if (!dev_handle) {
5758                 rte_flow_error_set(error, ENOMEM,
5759                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5760                                    "not enough memory to create flow handle");
5761                 return NULL;
5762         }
5763         /* No multi-thread supporting. */
5764         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5765         dev_flow->handle = dev_handle;
5766         dev_flow->handle_idx = handle_idx;
5767         /*
5768          * In some old rdma-core releases, before continuing, a check of the
5769          * length of matching parameter will be done at first. It needs to use
5770          * the length without misc4 param. If the flow has misc4 support, then
5771          * the length needs to be adjusted accordingly. Each param member is
5772          * aligned with a 64B boundary naturally.
5773          */
5774         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5775                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5776         /*
5777          * The matching value needs to be cleared to 0 before using. In the
5778          * past, it will be automatically cleared when using rte_*alloc
5779          * API. The time consumption will be almost the same as before.
5780          */
5781         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5782         dev_flow->ingress = attr->ingress;
5783         dev_flow->dv.transfer = attr->transfer;
5784         return dev_flow;
5785 }
5786
5787 #ifdef RTE_LIBRTE_MLX5_DEBUG
5788 /**
5789  * Sanity check for match mask and value. Similar to check_valid_spec() in
5790  * kernel driver. If unmasked bit is present in value, it returns failure.
5791  *
5792  * @param match_mask
5793  *   pointer to match mask buffer.
5794  * @param match_value
5795  *   pointer to match value buffer.
5796  *
5797  * @return
5798  *   0 if valid, -EINVAL otherwise.
5799  */
5800 static int
5801 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5802 {
5803         uint8_t *m = match_mask;
5804         uint8_t *v = match_value;
5805         unsigned int i;
5806
5807         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5808                 if (v[i] & ~m[i]) {
5809                         DRV_LOG(ERR,
5810                                 "match_value differs from match_criteria"
5811                                 " %p[%u] != %p[%u]",
5812                                 match_value, i, match_mask, i);
5813                         return -EINVAL;
5814                 }
5815         }
5816         return 0;
5817 }
5818 #endif
5819
5820 /**
5821  * Add match of ip_version.
5822  *
5823  * @param[in] group
5824  *   Flow group.
5825  * @param[in] headers_v
5826  *   Values header pointer.
5827  * @param[in] headers_m
5828  *   Masks header pointer.
5829  * @param[in] ip_version
5830  *   The IP version to set.
5831  */
5832 static inline void
5833 flow_dv_set_match_ip_version(uint32_t group,
5834                              void *headers_v,
5835                              void *headers_m,
5836                              uint8_t ip_version)
5837 {
5838         if (group == 0)
5839                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5840         else
5841                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5842                          ip_version);
5843         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5845         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5846 }
5847
5848 /**
5849  * Add Ethernet item to matcher and to the value.
5850  *
5851  * @param[in, out] matcher
5852  *   Flow matcher.
5853  * @param[in, out] key
5854  *   Flow matcher value.
5855  * @param[in] item
5856  *   Flow pattern to translate.
5857  * @param[in] inner
5858  *   Item is inner pattern.
5859  */
5860 static void
5861 flow_dv_translate_item_eth(void *matcher, void *key,
5862                            const struct rte_flow_item *item, int inner,
5863                            uint32_t group)
5864 {
5865         const struct rte_flow_item_eth *eth_m = item->mask;
5866         const struct rte_flow_item_eth *eth_v = item->spec;
5867         const struct rte_flow_item_eth nic_mask = {
5868                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5869                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5870                 .type = RTE_BE16(0xffff),
5871         };
5872         void *headers_m;
5873         void *headers_v;
5874         char *l24_v;
5875         unsigned int i;
5876
5877         if (!eth_v)
5878                 return;
5879         if (!eth_m)
5880                 eth_m = &nic_mask;
5881         if (inner) {
5882                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5883                                          inner_headers);
5884                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5885         } else {
5886                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5887                                          outer_headers);
5888                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5889         }
5890         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5891                &eth_m->dst, sizeof(eth_m->dst));
5892         /* The value must be in the range of the mask. */
5893         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5894         for (i = 0; i < sizeof(eth_m->dst); ++i)
5895                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5896         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5897                &eth_m->src, sizeof(eth_m->src));
5898         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5899         /* The value must be in the range of the mask. */
5900         for (i = 0; i < sizeof(eth_m->dst); ++i)
5901                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5902         if (eth_v->type) {
5903                 /* When ethertype is present set mask for tagged VLAN. */
5904                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5905                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5906                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5907                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5908                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5909                                  1);
5910                         /* Return here to avoid setting match on ethertype. */
5911                         return;
5912                 }
5913         }
5914         /*
5915          * HW supports match on one Ethertype, the Ethertype following the last
5916          * VLAN tag of the packet (see PRM).
5917          * Set match on ethertype only if ETH header is not followed by VLAN.
5918          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5919          * ethertype, and use ip_version field instead.
5920          * eCPRI over Ether layer will use type value 0xAEFE.
5921          */
5922         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5923             eth_m->type == 0xFFFF) {
5924                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5925         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5926                    eth_m->type == 0xFFFF) {
5927                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5928         } else {
5929                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5930                          rte_be_to_cpu_16(eth_m->type));
5931                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5932                                      ethertype);
5933                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5934         }
5935 }
5936
5937 /**
5938  * Add VLAN item to matcher and to the value.
5939  *
5940  * @param[in, out] dev_flow
5941  *   Flow descriptor.
5942  * @param[in, out] matcher
5943  *   Flow matcher.
5944  * @param[in, out] key
5945  *   Flow matcher value.
5946  * @param[in] item
5947  *   Flow pattern to translate.
5948  * @param[in] inner
5949  *   Item is inner pattern.
5950  */
5951 static void
5952 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5953                             void *matcher, void *key,
5954                             const struct rte_flow_item *item,
5955                             int inner, uint32_t group)
5956 {
5957         const struct rte_flow_item_vlan *vlan_m = item->mask;
5958         const struct rte_flow_item_vlan *vlan_v = item->spec;
5959         void *headers_m;
5960         void *headers_v;
5961         uint16_t tci_m;
5962         uint16_t tci_v;
5963
5964         if (inner) {
5965                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5966                                          inner_headers);
5967                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5968         } else {
5969                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5970                                          outer_headers);
5971                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5972                 /*
5973                  * This is workaround, masks are not supported,
5974                  * and pre-validated.
5975                  */
5976                 if (vlan_v)
5977                         dev_flow->handle->vf_vlan.tag =
5978                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5979         }
5980         /*
5981          * When VLAN item exists in flow, mark packet as tagged,
5982          * even if TCI is not specified.
5983          */
5984         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5985         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5986         if (!vlan_v)
5987                 return;
5988         if (!vlan_m)
5989                 vlan_m = &rte_flow_item_vlan_mask;
5990         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5991         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5992         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5993         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5994         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5995         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5996         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5997         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5998         /*
5999          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6000          * ethertype, and use ip_version field instead.
6001          */
6002         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6003             vlan_m->inner_type == 0xFFFF) {
6004                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6005         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6006                    vlan_m->inner_type == 0xFFFF) {
6007                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6008         } else {
6009                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6010                          rte_be_to_cpu_16(vlan_m->inner_type));
6011                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6012                          rte_be_to_cpu_16(vlan_m->inner_type &
6013                                           vlan_v->inner_type));
6014         }
6015 }
6016
6017 /**
6018  * Add IPV4 item to matcher and to the value.
6019  *
6020  * @param[in, out] matcher
6021  *   Flow matcher.
6022  * @param[in, out] key
6023  *   Flow matcher value.
6024  * @param[in] item
6025  *   Flow pattern to translate.
6026  * @param[in] item_flags
6027  *   Bit-fields that holds the items detected until now.
6028  * @param[in] inner
6029  *   Item is inner pattern.
6030  * @param[in] group
6031  *   The group to insert the rule.
6032  */
6033 static void
6034 flow_dv_translate_item_ipv4(void *matcher, void *key,
6035                             const struct rte_flow_item *item,
6036                             const uint64_t item_flags,
6037                             int inner, uint32_t group)
6038 {
6039         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6040         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6041         const struct rte_flow_item_ipv4 nic_mask = {
6042                 .hdr = {
6043                         .src_addr = RTE_BE32(0xffffffff),
6044                         .dst_addr = RTE_BE32(0xffffffff),
6045                         .type_of_service = 0xff,
6046                         .next_proto_id = 0xff,
6047                         .time_to_live = 0xff,
6048                 },
6049         };
6050         void *headers_m;
6051         void *headers_v;
6052         char *l24_m;
6053         char *l24_v;
6054         uint8_t tos;
6055
6056         if (inner) {
6057                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6058                                          inner_headers);
6059                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6060         } else {
6061                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6062                                          outer_headers);
6063                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6064         }
6065         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6066         /*
6067          * On outer header (which must contains L2), or inner header with L2,
6068          * set cvlan_tag mask bit to mark this packet as untagged.
6069          * This should be done even if item->spec is empty.
6070          */
6071         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6072                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6073         if (!ipv4_v)
6074                 return;
6075         if (!ipv4_m)
6076                 ipv4_m = &nic_mask;
6077         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6078                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6079         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6080                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6081         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6082         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6083         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6084                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6085         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6086                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6087         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6088         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6089         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6090         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6091                  ipv4_m->hdr.type_of_service);
6092         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6093         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6094                  ipv4_m->hdr.type_of_service >> 2);
6095         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6096         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6097                  ipv4_m->hdr.next_proto_id);
6098         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6099                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6100         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6101                  ipv4_m->hdr.time_to_live);
6102         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6103                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6104 }
6105
6106 /**
6107  * Add IPV6 item to matcher and to the value.
6108  *
6109  * @param[in, out] matcher
6110  *   Flow matcher.
6111  * @param[in, out] key
6112  *   Flow matcher value.
6113  * @param[in] item
6114  *   Flow pattern to translate.
6115  * @param[in] item_flags
6116  *   Bit-fields that holds the items detected until now.
6117  * @param[in] inner
6118  *   Item is inner pattern.
6119  * @param[in] group
6120  *   The group to insert the rule.
6121  */
6122 static void
6123 flow_dv_translate_item_ipv6(void *matcher, void *key,
6124                             const struct rte_flow_item *item,
6125                             const uint64_t item_flags,
6126                             int inner, uint32_t group)
6127 {
6128         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6129         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6130         const struct rte_flow_item_ipv6 nic_mask = {
6131                 .hdr = {
6132                         .src_addr =
6133                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6134                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6135                         .dst_addr =
6136                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6137                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6138                         .vtc_flow = RTE_BE32(0xffffffff),
6139                         .proto = 0xff,
6140                         .hop_limits = 0xff,
6141                 },
6142         };
6143         void *headers_m;
6144         void *headers_v;
6145         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6146         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6147         char *l24_m;
6148         char *l24_v;
6149         uint32_t vtc_m;
6150         uint32_t vtc_v;
6151         int i;
6152         int size;
6153
6154         if (inner) {
6155                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6156                                          inner_headers);
6157                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6158         } else {
6159                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6160                                          outer_headers);
6161                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6162         }
6163         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6164         /*
6165          * On outer header (which must contains L2), or inner header with L2,
6166          * set cvlan_tag mask bit to mark this packet as untagged.
6167          * This should be done even if item->spec is empty.
6168          */
6169         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6170                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6171         if (!ipv6_v)
6172                 return;
6173         if (!ipv6_m)
6174                 ipv6_m = &nic_mask;
6175         size = sizeof(ipv6_m->hdr.dst_addr);
6176         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6177                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6178         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6179                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6180         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6181         for (i = 0; i < size; ++i)
6182                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6183         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6184                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6185         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6186                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6187         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6188         for (i = 0; i < size; ++i)
6189                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6190         /* TOS. */
6191         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6192         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6193         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6194         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6195         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6196         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6197         /* Label. */
6198         if (inner) {
6199                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6200                          vtc_m);
6201                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6202                          vtc_v);
6203         } else {
6204                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6205                          vtc_m);
6206                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6207                          vtc_v);
6208         }
6209         /* Protocol. */
6210         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6211                  ipv6_m->hdr.proto);
6212         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6213                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6214         /* Hop limit. */
6215         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6216                  ipv6_m->hdr.hop_limits);
6217         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6218                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6219 }
6220
6221 /**
6222  * Add TCP item to matcher and to the value.
6223  *
6224  * @param[in, out] matcher
6225  *   Flow matcher.
6226  * @param[in, out] key
6227  *   Flow matcher value.
6228  * @param[in] item
6229  *   Flow pattern to translate.
6230  * @param[in] inner
6231  *   Item is inner pattern.
6232  */
6233 static void
6234 flow_dv_translate_item_tcp(void *matcher, void *key,
6235                            const struct rte_flow_item *item,
6236                            int inner)
6237 {
6238         const struct rte_flow_item_tcp *tcp_m = item->mask;
6239         const struct rte_flow_item_tcp *tcp_v = item->spec;
6240         void *headers_m;
6241         void *headers_v;
6242
6243         if (inner) {
6244                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6245                                          inner_headers);
6246                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6247         } else {
6248                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6249                                          outer_headers);
6250                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6251         }
6252         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6253         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6254         if (!tcp_v)
6255                 return;
6256         if (!tcp_m)
6257                 tcp_m = &rte_flow_item_tcp_mask;
6258         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6259                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6260         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6261                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6262         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6263                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6264         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6265                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6266         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6267                  tcp_m->hdr.tcp_flags);
6268         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6269                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6270 }
6271
6272 /**
6273  * Add UDP item to matcher and to the value.
6274  *
6275  * @param[in, out] matcher
6276  *   Flow matcher.
6277  * @param[in, out] key
6278  *   Flow matcher value.
6279  * @param[in] item
6280  *   Flow pattern to translate.
6281  * @param[in] inner
6282  *   Item is inner pattern.
6283  */
6284 static void
6285 flow_dv_translate_item_udp(void *matcher, void *key,
6286                            const struct rte_flow_item *item,
6287                            int inner)
6288 {
6289         const struct rte_flow_item_udp *udp_m = item->mask;
6290         const struct rte_flow_item_udp *udp_v = item->spec;
6291         void *headers_m;
6292         void *headers_v;
6293
6294         if (inner) {
6295                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6296                                          inner_headers);
6297                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6298         } else {
6299                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6300                                          outer_headers);
6301                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6302         }
6303         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6304         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6305         if (!udp_v)
6306                 return;
6307         if (!udp_m)
6308                 udp_m = &rte_flow_item_udp_mask;
6309         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6310                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6311         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6312                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6313         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6314                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6315         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6316                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6317 }
6318
6319 /**
6320  * Add GRE optional Key item to matcher and to the value.
6321  *
6322  * @param[in, out] matcher
6323  *   Flow matcher.
6324  * @param[in, out] key
6325  *   Flow matcher value.
6326  * @param[in] item
6327  *   Flow pattern to translate.
6328  * @param[in] inner
6329  *   Item is inner pattern.
6330  */
6331 static void
6332 flow_dv_translate_item_gre_key(void *matcher, void *key,
6333                                    const struct rte_flow_item *item)
6334 {
6335         const rte_be32_t *key_m = item->mask;
6336         const rte_be32_t *key_v = item->spec;
6337         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6338         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6339         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6340
6341         /* GRE K bit must be on and should already be validated */
6342         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6343         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6344         if (!key_v)
6345                 return;
6346         if (!key_m)
6347                 key_m = &gre_key_default_mask;
6348         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6349                  rte_be_to_cpu_32(*key_m) >> 8);
6350         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6351                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6352         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6353                  rte_be_to_cpu_32(*key_m) & 0xFF);
6354         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6355                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6356 }
6357
6358 /**
6359  * Add GRE item to matcher and to the value.
6360  *
6361  * @param[in, out] matcher
6362  *   Flow matcher.
6363  * @param[in, out] key
6364  *   Flow matcher value.
6365  * @param[in] item
6366  *   Flow pattern to translate.
6367  * @param[in] inner
6368  *   Item is inner pattern.
6369  */
6370 static void
6371 flow_dv_translate_item_gre(void *matcher, void *key,
6372                            const struct rte_flow_item *item,
6373                            int inner)
6374 {
6375         const struct rte_flow_item_gre *gre_m = item->mask;
6376         const struct rte_flow_item_gre *gre_v = item->spec;
6377         void *headers_m;
6378         void *headers_v;
6379         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6380         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6381         struct {
6382                 union {
6383                         __extension__
6384                         struct {
6385                                 uint16_t version:3;
6386                                 uint16_t rsvd0:9;
6387                                 uint16_t s_present:1;
6388                                 uint16_t k_present:1;
6389                                 uint16_t rsvd_bit1:1;
6390                                 uint16_t c_present:1;
6391                         };
6392                         uint16_t value;
6393                 };
6394         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6395
6396         if (inner) {
6397                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6398                                          inner_headers);
6399                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6400         } else {
6401                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6402                                          outer_headers);
6403                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6404         }
6405         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6406         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6407         if (!gre_v)
6408                 return;
6409         if (!gre_m)
6410                 gre_m = &rte_flow_item_gre_mask;
6411         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6412                  rte_be_to_cpu_16(gre_m->protocol));
6413         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6414                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6415         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6416         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6417         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6418                  gre_crks_rsvd0_ver_m.c_present);
6419         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6420                  gre_crks_rsvd0_ver_v.c_present &
6421                  gre_crks_rsvd0_ver_m.c_present);
6422         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6423                  gre_crks_rsvd0_ver_m.k_present);
6424         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6425                  gre_crks_rsvd0_ver_v.k_present &
6426                  gre_crks_rsvd0_ver_m.k_present);
6427         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6428                  gre_crks_rsvd0_ver_m.s_present);
6429         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6430                  gre_crks_rsvd0_ver_v.s_present &
6431                  gre_crks_rsvd0_ver_m.s_present);
6432 }
6433
6434 /**
6435  * Add NVGRE item to matcher and to the value.
6436  *
6437  * @param[in, out] matcher
6438  *   Flow matcher.
6439  * @param[in, out] key
6440  *   Flow matcher value.
6441  * @param[in] item
6442  *   Flow pattern to translate.
6443  * @param[in] inner
6444  *   Item is inner pattern.
6445  */
6446 static void
6447 flow_dv_translate_item_nvgre(void *matcher, void *key,
6448                              const struct rte_flow_item *item,
6449                              int inner)
6450 {
6451         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6452         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6453         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6454         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6455         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6456         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6457         char *gre_key_m;
6458         char *gre_key_v;
6459         int size;
6460         int i;
6461
6462         /* For NVGRE, GRE header fields must be set with defined values. */
6463         const struct rte_flow_item_gre gre_spec = {
6464                 .c_rsvd0_ver = RTE_BE16(0x2000),
6465                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6466         };
6467         const struct rte_flow_item_gre gre_mask = {
6468                 .c_rsvd0_ver = RTE_BE16(0xB000),
6469                 .protocol = RTE_BE16(UINT16_MAX),
6470         };
6471         const struct rte_flow_item gre_item = {
6472                 .spec = &gre_spec,
6473                 .mask = &gre_mask,
6474                 .last = NULL,
6475         };
6476         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6477         if (!nvgre_v)
6478                 return;
6479         if (!nvgre_m)
6480                 nvgre_m = &rte_flow_item_nvgre_mask;
6481         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6482         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6483         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6484         memcpy(gre_key_m, tni_flow_id_m, size);
6485         for (i = 0; i < size; ++i)
6486                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6487 }
6488
6489 /**
6490  * Add VXLAN item to matcher and to the value.
6491  *
6492  * @param[in, out] matcher
6493  *   Flow matcher.
6494  * @param[in, out] key
6495  *   Flow matcher value.
6496  * @param[in] item
6497  *   Flow pattern to translate.
6498  * @param[in] inner
6499  *   Item is inner pattern.
6500  */
6501 static void
6502 flow_dv_translate_item_vxlan(void *matcher, void *key,
6503                              const struct rte_flow_item *item,
6504                              int inner)
6505 {
6506         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6507         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6508         void *headers_m;
6509         void *headers_v;
6510         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6511         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6512         char *vni_m;
6513         char *vni_v;
6514         uint16_t dport;
6515         int size;
6516         int i;
6517
6518         if (inner) {
6519                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6520                                          inner_headers);
6521                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6522         } else {
6523                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6524                                          outer_headers);
6525                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6526         }
6527         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6528                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6529         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6530                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6531                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6532         }
6533         if (!vxlan_v)
6534                 return;
6535         if (!vxlan_m)
6536                 vxlan_m = &rte_flow_item_vxlan_mask;
6537         size = sizeof(vxlan_m->vni);
6538         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6539         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6540         memcpy(vni_m, vxlan_m->vni, size);
6541         for (i = 0; i < size; ++i)
6542                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6543 }
6544
6545 /**
6546  * Add VXLAN-GPE item to matcher and to the value.
6547  *
6548  * @param[in, out] matcher
6549  *   Flow matcher.
6550  * @param[in, out] key
6551  *   Flow matcher value.
6552  * @param[in] item
6553  *   Flow pattern to translate.
6554  * @param[in] inner
6555  *   Item is inner pattern.
6556  */
6557
6558 static void
6559 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6560                                  const struct rte_flow_item *item, int inner)
6561 {
6562         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6563         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6564         void *headers_m;
6565         void *headers_v;
6566         void *misc_m =
6567                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6568         void *misc_v =
6569                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6570         char *vni_m;
6571         char *vni_v;
6572         uint16_t dport;
6573         int size;
6574         int i;
6575         uint8_t flags_m = 0xff;
6576         uint8_t flags_v = 0xc;
6577
6578         if (inner) {
6579                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6580                                          inner_headers);
6581                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6582         } else {
6583                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6584                                          outer_headers);
6585                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6586         }
6587         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6588                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6589         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6590                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6591                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6592         }
6593         if (!vxlan_v)
6594                 return;
6595         if (!vxlan_m)
6596                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6597         size = sizeof(vxlan_m->vni);
6598         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6599         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6600         memcpy(vni_m, vxlan_m->vni, size);
6601         for (i = 0; i < size; ++i)
6602                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6603         if (vxlan_m->flags) {
6604                 flags_m = vxlan_m->flags;
6605                 flags_v = vxlan_v->flags;
6606         }
6607         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6608         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6609         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6610                  vxlan_m->protocol);
6611         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6612                  vxlan_v->protocol);
6613 }
6614
6615 /**
6616  * Add Geneve item to matcher and to the value.
6617  *
6618  * @param[in, out] matcher
6619  *   Flow matcher.
6620  * @param[in, out] key
6621  *   Flow matcher value.
6622  * @param[in] item
6623  *   Flow pattern to translate.
6624  * @param[in] inner
6625  *   Item is inner pattern.
6626  */
6627
6628 static void
6629 flow_dv_translate_item_geneve(void *matcher, void *key,
6630                               const struct rte_flow_item *item, int inner)
6631 {
6632         const struct rte_flow_item_geneve *geneve_m = item->mask;
6633         const struct rte_flow_item_geneve *geneve_v = item->spec;
6634         void *headers_m;
6635         void *headers_v;
6636         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6637         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6638         uint16_t dport;
6639         uint16_t gbhdr_m;
6640         uint16_t gbhdr_v;
6641         char *vni_m;
6642         char *vni_v;
6643         size_t size, i;
6644
6645         if (inner) {
6646                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6647                                          inner_headers);
6648                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6649         } else {
6650                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6651                                          outer_headers);
6652                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6653         }
6654         dport = MLX5_UDP_PORT_GENEVE;
6655         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6656                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6657                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6658         }
6659         if (!geneve_v)
6660                 return;
6661         if (!geneve_m)
6662                 geneve_m = &rte_flow_item_geneve_mask;
6663         size = sizeof(geneve_m->vni);
6664         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6665         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6666         memcpy(vni_m, geneve_m->vni, size);
6667         for (i = 0; i < size; ++i)
6668                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6669         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6670                  rte_be_to_cpu_16(geneve_m->protocol));
6671         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6672                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6673         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6674         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6675         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6676                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6677         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6678                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6679         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6680                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6681         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6682                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6683                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6684 }
6685
6686 /**
6687  * Add MPLS item to matcher and to the value.
6688  *
6689  * @param[in, out] matcher
6690  *   Flow matcher.
6691  * @param[in, out] key
6692  *   Flow matcher value.
6693  * @param[in] item
6694  *   Flow pattern to translate.
6695  * @param[in] prev_layer
6696  *   The protocol layer indicated in previous item.
6697  * @param[in] inner
6698  *   Item is inner pattern.
6699  */
6700 static void
6701 flow_dv_translate_item_mpls(void *matcher, void *key,
6702                             const struct rte_flow_item *item,
6703                             uint64_t prev_layer,
6704                             int inner)
6705 {
6706         const uint32_t *in_mpls_m = item->mask;
6707         const uint32_t *in_mpls_v = item->spec;
6708         uint32_t *out_mpls_m = 0;
6709         uint32_t *out_mpls_v = 0;
6710         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6711         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6712         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6713                                      misc_parameters_2);
6714         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6715         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6716         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6717
6718         switch (prev_layer) {
6719         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6720                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6721                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6722                          MLX5_UDP_PORT_MPLS);
6723                 break;
6724         case MLX5_FLOW_LAYER_GRE:
6725                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6726                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6727                          RTE_ETHER_TYPE_MPLS);
6728                 break;
6729         default:
6730                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6731                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6732                          IPPROTO_MPLS);
6733                 break;
6734         }
6735         if (!in_mpls_v)
6736                 return;
6737         if (!in_mpls_m)
6738                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6739         switch (prev_layer) {
6740         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6741                 out_mpls_m =
6742                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6743                                                  outer_first_mpls_over_udp);
6744                 out_mpls_v =
6745                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6746                                                  outer_first_mpls_over_udp);
6747                 break;
6748         case MLX5_FLOW_LAYER_GRE:
6749                 out_mpls_m =
6750                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6751                                                  outer_first_mpls_over_gre);
6752                 out_mpls_v =
6753                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6754                                                  outer_first_mpls_over_gre);
6755                 break;
6756         default:
6757                 /* Inner MPLS not over GRE is not supported. */
6758                 if (!inner) {
6759                         out_mpls_m =
6760                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6761                                                          misc2_m,
6762                                                          outer_first_mpls);
6763                         out_mpls_v =
6764                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6765                                                          misc2_v,
6766                                                          outer_first_mpls);
6767                 }
6768                 break;
6769         }
6770         if (out_mpls_m && out_mpls_v) {
6771                 *out_mpls_m = *in_mpls_m;
6772                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6773         }
6774 }
6775
6776 /**
6777  * Add metadata register item to matcher
6778  *
6779  * @param[in, out] matcher
6780  *   Flow matcher.
6781  * @param[in, out] key
6782  *   Flow matcher value.
6783  * @param[in] reg_type
6784  *   Type of device metadata register
6785  * @param[in] value
6786  *   Register value
6787  * @param[in] mask
6788  *   Register mask
6789  */
6790 static void
6791 flow_dv_match_meta_reg(void *matcher, void *key,
6792                        enum modify_reg reg_type,
6793                        uint32_t data, uint32_t mask)
6794 {
6795         void *misc2_m =
6796                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6797         void *misc2_v =
6798                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6799         uint32_t temp;
6800
6801         data &= mask;
6802         switch (reg_type) {
6803         case REG_A:
6804                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6805                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6806                 break;
6807         case REG_B:
6808                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6809                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6810                 break;
6811         case REG_C_0:
6812                 /*
6813                  * The metadata register C0 field might be divided into
6814                  * source vport index and META item value, we should set
6815                  * this field according to specified mask, not as whole one.
6816                  */
6817                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6818                 temp |= mask;
6819                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6820                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6821                 temp &= ~mask;
6822                 temp |= data;
6823                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6824                 break;
6825         case REG_C_1:
6826                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6827                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6828                 break;
6829         case REG_C_2:
6830                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6831                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6832                 break;
6833         case REG_C_3:
6834                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6835                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6836                 break;
6837         case REG_C_4:
6838                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6839                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6840                 break;
6841         case REG_C_5:
6842                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6843                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6844                 break;
6845         case REG_C_6:
6846                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6847                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6848                 break;
6849         case REG_C_7:
6850                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6851                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6852                 break;
6853         default:
6854                 MLX5_ASSERT(false);
6855                 break;
6856         }
6857 }
6858
6859 /**
6860  * Add MARK item to matcher
6861  *
6862  * @param[in] dev
6863  *   The device to configure through.
6864  * @param[in, out] matcher
6865  *   Flow matcher.
6866  * @param[in, out] key
6867  *   Flow matcher value.
6868  * @param[in] item
6869  *   Flow pattern to translate.
6870  */
6871 static void
6872 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6873                             void *matcher, void *key,
6874                             const struct rte_flow_item *item)
6875 {
6876         struct mlx5_priv *priv = dev->data->dev_private;
6877         const struct rte_flow_item_mark *mark;
6878         uint32_t value;
6879         uint32_t mask;
6880
6881         mark = item->mask ? (const void *)item->mask :
6882                             &rte_flow_item_mark_mask;
6883         mask = mark->id & priv->sh->dv_mark_mask;
6884         mark = (const void *)item->spec;
6885         MLX5_ASSERT(mark);
6886         value = mark->id & priv->sh->dv_mark_mask & mask;
6887         if (mask) {
6888                 enum modify_reg reg;
6889
6890                 /* Get the metadata register index for the mark. */
6891                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6892                 MLX5_ASSERT(reg > 0);
6893                 if (reg == REG_C_0) {
6894                         struct mlx5_priv *priv = dev->data->dev_private;
6895                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6896                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6897
6898                         mask &= msk_c0;
6899                         mask <<= shl_c0;
6900                         value <<= shl_c0;
6901                 }
6902                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6903         }
6904 }
6905
6906 /**
6907  * Add META item to matcher
6908  *
6909  * @param[in] dev
6910  *   The devich to configure through.
6911  * @param[in, out] matcher
6912  *   Flow matcher.
6913  * @param[in, out] key
6914  *   Flow matcher value.
6915  * @param[in] attr
6916  *   Attributes of flow that includes this item.
6917  * @param[in] item
6918  *   Flow pattern to translate.
6919  */
6920 static void
6921 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6922                             void *matcher, void *key,
6923                             const struct rte_flow_attr *attr,
6924                             const struct rte_flow_item *item)
6925 {
6926         const struct rte_flow_item_meta *meta_m;
6927         const struct rte_flow_item_meta *meta_v;
6928
6929         meta_m = (const void *)item->mask;
6930         if (!meta_m)
6931                 meta_m = &rte_flow_item_meta_mask;
6932         meta_v = (const void *)item->spec;
6933         if (meta_v) {
6934                 int reg;
6935                 uint32_t value = meta_v->data;
6936                 uint32_t mask = meta_m->data;
6937
6938                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6939                 if (reg < 0)
6940                         return;
6941                 /*
6942                  * In datapath code there is no endianness
6943                  * coversions for perfromance reasons, all
6944                  * pattern conversions are done in rte_flow.
6945                  */
6946                 value = rte_cpu_to_be_32(value);
6947                 mask = rte_cpu_to_be_32(mask);
6948                 if (reg == REG_C_0) {
6949                         struct mlx5_priv *priv = dev->data->dev_private;
6950                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6951                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6952 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6953                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6954
6955                         value >>= shr_c0;
6956                         mask >>= shr_c0;
6957 #endif
6958                         value <<= shl_c0;
6959                         mask <<= shl_c0;
6960                         MLX5_ASSERT(msk_c0);
6961                         MLX5_ASSERT(!(~msk_c0 & mask));
6962                 }
6963                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6964         }
6965 }
6966
6967 /**
6968  * Add vport metadata Reg C0 item to matcher
6969  *
6970  * @param[in, out] matcher
6971  *   Flow matcher.
6972  * @param[in, out] key
6973  *   Flow matcher value.
6974  * @param[in] reg
6975  *   Flow pattern to translate.
6976  */
6977 static void
6978 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6979                                   uint32_t value, uint32_t mask)
6980 {
6981         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6982 }
6983
6984 /**
6985  * Add tag item to matcher
6986  *
6987  * @param[in] dev
6988  *   The devich to configure through.
6989  * @param[in, out] matcher
6990  *   Flow matcher.
6991  * @param[in, out] key
6992  *   Flow matcher value.
6993  * @param[in] item
6994  *   Flow pattern to translate.
6995  */
6996 static void
6997 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6998                                 void *matcher, void *key,
6999                                 const struct rte_flow_item *item)
7000 {
7001         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7002         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7003         uint32_t mask, value;
7004
7005         MLX5_ASSERT(tag_v);
7006         value = tag_v->data;
7007         mask = tag_m ? tag_m->data : UINT32_MAX;
7008         if (tag_v->id == REG_C_0) {
7009                 struct mlx5_priv *priv = dev->data->dev_private;
7010                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7011                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7012
7013                 mask &= msk_c0;
7014                 mask <<= shl_c0;
7015                 value <<= shl_c0;
7016         }
7017         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7018 }
7019
7020 /**
7021  * Add TAG item to matcher
7022  *
7023  * @param[in] dev
7024  *   The devich to configure through.
7025  * @param[in, out] matcher
7026  *   Flow matcher.
7027  * @param[in, out] key
7028  *   Flow matcher value.
7029  * @param[in] item
7030  *   Flow pattern to translate.
7031  */
7032 static void
7033 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7034                            void *matcher, void *key,
7035                            const struct rte_flow_item *item)
7036 {
7037         const struct rte_flow_item_tag *tag_v = item->spec;
7038         const struct rte_flow_item_tag *tag_m = item->mask;
7039         enum modify_reg reg;
7040
7041         MLX5_ASSERT(tag_v);
7042         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7043         /* Get the metadata register index for the tag. */
7044         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7045         MLX5_ASSERT(reg > 0);
7046         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7047 }
7048
7049 /**
7050  * Add source vport match to the specified matcher.
7051  *
7052  * @param[in, out] matcher
7053  *   Flow matcher.
7054  * @param[in, out] key
7055  *   Flow matcher value.
7056  * @param[in] port
7057  *   Source vport value to match
7058  * @param[in] mask
7059  *   Mask
7060  */
7061 static void
7062 flow_dv_translate_item_source_vport(void *matcher, void *key,
7063                                     int16_t port, uint16_t mask)
7064 {
7065         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7066         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7067
7068         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7069         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7070 }
7071
7072 /**
7073  * Translate port-id item to eswitch match on  port-id.
7074  *
7075  * @param[in] dev
7076  *   The devich to configure through.
7077  * @param[in, out] matcher
7078  *   Flow matcher.
7079  * @param[in, out] key
7080  *   Flow matcher value.
7081  * @param[in] item
7082  *   Flow pattern to translate.
7083  *
7084  * @return
7085  *   0 on success, a negative errno value otherwise.
7086  */
7087 static int
7088 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7089                                void *key, const struct rte_flow_item *item)
7090 {
7091         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7092         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7093         struct mlx5_priv *priv;
7094         uint16_t mask, id;
7095
7096         mask = pid_m ? pid_m->id : 0xffff;
7097         id = pid_v ? pid_v->id : dev->data->port_id;
7098         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7099         if (!priv)
7100                 return -rte_errno;
7101         /* Translate to vport field or to metadata, depending on mode. */
7102         if (priv->vport_meta_mask)
7103                 flow_dv_translate_item_meta_vport(matcher, key,
7104                                                   priv->vport_meta_tag,
7105                                                   priv->vport_meta_mask);
7106         else
7107                 flow_dv_translate_item_source_vport(matcher, key,
7108                                                     priv->vport_id, mask);
7109         return 0;
7110 }
7111
7112 /**
7113  * Add ICMP6 item to matcher and to the value.
7114  *
7115  * @param[in, out] matcher
7116  *   Flow matcher.
7117  * @param[in, out] key
7118  *   Flow matcher value.
7119  * @param[in] item
7120  *   Flow pattern to translate.
7121  * @param[in] inner
7122  *   Item is inner pattern.
7123  */
7124 static void
7125 flow_dv_translate_item_icmp6(void *matcher, void *key,
7126                               const struct rte_flow_item *item,
7127                               int inner)
7128 {
7129         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7130         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7131         void *headers_m;
7132         void *headers_v;
7133         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7134                                      misc_parameters_3);
7135         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7136         if (inner) {
7137                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7138                                          inner_headers);
7139                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7140         } else {
7141                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7142                                          outer_headers);
7143                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7144         }
7145         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7146         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7147         if (!icmp6_v)
7148                 return;
7149         if (!icmp6_m)
7150                 icmp6_m = &rte_flow_item_icmp6_mask;
7151         /*
7152          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7153          * If only the protocol is specified, no need to match the frag.
7154          */
7155         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7156         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7157         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7158         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7159                  icmp6_v->type & icmp6_m->type);
7160         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7161         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7162                  icmp6_v->code & icmp6_m->code);
7163 }
7164
7165 /**
7166  * Add ICMP item to matcher and to the value.
7167  *
7168  * @param[in, out] matcher
7169  *   Flow matcher.
7170  * @param[in, out] key
7171  *   Flow matcher value.
7172  * @param[in] item
7173  *   Flow pattern to translate.
7174  * @param[in] inner
7175  *   Item is inner pattern.
7176  */
7177 static void
7178 flow_dv_translate_item_icmp(void *matcher, void *key,
7179                             const struct rte_flow_item *item,
7180                             int inner)
7181 {
7182         const struct rte_flow_item_icmp *icmp_m = item->mask;
7183         const struct rte_flow_item_icmp *icmp_v = item->spec;
7184         void *headers_m;
7185         void *headers_v;
7186         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7187                                      misc_parameters_3);
7188         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7189         if (inner) {
7190                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7191                                          inner_headers);
7192                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7193         } else {
7194                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7195                                          outer_headers);
7196                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7197         }
7198         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7199         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7200         if (!icmp_v)
7201                 return;
7202         if (!icmp_m)
7203                 icmp_m = &rte_flow_item_icmp_mask;
7204         /*
7205          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7206          * If only the protocol is specified, no need to match the frag.
7207          */
7208         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7209         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7210         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7211                  icmp_m->hdr.icmp_type);
7212         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7213                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7214         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7215                  icmp_m->hdr.icmp_code);
7216         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7217                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7218 }
7219
7220 /**
7221  * Add GTP item to matcher and to the value.
7222  *
7223  * @param[in, out] matcher
7224  *   Flow matcher.
7225  * @param[in, out] key
7226  *   Flow matcher value.
7227  * @param[in] item
7228  *   Flow pattern to translate.
7229  * @param[in] inner
7230  *   Item is inner pattern.
7231  */
7232 static void
7233 flow_dv_translate_item_gtp(void *matcher, void *key,
7234                            const struct rte_flow_item *item, int inner)
7235 {
7236         const struct rte_flow_item_gtp *gtp_m = item->mask;
7237         const struct rte_flow_item_gtp *gtp_v = item->spec;
7238         void *headers_m;
7239         void *headers_v;
7240         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7241                                      misc_parameters_3);
7242         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7243         uint16_t dport = RTE_GTPU_UDP_PORT;
7244
7245         if (inner) {
7246                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7247                                          inner_headers);
7248                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7249         } else {
7250                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7251                                          outer_headers);
7252                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7253         }
7254         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7255                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7257         }
7258         if (!gtp_v)
7259                 return;
7260         if (!gtp_m)
7261                 gtp_m = &rte_flow_item_gtp_mask;
7262         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7263                  gtp_m->v_pt_rsv_flags);
7264         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7265                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7266         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7267         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7268                  gtp_v->msg_type & gtp_m->msg_type);
7269         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7270                  rte_be_to_cpu_32(gtp_m->teid));
7271         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7272                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7273 }
7274
7275 /**
7276  * Add eCPRI item to matcher and to the value.
7277  *
7278  * @param[in] dev
7279  *   The devich to configure through.
7280  * @param[in, out] matcher
7281  *   Flow matcher.
7282  * @param[in, out] key
7283  *   Flow matcher value.
7284  * @param[in] item
7285  *   Flow pattern to translate.
7286  * @param[in] samples
7287  *   Sample IDs to be used in the matching.
7288  */
7289 static void
7290 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7291                              void *key, const struct rte_flow_item *item)
7292 {
7293         struct mlx5_priv *priv = dev->data->dev_private;
7294         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7295         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7296         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7297                                      misc_parameters_4);
7298         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7299         uint32_t *samples;
7300         void *dw_m;
7301         void *dw_v;
7302
7303         if (!ecpri_v)
7304                 return;
7305         if (!ecpri_m)
7306                 ecpri_m = &rte_flow_item_ecpri_mask;
7307         /*
7308          * Maximal four DW samples are supported in a single matching now.
7309          * Two are used now for a eCPRI matching:
7310          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7311          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7312          *    if any.
7313          */
7314         if (!ecpri_m->hdr.common.u32)
7315                 return;
7316         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7317         /* Need to take the whole DW as the mask to fill the entry. */
7318         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7319                             prog_sample_field_value_0);
7320         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7321                             prog_sample_field_value_0);
7322         /* Already big endian (network order) in the header. */
7323         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7324         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7325         /* Sample#0, used for matching type, offset 0. */
7326         MLX5_SET(fte_match_set_misc4, misc4_m,
7327                  prog_sample_field_id_0, samples[0]);
7328         /* It makes no sense to set the sample ID in the mask field. */
7329         MLX5_SET(fte_match_set_misc4, misc4_v,
7330                  prog_sample_field_id_0, samples[0]);
7331         /*
7332          * Checking if message body part needs to be matched.
7333          * Some wildcard rules only matching type field should be supported.
7334          */
7335         if (ecpri_m->hdr.dummy[0]) {
7336                 switch (ecpri_v->hdr.common.type) {
7337                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7338                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7339                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7340                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7341                                             prog_sample_field_value_1);
7342                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7343                                             prog_sample_field_value_1);
7344                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7345                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7346                         /* Sample#1, to match message body, offset 4. */
7347                         MLX5_SET(fte_match_set_misc4, misc4_m,
7348                                  prog_sample_field_id_1, samples[1]);
7349                         MLX5_SET(fte_match_set_misc4, misc4_v,
7350                                  prog_sample_field_id_1, samples[1]);
7351                         break;
7352                 default:
7353                         /* Others, do not match any sample ID. */
7354                         break;
7355                 }
7356         }
7357 }
7358
7359 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7360
7361 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7362         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7363                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7364
7365 /**
7366  * Calculate flow matcher enable bitmap.
7367  *
7368  * @param match_criteria
7369  *   Pointer to flow matcher criteria.
7370  *
7371  * @return
7372  *   Bitmap of enabled fields.
7373  */
7374 static uint8_t
7375 flow_dv_matcher_enable(uint32_t *match_criteria)
7376 {
7377         uint8_t match_criteria_enable;
7378
7379         match_criteria_enable =
7380                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7381                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7382         match_criteria_enable |=
7383                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7384                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7385         match_criteria_enable |=
7386                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7387                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7388         match_criteria_enable |=
7389                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7390                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7391         match_criteria_enable |=
7392                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7393                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7394         match_criteria_enable |=
7395                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7396                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7397         return match_criteria_enable;
7398 }
7399
7400
7401 /**
7402  * Get a flow table.
7403  *
7404  * @param[in, out] dev
7405  *   Pointer to rte_eth_dev structure.
7406  * @param[in] table_id
7407  *   Table id to use.
7408  * @param[in] egress
7409  *   Direction of the table.
7410  * @param[in] transfer
7411  *   E-Switch or NIC flow.
7412  * @param[out] error
7413  *   pointer to error structure.
7414  *
7415  * @return
7416  *   Returns tables resource based on the index, NULL in case of failed.
7417  */
7418 static struct mlx5_flow_tbl_resource *
7419 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7420                          uint32_t table_id, uint8_t egress,
7421                          uint8_t transfer,
7422                          struct rte_flow_error *error)
7423 {
7424         struct mlx5_priv *priv = dev->data->dev_private;
7425         struct mlx5_dev_ctx_shared *sh = priv->sh;
7426         struct mlx5_flow_tbl_resource *tbl;
7427         union mlx5_flow_tbl_key table_key = {
7428                 {
7429                         .table_id = table_id,
7430                         .reserved = 0,
7431                         .domain = !!transfer,
7432                         .direction = !!egress,
7433                 }
7434         };
7435         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7436                                                          table_key.v64);
7437         struct mlx5_flow_tbl_data_entry *tbl_data;
7438         uint32_t idx = 0;
7439         int ret;
7440         void *domain;
7441
7442         if (pos) {
7443                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7444                                         entry);
7445                 tbl = &tbl_data->tbl;
7446                 rte_atomic32_inc(&tbl->refcnt);
7447                 return tbl;
7448         }
7449         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7450         if (!tbl_data) {
7451                 rte_flow_error_set(error, ENOMEM,
7452                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7453                                    NULL,
7454                                    "cannot allocate flow table data entry");
7455                 return NULL;
7456         }
7457         tbl_data->idx = idx;
7458         tbl = &tbl_data->tbl;
7459         pos = &tbl_data->entry;
7460         if (transfer)
7461                 domain = sh->fdb_domain;
7462         else if (egress)
7463                 domain = sh->tx_domain;
7464         else
7465                 domain = sh->rx_domain;
7466         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7467         if (ret) {
7468                 rte_flow_error_set(error, ENOMEM,
7469                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7470                                    NULL, "cannot create flow table object");
7471                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7472                 return NULL;
7473         }
7474         /*
7475          * No multi-threads now, but still better to initialize the reference
7476          * count before insert it into the hash list.
7477          */
7478         rte_atomic32_init(&tbl->refcnt);
7479         /* Jump action reference count is initialized here. */
7480         rte_atomic32_init(&tbl_data->jump.refcnt);
7481         pos->key = table_key.v64;
7482         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7483         if (ret < 0) {
7484                 rte_flow_error_set(error, -ret,
7485                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7486                                    "cannot insert flow table data entry");
7487                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7488                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7489         }
7490         rte_atomic32_inc(&tbl->refcnt);
7491         return tbl;
7492 }
7493
7494 /**
7495  * Release a flow table.
7496  *
7497  * @param[in] dev
7498  *   Pointer to rte_eth_dev structure.
7499  * @param[in] tbl
7500  *   Table resource to be released.
7501  *
7502  * @return
7503  *   Returns 0 if table was released, else return 1;
7504  */
7505 static int
7506 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7507                              struct mlx5_flow_tbl_resource *tbl)
7508 {
7509         struct mlx5_priv *priv = dev->data->dev_private;
7510         struct mlx5_dev_ctx_shared *sh = priv->sh;
7511         struct mlx5_flow_tbl_data_entry *tbl_data =
7512                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7513
7514         if (!tbl)
7515                 return 0;
7516         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7517                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7518
7519                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7520                 tbl->obj = NULL;
7521                 /* remove the entry from the hash list and free memory. */
7522                 mlx5_hlist_remove(sh->flow_tbls, pos);
7523                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7524                                 tbl_data->idx);
7525                 return 0;
7526         }
7527         return 1;
7528 }
7529
7530 /**
7531  * Register the flow matcher.
7532  *
7533  * @param[in, out] dev
7534  *   Pointer to rte_eth_dev structure.
7535  * @param[in, out] matcher
7536  *   Pointer to flow matcher.
7537  * @param[in, out] key
7538  *   Pointer to flow table key.
7539  * @parm[in, out] dev_flow
7540  *   Pointer to the dev_flow.
7541  * @param[out] error
7542  *   pointer to error structure.
7543  *
7544  * @return
7545  *   0 on success otherwise -errno and errno is set.
7546  */
7547 static int
7548 flow_dv_matcher_register(struct rte_eth_dev *dev,
7549                          struct mlx5_flow_dv_matcher *matcher,
7550                          union mlx5_flow_tbl_key *key,
7551                          struct mlx5_flow *dev_flow,
7552                          struct rte_flow_error *error)
7553 {
7554         struct mlx5_priv *priv = dev->data->dev_private;
7555         struct mlx5_dev_ctx_shared *sh = priv->sh;
7556         struct mlx5_flow_dv_matcher *cache_matcher;
7557         struct mlx5dv_flow_matcher_attr dv_attr = {
7558                 .type = IBV_FLOW_ATTR_NORMAL,
7559                 .match_mask = (void *)&matcher->mask,
7560         };
7561         struct mlx5_flow_tbl_resource *tbl;
7562         struct mlx5_flow_tbl_data_entry *tbl_data;
7563         int ret;
7564
7565         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7566                                        key->domain, error);
7567         if (!tbl)
7568                 return -rte_errno;      /* No need to refill the error info */
7569         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7570         /* Lookup from cache. */
7571         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7572                 if (matcher->crc == cache_matcher->crc &&
7573                     matcher->priority == cache_matcher->priority &&
7574                     !memcmp((const void *)matcher->mask.buf,
7575                             (const void *)cache_matcher->mask.buf,
7576                             cache_matcher->mask.size)) {
7577                         DRV_LOG(DEBUG,
7578                                 "%s group %u priority %hd use %s "
7579                                 "matcher %p: refcnt %d++",
7580                                 key->domain ? "FDB" : "NIC", key->table_id,
7581                                 cache_matcher->priority,
7582                                 key->direction ? "tx" : "rx",
7583                                 (void *)cache_matcher,
7584                                 rte_atomic32_read(&cache_matcher->refcnt));
7585                         rte_atomic32_inc(&cache_matcher->refcnt);
7586                         dev_flow->handle->dvh.matcher = cache_matcher;
7587                         /* old matcher should not make the table ref++. */
7588                         flow_dv_tbl_resource_release(dev, tbl);
7589                         return 0;
7590                 }
7591         }
7592         /* Register new matcher. */
7593         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7594                                     SOCKET_ID_ANY);
7595         if (!cache_matcher) {
7596                 flow_dv_tbl_resource_release(dev, tbl);
7597                 return rte_flow_error_set(error, ENOMEM,
7598                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7599                                           "cannot allocate matcher memory");
7600         }
7601         *cache_matcher = *matcher;
7602         dv_attr.match_criteria_enable =
7603                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7604         dv_attr.priority = matcher->priority;
7605         if (key->direction)
7606                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7607         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7608                                                &cache_matcher->matcher_object);
7609         if (ret) {
7610                 mlx5_free(cache_matcher);
7611 #ifdef HAVE_MLX5DV_DR
7612                 flow_dv_tbl_resource_release(dev, tbl);
7613 #endif
7614                 return rte_flow_error_set(error, ENOMEM,
7615                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7616                                           NULL, "cannot create matcher");
7617         }
7618         /* Save the table information */
7619         cache_matcher->tbl = tbl;
7620         rte_atomic32_init(&cache_matcher->refcnt);
7621         /* only matcher ref++, table ref++ already done above in get API. */
7622         rte_atomic32_inc(&cache_matcher->refcnt);
7623         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7624         dev_flow->handle->dvh.matcher = cache_matcher;
7625         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7626                 key->domain ? "FDB" : "NIC", key->table_id,
7627                 cache_matcher->priority,
7628                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7629                 rte_atomic32_read(&cache_matcher->refcnt));
7630         return 0;
7631 }
7632
7633 /**
7634  * Find existing tag resource or create and register a new one.
7635  *
7636  * @param dev[in, out]
7637  *   Pointer to rte_eth_dev structure.
7638  * @param[in, out] tag_be24
7639  *   Tag value in big endian then R-shift 8.
7640  * @parm[in, out] dev_flow
7641  *   Pointer to the dev_flow.
7642  * @param[out] error
7643  *   pointer to error structure.
7644  *
7645  * @return
7646  *   0 on success otherwise -errno and errno is set.
7647  */
7648 static int
7649 flow_dv_tag_resource_register
7650                         (struct rte_eth_dev *dev,
7651                          uint32_t tag_be24,
7652                          struct mlx5_flow *dev_flow,
7653                          struct rte_flow_error *error)
7654 {
7655         struct mlx5_priv *priv = dev->data->dev_private;
7656         struct mlx5_dev_ctx_shared *sh = priv->sh;
7657         struct mlx5_flow_dv_tag_resource *cache_resource;
7658         struct mlx5_hlist_entry *entry;
7659         int ret;
7660
7661         /* Lookup a matching resource from cache. */
7662         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7663         if (entry) {
7664                 cache_resource = container_of
7665                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7666                 rte_atomic32_inc(&cache_resource->refcnt);
7667                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7668                 dev_flow->dv.tag_resource = cache_resource;
7669                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7670                         (void *)cache_resource,
7671                         rte_atomic32_read(&cache_resource->refcnt));
7672                 return 0;
7673         }
7674         /* Register new resource. */
7675         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7676                                        &dev_flow->handle->dvh.rix_tag);
7677         if (!cache_resource)
7678                 return rte_flow_error_set(error, ENOMEM,
7679                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7680                                           "cannot allocate resource memory");
7681         cache_resource->entry.key = (uint64_t)tag_be24;
7682         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7683                                                   &cache_resource->action);
7684         if (ret) {
7685                 mlx5_free(cache_resource);
7686                 return rte_flow_error_set(error, ENOMEM,
7687                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7688                                           NULL, "cannot create action");
7689         }
7690         rte_atomic32_init(&cache_resource->refcnt);
7691         rte_atomic32_inc(&cache_resource->refcnt);
7692         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7693                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7694                 mlx5_free(cache_resource);
7695                 return rte_flow_error_set(error, EEXIST,
7696                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7697                                           NULL, "cannot insert tag");
7698         }
7699         dev_flow->dv.tag_resource = cache_resource;
7700         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7701                 (void *)cache_resource,
7702                 rte_atomic32_read(&cache_resource->refcnt));
7703         return 0;
7704 }
7705
7706 /**
7707  * Release the tag.
7708  *
7709  * @param dev
7710  *   Pointer to Ethernet device.
7711  * @param tag_idx
7712  *   Tag index.
7713  *
7714  * @return
7715  *   1 while a reference on it exists, 0 when freed.
7716  */
7717 static int
7718 flow_dv_tag_release(struct rte_eth_dev *dev,
7719                     uint32_t tag_idx)
7720 {
7721         struct mlx5_priv *priv = dev->data->dev_private;
7722         struct mlx5_dev_ctx_shared *sh = priv->sh;
7723         struct mlx5_flow_dv_tag_resource *tag;
7724
7725         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7726         if (!tag)
7727                 return 0;
7728         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7729                 dev->data->port_id, (void *)tag,
7730                 rte_atomic32_read(&tag->refcnt));
7731         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7732                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7733                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7734                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7735                         dev->data->port_id, (void *)tag);
7736                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7737                 return 0;
7738         }
7739         return 1;
7740 }
7741
7742 /**
7743  * Translate port ID action to vport.
7744  *
7745  * @param[in] dev
7746  *   Pointer to rte_eth_dev structure.
7747  * @param[in] action
7748  *   Pointer to the port ID action.
7749  * @param[out] dst_port_id
7750  *   The target port ID.
7751  * @param[out] error
7752  *   Pointer to the error structure.
7753  *
7754  * @return
7755  *   0 on success, a negative errno value otherwise and rte_errno is set.
7756  */
7757 static int
7758 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7759                                  const struct rte_flow_action *action,
7760                                  uint32_t *dst_port_id,
7761                                  struct rte_flow_error *error)
7762 {
7763         uint32_t port;
7764         struct mlx5_priv *priv;
7765         const struct rte_flow_action_port_id *conf =
7766                         (const struct rte_flow_action_port_id *)action->conf;
7767
7768         port = conf->original ? dev->data->port_id : conf->id;
7769         priv = mlx5_port_to_eswitch_info(port, false);
7770         if (!priv)
7771                 return rte_flow_error_set(error, -rte_errno,
7772                                           RTE_FLOW_ERROR_TYPE_ACTION,
7773                                           NULL,
7774                                           "No eswitch info was found for port");
7775 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7776         /*
7777          * This parameter is transferred to
7778          * mlx5dv_dr_action_create_dest_ib_port().
7779          */
7780         *dst_port_id = priv->dev_port;
7781 #else
7782         /*
7783          * Legacy mode, no LAG configurations is supported.
7784          * This parameter is transferred to
7785          * mlx5dv_dr_action_create_dest_vport().
7786          */
7787         *dst_port_id = priv->vport_id;
7788 #endif
7789         return 0;
7790 }
7791
7792 /**
7793  * Create a counter with aging configuration.
7794  *
7795  * @param[in] dev
7796  *   Pointer to rte_eth_dev structure.
7797  * @param[out] count
7798  *   Pointer to the counter action configuration.
7799  * @param[in] age
7800  *   Pointer to the aging action configuration.
7801  *
7802  * @return
7803  *   Index to flow counter on success, 0 otherwise.
7804  */
7805 static uint32_t
7806 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7807                                 struct mlx5_flow *dev_flow,
7808                                 const struct rte_flow_action_count *count,
7809                                 const struct rte_flow_action_age *age)
7810 {
7811         uint32_t counter;
7812         struct mlx5_age_param *age_param;
7813
7814         counter = flow_dv_counter_alloc(dev,
7815                                 count ? count->shared : 0,
7816                                 count ? count->id : 0,
7817                                 dev_flow->dv.group, !!age);
7818         if (!counter || age == NULL)
7819                 return counter;
7820         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7821         /*
7822          * The counter age accuracy may have a bit delay. Have 3/4
7823          * second bias on the timeount in order to let it age in time.
7824          */
7825         age_param->context = age->context ? age->context :
7826                 (void *)(uintptr_t)(dev_flow->flow_idx);
7827         /*
7828          * The counter age accuracy may have a bit delay. Have 3/4
7829          * second bias on the timeount in order to let it age in time.
7830          */
7831         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7832         /* Set expire time in unit of 0.1 sec. */
7833         age_param->port_id = dev->data->port_id;
7834         age_param->expire = age_param->timeout +
7835                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7836         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7837         return counter;
7838 }
7839 /**
7840  * Add Tx queue matcher
7841  *
7842  * @param[in] dev
7843  *   Pointer to the dev struct.
7844  * @param[in, out] matcher
7845  *   Flow matcher.
7846  * @param[in, out] key
7847  *   Flow matcher value.
7848  * @param[in] item
7849  *   Flow pattern to translate.
7850  * @param[in] inner
7851  *   Item is inner pattern.
7852  */
7853 static void
7854 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7855                                 void *matcher, void *key,
7856                                 const struct rte_flow_item *item)
7857 {
7858         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7859         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7860         void *misc_m =
7861                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7862         void *misc_v =
7863                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7864         struct mlx5_txq_ctrl *txq;
7865         uint32_t queue;
7866
7867
7868         queue_m = (const void *)item->mask;
7869         if (!queue_m)
7870                 return;
7871         queue_v = (const void *)item->spec;
7872         if (!queue_v)
7873                 return;
7874         txq = mlx5_txq_get(dev, queue_v->queue);
7875         if (!txq)
7876                 return;
7877         queue = txq->obj->sq->id;
7878         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7879         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7880                  queue & queue_m->queue);
7881         mlx5_txq_release(dev, queue_v->queue);
7882 }
7883
7884 /**
7885  * Set the hash fields according to the @p flow information.
7886  *
7887  * @param[in] dev_flow
7888  *   Pointer to the mlx5_flow.
7889  * @param[in] rss_desc
7890  *   Pointer to the mlx5_flow_rss_desc.
7891  */
7892 static void
7893 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7894                        struct mlx5_flow_rss_desc *rss_desc)
7895 {
7896         uint64_t items = dev_flow->handle->layers;
7897         int rss_inner = 0;
7898         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7899
7900         dev_flow->hash_fields = 0;
7901 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7902         if (rss_desc->level >= 2) {
7903                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7904                 rss_inner = 1;
7905         }
7906 #endif
7907         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7908             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7909                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7910                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7911                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7912                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7913                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7914                         else
7915                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7916                 }
7917         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7918                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7919                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7920                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7921                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7922                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7923                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7924                         else
7925                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7926                 }
7927         }
7928         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7929             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7930                 if (rss_types & ETH_RSS_UDP) {
7931                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7932                                 dev_flow->hash_fields |=
7933                                                 IBV_RX_HASH_SRC_PORT_UDP;
7934                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7935                                 dev_flow->hash_fields |=
7936                                                 IBV_RX_HASH_DST_PORT_UDP;
7937                         else
7938                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7939                 }
7940         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7941                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7942                 if (rss_types & ETH_RSS_TCP) {
7943                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7944                                 dev_flow->hash_fields |=
7945                                                 IBV_RX_HASH_SRC_PORT_TCP;
7946                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7947                                 dev_flow->hash_fields |=
7948                                                 IBV_RX_HASH_DST_PORT_TCP;
7949                         else
7950                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7951                 }
7952         }
7953 }
7954
7955 /**
7956  * Fill the flow with DV spec, lock free
7957  * (mutex should be acquired by caller).
7958  *
7959  * @param[in] dev
7960  *   Pointer to rte_eth_dev structure.
7961  * @param[in, out] dev_flow
7962  *   Pointer to the sub flow.
7963  * @param[in] attr
7964  *   Pointer to the flow attributes.
7965  * @param[in] items
7966  *   Pointer to the list of items.
7967  * @param[in] actions
7968  *   Pointer to the list of actions.
7969  * @param[out] error
7970  *   Pointer to the error structure.
7971  *
7972  * @return
7973  *   0 on success, a negative errno value otherwise and rte_errno is set.
7974  */
7975 static int
7976 __flow_dv_translate(struct rte_eth_dev *dev,
7977                     struct mlx5_flow *dev_flow,
7978                     const struct rte_flow_attr *attr,
7979                     const struct rte_flow_item items[],
7980                     const struct rte_flow_action actions[],
7981                     struct rte_flow_error *error)
7982 {
7983         struct mlx5_priv *priv = dev->data->dev_private;
7984         struct mlx5_dev_config *dev_conf = &priv->config;
7985         struct rte_flow *flow = dev_flow->flow;
7986         struct mlx5_flow_handle *handle = dev_flow->handle;
7987         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7988                                               priv->rss_desc)
7989                                               [!!priv->flow_nested_idx];
7990         uint64_t item_flags = 0;
7991         uint64_t last_item = 0;
7992         uint64_t action_flags = 0;
7993         uint64_t priority = attr->priority;
7994         struct mlx5_flow_dv_matcher matcher = {
7995                 .mask = {
7996                         .size = sizeof(matcher.mask.buf) -
7997                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
7998                 },
7999         };
8000         int actions_n = 0;
8001         bool actions_end = false;
8002         union {
8003                 struct mlx5_flow_dv_modify_hdr_resource res;
8004                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8005                             sizeof(struct mlx5_modification_cmd) *
8006                             (MLX5_MAX_MODIFY_NUM + 1)];
8007         } mhdr_dummy;
8008         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8009         const struct rte_flow_action_count *count = NULL;
8010         const struct rte_flow_action_age *age = NULL;
8011         union flow_dv_attr flow_attr = { .attr = 0 };
8012         uint32_t tag_be;
8013         union mlx5_flow_tbl_key tbl_key;
8014         uint32_t modify_action_position = UINT32_MAX;
8015         void *match_mask = matcher.mask.buf;
8016         void *match_value = dev_flow->dv.value.buf;
8017         uint8_t next_protocol = 0xff;
8018         struct rte_vlan_hdr vlan = { 0 };
8019         uint32_t table;
8020         int ret = 0;
8021
8022         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8023                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8024         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8025                                        !!priv->fdb_def_rule, &table, error);
8026         if (ret)
8027                 return ret;
8028         dev_flow->dv.group = table;
8029         if (attr->transfer)
8030                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8031         if (priority == MLX5_FLOW_PRIO_RSVD)
8032                 priority = dev_conf->flow_prio - 1;
8033         /* number of actions must be set to 0 in case of dirty stack. */
8034         mhdr_res->actions_num = 0;
8035         for (; !actions_end ; actions++) {
8036                 const struct rte_flow_action_queue *queue;
8037                 const struct rte_flow_action_rss *rss;
8038                 const struct rte_flow_action *action = actions;
8039                 const uint8_t *rss_key;
8040                 const struct rte_flow_action_jump *jump_data;
8041                 const struct rte_flow_action_meter *mtr;
8042                 struct mlx5_flow_tbl_resource *tbl;
8043                 uint32_t port_id = 0;
8044                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8045                 int action_type = actions->type;
8046                 const struct rte_flow_action *found_action = NULL;
8047                 struct mlx5_flow_meter *fm = NULL;
8048
8049                 if (!mlx5_flow_os_action_supported(action_type))
8050                         return rte_flow_error_set(error, ENOTSUP,
8051                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8052                                                   actions,
8053                                                   "action not supported");
8054                 switch (action_type) {
8055                 case RTE_FLOW_ACTION_TYPE_VOID:
8056                         break;
8057                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8058                         if (flow_dv_translate_action_port_id(dev, action,
8059                                                              &port_id, error))
8060                                 return -rte_errno;
8061                         port_id_resource.port_id = port_id;
8062                         MLX5_ASSERT(!handle->rix_port_id_action);
8063                         if (flow_dv_port_id_action_resource_register
8064                             (dev, &port_id_resource, dev_flow, error))
8065                                 return -rte_errno;
8066                         dev_flow->dv.actions[actions_n++] =
8067                                         dev_flow->dv.port_id_action->action;
8068                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8069                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8070                         break;
8071                 case RTE_FLOW_ACTION_TYPE_FLAG:
8072                         action_flags |= MLX5_FLOW_ACTION_FLAG;
8073                         dev_flow->handle->mark = 1;
8074                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8075                                 struct rte_flow_action_mark mark = {
8076                                         .id = MLX5_FLOW_MARK_DEFAULT,
8077                                 };
8078
8079                                 if (flow_dv_convert_action_mark(dev, &mark,
8080                                                                 mhdr_res,
8081                                                                 error))
8082                                         return -rte_errno;
8083                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8084                                 break;
8085                         }
8086                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8087                         /*
8088                          * Only one FLAG or MARK is supported per device flow
8089                          * right now. So the pointer to the tag resource must be
8090                          * zero before the register process.
8091                          */
8092                         MLX5_ASSERT(!handle->dvh.rix_tag);
8093                         if (flow_dv_tag_resource_register(dev, tag_be,
8094                                                           dev_flow, error))
8095                                 return -rte_errno;
8096                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8097                         dev_flow->dv.actions[actions_n++] =
8098                                         dev_flow->dv.tag_resource->action;
8099                         break;
8100                 case RTE_FLOW_ACTION_TYPE_MARK:
8101                         action_flags |= MLX5_FLOW_ACTION_MARK;
8102                         dev_flow->handle->mark = 1;
8103                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8104                                 const struct rte_flow_action_mark *mark =
8105                                         (const struct rte_flow_action_mark *)
8106                                                 actions->conf;
8107
8108                                 if (flow_dv_convert_action_mark(dev, mark,
8109                                                                 mhdr_res,
8110                                                                 error))
8111                                         return -rte_errno;
8112                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8113                                 break;
8114                         }
8115                         /* Fall-through */
8116                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8117                         /* Legacy (non-extensive) MARK action. */
8118                         tag_be = mlx5_flow_mark_set
8119                               (((const struct rte_flow_action_mark *)
8120                                (actions->conf))->id);
8121                         MLX5_ASSERT(!handle->dvh.rix_tag);
8122                         if (flow_dv_tag_resource_register(dev, tag_be,
8123                                                           dev_flow, error))
8124                                 return -rte_errno;
8125                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8126                         dev_flow->dv.actions[actions_n++] =
8127                                         dev_flow->dv.tag_resource->action;
8128                         break;
8129                 case RTE_FLOW_ACTION_TYPE_SET_META:
8130                         if (flow_dv_convert_action_set_meta
8131                                 (dev, mhdr_res, attr,
8132                                  (const struct rte_flow_action_set_meta *)
8133                                   actions->conf, error))
8134                                 return -rte_errno;
8135                         action_flags |= MLX5_FLOW_ACTION_SET_META;
8136                         break;
8137                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8138                         if (flow_dv_convert_action_set_tag
8139                                 (dev, mhdr_res,
8140                                  (const struct rte_flow_action_set_tag *)
8141                                   actions->conf, error))
8142                                 return -rte_errno;
8143                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8144                         break;
8145                 case RTE_FLOW_ACTION_TYPE_DROP:
8146                         action_flags |= MLX5_FLOW_ACTION_DROP;
8147                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8148                         break;
8149                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8150                         queue = actions->conf;
8151                         rss_desc->queue_num = 1;
8152                         rss_desc->queue[0] = queue->index;
8153                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8154                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8155                         break;
8156                 case RTE_FLOW_ACTION_TYPE_RSS:
8157                         rss = actions->conf;
8158                         memcpy(rss_desc->queue, rss->queue,
8159                                rss->queue_num * sizeof(uint16_t));
8160                         rss_desc->queue_num = rss->queue_num;
8161                         /* NULL RSS key indicates default RSS key. */
8162                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
8163                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8164                         /*
8165                          * rss->level and rss.types should be set in advance
8166                          * when expanding items for RSS.
8167                          */
8168                         action_flags |= MLX5_FLOW_ACTION_RSS;
8169                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8170                         break;
8171                 case RTE_FLOW_ACTION_TYPE_AGE:
8172                 case RTE_FLOW_ACTION_TYPE_COUNT:
8173                         if (!dev_conf->devx) {
8174                                 return rte_flow_error_set
8175                                               (error, ENOTSUP,
8176                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8177                                                NULL,
8178                                                "count action not supported");
8179                         }
8180                         /* Save information first, will apply later. */
8181                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8182                                 count = action->conf;
8183                         else
8184                                 age = action->conf;
8185                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8186                         break;
8187                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8188                         dev_flow->dv.actions[actions_n++] =
8189                                                 priv->sh->pop_vlan_action;
8190                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8191                         break;
8192                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8193                         if (!(action_flags &
8194                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8195                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8196                         vlan.eth_proto = rte_be_to_cpu_16
8197                              ((((const struct rte_flow_action_of_push_vlan *)
8198                                                    actions->conf)->ethertype));
8199                         found_action = mlx5_flow_find_action
8200                                         (actions + 1,
8201                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8202                         if (found_action)
8203                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8204                         found_action = mlx5_flow_find_action
8205                                         (actions + 1,
8206                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8207                         if (found_action)
8208                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8209                         if (flow_dv_create_action_push_vlan
8210                                             (dev, attr, &vlan, dev_flow, error))
8211                                 return -rte_errno;
8212                         dev_flow->dv.actions[actions_n++] =
8213                                         dev_flow->dv.push_vlan_res->action;
8214                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8215                         break;
8216                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8217                         /* of_vlan_push action handled this action */
8218                         MLX5_ASSERT(action_flags &
8219                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8220                         break;
8221                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8222                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8223                                 break;
8224                         flow_dev_get_vlan_info_from_items(items, &vlan);
8225                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8226                         /* If no VLAN push - this is a modify header action */
8227                         if (flow_dv_convert_action_modify_vlan_vid
8228                                                 (mhdr_res, actions, error))
8229                                 return -rte_errno;
8230                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8231                         break;
8232                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8233                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8234                         if (flow_dv_create_action_l2_encap(dev, actions,
8235                                                            dev_flow,
8236                                                            attr->transfer,
8237                                                            error))
8238                                 return -rte_errno;
8239                         dev_flow->dv.actions[actions_n++] =
8240                                         dev_flow->dv.encap_decap->action;
8241                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8242                         break;
8243                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8244                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8245                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8246                                                            attr->transfer,
8247                                                            error))
8248                                 return -rte_errno;
8249                         dev_flow->dv.actions[actions_n++] =
8250                                         dev_flow->dv.encap_decap->action;
8251                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8252                         break;
8253                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8254                         /* Handle encap with preceding decap. */
8255                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8256                                 if (flow_dv_create_action_raw_encap
8257                                         (dev, actions, dev_flow, attr, error))
8258                                         return -rte_errno;
8259                                 dev_flow->dv.actions[actions_n++] =
8260                                         dev_flow->dv.encap_decap->action;
8261                         } else {
8262                                 /* Handle encap without preceding decap. */
8263                                 if (flow_dv_create_action_l2_encap
8264                                     (dev, actions, dev_flow, attr->transfer,
8265                                      error))
8266                                         return -rte_errno;
8267                                 dev_flow->dv.actions[actions_n++] =
8268                                         dev_flow->dv.encap_decap->action;
8269                         }
8270                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8271                         break;
8272                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8273                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8274                                 ;
8275                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8276                                 if (flow_dv_create_action_l2_decap
8277                                     (dev, dev_flow, attr->transfer, error))
8278                                         return -rte_errno;
8279                                 dev_flow->dv.actions[actions_n++] =
8280                                         dev_flow->dv.encap_decap->action;
8281                         }
8282                         /* If decap is followed by encap, handle it at encap. */
8283                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8284                         break;
8285                 case RTE_FLOW_ACTION_TYPE_JUMP:
8286                         jump_data = action->conf;
8287                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8288                                                        jump_data->group,
8289                                                        !!priv->fdb_def_rule,
8290                                                        &table, error);
8291                         if (ret)
8292                                 return ret;
8293                         tbl = flow_dv_tbl_resource_get(dev, table,
8294                                                        attr->egress,
8295                                                        attr->transfer, error);
8296                         if (!tbl)
8297                                 return rte_flow_error_set
8298                                                 (error, errno,
8299                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8300                                                  NULL,
8301                                                  "cannot create jump action.");
8302                         if (flow_dv_jump_tbl_resource_register
8303                             (dev, tbl, dev_flow, error)) {
8304                                 flow_dv_tbl_resource_release(dev, tbl);
8305                                 return rte_flow_error_set
8306                                                 (error, errno,
8307                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8308                                                  NULL,
8309                                                  "cannot create jump action.");
8310                         }
8311                         dev_flow->dv.actions[actions_n++] =
8312                                         dev_flow->dv.jump->action;
8313                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8314                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8315                         break;
8316                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8317                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8318                         if (flow_dv_convert_action_modify_mac
8319                                         (mhdr_res, actions, error))
8320                                 return -rte_errno;
8321                         action_flags |= actions->type ==
8322                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8323                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8324                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8325                         break;
8326                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8327                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8328                         if (flow_dv_convert_action_modify_ipv4
8329                                         (mhdr_res, actions, error))
8330                                 return -rte_errno;
8331                         action_flags |= actions->type ==
8332                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8333                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8334                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8335                         break;
8336                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8337                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8338                         if (flow_dv_convert_action_modify_ipv6
8339                                         (mhdr_res, actions, error))
8340                                 return -rte_errno;
8341                         action_flags |= actions->type ==
8342                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8343                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8344                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8345                         break;
8346                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8347                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8348                         if (flow_dv_convert_action_modify_tp
8349                                         (mhdr_res, actions, items,
8350                                          &flow_attr, dev_flow, !!(action_flags &
8351                                          MLX5_FLOW_ACTION_DECAP), error))
8352                                 return -rte_errno;
8353                         action_flags |= actions->type ==
8354                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8355                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8356                                         MLX5_FLOW_ACTION_SET_TP_DST;
8357                         break;
8358                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8359                         if (flow_dv_convert_action_modify_dec_ttl
8360                                         (mhdr_res, items, &flow_attr, dev_flow,
8361                                          !!(action_flags &
8362                                          MLX5_FLOW_ACTION_DECAP), error))
8363                                 return -rte_errno;
8364                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8365                         break;
8366                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8367                         if (flow_dv_convert_action_modify_ttl
8368                                         (mhdr_res, actions, items, &flow_attr,
8369                                          dev_flow, !!(action_flags &
8370                                          MLX5_FLOW_ACTION_DECAP), error))
8371                                 return -rte_errno;
8372                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8373                         break;
8374                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8375                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8376                         if (flow_dv_convert_action_modify_tcp_seq
8377                                         (mhdr_res, actions, error))
8378                                 return -rte_errno;
8379                         action_flags |= actions->type ==
8380                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8381                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8382                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8383                         break;
8384
8385                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8386                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8387                         if (flow_dv_convert_action_modify_tcp_ack
8388                                         (mhdr_res, actions, error))
8389                                 return -rte_errno;
8390                         action_flags |= actions->type ==
8391                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8392                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8393                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8394                         break;
8395                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8396                         if (flow_dv_convert_action_set_reg
8397                                         (mhdr_res, actions, error))
8398                                 return -rte_errno;
8399                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8400                         break;
8401                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8402                         if (flow_dv_convert_action_copy_mreg
8403                                         (dev, mhdr_res, actions, error))
8404                                 return -rte_errno;
8405                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8406                         break;
8407                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8408                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8409                         dev_flow->handle->fate_action =
8410                                         MLX5_FLOW_FATE_DEFAULT_MISS;
8411                         break;
8412                 case RTE_FLOW_ACTION_TYPE_METER:
8413                         mtr = actions->conf;
8414                         if (!flow->meter) {
8415                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8416                                                             attr, error);
8417                                 if (!fm)
8418                                         return rte_flow_error_set(error,
8419                                                 rte_errno,
8420                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8421                                                 NULL,
8422                                                 "meter not found "
8423                                                 "or invalid parameters");
8424                                 flow->meter = fm->idx;
8425                         }
8426                         /* Set the meter action. */
8427                         if (!fm) {
8428                                 fm = mlx5_ipool_get(priv->sh->ipool
8429                                                 [MLX5_IPOOL_MTR], flow->meter);
8430                                 if (!fm)
8431                                         return rte_flow_error_set(error,
8432                                                 rte_errno,
8433                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8434                                                 NULL,
8435                                                 "meter not found "
8436                                                 "or invalid parameters");
8437                         }
8438                         dev_flow->dv.actions[actions_n++] =
8439                                 fm->mfts->meter_action;
8440                         action_flags |= MLX5_FLOW_ACTION_METER;
8441                         break;
8442                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8443                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8444                                                               actions, error))
8445                                 return -rte_errno;
8446                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8447                         break;
8448                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8449                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8450                                                               actions, error))
8451                                 return -rte_errno;
8452                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8453                         break;
8454                 case RTE_FLOW_ACTION_TYPE_END:
8455                         actions_end = true;
8456                         if (mhdr_res->actions_num) {
8457                                 /* create modify action if needed. */
8458                                 if (flow_dv_modify_hdr_resource_register
8459                                         (dev, mhdr_res, dev_flow, error))
8460                                         return -rte_errno;
8461                                 dev_flow->dv.actions[modify_action_position] =
8462                                         handle->dvh.modify_hdr->action;
8463                         }
8464                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8465                                 flow->counter =
8466                                         flow_dv_translate_create_counter(dev,
8467                                                 dev_flow, count, age);
8468
8469                                 if (!flow->counter)
8470                                         return rte_flow_error_set
8471                                                 (error, rte_errno,
8472                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8473                                                 NULL,
8474                                                 "cannot create counter"
8475                                                 " object.");
8476                                 dev_flow->dv.actions[actions_n++] =
8477                                           (flow_dv_counter_get_by_idx(dev,
8478                                           flow->counter, NULL))->action;
8479                         }
8480                         break;
8481                 default:
8482                         break;
8483                 }
8484                 if (mhdr_res->actions_num &&
8485                     modify_action_position == UINT32_MAX)
8486                         modify_action_position = actions_n++;
8487         }
8488         dev_flow->dv.actions_n = actions_n;
8489         dev_flow->act_flags = action_flags;
8490         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8491                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8492                 int item_type = items->type;
8493
8494                 if (!mlx5_flow_os_item_supported(item_type))
8495                         return rte_flow_error_set(error, ENOTSUP,
8496                                                   RTE_FLOW_ERROR_TYPE_ITEM,
8497                                                   NULL, "item not supported");
8498                 switch (item_type) {
8499                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8500                         flow_dv_translate_item_port_id(dev, match_mask,
8501                                                        match_value, items);
8502                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8503                         break;
8504                 case RTE_FLOW_ITEM_TYPE_ETH:
8505                         flow_dv_translate_item_eth(match_mask, match_value,
8506                                                    items, tunnel,
8507                                                    dev_flow->dv.group);
8508                         matcher.priority = action_flags &
8509                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
8510                                         !dev_flow->external ?
8511                                         MLX5_PRIORITY_MAP_L3 :
8512                                         MLX5_PRIORITY_MAP_L2;
8513                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8514                                              MLX5_FLOW_LAYER_OUTER_L2;
8515                         break;
8516                 case RTE_FLOW_ITEM_TYPE_VLAN:
8517                         flow_dv_translate_item_vlan(dev_flow,
8518                                                     match_mask, match_value,
8519                                                     items, tunnel,
8520                                                     dev_flow->dv.group);
8521                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8522                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8523                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8524                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8525                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8526                         break;
8527                 case RTE_FLOW_ITEM_TYPE_IPV4:
8528                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8529                                                   &item_flags, &tunnel);
8530                         flow_dv_translate_item_ipv4(match_mask, match_value,
8531                                                     items, item_flags, tunnel,
8532                                                     dev_flow->dv.group);
8533                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8534                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8535                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8536                         if (items->mask != NULL &&
8537                             ((const struct rte_flow_item_ipv4 *)
8538                              items->mask)->hdr.next_proto_id) {
8539                                 next_protocol =
8540                                         ((const struct rte_flow_item_ipv4 *)
8541                                          (items->spec))->hdr.next_proto_id;
8542                                 next_protocol &=
8543                                         ((const struct rte_flow_item_ipv4 *)
8544                                          (items->mask))->hdr.next_proto_id;
8545                         } else {
8546                                 /* Reset for inner layer. */
8547                                 next_protocol = 0xff;
8548                         }
8549                         break;
8550                 case RTE_FLOW_ITEM_TYPE_IPV6:
8551                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8552                                                   &item_flags, &tunnel);
8553                         flow_dv_translate_item_ipv6(match_mask, match_value,
8554                                                     items, item_flags, tunnel,
8555                                                     dev_flow->dv.group);
8556                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8557                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8558                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8559                         if (items->mask != NULL &&
8560                             ((const struct rte_flow_item_ipv6 *)
8561                              items->mask)->hdr.proto) {
8562                                 next_protocol =
8563                                         ((const struct rte_flow_item_ipv6 *)
8564                                          items->spec)->hdr.proto;
8565                                 next_protocol &=
8566                                         ((const struct rte_flow_item_ipv6 *)
8567                                          items->mask)->hdr.proto;
8568                         } else {
8569                                 /* Reset for inner layer. */
8570                                 next_protocol = 0xff;
8571                         }
8572                         break;
8573                 case RTE_FLOW_ITEM_TYPE_TCP:
8574                         flow_dv_translate_item_tcp(match_mask, match_value,
8575                                                    items, tunnel);
8576                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8577                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8578                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8579                         break;
8580                 case RTE_FLOW_ITEM_TYPE_UDP:
8581                         flow_dv_translate_item_udp(match_mask, match_value,
8582                                                    items, tunnel);
8583                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8584                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8585                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8586                         break;
8587                 case RTE_FLOW_ITEM_TYPE_GRE:
8588                         flow_dv_translate_item_gre(match_mask, match_value,
8589                                                    items, tunnel);
8590                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8591                         last_item = MLX5_FLOW_LAYER_GRE;
8592                         break;
8593                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8594                         flow_dv_translate_item_gre_key(match_mask,
8595                                                        match_value, items);
8596                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8597                         break;
8598                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8599                         flow_dv_translate_item_nvgre(match_mask, match_value,
8600                                                      items, tunnel);
8601                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8602                         last_item = MLX5_FLOW_LAYER_GRE;
8603                         break;
8604                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8605                         flow_dv_translate_item_vxlan(match_mask, match_value,
8606                                                      items, tunnel);
8607                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8608                         last_item = MLX5_FLOW_LAYER_VXLAN;
8609                         break;
8610                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8611                         flow_dv_translate_item_vxlan_gpe(match_mask,
8612                                                          match_value, items,
8613                                                          tunnel);
8614                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8615                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8616                         break;
8617                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8618                         flow_dv_translate_item_geneve(match_mask, match_value,
8619                                                       items, tunnel);
8620                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8621                         last_item = MLX5_FLOW_LAYER_GENEVE;
8622                         break;
8623                 case RTE_FLOW_ITEM_TYPE_MPLS:
8624                         flow_dv_translate_item_mpls(match_mask, match_value,
8625                                                     items, last_item, tunnel);
8626                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8627                         last_item = MLX5_FLOW_LAYER_MPLS;
8628                         break;
8629                 case RTE_FLOW_ITEM_TYPE_MARK:
8630                         flow_dv_translate_item_mark(dev, match_mask,
8631                                                     match_value, items);
8632                         last_item = MLX5_FLOW_ITEM_MARK;
8633                         break;
8634                 case RTE_FLOW_ITEM_TYPE_META:
8635                         flow_dv_translate_item_meta(dev, match_mask,
8636                                                     match_value, attr, items);
8637                         last_item = MLX5_FLOW_ITEM_METADATA;
8638                         break;
8639                 case RTE_FLOW_ITEM_TYPE_ICMP:
8640                         flow_dv_translate_item_icmp(match_mask, match_value,
8641                                                     items, tunnel);
8642                         last_item = MLX5_FLOW_LAYER_ICMP;
8643                         break;
8644                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8645                         flow_dv_translate_item_icmp6(match_mask, match_value,
8646                                                       items, tunnel);
8647                         last_item = MLX5_FLOW_LAYER_ICMP6;
8648                         break;
8649                 case RTE_FLOW_ITEM_TYPE_TAG:
8650                         flow_dv_translate_item_tag(dev, match_mask,
8651                                                    match_value, items);
8652                         last_item = MLX5_FLOW_ITEM_TAG;
8653                         break;
8654                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8655                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8656                                                         match_value, items);
8657                         last_item = MLX5_FLOW_ITEM_TAG;
8658                         break;
8659                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8660                         flow_dv_translate_item_tx_queue(dev, match_mask,
8661                                                         match_value,
8662                                                         items);
8663                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8664                         break;
8665                 case RTE_FLOW_ITEM_TYPE_GTP:
8666                         flow_dv_translate_item_gtp(match_mask, match_value,
8667                                                    items, tunnel);
8668                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8669                         last_item = MLX5_FLOW_LAYER_GTP;
8670                         break;
8671                 case RTE_FLOW_ITEM_TYPE_ECPRI:
8672                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
8673                                 /* Create it only the first time to be used. */
8674                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
8675                                 if (ret)
8676                                         return rte_flow_error_set
8677                                                 (error, -ret,
8678                                                 RTE_FLOW_ERROR_TYPE_ITEM,
8679                                                 NULL,
8680                                                 "cannot create eCPRI parser");
8681                         }
8682                         /* Adjust the length matcher and device flow value. */
8683                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8684                         dev_flow->dv.value.size =
8685                                         MLX5_ST_SZ_BYTES(fte_match_param);
8686                         flow_dv_translate_item_ecpri(dev, match_mask,
8687                                                      match_value, items);
8688                         /* No other protocol should follow eCPRI layer. */
8689                         last_item = MLX5_FLOW_LAYER_ECPRI;
8690                         break;
8691                 default:
8692                         break;
8693                 }
8694                 item_flags |= last_item;
8695         }
8696         /*
8697          * When E-Switch mode is enabled, we have two cases where we need to
8698          * set the source port manually.
8699          * The first one, is in case of Nic steering rule, and the second is
8700          * E-Switch rule where no port_id item was found. In both cases
8701          * the source port is set according the current port in use.
8702          */
8703         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8704             (priv->representor || priv->master)) {
8705                 if (flow_dv_translate_item_port_id(dev, match_mask,
8706                                                    match_value, NULL))
8707                         return -rte_errno;
8708         }
8709 #ifdef RTE_LIBRTE_MLX5_DEBUG
8710         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8711                                               dev_flow->dv.value.buf));
8712 #endif
8713         /*
8714          * Layers may be already initialized from prefix flow if this dev_flow
8715          * is the suffix flow.
8716          */
8717         handle->layers |= item_flags;
8718         if (action_flags & MLX5_FLOW_ACTION_RSS)
8719                 flow_dv_hashfields_set(dev_flow, rss_desc);
8720         /* Register matcher. */
8721         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8722                                     matcher.mask.size);
8723         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8724                                                      matcher.priority);
8725         /* reserved field no needs to be set to 0 here. */
8726         tbl_key.domain = attr->transfer;
8727         tbl_key.direction = attr->egress;
8728         tbl_key.table_id = dev_flow->dv.group;
8729         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8730                 return -rte_errno;
8731         return 0;
8732 }
8733
8734 /**
8735  * Apply the flow to the NIC, lock free,
8736  * (mutex should be acquired by caller).
8737  *
8738  * @param[in] dev
8739  *   Pointer to the Ethernet device structure.
8740  * @param[in, out] flow
8741  *   Pointer to flow structure.
8742  * @param[out] error
8743  *   Pointer to error structure.
8744  *
8745  * @return
8746  *   0 on success, a negative errno value otherwise and rte_errno is set.
8747  */
8748 static int
8749 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8750                 struct rte_flow_error *error)
8751 {
8752         struct mlx5_flow_dv_workspace *dv;
8753         struct mlx5_flow_handle *dh;
8754         struct mlx5_flow_handle_dv *dv_h;
8755         struct mlx5_flow *dev_flow;
8756         struct mlx5_priv *priv = dev->data->dev_private;
8757         uint32_t handle_idx;
8758         int n;
8759         int err;
8760         int idx;
8761
8762         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8763                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8764                 dv = &dev_flow->dv;
8765                 dh = dev_flow->handle;
8766                 dv_h = &dh->dvh;
8767                 n = dv->actions_n;
8768                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8769                         if (dv->transfer) {
8770                                 dv->actions[n++] = priv->sh->esw_drop_action;
8771                         } else {
8772                                 struct mlx5_hrxq *drop_hrxq;
8773                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8774                                 if (!drop_hrxq) {
8775                                         rte_flow_error_set
8776                                                 (error, errno,
8777                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8778                                                  NULL,
8779                                                  "cannot get drop hash queue");
8780                                         goto error;
8781                                 }
8782                                 /*
8783                                  * Drop queues will be released by the specify
8784                                  * mlx5_hrxq_drop_release() function. Assign
8785                                  * the special index to hrxq to mark the queue
8786                                  * has been allocated.
8787                                  */
8788                                 dh->rix_hrxq = UINT32_MAX;
8789                                 dv->actions[n++] = drop_hrxq->action;
8790                         }
8791                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8792                         struct mlx5_hrxq *hrxq;
8793                         uint32_t hrxq_idx;
8794                         struct mlx5_flow_rss_desc *rss_desc =
8795                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8796                                 [!!priv->flow_nested_idx];
8797
8798                         MLX5_ASSERT(rss_desc->queue_num);
8799                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8800                                                  MLX5_RSS_HASH_KEY_LEN,
8801                                                  dev_flow->hash_fields,
8802                                                  rss_desc->queue,
8803                                                  rss_desc->queue_num);
8804                         if (!hrxq_idx) {
8805                                 hrxq_idx = mlx5_hrxq_new
8806                                                 (dev, rss_desc->key,
8807                                                 MLX5_RSS_HASH_KEY_LEN,
8808                                                 dev_flow->hash_fields,
8809                                                 rss_desc->queue,
8810                                                 rss_desc->queue_num,
8811                                                 !!(dh->layers &
8812                                                 MLX5_FLOW_LAYER_TUNNEL));
8813                         }
8814                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8815                                               hrxq_idx);
8816                         if (!hrxq) {
8817                                 rte_flow_error_set
8818                                         (error, rte_errno,
8819                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8820                                          "cannot get hash queue");
8821                                 goto error;
8822                         }
8823                         dh->rix_hrxq = hrxq_idx;
8824                         dv->actions[n++] = hrxq->action;
8825                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8826                         if (flow_dv_default_miss_resource_register
8827                                         (dev, error)) {
8828                                 rte_flow_error_set
8829                                         (error, rte_errno,
8830                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8831                                          "cannot create default miss resource");
8832                                 goto error_default_miss;
8833                         }
8834                         dh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;
8835                         dv->actions[n++] = priv->sh->default_miss.action;
8836                 }
8837                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8838                                                (void *)&dv->value, n,
8839                                                dv->actions, &dh->drv_flow);
8840                 if (err) {
8841                         rte_flow_error_set(error, errno,
8842                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8843                                            NULL,
8844                                            "hardware refuses to create flow");
8845                         goto error;
8846                 }
8847                 if (priv->vmwa_context &&
8848                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8849                         /*
8850                          * The rule contains the VLAN pattern.
8851                          * For VF we are going to create VLAN
8852                          * interface to make hypervisor set correct
8853                          * e-Switch vport context.
8854                          */
8855                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8856                 }
8857         }
8858         return 0;
8859 error:
8860         if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8861                 flow_dv_default_miss_resource_release(dev);
8862 error_default_miss:
8863         err = rte_errno; /* Save rte_errno before cleanup. */
8864         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8865                        handle_idx, dh, next) {
8866                 /* hrxq is union, don't clear it if the flag is not set. */
8867                 if (dh->rix_hrxq) {
8868                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8869                                 mlx5_hrxq_drop_release(dev);
8870                                 dh->rix_hrxq = 0;
8871                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8872                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8873                                 dh->rix_hrxq = 0;
8874                         }
8875                 }
8876                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8877                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8878         }
8879         rte_errno = err; /* Restore rte_errno. */
8880         return -rte_errno;
8881 }
8882
8883 /**
8884  * Release the flow matcher.
8885  *
8886  * @param dev
8887  *   Pointer to Ethernet device.
8888  * @param handle
8889  *   Pointer to mlx5_flow_handle.
8890  *
8891  * @return
8892  *   1 while a reference on it exists, 0 when freed.
8893  */
8894 static int
8895 flow_dv_matcher_release(struct rte_eth_dev *dev,
8896                         struct mlx5_flow_handle *handle)
8897 {
8898         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8899
8900         MLX5_ASSERT(matcher->matcher_object);
8901         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8902                 dev->data->port_id, (void *)matcher,
8903                 rte_atomic32_read(&matcher->refcnt));
8904         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8905                 claim_zero(mlx5_flow_os_destroy_flow_matcher
8906                            (matcher->matcher_object));
8907                 LIST_REMOVE(matcher, next);
8908                 /* table ref-- in release interface. */
8909                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8910                 mlx5_free(matcher);
8911                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8912                         dev->data->port_id, (void *)matcher);
8913                 return 0;
8914         }
8915         return 1;
8916 }
8917
8918 /**
8919  * Release an encap/decap resource.
8920  *
8921  * @param dev
8922  *   Pointer to Ethernet device.
8923  * @param handle
8924  *   Pointer to mlx5_flow_handle.
8925  *
8926  * @return
8927  *   1 while a reference on it exists, 0 when freed.
8928  */
8929 static int
8930 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8931                                      struct mlx5_flow_handle *handle)
8932 {
8933         struct mlx5_priv *priv = dev->data->dev_private;
8934         uint32_t idx = handle->dvh.rix_encap_decap;
8935         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8936
8937         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8938                          idx);
8939         if (!cache_resource)
8940                 return 0;
8941         MLX5_ASSERT(cache_resource->action);
8942         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8943                 (void *)cache_resource,
8944                 rte_atomic32_read(&cache_resource->refcnt));
8945         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8946                 claim_zero(mlx5_flow_os_destroy_flow_action
8947                                                 (cache_resource->action));
8948                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8949                              &priv->sh->encaps_decaps, idx,
8950                              cache_resource, next);
8951                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8952                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8953                         (void *)cache_resource);
8954                 return 0;
8955         }
8956         return 1;
8957 }
8958
8959 /**
8960  * Release an jump to table action resource.
8961  *
8962  * @param dev
8963  *   Pointer to Ethernet device.
8964  * @param handle
8965  *   Pointer to mlx5_flow_handle.
8966  *
8967  * @return
8968  *   1 while a reference on it exists, 0 when freed.
8969  */
8970 static int
8971 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8972                                   struct mlx5_flow_handle *handle)
8973 {
8974         struct mlx5_priv *priv = dev->data->dev_private;
8975         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8976         struct mlx5_flow_tbl_data_entry *tbl_data;
8977
8978         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8979                              handle->rix_jump);
8980         if (!tbl_data)
8981                 return 0;
8982         cache_resource = &tbl_data->jump;
8983         MLX5_ASSERT(cache_resource->action);
8984         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8985                 (void *)cache_resource,
8986                 rte_atomic32_read(&cache_resource->refcnt));
8987         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8988                 claim_zero(mlx5_flow_os_destroy_flow_action
8989                                                 (cache_resource->action));
8990                 /* jump action memory free is inside the table release. */
8991                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8992                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8993                         (void *)cache_resource);
8994                 return 0;
8995         }
8996         return 1;
8997 }
8998
8999 /**
9000  * Release a default miss resource.
9001  *
9002  * @param dev
9003  *   Pointer to Ethernet device.
9004  * @return
9005  *   1 while a reference on it exists, 0 when freed.
9006  */
9007 static int
9008 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9009 {
9010         struct mlx5_priv *priv = dev->data->dev_private;
9011         struct mlx5_dev_ctx_shared *sh = priv->sh;
9012         struct mlx5_flow_default_miss_resource *cache_resource =
9013                         &sh->default_miss;
9014
9015         MLX5_ASSERT(cache_resource->action);
9016         DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9017                         (void *)cache_resource->action,
9018                         rte_atomic32_read(&cache_resource->refcnt));
9019         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9020                 claim_zero(mlx5_glue->destroy_flow_action
9021                                 (cache_resource->action));
9022                 DRV_LOG(DEBUG, "default miss resource %p: removed",
9023                                 (void *)cache_resource->action);
9024                 return 0;
9025         }
9026         return 1;
9027 }
9028
9029 /**
9030  * Release a modify-header resource.
9031  *
9032  * @param handle
9033  *   Pointer to mlx5_flow_handle.
9034  *
9035  * @return
9036  *   1 while a reference on it exists, 0 when freed.
9037  */
9038 static int
9039 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9040 {
9041         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9042                                                         handle->dvh.modify_hdr;
9043
9044         MLX5_ASSERT(cache_resource->action);
9045         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9046                 (void *)cache_resource,
9047                 rte_atomic32_read(&cache_resource->refcnt));
9048         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9049                 claim_zero(mlx5_flow_os_destroy_flow_action
9050                                                 (cache_resource->action));
9051                 LIST_REMOVE(cache_resource, next);
9052                 mlx5_free(cache_resource);
9053                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9054                         (void *)cache_resource);
9055                 return 0;
9056         }
9057         return 1;
9058 }
9059
9060 /**
9061  * Release port ID action resource.
9062  *
9063  * @param dev
9064  *   Pointer to Ethernet device.
9065  * @param handle
9066  *   Pointer to mlx5_flow_handle.
9067  *
9068  * @return
9069  *   1 while a reference on it exists, 0 when freed.
9070  */
9071 static int
9072 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9073                                         struct mlx5_flow_handle *handle)
9074 {
9075         struct mlx5_priv *priv = dev->data->dev_private;
9076         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9077         uint32_t idx = handle->rix_port_id_action;
9078
9079         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9080                                         idx);
9081         if (!cache_resource)
9082                 return 0;
9083         MLX5_ASSERT(cache_resource->action);
9084         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9085                 (void *)cache_resource,
9086                 rte_atomic32_read(&cache_resource->refcnt));
9087         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9088                 claim_zero(mlx5_flow_os_destroy_flow_action
9089                                                 (cache_resource->action));
9090                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9091                              &priv->sh->port_id_action_list, idx,
9092                              cache_resource, next);
9093                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9094                 DRV_LOG(DEBUG, "port id action resource %p: removed",
9095                         (void *)cache_resource);
9096                 return 0;
9097         }
9098         return 1;
9099 }
9100
9101 /**
9102  * Release push vlan action resource.
9103  *
9104  * @param dev
9105  *   Pointer to Ethernet device.
9106  * @param handle
9107  *   Pointer to mlx5_flow_handle.
9108  *
9109  * @return
9110  *   1 while a reference on it exists, 0 when freed.
9111  */
9112 static int
9113 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9114                                           struct mlx5_flow_handle *handle)
9115 {
9116         struct mlx5_priv *priv = dev->data->dev_private;
9117         uint32_t idx = handle->dvh.rix_push_vlan;
9118         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9119
9120         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9121                                         idx);
9122         if (!cache_resource)
9123                 return 0;
9124         MLX5_ASSERT(cache_resource->action);
9125         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9126                 (void *)cache_resource,
9127                 rte_atomic32_read(&cache_resource->refcnt));
9128         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9129                 claim_zero(mlx5_flow_os_destroy_flow_action
9130                                                 (cache_resource->action));
9131                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9132                              &priv->sh->push_vlan_action_list, idx,
9133                              cache_resource, next);
9134                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9135                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9136                         (void *)cache_resource);
9137                 return 0;
9138         }
9139         return 1;
9140 }
9141
9142 /**
9143  * Release the fate resource.
9144  *
9145  * @param dev
9146  *   Pointer to Ethernet device.
9147  * @param handle
9148  *   Pointer to mlx5_flow_handle.
9149  */
9150 static void
9151 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9152                                struct mlx5_flow_handle *handle)
9153 {
9154         if (!handle->rix_fate)
9155                 return;
9156         switch (handle->fate_action) {
9157         case MLX5_FLOW_FATE_DROP:
9158                 mlx5_hrxq_drop_release(dev);
9159                 break;
9160         case MLX5_FLOW_FATE_QUEUE:
9161                 mlx5_hrxq_release(dev, handle->rix_hrxq);
9162                 break;
9163         case MLX5_FLOW_FATE_JUMP:
9164                 flow_dv_jump_tbl_resource_release(dev, handle);
9165                 break;
9166         case MLX5_FLOW_FATE_PORT_ID:
9167                 flow_dv_port_id_action_resource_release(dev, handle);
9168                 break;
9169         case MLX5_FLOW_FATE_DEFAULT_MISS:
9170                 flow_dv_default_miss_resource_release(dev);
9171                 break;
9172         default:
9173                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9174                 break;
9175         }
9176         handle->rix_fate = 0;
9177 }
9178
9179 /**
9180  * Remove the flow from the NIC but keeps it in memory.
9181  * Lock free, (mutex should be acquired by caller).
9182  *
9183  * @param[in] dev
9184  *   Pointer to Ethernet device.
9185  * @param[in, out] flow
9186  *   Pointer to flow structure.
9187  */
9188 static void
9189 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9190 {
9191         struct mlx5_flow_handle *dh;
9192         uint32_t handle_idx;
9193         struct mlx5_priv *priv = dev->data->dev_private;
9194
9195         if (!flow)
9196                 return;
9197         handle_idx = flow->dev_handles;
9198         while (handle_idx) {
9199                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9200                                     handle_idx);
9201                 if (!dh)
9202                         return;
9203                 if (dh->drv_flow) {
9204                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9205                         dh->drv_flow = NULL;
9206                 }
9207                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9208                     dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9209                     dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9210                         flow_dv_fate_resource_release(dev, dh);
9211                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9212                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9213                 handle_idx = dh->next.next;
9214         }
9215 }
9216
9217 /**
9218  * Remove the flow from the NIC and the memory.
9219  * Lock free, (mutex should be acquired by caller).
9220  *
9221  * @param[in] dev
9222  *   Pointer to the Ethernet device structure.
9223  * @param[in, out] flow
9224  *   Pointer to flow structure.
9225  */
9226 static void
9227 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9228 {
9229         struct mlx5_flow_handle *dev_handle;
9230         struct mlx5_priv *priv = dev->data->dev_private;
9231
9232         if (!flow)
9233                 return;
9234         __flow_dv_remove(dev, flow);
9235         if (flow->counter) {
9236                 flow_dv_counter_release(dev, flow->counter);
9237                 flow->counter = 0;
9238         }
9239         if (flow->meter) {
9240                 struct mlx5_flow_meter *fm;
9241
9242                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9243                                     flow->meter);
9244                 if (fm)
9245                         mlx5_flow_meter_detach(fm);
9246                 flow->meter = 0;
9247         }
9248         while (flow->dev_handles) {
9249                 uint32_t tmp_idx = flow->dev_handles;
9250
9251                 dev_handle = mlx5_ipool_get(priv->sh->ipool
9252                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9253                 if (!dev_handle)
9254                         return;
9255                 flow->dev_handles = dev_handle->next.next;
9256                 if (dev_handle->dvh.matcher)
9257                         flow_dv_matcher_release(dev, dev_handle);
9258                 if (dev_handle->dvh.rix_encap_decap)
9259                         flow_dv_encap_decap_resource_release(dev, dev_handle);
9260                 if (dev_handle->dvh.modify_hdr)
9261                         flow_dv_modify_hdr_resource_release(dev_handle);
9262                 if (dev_handle->dvh.rix_push_vlan)
9263                         flow_dv_push_vlan_action_resource_release(dev,
9264                                                                   dev_handle);
9265                 if (dev_handle->dvh.rix_tag)
9266                         flow_dv_tag_release(dev,
9267                                             dev_handle->dvh.rix_tag);
9268                 flow_dv_fate_resource_release(dev, dev_handle);
9269                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9270                            tmp_idx);
9271         }
9272 }
9273
9274 /**
9275  * Query a dv flow  rule for its statistics via devx.
9276  *
9277  * @param[in] dev
9278  *   Pointer to Ethernet device.
9279  * @param[in] flow
9280  *   Pointer to the sub flow.
9281  * @param[out] data
9282  *   data retrieved by the query.
9283  * @param[out] error
9284  *   Perform verbose error reporting if not NULL.
9285  *
9286  * @return
9287  *   0 on success, a negative errno value otherwise and rte_errno is set.
9288  */
9289 static int
9290 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9291                     void *data, struct rte_flow_error *error)
9292 {
9293         struct mlx5_priv *priv = dev->data->dev_private;
9294         struct rte_flow_query_count *qc = data;
9295
9296         if (!priv->config.devx)
9297                 return rte_flow_error_set(error, ENOTSUP,
9298                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9299                                           NULL,
9300                                           "counters are not supported");
9301         if (flow->counter) {
9302                 uint64_t pkts, bytes;
9303                 struct mlx5_flow_counter *cnt;
9304
9305                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9306                                                  NULL);
9307                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9308                                                &bytes);
9309
9310                 if (err)
9311                         return rte_flow_error_set(error, -err,
9312                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9313                                         NULL, "cannot read counters");
9314                 qc->hits_set = 1;
9315                 qc->bytes_set = 1;
9316                 qc->hits = pkts - cnt->hits;
9317                 qc->bytes = bytes - cnt->bytes;
9318                 if (qc->reset) {
9319                         cnt->hits = pkts;
9320                         cnt->bytes = bytes;
9321                 }
9322                 return 0;
9323         }
9324         return rte_flow_error_set(error, EINVAL,
9325                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9326                                   NULL,
9327                                   "counters are not available");
9328 }
9329
9330 /**
9331  * Query a flow.
9332  *
9333  * @see rte_flow_query()
9334  * @see rte_flow_ops
9335  */
9336 static int
9337 flow_dv_query(struct rte_eth_dev *dev,
9338               struct rte_flow *flow __rte_unused,
9339               const struct rte_flow_action *actions __rte_unused,
9340               void *data __rte_unused,
9341               struct rte_flow_error *error __rte_unused)
9342 {
9343         int ret = -EINVAL;
9344
9345         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9346                 switch (actions->type) {
9347                 case RTE_FLOW_ACTION_TYPE_VOID:
9348                         break;
9349                 case RTE_FLOW_ACTION_TYPE_COUNT:
9350                         ret = flow_dv_query_count(dev, flow, data, error);
9351                         break;
9352                 default:
9353                         return rte_flow_error_set(error, ENOTSUP,
9354                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9355                                                   actions,
9356                                                   "action not supported");
9357                 }
9358         }
9359         return ret;
9360 }
9361
9362 /**
9363  * Destroy the meter table set.
9364  * Lock free, (mutex should be acquired by caller).
9365  *
9366  * @param[in] dev
9367  *   Pointer to Ethernet device.
9368  * @param[in] tbl
9369  *   Pointer to the meter table set.
9370  *
9371  * @return
9372  *   Always 0.
9373  */
9374 static int
9375 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9376                         struct mlx5_meter_domains_infos *tbl)
9377 {
9378         struct mlx5_priv *priv = dev->data->dev_private;
9379         struct mlx5_meter_domains_infos *mtd =
9380                                 (struct mlx5_meter_domains_infos *)tbl;
9381
9382         if (!mtd || !priv->config.dv_flow_en)
9383                 return 0;
9384         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9385                 claim_zero(mlx5_flow_os_destroy_flow
9386                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9387         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9388                 claim_zero(mlx5_flow_os_destroy_flow
9389                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9390         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9391                 claim_zero(mlx5_flow_os_destroy_flow
9392                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9393         if (mtd->egress.color_matcher)
9394                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9395                            (mtd->egress.color_matcher));
9396         if (mtd->egress.any_matcher)
9397                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9398                            (mtd->egress.any_matcher));
9399         if (mtd->egress.tbl)
9400                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9401         if (mtd->egress.sfx_tbl)
9402                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9403         if (mtd->ingress.color_matcher)
9404                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9405                            (mtd->ingress.color_matcher));
9406         if (mtd->ingress.any_matcher)
9407                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9408                            (mtd->ingress.any_matcher));
9409         if (mtd->ingress.tbl)
9410                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9411         if (mtd->ingress.sfx_tbl)
9412                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9413         if (mtd->transfer.color_matcher)
9414                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9415                            (mtd->transfer.color_matcher));
9416         if (mtd->transfer.any_matcher)
9417                 claim_zero(mlx5_flow_os_destroy_flow_matcher
9418                            (mtd->transfer.any_matcher));
9419         if (mtd->transfer.tbl)
9420                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9421         if (mtd->transfer.sfx_tbl)
9422                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9423         if (mtd->drop_actn)
9424                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9425         mlx5_free(mtd);
9426         return 0;
9427 }
9428
9429 /* Number of meter flow actions, count and jump or count and drop. */
9430 #define METER_ACTIONS 2
9431
9432 /**
9433  * Create specify domain meter table and suffix table.
9434  *
9435  * @param[in] dev
9436  *   Pointer to Ethernet device.
9437  * @param[in,out] mtb
9438  *   Pointer to DV meter table set.
9439  * @param[in] egress
9440  *   Table attribute.
9441  * @param[in] transfer
9442  *   Table attribute.
9443  * @param[in] color_reg_c_idx
9444  *   Reg C index for color match.
9445  *
9446  * @return
9447  *   0 on success, -1 otherwise and rte_errno is set.
9448  */
9449 static int
9450 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9451                            struct mlx5_meter_domains_infos *mtb,
9452                            uint8_t egress, uint8_t transfer,
9453                            uint32_t color_reg_c_idx)
9454 {
9455         struct mlx5_priv *priv = dev->data->dev_private;
9456         struct mlx5_dev_ctx_shared *sh = priv->sh;
9457         struct mlx5_flow_dv_match_params mask = {
9458                 .size = sizeof(mask.buf),
9459         };
9460         struct mlx5_flow_dv_match_params value = {
9461                 .size = sizeof(value.buf),
9462         };
9463         struct mlx5dv_flow_matcher_attr dv_attr = {
9464                 .type = IBV_FLOW_ATTR_NORMAL,
9465                 .priority = 0,
9466                 .match_criteria_enable = 0,
9467                 .match_mask = (void *)&mask,
9468         };
9469         void *actions[METER_ACTIONS];
9470         struct mlx5_meter_domain_info *dtb;
9471         struct rte_flow_error error;
9472         int i = 0;
9473         int ret;
9474
9475         if (transfer)
9476                 dtb = &mtb->transfer;
9477         else if (egress)
9478                 dtb = &mtb->egress;
9479         else
9480                 dtb = &mtb->ingress;
9481         /* Create the meter table with METER level. */
9482         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9483                                             egress, transfer, &error);
9484         if (!dtb->tbl) {
9485                 DRV_LOG(ERR, "Failed to create meter policer table.");
9486                 return -1;
9487         }
9488         /* Create the meter suffix table with SUFFIX level. */
9489         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9490                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9491                                             egress, transfer, &error);
9492         if (!dtb->sfx_tbl) {
9493                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9494                 return -1;
9495         }
9496         /* Create matchers, Any and Color. */
9497         dv_attr.priority = 3;
9498         dv_attr.match_criteria_enable = 0;
9499         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9500                                                &dtb->any_matcher);
9501         if (ret) {
9502                 DRV_LOG(ERR, "Failed to create meter"
9503                              " policer default matcher.");
9504                 goto error_exit;
9505         }
9506         dv_attr.priority = 0;
9507         dv_attr.match_criteria_enable =
9508                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9509         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9510                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9511         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9512                                                &dtb->color_matcher);
9513         if (ret) {
9514                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9515                 goto error_exit;
9516         }
9517         if (mtb->count_actns[RTE_MTR_DROPPED])
9518                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9519         actions[i++] = mtb->drop_actn;
9520         /* Default rule: lowest priority, match any, actions: drop. */
9521         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9522                                        actions,
9523                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
9524         if (ret) {
9525                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9526                 goto error_exit;
9527         }
9528         return 0;
9529 error_exit:
9530         return -1;
9531 }
9532
9533 /**
9534  * Create the needed meter and suffix tables.
9535  * Lock free, (mutex should be acquired by caller).
9536  *
9537  * @param[in] dev
9538  *   Pointer to Ethernet device.
9539  * @param[in] fm
9540  *   Pointer to the flow meter.
9541  *
9542  * @return
9543  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9544  */
9545 static struct mlx5_meter_domains_infos *
9546 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9547                        const struct mlx5_flow_meter *fm)
9548 {
9549         struct mlx5_priv *priv = dev->data->dev_private;
9550         struct mlx5_meter_domains_infos *mtb;
9551         int ret;
9552         int i;
9553
9554         if (!priv->mtr_en) {
9555                 rte_errno = ENOTSUP;
9556                 return NULL;
9557         }
9558         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9559         if (!mtb) {
9560                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9561                 return NULL;
9562         }
9563         /* Create meter count actions */
9564         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9565                 struct mlx5_flow_counter *cnt;
9566                 if (!fm->policer_stats.cnt[i])
9567                         continue;
9568                 cnt = flow_dv_counter_get_by_idx(dev,
9569                       fm->policer_stats.cnt[i], NULL);
9570                 mtb->count_actns[i] = cnt->action;
9571         }
9572         /* Create drop action. */
9573         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9574         if (ret) {
9575                 DRV_LOG(ERR, "Failed to create drop action.");
9576                 goto error_exit;
9577         }
9578         /* Egress meter table. */
9579         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9580         if (ret) {
9581                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9582                 goto error_exit;
9583         }
9584         /* Ingress meter table. */
9585         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9586         if (ret) {
9587                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9588                 goto error_exit;
9589         }
9590         /* FDB meter table. */
9591         if (priv->config.dv_esw_en) {
9592                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9593                                                  priv->mtr_color_reg);
9594                 if (ret) {
9595                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9596                         goto error_exit;
9597                 }
9598         }
9599         return mtb;
9600 error_exit:
9601         flow_dv_destroy_mtr_tbl(dev, mtb);
9602         return NULL;
9603 }
9604
9605 /**
9606  * Destroy domain policer rule.
9607  *
9608  * @param[in] dt
9609  *   Pointer to domain table.
9610  */
9611 static void
9612 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9613 {
9614         int i;
9615
9616         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9617                 if (dt->policer_rules[i]) {
9618                         claim_zero(mlx5_flow_os_destroy_flow
9619                                    (dt->policer_rules[i]));
9620                         dt->policer_rules[i] = NULL;
9621                 }
9622         }
9623         if (dt->jump_actn) {
9624                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9625                 dt->jump_actn = NULL;
9626         }
9627 }
9628
9629 /**
9630  * Destroy policer rules.
9631  *
9632  * @param[in] dev
9633  *   Pointer to Ethernet device.
9634  * @param[in] fm
9635  *   Pointer to flow meter structure.
9636  * @param[in] attr
9637  *   Pointer to flow attributes.
9638  *
9639  * @return
9640  *   Always 0.
9641  */
9642 static int
9643 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9644                               const struct mlx5_flow_meter *fm,
9645                               const struct rte_flow_attr *attr)
9646 {
9647         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9648
9649         if (!mtb)
9650                 return 0;
9651         if (attr->egress)
9652                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9653         if (attr->ingress)
9654                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9655         if (attr->transfer)
9656                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9657         return 0;
9658 }
9659
9660 /**
9661  * Create specify domain meter policer rule.
9662  *
9663  * @param[in] fm
9664  *   Pointer to flow meter structure.
9665  * @param[in] mtb
9666  *   Pointer to DV meter table set.
9667  * @param[in] mtr_reg_c
9668  *   Color match REG_C.
9669  *
9670  * @return
9671  *   0 on success, -1 otherwise.
9672  */
9673 static int
9674 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9675                                     struct mlx5_meter_domain_info *dtb,
9676                                     uint8_t mtr_reg_c)
9677 {
9678         struct mlx5_flow_dv_match_params matcher = {
9679                 .size = sizeof(matcher.buf),
9680         };
9681         struct mlx5_flow_dv_match_params value = {
9682                 .size = sizeof(value.buf),
9683         };
9684         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9685         void *actions[METER_ACTIONS];
9686         int i;
9687         int ret = 0;
9688
9689         /* Create jump action. */
9690         if (!dtb->jump_actn)
9691                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9692                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9693         if (ret) {
9694                 DRV_LOG(ERR, "Failed to create policer jump action.");
9695                 goto error;
9696         }
9697         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9698                 int j = 0;
9699
9700                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9701                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9702                 if (mtb->count_actns[i])
9703                         actions[j++] = mtb->count_actns[i];
9704                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9705                         actions[j++] = mtb->drop_actn;
9706                 else
9707                         actions[j++] = dtb->jump_actn;
9708                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9709                                                (void *)&value, j, actions,
9710                                                &dtb->policer_rules[i]);
9711                 if (ret) {
9712                         DRV_LOG(ERR, "Failed to create policer rule.");
9713                         goto error;
9714                 }
9715         }
9716         return 0;
9717 error:
9718         rte_errno = errno;
9719         return -1;
9720 }
9721
9722 /**
9723  * Create policer rules.
9724  *
9725  * @param[in] dev
9726  *   Pointer to Ethernet device.
9727  * @param[in] fm
9728  *   Pointer to flow meter structure.
9729  * @param[in] attr
9730  *   Pointer to flow attributes.
9731  *
9732  * @return
9733  *   0 on success, -1 otherwise.
9734  */
9735 static int
9736 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9737                              struct mlx5_flow_meter *fm,
9738                              const struct rte_flow_attr *attr)
9739 {
9740         struct mlx5_priv *priv = dev->data->dev_private;
9741         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9742         int ret;
9743
9744         if (attr->egress) {
9745                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9746                                                 priv->mtr_color_reg);
9747                 if (ret) {
9748                         DRV_LOG(ERR, "Failed to create egress policer.");
9749                         goto error;
9750                 }
9751         }
9752         if (attr->ingress) {
9753                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9754                                                 priv->mtr_color_reg);
9755                 if (ret) {
9756                         DRV_LOG(ERR, "Failed to create ingress policer.");
9757                         goto error;
9758                 }
9759         }
9760         if (attr->transfer) {
9761                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9762                                                 priv->mtr_color_reg);
9763                 if (ret) {
9764                         DRV_LOG(ERR, "Failed to create transfer policer.");
9765                         goto error;
9766                 }
9767         }
9768         return 0;
9769 error:
9770         flow_dv_destroy_policer_rules(dev, fm, attr);
9771         return -1;
9772 }
9773
9774 /**
9775  * Query a devx counter.
9776  *
9777  * @param[in] dev
9778  *   Pointer to the Ethernet device structure.
9779  * @param[in] cnt
9780  *   Index to the flow counter.
9781  * @param[in] clear
9782  *   Set to clear the counter statistics.
9783  * @param[out] pkts
9784  *   The statistics value of packets.
9785  * @param[out] bytes
9786  *   The statistics value of bytes.
9787  *
9788  * @return
9789  *   0 on success, otherwise return -1.
9790  */
9791 static int
9792 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9793                       uint64_t *pkts, uint64_t *bytes)
9794 {
9795         struct mlx5_priv *priv = dev->data->dev_private;
9796         struct mlx5_flow_counter *cnt;
9797         uint64_t inn_pkts, inn_bytes;
9798         int ret;
9799
9800         if (!priv->config.devx)
9801                 return -1;
9802
9803         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9804         if (ret)
9805                 return -1;
9806         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9807         *pkts = inn_pkts - cnt->hits;
9808         *bytes = inn_bytes - cnt->bytes;
9809         if (clear) {
9810                 cnt->hits = inn_pkts;
9811                 cnt->bytes = inn_bytes;
9812         }
9813         return 0;
9814 }
9815
9816 /**
9817  * Get aged-out flows.
9818  *
9819  * @param[in] dev
9820  *   Pointer to the Ethernet device structure.
9821  * @param[in] context
9822  *   The address of an array of pointers to the aged-out flows contexts.
9823  * @param[in] nb_contexts
9824  *   The length of context array pointers.
9825  * @param[out] error
9826  *   Perform verbose error reporting if not NULL. Initialized in case of
9827  *   error only.
9828  *
9829  * @return
9830  *   how many contexts get in success, otherwise negative errno value.
9831  *   if nb_contexts is 0, return the amount of all aged contexts.
9832  *   if nb_contexts is not 0 , return the amount of aged flows reported
9833  *   in the context array.
9834  * @note: only stub for now
9835  */
9836 static int
9837 flow_get_aged_flows(struct rte_eth_dev *dev,
9838                     void **context,
9839                     uint32_t nb_contexts,
9840                     struct rte_flow_error *error)
9841 {
9842         struct mlx5_priv *priv = dev->data->dev_private;
9843         struct mlx5_age_info *age_info;
9844         struct mlx5_age_param *age_param;
9845         struct mlx5_flow_counter *counter;
9846         int nb_flows = 0;
9847
9848         if (nb_contexts && !context)
9849                 return rte_flow_error_set(error, EINVAL,
9850                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9851                                           NULL,
9852                                           "Should assign at least one flow or"
9853                                           " context to get if nb_contexts != 0");
9854         age_info = GET_PORT_AGE_INFO(priv);
9855         rte_spinlock_lock(&age_info->aged_sl);
9856         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9857                 nb_flows++;
9858                 if (nb_contexts) {
9859                         age_param = MLX5_CNT_TO_AGE(counter);
9860                         context[nb_flows - 1] = age_param->context;
9861                         if (!(--nb_contexts))
9862                                 break;
9863                 }
9864         }
9865         rte_spinlock_unlock(&age_info->aged_sl);
9866         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9867         return nb_flows;
9868 }
9869
9870 /*
9871  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9872  */
9873 static int
9874 flow_dv_translate(struct rte_eth_dev *dev,
9875                   struct mlx5_flow *dev_flow,
9876                   const struct rte_flow_attr *attr,
9877                   const struct rte_flow_item items[],
9878                   const struct rte_flow_action actions[],
9879                   struct rte_flow_error *error)
9880 {
9881         int ret;
9882
9883         flow_dv_shared_lock(dev);
9884         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9885         flow_dv_shared_unlock(dev);
9886         return ret;
9887 }
9888
9889 /*
9890  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9891  */
9892 static int
9893 flow_dv_apply(struct rte_eth_dev *dev,
9894               struct rte_flow *flow,
9895               struct rte_flow_error *error)
9896 {
9897         int ret;
9898
9899         flow_dv_shared_lock(dev);
9900         ret = __flow_dv_apply(dev, flow, error);
9901         flow_dv_shared_unlock(dev);
9902         return ret;
9903 }
9904
9905 /*
9906  * Mutex-protected thunk to lock-free __flow_dv_remove().
9907  */
9908 static void
9909 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9910 {
9911         flow_dv_shared_lock(dev);
9912         __flow_dv_remove(dev, flow);
9913         flow_dv_shared_unlock(dev);
9914 }
9915
9916 /*
9917  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9918  */
9919 static void
9920 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9921 {
9922         flow_dv_shared_lock(dev);
9923         __flow_dv_destroy(dev, flow);
9924         flow_dv_shared_unlock(dev);
9925 }
9926
9927 /*
9928  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9929  */
9930 static uint32_t
9931 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9932 {
9933         uint32_t cnt;
9934
9935         flow_dv_shared_lock(dev);
9936         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9937         flow_dv_shared_unlock(dev);
9938         return cnt;
9939 }
9940
9941 /*
9942  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9943  */
9944 static void
9945 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9946 {
9947         flow_dv_shared_lock(dev);
9948         flow_dv_counter_release(dev, cnt);
9949         flow_dv_shared_unlock(dev);
9950 }
9951
9952 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9953         .validate = flow_dv_validate,
9954         .prepare = flow_dv_prepare,
9955         .translate = flow_dv_translate,
9956         .apply = flow_dv_apply,
9957         .remove = flow_dv_remove,
9958         .destroy = flow_dv_destroy,
9959         .query = flow_dv_query,
9960         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9961         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9962         .create_policer_rules = flow_dv_create_policer_rules,
9963         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9964         .counter_alloc = flow_dv_counter_allocate,
9965         .counter_free = flow_dv_counter_free,
9966         .counter_query = flow_dv_counter_query,
9967         .get_aged_flows = flow_get_aged_flows,
9968 };
9969
9970 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
9971