drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30
  31 #include "mlx5.h"
  32 #include "mlx5_defs.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35 #include "mlx5_prm.h"
  36 #include "mlx5_rxtx.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 /**
  74  * Initialize flow attributes structure according to flow items' types.
  75  *
  76  * @param[in] item
  77  *   Pointer to item specification.
  78  * @param[out] attr
  79  *   Pointer to flow attributes structure.
  80  */
  81 static void
  82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
  83 {
  84         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
  85                 switch (item->type) {
  86                 case RTE_FLOW_ITEM_TYPE_IPV4:
  87                         attr->ipv4 = 1;
  88                         break;
  89                 case RTE_FLOW_ITEM_TYPE_IPV6:
  90                         attr->ipv6 = 1;
  91                         break;
  92                 case RTE_FLOW_ITEM_TYPE_UDP:
  93                         attr->udp = 1;
  94                         break;
  95                 case RTE_FLOW_ITEM_TYPE_TCP:
  96                         attr->tcp = 1;
  97                         break;
  98                 default:
  99                         break;
 100                 }
 101         }
 102         attr->valid = 1;
 103 }
 104
 105 struct field_modify_info {
 106         uint32_t size; /* Size of field in protocol header, in bytes. */
 107         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 108         enum mlx5_modification_field id;
 109 };
 110
 111 struct field_modify_info modify_eth[] = {
 112         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 113         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 114         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 115         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 116         {0, 0, 0},
 117 };
 118
 119 struct field_modify_info modify_vlan_out_first_vid[] = {
 120         /* Size in bits !!! */
 121         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 122         {0, 0, 0},
 123 };
 124
 125 struct field_modify_info modify_ipv4[] = {
 126         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 127         {4, 12, MLX5_MODI_OUT_SIPV4},
 128         {4, 16, MLX5_MODI_OUT_DIPV4},
 129         {0, 0, 0},
 130 };
 131
 132 struct field_modify_info modify_ipv6[] = {
 133         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 134         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 135         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 136         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 137         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 138         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 139         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 140         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 141         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 142         {0, 0, 0},
 143 };
 144
 145 struct field_modify_info modify_udp[] = {
 146         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 147         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 148         {0, 0, 0},
 149 };
 150
 151 struct field_modify_info modify_tcp[] = {
 152         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 153         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 154         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 155         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 156         {0, 0, 0},
 157 };
 158
 159 static void
 160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 161                           uint8_t next_protocol, uint64_t *item_flags,
 162                           int *tunnel)
 163 {
 164         assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 165                item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 166         if (next_protocol == IPPROTO_IPIP) {
 167                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 168                 *tunnel = 1;
 169         }
 170         if (next_protocol == IPPROTO_IPV6) {
 171                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 172                 *tunnel = 1;
 173         }
 174 }
 175
 176 /**
 177  * Acquire the synchronizing object to protect multithreaded access
 178  * to shared dv context. Lock occurs only if context is actually
 179  * shared, i.e. we have multiport IB device and representors are
 180  * created.
 181  *
 182  * @param[in] dev
 183  *   Pointer to the rte_eth_dev structure.
 184  */
 185 static void
 186 flow_dv_shared_lock(struct rte_eth_dev *dev)
 187 {
 188         struct mlx5_priv *priv = dev->data->dev_private;
 189         struct mlx5_ibv_shared *sh = priv->sh;
 190
 191         if (sh->dv_refcnt > 1) {
 192                 int ret;
 193
 194                 ret = pthread_mutex_lock(&sh->dv_mutex);
 195                 assert(!ret);
 196                 (void)ret;
 197         }
 198 }
 199
 200 static void
 201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 202 {
 203         struct mlx5_priv *priv = dev->data->dev_private;
 204         struct mlx5_ibv_shared *sh = priv->sh;
 205
 206         if (sh->dv_refcnt > 1) {
 207                 int ret;
 208
 209                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 210                 assert(!ret);
 211                 (void)ret;
 212         }
 213 }
 214
 215 /* Update VLAN's VID/PCP based on input rte_flow_action.
 216  *
 217  * @param[in] action
 218  *   Pointer to struct rte_flow_action.
 219  * @param[out] vlan
 220  *   Pointer to struct rte_vlan_hdr.
 221  */
 222 static void
 223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 224                          struct rte_vlan_hdr *vlan)
 225 {
 226         uint16_t vlan_tci;
 227         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 228                 vlan_tci =
 229                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 230                                                action->conf)->vlan_pcp;
 231                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 232                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 233                 vlan->vlan_tci |= vlan_tci;
 234         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 235                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 236                 vlan->vlan_tci |= rte_be_to_cpu_16
 237                     (((const struct rte_flow_action_of_set_vlan_vid *)
 238                                              action->conf)->vlan_vid);
 239         }
 240 }
 241
 242 /**
 243  * Fetch 1, 2, 3 or 4 byte field from the byte array
 244  * and return as unsigned integer in host-endian format.
 245  *
 246  * @param[in] data
 247  *   Pointer to data array.
 248  * @param[in] size
 249  *   Size of field to extract.
 250  *
 251  * @return
 252  *   converted field in host endian format.
 253  */
 254 static inline uint32_t
 255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 256 {
 257         uint32_t ret;
 258
 259         switch (size) {
 260         case 1:
 261                 ret = *data;
 262                 break;
 263         case 2:
 264                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 265                 break;
 266         case 3:
 267                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 268                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 269                 break;
 270         case 4:
 271                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 272                 break;
 273         default:
 274                 assert(false);
 275                 ret = 0;
 276                 break;
 277         }
 278         return ret;
 279 }
 280
 281 /**
 282  * Convert modify-header action to DV specification.
 283  *
 284  * Data length of each action is determined by provided field description
 285  * and the item mask. Data bit offset and width of each action is determined
 286  * by provided item mask.
 287  *
 288  * @param[in] item
 289  *   Pointer to item specification.
 290  * @param[in] field
 291  *   Pointer to field modification information.
 292  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 293  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 294  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 295  * @param[in] dcopy
 296  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 297  *   Negative offset value sets the same offset as source offset.
 298  *   size field is ignored, value is taken from source field.
 299  * @param[in,out] resource
 300  *   Pointer to the modify-header resource.
 301  * @param[in] type
 302  *   Type of modification.
 303  * @param[out] error
 304  *   Pointer to the error structure.
 305  *
 306  * @return
 307  *   0 on success, a negative errno value otherwise and rte_errno is set.
 308  */
 309 static int
 310 flow_dv_convert_modify_action(struct rte_flow_item *item,
 311                               struct field_modify_info *field,
 312                               struct field_modify_info *dcopy,
 313                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 314                               uint32_t type, struct rte_flow_error *error)
 315 {
 316         uint32_t i = resource->actions_num;
 317         struct mlx5_modification_cmd *actions = resource->actions;
 318
 319         /*
 320          * The item and mask are provided in big-endian format.
 321          * The fields should be presented as in big-endian format either.
 322          * Mask must be always present, it defines the actual field width.
 323          */
 324         assert(item->mask);
 325         assert(field->size);
 326         do {
 327                 unsigned int size_b;
 328                 unsigned int off_b;
 329                 uint32_t mask;
 330                 uint32_t data;
 331
 332                 if (i >= MLX5_MODIFY_NUM)
 333                         return rte_flow_error_set(error, EINVAL,
 334                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 335                                  "too many items to modify");
 336                 /* Fetch variable byte size mask from the array. */
 337                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 338                                            field->offset, field->size);
 339                 if (!mask) {
 340                         ++field;
 341                         continue;
 342                 }
 343                 /* Deduce actual data width in bits from mask value. */
 344                 off_b = rte_bsf32(mask);
 345                 size_b = sizeof(uint32_t) * CHAR_BIT -
 346                          off_b - __builtin_clz(mask);
 347                 assert(size_b);
 348                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 349                 actions[i].action_type = type;
 350                 actions[i].field = field->id;
 351                 actions[i].offset = off_b;
 352                 actions[i].length = size_b;
 353                 /* Convert entire record to expected big-endian format. */
 354                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 355                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 356                         assert(dcopy);
 357                         actions[i].dst_field = dcopy->id;
 358                         actions[i].dst_offset =
 359                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 360                         /* Convert entire record to big-endian format. */
 361                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 362                 } else {
 363                         assert(item->spec);
 364                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 365                                                    field->offset, field->size);
 366                         /* Shift out the trailing masked bits from data. */
 367                         data = (data & mask) >> off_b;
 368                         actions[i].data1 = rte_cpu_to_be_32(data);
 369                 }
 370                 ++i;
 371                 ++field;
 372         } while (field->size);
 373         resource->actions_num = i;
 374         if (!resource->actions_num)
 375                 return rte_flow_error_set(error, EINVAL,
 376                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 377                                           "invalid modification flow item");
 378         return 0;
 379 }
 380
 381 /**
 382  * Convert modify-header set IPv4 address action to DV specification.
 383  *
 384  * @param[in,out] resource
 385  *   Pointer to the modify-header resource.
 386  * @param[in] action
 387  *   Pointer to action specification.
 388  * @param[out] error
 389  *   Pointer to the error structure.
 390  *
 391  * @return
 392  *   0 on success, a negative errno value otherwise and rte_errno is set.
 393  */
 394 static int
 395 flow_dv_convert_action_modify_ipv4
 396                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 397                          const struct rte_flow_action *action,
 398                          struct rte_flow_error *error)
 399 {
 400         const struct rte_flow_action_set_ipv4 *conf =
 401                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 402         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 403         struct rte_flow_item_ipv4 ipv4;
 404         struct rte_flow_item_ipv4 ipv4_mask;
 405
 406         memset(&ipv4, 0, sizeof(ipv4));
 407         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 408         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 409                 ipv4.hdr.src_addr = conf->ipv4_addr;
 410                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 411         } else {
 412                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 413                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 414         }
 415         item.spec = &ipv4;
 416         item.mask = &ipv4_mask;
 417         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 418                                              MLX5_MODIFICATION_TYPE_SET, error);
 419 }
 420
 421 /**
 422  * Convert modify-header set IPv6 address action to DV specification.
 423  *
 424  * @param[in,out] resource
 425  *   Pointer to the modify-header resource.
 426  * @param[in] action
 427  *   Pointer to action specification.
 428  * @param[out] error
 429  *   Pointer to the error structure.
 430  *
 431  * @return
 432  *   0 on success, a negative errno value otherwise and rte_errno is set.
 433  */
 434 static int
 435 flow_dv_convert_action_modify_ipv6
 436                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 437                          const struct rte_flow_action *action,
 438                          struct rte_flow_error *error)
 439 {
 440         const struct rte_flow_action_set_ipv6 *conf =
 441                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 442         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 443         struct rte_flow_item_ipv6 ipv6;
 444         struct rte_flow_item_ipv6 ipv6_mask;
 445
 446         memset(&ipv6, 0, sizeof(ipv6));
 447         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 448         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 449                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 450                        sizeof(ipv6.hdr.src_addr));
 451                 memcpy(&ipv6_mask.hdr.src_addr,
 452                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 453                        sizeof(ipv6.hdr.src_addr));
 454         } else {
 455                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 456                        sizeof(ipv6.hdr.dst_addr));
 457                 memcpy(&ipv6_mask.hdr.dst_addr,
 458                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 459                        sizeof(ipv6.hdr.dst_addr));
 460         }
 461         item.spec = &ipv6;
 462         item.mask = &ipv6_mask;
 463         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 464                                              MLX5_MODIFICATION_TYPE_SET, error);
 465 }
 466
 467 /**
 468  * Convert modify-header set MAC address action to DV specification.
 469  *
 470  * @param[in,out] resource
 471  *   Pointer to the modify-header resource.
 472  * @param[in] action
 473  *   Pointer to action specification.
 474  * @param[out] error
 475  *   Pointer to the error structure.
 476  *
 477  * @return
 478  *   0 on success, a negative errno value otherwise and rte_errno is set.
 479  */
 480 static int
 481 flow_dv_convert_action_modify_mac
 482                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 483                          const struct rte_flow_action *action,
 484                          struct rte_flow_error *error)
 485 {
 486         const struct rte_flow_action_set_mac *conf =
 487                 (const struct rte_flow_action_set_mac *)(action->conf);
 488         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 489         struct rte_flow_item_eth eth;
 490         struct rte_flow_item_eth eth_mask;
 491
 492         memset(&eth, 0, sizeof(eth));
 493         memset(&eth_mask, 0, sizeof(eth_mask));
 494         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 495                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 496                        sizeof(eth.src.addr_bytes));
 497                 memcpy(&eth_mask.src.addr_bytes,
 498                        &rte_flow_item_eth_mask.src.addr_bytes,
 499                        sizeof(eth_mask.src.addr_bytes));
 500         } else {
 501                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 502                        sizeof(eth.dst.addr_bytes));
 503                 memcpy(&eth_mask.dst.addr_bytes,
 504                        &rte_flow_item_eth_mask.dst.addr_bytes,
 505                        sizeof(eth_mask.dst.addr_bytes));
 506         }
 507         item.spec = &eth;
 508         item.mask = &eth_mask;
 509         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 510                                              MLX5_MODIFICATION_TYPE_SET, error);
 511 }
 512
 513 /**
 514  * Convert modify-header set VLAN VID action to DV specification.
 515  *
 516  * @param[in,out] resource
 517  *   Pointer to the modify-header resource.
 518  * @param[in] action
 519  *   Pointer to action specification.
 520  * @param[out] error
 521  *   Pointer to the error structure.
 522  *
 523  * @return
 524  *   0 on success, a negative errno value otherwise and rte_errno is set.
 525  */
 526 static int
 527 flow_dv_convert_action_modify_vlan_vid
 528                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 529                          const struct rte_flow_action *action,
 530                          struct rte_flow_error *error)
 531 {
 532         const struct rte_flow_action_of_set_vlan_vid *conf =
 533                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 534         int i = resource->actions_num;
 535         struct mlx5_modification_cmd *actions = &resource->actions[i];
 536         struct field_modify_info *field = modify_vlan_out_first_vid;
 537
 538         if (i >= MLX5_MODIFY_NUM)
 539                 return rte_flow_error_set(error, EINVAL,
 540                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 541                          "too many items to modify");
 542         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 543         actions[i].field = field->id;
 544         actions[i].length = field->size;
 545         actions[i].offset = field->offset;
 546         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 547         actions[i].data1 = conf->vlan_vid;
 548         actions[i].data1 = actions[i].data1 << 16;
 549         resource->actions_num = ++i;
 550         return 0;
 551 }
 552
 553 /**
 554  * Convert modify-header set TP action to DV specification.
 555  *
 556  * @param[in,out] resource
 557  *   Pointer to the modify-header resource.
 558  * @param[in] action
 559  *   Pointer to action specification.
 560  * @param[in] items
 561  *   Pointer to rte_flow_item objects list.
 562  * @param[in] attr
 563  *   Pointer to flow attributes structure.
 564  * @param[out] error
 565  *   Pointer to the error structure.
 566  *
 567  * @return
 568  *   0 on success, a negative errno value otherwise and rte_errno is set.
 569  */
 570 static int
 571 flow_dv_convert_action_modify_tp
 572                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 573                          const struct rte_flow_action *action,
 574                          const struct rte_flow_item *items,
 575                          union flow_dv_attr *attr,
 576                          struct rte_flow_error *error)
 577 {
 578         const struct rte_flow_action_set_tp *conf =
 579                 (const struct rte_flow_action_set_tp *)(action->conf);
 580         struct rte_flow_item item;
 581         struct rte_flow_item_udp udp;
 582         struct rte_flow_item_udp udp_mask;
 583         struct rte_flow_item_tcp tcp;
 584         struct rte_flow_item_tcp tcp_mask;
 585         struct field_modify_info *field;
 586
 587         if (!attr->valid)
 588                 flow_dv_attr_init(items, attr);
 589         if (attr->udp) {
 590                 memset(&udp, 0, sizeof(udp));
 591                 memset(&udp_mask, 0, sizeof(udp_mask));
 592                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 593                         udp.hdr.src_port = conf->port;
 594                         udp_mask.hdr.src_port =
 595                                         rte_flow_item_udp_mask.hdr.src_port;
 596                 } else {
 597                         udp.hdr.dst_port = conf->port;
 598                         udp_mask.hdr.dst_port =
 599                                         rte_flow_item_udp_mask.hdr.dst_port;
 600                 }
 601                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 602                 item.spec = &udp;
 603                 item.mask = &udp_mask;
 604                 field = modify_udp;
 605         }
 606         if (attr->tcp) {
 607                 memset(&tcp, 0, sizeof(tcp));
 608                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 609                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 610                         tcp.hdr.src_port = conf->port;
 611                         tcp_mask.hdr.src_port =
 612                                         rte_flow_item_tcp_mask.hdr.src_port;
 613                 } else {
 614                         tcp.hdr.dst_port = conf->port;
 615                         tcp_mask.hdr.dst_port =
 616                                         rte_flow_item_tcp_mask.hdr.dst_port;
 617                 }
 618                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 619                 item.spec = &tcp;
 620                 item.mask = &tcp_mask;
 621                 field = modify_tcp;
 622         }
 623         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 624                                              MLX5_MODIFICATION_TYPE_SET, error);
 625 }
 626
 627 /**
 628  * Convert modify-header set TTL action to DV specification.
 629  *
 630  * @param[in,out] resource
 631  *   Pointer to the modify-header resource.
 632  * @param[in] action
 633  *   Pointer to action specification.
 634  * @param[in] items
 635  *   Pointer to rte_flow_item objects list.
 636  * @param[in] attr
 637  *   Pointer to flow attributes structure.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_ttl
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr,
 650                          struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_ttl *conf =
 653                 (const struct rte_flow_action_set_ttl *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_ipv4 ipv4;
 656         struct rte_flow_item_ipv4 ipv4_mask;
 657         struct rte_flow_item_ipv6 ipv6;
 658         struct rte_flow_item_ipv6 ipv6_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr);
 663         if (attr->ipv4) {
 664                 memset(&ipv4, 0, sizeof(ipv4));
 665                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 666                 ipv4.hdr.time_to_live = conf->ttl_value;
 667                 ipv4_mask.hdr.time_to_live = 0xFF;
 668                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 669                 item.spec = &ipv4;
 670                 item.mask = &ipv4_mask;
 671                 field = modify_ipv4;
 672         }
 673         if (attr->ipv6) {
 674                 memset(&ipv6, 0, sizeof(ipv6));
 675                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 676                 ipv6.hdr.hop_limits = conf->ttl_value;
 677                 ipv6_mask.hdr.hop_limits = 0xFF;
 678                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 679                 item.spec = &ipv6;
 680                 item.mask = &ipv6_mask;
 681                 field = modify_ipv6;
 682         }
 683         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 684                                              MLX5_MODIFICATION_TYPE_SET, error);
 685 }
 686
 687 /**
 688  * Convert modify-header decrement TTL action to DV specification.
 689  *
 690  * @param[in,out] resource
 691  *   Pointer to the modify-header resource.
 692  * @param[in] action
 693  *   Pointer to action specification.
 694  * @param[in] items
 695  *   Pointer to rte_flow_item objects list.
 696  * @param[in] attr
 697  *   Pointer to flow attributes structure.
 698  * @param[out] error
 699  *   Pointer to the error structure.
 700  *
 701  * @return
 702  *   0 on success, a negative errno value otherwise and rte_errno is set.
 703  */
 704 static int
 705 flow_dv_convert_action_modify_dec_ttl
 706                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 707                          const struct rte_flow_item *items,
 708                          union flow_dv_attr *attr,
 709                          struct rte_flow_error *error)
 710 {
 711         struct rte_flow_item item;
 712         struct rte_flow_item_ipv4 ipv4;
 713         struct rte_flow_item_ipv4 ipv4_mask;
 714         struct rte_flow_item_ipv6 ipv6;
 715         struct rte_flow_item_ipv6 ipv6_mask;
 716         struct field_modify_info *field;
 717
 718         if (!attr->valid)
 719                 flow_dv_attr_init(items, attr);
 720         if (attr->ipv4) {
 721                 memset(&ipv4, 0, sizeof(ipv4));
 722                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 723                 ipv4.hdr.time_to_live = 0xFF;
 724                 ipv4_mask.hdr.time_to_live = 0xFF;
 725                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 726                 item.spec = &ipv4;
 727                 item.mask = &ipv4_mask;
 728                 field = modify_ipv4;
 729         }
 730         if (attr->ipv6) {
 731                 memset(&ipv6, 0, sizeof(ipv6));
 732                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 733                 ipv6.hdr.hop_limits = 0xFF;
 734                 ipv6_mask.hdr.hop_limits = 0xFF;
 735                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 736                 item.spec = &ipv6;
 737                 item.mask = &ipv6_mask;
 738                 field = modify_ipv6;
 739         }
 740         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 741                                              MLX5_MODIFICATION_TYPE_ADD, error);
 742 }
 743
 744 /**
 745  * Convert modify-header increment/decrement TCP Sequence number
 746  * to DV specification.
 747  *
 748  * @param[in,out] resource
 749  *   Pointer to the modify-header resource.
 750  * @param[in] action
 751  *   Pointer to action specification.
 752  * @param[out] error
 753  *   Pointer to the error structure.
 754  *
 755  * @return
 756  *   0 on success, a negative errno value otherwise and rte_errno is set.
 757  */
 758 static int
 759 flow_dv_convert_action_modify_tcp_seq
 760                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 761                          const struct rte_flow_action *action,
 762                          struct rte_flow_error *error)
 763 {
 764         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 765         uint64_t value = rte_be_to_cpu_32(*conf);
 766         struct rte_flow_item item;
 767         struct rte_flow_item_tcp tcp;
 768         struct rte_flow_item_tcp tcp_mask;
 769
 770         memset(&tcp, 0, sizeof(tcp));
 771         memset(&tcp_mask, 0, sizeof(tcp_mask));
 772         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 773                 /*
 774                  * The HW has no decrement operation, only increment operation.
 775                  * To simulate decrement X from Y using increment operation
 776                  * we need to add UINT32_MAX X times to Y.
 777                  * Each adding of UINT32_MAX decrements Y by 1.
 778                  */
 779                 value *= UINT32_MAX;
 780         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 781         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 782         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 783         item.spec = &tcp;
 784         item.mask = &tcp_mask;
 785         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 786                                              MLX5_MODIFICATION_TYPE_ADD, error);
 787 }
 788
 789 /**
 790  * Convert modify-header increment/decrement TCP Acknowledgment number
 791  * to DV specification.
 792  *
 793  * @param[in,out] resource
 794  *   Pointer to the modify-header resource.
 795  * @param[in] action
 796  *   Pointer to action specification.
 797  * @param[out] error
 798  *   Pointer to the error structure.
 799  *
 800  * @return
 801  *   0 on success, a negative errno value otherwise and rte_errno is set.
 802  */
 803 static int
 804 flow_dv_convert_action_modify_tcp_ack
 805                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 806                          const struct rte_flow_action *action,
 807                          struct rte_flow_error *error)
 808 {
 809         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 810         uint64_t value = rte_be_to_cpu_32(*conf);
 811         struct rte_flow_item item;
 812         struct rte_flow_item_tcp tcp;
 813         struct rte_flow_item_tcp tcp_mask;
 814
 815         memset(&tcp, 0, sizeof(tcp));
 816         memset(&tcp_mask, 0, sizeof(tcp_mask));
 817         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 818                 /*
 819                  * The HW has no decrement operation, only increment operation.
 820                  * To simulate decrement X from Y using increment operation
 821                  * we need to add UINT32_MAX X times to Y.
 822                  * Each adding of UINT32_MAX decrements Y by 1.
 823                  */
 824                 value *= UINT32_MAX;
 825         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 826         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 827         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 828         item.spec = &tcp;
 829         item.mask = &tcp_mask;
 830         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 831                                              MLX5_MODIFICATION_TYPE_ADD, error);
 832 }
 833
 834 static enum mlx5_modification_field reg_to_field[] = {
 835         [REG_NONE] = MLX5_MODI_OUT_NONE,
 836         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 837         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 838         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 839         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 840         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 841         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 842         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 843         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 844         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 845         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 846 };
 847
 848 /**
 849  * Convert register set to DV specification.
 850  *
 851  * @param[in,out] resource
 852  *   Pointer to the modify-header resource.
 853  * @param[in] action
 854  *   Pointer to action specification.
 855  * @param[out] error
 856  *   Pointer to the error structure.
 857  *
 858  * @return
 859  *   0 on success, a negative errno value otherwise and rte_errno is set.
 860  */
 861 static int
 862 flow_dv_convert_action_set_reg
 863                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 864                          const struct rte_flow_action *action,
 865                          struct rte_flow_error *error)
 866 {
 867         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 868         struct mlx5_modification_cmd *actions = resource->actions;
 869         uint32_t i = resource->actions_num;
 870
 871         if (i >= MLX5_MODIFY_NUM)
 872                 return rte_flow_error_set(error, EINVAL,
 873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 874                                           "too many items to modify");
 875         assert(conf->id != REG_NONE);
 876         assert(conf->id < RTE_DIM(reg_to_field));
 877         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 878         actions[i].field = reg_to_field[conf->id];
 879         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 880         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 881         ++i;
 882         resource->actions_num = i;
 883         if (!resource->actions_num)
 884                 return rte_flow_error_set(error, EINVAL,
 885                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 886                                           "invalid modification flow item");
 887         return 0;
 888 }
 889
 890 /**
 891  * Convert SET_TAG action to DV specification.
 892  *
 893  * @param[in] dev
 894  *   Pointer to the rte_eth_dev structure.
 895  * @param[in,out] resource
 896  *   Pointer to the modify-header resource.
 897  * @param[in] conf
 898  *   Pointer to action specification.
 899  * @param[out] error
 900  *   Pointer to the error structure.
 901  *
 902  * @return
 903  *   0 on success, a negative errno value otherwise and rte_errno is set.
 904  */
 905 static int
 906 flow_dv_convert_action_set_tag
 907                         (struct rte_eth_dev *dev,
 908                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 909                          const struct rte_flow_action_set_tag *conf,
 910                          struct rte_flow_error *error)
 911 {
 912         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 913         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 914         struct rte_flow_item item = {
 915                 .spec = &data,
 916                 .mask = &mask,
 917         };
 918         struct field_modify_info reg_c_x[] = {
 919                 [1] = {0, 0, 0},
 920         };
 921         enum mlx5_modification_field reg_type;
 922         int ret;
 923
 924         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
 925         if (ret < 0)
 926                 return ret;
 927         assert(ret != REG_NONE);
 928         assert((unsigned int)ret < RTE_DIM(reg_to_field));
 929         reg_type = reg_to_field[ret];
 930         assert(reg_type > 0);
 931         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
 932         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
 933                                              MLX5_MODIFICATION_TYPE_SET, error);
 934 }
 935
 936 /**
 937  * Convert internal COPY_REG action to DV specification.
 938  *
 939  * @param[in] dev
 940  *   Pointer to the rte_eth_dev structure.
 941  * @param[in,out] res
 942  *   Pointer to the modify-header resource.
 943  * @param[in] action
 944  *   Pointer to action specification.
 945  * @param[out] error
 946  *   Pointer to the error structure.
 947  *
 948  * @return
 949  *   0 on success, a negative errno value otherwise and rte_errno is set.
 950  */
 951 static int
 952 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
 953                                  struct mlx5_flow_dv_modify_hdr_resource *res,
 954                                  const struct rte_flow_action *action,
 955                                  struct rte_flow_error *error)
 956 {
 957         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
 958         rte_be32_t mask = RTE_BE32(UINT32_MAX);
 959         struct rte_flow_item item = {
 960                 .spec = NULL,
 961                 .mask = &mask,
 962         };
 963         struct field_modify_info reg_src[] = {
 964                 {4, 0, reg_to_field[conf->src]},
 965                 {0, 0, 0},
 966         };
 967         struct field_modify_info reg_dst = {
 968                 .offset = 0,
 969                 .id = reg_to_field[conf->dst],
 970         };
 971         /* Adjust reg_c[0] usage according to reported mask. */
 972         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
 973                 struct mlx5_priv *priv = dev->data->dev_private;
 974                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
 975
 976                 assert(reg_c0);
 977                 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
 978                 if (conf->dst == REG_C_0) {
 979                         /* Copy to reg_c[0], within mask only. */
 980                         reg_dst.offset = rte_bsf32(reg_c0);
 981                         /*
 982                          * Mask is ignoring the enianness, because
 983                          * there is no conversion in datapath.
 984                          */
 985 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 986                         /* Copy from destination lower bits to reg_c[0]. */
 987                         mask = reg_c0 >> reg_dst.offset;
 988 #else
 989                         /* Copy from destination upper bits to reg_c[0]. */
 990                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
 991                                           rte_fls_u32(reg_c0));
 992 #endif
 993                 } else {
 994                         mask = rte_cpu_to_be_32(reg_c0);
 995 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 996                         /* Copy from reg_c[0] to destination lower bits. */
 997                         reg_dst.offset = 0;
 998 #else
 999                         /* Copy from reg_c[0] to destination upper bits. */
1000                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1001                                          (rte_fls_u32(reg_c0) -
1002                                           rte_bsf32(reg_c0));
1003 #endif
1004                 }
1005         }
1006         return flow_dv_convert_modify_action(&item,
1007                                              reg_src, &reg_dst, res,
1008                                              MLX5_MODIFICATION_TYPE_COPY,
1009                                              error);
1010 }
1011
1012 /**
1013  * Convert MARK action to DV specification. This routine is used
1014  * in extensive metadata only and requires metadata register to be
1015  * handled. In legacy mode hardware tag resource is engaged.
1016  *
1017  * @param[in] dev
1018  *   Pointer to the rte_eth_dev structure.
1019  * @param[in] conf
1020  *   Pointer to MARK action specification.
1021  * @param[in,out] resource
1022  *   Pointer to the modify-header resource.
1023  * @param[out] error
1024  *   Pointer to the error structure.
1025  *
1026  * @return
1027  *   0 on success, a negative errno value otherwise and rte_errno is set.
1028  */
1029 static int
1030 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1031                             const struct rte_flow_action_mark *conf,
1032                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1033                             struct rte_flow_error *error)
1034 {
1035         struct mlx5_priv *priv = dev->data->dev_private;
1036         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1037                                            priv->sh->dv_mark_mask);
1038         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1039         struct rte_flow_item item = {
1040                 .spec = &data,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_c_x[] = {
1044                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1045                 {0, 0, 0},
1046         };
1047         enum modify_reg reg;
1048
1049         if (!mask)
1050                 return rte_flow_error_set(error, EINVAL,
1051                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1052                                           NULL, "zero mark action mask");
1053         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1054         if (reg < 0)
1055                 return reg;
1056         assert(reg > 0);
1057         reg_c_x[0].id = reg_to_field[reg];
1058         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1059                                              MLX5_MODIFICATION_TYPE_SET, error);
1060 }
1061
1062 /**
1063  * Get metadata register index for specified steering domain.
1064  *
1065  * @param[in] dev
1066  *   Pointer to the rte_eth_dev structure.
1067  * @param[in] attr
1068  *   Attributes of flow to determine steering domain.
1069  * @param[out] error
1070  *   Pointer to the error structure.
1071  *
1072  * @return
1073  *   positive index on success, a negative errno value otherwise
1074  *   and rte_errno is set.
1075  */
1076 static enum modify_reg
1077 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1078                          const struct rte_flow_attr *attr,
1079                          struct rte_flow_error *error)
1080 {
1081         enum modify_reg reg =
1082                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1083                                           MLX5_METADATA_FDB :
1084                                             attr->egress ?
1085                                             MLX5_METADATA_TX :
1086                                             MLX5_METADATA_RX, 0, error);
1087         if (reg < 0)
1088                 return rte_flow_error_set(error,
1089                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1090                                           NULL, "unavailable "
1091                                           "metadata register");
1092         return reg;
1093 }
1094
1095 /**
1096  * Convert SET_META action to DV specification.
1097  *
1098  * @param[in] dev
1099  *   Pointer to the rte_eth_dev structure.
1100  * @param[in,out] resource
1101  *   Pointer to the modify-header resource.
1102  * @param[in] attr
1103  *   Attributes of flow that includes this item.
1104  * @param[in] conf
1105  *   Pointer to action specification.
1106  * @param[out] error
1107  *   Pointer to the error structure.
1108  *
1109  * @return
1110  *   0 on success, a negative errno value otherwise and rte_errno is set.
1111  */
1112 static int
1113 flow_dv_convert_action_set_meta
1114                         (struct rte_eth_dev *dev,
1115                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1116                          const struct rte_flow_attr *attr,
1117                          const struct rte_flow_action_set_meta *conf,
1118                          struct rte_flow_error *error)
1119 {
1120         uint32_t data = conf->data;
1121         uint32_t mask = conf->mask;
1122         struct rte_flow_item item = {
1123                 .spec = &data,
1124                 .mask = &mask,
1125         };
1126         struct field_modify_info reg_c_x[] = {
1127                 [1] = {0, 0, 0},
1128         };
1129         enum modify_reg reg = flow_dv_get_metadata_reg(dev, attr, error);
1130
1131         if (reg < 0)
1132                 return reg;
1133         /*
1134          * In datapath code there is no endianness
1135          * coversions for perfromance reasons, all
1136          * pattern conversions are done in rte_flow.
1137          */
1138         if (reg == REG_C_0) {
1139                 struct mlx5_priv *priv = dev->data->dev_private;
1140                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1141                 uint32_t shl_c0;
1142
1143                 assert(msk_c0);
1144 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1145                 shl_c0 = rte_bsf32(msk_c0);
1146 #else
1147                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1148 #endif
1149                 mask <<= shl_c0;
1150                 data <<= shl_c0;
1151                 assert(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1152         }
1153         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1154         /* The routine expects parameters in memory as big-endian ones. */
1155         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1156                                              MLX5_MODIFICATION_TYPE_SET, error);
1157 }
1158
1159 /**
1160  * Validate MARK item.
1161  *
1162  * @param[in] dev
1163  *   Pointer to the rte_eth_dev structure.
1164  * @param[in] item
1165  *   Item specification.
1166  * @param[in] attr
1167  *   Attributes of flow that includes this item.
1168  * @param[out] error
1169  *   Pointer to error structure.
1170  *
1171  * @return
1172  *   0 on success, a negative errno value otherwise and rte_errno is set.
1173  */
1174 static int
1175 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1176                            const struct rte_flow_item *item,
1177                            const struct rte_flow_attr *attr __rte_unused,
1178                            struct rte_flow_error *error)
1179 {
1180         struct mlx5_priv *priv = dev->data->dev_private;
1181         struct mlx5_dev_config *config = &priv->config;
1182         const struct rte_flow_item_mark *spec = item->spec;
1183         const struct rte_flow_item_mark *mask = item->mask;
1184         const struct rte_flow_item_mark nic_mask = {
1185                 .id = priv->sh->dv_mark_mask,
1186         };
1187         int ret;
1188
1189         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1190                 return rte_flow_error_set(error, ENOTSUP,
1191                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1192                                           "extended metadata feature"
1193                                           " isn't enabled");
1194         if (!mlx5_flow_ext_mreg_supported(dev))
1195                 return rte_flow_error_set(error, ENOTSUP,
1196                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1197                                           "extended metadata register"
1198                                           " isn't supported");
1199         if (!nic_mask.id)
1200                 return rte_flow_error_set(error, ENOTSUP,
1201                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1202                                           "extended metadata register"
1203                                           " isn't available");
1204         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1205         if (ret < 0)
1206                 return ret;
1207         if (!spec)
1208                 return rte_flow_error_set(error, EINVAL,
1209                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1210                                           item->spec,
1211                                           "data cannot be empty");
1212         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1213                 return rte_flow_error_set(error, EINVAL,
1214                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1215                                           &spec->id,
1216                                           "mark id exceeds the limit");
1217         if (!mask)
1218                 mask = &nic_mask;
1219         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1220                                         (const uint8_t *)&nic_mask,
1221                                         sizeof(struct rte_flow_item_mark),
1222                                         error);
1223         if (ret < 0)
1224                 return ret;
1225         return 0;
1226 }
1227
1228 /**
1229  * Validate META item.
1230  *
1231  * @param[in] dev
1232  *   Pointer to the rte_eth_dev structure.
1233  * @param[in] item
1234  *   Item specification.
1235  * @param[in] attr
1236  *   Attributes of flow that includes this item.
1237  * @param[out] error
1238  *   Pointer to error structure.
1239  *
1240  * @return
1241  *   0 on success, a negative errno value otherwise and rte_errno is set.
1242  */
1243 static int
1244 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1245                            const struct rte_flow_item *item,
1246                            const struct rte_flow_attr *attr,
1247                            struct rte_flow_error *error)
1248 {
1249         struct mlx5_priv *priv = dev->data->dev_private;
1250         struct mlx5_dev_config *config = &priv->config;
1251         const struct rte_flow_item_meta *spec = item->spec;
1252         const struct rte_flow_item_meta *mask = item->mask;
1253         struct rte_flow_item_meta nic_mask = {
1254                 .data = UINT32_MAX
1255         };
1256         enum modify_reg reg;
1257         int ret;
1258
1259         if (!spec)
1260                 return rte_flow_error_set(error, EINVAL,
1261                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1262                                           item->spec,
1263                                           "data cannot be empty");
1264         if (!spec->data)
1265                 return rte_flow_error_set(error, EINVAL,
1266                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1267                                           "data cannot be zero");
1268         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1269                 if (!mlx5_flow_ext_mreg_supported(dev))
1270                         return rte_flow_error_set(error, ENOTSUP,
1271                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1272                                           "extended metadata register"
1273                                           " isn't supported");
1274                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1275                 if (reg < 0)
1276                         return reg;
1277                 if (reg == REG_B)
1278                         return rte_flow_error_set(error, ENOTSUP,
1279                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1280                                           "match on reg_b "
1281                                           "isn't supported");
1282                 if (reg != REG_A)
1283                         nic_mask.data = priv->sh->dv_meta_mask;
1284         }
1285         if (!mask)
1286                 mask = &rte_flow_item_meta_mask;
1287         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1288                                         (const uint8_t *)&nic_mask,
1289                                         sizeof(struct rte_flow_item_meta),
1290                                         error);
1291         return ret;
1292 }
1293
1294 /**
1295  * Validate TAG item.
1296  *
1297  * @param[in] dev
1298  *   Pointer to the rte_eth_dev structure.
1299  * @param[in] item
1300  *   Item specification.
1301  * @param[in] attr
1302  *   Attributes of flow that includes this item.
1303  * @param[out] error
1304  *   Pointer to error structure.
1305  *
1306  * @return
1307  *   0 on success, a negative errno value otherwise and rte_errno is set.
1308  */
1309 static int
1310 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1311                           const struct rte_flow_item *item,
1312                           const struct rte_flow_attr *attr __rte_unused,
1313                           struct rte_flow_error *error)
1314 {
1315         const struct rte_flow_item_tag *spec = item->spec;
1316         const struct rte_flow_item_tag *mask = item->mask;
1317         const struct rte_flow_item_tag nic_mask = {
1318                 .data = RTE_BE32(UINT32_MAX),
1319                 .index = 0xff,
1320         };
1321         int ret;
1322
1323         if (!mlx5_flow_ext_mreg_supported(dev))
1324                 return rte_flow_error_set(error, ENOTSUP,
1325                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1326                                           "extensive metadata register"
1327                                           " isn't supported");
1328         if (!spec)
1329                 return rte_flow_error_set(error, EINVAL,
1330                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1331                                           item->spec,
1332                                           "data cannot be empty");
1333         if (!mask)
1334                 mask = &rte_flow_item_tag_mask;
1335         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1336                                         (const uint8_t *)&nic_mask,
1337                                         sizeof(struct rte_flow_item_tag),
1338                                         error);
1339         if (ret < 0)
1340                 return ret;
1341         if (mask->index != 0xff)
1342                 return rte_flow_error_set(error, EINVAL,
1343                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1344                                           "partial mask for tag index"
1345                                           " is not supported");
1346         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1347         if (ret < 0)
1348                 return ret;
1349         assert(ret != REG_NONE);
1350         return 0;
1351 }
1352
1353 /**
1354  * Validate vport item.
1355  *
1356  * @param[in] dev
1357  *   Pointer to the rte_eth_dev structure.
1358  * @param[in] item
1359  *   Item specification.
1360  * @param[in] attr
1361  *   Attributes of flow that includes this item.
1362  * @param[in] item_flags
1363  *   Bit-fields that holds the items detected until now.
1364  * @param[out] error
1365  *   Pointer to error structure.
1366  *
1367  * @return
1368  *   0 on success, a negative errno value otherwise and rte_errno is set.
1369  */
1370 static int
1371 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1372                               const struct rte_flow_item *item,
1373                               const struct rte_flow_attr *attr,
1374                               uint64_t item_flags,
1375                               struct rte_flow_error *error)
1376 {
1377         const struct rte_flow_item_port_id *spec = item->spec;
1378         const struct rte_flow_item_port_id *mask = item->mask;
1379         const struct rte_flow_item_port_id switch_mask = {
1380                         .id = 0xffffffff,
1381         };
1382         struct mlx5_priv *esw_priv;
1383         struct mlx5_priv *dev_priv;
1384         int ret;
1385
1386         if (!attr->transfer)
1387                 return rte_flow_error_set(error, EINVAL,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM,
1389                                           NULL,
1390                                           "match on port id is valid only"
1391                                           " when transfer flag is enabled");
1392         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1393                 return rte_flow_error_set(error, ENOTSUP,
1394                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1395                                           "multiple source ports are not"
1396                                           " supported");
1397         if (!mask)
1398                 mask = &switch_mask;
1399         if (mask->id != 0xffffffff)
1400                 return rte_flow_error_set(error, ENOTSUP,
1401                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1402                                            mask,
1403                                            "no support for partial mask on"
1404                                            " \"id\" field");
1405         ret = mlx5_flow_item_acceptable
1406                                 (item, (const uint8_t *)mask,
1407                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1408                                  sizeof(struct rte_flow_item_port_id),
1409                                  error);
1410         if (ret)
1411                 return ret;
1412         if (!spec)
1413                 return 0;
1414         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1415         if (!esw_priv)
1416                 return rte_flow_error_set(error, rte_errno,
1417                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1418                                           "failed to obtain E-Switch info for"
1419                                           " port");
1420         dev_priv = mlx5_dev_to_eswitch_info(dev);
1421         if (!dev_priv)
1422                 return rte_flow_error_set(error, rte_errno,
1423                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1424                                           NULL,
1425                                           "failed to obtain E-Switch info");
1426         if (esw_priv->domain_id != dev_priv->domain_id)
1427                 return rte_flow_error_set(error, EINVAL,
1428                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1429                                           "cannot match on a port from a"
1430                                           " different E-Switch");
1431         return 0;
1432 }
1433
1434 /**
1435  * Validate the pop VLAN action.
1436  *
1437  * @param[in] dev
1438  *   Pointer to the rte_eth_dev structure.
1439  * @param[in] action_flags
1440  *   Holds the actions detected until now.
1441  * @param[in] action
1442  *   Pointer to the pop vlan action.
1443  * @param[in] item_flags
1444  *   The items found in this flow rule.
1445  * @param[in] attr
1446  *   Pointer to flow attributes.
1447  * @param[out] error
1448  *   Pointer to error structure.
1449  *
1450  * @return
1451  *   0 on success, a negative errno value otherwise and rte_errno is set.
1452  */
1453 static int
1454 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1455                                  uint64_t action_flags,
1456                                  const struct rte_flow_action *action,
1457                                  uint64_t item_flags,
1458                                  const struct rte_flow_attr *attr,
1459                                  struct rte_flow_error *error)
1460 {
1461         struct mlx5_priv *priv = dev->data->dev_private;
1462
1463         (void)action;
1464         (void)attr;
1465         if (!priv->sh->pop_vlan_action)
1466                 return rte_flow_error_set(error, ENOTSUP,
1467                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1468                                           NULL,
1469                                           "pop vlan action is not supported");
1470         /*
1471          * Check for inconsistencies:
1472          *  fail strip_vlan in a flow that matches packets without VLAN tags.
1473          *  fail strip_vlan in a flow that matches packets without explicitly a
1474          *  matching on VLAN tag ?
1475          */
1476         if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1477                 return rte_flow_error_set(error, ENOTSUP,
1478                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1479                                           NULL,
1480                                           "no support for multiple vlan pop "
1481                                           "actions");
1482         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1483                 return rte_flow_error_set(error, ENOTSUP,
1484                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1485                                           NULL,
1486                                           "cannot pop vlan without a "
1487                                           "match on (outer) vlan in the flow");
1488         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1489                 return rte_flow_error_set(error, EINVAL,
1490                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1491                                           "wrong action order, port_id should "
1492                                           "be after pop VLAN action");
1493         return 0;
1494 }
1495
1496 /**
1497  * Get VLAN default info from vlan match info.
1498  *
1499  * @param[in] dev
1500  *   Pointer to the rte_eth_dev structure.
1501  * @param[in] item
1502  *   the list of item specifications.
1503  * @param[out] vlan
1504  *   pointer VLAN info to fill to.
1505  * @param[out] error
1506  *   Pointer to error structure.
1507  *
1508  * @return
1509  *   0 on success, a negative errno value otherwise and rte_errno is set.
1510  */
1511 static void
1512 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1513                                   struct rte_vlan_hdr *vlan)
1514 {
1515         const struct rte_flow_item_vlan nic_mask = {
1516                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1517                                 MLX5DV_FLOW_VLAN_VID_MASK),
1518                 .inner_type = RTE_BE16(0xffff),
1519         };
1520
1521         if (items == NULL)
1522                 return;
1523         for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1524                items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1525                 ;
1526         if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1527                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1528                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1529
1530                 if (!vlan_m)
1531                         vlan_m = &nic_mask;
1532                 /* Only full match values are accepted */
1533                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1534                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1535                         vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1536                         vlan->vlan_tci |=
1537                                 rte_be_to_cpu_16(vlan_v->tci &
1538                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1539                 }
1540                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1541                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1542                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1543                         vlan->vlan_tci |=
1544                                 rte_be_to_cpu_16(vlan_v->tci &
1545                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1546                 }
1547                 if (vlan_m->inner_type == nic_mask.inner_type)
1548                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1549                                                            vlan_m->inner_type);
1550         }
1551 }
1552
1553 /**
1554  * Validate the push VLAN action.
1555  *
1556  * @param[in] action_flags
1557  *   Holds the actions detected until now.
1558  * @param[in] action
1559  *   Pointer to the encap action.
1560  * @param[in] attr
1561  *   Pointer to flow attributes
1562  * @param[out] error
1563  *   Pointer to error structure.
1564  *
1565  * @return
1566  *   0 on success, a negative errno value otherwise and rte_errno is set.
1567  */
1568 static int
1569 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1570                                   uint64_t item_flags,
1571                                   const struct rte_flow_action *action,
1572                                   const struct rte_flow_attr *attr,
1573                                   struct rte_flow_error *error)
1574 {
1575         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1576
1577         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1578             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1579                 return rte_flow_error_set(error, EINVAL,
1580                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1581                                           "invalid vlan ethertype");
1582         if (action_flags &
1583                 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1584                 return rte_flow_error_set(error, ENOTSUP,
1585                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1586                                           "no support for multiple VLAN "
1587                                           "actions");
1588         if (!mlx5_flow_find_action
1589                         (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1590             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1591                 return rte_flow_error_set(error, ENOTSUP,
1592                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
1593                                 "push VLAN needs to match on VLAN in order to "
1594                                 "get VLAN VID information because there is "
1595                                 "no followed set VLAN VID action");
1596         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1597                 return rte_flow_error_set(error, EINVAL,
1598                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1599                                           "wrong action order, port_id should "
1600                                           "be after push VLAN");
1601         (void)attr;
1602         return 0;
1603 }
1604
1605 /**
1606  * Validate the set VLAN PCP.
1607  *
1608  * @param[in] action_flags
1609  *   Holds the actions detected until now.
1610  * @param[in] actions
1611  *   Pointer to the list of actions remaining in the flow rule.
1612  * @param[in] attr
1613  *   Pointer to flow attributes
1614  * @param[out] error
1615  *   Pointer to error structure.
1616  *
1617  * @return
1618  *   0 on success, a negative errno value otherwise and rte_errno is set.
1619  */
1620 static int
1621 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1622                                      const struct rte_flow_action actions[],
1623                                      struct rte_flow_error *error)
1624 {
1625         const struct rte_flow_action *action = actions;
1626         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1627
1628         if (conf->vlan_pcp > 7)
1629                 return rte_flow_error_set(error, EINVAL,
1630                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1631                                           "VLAN PCP value is too big");
1632         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1633                 return rte_flow_error_set(error, ENOTSUP,
1634                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1635                                           "set VLAN PCP action must follow "
1636                                           "the push VLAN action");
1637         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1638                 return rte_flow_error_set(error, ENOTSUP,
1639                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1640                                           "Multiple VLAN PCP modification are "
1641                                           "not supported");
1642         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1643                 return rte_flow_error_set(error, EINVAL,
1644                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1645                                           "wrong action order, port_id should "
1646                                           "be after set VLAN PCP");
1647         return 0;
1648 }
1649
1650 /**
1651  * Validate the set VLAN VID.
1652  *
1653  * @param[in] item_flags
1654  *   Holds the items detected in this rule.
1655  * @param[in] actions
1656  *   Pointer to the list of actions remaining in the flow rule.
1657  * @param[in] attr
1658  *   Pointer to flow attributes
1659  * @param[out] error
1660  *   Pointer to error structure.
1661  *
1662  * @return
1663  *   0 on success, a negative errno value otherwise and rte_errno is set.
1664  */
1665 static int
1666 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1667                                      uint64_t action_flags,
1668                                      const struct rte_flow_action actions[],
1669                                      struct rte_flow_error *error)
1670 {
1671         const struct rte_flow_action *action = actions;
1672         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1673
1674         if (conf->vlan_vid > RTE_BE16(0xFFE))
1675                 return rte_flow_error_set(error, EINVAL,
1676                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1677                                           "VLAN VID value is too big");
1678         /* there is an of_push_vlan action before us */
1679         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1680                 if (mlx5_flow_find_action(actions + 1,
1681                                           RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1682                         return rte_flow_error_set(error, ENOTSUP,
1683                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
1684                                         "Multiple VLAN VID modifications are "
1685                                         "not supported");
1686                 else
1687                         return 0;
1688         }
1689
1690         /*
1691          * Action is on an existing VLAN header:
1692          *    Need to verify this is a single modify CID action.
1693          *   Rule mast include a match on outer VLAN.
1694          */
1695         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1696                 return rte_flow_error_set(error, ENOTSUP,
1697                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1698                                           "Multiple VLAN VID modifications are "
1699                                           "not supported");
1700         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1701                 return rte_flow_error_set(error, EINVAL,
1702                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1703                                           "match on VLAN is required in order "
1704                                           "to set VLAN VID");
1705         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1706                 return rte_flow_error_set(error, EINVAL,
1707                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1708                                           "wrong action order, port_id should "
1709                                           "be after set VLAN VID");
1710         return 0;
1711 }
1712
1713 /*
1714  * Validate the FLAG action.
1715  *
1716  * @param[in] dev
1717  *   Pointer to the rte_eth_dev structure.
1718  * @param[in] action_flags
1719  *   Holds the actions detected until now.
1720  * @param[in] attr
1721  *   Pointer to flow attributes
1722  * @param[out] error
1723  *   Pointer to error structure.
1724  *
1725  * @return
1726  *   0 on success, a negative errno value otherwise and rte_errno is set.
1727  */
1728 static int
1729 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1730                              uint64_t action_flags,
1731                              const struct rte_flow_attr *attr,
1732                              struct rte_flow_error *error)
1733 {
1734         struct mlx5_priv *priv = dev->data->dev_private;
1735         struct mlx5_dev_config *config = &priv->config;
1736         int ret;
1737
1738         /* Fall back if no extended metadata register support. */
1739         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1740                 return mlx5_flow_validate_action_flag(action_flags, attr,
1741                                                       error);
1742         /* Extensive metadata mode requires registers. */
1743         if (!mlx5_flow_ext_mreg_supported(dev))
1744                 return rte_flow_error_set(error, ENOTSUP,
1745                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1746                                           "no metadata registers "
1747                                           "to support flag action");
1748         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1749                 return rte_flow_error_set(error, ENOTSUP,
1750                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1751                                           "extended metadata register"
1752                                           " isn't available");
1753         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1754         if (ret < 0)
1755                 return ret;
1756         assert(ret > 0);
1757         if (action_flags & MLX5_FLOW_ACTION_DROP)
1758                 return rte_flow_error_set(error, EINVAL,
1759                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1760                                           "can't drop and flag in same flow");
1761         if (action_flags & MLX5_FLOW_ACTION_MARK)
1762                 return rte_flow_error_set(error, EINVAL,
1763                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1764                                           "can't mark and flag in same flow");
1765         if (action_flags & MLX5_FLOW_ACTION_FLAG)
1766                 return rte_flow_error_set(error, EINVAL,
1767                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1768                                           "can't have 2 flag"
1769                                           " actions in same flow");
1770         return 0;
1771 }
1772
1773 /**
1774  * Validate MARK action.
1775  *
1776  * @param[in] dev
1777  *   Pointer to the rte_eth_dev structure.
1778  * @param[in] action
1779  *   Pointer to action.
1780  * @param[in] action_flags
1781  *   Holds the actions detected until now.
1782  * @param[in] attr
1783  *   Pointer to flow attributes
1784  * @param[out] error
1785  *   Pointer to error structure.
1786  *
1787  * @return
1788  *   0 on success, a negative errno value otherwise and rte_errno is set.
1789  */
1790 static int
1791 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1792                              const struct rte_flow_action *action,
1793                              uint64_t action_flags,
1794                              const struct rte_flow_attr *attr,
1795                              struct rte_flow_error *error)
1796 {
1797         struct mlx5_priv *priv = dev->data->dev_private;
1798         struct mlx5_dev_config *config = &priv->config;
1799         const struct rte_flow_action_mark *mark = action->conf;
1800         int ret;
1801
1802         /* Fall back if no extended metadata register support. */
1803         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1804                 return mlx5_flow_validate_action_mark(action, action_flags,
1805                                                       attr, error);
1806         /* Extensive metadata mode requires registers. */
1807         if (!mlx5_flow_ext_mreg_supported(dev))
1808                 return rte_flow_error_set(error, ENOTSUP,
1809                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1810                                           "no metadata registers "
1811                                           "to support mark action");
1812         if (!priv->sh->dv_mark_mask)
1813                 return rte_flow_error_set(error, ENOTSUP,
1814                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1815                                           "extended metadata register"
1816                                           " isn't available");
1817         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1818         if (ret < 0)
1819                 return ret;
1820         assert(ret > 0);
1821         if (!mark)
1822                 return rte_flow_error_set(error, EINVAL,
1823                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1824                                           "configuration cannot be null");
1825         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1826                 return rte_flow_error_set(error, EINVAL,
1827                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1828                                           &mark->id,
1829                                           "mark id exceeds the limit");
1830         if (action_flags & MLX5_FLOW_ACTION_DROP)
1831                 return rte_flow_error_set(error, EINVAL,
1832                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1833                                           "can't drop and mark in same flow");
1834         if (action_flags & MLX5_FLOW_ACTION_FLAG)
1835                 return rte_flow_error_set(error, EINVAL,
1836                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1837                                           "can't flag and mark in same flow");
1838         if (action_flags & MLX5_FLOW_ACTION_MARK)
1839                 return rte_flow_error_set(error, EINVAL,
1840                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1841                                           "can't have 2 mark actions in same"
1842                                           " flow");
1843         return 0;
1844 }
1845
1846 /**
1847  * Validate SET_META action.
1848  *
1849  * @param[in] dev
1850  *   Pointer to the rte_eth_dev structure.
1851  * @param[in] action
1852  *   Pointer to the encap action.
1853  * @param[in] action_flags
1854  *   Holds the actions detected until now.
1855  * @param[in] attr
1856  *   Pointer to flow attributes
1857  * @param[out] error
1858  *   Pointer to error structure.
1859  *
1860  * @return
1861  *   0 on success, a negative errno value otherwise and rte_errno is set.
1862  */
1863 static int
1864 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
1865                                  const struct rte_flow_action *action,
1866                                  uint64_t action_flags __rte_unused,
1867                                  const struct rte_flow_attr *attr,
1868                                  struct rte_flow_error *error)
1869 {
1870         const struct rte_flow_action_set_meta *conf;
1871         uint32_t nic_mask = UINT32_MAX;
1872         enum modify_reg reg;
1873
1874         if (!mlx5_flow_ext_mreg_supported(dev))
1875                 return rte_flow_error_set(error, ENOTSUP,
1876                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1877                                           "extended metadata register"
1878                                           " isn't supported");
1879         reg = flow_dv_get_metadata_reg(dev, attr, error);
1880         if (reg < 0)
1881                 return reg;
1882         if (reg != REG_A && reg != REG_B) {
1883                 struct mlx5_priv *priv = dev->data->dev_private;
1884
1885                 nic_mask = priv->sh->dv_meta_mask;
1886         }
1887         if (!(action->conf))
1888                 return rte_flow_error_set(error, EINVAL,
1889                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1890                                           "configuration cannot be null");
1891         conf = (const struct rte_flow_action_set_meta *)action->conf;
1892         if (!conf->mask)
1893                 return rte_flow_error_set(error, EINVAL,
1894                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1895                                           "zero mask doesn't have any effect");
1896         if (conf->mask & ~nic_mask)
1897                 return rte_flow_error_set(error, EINVAL,
1898                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1899                                           "meta data must be within reg C0");
1900         if (!(conf->data & conf->mask))
1901                 return rte_flow_error_set(error, EINVAL,
1902                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1903                                           "zero value has no effect");
1904         return 0;
1905 }
1906
1907 /**
1908  * Validate SET_TAG action.
1909  *
1910  * @param[in] dev
1911  *   Pointer to the rte_eth_dev structure.
1912  * @param[in] action
1913  *   Pointer to the encap action.
1914  * @param[in] action_flags
1915  *   Holds the actions detected until now.
1916  * @param[in] attr
1917  *   Pointer to flow attributes
1918  * @param[out] error
1919  *   Pointer to error structure.
1920  *
1921  * @return
1922  *   0 on success, a negative errno value otherwise and rte_errno is set.
1923  */
1924 static int
1925 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
1926                                 const struct rte_flow_action *action,
1927                                 uint64_t action_flags,
1928                                 const struct rte_flow_attr *attr,
1929                                 struct rte_flow_error *error)
1930 {
1931         const struct rte_flow_action_set_tag *conf;
1932         const uint64_t terminal_action_flags =
1933                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
1934                 MLX5_FLOW_ACTION_RSS;
1935         int ret;
1936
1937         if (!mlx5_flow_ext_mreg_supported(dev))
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1940                                           "extensive metadata register"
1941                                           " isn't supported");
1942         if (!(action->conf))
1943                 return rte_flow_error_set(error, EINVAL,
1944                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1945                                           "configuration cannot be null");
1946         conf = (const struct rte_flow_action_set_tag *)action->conf;
1947         if (!conf->mask)
1948                 return rte_flow_error_set(error, EINVAL,
1949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1950                                           "zero mask doesn't have any effect");
1951         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1952         if (ret < 0)
1953                 return ret;
1954         if (!attr->transfer && attr->ingress &&
1955             (action_flags & terminal_action_flags))
1956                 return rte_flow_error_set(error, EINVAL,
1957                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1958                                           "set_tag has no effect"
1959                                           " with terminal actions");
1960         return 0;
1961 }
1962
1963 /**
1964  * Validate count action.
1965  *
1966  * @param[in] dev
1967  *   device otr.
1968  * @param[out] error
1969  *   Pointer to error structure.
1970  *
1971  * @return
1972  *   0 on success, a negative errno value otherwise and rte_errno is set.
1973  */
1974 static int
1975 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1976                               struct rte_flow_error *error)
1977 {
1978         struct mlx5_priv *priv = dev->data->dev_private;
1979
1980         if (!priv->config.devx)
1981                 goto notsup_err;
1982 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1983         return 0;
1984 #endif
1985 notsup_err:
1986         return rte_flow_error_set
1987                       (error, ENOTSUP,
1988                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1989                        NULL,
1990                        "count action not supported");
1991 }
1992
1993 /**
1994  * Validate the L2 encap action.
1995  *
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] action
1999  *   Pointer to the encap action.
2000  * @param[in] attr
2001  *   Pointer to flow attributes
2002  * @param[out] error
2003  *   Pointer to error structure.
2004  *
2005  * @return
2006  *   0 on success, a negative errno value otherwise and rte_errno is set.
2007  */
2008 static int
2009 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2010                                  const struct rte_flow_action *action,
2011                                  const struct rte_flow_attr *attr,
2012                                  struct rte_flow_error *error)
2013 {
2014         if (!(action->conf))
2015                 return rte_flow_error_set(error, EINVAL,
2016                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2017                                           "configuration cannot be null");
2018         if (action_flags & MLX5_FLOW_ACTION_DROP)
2019                 return rte_flow_error_set(error, EINVAL,
2020                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2021                                           "can't drop and encap in same flow");
2022         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2023                 return rte_flow_error_set(error, EINVAL,
2024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2025                                           "can only have a single encap or"
2026                                           " decap action in a flow");
2027         if (!attr->transfer && attr->ingress)
2028                 return rte_flow_error_set(error, ENOTSUP,
2029                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2030                                           NULL,
2031                                           "encap action not supported for "
2032                                           "ingress");
2033         return 0;
2034 }
2035
2036 /**
2037  * Validate the L2 decap action.
2038  *
2039  * @param[in] action_flags
2040  *   Holds the actions detected until now.
2041  * @param[in] attr
2042  *   Pointer to flow attributes
2043  * @param[out] error
2044  *   Pointer to error structure.
2045  *
2046  * @return
2047  *   0 on success, a negative errno value otherwise and rte_errno is set.
2048  */
2049 static int
2050 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2051                                  const struct rte_flow_attr *attr,
2052                                  struct rte_flow_error *error)
2053 {
2054         if (action_flags & MLX5_FLOW_ACTION_DROP)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2057                                           "can't drop and decap in same flow");
2058         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2059                 return rte_flow_error_set(error, EINVAL,
2060                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2061                                           "can only have a single encap or"
2062                                           " decap action in a flow");
2063         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2064                 return rte_flow_error_set(error, EINVAL,
2065                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2066                                           "can't have decap action after"
2067                                           " modify action");
2068         if (attr->egress)
2069                 return rte_flow_error_set(error, ENOTSUP,
2070                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2071                                           NULL,
2072                                           "decap action not supported for "
2073                                           "egress");
2074         return 0;
2075 }
2076
2077 /**
2078  * Validate the raw encap action.
2079  *
2080  * @param[in] action_flags
2081  *   Holds the actions detected until now.
2082  * @param[in] action
2083  *   Pointer to the encap action.
2084  * @param[in] attr
2085  *   Pointer to flow attributes
2086  * @param[out] error
2087  *   Pointer to error structure.
2088  *
2089  * @return
2090  *   0 on success, a negative errno value otherwise and rte_errno is set.
2091  */
2092 static int
2093 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2094                                   const struct rte_flow_action *action,
2095                                   const struct rte_flow_attr *attr,
2096                                   struct rte_flow_error *error)
2097 {
2098         const struct rte_flow_action_raw_encap *raw_encap =
2099                 (const struct rte_flow_action_raw_encap *)action->conf;
2100         if (!(action->conf))
2101                 return rte_flow_error_set(error, EINVAL,
2102                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2103                                           "configuration cannot be null");
2104         if (action_flags & MLX5_FLOW_ACTION_DROP)
2105                 return rte_flow_error_set(error, EINVAL,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2107                                           "can't drop and encap in same flow");
2108         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2109                 return rte_flow_error_set(error, EINVAL,
2110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111                                           "can only have a single encap"
2112                                           " action in a flow");
2113         /* encap without preceding decap is not supported for ingress */
2114         if (!attr->transfer &&  attr->ingress &&
2115             !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2116                 return rte_flow_error_set(error, ENOTSUP,
2117                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2118                                           NULL,
2119                                           "encap action not supported for "
2120                                           "ingress");
2121         if (!raw_encap->size || !raw_encap->data)
2122                 return rte_flow_error_set(error, EINVAL,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2124                                           "raw encap data cannot be empty");
2125         return 0;
2126 }
2127
2128 /**
2129  * Validate the raw decap action.
2130  *
2131  * @param[in] action_flags
2132  *   Holds the actions detected until now.
2133  * @param[in] action
2134  *   Pointer to the encap action.
2135  * @param[in] attr
2136  *   Pointer to flow attributes
2137  * @param[out] error
2138  *   Pointer to error structure.
2139  *
2140  * @return
2141  *   0 on success, a negative errno value otherwise and rte_errno is set.
2142  */
2143 static int
2144 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2145                                   const struct rte_flow_action *action,
2146                                   const struct rte_flow_attr *attr,
2147                                   struct rte_flow_error *error)
2148 {
2149         if (action_flags & MLX5_FLOW_ACTION_DROP)
2150                 return rte_flow_error_set(error, EINVAL,
2151                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2152                                           "can't drop and decap in same flow");
2153         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2154                 return rte_flow_error_set(error, EINVAL,
2155                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2156                                           "can't have encap action before"
2157                                           " decap action");
2158         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2159                 return rte_flow_error_set(error, EINVAL,
2160                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2161                                           "can only have a single decap"
2162                                           " action in a flow");
2163         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2164                 return rte_flow_error_set(error, EINVAL,
2165                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2166                                           "can't have decap action after"
2167                                           " modify action");
2168         /* decap action is valid on egress only if it is followed by encap */
2169         if (attr->egress) {
2170                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
2171                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
2172                        action++) {
2173                 }
2174                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
2175                         return rte_flow_error_set
2176                                         (error, ENOTSUP,
2177                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2178                                          NULL, "decap action not supported"
2179                                          " for egress");
2180         }
2181         return 0;
2182 }
2183
2184 /**
2185  * Find existing encap/decap resource or create and register a new one.
2186  *
2187  * @param dev[in, out]
2188  *   Pointer to rte_eth_dev structure.
2189  * @param[in, out] resource
2190  *   Pointer to encap/decap resource.
2191  * @parm[in, out] dev_flow
2192  *   Pointer to the dev_flow.
2193  * @param[out] error
2194  *   pointer to error structure.
2195  *
2196  * @return
2197  *   0 on success otherwise -errno and errno is set.
2198  */
2199 static int
2200 flow_dv_encap_decap_resource_register
2201                         (struct rte_eth_dev *dev,
2202                          struct mlx5_flow_dv_encap_decap_resource *resource,
2203                          struct mlx5_flow *dev_flow,
2204                          struct rte_flow_error *error)
2205 {
2206         struct mlx5_priv *priv = dev->data->dev_private;
2207         struct mlx5_ibv_shared *sh = priv->sh;
2208         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2209         struct mlx5dv_dr_domain *domain;
2210
2211         resource->flags = dev_flow->group ? 0 : 1;
2212         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2213                 domain = sh->fdb_domain;
2214         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2215                 domain = sh->rx_domain;
2216         else
2217                 domain = sh->tx_domain;
2218
2219         /* Lookup a matching resource from cache. */
2220         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2221                 if (resource->reformat_type == cache_resource->reformat_type &&
2222                     resource->ft_type == cache_resource->ft_type &&
2223                     resource->flags == cache_resource->flags &&
2224                     resource->size == cache_resource->size &&
2225                     !memcmp((const void *)resource->buf,
2226                             (const void *)cache_resource->buf,
2227                             resource->size)) {
2228                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2229                                 (void *)cache_resource,
2230                                 rte_atomic32_read(&cache_resource->refcnt));
2231                         rte_atomic32_inc(&cache_resource->refcnt);
2232                         dev_flow->dv.encap_decap = cache_resource;
2233                         return 0;
2234                 }
2235         }
2236         /* Register new encap/decap resource. */
2237         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2238         if (!cache_resource)
2239                 return rte_flow_error_set(error, ENOMEM,
2240                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2241                                           "cannot allocate resource memory");
2242         *cache_resource = *resource;
2243         cache_resource->verbs_action =
2244                 mlx5_glue->dv_create_flow_action_packet_reformat
2245                         (sh->ctx, cache_resource->reformat_type,
2246                          cache_resource->ft_type, domain, cache_resource->flags,
2247                          cache_resource->size,
2248                          (cache_resource->size ? cache_resource->buf : NULL));
2249         if (!cache_resource->verbs_action) {
2250                 rte_free(cache_resource);
2251                 return rte_flow_error_set(error, ENOMEM,
2252                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2253                                           NULL, "cannot create action");
2254         }
2255         rte_atomic32_init(&cache_resource->refcnt);
2256         rte_atomic32_inc(&cache_resource->refcnt);
2257         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2258         dev_flow->dv.encap_decap = cache_resource;
2259         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2260                 (void *)cache_resource,
2261                 rte_atomic32_read(&cache_resource->refcnt));
2262         return 0;
2263 }
2264
2265 /**
2266  * Find existing table jump resource or create and register a new one.
2267  *
2268  * @param dev[in, out]
2269  *   Pointer to rte_eth_dev structure.
2270  * @param[in, out] resource
2271  *   Pointer to jump table resource.
2272  * @parm[in, out] dev_flow
2273  *   Pointer to the dev_flow.
2274  * @param[out] error
2275  *   pointer to error structure.
2276  *
2277  * @return
2278  *   0 on success otherwise -errno and errno is set.
2279  */
2280 static int
2281 flow_dv_jump_tbl_resource_register
2282                         (struct rte_eth_dev *dev,
2283                          struct mlx5_flow_dv_jump_tbl_resource *resource,
2284                          struct mlx5_flow *dev_flow,
2285                          struct rte_flow_error *error)
2286 {
2287         struct mlx5_priv *priv = dev->data->dev_private;
2288         struct mlx5_ibv_shared *sh = priv->sh;
2289         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
2290
2291         /* Lookup a matching resource from cache. */
2292         LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
2293                 if (resource->tbl == cache_resource->tbl) {
2294                         DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
2295                                 (void *)cache_resource,
2296                                 rte_atomic32_read(&cache_resource->refcnt));
2297                         rte_atomic32_inc(&cache_resource->refcnt);
2298                         dev_flow->dv.jump = cache_resource;
2299                         return 0;
2300                 }
2301         }
2302         /* Register new jump table resource. */
2303         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2304         if (!cache_resource)
2305                 return rte_flow_error_set(error, ENOMEM,
2306                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2307                                           "cannot allocate resource memory");
2308         *cache_resource = *resource;
2309         cache_resource->action =
2310                 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2311                 (resource->tbl->obj);
2312         if (!cache_resource->action) {
2313                 rte_free(cache_resource);
2314                 return rte_flow_error_set(error, ENOMEM,
2315                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2316                                           NULL, "cannot create action");
2317         }
2318         rte_atomic32_init(&cache_resource->refcnt);
2319         rte_atomic32_inc(&cache_resource->refcnt);
2320         LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
2321         dev_flow->dv.jump = cache_resource;
2322         DRV_LOG(DEBUG, "new jump table  resource %p: refcnt %d++",
2323                 (void *)cache_resource,
2324                 rte_atomic32_read(&cache_resource->refcnt));
2325         return 0;
2326 }
2327
2328 /**
2329  * Find existing table port ID resource or create and register a new one.
2330  *
2331  * @param dev[in, out]
2332  *   Pointer to rte_eth_dev structure.
2333  * @param[in, out] resource
2334  *   Pointer to port ID action resource.
2335  * @parm[in, out] dev_flow
2336  *   Pointer to the dev_flow.
2337  * @param[out] error
2338  *   pointer to error structure.
2339  *
2340  * @return
2341  *   0 on success otherwise -errno and errno is set.
2342  */
2343 static int
2344 flow_dv_port_id_action_resource_register
2345                         (struct rte_eth_dev *dev,
2346                          struct mlx5_flow_dv_port_id_action_resource *resource,
2347                          struct mlx5_flow *dev_flow,
2348                          struct rte_flow_error *error)
2349 {
2350         struct mlx5_priv *priv = dev->data->dev_private;
2351         struct mlx5_ibv_shared *sh = priv->sh;
2352         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2353
2354         /* Lookup a matching resource from cache. */
2355         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2356                 if (resource->port_id == cache_resource->port_id) {
2357                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2358                                 "refcnt %d++",
2359                                 (void *)cache_resource,
2360                                 rte_atomic32_read(&cache_resource->refcnt));
2361                         rte_atomic32_inc(&cache_resource->refcnt);
2362                         dev_flow->dv.port_id_action = cache_resource;
2363                         return 0;
2364                 }
2365         }
2366         /* Register new port id action resource. */
2367         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2368         if (!cache_resource)
2369                 return rte_flow_error_set(error, ENOMEM,
2370                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2371                                           "cannot allocate resource memory");
2372         *cache_resource = *resource;
2373         cache_resource->action =
2374                 mlx5_glue->dr_create_flow_action_dest_vport
2375                         (priv->sh->fdb_domain, resource->port_id);
2376         if (!cache_resource->action) {
2377                 rte_free(cache_resource);
2378                 return rte_flow_error_set(error, ENOMEM,
2379                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2380                                           NULL, "cannot create action");
2381         }
2382         rte_atomic32_init(&cache_resource->refcnt);
2383         rte_atomic32_inc(&cache_resource->refcnt);
2384         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2385         dev_flow->dv.port_id_action = cache_resource;
2386         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2387                 (void *)cache_resource,
2388                 rte_atomic32_read(&cache_resource->refcnt));
2389         return 0;
2390 }
2391
2392 /**
2393  * Find existing push vlan resource or create and register a new one.
2394  *
2395  * @param dev[in, out]
2396  *   Pointer to rte_eth_dev structure.
2397  * @param[in, out] resource
2398  *   Pointer to port ID action resource.
2399  * @parm[in, out] dev_flow
2400  *   Pointer to the dev_flow.
2401  * @param[out] error
2402  *   pointer to error structure.
2403  *
2404  * @return
2405  *   0 on success otherwise -errno and errno is set.
2406  */
2407 static int
2408 flow_dv_push_vlan_action_resource_register
2409                        (struct rte_eth_dev *dev,
2410                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2411                         struct mlx5_flow *dev_flow,
2412                         struct rte_flow_error *error)
2413 {
2414         struct mlx5_priv *priv = dev->data->dev_private;
2415         struct mlx5_ibv_shared *sh = priv->sh;
2416         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2417         struct mlx5dv_dr_domain *domain;
2418
2419         /* Lookup a matching resource from cache. */
2420         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2421                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2422                     resource->ft_type == cache_resource->ft_type) {
2423                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2424                                 "refcnt %d++",
2425                                 (void *)cache_resource,
2426                                 rte_atomic32_read(&cache_resource->refcnt));
2427                         rte_atomic32_inc(&cache_resource->refcnt);
2428                         dev_flow->dv.push_vlan_res = cache_resource;
2429                         return 0;
2430                 }
2431         }
2432         /* Register new push_vlan action resource. */
2433         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2434         if (!cache_resource)
2435                 return rte_flow_error_set(error, ENOMEM,
2436                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2437                                           "cannot allocate resource memory");
2438         *cache_resource = *resource;
2439         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2440                 domain = sh->fdb_domain;
2441         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2442                 domain = sh->rx_domain;
2443         else
2444                 domain = sh->tx_domain;
2445         cache_resource->action =
2446                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2447                                                            resource->vlan_tag);
2448         if (!cache_resource->action) {
2449                 rte_free(cache_resource);
2450                 return rte_flow_error_set(error, ENOMEM,
2451                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2452                                           NULL, "cannot create action");
2453         }
2454         rte_atomic32_init(&cache_resource->refcnt);
2455         rte_atomic32_inc(&cache_resource->refcnt);
2456         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2457         dev_flow->dv.push_vlan_res = cache_resource;
2458         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2459                 (void *)cache_resource,
2460                 rte_atomic32_read(&cache_resource->refcnt));
2461         return 0;
2462 }
2463 /**
2464  * Get the size of specific rte_flow_item_type
2465  *
2466  * @param[in] item_type
2467  *   Tested rte_flow_item_type.
2468  *
2469  * @return
2470  *   sizeof struct item_type, 0 if void or irrelevant.
2471  */
2472 static size_t
2473 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2474 {
2475         size_t retval;
2476
2477         switch (item_type) {
2478         case RTE_FLOW_ITEM_TYPE_ETH:
2479                 retval = sizeof(struct rte_flow_item_eth);
2480                 break;
2481         case RTE_FLOW_ITEM_TYPE_VLAN:
2482                 retval = sizeof(struct rte_flow_item_vlan);
2483                 break;
2484         case RTE_FLOW_ITEM_TYPE_IPV4:
2485                 retval = sizeof(struct rte_flow_item_ipv4);
2486                 break;
2487         case RTE_FLOW_ITEM_TYPE_IPV6:
2488                 retval = sizeof(struct rte_flow_item_ipv6);
2489                 break;
2490         case RTE_FLOW_ITEM_TYPE_UDP:
2491                 retval = sizeof(struct rte_flow_item_udp);
2492                 break;
2493         case RTE_FLOW_ITEM_TYPE_TCP:
2494                 retval = sizeof(struct rte_flow_item_tcp);
2495                 break;
2496         case RTE_FLOW_ITEM_TYPE_VXLAN:
2497                 retval = sizeof(struct rte_flow_item_vxlan);
2498                 break;
2499         case RTE_FLOW_ITEM_TYPE_GRE:
2500                 retval = sizeof(struct rte_flow_item_gre);
2501                 break;
2502         case RTE_FLOW_ITEM_TYPE_NVGRE:
2503                 retval = sizeof(struct rte_flow_item_nvgre);
2504                 break;
2505         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2506                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2507                 break;
2508         case RTE_FLOW_ITEM_TYPE_MPLS:
2509                 retval = sizeof(struct rte_flow_item_mpls);
2510                 break;
2511         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2512         default:
2513                 retval = 0;
2514                 break;
2515         }
2516         return retval;
2517 }
2518
2519 #define MLX5_ENCAP_IPV4_VERSION         0x40
2520 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2521 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2522 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2523 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2524 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2525 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2526
2527 /**
2528  * Convert the encap action data from list of rte_flow_item to raw buffer
2529  *
2530  * @param[in] items
2531  *   Pointer to rte_flow_item objects list.
2532  * @param[out] buf
2533  *   Pointer to the output buffer.
2534  * @param[out] size
2535  *   Pointer to the output buffer size.
2536  * @param[out] error
2537  *   Pointer to the error structure.
2538  *
2539  * @return
2540  *   0 on success, a negative errno value otherwise and rte_errno is set.
2541  */
2542 static int
2543 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2544                            size_t *size, struct rte_flow_error *error)
2545 {
2546         struct rte_ether_hdr *eth = NULL;
2547         struct rte_vlan_hdr *vlan = NULL;
2548         struct rte_ipv4_hdr *ipv4 = NULL;
2549         struct rte_ipv6_hdr *ipv6 = NULL;
2550         struct rte_udp_hdr *udp = NULL;
2551         struct rte_vxlan_hdr *vxlan = NULL;
2552         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2553         struct rte_gre_hdr *gre = NULL;
2554         size_t len;
2555         size_t temp_size = 0;
2556
2557         if (!items)
2558                 return rte_flow_error_set(error, EINVAL,
2559                                           RTE_FLOW_ERROR_TYPE_ACTION,
2560                                           NULL, "invalid empty data");
2561         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2562                 len = flow_dv_get_item_len(items->type);
2563                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2564                         return rte_flow_error_set(error, EINVAL,
2565                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2566                                                   (void *)items->type,
2567                                                   "items total size is too big"
2568                                                   " for encap action");
2569                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2570                 switch (items->type) {
2571                 case RTE_FLOW_ITEM_TYPE_ETH:
2572                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2573                         break;
2574                 case RTE_FLOW_ITEM_TYPE_VLAN:
2575                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2576                         if (!eth)
2577                                 return rte_flow_error_set(error, EINVAL,
2578                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2579                                                 (void *)items->type,
2580                                                 "eth header not found");
2581                         if (!eth->ether_type)
2582                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2583                         break;
2584                 case RTE_FLOW_ITEM_TYPE_IPV4:
2585                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2586                         if (!vlan && !eth)
2587                                 return rte_flow_error_set(error, EINVAL,
2588                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2589                                                 (void *)items->type,
2590                                                 "neither eth nor vlan"
2591                                                 " header found");
2592                         if (vlan && !vlan->eth_proto)
2593                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2594                         else if (eth && !eth->ether_type)
2595                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2596                         if (!ipv4->version_ihl)
2597                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2598                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2599                         if (!ipv4->time_to_live)
2600                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2601                         break;
2602                 case RTE_FLOW_ITEM_TYPE_IPV6:
2603                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2604                         if (!vlan && !eth)
2605                                 return rte_flow_error_set(error, EINVAL,
2606                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2607                                                 (void *)items->type,
2608                                                 "neither eth nor vlan"
2609                                                 " header found");
2610                         if (vlan && !vlan->eth_proto)
2611                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2612                         else if (eth && !eth->ether_type)
2613                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2614                         if (!ipv6->vtc_flow)
2615                                 ipv6->vtc_flow =
2616                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2617                         if (!ipv6->hop_limits)
2618                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2619                         break;
2620                 case RTE_FLOW_ITEM_TYPE_UDP:
2621                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2622                         if (!ipv4 && !ipv6)
2623                                 return rte_flow_error_set(error, EINVAL,
2624                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2625                                                 (void *)items->type,
2626                                                 "ip header not found");
2627                         if (ipv4 && !ipv4->next_proto_id)
2628                                 ipv4->next_proto_id = IPPROTO_UDP;
2629                         else if (ipv6 && !ipv6->proto)
2630                                 ipv6->proto = IPPROTO_UDP;
2631                         break;
2632                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2633                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2634                         if (!udp)
2635                                 return rte_flow_error_set(error, EINVAL,
2636                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2637                                                 (void *)items->type,
2638                                                 "udp header not found");
2639                         if (!udp->dst_port)
2640                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2641                         if (!vxlan->vx_flags)
2642                                 vxlan->vx_flags =
2643                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2644                         break;
2645                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2646                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2647                         if (!udp)
2648                                 return rte_flow_error_set(error, EINVAL,
2649                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2650                                                 (void *)items->type,
2651                                                 "udp header not found");
2652                         if (!vxlan_gpe->proto)
2653                                 return rte_flow_error_set(error, EINVAL,
2654                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2655                                                 (void *)items->type,
2656                                                 "next protocol not found");
2657                         if (!udp->dst_port)
2658                                 udp->dst_port =
2659                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2660                         if (!vxlan_gpe->vx_flags)
2661                                 vxlan_gpe->vx_flags =
2662                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2663                         break;
2664                 case RTE_FLOW_ITEM_TYPE_GRE:
2665                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2666                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2667                         if (!gre->proto)
2668                                 return rte_flow_error_set(error, EINVAL,
2669                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2670                                                 (void *)items->type,
2671                                                 "next protocol not found");
2672                         if (!ipv4 && !ipv6)
2673                                 return rte_flow_error_set(error, EINVAL,
2674                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2675                                                 (void *)items->type,
2676                                                 "ip header not found");
2677                         if (ipv4 && !ipv4->next_proto_id)
2678                                 ipv4->next_proto_id = IPPROTO_GRE;
2679                         else if (ipv6 && !ipv6->proto)
2680                                 ipv6->proto = IPPROTO_GRE;
2681                         break;
2682                 case RTE_FLOW_ITEM_TYPE_VOID:
2683                         break;
2684                 default:
2685                         return rte_flow_error_set(error, EINVAL,
2686                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2687                                                   (void *)items->type,
2688                                                   "unsupported item type");
2689                         break;
2690                 }
2691                 temp_size += len;
2692         }
2693         *size = temp_size;
2694         return 0;
2695 }
2696
2697 static int
2698 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2699 {
2700         struct rte_ether_hdr *eth = NULL;
2701         struct rte_vlan_hdr *vlan = NULL;
2702         struct rte_ipv6_hdr *ipv6 = NULL;
2703         struct rte_udp_hdr *udp = NULL;
2704         char *next_hdr;
2705         uint16_t proto;
2706
2707         eth = (struct rte_ether_hdr *)data;
2708         next_hdr = (char *)(eth + 1);
2709         proto = RTE_BE16(eth->ether_type);
2710
2711         /* VLAN skipping */
2712         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2713                 vlan = (struct rte_vlan_hdr *)next_hdr;
2714                 proto = RTE_BE16(vlan->eth_proto);
2715                 next_hdr += sizeof(struct rte_vlan_hdr);
2716         }
2717
2718         /* HW calculates IPv4 csum. no need to proceed */
2719         if (proto == RTE_ETHER_TYPE_IPV4)
2720                 return 0;
2721
2722         /* non IPv4/IPv6 header. not supported */
2723         if (proto != RTE_ETHER_TYPE_IPV6) {
2724                 return rte_flow_error_set(error, ENOTSUP,
2725                                           RTE_FLOW_ERROR_TYPE_ACTION,
2726                                           NULL, "Cannot offload non IPv4/IPv6");
2727         }
2728
2729         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2730
2731         /* ignore non UDP */
2732         if (ipv6->proto != IPPROTO_UDP)
2733                 return 0;
2734
2735         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2736         udp->dgram_cksum = 0;
2737
2738         return 0;
2739 }
2740
2741 /**
2742  * Convert L2 encap action to DV specification.
2743  *
2744  * @param[in] dev
2745  *   Pointer to rte_eth_dev structure.
2746  * @param[in] action
2747  *   Pointer to action structure.
2748  * @param[in, out] dev_flow
2749  *   Pointer to the mlx5_flow.
2750  * @param[in] transfer
2751  *   Mark if the flow is E-Switch flow.
2752  * @param[out] error
2753  *   Pointer to the error structure.
2754  *
2755  * @return
2756  *   0 on success, a negative errno value otherwise and rte_errno is set.
2757  */
2758 static int
2759 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2760                                const struct rte_flow_action *action,
2761                                struct mlx5_flow *dev_flow,
2762                                uint8_t transfer,
2763                                struct rte_flow_error *error)
2764 {
2765         const struct rte_flow_item *encap_data;
2766         const struct rte_flow_action_raw_encap *raw_encap_data;
2767         struct mlx5_flow_dv_encap_decap_resource res = {
2768                 .reformat_type =
2769                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2770                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2771                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2772         };
2773
2774         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2775                 raw_encap_data =
2776                         (const struct rte_flow_action_raw_encap *)action->conf;
2777                 res.size = raw_encap_data->size;
2778                 memcpy(res.buf, raw_encap_data->data, res.size);
2779                 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2780                         return -rte_errno;
2781         } else {
2782                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2783                         encap_data =
2784                                 ((const struct rte_flow_action_vxlan_encap *)
2785                                                 action->conf)->definition;
2786                 else
2787                         encap_data =
2788                                 ((const struct rte_flow_action_nvgre_encap *)
2789                                                 action->conf)->definition;
2790                 if (flow_dv_convert_encap_data(encap_data, res.buf,
2791                                                &res.size, error))
2792                         return -rte_errno;
2793         }
2794         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2795                 return rte_flow_error_set(error, EINVAL,
2796                                           RTE_FLOW_ERROR_TYPE_ACTION,
2797                                           NULL, "can't create L2 encap action");
2798         return 0;
2799 }
2800
2801 /**
2802  * Convert L2 decap action to DV specification.
2803  *
2804  * @param[in] dev
2805  *   Pointer to rte_eth_dev structure.
2806  * @param[in, out] dev_flow
2807  *   Pointer to the mlx5_flow.
2808  * @param[in] transfer
2809  *   Mark if the flow is E-Switch flow.
2810  * @param[out] error
2811  *   Pointer to the error structure.
2812  *
2813  * @return
2814  *   0 on success, a negative errno value otherwise and rte_errno is set.
2815  */
2816 static int
2817 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2818                                struct mlx5_flow *dev_flow,
2819                                uint8_t transfer,
2820                                struct rte_flow_error *error)
2821 {
2822         struct mlx5_flow_dv_encap_decap_resource res = {
2823                 .size = 0,
2824                 .reformat_type =
2825                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2826                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2827                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2828         };
2829
2830         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2831                 return rte_flow_error_set(error, EINVAL,
2832                                           RTE_FLOW_ERROR_TYPE_ACTION,
2833                                           NULL, "can't create L2 decap action");
2834         return 0;
2835 }
2836
2837 /**
2838  * Convert raw decap/encap (L3 tunnel) action to DV specification.
2839  *
2840  * @param[in] dev
2841  *   Pointer to rte_eth_dev structure.
2842  * @param[in] action
2843  *   Pointer to action structure.
2844  * @param[in, out] dev_flow
2845  *   Pointer to the mlx5_flow.
2846  * @param[in] attr
2847  *   Pointer to the flow attributes.
2848  * @param[out] error
2849  *   Pointer to the error structure.
2850  *
2851  * @return
2852  *   0 on success, a negative errno value otherwise and rte_errno is set.
2853  */
2854 static int
2855 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2856                                 const struct rte_flow_action *action,
2857                                 struct mlx5_flow *dev_flow,
2858                                 const struct rte_flow_attr *attr,
2859                                 struct rte_flow_error *error)
2860 {
2861         const struct rte_flow_action_raw_encap *encap_data;
2862         struct mlx5_flow_dv_encap_decap_resource res;
2863
2864         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2865         res.size = encap_data->size;
2866         memcpy(res.buf, encap_data->data, res.size);
2867         res.reformat_type = attr->egress ?
2868                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2869                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2870         if (attr->transfer)
2871                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2872         else
2873                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2874                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2875         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2876                 return rte_flow_error_set(error, EINVAL,
2877                                           RTE_FLOW_ERROR_TYPE_ACTION,
2878                                           NULL, "can't create encap action");
2879         return 0;
2880 }
2881
2882 /**
2883  * Create action push VLAN.
2884  *
2885  * @param[in] dev
2886  *   Pointer to rte_eth_dev structure.
2887  * @param[in] vlan_tag
2888  *   the vlan tag to push to the Ethernet header.
2889  * @param[in, out] dev_flow
2890  *   Pointer to the mlx5_flow.
2891  * @param[in] attr
2892  *   Pointer to the flow attributes.
2893  * @param[out] error
2894  *   Pointer to the error structure.
2895  *
2896  * @return
2897  *   0 on success, a negative errno value otherwise and rte_errno is set.
2898  */
2899 static int
2900 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2901                                 const struct rte_flow_attr *attr,
2902                                 const struct rte_vlan_hdr *vlan,
2903                                 struct mlx5_flow *dev_flow,
2904                                 struct rte_flow_error *error)
2905 {
2906         struct mlx5_flow_dv_push_vlan_action_resource res;
2907
2908         res.vlan_tag =
2909                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2910                                  vlan->vlan_tci);
2911         if (attr->transfer)
2912                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2913         else
2914                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2915                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2916         return flow_dv_push_vlan_action_resource_register
2917                                             (dev, &res, dev_flow, error);
2918 }
2919
2920 /**
2921  * Validate the modify-header actions.
2922  *
2923  * @param[in] action_flags
2924  *   Holds the actions detected until now.
2925  * @param[in] action
2926  *   Pointer to the modify action.
2927  * @param[out] error
2928  *   Pointer to error structure.
2929  *
2930  * @return
2931  *   0 on success, a negative errno value otherwise and rte_errno is set.
2932  */
2933 static int
2934 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2935                                    const struct rte_flow_action *action,
2936                                    struct rte_flow_error *error)
2937 {
2938         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2939                 return rte_flow_error_set(error, EINVAL,
2940                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2941                                           NULL, "action configuration not set");
2942         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2943                 return rte_flow_error_set(error, EINVAL,
2944                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2945                                           "can't have encap action before"
2946                                           " modify action");
2947         return 0;
2948 }
2949
2950 /**
2951  * Validate the modify-header MAC address actions.
2952  *
2953  * @param[in] action_flags
2954  *   Holds the actions detected until now.
2955  * @param[in] action
2956  *   Pointer to the modify action.
2957  * @param[in] item_flags
2958  *   Holds the items detected.
2959  * @param[out] error
2960  *   Pointer to error structure.
2961  *
2962  * @return
2963  *   0 on success, a negative errno value otherwise and rte_errno is set.
2964  */
2965 static int
2966 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2967                                    const struct rte_flow_action *action,
2968                                    const uint64_t item_flags,
2969                                    struct rte_flow_error *error)
2970 {
2971         int ret = 0;
2972
2973         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2974         if (!ret) {
2975                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2976                         return rte_flow_error_set(error, EINVAL,
2977                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2978                                                   NULL,
2979                                                   "no L2 item in pattern");
2980         }
2981         return ret;
2982 }
2983
2984 /**
2985  * Validate the modify-header IPv4 address actions.
2986  *
2987  * @param[in] action_flags
2988  *   Holds the actions detected until now.
2989  * @param[in] action
2990  *   Pointer to the modify action.
2991  * @param[in] item_flags
2992  *   Holds the items detected.
2993  * @param[out] error
2994  *   Pointer to error structure.
2995  *
2996  * @return
2997  *   0 on success, a negative errno value otherwise and rte_errno is set.
2998  */
2999 static int
3000 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3001                                     const struct rte_flow_action *action,
3002                                     const uint64_t item_flags,
3003                                     struct rte_flow_error *error)
3004 {
3005         int ret = 0;
3006
3007         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3008         if (!ret) {
3009                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3010                         return rte_flow_error_set(error, EINVAL,
3011                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3012                                                   NULL,
3013                                                   "no ipv4 item in pattern");
3014         }
3015         return ret;
3016 }
3017
3018 /**
3019  * Validate the modify-header IPv6 address actions.
3020  *
3021  * @param[in] action_flags
3022  *   Holds the actions detected until now.
3023  * @param[in] action
3024  *   Pointer to the modify action.
3025  * @param[in] item_flags
3026  *   Holds the items detected.
3027  * @param[out] error
3028  *   Pointer to error structure.
3029  *
3030  * @return
3031  *   0 on success, a negative errno value otherwise and rte_errno is set.
3032  */
3033 static int
3034 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3035                                     const struct rte_flow_action *action,
3036                                     const uint64_t item_flags,
3037                                     struct rte_flow_error *error)
3038 {
3039         int ret = 0;
3040
3041         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3042         if (!ret) {
3043                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3044                         return rte_flow_error_set(error, EINVAL,
3045                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3046                                                   NULL,
3047                                                   "no ipv6 item in pattern");
3048         }
3049         return ret;
3050 }
3051
3052 /**
3053  * Validate the modify-header TP actions.
3054  *
3055  * @param[in] action_flags
3056  *   Holds the actions detected until now.
3057  * @param[in] action
3058  *   Pointer to the modify action.
3059  * @param[in] item_flags
3060  *   Holds the items detected.
3061  * @param[out] error
3062  *   Pointer to error structure.
3063  *
3064  * @return
3065  *   0 on success, a negative errno value otherwise and rte_errno is set.
3066  */
3067 static int
3068 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3069                                   const struct rte_flow_action *action,
3070                                   const uint64_t item_flags,
3071                                   struct rte_flow_error *error)
3072 {
3073         int ret = 0;
3074
3075         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3076         if (!ret) {
3077                 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3078                         return rte_flow_error_set(error, EINVAL,
3079                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3080                                                   NULL, "no transport layer "
3081                                                   "in pattern");
3082         }
3083         return ret;
3084 }
3085
3086 /**
3087  * Validate the modify-header actions of increment/decrement
3088  * TCP Sequence-number.
3089  *
3090  * @param[in] action_flags
3091  *   Holds the actions detected until now.
3092  * @param[in] action
3093  *   Pointer to the modify action.
3094  * @param[in] item_flags
3095  *   Holds the items detected.
3096  * @param[out] error
3097  *   Pointer to error structure.
3098  *
3099  * @return
3100  *   0 on success, a negative errno value otherwise and rte_errno is set.
3101  */
3102 static int
3103 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3104                                        const struct rte_flow_action *action,
3105                                        const uint64_t item_flags,
3106                                        struct rte_flow_error *error)
3107 {
3108         int ret = 0;
3109
3110         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3111         if (!ret) {
3112                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3113                         return rte_flow_error_set(error, EINVAL,
3114                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3115                                                   NULL, "no TCP item in"
3116                                                   " pattern");
3117                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3118                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3119                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3120                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3121                         return rte_flow_error_set(error, EINVAL,
3122                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3123                                                   NULL,
3124                                                   "cannot decrease and increase"
3125                                                   " TCP sequence number"
3126                                                   " at the same time");
3127         }
3128         return ret;
3129 }
3130
3131 /**
3132  * Validate the modify-header actions of increment/decrement
3133  * TCP Acknowledgment number.
3134  *
3135  * @param[in] action_flags
3136  *   Holds the actions detected until now.
3137  * @param[in] action
3138  *   Pointer to the modify action.
3139  * @param[in] item_flags
3140  *   Holds the items detected.
3141  * @param[out] error
3142  *   Pointer to error structure.
3143  *
3144  * @return
3145  *   0 on success, a negative errno value otherwise and rte_errno is set.
3146  */
3147 static int
3148 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3149                                        const struct rte_flow_action *action,
3150                                        const uint64_t item_flags,
3151                                        struct rte_flow_error *error)
3152 {
3153         int ret = 0;
3154
3155         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3156         if (!ret) {
3157                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3158                         return rte_flow_error_set(error, EINVAL,
3159                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3160                                                   NULL, "no TCP item in"
3161                                                   " pattern");
3162                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3163                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3164                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3165                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3166                         return rte_flow_error_set(error, EINVAL,
3167                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3168                                                   NULL,
3169                                                   "cannot decrease and increase"
3170                                                   " TCP acknowledgment number"
3171                                                   " at the same time");
3172         }
3173         return ret;
3174 }
3175
3176 /**
3177  * Validate the modify-header TTL actions.
3178  *
3179  * @param[in] action_flags
3180  *   Holds the actions detected until now.
3181  * @param[in] action
3182  *   Pointer to the modify action.
3183  * @param[in] item_flags
3184  *   Holds the items detected.
3185  * @param[out] error
3186  *   Pointer to error structure.
3187  *
3188  * @return
3189  *   0 on success, a negative errno value otherwise and rte_errno is set.
3190  */
3191 static int
3192 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3193                                    const struct rte_flow_action *action,
3194                                    const uint64_t item_flags,
3195                                    struct rte_flow_error *error)
3196 {
3197         int ret = 0;
3198
3199         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3200         if (!ret) {
3201                 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3202                         return rte_flow_error_set(error, EINVAL,
3203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3204                                                   NULL,
3205                                                   "no IP protocol in pattern");
3206         }
3207         return ret;
3208 }
3209
3210 /**
3211  * Validate jump action.
3212  *
3213  * @param[in] action
3214  *   Pointer to the jump action.
3215  * @param[in] action_flags
3216  *   Holds the actions detected until now.
3217  * @param[in] attributes
3218  *   Pointer to flow attributes
3219  * @param[in] external
3220  *   Action belongs to flow rule created by request external to PMD.
3221  * @param[out] error
3222  *   Pointer to error structure.
3223  *
3224  * @return
3225  *   0 on success, a negative errno value otherwise and rte_errno is set.
3226  */
3227 static int
3228 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3229                              uint64_t action_flags,
3230                              const struct rte_flow_attr *attributes,
3231                              bool external, struct rte_flow_error *error)
3232 {
3233         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3234                                                     MLX5_MAX_TABLES;
3235         uint32_t target_group, table;
3236         int ret = 0;
3237
3238         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3239                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3240                 return rte_flow_error_set(error, EINVAL,
3241                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3242                                           "can't have 2 fate actions in"
3243                                           " same flow");
3244         if (!action->conf)
3245                 return rte_flow_error_set(error, EINVAL,
3246                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3247                                           NULL, "action configuration not set");
3248         target_group =
3249                 ((const struct rte_flow_action_jump *)action->conf)->group;
3250         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3251                                        &table, error);
3252         if (ret)
3253                 return ret;
3254         if (table >= max_group)
3255                 return rte_flow_error_set(error, EINVAL,
3256                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3257                                           "target group index out of range");
3258         if (attributes->group >= target_group)
3259                 return rte_flow_error_set(error, EINVAL,
3260                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3261                                           "target group must be higher than"
3262                                           " the current flow group");
3263         return 0;
3264 }
3265
3266 /*
3267  * Validate the port_id action.
3268  *
3269  * @param[in] dev
3270  *   Pointer to rte_eth_dev structure.
3271  * @param[in] action_flags
3272  *   Bit-fields that holds the actions detected until now.
3273  * @param[in] action
3274  *   Port_id RTE action structure.
3275  * @param[in] attr
3276  *   Attributes of flow that includes this action.
3277  * @param[out] error
3278  *   Pointer to error structure.
3279  *
3280  * @return
3281  *   0 on success, a negative errno value otherwise and rte_errno is set.
3282  */
3283 static int
3284 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3285                                 uint64_t action_flags,
3286                                 const struct rte_flow_action *action,
3287                                 const struct rte_flow_attr *attr,
3288                                 struct rte_flow_error *error)
3289 {
3290         const struct rte_flow_action_port_id *port_id;
3291         struct mlx5_priv *act_priv;
3292         struct mlx5_priv *dev_priv;
3293         uint16_t port;
3294
3295         if (!attr->transfer)
3296                 return rte_flow_error_set(error, ENOTSUP,
3297                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3298                                           NULL,
3299                                           "port id action is valid in transfer"
3300                                           " mode only");
3301         if (!action || !action->conf)
3302                 return rte_flow_error_set(error, ENOTSUP,
3303                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3304                                           NULL,
3305                                           "port id action parameters must be"
3306                                           " specified");
3307         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3308                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3309                 return rte_flow_error_set(error, EINVAL,
3310                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311                                           "can have only one fate actions in"
3312                                           " a flow");
3313         dev_priv = mlx5_dev_to_eswitch_info(dev);
3314         if (!dev_priv)
3315                 return rte_flow_error_set(error, rte_errno,
3316                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3317                                           NULL,
3318                                           "failed to obtain E-Switch info");
3319         port_id = action->conf;
3320         port = port_id->original ? dev->data->port_id : port_id->id;
3321         act_priv = mlx5_port_to_eswitch_info(port, false);
3322         if (!act_priv)
3323                 return rte_flow_error_set
3324                                 (error, rte_errno,
3325                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3326                                  "failed to obtain E-Switch port id for port");
3327         if (act_priv->domain_id != dev_priv->domain_id)
3328                 return rte_flow_error_set
3329                                 (error, EINVAL,
3330                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3331                                  "port does not belong to"
3332                                  " E-Switch being configured");
3333         return 0;
3334 }
3335
3336 /**
3337  * Get the maximum number of modify header actions.
3338  *
3339  * @param dev
3340  *   Pointer to rte_eth_dev structure.
3341  *
3342  * @return
3343  *   Max number of modify header actions device can support.
3344  */
3345 static unsigned int
3346 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
3347 {
3348         /*
3349          * There's no way to directly query the max cap. Although it has to be
3350          * acquried by iterative trial, it is a safe assumption that more
3351          * actions are supported by FW if extensive metadata register is
3352          * supported.
3353          */
3354         return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
3355                                                    MLX5_MODIFY_NUM_NO_MREG;
3356 }
3357 /**
3358  * Find existing modify-header resource or create and register a new one.
3359  *
3360  * @param dev[in, out]
3361  *   Pointer to rte_eth_dev structure.
3362  * @param[in, out] resource
3363  *   Pointer to modify-header resource.
3364  * @parm[in, out] dev_flow
3365  *   Pointer to the dev_flow.
3366  * @param[out] error
3367  *   pointer to error structure.
3368  *
3369  * @return
3370  *   0 on success otherwise -errno and errno is set.
3371  */
3372 static int
3373 flow_dv_modify_hdr_resource_register
3374                         (struct rte_eth_dev *dev,
3375                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3376                          struct mlx5_flow *dev_flow,
3377                          struct rte_flow_error *error)
3378 {
3379         struct mlx5_priv *priv = dev->data->dev_private;
3380         struct mlx5_ibv_shared *sh = priv->sh;
3381         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3382         struct mlx5dv_dr_domain *ns;
3383
3384         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
3385                 return rte_flow_error_set(error, EOVERFLOW,
3386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3387                                           "too many modify header items");
3388         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3389                 ns = sh->fdb_domain;
3390         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3391                 ns = sh->tx_domain;
3392         else
3393                 ns = sh->rx_domain;
3394         resource->flags =
3395                 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3396         /* Lookup a matching resource from cache. */
3397         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3398                 if (resource->ft_type == cache_resource->ft_type &&
3399                     resource->actions_num == cache_resource->actions_num &&
3400                     resource->flags == cache_resource->flags &&
3401                     !memcmp((const void *)resource->actions,
3402                             (const void *)cache_resource->actions,
3403                             (resource->actions_num *
3404                                             sizeof(resource->actions[0])))) {
3405                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3406                                 (void *)cache_resource,
3407                                 rte_atomic32_read(&cache_resource->refcnt));
3408                         rte_atomic32_inc(&cache_resource->refcnt);
3409                         dev_flow->dv.modify_hdr = cache_resource;
3410                         return 0;
3411                 }
3412         }
3413         /* Register new modify-header resource. */
3414         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
3415         if (!cache_resource)
3416                 return rte_flow_error_set(error, ENOMEM,
3417                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418                                           "cannot allocate resource memory");
3419         *cache_resource = *resource;
3420         cache_resource->verbs_action =
3421                 mlx5_glue->dv_create_flow_action_modify_header
3422                                         (sh->ctx, cache_resource->ft_type,
3423                                          ns, cache_resource->flags,
3424                                          cache_resource->actions_num *
3425                                          sizeof(cache_resource->actions[0]),
3426                                          (uint64_t *)cache_resource->actions);
3427         if (!cache_resource->verbs_action) {
3428                 rte_free(cache_resource);
3429                 return rte_flow_error_set(error, ENOMEM,
3430                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3431                                           NULL, "cannot create action");
3432         }
3433         rte_atomic32_init(&cache_resource->refcnt);
3434         rte_atomic32_inc(&cache_resource->refcnt);
3435         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3436         dev_flow->dv.modify_hdr = cache_resource;
3437         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3438                 (void *)cache_resource,
3439                 rte_atomic32_read(&cache_resource->refcnt));
3440         return 0;
3441 }
3442
3443 #define MLX5_CNT_CONTAINER_RESIZE 64
3444
3445 /**
3446  * Get or create a flow counter.
3447  *
3448  * @param[in] dev
3449  *   Pointer to the Ethernet device structure.
3450  * @param[in] shared
3451  *   Indicate if this counter is shared with other flows.
3452  * @param[in] id
3453  *   Counter identifier.
3454  *
3455  * @return
3456  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3457  */
3458 static struct mlx5_flow_counter *
3459 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3460                                uint32_t id)
3461 {
3462         struct mlx5_priv *priv = dev->data->dev_private;
3463         struct mlx5_flow_counter *cnt = NULL;
3464         struct mlx5_devx_obj *dcs = NULL;
3465
3466         if (!priv->config.devx) {
3467                 rte_errno = ENOTSUP;
3468                 return NULL;
3469         }
3470         if (shared) {
3471                 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3472                         if (cnt->shared && cnt->id == id) {
3473                                 cnt->ref_cnt++;
3474                                 return cnt;
3475                         }
3476                 }
3477         }
3478         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3479         if (!dcs)
3480                 return NULL;
3481         cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3482         if (!cnt) {
3483                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3484                 rte_errno = ENOMEM;
3485                 return NULL;
3486         }
3487         struct mlx5_flow_counter tmpl = {
3488                 .shared = shared,
3489                 .ref_cnt = 1,
3490                 .id = id,
3491                 .dcs = dcs,
3492         };
3493         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3494         if (!tmpl.action) {
3495                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3496                 rte_errno = errno;
3497                 rte_free(cnt);
3498                 return NULL;
3499         }
3500         *cnt = tmpl;
3501         TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3502         return cnt;
3503 }
3504
3505 /**
3506  * Release a flow counter.
3507  *
3508  * @param[in] dev
3509  *   Pointer to the Ethernet device structure.
3510  * @param[in] counter
3511  *   Pointer to the counter handler.
3512  */
3513 static void
3514 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3515                                  struct mlx5_flow_counter *counter)
3516 {
3517         struct mlx5_priv *priv = dev->data->dev_private;
3518
3519         if (!counter)
3520                 return;
3521         if (--counter->ref_cnt == 0) {
3522                 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3523                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3524                 rte_free(counter);
3525         }
3526 }
3527
3528 /**
3529  * Query a devx flow counter.
3530  *
3531  * @param[in] dev
3532  *   Pointer to the Ethernet device structure.
3533  * @param[in] cnt
3534  *   Pointer to the flow counter.
3535  * @param[out] pkts
3536  *   The statistics value of packets.
3537  * @param[out] bytes
3538  *   The statistics value of bytes.
3539  *
3540  * @return
3541  *   0 on success, otherwise a negative errno value and rte_errno is set.
3542  */
3543 static inline int
3544 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3545                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3546                      uint64_t *bytes)
3547 {
3548         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3549                                                 0, NULL, NULL, 0);
3550 }
3551
3552 /**
3553  * Get a pool by a counter.
3554  *
3555  * @param[in] cnt
3556  *   Pointer to the counter.
3557  *
3558  * @return
3559  *   The counter pool.
3560  */
3561 static struct mlx5_flow_counter_pool *
3562 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3563 {
3564         if (!cnt->batch) {
3565                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3566                 return (struct mlx5_flow_counter_pool *)cnt - 1;
3567         }
3568         return cnt->pool;
3569 }
3570
3571 /**
3572  * Get a pool by devx counter ID.
3573  *
3574  * @param[in] cont
3575  *   Pointer to the counter container.
3576  * @param[in] id
3577  *   The counter devx ID.
3578  *
3579  * @return
3580  *   The counter pool pointer if exists, NULL otherwise,
3581  */
3582 static struct mlx5_flow_counter_pool *
3583 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3584 {
3585         struct mlx5_flow_counter_pool *pool;
3586
3587         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3588                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3589                                 MLX5_COUNTERS_PER_POOL;
3590
3591                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3592                         return pool;
3593         };
3594         return NULL;
3595 }
3596
3597 /**
3598  * Allocate a new memory for the counter values wrapped by all the needed
3599  * management.
3600  *
3601  * @param[in] dev
3602  *   Pointer to the Ethernet device structure.
3603  * @param[in] raws_n
3604  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3605  *
3606  * @return
3607  *   The new memory management pointer on success, otherwise NULL and rte_errno
3608  *   is set.
3609  */
3610 static struct mlx5_counter_stats_mem_mng *
3611 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3612 {
3613         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3614                                         (dev->data->dev_private))->sh;
3615         struct mlx5_devx_mkey_attr mkey_attr;
3616         struct mlx5_counter_stats_mem_mng *mem_mng;
3617         volatile struct flow_counter_stats *raw_data;
3618         int size = (sizeof(struct flow_counter_stats) *
3619                         MLX5_COUNTERS_PER_POOL +
3620                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3621                         sizeof(struct mlx5_counter_stats_mem_mng);
3622         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3623         int i;
3624
3625         if (!mem) {
3626                 rte_errno = ENOMEM;
3627                 return NULL;
3628         }
3629         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3630         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3631         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3632                                                  IBV_ACCESS_LOCAL_WRITE);
3633         if (!mem_mng->umem) {
3634                 rte_errno = errno;
3635                 rte_free(mem);
3636                 return NULL;
3637         }
3638         mkey_attr.addr = (uintptr_t)mem;
3639         mkey_attr.size = size;
3640         mkey_attr.umem_id = mem_mng->umem->umem_id;
3641         mkey_attr.pd = sh->pdn;
3642         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3643         if (!mem_mng->dm) {
3644                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3645                 rte_errno = errno;
3646                 rte_free(mem);
3647                 return NULL;
3648         }
3649         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3650         raw_data = (volatile struct flow_counter_stats *)mem;
3651         for (i = 0; i < raws_n; ++i) {
3652                 mem_mng->raws[i].mem_mng = mem_mng;
3653                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3654         }
3655         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3656         return mem_mng;
3657 }
3658
3659 /**
3660  * Resize a counter container.
3661  *
3662  * @param[in] dev
3663  *   Pointer to the Ethernet device structure.
3664  * @param[in] batch
3665  *   Whether the pool is for counter that was allocated by batch command.
3666  *
3667  * @return
3668  *   The new container pointer on success, otherwise NULL and rte_errno is set.
3669  */
3670 static struct mlx5_pools_container *
3671 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3672 {
3673         struct mlx5_priv *priv = dev->data->dev_private;
3674         struct mlx5_pools_container *cont =
3675                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3676         struct mlx5_pools_container *new_cont =
3677                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3678         struct mlx5_counter_stats_mem_mng *mem_mng;
3679         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3680         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3681         int i;
3682
3683         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3684                 /* The last resize still hasn't detected by the host thread. */
3685                 rte_errno = EAGAIN;
3686                 return NULL;
3687         }
3688         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3689         if (!new_cont->pools) {
3690                 rte_errno = ENOMEM;
3691                 return NULL;
3692         }
3693         if (cont->n)
3694                 memcpy(new_cont->pools, cont->pools, cont->n *
3695                        sizeof(struct mlx5_flow_counter_pool *));
3696         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3697                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3698         if (!mem_mng) {
3699                 rte_free(new_cont->pools);
3700                 return NULL;
3701         }
3702         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3703                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3704                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3705                                  i, next);
3706         new_cont->n = resize;
3707         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3708         TAILQ_INIT(&new_cont->pool_list);
3709         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3710         new_cont->init_mem_mng = mem_mng;
3711         rte_cio_wmb();
3712          /* Flip the master container. */
3713         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3714         return new_cont;
3715 }
3716
3717 /**
3718  * Query a devx flow counter.
3719  *
3720  * @param[in] dev
3721  *   Pointer to the Ethernet device structure.
3722  * @param[in] cnt
3723  *   Pointer to the flow counter.
3724  * @param[out] pkts
3725  *   The statistics value of packets.
3726  * @param[out] bytes
3727  *   The statistics value of bytes.
3728  *
3729  * @return
3730  *   0 on success, otherwise a negative errno value and rte_errno is set.
3731  */
3732 static inline int
3733 _flow_dv_query_count(struct rte_eth_dev *dev,
3734                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3735                      uint64_t *bytes)
3736 {
3737         struct mlx5_priv *priv = dev->data->dev_private;
3738         struct mlx5_flow_counter_pool *pool =
3739                         flow_dv_counter_pool_get(cnt);
3740         int offset = cnt - &pool->counters_raw[0];
3741
3742         if (priv->counter_fallback)
3743                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3744
3745         rte_spinlock_lock(&pool->sl);
3746         /*
3747          * The single counters allocation may allocate smaller ID than the
3748          * current allocated in parallel to the host reading.
3749          * In this case the new counter values must be reported as 0.
3750          */
3751         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3752                 *pkts = 0;
3753                 *bytes = 0;
3754         } else {
3755                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3756                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3757         }
3758         rte_spinlock_unlock(&pool->sl);
3759         return 0;
3760 }
3761
3762 /**
3763  * Create and initialize a new counter pool.
3764  *
3765  * @param[in] dev
3766  *   Pointer to the Ethernet device structure.
3767  * @param[out] dcs
3768  *   The devX counter handle.
3769  * @param[in] batch
3770  *   Whether the pool is for counter that was allocated by batch command.
3771  *
3772  * @return
3773  *   A new pool pointer on success, NULL otherwise and rte_errno is set.
3774  */
3775 static struct mlx5_flow_counter_pool *
3776 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3777                     uint32_t batch)
3778 {
3779         struct mlx5_priv *priv = dev->data->dev_private;
3780         struct mlx5_flow_counter_pool *pool;
3781         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3782                                                                0);
3783         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3784         uint32_t size;
3785
3786         if (cont->n == n_valid) {
3787                 cont = flow_dv_container_resize(dev, batch);
3788                 if (!cont)
3789                         return NULL;
3790         }
3791         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3792                         sizeof(struct mlx5_flow_counter);
3793         pool = rte_calloc(__func__, 1, size, 0);
3794         if (!pool) {
3795                 rte_errno = ENOMEM;
3796                 return NULL;
3797         }
3798         pool->min_dcs = dcs;
3799         pool->raw = cont->init_mem_mng->raws + n_valid %
3800                                                      MLX5_CNT_CONTAINER_RESIZE;
3801         pool->raw_hw = NULL;
3802         rte_spinlock_init(&pool->sl);
3803         /*
3804          * The generation of the new allocated counters in this pool is 0, 2 in
3805          * the pool generation makes all the counters valid for allocation.
3806          */
3807         rte_atomic64_set(&pool->query_gen, 0x2);
3808         TAILQ_INIT(&pool->counters);
3809         TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3810         cont->pools[n_valid] = pool;
3811         /* Pool initialization must be updated before host thread access. */
3812         rte_cio_wmb();
3813         rte_atomic16_add(&cont->n_valid, 1);
3814         return pool;
3815 }
3816
3817 /**
3818  * Prepare a new counter and/or a new counter pool.
3819  *
3820  * @param[in] dev
3821  *   Pointer to the Ethernet device structure.
3822  * @param[out] cnt_free
3823  *   Where to put the pointer of a new counter.
3824  * @param[in] batch
3825  *   Whether the pool is for counter that was allocated by batch command.
3826  *
3827  * @return
3828  *   The free counter pool pointer and @p cnt_free is set on success,
3829  *   NULL otherwise and rte_errno is set.
3830  */
3831 static struct mlx5_flow_counter_pool *
3832 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3833                              struct mlx5_flow_counter **cnt_free,
3834                              uint32_t batch)
3835 {
3836         struct mlx5_priv *priv = dev->data->dev_private;
3837         struct mlx5_flow_counter_pool *pool;
3838         struct mlx5_devx_obj *dcs = NULL;
3839         struct mlx5_flow_counter *cnt;
3840         uint32_t i;
3841
3842         if (!batch) {
3843                 /* bulk_bitmap must be 0 for single counter allocation. */
3844                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3845                 if (!dcs)
3846                         return NULL;
3847                 pool = flow_dv_find_pool_by_id
3848                         (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3849                 if (!pool) {
3850                         pool = flow_dv_pool_create(dev, dcs, batch);
3851                         if (!pool) {
3852                                 mlx5_devx_cmd_destroy(dcs);
3853                                 return NULL;
3854                         }
3855                 } else if (dcs->id < pool->min_dcs->id) {
3856                         rte_atomic64_set(&pool->a64_dcs,
3857                                          (int64_t)(uintptr_t)dcs);
3858                 }
3859                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3860                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3861                 cnt->dcs = dcs;
3862                 *cnt_free = cnt;
3863                 return pool;
3864         }
3865         /* bulk_bitmap is in 128 counters units. */
3866         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3867                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3868         if (!dcs) {
3869                 rte_errno = ENODATA;
3870                 return NULL;
3871         }
3872         pool = flow_dv_pool_create(dev, dcs, batch);
3873         if (!pool) {
3874                 mlx5_devx_cmd_destroy(dcs);
3875                 return NULL;
3876         }
3877         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3878                 cnt = &pool->counters_raw[i];
3879                 cnt->pool = pool;
3880                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3881         }
3882         *cnt_free = &pool->counters_raw[0];
3883         return pool;
3884 }
3885
3886 /**
3887  * Search for existed shared counter.
3888  *
3889  * @param[in] cont
3890  *   Pointer to the relevant counter pool container.
3891  * @param[in] id
3892  *   The shared counter ID to search.
3893  *
3894  * @return
3895  *   NULL if not existed, otherwise pointer to the shared counter.
3896  */
3897 static struct mlx5_flow_counter *
3898 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3899                               uint32_t id)
3900 {
3901         static struct mlx5_flow_counter *cnt;
3902         struct mlx5_flow_counter_pool *pool;
3903         int i;
3904
3905         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3906                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3907                         cnt = &pool->counters_raw[i];
3908                         if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3909                                 return cnt;
3910                 }
3911         }
3912         return NULL;
3913 }
3914
3915 /**
3916  * Allocate a flow counter.
3917  *
3918  * @param[in] dev
3919  *   Pointer to the Ethernet device structure.
3920  * @param[in] shared
3921  *   Indicate if this counter is shared with other flows.
3922  * @param[in] id
3923  *   Counter identifier.
3924  * @param[in] group
3925  *   Counter flow group.
3926  *
3927  * @return
3928  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3929  */
3930 static struct mlx5_flow_counter *
3931 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3932                       uint16_t group)
3933 {
3934         struct mlx5_priv *priv = dev->data->dev_private;
3935         struct mlx5_flow_counter_pool *pool = NULL;
3936         struct mlx5_flow_counter *cnt_free = NULL;
3937         /*
3938          * Currently group 0 flow counter cannot be assigned to a flow if it is
3939          * not the first one in the batch counter allocation, so it is better
3940          * to allocate counters one by one for these flows in a separate
3941          * container.
3942          * A counter can be shared between different groups so need to take
3943          * shared counters from the single container.
3944          */
3945         uint32_t batch = (group && !shared) ? 1 : 0;
3946         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3947                                                                0);
3948
3949         if (priv->counter_fallback)
3950                 return flow_dv_counter_alloc_fallback(dev, shared, id);
3951         if (!priv->config.devx) {
3952                 rte_errno = ENOTSUP;
3953                 return NULL;
3954         }
3955         if (shared) {
3956                 cnt_free = flow_dv_counter_shared_search(cont, id);
3957                 if (cnt_free) {
3958                         if (cnt_free->ref_cnt + 1 == 0) {
3959                                 rte_errno = E2BIG;
3960                                 return NULL;
3961                         }
3962                         cnt_free->ref_cnt++;
3963                         return cnt_free;
3964                 }
3965         }
3966         /* Pools which has a free counters are in the start. */
3967         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3968                 /*
3969                  * The free counter reset values must be updated between the
3970                  * counter release to the counter allocation, so, at least one
3971                  * query must be done in this time. ensure it by saving the
3972                  * query generation in the release time.
3973                  * The free list is sorted according to the generation - so if
3974                  * the first one is not updated, all the others are not
3975                  * updated too.
3976                  */
3977                 cnt_free = TAILQ_FIRST(&pool->counters);
3978                 if (cnt_free && cnt_free->query_gen + 1 <
3979                     rte_atomic64_read(&pool->query_gen))
3980                         break;
3981                 cnt_free = NULL;
3982         }
3983         if (!cnt_free) {
3984                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3985                 if (!pool)
3986                         return NULL;
3987         }
3988         cnt_free->batch = batch;
3989         /* Create a DV counter action only in the first time usage. */
3990         if (!cnt_free->action) {
3991                 uint16_t offset;
3992                 struct mlx5_devx_obj *dcs;
3993
3994                 if (batch) {
3995                         offset = cnt_free - &pool->counters_raw[0];
3996                         dcs = pool->min_dcs;
3997                 } else {
3998                         offset = 0;
3999                         dcs = cnt_free->dcs;
4000                 }
4001                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4002                                         (dcs->obj, offset);
4003                 if (!cnt_free->action) {
4004                         rte_errno = errno;
4005                         return NULL;
4006                 }
4007         }
4008         /* Update the counter reset values. */
4009         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4010                                  &cnt_free->bytes))
4011                 return NULL;
4012         cnt_free->shared = shared;
4013         cnt_free->ref_cnt = 1;
4014         cnt_free->id = id;
4015         if (!priv->sh->cmng.query_thread_on)
4016                 /* Start the asynchronous batch query by the host thread. */
4017                 mlx5_set_query_alarm(priv->sh);
4018         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4019         if (TAILQ_EMPTY(&pool->counters)) {
4020                 /* Move the pool to the end of the container pool list. */
4021                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4022                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4023         }
4024         return cnt_free;
4025 }
4026
4027 /**
4028  * Release a flow counter.
4029  *
4030  * @param[in] dev
4031  *   Pointer to the Ethernet device structure.
4032  * @param[in] counter
4033  *   Pointer to the counter handler.
4034  */
4035 static void
4036 flow_dv_counter_release(struct rte_eth_dev *dev,
4037                         struct mlx5_flow_counter *counter)
4038 {
4039         struct mlx5_priv *priv = dev->data->dev_private;
4040
4041         if (!counter)
4042                 return;
4043         if (priv->counter_fallback) {
4044                 flow_dv_counter_release_fallback(dev, counter);
4045                 return;
4046         }
4047         if (--counter->ref_cnt == 0) {
4048                 struct mlx5_flow_counter_pool *pool =
4049                                 flow_dv_counter_pool_get(counter);
4050
4051                 /* Put the counter in the end - the last updated one. */
4052                 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4053                 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4054         }
4055 }
4056
4057 /**
4058  * Verify the @p attributes will be correctly understood by the NIC and store
4059  * them in the @p flow if everything is correct.
4060  *
4061  * @param[in] dev
4062  *   Pointer to dev struct.
4063  * @param[in] attributes
4064  *   Pointer to flow attributes
4065  * @param[in] external
4066  *   This flow rule is created by request external to PMD.
4067  * @param[out] error
4068  *   Pointer to error structure.
4069  *
4070  * @return
4071  *   0 on success, a negative errno value otherwise and rte_errno is set.
4072  */
4073 static int
4074 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4075                             const struct rte_flow_attr *attributes,
4076                             bool external __rte_unused,
4077                             struct rte_flow_error *error)
4078 {
4079         struct mlx5_priv *priv = dev->data->dev_private;
4080         uint32_t priority_max = priv->config.flow_prio - 1;
4081
4082 #ifndef HAVE_MLX5DV_DR
4083         if (attributes->group)
4084                 return rte_flow_error_set(error, ENOTSUP,
4085                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4086                                           NULL,
4087                                           "groups are not supported");
4088 #else
4089         uint32_t max_group = attributes->transfer ?
4090                              MLX5_MAX_TABLES_FDB :
4091                                 external ?
4092                                 MLX5_MAX_TABLES_EXTERNAL :
4093                                 MLX5_MAX_TABLES;
4094         uint32_t table;
4095         int ret;
4096
4097         ret = mlx5_flow_group_to_table(attributes, external,
4098                                        attributes->group,
4099                                        &table, error);
4100         if (ret)
4101                 return ret;
4102         if (table >= max_group)
4103                 return rte_flow_error_set(error, EINVAL,
4104                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
4105                                           "group index out of range");
4106 #endif
4107         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4108             attributes->priority >= priority_max)
4109                 return rte_flow_error_set(error, ENOTSUP,
4110                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4111                                           NULL,
4112                                           "priority out of range");
4113         if (attributes->transfer) {
4114                 if (!priv->config.dv_esw_en)
4115                         return rte_flow_error_set
4116                                 (error, ENOTSUP,
4117                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4118                                  "E-Switch dr is not supported");
4119                 if (!(priv->representor || priv->master))
4120                         return rte_flow_error_set
4121                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4122                                  NULL, "E-Switch configuration can only be"
4123                                  " done by a master or a representor device");
4124                 if (attributes->egress)
4125                         return rte_flow_error_set
4126                                 (error, ENOTSUP,
4127                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4128                                  "egress is not supported");
4129         }
4130         if (!(attributes->egress ^ attributes->ingress))
4131                 return rte_flow_error_set(error, ENOTSUP,
4132                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4133                                           "must specify exactly one of "
4134                                           "ingress or egress");
4135         return 0;
4136 }
4137
4138 /**
4139  * Internal validation function. For validating both actions and items.
4140  *
4141  * @param[in] dev
4142  *   Pointer to the rte_eth_dev structure.
4143  * @param[in] attr
4144  *   Pointer to the flow attributes.
4145  * @param[in] items
4146  *   Pointer to the list of items.
4147  * @param[in] actions
4148  *   Pointer to the list of actions.
4149  * @param[in] external
4150  *   This flow rule is created by request external to PMD.
4151  * @param[out] error
4152  *   Pointer to the error structure.
4153  *
4154  * @return
4155  *   0 on success, a negative errno value otherwise and rte_errno is set.
4156  */
4157 static int
4158 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4159                  const struct rte_flow_item items[],
4160                  const struct rte_flow_action actions[],
4161                  bool external, struct rte_flow_error *error)
4162 {
4163         int ret;
4164         uint64_t action_flags = 0;
4165         uint64_t item_flags = 0;
4166         uint64_t last_item = 0;
4167         uint8_t next_protocol = 0xff;
4168         uint16_t ether_type = 0;
4169         int actions_n = 0;
4170         const struct rte_flow_item *gre_item = NULL;
4171         struct rte_flow_item_tcp nic_tcp_mask = {
4172                 .hdr = {
4173                         .tcp_flags = 0xFF,
4174                         .src_port = RTE_BE16(UINT16_MAX),
4175                         .dst_port = RTE_BE16(UINT16_MAX),
4176                 }
4177         };
4178         struct mlx5_priv *priv = dev->data->dev_private;
4179         struct mlx5_dev_config *dev_conf = &priv->config;
4180
4181         if (items == NULL)
4182                 return -1;
4183         ret = flow_dv_validate_attributes(dev, attr, external, error);
4184         if (ret < 0)
4185                 return ret;
4186         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4187                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4188                 int type = items->type;
4189
4190                 switch (type) {
4191                 case RTE_FLOW_ITEM_TYPE_VOID:
4192                         break;
4193                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4194                         ret = flow_dv_validate_item_port_id
4195                                         (dev, items, attr, item_flags, error);
4196                         if (ret < 0)
4197                                 return ret;
4198                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4199                         break;
4200                 case RTE_FLOW_ITEM_TYPE_ETH:
4201                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4202                                                           error);
4203                         if (ret < 0)
4204                                 return ret;
4205                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4206                                              MLX5_FLOW_LAYER_OUTER_L2;
4207                         if (items->mask != NULL && items->spec != NULL) {
4208                                 ether_type =
4209                                         ((const struct rte_flow_item_eth *)
4210                                          items->spec)->type;
4211                                 ether_type &=
4212                                         ((const struct rte_flow_item_eth *)
4213                                          items->mask)->type;
4214                                 ether_type = rte_be_to_cpu_16(ether_type);
4215                         } else {
4216                                 ether_type = 0;
4217                         }
4218                         break;
4219                 case RTE_FLOW_ITEM_TYPE_VLAN:
4220                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4221                                                            dev, error);
4222                         if (ret < 0)
4223                                 return ret;
4224                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4225                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4226                         if (items->mask != NULL && items->spec != NULL) {
4227                                 ether_type =
4228                                         ((const struct rte_flow_item_vlan *)
4229                                          items->spec)->inner_type;
4230                                 ether_type &=
4231                                         ((const struct rte_flow_item_vlan *)
4232                                          items->mask)->inner_type;
4233                                 ether_type = rte_be_to_cpu_16(ether_type);
4234                         } else {
4235                                 ether_type = 0;
4236                         }
4237                         break;
4238                 case RTE_FLOW_ITEM_TYPE_IPV4:
4239                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4240                                                   &item_flags, &tunnel);
4241                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4242                                                            last_item,
4243                                                            ether_type, NULL,
4244                                                            error);
4245                         if (ret < 0)
4246                                 return ret;
4247                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4248                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4249                         if (items->mask != NULL &&
4250                             ((const struct rte_flow_item_ipv4 *)
4251                              items->mask)->hdr.next_proto_id) {
4252                                 next_protocol =
4253                                         ((const struct rte_flow_item_ipv4 *)
4254                                          (items->spec))->hdr.next_proto_id;
4255                                 next_protocol &=
4256                                         ((const struct rte_flow_item_ipv4 *)
4257                                          (items->mask))->hdr.next_proto_id;
4258                         } else {
4259                                 /* Reset for inner layer. */
4260                                 next_protocol = 0xff;
4261                         }
4262                         break;
4263                 case RTE_FLOW_ITEM_TYPE_IPV6:
4264                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4265                                                   &item_flags, &tunnel);
4266                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4267                                                            last_item,
4268                                                            ether_type, NULL,
4269                                                            error);
4270                         if (ret < 0)
4271                                 return ret;
4272                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4273                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4274                         if (items->mask != NULL &&
4275                             ((const struct rte_flow_item_ipv6 *)
4276                              items->mask)->hdr.proto) {
4277                                 next_protocol =
4278                                         ((const struct rte_flow_item_ipv6 *)
4279                                          items->spec)->hdr.proto;
4280                                 next_protocol &=
4281                                         ((const struct rte_flow_item_ipv6 *)
4282                                          items->mask)->hdr.proto;
4283                         } else {
4284                                 /* Reset for inner layer. */
4285                                 next_protocol = 0xff;
4286                         }
4287                         break;
4288                 case RTE_FLOW_ITEM_TYPE_TCP:
4289                         ret = mlx5_flow_validate_item_tcp
4290                                                 (items, item_flags,
4291                                                  next_protocol,
4292                                                  &nic_tcp_mask,
4293                                                  error);
4294                         if (ret < 0)
4295                                 return ret;
4296                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4297                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4298                         break;
4299                 case RTE_FLOW_ITEM_TYPE_UDP:
4300                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4301                                                           next_protocol,
4302                                                           error);
4303                         if (ret < 0)
4304                                 return ret;
4305                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4306                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4307                         break;
4308                 case RTE_FLOW_ITEM_TYPE_GRE:
4309                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4310                                                           next_protocol, error);
4311                         if (ret < 0)
4312                                 return ret;
4313                         gre_item = items;
4314                         last_item = MLX5_FLOW_LAYER_GRE;
4315                         break;
4316                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4317                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4318                                                             next_protocol,
4319                                                             error);
4320                         if (ret < 0)
4321                                 return ret;
4322                         last_item = MLX5_FLOW_LAYER_NVGRE;
4323                         break;
4324                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4325                         ret = mlx5_flow_validate_item_gre_key
4326                                 (items, item_flags, gre_item, error);
4327                         if (ret < 0)
4328                                 return ret;
4329                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4330                         break;
4331                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4332                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4333                                                             error);
4334                         if (ret < 0)
4335                                 return ret;
4336                         last_item = MLX5_FLOW_LAYER_VXLAN;
4337                         break;
4338                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4339                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4340                                                                 item_flags, dev,
4341                                                                 error);
4342                         if (ret < 0)
4343                                 return ret;
4344                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4345                         break;
4346                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4347                         ret = mlx5_flow_validate_item_geneve(items,
4348                                                              item_flags, dev,
4349                                                              error);
4350                         if (ret < 0)
4351                                 return ret;
4352                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4353                         break;
4354                 case RTE_FLOW_ITEM_TYPE_MPLS:
4355                         ret = mlx5_flow_validate_item_mpls(dev, items,
4356                                                            item_flags,
4357                                                            last_item, error);
4358                         if (ret < 0)
4359                                 return ret;
4360                         last_item = MLX5_FLOW_LAYER_MPLS;
4361                         break;
4362
4363                 case RTE_FLOW_ITEM_TYPE_MARK:
4364                         ret = flow_dv_validate_item_mark(dev, items, attr,
4365                                                          error);
4366                         if (ret < 0)
4367                                 return ret;
4368                         last_item = MLX5_FLOW_ITEM_MARK;
4369                         break;
4370                 case RTE_FLOW_ITEM_TYPE_META:
4371                         ret = flow_dv_validate_item_meta(dev, items, attr,
4372                                                          error);
4373                         if (ret < 0)
4374                                 return ret;
4375                         last_item = MLX5_FLOW_ITEM_METADATA;
4376                         break;
4377                 case RTE_FLOW_ITEM_TYPE_ICMP:
4378                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4379                                                            next_protocol,
4380                                                            error);
4381                         if (ret < 0)
4382                                 return ret;
4383                         last_item = MLX5_FLOW_LAYER_ICMP;
4384                         break;
4385                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4386                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4387                                                             next_protocol,
4388                                                             error);
4389                         if (ret < 0)
4390                                 return ret;
4391                         last_item = MLX5_FLOW_LAYER_ICMP6;
4392                         break;
4393                 case RTE_FLOW_ITEM_TYPE_TAG:
4394                         ret = flow_dv_validate_item_tag(dev, items,
4395                                                         attr, error);
4396                         if (ret < 0)
4397                                 return ret;
4398                         last_item = MLX5_FLOW_ITEM_TAG;
4399                         break;
4400                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4401                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4402                         break;
4403                 default:
4404                         return rte_flow_error_set(error, ENOTSUP,
4405                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4406                                                   NULL, "item not supported");
4407                 }
4408                 item_flags |= last_item;
4409         }
4410         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4411                 int type = actions->type;
4412                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4413                         return rte_flow_error_set(error, ENOTSUP,
4414                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4415                                                   actions, "too many actions");
4416                 switch (type) {
4417                 case RTE_FLOW_ACTION_TYPE_VOID:
4418                         break;
4419                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4420                         ret = flow_dv_validate_action_port_id(dev,
4421                                                               action_flags,
4422                                                               actions,
4423                                                               attr,
4424                                                               error);
4425                         if (ret)
4426                                 return ret;
4427                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4428                         ++actions_n;
4429                         break;
4430                 case RTE_FLOW_ACTION_TYPE_FLAG:
4431                         ret = flow_dv_validate_action_flag(dev, action_flags,
4432                                                            attr, error);
4433                         if (ret < 0)
4434                                 return ret;
4435                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4436                                 /* Count all modify-header actions as one. */
4437                                 if (!(action_flags &
4438                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4439                                         ++actions_n;
4440                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4441                                                 MLX5_FLOW_ACTION_MARK_EXT;
4442                         } else {
4443                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4444                                 ++actions_n;
4445                         }
4446                         break;
4447                 case RTE_FLOW_ACTION_TYPE_MARK:
4448                         ret = flow_dv_validate_action_mark(dev, actions,
4449                                                            action_flags,
4450                                                            attr, error);
4451                         if (ret < 0)
4452                                 return ret;
4453                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4454                                 /* Count all modify-header actions as one. */
4455                                 if (!(action_flags &
4456                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4457                                         ++actions_n;
4458                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4459                                                 MLX5_FLOW_ACTION_MARK_EXT;
4460                         } else {
4461                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4462                                 ++actions_n;
4463                         }
4464                         break;
4465                 case RTE_FLOW_ACTION_TYPE_SET_META:
4466                         ret = flow_dv_validate_action_set_meta(dev, actions,
4467                                                                action_flags,
4468                                                                attr, error);
4469                         if (ret < 0)
4470                                 return ret;
4471                         /* Count all modify-header actions as one action. */
4472                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4473                                 ++actions_n;
4474                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4475                         break;
4476                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4477                         ret = flow_dv_validate_action_set_tag(dev, actions,
4478                                                               action_flags,
4479                                                               attr, error);
4480                         if (ret < 0)
4481                                 return ret;
4482                         /* Count all modify-header actions as one action. */
4483                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4484                                 ++actions_n;
4485                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4486                         break;
4487                 case RTE_FLOW_ACTION_TYPE_DROP:
4488                         ret = mlx5_flow_validate_action_drop(action_flags,
4489                                                              attr, error);
4490                         if (ret < 0)
4491                                 return ret;
4492                         action_flags |= MLX5_FLOW_ACTION_DROP;
4493                         ++actions_n;
4494                         break;
4495                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4496                         ret = mlx5_flow_validate_action_queue(actions,
4497                                                               action_flags, dev,
4498                                                               attr, error);
4499                         if (ret < 0)
4500                                 return ret;
4501                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4502                         ++actions_n;
4503                         break;
4504                 case RTE_FLOW_ACTION_TYPE_RSS:
4505                         ret = mlx5_flow_validate_action_rss(actions,
4506                                                             action_flags, dev,
4507                                                             attr, item_flags,
4508                                                             error);
4509                         if (ret < 0)
4510                                 return ret;
4511                         action_flags |= MLX5_FLOW_ACTION_RSS;
4512                         ++actions_n;
4513                         break;
4514                 case RTE_FLOW_ACTION_TYPE_COUNT:
4515                         ret = flow_dv_validate_action_count(dev, error);
4516                         if (ret < 0)
4517                                 return ret;
4518                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4519                         ++actions_n;
4520                         break;
4521                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4522                         if (flow_dv_validate_action_pop_vlan(dev,
4523                                                              action_flags,
4524                                                              actions,
4525                                                              item_flags, attr,
4526                                                              error))
4527                                 return -rte_errno;
4528                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4529                         ++actions_n;
4530                         break;
4531                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4532                         ret = flow_dv_validate_action_push_vlan(action_flags,
4533                                                                 item_flags,
4534                                                                 actions, attr,
4535                                                                 error);
4536                         if (ret < 0)
4537                                 return ret;
4538                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4539                         ++actions_n;
4540                         break;
4541                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4542                         ret = flow_dv_validate_action_set_vlan_pcp
4543                                                 (action_flags, actions, error);
4544                         if (ret < 0)
4545                                 return ret;
4546                         /* Count PCP with push_vlan command. */
4547                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4548                         break;
4549                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4550                         ret = flow_dv_validate_action_set_vlan_vid
4551                                                 (item_flags, action_flags,
4552                                                  actions, error);
4553                         if (ret < 0)
4554                                 return ret;
4555                         /* Count VID with push_vlan command. */
4556                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4557                         break;
4558                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4559                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4560                         ret = flow_dv_validate_action_l2_encap(action_flags,
4561                                                                actions, attr,
4562                                                                error);
4563                         if (ret < 0)
4564                                 return ret;
4565                         action_flags |= actions->type ==
4566                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4567                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
4568                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
4569                         ++actions_n;
4570                         break;
4571                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4572                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4573                         ret = flow_dv_validate_action_l2_decap(action_flags,
4574                                                                attr, error);
4575                         if (ret < 0)
4576                                 return ret;
4577                         action_flags |= actions->type ==
4578                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4579                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
4580                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
4581                         ++actions_n;
4582                         break;
4583                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4584                         ret = flow_dv_validate_action_raw_encap(action_flags,
4585                                                                 actions, attr,
4586                                                                 error);
4587                         if (ret < 0)
4588                                 return ret;
4589                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4590                         ++actions_n;
4591                         break;
4592                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4593                         ret = flow_dv_validate_action_raw_decap(action_flags,
4594                                                                 actions, attr,
4595                                                                 error);
4596                         if (ret < 0)
4597                                 return ret;
4598                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4599                         ++actions_n;
4600                         break;
4601                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4602                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4603                         ret = flow_dv_validate_action_modify_mac(action_flags,
4604                                                                  actions,
4605                                                                  item_flags,
4606                                                                  error);
4607                         if (ret < 0)
4608                                 return ret;
4609                         /* Count all modify-header actions as one action. */
4610                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4611                                 ++actions_n;
4612                         action_flags |= actions->type ==
4613                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4614                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
4615                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
4616                         break;
4617
4618                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4619                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4620                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
4621                                                                   actions,
4622                                                                   item_flags,
4623                                                                   error);
4624                         if (ret < 0)
4625                                 return ret;
4626                         /* Count all modify-header actions as one action. */
4627                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4628                                 ++actions_n;
4629                         action_flags |= actions->type ==
4630                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4631                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4632                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
4633                         break;
4634                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4635                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4636                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
4637                                                                   actions,
4638                                                                   item_flags,
4639                                                                   error);
4640                         if (ret < 0)
4641                                 return ret;
4642                         /* Count all modify-header actions as one action. */
4643                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4644                                 ++actions_n;
4645                         action_flags |= actions->type ==
4646                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4647                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4648                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
4649                         break;
4650                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4651                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4652                         ret = flow_dv_validate_action_modify_tp(action_flags,
4653                                                                 actions,
4654                                                                 item_flags,
4655                                                                 error);
4656                         if (ret < 0)
4657                                 return ret;
4658                         /* Count all modify-header actions as one action. */
4659                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4660                                 ++actions_n;
4661                         action_flags |= actions->type ==
4662                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4663                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
4664                                                 MLX5_FLOW_ACTION_SET_TP_DST;
4665                         break;
4666                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4667                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4668                         ret = flow_dv_validate_action_modify_ttl(action_flags,
4669                                                                  actions,
4670                                                                  item_flags,
4671                                                                  error);
4672                         if (ret < 0)
4673                                 return ret;
4674                         /* Count all modify-header actions as one action. */
4675                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4676                                 ++actions_n;
4677                         action_flags |= actions->type ==
4678                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
4679                                                 MLX5_FLOW_ACTION_SET_TTL :
4680                                                 MLX5_FLOW_ACTION_DEC_TTL;
4681                         break;
4682                 case RTE_FLOW_ACTION_TYPE_JUMP:
4683                         ret = flow_dv_validate_action_jump(actions,
4684                                                            action_flags,
4685                                                            attr, external,
4686                                                            error);
4687                         if (ret)
4688                                 return ret;
4689                         ++actions_n;
4690                         action_flags |= MLX5_FLOW_ACTION_JUMP;
4691                         break;
4692                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4693                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4694                         ret = flow_dv_validate_action_modify_tcp_seq
4695                                                                 (action_flags,
4696                                                                  actions,
4697                                                                  item_flags,
4698                                                                  error);
4699                         if (ret < 0)
4700                                 return ret;
4701                         /* Count all modify-header actions as one action. */
4702                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4703                                 ++actions_n;
4704                         action_flags |= actions->type ==
4705                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4706                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4707                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4708                         break;
4709                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4710                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4711                         ret = flow_dv_validate_action_modify_tcp_ack
4712                                                                 (action_flags,
4713                                                                  actions,
4714                                                                  item_flags,
4715                                                                  error);
4716                         if (ret < 0)
4717                                 return ret;
4718                         /* Count all modify-header actions as one action. */
4719                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4720                                 ++actions_n;
4721                         action_flags |= actions->type ==
4722                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4723                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
4724                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4725                         break;
4726                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4727                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4728                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4729                         break;
4730                 default:
4731                         return rte_flow_error_set(error, ENOTSUP,
4732                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4733                                                   actions,
4734                                                   "action not supported");
4735                 }
4736         }
4737         if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4738             (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4739                 return rte_flow_error_set(error, ENOTSUP,
4740                                           RTE_FLOW_ERROR_TYPE_ACTION,
4741                                           actions,
4742                                           "can't have vxlan and vlan"
4743                                           " actions in the same rule");
4744         /* Eswitch has few restrictions on using items and actions */
4745         if (attr->transfer) {
4746                 if (!mlx5_flow_ext_mreg_supported(dev) &&
4747                     action_flags & MLX5_FLOW_ACTION_FLAG)
4748                         return rte_flow_error_set(error, ENOTSUP,
4749                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4750                                                   NULL,
4751                                                   "unsupported action FLAG");
4752                 if (!mlx5_flow_ext_mreg_supported(dev) &&
4753                     action_flags & MLX5_FLOW_ACTION_MARK)
4754                         return rte_flow_error_set(error, ENOTSUP,
4755                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4756                                                   NULL,
4757                                                   "unsupported action MARK");
4758                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4759                         return rte_flow_error_set(error, ENOTSUP,
4760                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4761                                                   NULL,
4762                                                   "unsupported action QUEUE");
4763                 if (action_flags & MLX5_FLOW_ACTION_RSS)
4764                         return rte_flow_error_set(error, ENOTSUP,
4765                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4766                                                   NULL,
4767                                                   "unsupported action RSS");
4768                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4769                         return rte_flow_error_set(error, EINVAL,
4770                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4771                                                   actions,
4772                                                   "no fate action is found");
4773         } else {
4774                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4775                         return rte_flow_error_set(error, EINVAL,
4776                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4777                                                   actions,
4778                                                   "no fate action is found");
4779         }
4780         return 0;
4781 }
4782
4783 /**
4784  * Internal preparation function. Allocates the DV flow size,
4785  * this size is constant.
4786  *
4787  * @param[in] attr
4788  *   Pointer to the flow attributes.
4789  * @param[in] items
4790  *   Pointer to the list of items.
4791  * @param[in] actions
4792  *   Pointer to the list of actions.
4793  * @param[out] error
4794  *   Pointer to the error structure.
4795  *
4796  * @return
4797  *   Pointer to mlx5_flow object on success,
4798  *   otherwise NULL and rte_errno is set.
4799  */
4800 static struct mlx5_flow *
4801 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4802                 const struct rte_flow_item items[] __rte_unused,
4803                 const struct rte_flow_action actions[] __rte_unused,
4804                 struct rte_flow_error *error)
4805 {
4806         size_t size = sizeof(struct mlx5_flow);
4807         struct mlx5_flow *dev_flow;
4808
4809         dev_flow = rte_calloc(__func__, 1, size, 0);
4810         if (!dev_flow) {
4811                 rte_flow_error_set(error, ENOMEM,
4812                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4813                                    "not enough memory to create flow");
4814                 return NULL;
4815         }
4816         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4817         dev_flow->ingress = attr->ingress;
4818         dev_flow->transfer = attr->transfer;
4819         return dev_flow;
4820 }
4821
4822 #ifndef NDEBUG
4823 /**
4824  * Sanity check for match mask and value. Similar to check_valid_spec() in
4825  * kernel driver. If unmasked bit is present in value, it returns failure.
4826  *
4827  * @param match_mask
4828  *   pointer to match mask buffer.
4829  * @param match_value
4830  *   pointer to match value buffer.
4831  *
4832  * @return
4833  *   0 if valid, -EINVAL otherwise.
4834  */
4835 static int
4836 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4837 {
4838         uint8_t *m = match_mask;
4839         uint8_t *v = match_value;
4840         unsigned int i;
4841
4842         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4843                 if (v[i] & ~m[i]) {
4844                         DRV_LOG(ERR,
4845                                 "match_value differs from match_criteria"
4846                                 " %p[%u] != %p[%u]",
4847                                 match_value, i, match_mask, i);
4848                         return -EINVAL;
4849                 }
4850         }
4851         return 0;
4852 }
4853 #endif
4854
4855 /**
4856  * Add Ethernet item to matcher and to the value.
4857  *
4858  * @param[in, out] matcher
4859  *   Flow matcher.
4860  * @param[in, out] key
4861  *   Flow matcher value.
4862  * @param[in] item
4863  *   Flow pattern to translate.
4864  * @param[in] inner
4865  *   Item is inner pattern.
4866  */
4867 static void
4868 flow_dv_translate_item_eth(void *matcher, void *key,
4869                            const struct rte_flow_item *item, int inner)
4870 {
4871         const struct rte_flow_item_eth *eth_m = item->mask;
4872         const struct rte_flow_item_eth *eth_v = item->spec;
4873         const struct rte_flow_item_eth nic_mask = {
4874                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4875                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4876                 .type = RTE_BE16(0xffff),
4877         };
4878         void *headers_m;
4879         void *headers_v;
4880         char *l24_v;
4881         unsigned int i;
4882
4883         if (!eth_v)
4884                 return;
4885         if (!eth_m)
4886                 eth_m = &nic_mask;
4887         if (inner) {
4888                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4889                                          inner_headers);
4890                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4891         } else {
4892                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4893                                          outer_headers);
4894                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4895         }
4896         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4897                &eth_m->dst, sizeof(eth_m->dst));
4898         /* The value must be in the range of the mask. */
4899         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4900         for (i = 0; i < sizeof(eth_m->dst); ++i)
4901                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4902         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4903                &eth_m->src, sizeof(eth_m->src));
4904         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4905         /* The value must be in the range of the mask. */
4906         for (i = 0; i < sizeof(eth_m->dst); ++i)
4907                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4908         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4909                  rte_be_to_cpu_16(eth_m->type));
4910         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4911         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4912 }
4913
4914 /**
4915  * Add VLAN item to matcher and to the value.
4916  *
4917  * @param[in, out] dev_flow
4918  *   Flow descriptor.
4919  * @param[in, out] matcher
4920  *   Flow matcher.
4921  * @param[in, out] key
4922  *   Flow matcher value.
4923  * @param[in] item
4924  *   Flow pattern to translate.
4925  * @param[in] inner
4926  *   Item is inner pattern.
4927  */
4928 static void
4929 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4930                             void *matcher, void *key,
4931                             const struct rte_flow_item *item,
4932                             int inner)
4933 {
4934         const struct rte_flow_item_vlan *vlan_m = item->mask;
4935         const struct rte_flow_item_vlan *vlan_v = item->spec;
4936         void *headers_m;
4937         void *headers_v;
4938         uint16_t tci_m;
4939         uint16_t tci_v;
4940
4941         if (!vlan_v)
4942                 return;
4943         if (!vlan_m)
4944                 vlan_m = &rte_flow_item_vlan_mask;
4945         if (inner) {
4946                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4947                                          inner_headers);
4948                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4949         } else {
4950                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4951                                          outer_headers);
4952                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4953                 /*
4954                  * This is workaround, masks are not supported,
4955                  * and pre-validated.
4956                  */
4957                 dev_flow->dv.vf_vlan.tag =
4958                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4959         }
4960         tci_m = rte_be_to_cpu_16(vlan_m->tci);
4961         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4962         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4963         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4964         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4965         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4966         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4967         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4968         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4969         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4970         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4971                  rte_be_to_cpu_16(vlan_m->inner_type));
4972         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4973                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4974 }
4975
4976 /**
4977  * Add IPV4 item to matcher and to the value.
4978  *
4979  * @param[in, out] matcher
4980  *   Flow matcher.
4981  * @param[in, out] key
4982  *   Flow matcher value.
4983  * @param[in] item
4984  *   Flow pattern to translate.
4985  * @param[in] inner
4986  *   Item is inner pattern.
4987  * @param[in] group
4988  *   The group to insert the rule.
4989  */
4990 static void
4991 flow_dv_translate_item_ipv4(void *matcher, void *key,
4992                             const struct rte_flow_item *item,
4993                             int inner, uint32_t group)
4994 {
4995         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4996         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4997         const struct rte_flow_item_ipv4 nic_mask = {
4998                 .hdr = {
4999                         .src_addr = RTE_BE32(0xffffffff),
5000                         .dst_addr = RTE_BE32(0xffffffff),
5001                         .type_of_service = 0xff,
5002                         .next_proto_id = 0xff,
5003                 },
5004         };
5005         void *headers_m;
5006         void *headers_v;
5007         char *l24_m;
5008         char *l24_v;
5009         uint8_t tos;
5010
5011         if (inner) {
5012                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5013                                          inner_headers);
5014                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5015         } else {
5016                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5017                                          outer_headers);
5018                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5019         }
5020         if (group == 0)
5021                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5022         else
5023                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5024         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5025         if (!ipv4_v)
5026                 return;
5027         if (!ipv4_m)
5028                 ipv4_m = &nic_mask;
5029         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5030                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5031         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5032                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5033         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5034         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5035         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5036                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5037         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5038                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5039         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5040         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5041         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5042         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5043                  ipv4_m->hdr.type_of_service);
5044         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5045         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5046                  ipv4_m->hdr.type_of_service >> 2);
5047         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5048         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5049                  ipv4_m->hdr.next_proto_id);
5050         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5051                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5052 }
5053
5054 /**
5055  * Add IPV6 item to matcher and to the value.
5056  *
5057  * @param[in, out] matcher
5058  *   Flow matcher.
5059  * @param[in, out] key
5060  *   Flow matcher value.
5061  * @param[in] item
5062  *   Flow pattern to translate.
5063  * @param[in] inner
5064  *   Item is inner pattern.
5065  * @param[in] group
5066  *   The group to insert the rule.
5067  */
5068 static void
5069 flow_dv_translate_item_ipv6(void *matcher, void *key,
5070                             const struct rte_flow_item *item,
5071                             int inner, uint32_t group)
5072 {
5073         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5074         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5075         const struct rte_flow_item_ipv6 nic_mask = {
5076                 .hdr = {
5077                         .src_addr =
5078                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5079                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5080                         .dst_addr =
5081                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5082                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5083                         .vtc_flow = RTE_BE32(0xffffffff),
5084                         .proto = 0xff,
5085                         .hop_limits = 0xff,
5086                 },
5087         };
5088         void *headers_m;
5089         void *headers_v;
5090         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5091         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5092         char *l24_m;
5093         char *l24_v;
5094         uint32_t vtc_m;
5095         uint32_t vtc_v;
5096         int i;
5097         int size;
5098
5099         if (inner) {
5100                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5101                                          inner_headers);
5102                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5103         } else {
5104                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5105                                          outer_headers);
5106                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5107         }
5108         if (group == 0)
5109                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5110         else
5111                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5112         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5113         if (!ipv6_v)
5114                 return;
5115         if (!ipv6_m)
5116                 ipv6_m = &nic_mask;
5117         size = sizeof(ipv6_m->hdr.dst_addr);
5118         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5119                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5120         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5121                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5122         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5123         for (i = 0; i < size; ++i)
5124                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5125         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5126                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5127         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5128                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5129         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5130         for (i = 0; i < size; ++i)
5131                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5132         /* TOS. */
5133         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5134         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5135         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5136         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5137         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5138         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5139         /* Label. */
5140         if (inner) {
5141                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5142                          vtc_m);
5143                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5144                          vtc_v);
5145         } else {
5146                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5147                          vtc_m);
5148                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5149                          vtc_v);
5150         }
5151         /* Protocol. */
5152         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5153                  ipv6_m->hdr.proto);
5154         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5155                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5156 }
5157
5158 /**
5159  * Add TCP item to matcher and to the value.
5160  *
5161  * @param[in, out] matcher
5162  *   Flow matcher.
5163  * @param[in, out] key
5164  *   Flow matcher value.
5165  * @param[in] item
5166  *   Flow pattern to translate.
5167  * @param[in] inner
5168  *   Item is inner pattern.
5169  */
5170 static void
5171 flow_dv_translate_item_tcp(void *matcher, void *key,
5172                            const struct rte_flow_item *item,
5173                            int inner)
5174 {
5175         const struct rte_flow_item_tcp *tcp_m = item->mask;
5176         const struct rte_flow_item_tcp *tcp_v = item->spec;
5177         void *headers_m;
5178         void *headers_v;
5179
5180         if (inner) {
5181                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5182                                          inner_headers);
5183                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5184         } else {
5185                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5186                                          outer_headers);
5187                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5188         }
5189         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5190         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5191         if (!tcp_v)
5192                 return;
5193         if (!tcp_m)
5194                 tcp_m = &rte_flow_item_tcp_mask;
5195         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5196                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5197         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5198                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5199         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5200                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5201         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5202                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5203         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5204                  tcp_m->hdr.tcp_flags);
5205         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5206                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5207 }
5208
5209 /**
5210  * Add UDP item to matcher and to the value.
5211  *
5212  * @param[in, out] matcher
5213  *   Flow matcher.
5214  * @param[in, out] key
5215  *   Flow matcher value.
5216  * @param[in] item
5217  *   Flow pattern to translate.
5218  * @param[in] inner
5219  *   Item is inner pattern.
5220  */
5221 static void
5222 flow_dv_translate_item_udp(void *matcher, void *key,
5223                            const struct rte_flow_item *item,
5224                            int inner)
5225 {
5226         const struct rte_flow_item_udp *udp_m = item->mask;
5227         const struct rte_flow_item_udp *udp_v = item->spec;
5228         void *headers_m;
5229         void *headers_v;
5230
5231         if (inner) {
5232                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5233                                          inner_headers);
5234                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5235         } else {
5236                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5237                                          outer_headers);
5238                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5239         }
5240         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5241         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5242         if (!udp_v)
5243                 return;
5244         if (!udp_m)
5245                 udp_m = &rte_flow_item_udp_mask;
5246         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5247                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5248         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5249                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5250         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5251                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5252         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5253                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5254 }
5255
5256 /**
5257  * Add GRE optional Key item to matcher and to the value.
5258  *
5259  * @param[in, out] matcher
5260  *   Flow matcher.
5261  * @param[in, out] key
5262  *   Flow matcher value.
5263  * @param[in] item
5264  *   Flow pattern to translate.
5265  * @param[in] inner
5266  *   Item is inner pattern.
5267  */
5268 static void
5269 flow_dv_translate_item_gre_key(void *matcher, void *key,
5270                                    const struct rte_flow_item *item)
5271 {
5272         const rte_be32_t *key_m = item->mask;
5273         const rte_be32_t *key_v = item->spec;
5274         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5275         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5276         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5277
5278         if (!key_v)
5279                 return;
5280         if (!key_m)
5281                 key_m = &gre_key_default_mask;
5282         /* GRE K bit must be on and should already be validated */
5283         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5284         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5285         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5286                  rte_be_to_cpu_32(*key_m) >> 8);
5287         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5288                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5289         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5290                  rte_be_to_cpu_32(*key_m) & 0xFF);
5291         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5292                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5293 }
5294
5295 /**
5296  * Add GRE item to matcher and to the value.
5297  *
5298  * @param[in, out] matcher
5299  *   Flow matcher.
5300  * @param[in, out] key
5301  *   Flow matcher value.
5302  * @param[in] item
5303  *   Flow pattern to translate.
5304  * @param[in] inner
5305  *   Item is inner pattern.
5306  */
5307 static void
5308 flow_dv_translate_item_gre(void *matcher, void *key,
5309                            const struct rte_flow_item *item,
5310                            int inner)
5311 {
5312         const struct rte_flow_item_gre *gre_m = item->mask;
5313         const struct rte_flow_item_gre *gre_v = item->spec;
5314         void *headers_m;
5315         void *headers_v;
5316         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5317         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5318         struct {
5319                 union {
5320                         __extension__
5321                         struct {
5322                                 uint16_t version:3;
5323                                 uint16_t rsvd0:9;
5324                                 uint16_t s_present:1;
5325                                 uint16_t k_present:1;
5326                                 uint16_t rsvd_bit1:1;
5327                                 uint16_t c_present:1;
5328                         };
5329                         uint16_t value;
5330                 };
5331         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5332
5333         if (inner) {
5334                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5335                                          inner_headers);
5336                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5337         } else {
5338                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5339                                          outer_headers);
5340                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5341         }
5342         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5343         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5344         if (!gre_v)
5345                 return;
5346         if (!gre_m)
5347                 gre_m = &rte_flow_item_gre_mask;
5348         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5349                  rte_be_to_cpu_16(gre_m->protocol));
5350         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5351                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5352         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5353         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5354         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5355                  gre_crks_rsvd0_ver_m.c_present);
5356         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5357                  gre_crks_rsvd0_ver_v.c_present &
5358                  gre_crks_rsvd0_ver_m.c_present);
5359         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5360                  gre_crks_rsvd0_ver_m.k_present);
5361         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5362                  gre_crks_rsvd0_ver_v.k_present &
5363                  gre_crks_rsvd0_ver_m.k_present);
5364         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5365                  gre_crks_rsvd0_ver_m.s_present);
5366         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5367                  gre_crks_rsvd0_ver_v.s_present &
5368                  gre_crks_rsvd0_ver_m.s_present);
5369 }
5370
5371 /**
5372  * Add NVGRE item to matcher and to the value.
5373  *
5374  * @param[in, out] matcher
5375  *   Flow matcher.
5376  * @param[in, out] key
5377  *   Flow matcher value.
5378  * @param[in] item
5379  *   Flow pattern to translate.
5380  * @param[in] inner
5381  *   Item is inner pattern.
5382  */
5383 static void
5384 flow_dv_translate_item_nvgre(void *matcher, void *key,
5385                              const struct rte_flow_item *item,
5386                              int inner)
5387 {
5388         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5389         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5390         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5391         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5392         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5393         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5394         char *gre_key_m;
5395         char *gre_key_v;
5396         int size;
5397         int i;
5398
5399         /* For NVGRE, GRE header fields must be set with defined values. */
5400         const struct rte_flow_item_gre gre_spec = {
5401                 .c_rsvd0_ver = RTE_BE16(0x2000),
5402                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5403         };
5404         const struct rte_flow_item_gre gre_mask = {
5405                 .c_rsvd0_ver = RTE_BE16(0xB000),
5406                 .protocol = RTE_BE16(UINT16_MAX),
5407         };
5408         const struct rte_flow_item gre_item = {
5409                 .spec = &gre_spec,
5410                 .mask = &gre_mask,
5411                 .last = NULL,
5412         };
5413         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5414         if (!nvgre_v)
5415                 return;
5416         if (!nvgre_m)
5417                 nvgre_m = &rte_flow_item_nvgre_mask;
5418         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5419         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5420         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5421         memcpy(gre_key_m, tni_flow_id_m, size);
5422         for (i = 0; i < size; ++i)
5423                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5424 }
5425
5426 /**
5427  * Add VXLAN item to matcher and to the value.
5428  *
5429  * @param[in, out] matcher
5430  *   Flow matcher.
5431  * @param[in, out] key
5432  *   Flow matcher value.
5433  * @param[in] item
5434  *   Flow pattern to translate.
5435  * @param[in] inner
5436  *   Item is inner pattern.
5437  */
5438 static void
5439 flow_dv_translate_item_vxlan(void *matcher, void *key,
5440                              const struct rte_flow_item *item,
5441                              int inner)
5442 {
5443         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5444         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5445         void *headers_m;
5446         void *headers_v;
5447         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5448         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5449         char *vni_m;
5450         char *vni_v;
5451         uint16_t dport;
5452         int size;
5453         int i;
5454
5455         if (inner) {
5456                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5457                                          inner_headers);
5458                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5459         } else {
5460                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5461                                          outer_headers);
5462                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5463         }
5464         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5465                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5466         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5467                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5468                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5469         }
5470         if (!vxlan_v)
5471                 return;
5472         if (!vxlan_m)
5473                 vxlan_m = &rte_flow_item_vxlan_mask;
5474         size = sizeof(vxlan_m->vni);
5475         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5476         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5477         memcpy(vni_m, vxlan_m->vni, size);
5478         for (i = 0; i < size; ++i)
5479                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5480 }
5481
5482 /**
5483  * Add Geneve item to matcher and to the value.
5484  *
5485  * @param[in, out] matcher
5486  *   Flow matcher.
5487  * @param[in, out] key
5488  *   Flow matcher value.
5489  * @param[in] item
5490  *   Flow pattern to translate.
5491  * @param[in] inner
5492  *   Item is inner pattern.
5493  */
5494
5495 static void
5496 flow_dv_translate_item_geneve(void *matcher, void *key,
5497                               const struct rte_flow_item *item, int inner)
5498 {
5499         const struct rte_flow_item_geneve *geneve_m = item->mask;
5500         const struct rte_flow_item_geneve *geneve_v = item->spec;
5501         void *headers_m;
5502         void *headers_v;
5503         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5504         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5505         uint16_t dport;
5506         uint16_t gbhdr_m;
5507         uint16_t gbhdr_v;
5508         char *vni_m;
5509         char *vni_v;
5510         size_t size, i;
5511
5512         if (inner) {
5513                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5514                                          inner_headers);
5515                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5516         } else {
5517                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5518                                          outer_headers);
5519                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5520         }
5521         dport = MLX5_UDP_PORT_GENEVE;
5522         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5523                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5524                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5525         }
5526         if (!geneve_v)
5527                 return;
5528         if (!geneve_m)
5529                 geneve_m = &rte_flow_item_geneve_mask;
5530         size = sizeof(geneve_m->vni);
5531         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5532         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5533         memcpy(vni_m, geneve_m->vni, size);
5534         for (i = 0; i < size; ++i)
5535                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5536         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5537                  rte_be_to_cpu_16(geneve_m->protocol));
5538         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5539                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5540         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5541         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5542         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5543                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5544         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5545                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5546         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5547                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5548         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5549                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5550                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5551 }
5552
5553 /**
5554  * Add MPLS item to matcher and to the value.
5555  *
5556  * @param[in, out] matcher
5557  *   Flow matcher.
5558  * @param[in, out] key
5559  *   Flow matcher value.
5560  * @param[in] item
5561  *   Flow pattern to translate.
5562  * @param[in] prev_layer
5563  *   The protocol layer indicated in previous item.
5564  * @param[in] inner
5565  *   Item is inner pattern.
5566  */
5567 static void
5568 flow_dv_translate_item_mpls(void *matcher, void *key,
5569                             const struct rte_flow_item *item,
5570                             uint64_t prev_layer,
5571                             int inner)
5572 {
5573         const uint32_t *in_mpls_m = item->mask;
5574         const uint32_t *in_mpls_v = item->spec;
5575         uint32_t *out_mpls_m = 0;
5576         uint32_t *out_mpls_v = 0;
5577         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5578         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5579         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5580                                      misc_parameters_2);
5581         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5582         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5583         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5584
5585         switch (prev_layer) {
5586         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5587                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5588                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5589                          MLX5_UDP_PORT_MPLS);
5590                 break;
5591         case MLX5_FLOW_LAYER_GRE:
5592                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5593                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5594                          RTE_ETHER_TYPE_MPLS);
5595                 break;
5596         default:
5597                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5598                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5599                          IPPROTO_MPLS);
5600                 break;
5601         }
5602         if (!in_mpls_v)
5603                 return;
5604         if (!in_mpls_m)
5605                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5606         switch (prev_layer) {
5607         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5608                 out_mpls_m =
5609                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5610                                                  outer_first_mpls_over_udp);
5611                 out_mpls_v =
5612                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5613                                                  outer_first_mpls_over_udp);
5614                 break;
5615         case MLX5_FLOW_LAYER_GRE:
5616                 out_mpls_m =
5617                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5618                                                  outer_first_mpls_over_gre);
5619                 out_mpls_v =
5620                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5621                                                  outer_first_mpls_over_gre);
5622                 break;
5623         default:
5624                 /* Inner MPLS not over GRE is not supported. */
5625                 if (!inner) {
5626                         out_mpls_m =
5627                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5628                                                          misc2_m,
5629                                                          outer_first_mpls);
5630                         out_mpls_v =
5631                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5632                                                          misc2_v,
5633                                                          outer_first_mpls);
5634                 }
5635                 break;
5636         }
5637         if (out_mpls_m && out_mpls_v) {
5638                 *out_mpls_m = *in_mpls_m;
5639                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5640         }
5641 }
5642
5643 /**
5644  * Add metadata register item to matcher
5645  *
5646  * @param[in, out] matcher
5647  *   Flow matcher.
5648  * @param[in, out] key
5649  *   Flow matcher value.
5650  * @param[in] reg_type
5651  *   Type of device metadata register
5652  * @param[in] value
5653  *   Register value
5654  * @param[in] mask
5655  *   Register mask
5656  */
5657 static void
5658 flow_dv_match_meta_reg(void *matcher, void *key,
5659                        enum modify_reg reg_type,
5660                        uint32_t data, uint32_t mask)
5661 {
5662         void *misc2_m =
5663                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5664         void *misc2_v =
5665                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5666
5667         data &= mask;
5668         switch (reg_type) {
5669         case REG_A:
5670                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5671                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5672                 break;
5673         case REG_B:
5674                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5675                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5676                 break;
5677         case REG_C_0:
5678                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5679                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5680                 break;
5681         case REG_C_1:
5682                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5683                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5684                 break;
5685         case REG_C_2:
5686                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5687                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5688                 break;
5689         case REG_C_3:
5690                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5691                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5692                 break;
5693         case REG_C_4:
5694                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5695                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5696                 break;
5697         case REG_C_5:
5698                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5699                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5700                 break;
5701         case REG_C_6:
5702                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5703                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5704                 break;
5705         case REG_C_7:
5706                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5707                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5708                 break;
5709         default:
5710                 assert(false);
5711                 break;
5712         }
5713 }
5714
5715 /**
5716  * Add MARK item to matcher
5717  *
5718  * @param[in] dev
5719  *   The device to configure through.
5720  * @param[in, out] matcher
5721  *   Flow matcher.
5722  * @param[in, out] key
5723  *   Flow matcher value.
5724  * @param[in] item
5725  *   Flow pattern to translate.
5726  */
5727 static void
5728 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
5729                             void *matcher, void *key,
5730                             const struct rte_flow_item *item)
5731 {
5732         struct mlx5_priv *priv = dev->data->dev_private;
5733         const struct rte_flow_item_mark *mark;
5734         uint32_t value;
5735         uint32_t mask;
5736
5737         mark = item->mask ? (const void *)item->mask :
5738                             &rte_flow_item_mark_mask;
5739         mask = mark->id & priv->sh->dv_mark_mask;
5740         mark = (const void *)item->spec;
5741         assert(mark);
5742         value = mark->id & priv->sh->dv_mark_mask & mask;
5743         if (mask) {
5744                 enum modify_reg reg;
5745
5746                 /* Get the metadata register index for the mark. */
5747                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
5748                 assert(reg > 0);
5749                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
5750         }
5751 }
5752
5753 /**
5754  * Add META item to matcher
5755  *
5756  * @param[in] dev
5757  *   The devich to configure through.
5758  * @param[in, out] matcher
5759  *   Flow matcher.
5760  * @param[in, out] key
5761  *   Flow matcher value.
5762  * @param[in] attr
5763  *   Attributes of flow that includes this item.
5764  * @param[in] item
5765  *   Flow pattern to translate.
5766  */
5767 static void
5768 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
5769                             void *matcher, void *key,
5770                             const struct rte_flow_attr *attr,
5771                             const struct rte_flow_item *item)
5772 {
5773         const struct rte_flow_item_meta *meta_m;
5774         const struct rte_flow_item_meta *meta_v;
5775
5776         meta_m = (const void *)item->mask;
5777         if (!meta_m)
5778                 meta_m = &rte_flow_item_meta_mask;
5779         meta_v = (const void *)item->spec;
5780         if (meta_v) {
5781                 enum modify_reg reg;
5782                 uint32_t value = meta_v->data;
5783                 uint32_t mask = meta_m->data;
5784
5785                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
5786                 if (reg < 0)
5787                         return;
5788                 /*
5789                  * In datapath code there is no endianness
5790                  * coversions for perfromance reasons, all
5791                  * pattern conversions are done in rte_flow.
5792                  */
5793                 value = rte_cpu_to_be_32(value);
5794                 mask = rte_cpu_to_be_32(mask);
5795                 if (reg == REG_C_0) {
5796                         struct mlx5_priv *priv = dev->data->dev_private;
5797                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
5798                         uint32_t shl_c0 = rte_bsf32(msk_c0);
5799
5800                         msk_c0 = rte_cpu_to_be_32(msk_c0);
5801                         value <<= shl_c0;
5802                         mask <<= shl_c0;
5803                         assert(msk_c0);
5804                         assert(!(~msk_c0 & mask));
5805                 }
5806                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
5807         }
5808 }
5809
5810 /**
5811  * Add vport metadata Reg C0 item to matcher
5812  *
5813  * @param[in, out] matcher
5814  *   Flow matcher.
5815  * @param[in, out] key
5816  *   Flow matcher value.
5817  * @param[in] reg
5818  *   Flow pattern to translate.
5819  */
5820 static void
5821 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5822                                   uint32_t value, uint32_t mask)
5823 {
5824         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5825 }
5826
5827 /**
5828  * Add tag item to matcher
5829  *
5830  * @param[in, out] matcher
5831  *   Flow matcher.
5832  * @param[in, out] key
5833  *   Flow matcher value.
5834  * @param[in] item
5835  *   Flow pattern to translate.
5836  */
5837 static void
5838 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5839                                 const struct rte_flow_item *item)
5840 {
5841         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5842         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5843
5844         assert(tag_v);
5845         flow_dv_match_meta_reg(matcher, key, tag_v->id, tag_v->data,
5846                                tag_m ? tag_m->data : UINT32_MAX);
5847 }
5848
5849 /**
5850  * Add TAG item to matcher
5851  *
5852  * @param[in] dev
5853  *   The devich to configure through.
5854  * @param[in, out] matcher
5855  *   Flow matcher.
5856  * @param[in, out] key
5857  *   Flow matcher value.
5858  * @param[in] item
5859  *   Flow pattern to translate.
5860  */
5861 static void
5862 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
5863                            void *matcher, void *key,
5864                            const struct rte_flow_item *item)
5865 {
5866         const struct rte_flow_item_tag *tag_v = item->spec;
5867         const struct rte_flow_item_tag *tag_m = item->mask;
5868         enum modify_reg reg;
5869
5870         assert(tag_v);
5871         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
5872         /* Get the metadata register index for the tag. */
5873         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
5874         assert(reg > 0);
5875         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5876 }
5877
5878 /**
5879  * Add source vport match to the specified matcher.
5880  *
5881  * @param[in, out] matcher
5882  *   Flow matcher.
5883  * @param[in, out] key
5884  *   Flow matcher value.
5885  * @param[in] port
5886  *   Source vport value to match
5887  * @param[in] mask
5888  *   Mask
5889  */
5890 static void
5891 flow_dv_translate_item_source_vport(void *matcher, void *key,
5892                                     int16_t port, uint16_t mask)
5893 {
5894         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5895         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5896
5897         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5898         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5899 }
5900
5901 /**
5902  * Translate port-id item to eswitch match on  port-id.
5903  *
5904  * @param[in] dev
5905  *   The devich to configure through.
5906  * @param[in, out] matcher
5907  *   Flow matcher.
5908  * @param[in, out] key
5909  *   Flow matcher value.
5910  * @param[in] item
5911  *   Flow pattern to translate.
5912  *
5913  * @return
5914  *   0 on success, a negative errno value otherwise.
5915  */
5916 static int
5917 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5918                                void *key, const struct rte_flow_item *item)
5919 {
5920         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5921         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5922         struct mlx5_priv *priv;
5923         uint16_t mask, id;
5924
5925         mask = pid_m ? pid_m->id : 0xffff;
5926         id = pid_v ? pid_v->id : dev->data->port_id;
5927         priv = mlx5_port_to_eswitch_info(id, item == NULL);
5928         if (!priv)
5929                 return -rte_errno;
5930         /* Translate to vport field or to metadata, depending on mode. */
5931         if (priv->vport_meta_mask)
5932                 flow_dv_translate_item_meta_vport(matcher, key,
5933                                                   priv->vport_meta_tag,
5934                                                   priv->vport_meta_mask);
5935         else
5936                 flow_dv_translate_item_source_vport(matcher, key,
5937                                                     priv->vport_id, mask);
5938         return 0;
5939 }
5940
5941 /**
5942  * Add ICMP6 item to matcher and to the value.
5943  *
5944  * @param[in, out] matcher
5945  *   Flow matcher.
5946  * @param[in, out] key
5947  *   Flow matcher value.
5948  * @param[in] item
5949  *   Flow pattern to translate.
5950  * @param[in] inner
5951  *   Item is inner pattern.
5952  */
5953 static void
5954 flow_dv_translate_item_icmp6(void *matcher, void *key,
5955                               const struct rte_flow_item *item,
5956                               int inner)
5957 {
5958         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5959         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5960         void *headers_m;
5961         void *headers_v;
5962         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5963                                      misc_parameters_3);
5964         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5965         if (inner) {
5966                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5967                                          inner_headers);
5968                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5969         } else {
5970                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5971                                          outer_headers);
5972                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5973         }
5974         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5975         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5976         if (!icmp6_v)
5977                 return;
5978         if (!icmp6_m)
5979                 icmp6_m = &rte_flow_item_icmp6_mask;
5980         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5981         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5982                  icmp6_v->type & icmp6_m->type);
5983         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5984         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5985                  icmp6_v->code & icmp6_m->code);
5986 }
5987
5988 /**
5989  * Add ICMP item to matcher and to the value.
5990  *
5991  * @param[in, out] matcher
5992  *   Flow matcher.
5993  * @param[in, out] key
5994  *   Flow matcher value.
5995  * @param[in] item
5996  *   Flow pattern to translate.
5997  * @param[in] inner
5998  *   Item is inner pattern.
5999  */
6000 static void
6001 flow_dv_translate_item_icmp(void *matcher, void *key,
6002                             const struct rte_flow_item *item,
6003                             int inner)
6004 {
6005         const struct rte_flow_item_icmp *icmp_m = item->mask;
6006         const struct rte_flow_item_icmp *icmp_v = item->spec;
6007         void *headers_m;
6008         void *headers_v;
6009         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6010                                      misc_parameters_3);
6011         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6012         if (inner) {
6013                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6014                                          inner_headers);
6015                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6016         } else {
6017                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6018                                          outer_headers);
6019                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6020         }
6021         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6022         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6023         if (!icmp_v)
6024                 return;
6025         if (!icmp_m)
6026                 icmp_m = &rte_flow_item_icmp_mask;
6027         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6028                  icmp_m->hdr.icmp_type);
6029         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6030                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6031         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6032                  icmp_m->hdr.icmp_code);
6033         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6034                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6035 }
6036
6037 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6038
6039 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6040         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6041                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6042
6043 /**
6044  * Calculate flow matcher enable bitmap.
6045  *
6046  * @param match_criteria
6047  *   Pointer to flow matcher criteria.
6048  *
6049  * @return
6050  *   Bitmap of enabled fields.
6051  */
6052 static uint8_t
6053 flow_dv_matcher_enable(uint32_t *match_criteria)
6054 {
6055         uint8_t match_criteria_enable;
6056
6057         match_criteria_enable =
6058                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6059                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6060         match_criteria_enable |=
6061                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6062                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6063         match_criteria_enable |=
6064                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6065                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6066         match_criteria_enable |=
6067                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6068                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6069         match_criteria_enable |=
6070                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6071                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6072         return match_criteria_enable;
6073 }
6074
6075
6076 /**
6077  * Get a flow table.
6078  *
6079  * @param dev[in, out]
6080  *   Pointer to rte_eth_dev structure.
6081  * @param[in] table_id
6082  *   Table id to use.
6083  * @param[in] egress
6084  *   Direction of the table.
6085  * @param[in] transfer
6086  *   E-Switch or NIC flow.
6087  * @param[out] error
6088  *   pointer to error structure.
6089  *
6090  * @return
6091  *   Returns tables resource based on the index, NULL in case of failed.
6092  */
6093 static struct mlx5_flow_tbl_resource *
6094 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6095                          uint32_t table_id, uint8_t egress,
6096                          uint8_t transfer,
6097                          struct rte_flow_error *error)
6098 {
6099         struct mlx5_priv *priv = dev->data->dev_private;
6100         struct mlx5_ibv_shared *sh = priv->sh;
6101         struct mlx5_flow_tbl_resource *tbl;
6102
6103 #ifdef HAVE_MLX5DV_DR
6104         if (transfer) {
6105                 tbl = &sh->fdb_tbl[table_id];
6106                 if (!tbl->obj)
6107                         tbl->obj = mlx5_glue->dr_create_flow_tbl
6108                                 (sh->fdb_domain, table_id);
6109         } else if (egress) {
6110                 tbl = &sh->tx_tbl[table_id];
6111                 if (!tbl->obj)
6112                         tbl->obj = mlx5_glue->dr_create_flow_tbl
6113                                 (sh->tx_domain, table_id);
6114         } else {
6115                 tbl = &sh->rx_tbl[table_id];
6116                 if (!tbl->obj)
6117                         tbl->obj = mlx5_glue->dr_create_flow_tbl
6118                                 (sh->rx_domain, table_id);
6119         }
6120         if (!tbl->obj) {
6121                 rte_flow_error_set(error, ENOMEM,
6122                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6123                                    NULL, "cannot create table");
6124                 return NULL;
6125         }
6126         rte_atomic32_inc(&tbl->refcnt);
6127         return tbl;
6128 #else
6129         (void)error;
6130         (void)tbl;
6131         if (transfer)
6132                 return &sh->fdb_tbl[table_id];
6133         else if (egress)
6134                 return &sh->tx_tbl[table_id];
6135         else
6136                 return &sh->rx_tbl[table_id];
6137 #endif
6138 }
6139
6140 /**
6141  * Release a flow table.
6142  *
6143  * @param[in] tbl
6144  *   Table resource to be released.
6145  *
6146  * @return
6147  *   Returns 0 if table was released, else return 1;
6148  */
6149 static int
6150 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
6151 {
6152         if (!tbl)
6153                 return 0;
6154         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6155                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6156                 tbl->obj = NULL;
6157                 return 0;
6158         }
6159         return 1;
6160 }
6161
6162 /**
6163  * Register the flow matcher.
6164  *
6165  * @param dev[in, out]
6166  *   Pointer to rte_eth_dev structure.
6167  * @param[in, out] matcher
6168  *   Pointer to flow matcher.
6169  * @parm[in, out] dev_flow
6170  *   Pointer to the dev_flow.
6171  * @param[out] error
6172  *   pointer to error structure.
6173  *
6174  * @return
6175  *   0 on success otherwise -errno and errno is set.
6176  */
6177 static int
6178 flow_dv_matcher_register(struct rte_eth_dev *dev,
6179                          struct mlx5_flow_dv_matcher *matcher,
6180                          struct mlx5_flow *dev_flow,
6181                          struct rte_flow_error *error)
6182 {
6183         struct mlx5_priv *priv = dev->data->dev_private;
6184         struct mlx5_ibv_shared *sh = priv->sh;
6185         struct mlx5_flow_dv_matcher *cache_matcher;
6186         struct mlx5dv_flow_matcher_attr dv_attr = {
6187                 .type = IBV_FLOW_ATTR_NORMAL,
6188                 .match_mask = (void *)&matcher->mask,
6189         };
6190         struct mlx5_flow_tbl_resource *tbl = NULL;
6191
6192         /* Lookup from cache. */
6193         LIST_FOREACH(cache_matcher, &sh->matchers, next) {
6194                 if (matcher->crc == cache_matcher->crc &&
6195                     matcher->priority == cache_matcher->priority &&
6196                     matcher->egress == cache_matcher->egress &&
6197                     matcher->group == cache_matcher->group &&
6198                     matcher->transfer == cache_matcher->transfer &&
6199                     !memcmp((const void *)matcher->mask.buf,
6200                             (const void *)cache_matcher->mask.buf,
6201                             cache_matcher->mask.size)) {
6202                         DRV_LOG(DEBUG,
6203                                 "priority %hd use %s matcher %p: refcnt %d++",
6204                                 cache_matcher->priority,
6205                                 cache_matcher->egress ? "tx" : "rx",
6206                                 (void *)cache_matcher,
6207                                 rte_atomic32_read(&cache_matcher->refcnt));
6208                         rte_atomic32_inc(&cache_matcher->refcnt);
6209                         dev_flow->dv.matcher = cache_matcher;
6210                         return 0;
6211                 }
6212         }
6213         /* Register new matcher. */
6214         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6215         if (!cache_matcher)
6216                 return rte_flow_error_set(error, ENOMEM,
6217                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6218                                           "cannot allocate matcher memory");
6219         tbl = flow_dv_tbl_resource_get(dev, matcher->group,
6220                                        matcher->egress, matcher->transfer,
6221                                        error);
6222         if (!tbl) {
6223                 rte_free(cache_matcher);
6224                 return rte_flow_error_set(error, ENOMEM,
6225                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6226                                           NULL, "cannot create table");
6227         }
6228         *cache_matcher = *matcher;
6229         dv_attr.match_criteria_enable =
6230                 flow_dv_matcher_enable(cache_matcher->mask.buf);
6231         dv_attr.priority = matcher->priority;
6232         if (matcher->egress)
6233                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6234         cache_matcher->matcher_object =
6235                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6236         if (!cache_matcher->matcher_object) {
6237                 rte_free(cache_matcher);
6238 #ifdef HAVE_MLX5DV_DR
6239                 flow_dv_tbl_resource_release(tbl);
6240 #endif
6241                 return rte_flow_error_set(error, ENOMEM,
6242                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6243                                           NULL, "cannot create matcher");
6244         }
6245         rte_atomic32_inc(&cache_matcher->refcnt);
6246         LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
6247         dev_flow->dv.matcher = cache_matcher;
6248         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
6249                 cache_matcher->priority,
6250                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
6251                 rte_atomic32_read(&cache_matcher->refcnt));
6252         rte_atomic32_inc(&tbl->refcnt);
6253         return 0;
6254 }
6255
6256 /**
6257  * Find existing tag resource or create and register a new one.
6258  *
6259  * @param dev[in, out]
6260  *   Pointer to rte_eth_dev structure.
6261  * @param[in, out] resource
6262  *   Pointer to tag resource.
6263  * @parm[in, out] dev_flow
6264  *   Pointer to the dev_flow.
6265  * @param[out] error
6266  *   pointer to error structure.
6267  *
6268  * @return
6269  *   0 on success otherwise -errno and errno is set.
6270  */
6271 static int
6272 flow_dv_tag_resource_register
6273                         (struct rte_eth_dev *dev,
6274                          struct mlx5_flow_dv_tag_resource *resource,
6275                          struct mlx5_flow *dev_flow,
6276                          struct rte_flow_error *error)
6277 {
6278         struct mlx5_priv *priv = dev->data->dev_private;
6279         struct mlx5_ibv_shared *sh = priv->sh;
6280         struct mlx5_flow_dv_tag_resource *cache_resource;
6281
6282         /* Lookup a matching resource from cache. */
6283         LIST_FOREACH(cache_resource, &sh->tags, next) {
6284                 if (resource->tag == cache_resource->tag) {
6285                         DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
6286                                 (void *)cache_resource,
6287                                 rte_atomic32_read(&cache_resource->refcnt));
6288                         rte_atomic32_inc(&cache_resource->refcnt);
6289                         dev_flow->dv.tag_resource = cache_resource;
6290                         return 0;
6291                 }
6292         }
6293         /* Register new  resource. */
6294         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6295         if (!cache_resource)
6296                 return rte_flow_error_set(error, ENOMEM,
6297                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6298                                           "cannot allocate resource memory");
6299         *cache_resource = *resource;
6300         cache_resource->action = mlx5_glue->dv_create_flow_action_tag
6301                 (resource->tag);
6302         if (!cache_resource->action) {
6303                 rte_free(cache_resource);
6304                 return rte_flow_error_set(error, ENOMEM,
6305                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6306                                           NULL, "cannot create action");
6307         }
6308         rte_atomic32_init(&cache_resource->refcnt);
6309         rte_atomic32_inc(&cache_resource->refcnt);
6310         LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
6311         dev_flow->dv.tag_resource = cache_resource;
6312         DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
6313                 (void *)cache_resource,
6314                 rte_atomic32_read(&cache_resource->refcnt));
6315         return 0;
6316 }
6317
6318 /**
6319  * Release the tag.
6320  *
6321  * @param dev
6322  *   Pointer to Ethernet device.
6323  * @param flow
6324  *   Pointer to mlx5_flow.
6325  *
6326  * @return
6327  *   1 while a reference on it exists, 0 when freed.
6328  */
6329 static int
6330 flow_dv_tag_release(struct rte_eth_dev *dev,
6331                     struct mlx5_flow_dv_tag_resource *tag)
6332 {
6333         assert(tag);
6334         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6335                 dev->data->port_id, (void *)tag,
6336                 rte_atomic32_read(&tag->refcnt));
6337         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6338                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6339                 LIST_REMOVE(tag, next);
6340                 DRV_LOG(DEBUG, "port %u tag %p: removed",
6341                         dev->data->port_id, (void *)tag);
6342                 rte_free(tag);
6343                 return 0;
6344         }
6345         return 1;
6346 }
6347
6348 /**
6349  * Translate port ID action to vport.
6350  *
6351  * @param[in] dev
6352  *   Pointer to rte_eth_dev structure.
6353  * @param[in] action
6354  *   Pointer to the port ID action.
6355  * @param[out] dst_port_id
6356  *   The target port ID.
6357  * @param[out] error
6358  *   Pointer to the error structure.
6359  *
6360  * @return
6361  *   0 on success, a negative errno value otherwise and rte_errno is set.
6362  */
6363 static int
6364 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6365                                  const struct rte_flow_action *action,
6366                                  uint32_t *dst_port_id,
6367                                  struct rte_flow_error *error)
6368 {
6369         uint32_t port;
6370         struct mlx5_priv *priv;
6371         const struct rte_flow_action_port_id *conf =
6372                         (const struct rte_flow_action_port_id *)action->conf;
6373
6374         port = conf->original ? dev->data->port_id : conf->id;
6375         priv = mlx5_port_to_eswitch_info(port, false);
6376         if (!priv)
6377                 return rte_flow_error_set(error, -rte_errno,
6378                                           RTE_FLOW_ERROR_TYPE_ACTION,
6379                                           NULL,
6380                                           "No eswitch info was found for port");
6381         if (priv->vport_meta_mask)
6382                 *dst_port_id = priv->vport_meta_tag;
6383         else
6384                 *dst_port_id = priv->vport_id;
6385         return 0;
6386 }
6387
6388 /**
6389  * Add Tx queue matcher
6390  *
6391  * @param[in] dev
6392  *   Pointer to the dev struct.
6393  * @param[in, out] matcher
6394  *   Flow matcher.
6395  * @param[in, out] key
6396  *   Flow matcher value.
6397  * @param[in] item
6398  *   Flow pattern to translate.
6399  * @param[in] inner
6400  *   Item is inner pattern.
6401  */
6402 static void
6403 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6404                                 void *matcher, void *key,
6405                                 const struct rte_flow_item *item)
6406 {
6407         const struct mlx5_rte_flow_item_tx_queue *queue_m;
6408         const struct mlx5_rte_flow_item_tx_queue *queue_v;
6409         void *misc_m =
6410                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6411         void *misc_v =
6412                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6413         struct mlx5_txq_ctrl *txq;
6414         uint32_t queue;
6415
6416
6417         queue_m = (const void *)item->mask;
6418         if (!queue_m)
6419                 return;
6420         queue_v = (const void *)item->spec;
6421         if (!queue_v)
6422                 return;
6423         txq = mlx5_txq_get(dev, queue_v->queue);
6424         if (!txq)
6425                 return;
6426         queue = txq->obj->sq->id;
6427         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6428         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6429                  queue & queue_m->queue);
6430         mlx5_txq_release(dev, queue_v->queue);
6431 }
6432
6433 /**
6434  * Fill the flow with DV spec, lock free
6435  * (mutex should be acquired by caller).
6436  *
6437  * @param[in] dev
6438  *   Pointer to rte_eth_dev structure.
6439  * @param[in, out] dev_flow
6440  *   Pointer to the sub flow.
6441  * @param[in] attr
6442  *   Pointer to the flow attributes.
6443  * @param[in] items
6444  *   Pointer to the list of items.
6445  * @param[in] actions
6446  *   Pointer to the list of actions.
6447  * @param[out] error
6448  *   Pointer to the error structure.
6449  *
6450  * @return
6451  *   0 on success, a negative errno value otherwise and rte_errno is set.
6452  */
6453 static int
6454 __flow_dv_translate(struct rte_eth_dev *dev,
6455                     struct mlx5_flow *dev_flow,
6456                     const struct rte_flow_attr *attr,
6457                     const struct rte_flow_item items[],
6458                     const struct rte_flow_action actions[],
6459                     struct rte_flow_error *error)
6460 {
6461         struct mlx5_priv *priv = dev->data->dev_private;
6462         struct mlx5_dev_config *dev_conf = &priv->config;
6463         struct rte_flow *flow = dev_flow->flow;
6464         uint64_t item_flags = 0;
6465         uint64_t last_item = 0;
6466         uint64_t action_flags = 0;
6467         uint64_t priority = attr->priority;
6468         struct mlx5_flow_dv_matcher matcher = {
6469                 .mask = {
6470                         .size = sizeof(matcher.mask.buf),
6471                 },
6472         };
6473         int actions_n = 0;
6474         bool actions_end = false;
6475         struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
6476                 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
6477                                           MLX5DV_FLOW_TABLE_TYPE_NIC_RX
6478         };
6479         union flow_dv_attr flow_attr = { .attr = 0 };
6480         struct mlx5_flow_dv_tag_resource tag_resource;
6481         uint32_t modify_action_position = UINT32_MAX;
6482         void *match_mask = matcher.mask.buf;
6483         void *match_value = dev_flow->dv.value.buf;
6484         uint8_t next_protocol = 0xff;
6485         struct rte_vlan_hdr vlan = { 0 };
6486         uint32_t table;
6487         int ret = 0;
6488
6489         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
6490                                        &table, error);
6491         if (ret)
6492                 return ret;
6493         dev_flow->group = table;
6494         if (attr->transfer)
6495                 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
6496         if (priority == MLX5_FLOW_PRIO_RSVD)
6497                 priority = dev_conf->flow_prio - 1;
6498         for (; !actions_end ; actions++) {
6499                 const struct rte_flow_action_queue *queue;
6500                 const struct rte_flow_action_rss *rss;
6501                 const struct rte_flow_action *action = actions;
6502                 const struct rte_flow_action_count *count = action->conf;
6503                 const uint8_t *rss_key;
6504                 const struct rte_flow_action_jump *jump_data;
6505                 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
6506                 struct mlx5_flow_tbl_resource *tbl;
6507                 uint32_t port_id = 0;
6508                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
6509                 int action_type = actions->type;
6510                 const struct rte_flow_action *found_action = NULL;
6511
6512                 switch (action_type) {
6513                 case RTE_FLOW_ACTION_TYPE_VOID:
6514                         break;
6515                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6516                         if (flow_dv_translate_action_port_id(dev, action,
6517                                                              &port_id, error))
6518                                 return -rte_errno;
6519                         port_id_resource.port_id = port_id;
6520                         if (flow_dv_port_id_action_resource_register
6521                             (dev, &port_id_resource, dev_flow, error))
6522                                 return -rte_errno;
6523                         dev_flow->dv.actions[actions_n++] =
6524                                 dev_flow->dv.port_id_action->action;
6525                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6526                         break;
6527                 case RTE_FLOW_ACTION_TYPE_FLAG:
6528                         action_flags |= MLX5_FLOW_ACTION_FLAG;
6529                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6530                                 struct rte_flow_action_mark mark = {
6531                                         .id = MLX5_FLOW_MARK_DEFAULT,
6532                                 };
6533
6534                                 if (flow_dv_convert_action_mark(dev, &mark,
6535                                                                 &mhdr_res,
6536                                                                 error))
6537                                         return -rte_errno;
6538                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6539                                 break;
6540                         }
6541                         tag_resource.tag =
6542                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
6543                         if (!dev_flow->dv.tag_resource)
6544                                 if (flow_dv_tag_resource_register
6545                                     (dev, &tag_resource, dev_flow, error))
6546                                         return errno;
6547                         dev_flow->dv.actions[actions_n++] =
6548                                 dev_flow->dv.tag_resource->action;
6549                         break;
6550                 case RTE_FLOW_ACTION_TYPE_MARK:
6551                         action_flags |= MLX5_FLOW_ACTION_MARK;
6552                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6553                                 const struct rte_flow_action_mark *mark =
6554                                         (const struct rte_flow_action_mark *)
6555                                                 actions->conf;
6556
6557                                 if (flow_dv_convert_action_mark(dev, mark,
6558                                                                 &mhdr_res,
6559                                                                 error))
6560                                         return -rte_errno;
6561                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
6562                                 break;
6563                         }
6564                         /* Fall-through */
6565                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6566                         /* Legacy (non-extensive) MARK action. */
6567                         tag_resource.tag = mlx5_flow_mark_set
6568                               (((const struct rte_flow_action_mark *)
6569                                (actions->conf))->id);
6570                         if (!dev_flow->dv.tag_resource)
6571                                 if (flow_dv_tag_resource_register
6572                                     (dev, &tag_resource, dev_flow, error))
6573                                         return errno;
6574                         dev_flow->dv.actions[actions_n++] =
6575                                 dev_flow->dv.tag_resource->action;
6576                         break;
6577                 case RTE_FLOW_ACTION_TYPE_SET_META:
6578                         if (flow_dv_convert_action_set_meta
6579                                 (dev, &mhdr_res, attr,
6580                                  (const struct rte_flow_action_set_meta *)
6581                                   actions->conf, error))
6582                                 return -rte_errno;
6583                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6584                         break;
6585                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6586                         if (flow_dv_convert_action_set_tag
6587                                 (dev, &mhdr_res,
6588                                  (const struct rte_flow_action_set_tag *)
6589                                   actions->conf, error))
6590                                 return -rte_errno;
6591                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6592                         break;
6593                 case RTE_FLOW_ACTION_TYPE_DROP:
6594                         action_flags |= MLX5_FLOW_ACTION_DROP;
6595                         break;
6596                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6597                         assert(flow->rss.queue);
6598                         queue = actions->conf;
6599                         flow->rss.queue_num = 1;
6600                         (*flow->rss.queue)[0] = queue->index;
6601                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6602                         break;
6603                 case RTE_FLOW_ACTION_TYPE_RSS:
6604                         assert(flow->rss.queue);
6605                         rss = actions->conf;
6606                         if (flow->rss.queue)
6607                                 memcpy((*flow->rss.queue), rss->queue,
6608                                        rss->queue_num * sizeof(uint16_t));
6609                         flow->rss.queue_num = rss->queue_num;
6610                         /* NULL RSS key indicates default RSS key. */
6611                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
6612                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
6613                         /*
6614                          * rss->level and rss.types should be set in advance
6615                          * when expanding items for RSS.
6616                          */
6617                         action_flags |= MLX5_FLOW_ACTION_RSS;
6618                         break;
6619                 case RTE_FLOW_ACTION_TYPE_COUNT:
6620                         if (!dev_conf->devx) {
6621                                 rte_errno = ENOTSUP;
6622                                 goto cnt_err;
6623                         }
6624                         flow->counter = flow_dv_counter_alloc(dev,
6625                                                               count->shared,
6626                                                               count->id,
6627                                                               dev_flow->group);
6628                         if (flow->counter == NULL)
6629                                 goto cnt_err;
6630                         dev_flow->dv.actions[actions_n++] =
6631                                 flow->counter->action;
6632                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6633                         break;
6634 cnt_err:
6635                         if (rte_errno == ENOTSUP)
6636                                 return rte_flow_error_set
6637                                               (error, ENOTSUP,
6638                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6639                                                NULL,
6640                                                "count action not supported");
6641                         else
6642                                 return rte_flow_error_set
6643                                                 (error, rte_errno,
6644                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6645                                                  action,
6646                                                  "cannot create counter"
6647                                                   " object.");
6648                         break;
6649                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6650                         dev_flow->dv.actions[actions_n++] =
6651                                                 priv->sh->pop_vlan_action;
6652                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6653                         break;
6654                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6655                         flow_dev_get_vlan_info_from_items(items, &vlan);
6656                         vlan.eth_proto = rte_be_to_cpu_16
6657                              ((((const struct rte_flow_action_of_push_vlan *)
6658                                                    actions->conf)->ethertype));
6659                         found_action = mlx5_flow_find_action
6660                                         (actions + 1,
6661                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
6662                         if (found_action)
6663                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6664                         found_action = mlx5_flow_find_action
6665                                         (actions + 1,
6666                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
6667                         if (found_action)
6668                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
6669                         if (flow_dv_create_action_push_vlan
6670                                             (dev, attr, &vlan, dev_flow, error))
6671                                 return -rte_errno;
6672                         dev_flow->dv.actions[actions_n++] =
6673                                            dev_flow->dv.push_vlan_res->action;
6674                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6675                         break;
6676                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6677                         /* of_vlan_push action handled this action */
6678                         assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
6679                         break;
6680                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6681                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6682                                 break;
6683                         flow_dev_get_vlan_info_from_items(items, &vlan);
6684                         mlx5_update_vlan_vid_pcp(actions, &vlan);
6685                         /* If no VLAN push - this is a modify header action */
6686                         if (flow_dv_convert_action_modify_vlan_vid
6687                                                 (&mhdr_res, actions, error))
6688                                 return -rte_errno;
6689                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6690                         break;
6691                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6692                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6693                         if (flow_dv_create_action_l2_encap(dev, actions,
6694                                                            dev_flow,
6695                                                            attr->transfer,
6696                                                            error))
6697                                 return -rte_errno;
6698                         dev_flow->dv.actions[actions_n++] =
6699                                 dev_flow->dv.encap_decap->verbs_action;
6700                         action_flags |= actions->type ==
6701                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
6702                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
6703                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
6704                         break;
6705                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6706                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6707                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
6708                                                            attr->transfer,
6709                                                            error))
6710                                 return -rte_errno;
6711                         dev_flow->dv.actions[actions_n++] =
6712                                 dev_flow->dv.encap_decap->verbs_action;
6713                         action_flags |= actions->type ==
6714                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
6715                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
6716                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
6717                         break;
6718                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6719                         /* Handle encap with preceding decap. */
6720                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
6721                                 if (flow_dv_create_action_raw_encap
6722                                         (dev, actions, dev_flow, attr, error))
6723                                         return -rte_errno;
6724                                 dev_flow->dv.actions[actions_n++] =
6725                                         dev_flow->dv.encap_decap->verbs_action;
6726                         } else {
6727                                 /* Handle encap without preceding decap. */
6728                                 if (flow_dv_create_action_l2_encap
6729                                     (dev, actions, dev_flow, attr->transfer,
6730                                      error))
6731                                         return -rte_errno;
6732                                 dev_flow->dv.actions[actions_n++] =
6733                                         dev_flow->dv.encap_decap->verbs_action;
6734                         }
6735                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
6736                         break;
6737                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6738                         /* Check if this decap is followed by encap. */
6739                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
6740                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
6741                                action++) {
6742                         }
6743                         /* Handle decap only if it isn't followed by encap. */
6744                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6745                                 if (flow_dv_create_action_l2_decap
6746                                     (dev, dev_flow, attr->transfer, error))
6747                                         return -rte_errno;
6748                                 dev_flow->dv.actions[actions_n++] =
6749                                         dev_flow->dv.encap_decap->verbs_action;
6750                         }
6751                         /* If decap is followed by encap, handle it at encap. */
6752                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
6753                         break;
6754                 case RTE_FLOW_ACTION_TYPE_JUMP:
6755                         jump_data = action->conf;
6756                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
6757                                                        jump_data->group, &table,
6758                                                        error);
6759                         if (ret)
6760                                 return ret;
6761                         tbl = flow_dv_tbl_resource_get(dev, table,
6762                                                        attr->egress,
6763                                                        attr->transfer, error);
6764                         if (!tbl)
6765                                 return rte_flow_error_set
6766                                                 (error, errno,
6767                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6768                                                  NULL,
6769                                                  "cannot create jump action.");
6770                         jump_tbl_resource.tbl = tbl;
6771                         if (flow_dv_jump_tbl_resource_register
6772                             (dev, &jump_tbl_resource, dev_flow, error)) {
6773                                 flow_dv_tbl_resource_release(tbl);
6774                                 return rte_flow_error_set
6775                                                 (error, errno,
6776                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6777                                                  NULL,
6778                                                  "cannot create jump action.");
6779                         }
6780                         dev_flow->dv.actions[actions_n++] =
6781                                 dev_flow->dv.jump->action;
6782                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6783                         break;
6784                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6785                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6786                         if (flow_dv_convert_action_modify_mac
6787                                         (&mhdr_res, actions, error))
6788                                 return -rte_errno;
6789                         action_flags |= actions->type ==
6790                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6791                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
6792                                         MLX5_FLOW_ACTION_SET_MAC_DST;
6793                         break;
6794                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6795                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6796                         if (flow_dv_convert_action_modify_ipv4
6797                                         (&mhdr_res, actions, error))
6798                                 return -rte_errno;
6799                         action_flags |= actions->type ==
6800                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6801                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
6802                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
6803                         break;
6804                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6805                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6806                         if (flow_dv_convert_action_modify_ipv6
6807                                         (&mhdr_res, actions, error))
6808                                 return -rte_errno;
6809                         action_flags |= actions->type ==
6810                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6811                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
6812                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
6813                         break;
6814                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6815                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6816                         if (flow_dv_convert_action_modify_tp
6817                                         (&mhdr_res, actions, items,
6818                                          &flow_attr, error))
6819                                 return -rte_errno;
6820                         action_flags |= actions->type ==
6821                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6822                                         MLX5_FLOW_ACTION_SET_TP_SRC :
6823                                         MLX5_FLOW_ACTION_SET_TP_DST;
6824                         break;
6825                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6826                         if (flow_dv_convert_action_modify_dec_ttl
6827                                         (&mhdr_res, items, &flow_attr, error))
6828                                 return -rte_errno;
6829                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6830                         break;
6831                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6832                         if (flow_dv_convert_action_modify_ttl
6833                                         (&mhdr_res, actions, items,
6834                                          &flow_attr, error))
6835                                 return -rte_errno;
6836                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6837                         break;
6838                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6839                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6840                         if (flow_dv_convert_action_modify_tcp_seq
6841                                         (&mhdr_res, actions, error))
6842                                 return -rte_errno;
6843                         action_flags |= actions->type ==
6844                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6845                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
6846                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6847                         break;
6848
6849                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6850                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6851                         if (flow_dv_convert_action_modify_tcp_ack
6852                                         (&mhdr_res, actions, error))
6853                                 return -rte_errno;
6854                         action_flags |= actions->type ==
6855                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6856                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
6857                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
6858                         break;
6859                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6860                         if (flow_dv_convert_action_set_reg
6861                                         (&mhdr_res, actions, error))
6862                                 return -rte_errno;
6863                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6864                         break;
6865                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6866                         if (flow_dv_convert_action_copy_mreg
6867                                         (dev, &mhdr_res, actions, error))
6868                                 return -rte_errno;
6869                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6870                         break;
6871                 case RTE_FLOW_ACTION_TYPE_END:
6872                         actions_end = true;
6873                         if (mhdr_res.actions_num) {
6874                                 /* create modify action if needed. */
6875                                 if (flow_dv_modify_hdr_resource_register
6876                                         (dev, &mhdr_res, dev_flow, error))
6877                                         return -rte_errno;
6878                                 dev_flow->dv.actions[modify_action_position] =
6879                                         dev_flow->dv.modify_hdr->verbs_action;
6880                         }
6881                         break;
6882                 default:
6883                         break;
6884                 }
6885                 if (mhdr_res.actions_num &&
6886                     modify_action_position == UINT32_MAX)
6887                         modify_action_position = actions_n++;
6888         }
6889         dev_flow->dv.actions_n = actions_n;
6890         dev_flow->actions = action_flags;
6891         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6892                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6893                 int item_type = items->type;
6894
6895                 switch (item_type) {
6896                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6897                         flow_dv_translate_item_port_id(dev, match_mask,
6898                                                        match_value, items);
6899                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6900                         break;
6901                 case RTE_FLOW_ITEM_TYPE_ETH:
6902                         flow_dv_translate_item_eth(match_mask, match_value,
6903                                                    items, tunnel);
6904                         matcher.priority = MLX5_PRIORITY_MAP_L2;
6905                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6906                                              MLX5_FLOW_LAYER_OUTER_L2;
6907                         break;
6908                 case RTE_FLOW_ITEM_TYPE_VLAN:
6909                         flow_dv_translate_item_vlan(dev_flow,
6910                                                     match_mask, match_value,
6911                                                     items, tunnel);
6912                         matcher.priority = MLX5_PRIORITY_MAP_L2;
6913                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6914                                               MLX5_FLOW_LAYER_INNER_VLAN) :
6915                                              (MLX5_FLOW_LAYER_OUTER_L2 |
6916                                               MLX5_FLOW_LAYER_OUTER_VLAN);
6917                         break;
6918                 case RTE_FLOW_ITEM_TYPE_IPV4:
6919                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6920                                                   &item_flags, &tunnel);
6921                         flow_dv_translate_item_ipv4(match_mask, match_value,
6922                                                     items, tunnel,
6923                                                     dev_flow->group);
6924                         matcher.priority = MLX5_PRIORITY_MAP_L3;
6925                         dev_flow->hash_fields |=
6926                                 mlx5_flow_hashfields_adjust
6927                                         (dev_flow, tunnel,
6928                                          MLX5_IPV4_LAYER_TYPES,
6929                                          MLX5_IPV4_IBV_RX_HASH);
6930                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6931                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6932                         if (items->mask != NULL &&
6933                             ((const struct rte_flow_item_ipv4 *)
6934                              items->mask)->hdr.next_proto_id) {
6935                                 next_protocol =
6936                                         ((const struct rte_flow_item_ipv4 *)
6937                                          (items->spec))->hdr.next_proto_id;
6938                                 next_protocol &=
6939                                         ((const struct rte_flow_item_ipv4 *)
6940                                          (items->mask))->hdr.next_proto_id;
6941                         } else {
6942                                 /* Reset for inner layer. */
6943                                 next_protocol = 0xff;
6944                         }
6945                         break;
6946                 case RTE_FLOW_ITEM_TYPE_IPV6:
6947                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6948                                                   &item_flags, &tunnel);
6949                         flow_dv_translate_item_ipv6(match_mask, match_value,
6950                                                     items, tunnel,
6951                                                     dev_flow->group);
6952                         matcher.priority = MLX5_PRIORITY_MAP_L3;
6953                         dev_flow->hash_fields |=
6954                                 mlx5_flow_hashfields_adjust
6955                                         (dev_flow, tunnel,
6956                                          MLX5_IPV6_LAYER_TYPES,
6957                                          MLX5_IPV6_IBV_RX_HASH);
6958                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6959                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6960                         if (items->mask != NULL &&
6961                             ((const struct rte_flow_item_ipv6 *)
6962                              items->mask)->hdr.proto) {
6963                                 next_protocol =
6964                                         ((const struct rte_flow_item_ipv6 *)
6965                                          items->spec)->hdr.proto;
6966                                 next_protocol &=
6967                                         ((const struct rte_flow_item_ipv6 *)
6968                                          items->mask)->hdr.proto;
6969                         } else {
6970                                 /* Reset for inner layer. */
6971                                 next_protocol = 0xff;
6972                         }
6973                         break;
6974                 case RTE_FLOW_ITEM_TYPE_TCP:
6975                         flow_dv_translate_item_tcp(match_mask, match_value,
6976                                                    items, tunnel);
6977                         matcher.priority = MLX5_PRIORITY_MAP_L4;
6978                         dev_flow->hash_fields |=
6979                                 mlx5_flow_hashfields_adjust
6980                                         (dev_flow, tunnel, ETH_RSS_TCP,
6981                                          IBV_RX_HASH_SRC_PORT_TCP |
6982                                          IBV_RX_HASH_DST_PORT_TCP);
6983                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6984                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6985                         break;
6986                 case RTE_FLOW_ITEM_TYPE_UDP:
6987                         flow_dv_translate_item_udp(match_mask, match_value,
6988                                                    items, tunnel);
6989                         matcher.priority = MLX5_PRIORITY_MAP_L4;
6990                         dev_flow->hash_fields |=
6991                                 mlx5_flow_hashfields_adjust
6992                                         (dev_flow, tunnel, ETH_RSS_UDP,
6993                                          IBV_RX_HASH_SRC_PORT_UDP |
6994                                          IBV_RX_HASH_DST_PORT_UDP);
6995                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6996                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6997                         break;
6998                 case RTE_FLOW_ITEM_TYPE_GRE:
6999                         flow_dv_translate_item_gre(match_mask, match_value,
7000                                                    items, tunnel);
7001                         last_item = MLX5_FLOW_LAYER_GRE;
7002                         break;
7003                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7004                         flow_dv_translate_item_gre_key(match_mask,
7005                                                        match_value, items);
7006                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7007                         break;
7008                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7009                         flow_dv_translate_item_nvgre(match_mask, match_value,
7010                                                      items, tunnel);
7011                         last_item = MLX5_FLOW_LAYER_GRE;
7012                         break;
7013                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7014                         flow_dv_translate_item_vxlan(match_mask, match_value,
7015                                                      items, tunnel);
7016                         last_item = MLX5_FLOW_LAYER_VXLAN;
7017                         break;
7018                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7019                         flow_dv_translate_item_vxlan(match_mask, match_value,
7020                                                      items, tunnel);
7021                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7022                         break;
7023                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7024                         flow_dv_translate_item_geneve(match_mask, match_value,
7025                                                       items, tunnel);
7026                         last_item = MLX5_FLOW_LAYER_GENEVE;
7027                         break;
7028                 case RTE_FLOW_ITEM_TYPE_MPLS:
7029                         flow_dv_translate_item_mpls(match_mask, match_value,
7030                                                     items, last_item, tunnel);
7031                         last_item = MLX5_FLOW_LAYER_MPLS;
7032                         break;
7033                 case RTE_FLOW_ITEM_TYPE_MARK:
7034                         flow_dv_translate_item_mark(dev, match_mask,
7035                                                     match_value, items);
7036                         last_item = MLX5_FLOW_ITEM_MARK;
7037                         break;
7038                 case RTE_FLOW_ITEM_TYPE_META:
7039                         flow_dv_translate_item_meta(dev, match_mask,
7040                                                     match_value, attr, items);
7041                         last_item = MLX5_FLOW_ITEM_METADATA;
7042                         break;
7043                 case RTE_FLOW_ITEM_TYPE_ICMP:
7044                         flow_dv_translate_item_icmp(match_mask, match_value,
7045                                                     items, tunnel);
7046                         last_item = MLX5_FLOW_LAYER_ICMP;
7047                         break;
7048                 case RTE_FLOW_ITEM_TYPE_ICMP6:
7049                         flow_dv_translate_item_icmp6(match_mask, match_value,
7050                                                       items, tunnel);
7051                         last_item = MLX5_FLOW_LAYER_ICMP6;
7052                         break;
7053                 case RTE_FLOW_ITEM_TYPE_TAG:
7054                         flow_dv_translate_item_tag(dev, match_mask,
7055                                                    match_value, items);
7056                         last_item = MLX5_FLOW_ITEM_TAG;
7057                         break;
7058                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7059                         flow_dv_translate_mlx5_item_tag(match_mask,
7060                                                         match_value, items);
7061                         last_item = MLX5_FLOW_ITEM_TAG;
7062                         break;
7063                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7064                         flow_dv_translate_item_tx_queue(dev, match_mask,
7065                                                         match_value,
7066                                                         items);
7067                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7068                         break;
7069                 default:
7070                         break;
7071                 }
7072                 item_flags |= last_item;
7073         }
7074         /*
7075          * In case of ingress traffic when E-Switch mode is enabled,
7076          * we have two cases where we need to set the source port manually.
7077          * The first one, is in case of Nic steering rule, and the second is
7078          * E-Switch rule where no port_id item was found. In both cases
7079          * the source port is set according the current port in use.
7080          */
7081         if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
7082             (priv->representor || priv->master)) {
7083                 if (flow_dv_translate_item_port_id(dev, match_mask,
7084                                                    match_value, NULL))
7085                         return -rte_errno;
7086         }
7087         assert(!flow_dv_check_valid_spec(matcher.mask.buf,
7088                                          dev_flow->dv.value.buf));
7089         dev_flow->layers = item_flags;
7090         /* Register matcher. */
7091         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7092                                     matcher.mask.size);
7093         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7094                                                      matcher.priority);
7095         matcher.egress = attr->egress;
7096         matcher.group = dev_flow->group;
7097         matcher.transfer = attr->transfer;
7098         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
7099                 return -rte_errno;
7100         return 0;
7101 }
7102
7103 /**
7104  * Apply the flow to the NIC, lock free,
7105  * (mutex should be acquired by caller).
7106  *
7107  * @param[in] dev
7108  *   Pointer to the Ethernet device structure.
7109  * @param[in, out] flow
7110  *   Pointer to flow structure.
7111  * @param[out] error
7112  *   Pointer to error structure.
7113  *
7114  * @return
7115  *   0 on success, a negative errno value otherwise and rte_errno is set.
7116  */
7117 static int
7118 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7119                 struct rte_flow_error *error)
7120 {
7121         struct mlx5_flow_dv *dv;
7122         struct mlx5_flow *dev_flow;
7123         struct mlx5_priv *priv = dev->data->dev_private;
7124         int n;
7125         int err;
7126
7127         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7128                 dv = &dev_flow->dv;
7129                 n = dv->actions_n;
7130                 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7131                         if (dev_flow->transfer) {
7132                                 dv->actions[n++] = priv->sh->esw_drop_action;
7133                         } else {
7134                                 dv->hrxq = mlx5_hrxq_drop_new(dev);
7135                                 if (!dv->hrxq) {
7136                                         rte_flow_error_set
7137                                                 (error, errno,
7138                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7139                                                  NULL,
7140                                                  "cannot get drop hash queue");
7141                                         goto error;
7142                                 }
7143                                 dv->actions[n++] = dv->hrxq->action;
7144                         }
7145                 } else if (dev_flow->actions &
7146                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7147                         struct mlx5_hrxq *hrxq;
7148
7149                         assert(flow->rss.queue);
7150                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7151                                              MLX5_RSS_HASH_KEY_LEN,
7152                                              dev_flow->hash_fields,
7153                                              (*flow->rss.queue),
7154                                              flow->rss.queue_num);
7155                         if (!hrxq) {
7156                                 hrxq = mlx5_hrxq_new
7157                                         (dev, flow->rss.key,
7158                                          MLX5_RSS_HASH_KEY_LEN,
7159                                          dev_flow->hash_fields,
7160                                          (*flow->rss.queue),
7161                                          flow->rss.queue_num,
7162                                          !!(dev_flow->layers &
7163                                             MLX5_FLOW_LAYER_TUNNEL));
7164                         }
7165                         if (!hrxq) {
7166                                 rte_flow_error_set
7167                                         (error, rte_errno,
7168                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7169                                          "cannot get hash queue");
7170                                 goto error;
7171                         }
7172                         dv->hrxq = hrxq;
7173                         dv->actions[n++] = dv->hrxq->action;
7174                 }
7175                 dv->flow =
7176                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7177                                                   (void *)&dv->value, n,
7178                                                   dv->actions);
7179                 if (!dv->flow) {
7180                         rte_flow_error_set(error, errno,
7181                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7182                                            NULL,
7183                                            "hardware refuses to create flow");
7184                         goto error;
7185                 }
7186                 if (priv->vmwa_context &&
7187                     dev_flow->dv.vf_vlan.tag &&
7188                     !dev_flow->dv.vf_vlan.created) {
7189                         /*
7190                          * The rule contains the VLAN pattern.
7191                          * For VF we are going to create VLAN
7192                          * interface to make hypervisor set correct
7193                          * e-Switch vport context.
7194                          */
7195                         mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7196                 }
7197         }
7198         return 0;
7199 error:
7200         err = rte_errno; /* Save rte_errno before cleanup. */
7201         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7202                 struct mlx5_flow_dv *dv = &dev_flow->dv;
7203                 if (dv->hrxq) {
7204                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7205                                 mlx5_hrxq_drop_release(dev);
7206                         else
7207                                 mlx5_hrxq_release(dev, dv->hrxq);
7208                         dv->hrxq = NULL;
7209                 }
7210                 if (dev_flow->dv.vf_vlan.tag &&
7211                     dev_flow->dv.vf_vlan.created)
7212                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7213         }
7214         rte_errno = err; /* Restore rte_errno. */
7215         return -rte_errno;
7216 }
7217
7218 /**
7219  * Release the flow matcher.
7220  *
7221  * @param dev
7222  *   Pointer to Ethernet device.
7223  * @param flow
7224  *   Pointer to mlx5_flow.
7225  *
7226  * @return
7227  *   1 while a reference on it exists, 0 when freed.
7228  */
7229 static int
7230 flow_dv_matcher_release(struct rte_eth_dev *dev,
7231                         struct mlx5_flow *flow)
7232 {
7233         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7234         struct mlx5_priv *priv = dev->data->dev_private;
7235         struct mlx5_ibv_shared *sh = priv->sh;
7236         struct mlx5_flow_tbl_resource *tbl;
7237
7238         assert(matcher->matcher_object);
7239         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7240                 dev->data->port_id, (void *)matcher,
7241                 rte_atomic32_read(&matcher->refcnt));
7242         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7243                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7244                            (matcher->matcher_object));
7245                 LIST_REMOVE(matcher, next);
7246                 if (matcher->egress)
7247                         tbl = &sh->tx_tbl[matcher->group];
7248                 else
7249                         tbl = &sh->rx_tbl[matcher->group];
7250                 flow_dv_tbl_resource_release(tbl);
7251                 rte_free(matcher);
7252                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7253                         dev->data->port_id, (void *)matcher);
7254                 return 0;
7255         }
7256         return 1;
7257 }
7258
7259 /**
7260  * Release an encap/decap resource.
7261  *
7262  * @param flow
7263  *   Pointer to mlx5_flow.
7264  *
7265  * @return
7266  *   1 while a reference on it exists, 0 when freed.
7267  */
7268 static int
7269 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7270 {
7271         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7272                                                 flow->dv.encap_decap;
7273
7274         assert(cache_resource->verbs_action);
7275         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7276                 (void *)cache_resource,
7277                 rte_atomic32_read(&cache_resource->refcnt));
7278         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7279                 claim_zero(mlx5_glue->destroy_flow_action
7280                                 (cache_resource->verbs_action));
7281                 LIST_REMOVE(cache_resource, next);
7282                 rte_free(cache_resource);
7283                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7284                         (void *)cache_resource);
7285                 return 0;
7286         }
7287         return 1;
7288 }
7289
7290 /**
7291  * Release an jump to table action resource.
7292  *
7293  * @param flow
7294  *   Pointer to mlx5_flow.
7295  *
7296  * @return
7297  *   1 while a reference on it exists, 0 when freed.
7298  */
7299 static int
7300 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
7301 {
7302         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
7303                                                 flow->dv.jump;
7304
7305         assert(cache_resource->action);
7306         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7307                 (void *)cache_resource,
7308                 rte_atomic32_read(&cache_resource->refcnt));
7309         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7310                 claim_zero(mlx5_glue->destroy_flow_action
7311                                 (cache_resource->action));
7312                 LIST_REMOVE(cache_resource, next);
7313                 flow_dv_tbl_resource_release(cache_resource->tbl);
7314                 rte_free(cache_resource);
7315                 DRV_LOG(DEBUG, "jump table resource %p: removed",
7316                         (void *)cache_resource);
7317                 return 0;
7318         }
7319         return 1;
7320 }
7321
7322 /**
7323  * Release a modify-header resource.
7324  *
7325  * @param flow
7326  *   Pointer to mlx5_flow.
7327  *
7328  * @return
7329  *   1 while a reference on it exists, 0 when freed.
7330  */
7331 static int
7332 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7333 {
7334         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7335                                                 flow->dv.modify_hdr;
7336
7337         assert(cache_resource->verbs_action);
7338         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7339                 (void *)cache_resource,
7340                 rte_atomic32_read(&cache_resource->refcnt));
7341         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7342                 claim_zero(mlx5_glue->destroy_flow_action
7343                                 (cache_resource->verbs_action));
7344                 LIST_REMOVE(cache_resource, next);
7345                 rte_free(cache_resource);
7346                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7347                         (void *)cache_resource);
7348                 return 0;
7349         }
7350         return 1;
7351 }
7352
7353 /**
7354  * Release port ID action resource.
7355  *
7356  * @param flow
7357  *   Pointer to mlx5_flow.
7358  *
7359  * @return
7360  *   1 while a reference on it exists, 0 when freed.
7361  */
7362 static int
7363 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7364 {
7365         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7366                 flow->dv.port_id_action;
7367
7368         assert(cache_resource->action);
7369         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7370                 (void *)cache_resource,
7371                 rte_atomic32_read(&cache_resource->refcnt));
7372         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7373                 claim_zero(mlx5_glue->destroy_flow_action
7374                                 (cache_resource->action));
7375                 LIST_REMOVE(cache_resource, next);
7376                 rte_free(cache_resource);
7377                 DRV_LOG(DEBUG, "port id action resource %p: removed",
7378                         (void *)cache_resource);
7379                 return 0;
7380         }
7381         return 1;
7382 }
7383
7384 /**
7385  * Release push vlan action resource.
7386  *
7387  * @param flow
7388  *   Pointer to mlx5_flow.
7389  *
7390  * @return
7391  *   1 while a reference on it exists, 0 when freed.
7392  */
7393 static int
7394 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7395 {
7396         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7397                 flow->dv.push_vlan_res;
7398
7399         assert(cache_resource->action);
7400         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7401                 (void *)cache_resource,
7402                 rte_atomic32_read(&cache_resource->refcnt));
7403         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7404                 claim_zero(mlx5_glue->destroy_flow_action
7405                                 (cache_resource->action));
7406                 LIST_REMOVE(cache_resource, next);
7407                 rte_free(cache_resource);
7408                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7409                         (void *)cache_resource);
7410                 return 0;
7411         }
7412         return 1;
7413 }
7414
7415 /**
7416  * Remove the flow from the NIC but keeps it in memory.
7417  * Lock free, (mutex should be acquired by caller).
7418  *
7419  * @param[in] dev
7420  *   Pointer to Ethernet device.
7421  * @param[in, out] flow
7422  *   Pointer to flow structure.
7423  */
7424 static void
7425 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7426 {
7427         struct mlx5_flow_dv *dv;
7428         struct mlx5_flow *dev_flow;
7429
7430         if (!flow)
7431                 return;
7432         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7433                 dv = &dev_flow->dv;
7434                 if (dv->flow) {
7435                         claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
7436                         dv->flow = NULL;
7437                 }
7438                 if (dv->hrxq) {
7439                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7440                                 mlx5_hrxq_drop_release(dev);
7441                         else
7442                                 mlx5_hrxq_release(dev, dv->hrxq);
7443                         dv->hrxq = NULL;
7444                 }
7445                 if (dev_flow->dv.vf_vlan.tag &&
7446                     dev_flow->dv.vf_vlan.created)
7447                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7448         }
7449 }
7450
7451 /**
7452  * Remove the flow from the NIC and the memory.
7453  * Lock free, (mutex should be acquired by caller).
7454  *
7455  * @param[in] dev
7456  *   Pointer to the Ethernet device structure.
7457  * @param[in, out] flow
7458  *   Pointer to flow structure.
7459  */
7460 static void
7461 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7462 {
7463         struct mlx5_flow *dev_flow;
7464
7465         if (!flow)
7466                 return;
7467         __flow_dv_remove(dev, flow);
7468         if (flow->counter) {
7469                 flow_dv_counter_release(dev, flow->counter);
7470                 flow->counter = NULL;
7471         }
7472         while (!LIST_EMPTY(&flow->dev_flows)) {
7473                 dev_flow = LIST_FIRST(&flow->dev_flows);
7474                 LIST_REMOVE(dev_flow, next);
7475                 if (dev_flow->dv.matcher)
7476                         flow_dv_matcher_release(dev, dev_flow);
7477                 if (dev_flow->dv.encap_decap)
7478                         flow_dv_encap_decap_resource_release(dev_flow);
7479                 if (dev_flow->dv.modify_hdr)
7480                         flow_dv_modify_hdr_resource_release(dev_flow);
7481                 if (dev_flow->dv.jump)
7482                         flow_dv_jump_tbl_resource_release(dev_flow);
7483                 if (dev_flow->dv.port_id_action)
7484                         flow_dv_port_id_action_resource_release(dev_flow);
7485                 if (dev_flow->dv.push_vlan_res)
7486                         flow_dv_push_vlan_action_resource_release(dev_flow);
7487                 if (dev_flow->dv.tag_resource)
7488                         flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
7489                 rte_free(dev_flow);
7490         }
7491 }
7492
7493 /**
7494  * Query a dv flow  rule for its statistics via devx.
7495  *
7496  * @param[in] dev
7497  *   Pointer to Ethernet device.
7498  * @param[in] flow
7499  *   Pointer to the sub flow.
7500  * @param[out] data
7501  *   data retrieved by the query.
7502  * @param[out] error
7503  *   Perform verbose error reporting if not NULL.
7504  *
7505  * @return
7506  *   0 on success, a negative errno value otherwise and rte_errno is set.
7507  */
7508 static int
7509 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
7510                     void *data, struct rte_flow_error *error)
7511 {
7512         struct mlx5_priv *priv = dev->data->dev_private;
7513         struct rte_flow_query_count *qc = data;
7514
7515         if (!priv->config.devx)
7516                 return rte_flow_error_set(error, ENOTSUP,
7517                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7518                                           NULL,
7519                                           "counters are not supported");
7520         if (flow->counter) {
7521                 uint64_t pkts, bytes;
7522                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
7523                                                &bytes);
7524
7525                 if (err)
7526                         return rte_flow_error_set(error, -err,
7527                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7528                                         NULL, "cannot read counters");
7529                 qc->hits_set = 1;
7530                 qc->bytes_set = 1;
7531                 qc->hits = pkts - flow->counter->hits;
7532                 qc->bytes = bytes - flow->counter->bytes;
7533                 if (qc->reset) {
7534                         flow->counter->hits = pkts;
7535                         flow->counter->bytes = bytes;
7536                 }
7537                 return 0;
7538         }
7539         return rte_flow_error_set(error, EINVAL,
7540                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7541                                   NULL,
7542                                   "counters are not available");
7543 }
7544
7545 /**
7546  * Query a flow.
7547  *
7548  * @see rte_flow_query()
7549  * @see rte_flow_ops
7550  */
7551 static int
7552 flow_dv_query(struct rte_eth_dev *dev,
7553               struct rte_flow *flow __rte_unused,
7554               const struct rte_flow_action *actions __rte_unused,
7555               void *data __rte_unused,
7556               struct rte_flow_error *error __rte_unused)
7557 {
7558         int ret = -EINVAL;
7559
7560         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7561                 switch (actions->type) {
7562                 case RTE_FLOW_ACTION_TYPE_VOID:
7563                         break;
7564                 case RTE_FLOW_ACTION_TYPE_COUNT:
7565                         ret = flow_dv_query_count(dev, flow, data, error);
7566                         break;
7567                 default:
7568                         return rte_flow_error_set(error, ENOTSUP,
7569                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7570                                                   actions,
7571                                                   "action not supported");
7572                 }
7573         }
7574         return ret;
7575 }
7576
7577 /*
7578  * Mutex-protected thunk to lock-free  __flow_dv_translate().
7579  */
7580 static int
7581 flow_dv_translate(struct rte_eth_dev *dev,
7582                   struct mlx5_flow *dev_flow,
7583                   const struct rte_flow_attr *attr,
7584                   const struct rte_flow_item items[],
7585                   const struct rte_flow_action actions[],
7586                   struct rte_flow_error *error)
7587 {
7588         int ret;
7589
7590         flow_dv_shared_lock(dev);
7591         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
7592         flow_dv_shared_unlock(dev);
7593         return ret;
7594 }
7595
7596 /*
7597  * Mutex-protected thunk to lock-free  __flow_dv_apply().
7598  */
7599 static int
7600 flow_dv_apply(struct rte_eth_dev *dev,
7601               struct rte_flow *flow,
7602               struct rte_flow_error *error)
7603 {
7604         int ret;
7605
7606         flow_dv_shared_lock(dev);
7607         ret = __flow_dv_apply(dev, flow, error);
7608         flow_dv_shared_unlock(dev);
7609         return ret;
7610 }
7611
7612 /*
7613  * Mutex-protected thunk to lock-free __flow_dv_remove().
7614  */
7615 static void
7616 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7617 {
7618         flow_dv_shared_lock(dev);
7619         __flow_dv_remove(dev, flow);
7620         flow_dv_shared_unlock(dev);
7621 }
7622
7623 /*
7624  * Mutex-protected thunk to lock-free __flow_dv_destroy().
7625  */
7626 static void
7627 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
7628 {
7629         flow_dv_shared_lock(dev);
7630         __flow_dv_destroy(dev, flow);
7631         flow_dv_shared_unlock(dev);
7632 }
7633
7634 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
7635         .validate = flow_dv_validate,
7636         .prepare = flow_dv_prepare,
7637         .translate = flow_dv_translate,
7638         .apply = flow_dv_apply,
7639         .remove = flow_dv_remove,
7640         .destroy = flow_dv_destroy,
7641         .query = flow_dv_query,
7642 };
7643
7644 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */