drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
  58                                           sizeof(struct rte_flow_item_ipv4))
  59 /* VLAN header definitions */
  60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  65
  66 union flow_dv_attr {
  67         struct {
  68                 uint32_t valid:1;
  69                 uint32_t ipv4:1;
  70                 uint32_t ipv6:1;
  71                 uint32_t tcp:1;
  72                 uint32_t udp:1;
  73                 uint32_t reserved:27;
  74         };
  75         uint32_t attr;
  76 };
  77
  78 /**
  79  * Initialize flow attributes structure according to flow items' types.
  80  *
  81  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  82  * mode. For tunnel mode, the items to be modified are the outermost ones.
  83  *
  84  * @param[in] item
  85  *   Pointer to item specification.
  86  * @param[out] attr
  87  *   Pointer to flow attributes structure.
  88  */
  89 static void
  90 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
  91 {
  92         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
  93                 switch (item->type) {
  94                 case RTE_FLOW_ITEM_TYPE_IPV4:
  95                         if (!attr->ipv6)
  96                                 attr->ipv4 = 1;
  97                         break;
  98                 case RTE_FLOW_ITEM_TYPE_IPV6:
  99                         if (!attr->ipv4)
 100                                 attr->ipv6 = 1;
 101                         break;
 102                 case RTE_FLOW_ITEM_TYPE_UDP:
 103                         if (!attr->tcp)
 104                                 attr->udp = 1;
 105                         break;
 106                 case RTE_FLOW_ITEM_TYPE_TCP:
 107                         if (!attr->udp)
 108                                 attr->tcp = 1;
 109                         break;
 110                 default:
 111                         break;
 112                 }
 113         }
 114         attr->valid = 1;
 115 }
 116
 117 /**
 118  * Convert rte_mtr_color to mlx5 color.
 119  *
 120  * @param[in] rcol
 121  *   rte_mtr_color.
 122  *
 123  * @return
 124  *   mlx5 color.
 125  */
 126 static int
 127 rte_col_2_mlx5_col(enum rte_color rcol)
 128 {
 129         switch (rcol) {
 130         case RTE_COLOR_GREEN:
 131                 return MLX5_FLOW_COLOR_GREEN;
 132         case RTE_COLOR_YELLOW:
 133                 return MLX5_FLOW_COLOR_YELLOW;
 134         case RTE_COLOR_RED:
 135                 return MLX5_FLOW_COLOR_RED;
 136         default:
 137                 break;
 138         }
 139         return MLX5_FLOW_COLOR_UNDEFINED;
 140 }
 141
 142 struct field_modify_info {
 143         uint32_t size; /* Size of field in protocol header, in bytes. */
 144         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 145         enum mlx5_modification_field id;
 146 };
 147
 148 struct field_modify_info modify_eth[] = {
 149         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 150         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 151         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 152         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 153         {0, 0, 0},
 154 };
 155
 156 struct field_modify_info modify_vlan_out_first_vid[] = {
 157         /* Size in bits !!! */
 158         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 159         {0, 0, 0},
 160 };
 161
 162 struct field_modify_info modify_ipv4[] = {
 163         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 164         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 165         {4, 12, MLX5_MODI_OUT_SIPV4},
 166         {4, 16, MLX5_MODI_OUT_DIPV4},
 167         {0, 0, 0},
 168 };
 169
 170 struct field_modify_info modify_ipv6[] = {
 171         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 172         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 173         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 174         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 175         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 176         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 177         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 178         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 179         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 180         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 181         {0, 0, 0},
 182 };
 183
 184 struct field_modify_info modify_udp[] = {
 185         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 186         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 187         {0, 0, 0},
 188 };
 189
 190 struct field_modify_info modify_tcp[] = {
 191         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 192         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 193         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 194         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 195         {0, 0, 0},
 196 };
 197
 198 static void
 199 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 200                           uint8_t next_protocol, uint64_t *item_flags,
 201                           int *tunnel)
 202 {
 203         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 204                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 205         if (next_protocol == IPPROTO_IPIP) {
 206                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 207                 *tunnel = 1;
 208         }
 209         if (next_protocol == IPPROTO_IPV6) {
 210                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 211                 *tunnel = 1;
 212         }
 213 }
 214
 215 /**
 216  * Acquire the synchronizing object to protect multithreaded access
 217  * to shared dv context. Lock occurs only if context is actually
 218  * shared, i.e. we have multiport IB device and representors are
 219  * created.
 220  *
 221  * @param[in] dev
 222  *   Pointer to the rte_eth_dev structure.
 223  */
 224 static void
 225 flow_dv_shared_lock(struct rte_eth_dev *dev)
 226 {
 227         struct mlx5_priv *priv = dev->data->dev_private;
 228         struct mlx5_ibv_shared *sh = priv->sh;
 229
 230         if (sh->dv_refcnt > 1) {
 231                 int ret;
 232
 233                 ret = pthread_mutex_lock(&sh->dv_mutex);
 234                 MLX5_ASSERT(!ret);
 235                 (void)ret;
 236         }
 237 }
 238
 239 static void
 240 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 241 {
 242         struct mlx5_priv *priv = dev->data->dev_private;
 243         struct mlx5_ibv_shared *sh = priv->sh;
 244
 245         if (sh->dv_refcnt > 1) {
 246                 int ret;
 247
 248                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 249                 MLX5_ASSERT(!ret);
 250                 (void)ret;
 251         }
 252 }
 253
 254 /* Update VLAN's VID/PCP based on input rte_flow_action.
 255  *
 256  * @param[in] action
 257  *   Pointer to struct rte_flow_action.
 258  * @param[out] vlan
 259  *   Pointer to struct rte_vlan_hdr.
 260  */
 261 static void
 262 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 263                          struct rte_vlan_hdr *vlan)
 264 {
 265         uint16_t vlan_tci;
 266         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 267                 vlan_tci =
 268                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 269                                                action->conf)->vlan_pcp;
 270                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 271                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 272                 vlan->vlan_tci |= vlan_tci;
 273         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 274                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 275                 vlan->vlan_tci |= rte_be_to_cpu_16
 276                     (((const struct rte_flow_action_of_set_vlan_vid *)
 277                                              action->conf)->vlan_vid);
 278         }
 279 }
 280
 281 /**
 282  * Fetch 1, 2, 3 or 4 byte field from the byte array
 283  * and return as unsigned integer in host-endian format.
 284  *
 285  * @param[in] data
 286  *   Pointer to data array.
 287  * @param[in] size
 288  *   Size of field to extract.
 289  *
 290  * @return
 291  *   converted field in host endian format.
 292  */
 293 static inline uint32_t
 294 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 295 {
 296         uint32_t ret;
 297
 298         switch (size) {
 299         case 1:
 300                 ret = *data;
 301                 break;
 302         case 2:
 303                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 304                 break;
 305         case 3:
 306                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 307                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 308                 break;
 309         case 4:
 310                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 311                 break;
 312         default:
 313                 MLX5_ASSERT(false);
 314                 ret = 0;
 315                 break;
 316         }
 317         return ret;
 318 }
 319
 320 /**
 321  * Convert modify-header action to DV specification.
 322  *
 323  * Data length of each action is determined by provided field description
 324  * and the item mask. Data bit offset and width of each action is determined
 325  * by provided item mask.
 326  *
 327  * @param[in] item
 328  *   Pointer to item specification.
 329  * @param[in] field
 330  *   Pointer to field modification information.
 331  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 332  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 333  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 334  * @param[in] dcopy
 335  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 336  *   Negative offset value sets the same offset as source offset.
 337  *   size field is ignored, value is taken from source field.
 338  * @param[in,out] resource
 339  *   Pointer to the modify-header resource.
 340  * @param[in] type
 341  *   Type of modification.
 342  * @param[out] error
 343  *   Pointer to the error structure.
 344  *
 345  * @return
 346  *   0 on success, a negative errno value otherwise and rte_errno is set.
 347  */
 348 static int
 349 flow_dv_convert_modify_action(struct rte_flow_item *item,
 350                               struct field_modify_info *field,
 351                               struct field_modify_info *dcopy,
 352                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 353                               uint32_t type, struct rte_flow_error *error)
 354 {
 355         uint32_t i = resource->actions_num;
 356         struct mlx5_modification_cmd *actions = resource->actions;
 357
 358         /*
 359          * The item and mask are provided in big-endian format.
 360          * The fields should be presented as in big-endian format either.
 361          * Mask must be always present, it defines the actual field width.
 362          */
 363         MLX5_ASSERT(item->mask);
 364         MLX5_ASSERT(field->size);
 365         do {
 366                 unsigned int size_b;
 367                 unsigned int off_b;
 368                 uint32_t mask;
 369                 uint32_t data;
 370
 371                 if (i >= MLX5_MAX_MODIFY_NUM)
 372                         return rte_flow_error_set(error, EINVAL,
 373                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 374                                  "too many items to modify");
 375                 /* Fetch variable byte size mask from the array. */
 376                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 377                                            field->offset, field->size);
 378                 if (!mask) {
 379                         ++field;
 380                         continue;
 381                 }
 382                 /* Deduce actual data width in bits from mask value. */
 383                 off_b = rte_bsf32(mask);
 384                 size_b = sizeof(uint32_t) * CHAR_BIT -
 385                          off_b - __builtin_clz(mask);
 386                 MLX5_ASSERT(size_b);
 387                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 388                 actions[i] = (struct mlx5_modification_cmd) {
 389                         .action_type = type,
 390                         .field = field->id,
 391                         .offset = off_b,
 392                         .length = size_b,
 393                 };
 394                 /* Convert entire record to expected big-endian format. */
 395                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 396                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 397                         MLX5_ASSERT(dcopy);
 398                         actions[i].dst_field = dcopy->id;
 399                         actions[i].dst_offset =
 400                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 401                         /* Convert entire record to big-endian format. */
 402                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 403                 } else {
 404                         MLX5_ASSERT(item->spec);
 405                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 406                                                    field->offset, field->size);
 407                         /* Shift out the trailing masked bits from data. */
 408                         data = (data & mask) >> off_b;
 409                         actions[i].data1 = rte_cpu_to_be_32(data);
 410                 }
 411                 ++i;
 412                 ++field;
 413         } while (field->size);
 414         if (resource->actions_num == i)
 415                 return rte_flow_error_set(error, EINVAL,
 416                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 417                                           "invalid modification flow item");
 418         resource->actions_num = i;
 419         return 0;
 420 }
 421
 422 /**
 423  * Convert modify-header set IPv4 address action to DV specification.
 424  *
 425  * @param[in,out] resource
 426  *   Pointer to the modify-header resource.
 427  * @param[in] action
 428  *   Pointer to action specification.
 429  * @param[out] error
 430  *   Pointer to the error structure.
 431  *
 432  * @return
 433  *   0 on success, a negative errno value otherwise and rte_errno is set.
 434  */
 435 static int
 436 flow_dv_convert_action_modify_ipv4
 437                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 438                          const struct rte_flow_action *action,
 439                          struct rte_flow_error *error)
 440 {
 441         const struct rte_flow_action_set_ipv4 *conf =
 442                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 443         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 444         struct rte_flow_item_ipv4 ipv4;
 445         struct rte_flow_item_ipv4 ipv4_mask;
 446
 447         memset(&ipv4, 0, sizeof(ipv4));
 448         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 449         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 450                 ipv4.hdr.src_addr = conf->ipv4_addr;
 451                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 452         } else {
 453                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 454                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 455         }
 456         item.spec = &ipv4;
 457         item.mask = &ipv4_mask;
 458         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 459                                              MLX5_MODIFICATION_TYPE_SET, error);
 460 }
 461
 462 /**
 463  * Convert modify-header set IPv6 address action to DV specification.
 464  *
 465  * @param[in,out] resource
 466  *   Pointer to the modify-header resource.
 467  * @param[in] action
 468  *   Pointer to action specification.
 469  * @param[out] error
 470  *   Pointer to the error structure.
 471  *
 472  * @return
 473  *   0 on success, a negative errno value otherwise and rte_errno is set.
 474  */
 475 static int
 476 flow_dv_convert_action_modify_ipv6
 477                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 478                          const struct rte_flow_action *action,
 479                          struct rte_flow_error *error)
 480 {
 481         const struct rte_flow_action_set_ipv6 *conf =
 482                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 483         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 484         struct rte_flow_item_ipv6 ipv6;
 485         struct rte_flow_item_ipv6 ipv6_mask;
 486
 487         memset(&ipv6, 0, sizeof(ipv6));
 488         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 489         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 490                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 491                        sizeof(ipv6.hdr.src_addr));
 492                 memcpy(&ipv6_mask.hdr.src_addr,
 493                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 494                        sizeof(ipv6.hdr.src_addr));
 495         } else {
 496                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 497                        sizeof(ipv6.hdr.dst_addr));
 498                 memcpy(&ipv6_mask.hdr.dst_addr,
 499                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 500                        sizeof(ipv6.hdr.dst_addr));
 501         }
 502         item.spec = &ipv6;
 503         item.mask = &ipv6_mask;
 504         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 505                                              MLX5_MODIFICATION_TYPE_SET, error);
 506 }
 507
 508 /**
 509  * Convert modify-header set MAC address action to DV specification.
 510  *
 511  * @param[in,out] resource
 512  *   Pointer to the modify-header resource.
 513  * @param[in] action
 514  *   Pointer to action specification.
 515  * @param[out] error
 516  *   Pointer to the error structure.
 517  *
 518  * @return
 519  *   0 on success, a negative errno value otherwise and rte_errno is set.
 520  */
 521 static int
 522 flow_dv_convert_action_modify_mac
 523                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 524                          const struct rte_flow_action *action,
 525                          struct rte_flow_error *error)
 526 {
 527         const struct rte_flow_action_set_mac *conf =
 528                 (const struct rte_flow_action_set_mac *)(action->conf);
 529         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 530         struct rte_flow_item_eth eth;
 531         struct rte_flow_item_eth eth_mask;
 532
 533         memset(&eth, 0, sizeof(eth));
 534         memset(&eth_mask, 0, sizeof(eth_mask));
 535         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 536                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 537                        sizeof(eth.src.addr_bytes));
 538                 memcpy(&eth_mask.src.addr_bytes,
 539                        &rte_flow_item_eth_mask.src.addr_bytes,
 540                        sizeof(eth_mask.src.addr_bytes));
 541         } else {
 542                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 543                        sizeof(eth.dst.addr_bytes));
 544                 memcpy(&eth_mask.dst.addr_bytes,
 545                        &rte_flow_item_eth_mask.dst.addr_bytes,
 546                        sizeof(eth_mask.dst.addr_bytes));
 547         }
 548         item.spec = &eth;
 549         item.mask = &eth_mask;
 550         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 551                                              MLX5_MODIFICATION_TYPE_SET, error);
 552 }
 553
 554 /**
 555  * Convert modify-header set VLAN VID action to DV specification.
 556  *
 557  * @param[in,out] resource
 558  *   Pointer to the modify-header resource.
 559  * @param[in] action
 560  *   Pointer to action specification.
 561  * @param[out] error
 562  *   Pointer to the error structure.
 563  *
 564  * @return
 565  *   0 on success, a negative errno value otherwise and rte_errno is set.
 566  */
 567 static int
 568 flow_dv_convert_action_modify_vlan_vid
 569                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 570                          const struct rte_flow_action *action,
 571                          struct rte_flow_error *error)
 572 {
 573         const struct rte_flow_action_of_set_vlan_vid *conf =
 574                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 575         int i = resource->actions_num;
 576         struct mlx5_modification_cmd *actions = &resource->actions[i];
 577         struct field_modify_info *field = modify_vlan_out_first_vid;
 578
 579         if (i >= MLX5_MAX_MODIFY_NUM)
 580                 return rte_flow_error_set(error, EINVAL,
 581                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 582                          "too many items to modify");
 583         actions[i] = (struct mlx5_modification_cmd) {
 584                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 585                 .field = field->id,
 586                 .length = field->size,
 587                 .offset = field->offset,
 588         };
 589         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 590         actions[i].data1 = conf->vlan_vid;
 591         actions[i].data1 = actions[i].data1 << 16;
 592         resource->actions_num = ++i;
 593         return 0;
 594 }
 595
 596 /**
 597  * Convert modify-header set TP action to DV specification.
 598  *
 599  * @param[in,out] resource
 600  *   Pointer to the modify-header resource.
 601  * @param[in] action
 602  *   Pointer to action specification.
 603  * @param[in] items
 604  *   Pointer to rte_flow_item objects list.
 605  * @param[in] attr
 606  *   Pointer to flow attributes structure.
 607  * @param[out] error
 608  *   Pointer to the error structure.
 609  *
 610  * @return
 611  *   0 on success, a negative errno value otherwise and rte_errno is set.
 612  */
 613 static int
 614 flow_dv_convert_action_modify_tp
 615                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 616                          const struct rte_flow_action *action,
 617                          const struct rte_flow_item *items,
 618                          union flow_dv_attr *attr,
 619                          struct rte_flow_error *error)
 620 {
 621         const struct rte_flow_action_set_tp *conf =
 622                 (const struct rte_flow_action_set_tp *)(action->conf);
 623         struct rte_flow_item item;
 624         struct rte_flow_item_udp udp;
 625         struct rte_flow_item_udp udp_mask;
 626         struct rte_flow_item_tcp tcp;
 627         struct rte_flow_item_tcp tcp_mask;
 628         struct field_modify_info *field;
 629
 630         if (!attr->valid)
 631                 flow_dv_attr_init(items, attr);
 632         if (attr->udp) {
 633                 memset(&udp, 0, sizeof(udp));
 634                 memset(&udp_mask, 0, sizeof(udp_mask));
 635                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 636                         udp.hdr.src_port = conf->port;
 637                         udp_mask.hdr.src_port =
 638                                         rte_flow_item_udp_mask.hdr.src_port;
 639                 } else {
 640                         udp.hdr.dst_port = conf->port;
 641                         udp_mask.hdr.dst_port =
 642                                         rte_flow_item_udp_mask.hdr.dst_port;
 643                 }
 644                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 645                 item.spec = &udp;
 646                 item.mask = &udp_mask;
 647                 field = modify_udp;
 648         }
 649         if (attr->tcp) {
 650                 memset(&tcp, 0, sizeof(tcp));
 651                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 652                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 653                         tcp.hdr.src_port = conf->port;
 654                         tcp_mask.hdr.src_port =
 655                                         rte_flow_item_tcp_mask.hdr.src_port;
 656                 } else {
 657                         tcp.hdr.dst_port = conf->port;
 658                         tcp_mask.hdr.dst_port =
 659                                         rte_flow_item_tcp_mask.hdr.dst_port;
 660                 }
 661                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 662                 item.spec = &tcp;
 663                 item.mask = &tcp_mask;
 664                 field = modify_tcp;
 665         }
 666         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 667                                              MLX5_MODIFICATION_TYPE_SET, error);
 668 }
 669
 670 /**
 671  * Convert modify-header set TTL action to DV specification.
 672  *
 673  * @param[in,out] resource
 674  *   Pointer to the modify-header resource.
 675  * @param[in] action
 676  *   Pointer to action specification.
 677  * @param[in] items
 678  *   Pointer to rte_flow_item objects list.
 679  * @param[in] attr
 680  *   Pointer to flow attributes structure.
 681  * @param[out] error
 682  *   Pointer to the error structure.
 683  *
 684  * @return
 685  *   0 on success, a negative errno value otherwise and rte_errno is set.
 686  */
 687 static int
 688 flow_dv_convert_action_modify_ttl
 689                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 690                          const struct rte_flow_action *action,
 691                          const struct rte_flow_item *items,
 692                          union flow_dv_attr *attr,
 693                          struct rte_flow_error *error)
 694 {
 695         const struct rte_flow_action_set_ttl *conf =
 696                 (const struct rte_flow_action_set_ttl *)(action->conf);
 697         struct rte_flow_item item;
 698         struct rte_flow_item_ipv4 ipv4;
 699         struct rte_flow_item_ipv4 ipv4_mask;
 700         struct rte_flow_item_ipv6 ipv6;
 701         struct rte_flow_item_ipv6 ipv6_mask;
 702         struct field_modify_info *field;
 703
 704         if (!attr->valid)
 705                 flow_dv_attr_init(items, attr);
 706         if (attr->ipv4) {
 707                 memset(&ipv4, 0, sizeof(ipv4));
 708                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 709                 ipv4.hdr.time_to_live = conf->ttl_value;
 710                 ipv4_mask.hdr.time_to_live = 0xFF;
 711                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 712                 item.spec = &ipv4;
 713                 item.mask = &ipv4_mask;
 714                 field = modify_ipv4;
 715         }
 716         if (attr->ipv6) {
 717                 memset(&ipv6, 0, sizeof(ipv6));
 718                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 719                 ipv6.hdr.hop_limits = conf->ttl_value;
 720                 ipv6_mask.hdr.hop_limits = 0xFF;
 721                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 722                 item.spec = &ipv6;
 723                 item.mask = &ipv6_mask;
 724                 field = modify_ipv6;
 725         }
 726         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 727                                              MLX5_MODIFICATION_TYPE_SET, error);
 728 }
 729
 730 /**
 731  * Convert modify-header decrement TTL action to DV specification.
 732  *
 733  * @param[in,out] resource
 734  *   Pointer to the modify-header resource.
 735  * @param[in] action
 736  *   Pointer to action specification.
 737  * @param[in] items
 738  *   Pointer to rte_flow_item objects list.
 739  * @param[in] attr
 740  *   Pointer to flow attributes structure.
 741  * @param[out] error
 742  *   Pointer to the error structure.
 743  *
 744  * @return
 745  *   0 on success, a negative errno value otherwise and rte_errno is set.
 746  */
 747 static int
 748 flow_dv_convert_action_modify_dec_ttl
 749                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 750                          const struct rte_flow_item *items,
 751                          union flow_dv_attr *attr,
 752                          struct rte_flow_error *error)
 753 {
 754         struct rte_flow_item item;
 755         struct rte_flow_item_ipv4 ipv4;
 756         struct rte_flow_item_ipv4 ipv4_mask;
 757         struct rte_flow_item_ipv6 ipv6;
 758         struct rte_flow_item_ipv6 ipv6_mask;
 759         struct field_modify_info *field;
 760
 761         if (!attr->valid)
 762                 flow_dv_attr_init(items, attr);
 763         if (attr->ipv4) {
 764                 memset(&ipv4, 0, sizeof(ipv4));
 765                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 766                 ipv4.hdr.time_to_live = 0xFF;
 767                 ipv4_mask.hdr.time_to_live = 0xFF;
 768                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 769                 item.spec = &ipv4;
 770                 item.mask = &ipv4_mask;
 771                 field = modify_ipv4;
 772         }
 773         if (attr->ipv6) {
 774                 memset(&ipv6, 0, sizeof(ipv6));
 775                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 776                 ipv6.hdr.hop_limits = 0xFF;
 777                 ipv6_mask.hdr.hop_limits = 0xFF;
 778                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 779                 item.spec = &ipv6;
 780                 item.mask = &ipv6_mask;
 781                 field = modify_ipv6;
 782         }
 783         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 784                                              MLX5_MODIFICATION_TYPE_ADD, error);
 785 }
 786
 787 /**
 788  * Convert modify-header increment/decrement TCP Sequence number
 789  * to DV specification.
 790  *
 791  * @param[in,out] resource
 792  *   Pointer to the modify-header resource.
 793  * @param[in] action
 794  *   Pointer to action specification.
 795  * @param[out] error
 796  *   Pointer to the error structure.
 797  *
 798  * @return
 799  *   0 on success, a negative errno value otherwise and rte_errno is set.
 800  */
 801 static int
 802 flow_dv_convert_action_modify_tcp_seq
 803                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 804                          const struct rte_flow_action *action,
 805                          struct rte_flow_error *error)
 806 {
 807         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 808         uint64_t value = rte_be_to_cpu_32(*conf);
 809         struct rte_flow_item item;
 810         struct rte_flow_item_tcp tcp;
 811         struct rte_flow_item_tcp tcp_mask;
 812
 813         memset(&tcp, 0, sizeof(tcp));
 814         memset(&tcp_mask, 0, sizeof(tcp_mask));
 815         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 816                 /*
 817                  * The HW has no decrement operation, only increment operation.
 818                  * To simulate decrement X from Y using increment operation
 819                  * we need to add UINT32_MAX X times to Y.
 820                  * Each adding of UINT32_MAX decrements Y by 1.
 821                  */
 822                 value *= UINT32_MAX;
 823         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 824         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 825         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 826         item.spec = &tcp;
 827         item.mask = &tcp_mask;
 828         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 829                                              MLX5_MODIFICATION_TYPE_ADD, error);
 830 }
 831
 832 /**
 833  * Convert modify-header increment/decrement TCP Acknowledgment number
 834  * to DV specification.
 835  *
 836  * @param[in,out] resource
 837  *   Pointer to the modify-header resource.
 838  * @param[in] action
 839  *   Pointer to action specification.
 840  * @param[out] error
 841  *   Pointer to the error structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 static int
 847 flow_dv_convert_action_modify_tcp_ack
 848                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 849                          const struct rte_flow_action *action,
 850                          struct rte_flow_error *error)
 851 {
 852         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 853         uint64_t value = rte_be_to_cpu_32(*conf);
 854         struct rte_flow_item item;
 855         struct rte_flow_item_tcp tcp;
 856         struct rte_flow_item_tcp tcp_mask;
 857
 858         memset(&tcp, 0, sizeof(tcp));
 859         memset(&tcp_mask, 0, sizeof(tcp_mask));
 860         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 861                 /*
 862                  * The HW has no decrement operation, only increment operation.
 863                  * To simulate decrement X from Y using increment operation
 864                  * we need to add UINT32_MAX X times to Y.
 865                  * Each adding of UINT32_MAX decrements Y by 1.
 866                  */
 867                 value *= UINT32_MAX;
 868         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 869         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 870         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 871         item.spec = &tcp;
 872         item.mask = &tcp_mask;
 873         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 874                                              MLX5_MODIFICATION_TYPE_ADD, error);
 875 }
 876
 877 static enum mlx5_modification_field reg_to_field[] = {
 878         [REG_NONE] = MLX5_MODI_OUT_NONE,
 879         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 880         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 881         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 882         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 883         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 884         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 885         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 886         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 887         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 888         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 889 };
 890
 891 /**
 892  * Convert register set to DV specification.
 893  *
 894  * @param[in,out] resource
 895  *   Pointer to the modify-header resource.
 896  * @param[in] action
 897  *   Pointer to action specification.
 898  * @param[out] error
 899  *   Pointer to the error structure.
 900  *
 901  * @return
 902  *   0 on success, a negative errno value otherwise and rte_errno is set.
 903  */
 904 static int
 905 flow_dv_convert_action_set_reg
 906                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 907                          const struct rte_flow_action *action,
 908                          struct rte_flow_error *error)
 909 {
 910         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 911         struct mlx5_modification_cmd *actions = resource->actions;
 912         uint32_t i = resource->actions_num;
 913
 914         if (i >= MLX5_MAX_MODIFY_NUM)
 915                 return rte_flow_error_set(error, EINVAL,
 916                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 917                                           "too many items to modify");
 918         MLX5_ASSERT(conf->id != REG_NONE);
 919         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 920         actions[i] = (struct mlx5_modification_cmd) {
 921                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 922                 .field = reg_to_field[conf->id],
 923         };
 924         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 925         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 926         ++i;
 927         resource->actions_num = i;
 928         return 0;
 929 }
 930
 931 /**
 932  * Convert SET_TAG action to DV specification.
 933  *
 934  * @param[in] dev
 935  *   Pointer to the rte_eth_dev structure.
 936  * @param[in,out] resource
 937  *   Pointer to the modify-header resource.
 938  * @param[in] conf
 939  *   Pointer to action specification.
 940  * @param[out] error
 941  *   Pointer to the error structure.
 942  *
 943  * @return
 944  *   0 on success, a negative errno value otherwise and rte_errno is set.
 945  */
 946 static int
 947 flow_dv_convert_action_set_tag
 948                         (struct rte_eth_dev *dev,
 949                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 950                          const struct rte_flow_action_set_tag *conf,
 951                          struct rte_flow_error *error)
 952 {
 953         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 954         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 955         struct rte_flow_item item = {
 956                 .spec = &data,
 957                 .mask = &mask,
 958         };
 959         struct field_modify_info reg_c_x[] = {
 960                 [1] = {0, 0, 0},
 961         };
 962         enum mlx5_modification_field reg_type;
 963         int ret;
 964
 965         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
 966         if (ret < 0)
 967                 return ret;
 968         MLX5_ASSERT(ret != REG_NONE);
 969         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
 970         reg_type = reg_to_field[ret];
 971         MLX5_ASSERT(reg_type > 0);
 972         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
 973         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
 974                                              MLX5_MODIFICATION_TYPE_SET, error);
 975 }
 976
 977 /**
 978  * Convert internal COPY_REG action to DV specification.
 979  *
 980  * @param[in] dev
 981  *   Pointer to the rte_eth_dev structure.
 982  * @param[in,out] res
 983  *   Pointer to the modify-header resource.
 984  * @param[in] action
 985  *   Pointer to action specification.
 986  * @param[out] error
 987  *   Pointer to the error structure.
 988  *
 989  * @return
 990  *   0 on success, a negative errno value otherwise and rte_errno is set.
 991  */
 992 static int
 993 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
 994                                  struct mlx5_flow_dv_modify_hdr_resource *res,
 995                                  const struct rte_flow_action *action,
 996                                  struct rte_flow_error *error)
 997 {
 998         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
 999         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1000         struct rte_flow_item item = {
1001                 .spec = NULL,
1002                 .mask = &mask,
1003         };
1004         struct field_modify_info reg_src[] = {
1005                 {4, 0, reg_to_field[conf->src]},
1006                 {0, 0, 0},
1007         };
1008         struct field_modify_info reg_dst = {
1009                 .offset = 0,
1010                 .id = reg_to_field[conf->dst],
1011         };
1012         /* Adjust reg_c[0] usage according to reported mask. */
1013         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1014                 struct mlx5_priv *priv = dev->data->dev_private;
1015                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1016
1017                 MLX5_ASSERT(reg_c0);
1018                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1019                 if (conf->dst == REG_C_0) {
1020                         /* Copy to reg_c[0], within mask only. */
1021                         reg_dst.offset = rte_bsf32(reg_c0);
1022                         /*
1023                          * Mask is ignoring the enianness, because
1024                          * there is no conversion in datapath.
1025                          */
1026 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1027                         /* Copy from destination lower bits to reg_c[0]. */
1028                         mask = reg_c0 >> reg_dst.offset;
1029 #else
1030                         /* Copy from destination upper bits to reg_c[0]. */
1031                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1032                                           rte_fls_u32(reg_c0));
1033 #endif
1034                 } else {
1035                         mask = rte_cpu_to_be_32(reg_c0);
1036 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1037                         /* Copy from reg_c[0] to destination lower bits. */
1038                         reg_dst.offset = 0;
1039 #else
1040                         /* Copy from reg_c[0] to destination upper bits. */
1041                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1042                                          (rte_fls_u32(reg_c0) -
1043                                           rte_bsf32(reg_c0));
1044 #endif
1045                 }
1046         }
1047         return flow_dv_convert_modify_action(&item,
1048                                              reg_src, &reg_dst, res,
1049                                              MLX5_MODIFICATION_TYPE_COPY,
1050                                              error);
1051 }
1052
1053 /**
1054  * Convert MARK action to DV specification. This routine is used
1055  * in extensive metadata only and requires metadata register to be
1056  * handled. In legacy mode hardware tag resource is engaged.
1057  *
1058  * @param[in] dev
1059  *   Pointer to the rte_eth_dev structure.
1060  * @param[in] conf
1061  *   Pointer to MARK action specification.
1062  * @param[in,out] resource
1063  *   Pointer to the modify-header resource.
1064  * @param[out] error
1065  *   Pointer to the error structure.
1066  *
1067  * @return
1068  *   0 on success, a negative errno value otherwise and rte_errno is set.
1069  */
1070 static int
1071 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1072                             const struct rte_flow_action_mark *conf,
1073                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1074                             struct rte_flow_error *error)
1075 {
1076         struct mlx5_priv *priv = dev->data->dev_private;
1077         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1078                                            priv->sh->dv_mark_mask);
1079         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1080         struct rte_flow_item item = {
1081                 .spec = &data,
1082                 .mask = &mask,
1083         };
1084         struct field_modify_info reg_c_x[] = {
1085                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1086                 {0, 0, 0},
1087         };
1088         int reg;
1089
1090         if (!mask)
1091                 return rte_flow_error_set(error, EINVAL,
1092                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1093                                           NULL, "zero mark action mask");
1094         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1095         if (reg < 0)
1096                 return reg;
1097         MLX5_ASSERT(reg > 0);
1098         if (reg == REG_C_0) {
1099                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1100                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1101
1102                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1103                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1104                 mask = rte_cpu_to_be_32(mask << shl_c0);
1105         }
1106         reg_c_x[0].id = reg_to_field[reg];
1107         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1108                                              MLX5_MODIFICATION_TYPE_SET, error);
1109 }
1110
1111 /**
1112  * Get metadata register index for specified steering domain.
1113  *
1114  * @param[in] dev
1115  *   Pointer to the rte_eth_dev structure.
1116  * @param[in] attr
1117  *   Attributes of flow to determine steering domain.
1118  * @param[out] error
1119  *   Pointer to the error structure.
1120  *
1121  * @return
1122  *   positive index on success, a negative errno value otherwise
1123  *   and rte_errno is set.
1124  */
1125 static enum modify_reg
1126 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1127                          const struct rte_flow_attr *attr,
1128                          struct rte_flow_error *error)
1129 {
1130         int reg =
1131                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1132                                           MLX5_METADATA_FDB :
1133                                             attr->egress ?
1134                                             MLX5_METADATA_TX :
1135                                             MLX5_METADATA_RX, 0, error);
1136         if (reg < 0)
1137                 return rte_flow_error_set(error,
1138                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1139                                           NULL, "unavailable "
1140                                           "metadata register");
1141         return reg;
1142 }
1143
1144 /**
1145  * Convert SET_META action to DV specification.
1146  *
1147  * @param[in] dev
1148  *   Pointer to the rte_eth_dev structure.
1149  * @param[in,out] resource
1150  *   Pointer to the modify-header resource.
1151  * @param[in] attr
1152  *   Attributes of flow that includes this item.
1153  * @param[in] conf
1154  *   Pointer to action specification.
1155  * @param[out] error
1156  *   Pointer to the error structure.
1157  *
1158  * @return
1159  *   0 on success, a negative errno value otherwise and rte_errno is set.
1160  */
1161 static int
1162 flow_dv_convert_action_set_meta
1163                         (struct rte_eth_dev *dev,
1164                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1165                          const struct rte_flow_attr *attr,
1166                          const struct rte_flow_action_set_meta *conf,
1167                          struct rte_flow_error *error)
1168 {
1169         uint32_t data = conf->data;
1170         uint32_t mask = conf->mask;
1171         struct rte_flow_item item = {
1172                 .spec = &data,
1173                 .mask = &mask,
1174         };
1175         struct field_modify_info reg_c_x[] = {
1176                 [1] = {0, 0, 0},
1177         };
1178         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1179
1180         if (reg < 0)
1181                 return reg;
1182         /*
1183          * In datapath code there is no endianness
1184          * coversions for perfromance reasons, all
1185          * pattern conversions are done in rte_flow.
1186          */
1187         if (reg == REG_C_0) {
1188                 struct mlx5_priv *priv = dev->data->dev_private;
1189                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1190                 uint32_t shl_c0;
1191
1192                 MLX5_ASSERT(msk_c0);
1193 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1194                 shl_c0 = rte_bsf32(msk_c0);
1195 #else
1196                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1197 #endif
1198                 mask <<= shl_c0;
1199                 data <<= shl_c0;
1200                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1201         }
1202         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1203         /* The routine expects parameters in memory as big-endian ones. */
1204         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1205                                              MLX5_MODIFICATION_TYPE_SET, error);
1206 }
1207
1208 /**
1209  * Convert modify-header set IPv4 DSCP action to DV specification.
1210  *
1211  * @param[in,out] resource
1212  *   Pointer to the modify-header resource.
1213  * @param[in] action
1214  *   Pointer to action specification.
1215  * @param[out] error
1216  *   Pointer to the error structure.
1217  *
1218  * @return
1219  *   0 on success, a negative errno value otherwise and rte_errno is set.
1220  */
1221 static int
1222 flow_dv_convert_action_modify_ipv4_dscp
1223                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1224                          const struct rte_flow_action *action,
1225                          struct rte_flow_error *error)
1226 {
1227         const struct rte_flow_action_set_dscp *conf =
1228                 (const struct rte_flow_action_set_dscp *)(action->conf);
1229         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1230         struct rte_flow_item_ipv4 ipv4;
1231         struct rte_flow_item_ipv4 ipv4_mask;
1232
1233         memset(&ipv4, 0, sizeof(ipv4));
1234         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1235         ipv4.hdr.type_of_service = conf->dscp;
1236         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1237         item.spec = &ipv4;
1238         item.mask = &ipv4_mask;
1239         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1240                                              MLX5_MODIFICATION_TYPE_SET, error);
1241 }
1242
1243 /**
1244  * Convert modify-header set IPv6 DSCP action to DV specification.
1245  *
1246  * @param[in,out] resource
1247  *   Pointer to the modify-header resource.
1248  * @param[in] action
1249  *   Pointer to action specification.
1250  * @param[out] error
1251  *   Pointer to the error structure.
1252  *
1253  * @return
1254  *   0 on success, a negative errno value otherwise and rte_errno is set.
1255  */
1256 static int
1257 flow_dv_convert_action_modify_ipv6_dscp
1258                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1259                          const struct rte_flow_action *action,
1260                          struct rte_flow_error *error)
1261 {
1262         const struct rte_flow_action_set_dscp *conf =
1263                 (const struct rte_flow_action_set_dscp *)(action->conf);
1264         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1265         struct rte_flow_item_ipv6 ipv6;
1266         struct rte_flow_item_ipv6 ipv6_mask;
1267
1268         memset(&ipv6, 0, sizeof(ipv6));
1269         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1270         /*
1271          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1272          * rdma-core only accept the DSCP bits byte aligned start from
1273          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1274          * bits in IPv6 case as rdma-core requires byte aligned value.
1275          */
1276         ipv6.hdr.vtc_flow = conf->dscp;
1277         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1278         item.spec = &ipv6;
1279         item.mask = &ipv6_mask;
1280         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1281                                              MLX5_MODIFICATION_TYPE_SET, error);
1282 }
1283
1284 /**
1285  * Validate MARK item.
1286  *
1287  * @param[in] dev
1288  *   Pointer to the rte_eth_dev structure.
1289  * @param[in] item
1290  *   Item specification.
1291  * @param[in] attr
1292  *   Attributes of flow that includes this item.
1293  * @param[out] error
1294  *   Pointer to error structure.
1295  *
1296  * @return
1297  *   0 on success, a negative errno value otherwise and rte_errno is set.
1298  */
1299 static int
1300 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1301                            const struct rte_flow_item *item,
1302                            const struct rte_flow_attr *attr __rte_unused,
1303                            struct rte_flow_error *error)
1304 {
1305         struct mlx5_priv *priv = dev->data->dev_private;
1306         struct mlx5_dev_config *config = &priv->config;
1307         const struct rte_flow_item_mark *spec = item->spec;
1308         const struct rte_flow_item_mark *mask = item->mask;
1309         const struct rte_flow_item_mark nic_mask = {
1310                 .id = priv->sh->dv_mark_mask,
1311         };
1312         int ret;
1313
1314         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1315                 return rte_flow_error_set(error, ENOTSUP,
1316                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1317                                           "extended metadata feature"
1318                                           " isn't enabled");
1319         if (!mlx5_flow_ext_mreg_supported(dev))
1320                 return rte_flow_error_set(error, ENOTSUP,
1321                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1322                                           "extended metadata register"
1323                                           " isn't supported");
1324         if (!nic_mask.id)
1325                 return rte_flow_error_set(error, ENOTSUP,
1326                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1327                                           "extended metadata register"
1328                                           " isn't available");
1329         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1330         if (ret < 0)
1331                 return ret;
1332         if (!spec)
1333                 return rte_flow_error_set(error, EINVAL,
1334                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1335                                           item->spec,
1336                                           "data cannot be empty");
1337         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1338                 return rte_flow_error_set(error, EINVAL,
1339                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1340                                           &spec->id,
1341                                           "mark id exceeds the limit");
1342         if (!mask)
1343                 mask = &nic_mask;
1344         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1345                                         (const uint8_t *)&nic_mask,
1346                                         sizeof(struct rte_flow_item_mark),
1347                                         error);
1348         if (ret < 0)
1349                 return ret;
1350         return 0;
1351 }
1352
1353 /**
1354  * Validate META item.
1355  *
1356  * @param[in] dev
1357  *   Pointer to the rte_eth_dev structure.
1358  * @param[in] item
1359  *   Item specification.
1360  * @param[in] attr
1361  *   Attributes of flow that includes this item.
1362  * @param[out] error
1363  *   Pointer to error structure.
1364  *
1365  * @return
1366  *   0 on success, a negative errno value otherwise and rte_errno is set.
1367  */
1368 static int
1369 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1370                            const struct rte_flow_item *item,
1371                            const struct rte_flow_attr *attr,
1372                            struct rte_flow_error *error)
1373 {
1374         struct mlx5_priv *priv = dev->data->dev_private;
1375         struct mlx5_dev_config *config = &priv->config;
1376         const struct rte_flow_item_meta *spec = item->spec;
1377         const struct rte_flow_item_meta *mask = item->mask;
1378         struct rte_flow_item_meta nic_mask = {
1379                 .data = UINT32_MAX
1380         };
1381         int reg;
1382         int ret;
1383
1384         if (!spec)
1385                 return rte_flow_error_set(error, EINVAL,
1386                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1387                                           item->spec,
1388                                           "data cannot be empty");
1389         if (!spec->data)
1390                 return rte_flow_error_set(error, EINVAL,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1392                                           "data cannot be zero");
1393         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1394                 if (!mlx5_flow_ext_mreg_supported(dev))
1395                         return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't supported");
1399                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1400                 if (reg < 0)
1401                         return reg;
1402                 if (reg == REG_B)
1403                         return rte_flow_error_set(error, ENOTSUP,
1404                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1405                                           "match on reg_b "
1406                                           "isn't supported");
1407                 if (reg != REG_A)
1408                         nic_mask.data = priv->sh->dv_meta_mask;
1409         }
1410         if (!mask)
1411                 mask = &rte_flow_item_meta_mask;
1412         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1413                                         (const uint8_t *)&nic_mask,
1414                                         sizeof(struct rte_flow_item_meta),
1415                                         error);
1416         return ret;
1417 }
1418
1419 /**
1420  * Validate TAG item.
1421  *
1422  * @param[in] dev
1423  *   Pointer to the rte_eth_dev structure.
1424  * @param[in] item
1425  *   Item specification.
1426  * @param[in] attr
1427  *   Attributes of flow that includes this item.
1428  * @param[out] error
1429  *   Pointer to error structure.
1430  *
1431  * @return
1432  *   0 on success, a negative errno value otherwise and rte_errno is set.
1433  */
1434 static int
1435 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1436                           const struct rte_flow_item *item,
1437                           const struct rte_flow_attr *attr __rte_unused,
1438                           struct rte_flow_error *error)
1439 {
1440         const struct rte_flow_item_tag *spec = item->spec;
1441         const struct rte_flow_item_tag *mask = item->mask;
1442         const struct rte_flow_item_tag nic_mask = {
1443                 .data = RTE_BE32(UINT32_MAX),
1444                 .index = 0xff,
1445         };
1446         int ret;
1447
1448         if (!mlx5_flow_ext_mreg_supported(dev))
1449                 return rte_flow_error_set(error, ENOTSUP,
1450                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1451                                           "extensive metadata register"
1452                                           " isn't supported");
1453         if (!spec)
1454                 return rte_flow_error_set(error, EINVAL,
1455                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1456                                           item->spec,
1457                                           "data cannot be empty");
1458         if (!mask)
1459                 mask = &rte_flow_item_tag_mask;
1460         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1461                                         (const uint8_t *)&nic_mask,
1462                                         sizeof(struct rte_flow_item_tag),
1463                                         error);
1464         if (ret < 0)
1465                 return ret;
1466         if (mask->index != 0xff)
1467                 return rte_flow_error_set(error, EINVAL,
1468                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1469                                           "partial mask for tag index"
1470                                           " is not supported");
1471         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1472         if (ret < 0)
1473                 return ret;
1474         MLX5_ASSERT(ret != REG_NONE);
1475         return 0;
1476 }
1477
1478 /**
1479  * Validate vport item.
1480  *
1481  * @param[in] dev
1482  *   Pointer to the rte_eth_dev structure.
1483  * @param[in] item
1484  *   Item specification.
1485  * @param[in] attr
1486  *   Attributes of flow that includes this item.
1487  * @param[in] item_flags
1488  *   Bit-fields that holds the items detected until now.
1489  * @param[out] error
1490  *   Pointer to error structure.
1491  *
1492  * @return
1493  *   0 on success, a negative errno value otherwise and rte_errno is set.
1494  */
1495 static int
1496 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1497                               const struct rte_flow_item *item,
1498                               const struct rte_flow_attr *attr,
1499                               uint64_t item_flags,
1500                               struct rte_flow_error *error)
1501 {
1502         const struct rte_flow_item_port_id *spec = item->spec;
1503         const struct rte_flow_item_port_id *mask = item->mask;
1504         const struct rte_flow_item_port_id switch_mask = {
1505                         .id = 0xffffffff,
1506         };
1507         struct mlx5_priv *esw_priv;
1508         struct mlx5_priv *dev_priv;
1509         int ret;
1510
1511         if (!attr->transfer)
1512                 return rte_flow_error_set(error, EINVAL,
1513                                           RTE_FLOW_ERROR_TYPE_ITEM,
1514                                           NULL,
1515                                           "match on port id is valid only"
1516                                           " when transfer flag is enabled");
1517         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1518                 return rte_flow_error_set(error, ENOTSUP,
1519                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1520                                           "multiple source ports are not"
1521                                           " supported");
1522         if (!mask)
1523                 mask = &switch_mask;
1524         if (mask->id != 0xffffffff)
1525                 return rte_flow_error_set(error, ENOTSUP,
1526                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1527                                            mask,
1528                                            "no support for partial mask on"
1529                                            " \"id\" field");
1530         ret = mlx5_flow_item_acceptable
1531                                 (item, (const uint8_t *)mask,
1532                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1533                                  sizeof(struct rte_flow_item_port_id),
1534                                  error);
1535         if (ret)
1536                 return ret;
1537         if (!spec)
1538                 return 0;
1539         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1540         if (!esw_priv)
1541                 return rte_flow_error_set(error, rte_errno,
1542                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1543                                           "failed to obtain E-Switch info for"
1544                                           " port");
1545         dev_priv = mlx5_dev_to_eswitch_info(dev);
1546         if (!dev_priv)
1547                 return rte_flow_error_set(error, rte_errno,
1548                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1549                                           NULL,
1550                                           "failed to obtain E-Switch info");
1551         if (esw_priv->domain_id != dev_priv->domain_id)
1552                 return rte_flow_error_set(error, EINVAL,
1553                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1554                                           "cannot match on a port from a"
1555                                           " different E-Switch");
1556         return 0;
1557 }
1558
1559 /**
1560  * Validate GTP item.
1561  *
1562  * @param[in] dev
1563  *   Pointer to the rte_eth_dev structure.
1564  * @param[in] item
1565  *   Item specification.
1566  * @param[in] item_flags
1567  *   Bit-fields that holds the items detected until now.
1568  * @param[out] error
1569  *   Pointer to error structure.
1570  *
1571  * @return
1572  *   0 on success, a negative errno value otherwise and rte_errno is set.
1573  */
1574 static int
1575 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1576                           const struct rte_flow_item *item,
1577                           uint64_t item_flags,
1578                           struct rte_flow_error *error)
1579 {
1580         struct mlx5_priv *priv = dev->data->dev_private;
1581         const struct rte_flow_item_gtp *mask = item->mask;
1582         const struct rte_flow_item_gtp nic_mask = {
1583                 .msg_type = 0xff,
1584                 .teid = RTE_BE32(0xffffffff),
1585         };
1586
1587         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1588                 return rte_flow_error_set(error, ENOTSUP,
1589                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1590                                           "GTP support is not enabled");
1591         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1592                 return rte_flow_error_set(error, ENOTSUP,
1593                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1594                                           "multiple tunnel layers not"
1595                                           " supported");
1596         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1597                 return rte_flow_error_set(error, EINVAL,
1598                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1599                                           "no outer UDP layer found");
1600         if (!mask)
1601                 mask = &rte_flow_item_gtp_mask;
1602         return mlx5_flow_item_acceptable
1603                 (item, (const uint8_t *)mask,
1604                  (const uint8_t *)&nic_mask,
1605                  sizeof(struct rte_flow_item_gtp),
1606                  error);
1607 }
1608
1609 /**
1610  * Validate the pop VLAN action.
1611  *
1612  * @param[in] dev
1613  *   Pointer to the rte_eth_dev structure.
1614  * @param[in] action_flags
1615  *   Holds the actions detected until now.
1616  * @param[in] action
1617  *   Pointer to the pop vlan action.
1618  * @param[in] item_flags
1619  *   The items found in this flow rule.
1620  * @param[in] attr
1621  *   Pointer to flow attributes.
1622  * @param[out] error
1623  *   Pointer to error structure.
1624  *
1625  * @return
1626  *   0 on success, a negative errno value otherwise and rte_errno is set.
1627  */
1628 static int
1629 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1630                                  uint64_t action_flags,
1631                                  const struct rte_flow_action *action,
1632                                  uint64_t item_flags,
1633                                  const struct rte_flow_attr *attr,
1634                                  struct rte_flow_error *error)
1635 {
1636         struct mlx5_priv *priv = dev->data->dev_private;
1637
1638         (void)action;
1639         (void)attr;
1640         if (!priv->sh->pop_vlan_action)
1641                 return rte_flow_error_set(error, ENOTSUP,
1642                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1643                                           NULL,
1644                                           "pop vlan action is not supported");
1645         if (attr->egress)
1646                 return rte_flow_error_set(error, ENOTSUP,
1647                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1648                                           NULL,
1649                                           "pop vlan action not supported for "
1650                                           "egress");
1651         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1652                 return rte_flow_error_set(error, ENOTSUP,
1653                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1654                                           "no support for multiple VLAN "
1655                                           "actions");
1656         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1657                 return rte_flow_error_set(error, ENOTSUP,
1658                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1659                                           NULL,
1660                                           "cannot pop vlan without a "
1661                                           "match on (outer) vlan in the flow");
1662         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1663                 return rte_flow_error_set(error, EINVAL,
1664                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1665                                           "wrong action order, port_id should "
1666                                           "be after pop VLAN action");
1667         return 0;
1668 }
1669
1670 /**
1671  * Get VLAN default info from vlan match info.
1672  *
1673  * @param[in] items
1674  *   the list of item specifications.
1675  * @param[out] vlan
1676  *   pointer VLAN info to fill to.
1677  *
1678  * @return
1679  *   0 on success, a negative errno value otherwise and rte_errno is set.
1680  */
1681 static void
1682 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1683                                   struct rte_vlan_hdr *vlan)
1684 {
1685         const struct rte_flow_item_vlan nic_mask = {
1686                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1687                                 MLX5DV_FLOW_VLAN_VID_MASK),
1688                 .inner_type = RTE_BE16(0xffff),
1689         };
1690
1691         if (items == NULL)
1692                 return;
1693         for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1694                items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1695                 ;
1696         if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1697                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1698                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1699
1700                 if (!vlan_m)
1701                         vlan_m = &nic_mask;
1702                 /* Only full match values are accepted */
1703                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1704                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1705                         vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1706                         vlan->vlan_tci |=
1707                                 rte_be_to_cpu_16(vlan_v->tci &
1708                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1709                 }
1710                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1711                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1712                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1713                         vlan->vlan_tci |=
1714                                 rte_be_to_cpu_16(vlan_v->tci &
1715                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1716                 }
1717                 if (vlan_m->inner_type == nic_mask.inner_type)
1718                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1719                                                            vlan_m->inner_type);
1720         }
1721 }
1722
1723 /**
1724  * Validate the push VLAN action.
1725  *
1726  * @param[in] action_flags
1727  *   Holds the actions detected until now.
1728  * @param[in] item_flags
1729  *   The items found in this flow rule.
1730  * @param[in] action
1731  *   Pointer to the action structure.
1732  * @param[in] attr
1733  *   Pointer to flow attributes
1734  * @param[out] error
1735  *   Pointer to error structure.
1736  *
1737  * @return
1738  *   0 on success, a negative errno value otherwise and rte_errno is set.
1739  */
1740 static int
1741 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1742                                   uint64_t item_flags __rte_unused,
1743                                   const struct rte_flow_action *action,
1744                                   const struct rte_flow_attr *attr,
1745                                   struct rte_flow_error *error)
1746 {
1747         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1748
1749         if (!attr->transfer && attr->ingress)
1750                 return rte_flow_error_set(error, ENOTSUP,
1751                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1752                                           NULL,
1753                                           "push VLAN action not supported for "
1754                                           "ingress");
1755         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1756             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1757                 return rte_flow_error_set(error, EINVAL,
1758                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1759                                           "invalid vlan ethertype");
1760         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1761                 return rte_flow_error_set(error, ENOTSUP,
1762                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1763                                           "no support for multiple VLAN "
1764                                           "actions");
1765         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1766                 return rte_flow_error_set(error, EINVAL,
1767                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1768                                           "wrong action order, port_id should "
1769                                           "be after push VLAN");
1770         (void)attr;
1771         return 0;
1772 }
1773
1774 /**
1775  * Validate the set VLAN PCP.
1776  *
1777  * @param[in] action_flags
1778  *   Holds the actions detected until now.
1779  * @param[in] actions
1780  *   Pointer to the list of actions remaining in the flow rule.
1781  * @param[out] error
1782  *   Pointer to error structure.
1783  *
1784  * @return
1785  *   0 on success, a negative errno value otherwise and rte_errno is set.
1786  */
1787 static int
1788 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1789                                      const struct rte_flow_action actions[],
1790                                      struct rte_flow_error *error)
1791 {
1792         const struct rte_flow_action *action = actions;
1793         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1794
1795         if (conf->vlan_pcp > 7)
1796                 return rte_flow_error_set(error, EINVAL,
1797                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1798                                           "VLAN PCP value is too big");
1799         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1800                 return rte_flow_error_set(error, ENOTSUP,
1801                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1802                                           "set VLAN PCP action must follow "
1803                                           "the push VLAN action");
1804         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1805                 return rte_flow_error_set(error, ENOTSUP,
1806                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1807                                           "Multiple VLAN PCP modification are "
1808                                           "not supported");
1809         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1810                 return rte_flow_error_set(error, EINVAL,
1811                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1812                                           "wrong action order, port_id should "
1813                                           "be after set VLAN PCP");
1814         return 0;
1815 }
1816
1817 /**
1818  * Validate the set VLAN VID.
1819  *
1820  * @param[in] item_flags
1821  *   Holds the items detected in this rule.
1822  * @param[in] action_flags
1823  *   Holds the actions detected until now.
1824  * @param[in] actions
1825  *   Pointer to the list of actions remaining in the flow rule.
1826  * @param[out] error
1827  *   Pointer to error structure.
1828  *
1829  * @return
1830  *   0 on success, a negative errno value otherwise and rte_errno is set.
1831  */
1832 static int
1833 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1834                                      uint64_t action_flags,
1835                                      const struct rte_flow_action actions[],
1836                                      struct rte_flow_error *error)
1837 {
1838         const struct rte_flow_action *action = actions;
1839         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1840
1841         if (conf->vlan_vid > RTE_BE16(0xFFE))
1842                 return rte_flow_error_set(error, EINVAL,
1843                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1844                                           "VLAN VID value is too big");
1845         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1846             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847                 return rte_flow_error_set(error, ENOTSUP,
1848                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1849                                           "set VLAN VID action must follow push"
1850                                           " VLAN action or match on VLAN item");
1851         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1852                 return rte_flow_error_set(error, ENOTSUP,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1854                                           "Multiple VLAN VID modifications are "
1855                                           "not supported");
1856         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857                 return rte_flow_error_set(error, EINVAL,
1858                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1859                                           "wrong action order, port_id should "
1860                                           "be after set VLAN VID");
1861         return 0;
1862 }
1863
1864 /*
1865  * Validate the FLAG action.
1866  *
1867  * @param[in] dev
1868  *   Pointer to the rte_eth_dev structure.
1869  * @param[in] action_flags
1870  *   Holds the actions detected until now.
1871  * @param[in] attr
1872  *   Pointer to flow attributes
1873  * @param[out] error
1874  *   Pointer to error structure.
1875  *
1876  * @return
1877  *   0 on success, a negative errno value otherwise and rte_errno is set.
1878  */
1879 static int
1880 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1881                              uint64_t action_flags,
1882                              const struct rte_flow_attr *attr,
1883                              struct rte_flow_error *error)
1884 {
1885         struct mlx5_priv *priv = dev->data->dev_private;
1886         struct mlx5_dev_config *config = &priv->config;
1887         int ret;
1888
1889         /* Fall back if no extended metadata register support. */
1890         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1891                 return mlx5_flow_validate_action_flag(action_flags, attr,
1892                                                       error);
1893         /* Extensive metadata mode requires registers. */
1894         if (!mlx5_flow_ext_mreg_supported(dev))
1895                 return rte_flow_error_set(error, ENOTSUP,
1896                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1897                                           "no metadata registers "
1898                                           "to support flag action");
1899         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1900                 return rte_flow_error_set(error, ENOTSUP,
1901                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1902                                           "extended metadata register"
1903                                           " isn't available");
1904         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1905         if (ret < 0)
1906                 return ret;
1907         MLX5_ASSERT(ret > 0);
1908         if (action_flags & MLX5_FLOW_ACTION_MARK)
1909                 return rte_flow_error_set(error, EINVAL,
1910                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1911                                           "can't mark and flag in same flow");
1912         if (action_flags & MLX5_FLOW_ACTION_FLAG)
1913                 return rte_flow_error_set(error, EINVAL,
1914                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1915                                           "can't have 2 flag"
1916                                           " actions in same flow");
1917         return 0;
1918 }
1919
1920 /**
1921  * Validate MARK action.
1922  *
1923  * @param[in] dev
1924  *   Pointer to the rte_eth_dev structure.
1925  * @param[in] action
1926  *   Pointer to action.
1927  * @param[in] action_flags
1928  *   Holds the actions detected until now.
1929  * @param[in] attr
1930  *   Pointer to flow attributes
1931  * @param[out] error
1932  *   Pointer to error structure.
1933  *
1934  * @return
1935  *   0 on success, a negative errno value otherwise and rte_errno is set.
1936  */
1937 static int
1938 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1939                              const struct rte_flow_action *action,
1940                              uint64_t action_flags,
1941                              const struct rte_flow_attr *attr,
1942                              struct rte_flow_error *error)
1943 {
1944         struct mlx5_priv *priv = dev->data->dev_private;
1945         struct mlx5_dev_config *config = &priv->config;
1946         const struct rte_flow_action_mark *mark = action->conf;
1947         int ret;
1948
1949         /* Fall back if no extended metadata register support. */
1950         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1951                 return mlx5_flow_validate_action_mark(action, action_flags,
1952                                                       attr, error);
1953         /* Extensive metadata mode requires registers. */
1954         if (!mlx5_flow_ext_mreg_supported(dev))
1955                 return rte_flow_error_set(error, ENOTSUP,
1956                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1957                                           "no metadata registers "
1958                                           "to support mark action");
1959         if (!priv->sh->dv_mark_mask)
1960                 return rte_flow_error_set(error, ENOTSUP,
1961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1962                                           "extended metadata register"
1963                                           " isn't available");
1964         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1965         if (ret < 0)
1966                 return ret;
1967         MLX5_ASSERT(ret > 0);
1968         if (!mark)
1969                 return rte_flow_error_set(error, EINVAL,
1970                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1971                                           "configuration cannot be null");
1972         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1975                                           &mark->id,
1976                                           "mark id exceeds the limit");
1977         if (action_flags & MLX5_FLOW_ACTION_FLAG)
1978                 return rte_flow_error_set(error, EINVAL,
1979                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1980                                           "can't flag and mark in same flow");
1981         if (action_flags & MLX5_FLOW_ACTION_MARK)
1982                 return rte_flow_error_set(error, EINVAL,
1983                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1984                                           "can't have 2 mark actions in same"
1985                                           " flow");
1986         return 0;
1987 }
1988
1989 /**
1990  * Validate SET_META action.
1991  *
1992  * @param[in] dev
1993  *   Pointer to the rte_eth_dev structure.
1994  * @param[in] action
1995  *   Pointer to the action structure.
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] attr
1999  *   Pointer to flow attributes
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2008                                  const struct rte_flow_action *action,
2009                                  uint64_t action_flags __rte_unused,
2010                                  const struct rte_flow_attr *attr,
2011                                  struct rte_flow_error *error)
2012 {
2013         const struct rte_flow_action_set_meta *conf;
2014         uint32_t nic_mask = UINT32_MAX;
2015         int reg;
2016
2017         if (!mlx5_flow_ext_mreg_supported(dev))
2018                 return rte_flow_error_set(error, ENOTSUP,
2019                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2020                                           "extended metadata register"
2021                                           " isn't supported");
2022         reg = flow_dv_get_metadata_reg(dev, attr, error);
2023         if (reg < 0)
2024                 return reg;
2025         if (reg != REG_A && reg != REG_B) {
2026                 struct mlx5_priv *priv = dev->data->dev_private;
2027
2028                 nic_mask = priv->sh->dv_meta_mask;
2029         }
2030         if (!(action->conf))
2031                 return rte_flow_error_set(error, EINVAL,
2032                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2033                                           "configuration cannot be null");
2034         conf = (const struct rte_flow_action_set_meta *)action->conf;
2035         if (!conf->mask)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2038                                           "zero mask doesn't have any effect");
2039         if (conf->mask & ~nic_mask)
2040                 return rte_flow_error_set(error, EINVAL,
2041                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2042                                           "meta data must be within reg C0");
2043         if (!(conf->data & conf->mask))
2044                 return rte_flow_error_set(error, EINVAL,
2045                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2046                                           "zero value has no effect");
2047         return 0;
2048 }
2049
2050 /**
2051  * Validate SET_TAG action.
2052  *
2053  * @param[in] dev
2054  *   Pointer to the rte_eth_dev structure.
2055  * @param[in] action
2056  *   Pointer to the action structure.
2057  * @param[in] action_flags
2058  *   Holds the actions detected until now.
2059  * @param[in] attr
2060  *   Pointer to flow attributes
2061  * @param[out] error
2062  *   Pointer to error structure.
2063  *
2064  * @return
2065  *   0 on success, a negative errno value otherwise and rte_errno is set.
2066  */
2067 static int
2068 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2069                                 const struct rte_flow_action *action,
2070                                 uint64_t action_flags,
2071                                 const struct rte_flow_attr *attr,
2072                                 struct rte_flow_error *error)
2073 {
2074         const struct rte_flow_action_set_tag *conf;
2075         const uint64_t terminal_action_flags =
2076                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2077                 MLX5_FLOW_ACTION_RSS;
2078         int ret;
2079
2080         if (!mlx5_flow_ext_mreg_supported(dev))
2081                 return rte_flow_error_set(error, ENOTSUP,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2083                                           "extensive metadata register"
2084                                           " isn't supported");
2085         if (!(action->conf))
2086                 return rte_flow_error_set(error, EINVAL,
2087                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2088                                           "configuration cannot be null");
2089         conf = (const struct rte_flow_action_set_tag *)action->conf;
2090         if (!conf->mask)
2091                 return rte_flow_error_set(error, EINVAL,
2092                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2093                                           "zero mask doesn't have any effect");
2094         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2095         if (ret < 0)
2096                 return ret;
2097         if (!attr->transfer && attr->ingress &&
2098             (action_flags & terminal_action_flags))
2099                 return rte_flow_error_set(error, EINVAL,
2100                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2101                                           "set_tag has no effect"
2102                                           " with terminal actions");
2103         return 0;
2104 }
2105
2106 /**
2107  * Validate count action.
2108  *
2109  * @param[in] dev
2110  *   Pointer to rte_eth_dev structure.
2111  * @param[out] error
2112  *   Pointer to error structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 static int
2118 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2119                               struct rte_flow_error *error)
2120 {
2121         struct mlx5_priv *priv = dev->data->dev_private;
2122
2123         if (!priv->config.devx)
2124                 goto notsup_err;
2125 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2126         return 0;
2127 #endif
2128 notsup_err:
2129         return rte_flow_error_set
2130                       (error, ENOTSUP,
2131                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2132                        NULL,
2133                        "count action not supported");
2134 }
2135
2136 /**
2137  * Validate the L2 encap action.
2138  *
2139  * @param[in] action_flags
2140  *   Holds the actions detected until now.
2141  * @param[in] action
2142  *   Pointer to the action structure.
2143  * @param[out] error
2144  *   Pointer to error structure.
2145  *
2146  * @return
2147  *   0 on success, a negative errno value otherwise and rte_errno is set.
2148  */
2149 static int
2150 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2151                                  const struct rte_flow_action *action,
2152                                  struct rte_flow_error *error)
2153 {
2154         if (!(action->conf))
2155                 return rte_flow_error_set(error, EINVAL,
2156                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2157                                           "configuration cannot be null");
2158         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2159                 return rte_flow_error_set(error, EINVAL,
2160                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2161                                           "can only have a single encap action "
2162                                           "in a flow");
2163         return 0;
2164 }
2165
2166 /**
2167  * Validate a decap action.
2168  *
2169  * @param[in] action_flags
2170  *   Holds the actions detected until now.
2171  * @param[in] attr
2172  *   Pointer to flow attributes
2173  * @param[out] error
2174  *   Pointer to error structure.
2175  *
2176  * @return
2177  *   0 on success, a negative errno value otherwise and rte_errno is set.
2178  */
2179 static int
2180 flow_dv_validate_action_decap(uint64_t action_flags,
2181                                  const struct rte_flow_attr *attr,
2182                                  struct rte_flow_error *error)
2183 {
2184         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2185                 return rte_flow_error_set(error, ENOTSUP,
2186                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2187                                           action_flags &
2188                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2189                                           "have a single decap action" : "decap "
2190                                           "after encap is not supported");
2191         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2194                                           "can't have decap action after"
2195                                           " modify action");
2196         if (attr->egress)
2197                 return rte_flow_error_set(error, ENOTSUP,
2198                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2199                                           NULL,
2200                                           "decap action not supported for "
2201                                           "egress");
2202         return 0;
2203 }
2204
2205 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2206
2207 /**
2208  * Validate the raw encap and decap actions.
2209  *
2210  * @param[in] decap
2211  *   Pointer to the decap action.
2212  * @param[in] encap
2213  *   Pointer to the encap action.
2214  * @param[in] attr
2215  *   Pointer to flow attributes
2216  * @param[in/out] action_flags
2217  *   Holds the actions detected until now.
2218  * @param[out] actions_n
2219  *   pointer to the number of actions counter.
2220  * @param[out] error
2221  *   Pointer to error structure.
2222  *
2223  * @return
2224  *   0 on success, a negative errno value otherwise and rte_errno is set.
2225  */
2226 static int
2227 flow_dv_validate_action_raw_encap_decap
2228         (const struct rte_flow_action_raw_decap *decap,
2229          const struct rte_flow_action_raw_encap *encap,
2230          const struct rte_flow_attr *attr, uint64_t *action_flags,
2231          int *actions_n, struct rte_flow_error *error)
2232 {
2233         int ret;
2234
2235         if (encap && (!encap->size || !encap->data))
2236                 return rte_flow_error_set(error, EINVAL,
2237                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2238                                           "raw encap data cannot be empty");
2239         if (decap && encap) {
2240                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2241                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2242                         /* L3 encap. */
2243                         decap = NULL;
2244                 else if (encap->size <=
2245                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2246                            decap->size >
2247                            MLX5_ENCAPSULATION_DECISION_SIZE)
2248                         /* L3 decap. */
2249                         encap = NULL;
2250                 else if (encap->size >
2251                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2252                            decap->size >
2253                            MLX5_ENCAPSULATION_DECISION_SIZE)
2254                         /* 2 L2 actions: encap and decap. */
2255                         ;
2256                 else
2257                         return rte_flow_error_set(error,
2258                                 ENOTSUP,
2259                                 RTE_FLOW_ERROR_TYPE_ACTION,
2260                                 NULL, "unsupported too small "
2261                                 "raw decap and too small raw "
2262                                 "encap combination");
2263         }
2264         if (decap) {
2265                 ret = flow_dv_validate_action_decap(*action_flags, attr, error);
2266                 if (ret < 0)
2267                         return ret;
2268                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2269                 ++(*actions_n);
2270         }
2271         if (encap) {
2272                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2273                         return rte_flow_error_set(error, ENOTSUP,
2274                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2275                                                   NULL,
2276                                                   "small raw encap size");
2277                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2278                         return rte_flow_error_set(error, EINVAL,
2279                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2280                                                   NULL,
2281                                                   "more than one encap action");
2282                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2283                 ++(*actions_n);
2284         }
2285         return 0;
2286 }
2287
2288 /**
2289  * Find existing encap/decap resource or create and register a new one.
2290  *
2291  * @param[in, out] dev
2292  *   Pointer to rte_eth_dev structure.
2293  * @param[in, out] resource
2294  *   Pointer to encap/decap resource.
2295  * @parm[in, out] dev_flow
2296  *   Pointer to the dev_flow.
2297  * @param[out] error
2298  *   pointer to error structure.
2299  *
2300  * @return
2301  *   0 on success otherwise -errno and errno is set.
2302  */
2303 static int
2304 flow_dv_encap_decap_resource_register
2305                         (struct rte_eth_dev *dev,
2306                          struct mlx5_flow_dv_encap_decap_resource *resource,
2307                          struct mlx5_flow *dev_flow,
2308                          struct rte_flow_error *error)
2309 {
2310         struct mlx5_priv *priv = dev->data->dev_private;
2311         struct mlx5_ibv_shared *sh = priv->sh;
2312         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2313         struct mlx5dv_dr_domain *domain;
2314
2315         resource->flags = dev_flow->group ? 0 : 1;
2316         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2317                 domain = sh->fdb_domain;
2318         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2319                 domain = sh->rx_domain;
2320         else
2321                 domain = sh->tx_domain;
2322         /* Lookup a matching resource from cache. */
2323         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2324                 if (resource->reformat_type == cache_resource->reformat_type &&
2325                     resource->ft_type == cache_resource->ft_type &&
2326                     resource->flags == cache_resource->flags &&
2327                     resource->size == cache_resource->size &&
2328                     !memcmp((const void *)resource->buf,
2329                             (const void *)cache_resource->buf,
2330                             resource->size)) {
2331                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2332                                 (void *)cache_resource,
2333                                 rte_atomic32_read(&cache_resource->refcnt));
2334                         rte_atomic32_inc(&cache_resource->refcnt);
2335                         dev_flow->dv.encap_decap = cache_resource;
2336                         return 0;
2337                 }
2338         }
2339         /* Register new encap/decap resource. */
2340         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2341         if (!cache_resource)
2342                 return rte_flow_error_set(error, ENOMEM,
2343                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2344                                           "cannot allocate resource memory");
2345         *cache_resource = *resource;
2346         cache_resource->verbs_action =
2347                 mlx5_glue->dv_create_flow_action_packet_reformat
2348                         (sh->ctx, cache_resource->reformat_type,
2349                          cache_resource->ft_type, domain, cache_resource->flags,
2350                          cache_resource->size,
2351                          (cache_resource->size ? cache_resource->buf : NULL));
2352         if (!cache_resource->verbs_action) {
2353                 rte_free(cache_resource);
2354                 return rte_flow_error_set(error, ENOMEM,
2355                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2356                                           NULL, "cannot create action");
2357         }
2358         rte_atomic32_init(&cache_resource->refcnt);
2359         rte_atomic32_inc(&cache_resource->refcnt);
2360         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2361         dev_flow->dv.encap_decap = cache_resource;
2362         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2363                 (void *)cache_resource,
2364                 rte_atomic32_read(&cache_resource->refcnt));
2365         return 0;
2366 }
2367
2368 /**
2369  * Find existing table jump resource or create and register a new one.
2370  *
2371  * @param[in, out] dev
2372  *   Pointer to rte_eth_dev structure.
2373  * @param[in, out] tbl
2374  *   Pointer to flow table resource.
2375  * @parm[in, out] dev_flow
2376  *   Pointer to the dev_flow.
2377  * @param[out] error
2378  *   pointer to error structure.
2379  *
2380  * @return
2381  *   0 on success otherwise -errno and errno is set.
2382  */
2383 static int
2384 flow_dv_jump_tbl_resource_register
2385                         (struct rte_eth_dev *dev __rte_unused,
2386                          struct mlx5_flow_tbl_resource *tbl,
2387                          struct mlx5_flow *dev_flow,
2388                          struct rte_flow_error *error)
2389 {
2390         struct mlx5_flow_tbl_data_entry *tbl_data =
2391                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2392         int cnt;
2393
2394         MLX5_ASSERT(tbl);
2395         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2396         if (!cnt) {
2397                 tbl_data->jump.action =
2398                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2399                         (tbl->obj);
2400                 if (!tbl_data->jump.action)
2401                         return rte_flow_error_set(error, ENOMEM,
2402                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2403                                         NULL, "cannot create jump action");
2404                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2405                         (void *)&tbl_data->jump, cnt);
2406         } else {
2407                 MLX5_ASSERT(tbl_data->jump.action);
2408                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2409                         (void *)&tbl_data->jump, cnt);
2410         }
2411         rte_atomic32_inc(&tbl_data->jump.refcnt);
2412         dev_flow->dv.jump = &tbl_data->jump;
2413         return 0;
2414 }
2415
2416 /**
2417  * Find existing table port ID resource or create and register a new one.
2418  *
2419  * @param[in, out] dev
2420  *   Pointer to rte_eth_dev structure.
2421  * @param[in, out] resource
2422  *   Pointer to port ID action resource.
2423  * @parm[in, out] dev_flow
2424  *   Pointer to the dev_flow.
2425  * @param[out] error
2426  *   pointer to error structure.
2427  *
2428  * @return
2429  *   0 on success otherwise -errno and errno is set.
2430  */
2431 static int
2432 flow_dv_port_id_action_resource_register
2433                         (struct rte_eth_dev *dev,
2434                          struct mlx5_flow_dv_port_id_action_resource *resource,
2435                          struct mlx5_flow *dev_flow,
2436                          struct rte_flow_error *error)
2437 {
2438         struct mlx5_priv *priv = dev->data->dev_private;
2439         struct mlx5_ibv_shared *sh = priv->sh;
2440         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2441
2442         /* Lookup a matching resource from cache. */
2443         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2444                 if (resource->port_id == cache_resource->port_id) {
2445                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2446                                 "refcnt %d++",
2447                                 (void *)cache_resource,
2448                                 rte_atomic32_read(&cache_resource->refcnt));
2449                         rte_atomic32_inc(&cache_resource->refcnt);
2450                         dev_flow->dv.port_id_action = cache_resource;
2451                         return 0;
2452                 }
2453         }
2454         /* Register new port id action resource. */
2455         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2456         if (!cache_resource)
2457                 return rte_flow_error_set(error, ENOMEM,
2458                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2459                                           "cannot allocate resource memory");
2460         *cache_resource = *resource;
2461         /*
2462          * Depending on rdma_core version the glue routine calls
2463          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2464          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2465          */
2466         cache_resource->action =
2467                 mlx5_glue->dr_create_flow_action_dest_port
2468                         (priv->sh->fdb_domain, resource->port_id);
2469         if (!cache_resource->action) {
2470                 rte_free(cache_resource);
2471                 return rte_flow_error_set(error, ENOMEM,
2472                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2473                                           NULL, "cannot create action");
2474         }
2475         rte_atomic32_init(&cache_resource->refcnt);
2476         rte_atomic32_inc(&cache_resource->refcnt);
2477         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2478         dev_flow->dv.port_id_action = cache_resource;
2479         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2480                 (void *)cache_resource,
2481                 rte_atomic32_read(&cache_resource->refcnt));
2482         return 0;
2483 }
2484
2485 /**
2486  * Find existing push vlan resource or create and register a new one.
2487  *
2488  * @param [in, out] dev
2489  *   Pointer to rte_eth_dev structure.
2490  * @param[in, out] resource
2491  *   Pointer to port ID action resource.
2492  * @parm[in, out] dev_flow
2493  *   Pointer to the dev_flow.
2494  * @param[out] error
2495  *   pointer to error structure.
2496  *
2497  * @return
2498  *   0 on success otherwise -errno and errno is set.
2499  */
2500 static int
2501 flow_dv_push_vlan_action_resource_register
2502                        (struct rte_eth_dev *dev,
2503                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2504                         struct mlx5_flow *dev_flow,
2505                         struct rte_flow_error *error)
2506 {
2507         struct mlx5_priv *priv = dev->data->dev_private;
2508         struct mlx5_ibv_shared *sh = priv->sh;
2509         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2510         struct mlx5dv_dr_domain *domain;
2511
2512         /* Lookup a matching resource from cache. */
2513         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2514                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2515                     resource->ft_type == cache_resource->ft_type) {
2516                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2517                                 "refcnt %d++",
2518                                 (void *)cache_resource,
2519                                 rte_atomic32_read(&cache_resource->refcnt));
2520                         rte_atomic32_inc(&cache_resource->refcnt);
2521                         dev_flow->dv.push_vlan_res = cache_resource;
2522                         return 0;
2523                 }
2524         }
2525         /* Register new push_vlan action resource. */
2526         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2527         if (!cache_resource)
2528                 return rte_flow_error_set(error, ENOMEM,
2529                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2530                                           "cannot allocate resource memory");
2531         *cache_resource = *resource;
2532         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2533                 domain = sh->fdb_domain;
2534         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2535                 domain = sh->rx_domain;
2536         else
2537                 domain = sh->tx_domain;
2538         cache_resource->action =
2539                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2540                                                            resource->vlan_tag);
2541         if (!cache_resource->action) {
2542                 rte_free(cache_resource);
2543                 return rte_flow_error_set(error, ENOMEM,
2544                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2545                                           NULL, "cannot create action");
2546         }
2547         rte_atomic32_init(&cache_resource->refcnt);
2548         rte_atomic32_inc(&cache_resource->refcnt);
2549         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2550         dev_flow->dv.push_vlan_res = cache_resource;
2551         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2552                 (void *)cache_resource,
2553                 rte_atomic32_read(&cache_resource->refcnt));
2554         return 0;
2555 }
2556 /**
2557  * Get the size of specific rte_flow_item_type
2558  *
2559  * @param[in] item_type
2560  *   Tested rte_flow_item_type.
2561  *
2562  * @return
2563  *   sizeof struct item_type, 0 if void or irrelevant.
2564  */
2565 static size_t
2566 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2567 {
2568         size_t retval;
2569
2570         switch (item_type) {
2571         case RTE_FLOW_ITEM_TYPE_ETH:
2572                 retval = sizeof(struct rte_flow_item_eth);
2573                 break;
2574         case RTE_FLOW_ITEM_TYPE_VLAN:
2575                 retval = sizeof(struct rte_flow_item_vlan);
2576                 break;
2577         case RTE_FLOW_ITEM_TYPE_IPV4:
2578                 retval = sizeof(struct rte_flow_item_ipv4);
2579                 break;
2580         case RTE_FLOW_ITEM_TYPE_IPV6:
2581                 retval = sizeof(struct rte_flow_item_ipv6);
2582                 break;
2583         case RTE_FLOW_ITEM_TYPE_UDP:
2584                 retval = sizeof(struct rte_flow_item_udp);
2585                 break;
2586         case RTE_FLOW_ITEM_TYPE_TCP:
2587                 retval = sizeof(struct rte_flow_item_tcp);
2588                 break;
2589         case RTE_FLOW_ITEM_TYPE_VXLAN:
2590                 retval = sizeof(struct rte_flow_item_vxlan);
2591                 break;
2592         case RTE_FLOW_ITEM_TYPE_GRE:
2593                 retval = sizeof(struct rte_flow_item_gre);
2594                 break;
2595         case RTE_FLOW_ITEM_TYPE_NVGRE:
2596                 retval = sizeof(struct rte_flow_item_nvgre);
2597                 break;
2598         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2599                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2600                 break;
2601         case RTE_FLOW_ITEM_TYPE_MPLS:
2602                 retval = sizeof(struct rte_flow_item_mpls);
2603                 break;
2604         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2605         default:
2606                 retval = 0;
2607                 break;
2608         }
2609         return retval;
2610 }
2611
2612 #define MLX5_ENCAP_IPV4_VERSION         0x40
2613 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2614 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2615 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2616 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2617 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2618 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2619
2620 /**
2621  * Convert the encap action data from list of rte_flow_item to raw buffer
2622  *
2623  * @param[in] items
2624  *   Pointer to rte_flow_item objects list.
2625  * @param[out] buf
2626  *   Pointer to the output buffer.
2627  * @param[out] size
2628  *   Pointer to the output buffer size.
2629  * @param[out] error
2630  *   Pointer to the error structure.
2631  *
2632  * @return
2633  *   0 on success, a negative errno value otherwise and rte_errno is set.
2634  */
2635 static int
2636 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2637                            size_t *size, struct rte_flow_error *error)
2638 {
2639         struct rte_ether_hdr *eth = NULL;
2640         struct rte_vlan_hdr *vlan = NULL;
2641         struct rte_ipv4_hdr *ipv4 = NULL;
2642         struct rte_ipv6_hdr *ipv6 = NULL;
2643         struct rte_udp_hdr *udp = NULL;
2644         struct rte_vxlan_hdr *vxlan = NULL;
2645         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2646         struct rte_gre_hdr *gre = NULL;
2647         size_t len;
2648         size_t temp_size = 0;
2649
2650         if (!items)
2651                 return rte_flow_error_set(error, EINVAL,
2652                                           RTE_FLOW_ERROR_TYPE_ACTION,
2653                                           NULL, "invalid empty data");
2654         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2655                 len = flow_dv_get_item_len(items->type);
2656                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2657                         return rte_flow_error_set(error, EINVAL,
2658                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2659                                                   (void *)items->type,
2660                                                   "items total size is too big"
2661                                                   " for encap action");
2662                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2663                 switch (items->type) {
2664                 case RTE_FLOW_ITEM_TYPE_ETH:
2665                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2666                         break;
2667                 case RTE_FLOW_ITEM_TYPE_VLAN:
2668                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2669                         if (!eth)
2670                                 return rte_flow_error_set(error, EINVAL,
2671                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2672                                                 (void *)items->type,
2673                                                 "eth header not found");
2674                         if (!eth->ether_type)
2675                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2676                         break;
2677                 case RTE_FLOW_ITEM_TYPE_IPV4:
2678                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2679                         if (!vlan && !eth)
2680                                 return rte_flow_error_set(error, EINVAL,
2681                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2682                                                 (void *)items->type,
2683                                                 "neither eth nor vlan"
2684                                                 " header found");
2685                         if (vlan && !vlan->eth_proto)
2686                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2687                         else if (eth && !eth->ether_type)
2688                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2689                         if (!ipv4->version_ihl)
2690                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2691                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2692                         if (!ipv4->time_to_live)
2693                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2694                         break;
2695                 case RTE_FLOW_ITEM_TYPE_IPV6:
2696                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2697                         if (!vlan && !eth)
2698                                 return rte_flow_error_set(error, EINVAL,
2699                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2700                                                 (void *)items->type,
2701                                                 "neither eth nor vlan"
2702                                                 " header found");
2703                         if (vlan && !vlan->eth_proto)
2704                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2705                         else if (eth && !eth->ether_type)
2706                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2707                         if (!ipv6->vtc_flow)
2708                                 ipv6->vtc_flow =
2709                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2710                         if (!ipv6->hop_limits)
2711                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2712                         break;
2713                 case RTE_FLOW_ITEM_TYPE_UDP:
2714                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2715                         if (!ipv4 && !ipv6)
2716                                 return rte_flow_error_set(error, EINVAL,
2717                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2718                                                 (void *)items->type,
2719                                                 "ip header not found");
2720                         if (ipv4 && !ipv4->next_proto_id)
2721                                 ipv4->next_proto_id = IPPROTO_UDP;
2722                         else if (ipv6 && !ipv6->proto)
2723                                 ipv6->proto = IPPROTO_UDP;
2724                         break;
2725                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2726                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2727                         if (!udp)
2728                                 return rte_flow_error_set(error, EINVAL,
2729                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2730                                                 (void *)items->type,
2731                                                 "udp header not found");
2732                         if (!udp->dst_port)
2733                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2734                         if (!vxlan->vx_flags)
2735                                 vxlan->vx_flags =
2736                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2737                         break;
2738                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2739                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2740                         if (!udp)
2741                                 return rte_flow_error_set(error, EINVAL,
2742                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2743                                                 (void *)items->type,
2744                                                 "udp header not found");
2745                         if (!vxlan_gpe->proto)
2746                                 return rte_flow_error_set(error, EINVAL,
2747                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2748                                                 (void *)items->type,
2749                                                 "next protocol not found");
2750                         if (!udp->dst_port)
2751                                 udp->dst_port =
2752                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2753                         if (!vxlan_gpe->vx_flags)
2754                                 vxlan_gpe->vx_flags =
2755                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2756                         break;
2757                 case RTE_FLOW_ITEM_TYPE_GRE:
2758                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2759                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2760                         if (!gre->proto)
2761                                 return rte_flow_error_set(error, EINVAL,
2762                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2763                                                 (void *)items->type,
2764                                                 "next protocol not found");
2765                         if (!ipv4 && !ipv6)
2766                                 return rte_flow_error_set(error, EINVAL,
2767                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2768                                                 (void *)items->type,
2769                                                 "ip header not found");
2770                         if (ipv4 && !ipv4->next_proto_id)
2771                                 ipv4->next_proto_id = IPPROTO_GRE;
2772                         else if (ipv6 && !ipv6->proto)
2773                                 ipv6->proto = IPPROTO_GRE;
2774                         break;
2775                 case RTE_FLOW_ITEM_TYPE_VOID:
2776                         break;
2777                 default:
2778                         return rte_flow_error_set(error, EINVAL,
2779                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2780                                                   (void *)items->type,
2781                                                   "unsupported item type");
2782                         break;
2783                 }
2784                 temp_size += len;
2785         }
2786         *size = temp_size;
2787         return 0;
2788 }
2789
2790 static int
2791 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2792 {
2793         struct rte_ether_hdr *eth = NULL;
2794         struct rte_vlan_hdr *vlan = NULL;
2795         struct rte_ipv6_hdr *ipv6 = NULL;
2796         struct rte_udp_hdr *udp = NULL;
2797         char *next_hdr;
2798         uint16_t proto;
2799
2800         eth = (struct rte_ether_hdr *)data;
2801         next_hdr = (char *)(eth + 1);
2802         proto = RTE_BE16(eth->ether_type);
2803
2804         /* VLAN skipping */
2805         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2806                 vlan = (struct rte_vlan_hdr *)next_hdr;
2807                 proto = RTE_BE16(vlan->eth_proto);
2808                 next_hdr += sizeof(struct rte_vlan_hdr);
2809         }
2810
2811         /* HW calculates IPv4 csum. no need to proceed */
2812         if (proto == RTE_ETHER_TYPE_IPV4)
2813                 return 0;
2814
2815         /* non IPv4/IPv6 header. not supported */
2816         if (proto != RTE_ETHER_TYPE_IPV6) {
2817                 return rte_flow_error_set(error, ENOTSUP,
2818                                           RTE_FLOW_ERROR_TYPE_ACTION,
2819                                           NULL, "Cannot offload non IPv4/IPv6");
2820         }
2821
2822         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2823
2824         /* ignore non UDP */
2825         if (ipv6->proto != IPPROTO_UDP)
2826                 return 0;
2827
2828         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2829         udp->dgram_cksum = 0;
2830
2831         return 0;
2832 }
2833
2834 /**
2835  * Convert L2 encap action to DV specification.
2836  *
2837  * @param[in] dev
2838  *   Pointer to rte_eth_dev structure.
2839  * @param[in] action
2840  *   Pointer to action structure.
2841  * @param[in, out] dev_flow
2842  *   Pointer to the mlx5_flow.
2843  * @param[in] transfer
2844  *   Mark if the flow is E-Switch flow.
2845  * @param[out] error
2846  *   Pointer to the error structure.
2847  *
2848  * @return
2849  *   0 on success, a negative errno value otherwise and rte_errno is set.
2850  */
2851 static int
2852 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2853                                const struct rte_flow_action *action,
2854                                struct mlx5_flow *dev_flow,
2855                                uint8_t transfer,
2856                                struct rte_flow_error *error)
2857 {
2858         const struct rte_flow_item *encap_data;
2859         const struct rte_flow_action_raw_encap *raw_encap_data;
2860         struct mlx5_flow_dv_encap_decap_resource res = {
2861                 .reformat_type =
2862                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2863                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2864                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2865         };
2866
2867         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2868                 raw_encap_data =
2869                         (const struct rte_flow_action_raw_encap *)action->conf;
2870                 res.size = raw_encap_data->size;
2871                 memcpy(res.buf, raw_encap_data->data, res.size);
2872         } else {
2873                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2874                         encap_data =
2875                                 ((const struct rte_flow_action_vxlan_encap *)
2876                                                 action->conf)->definition;
2877                 else
2878                         encap_data =
2879                                 ((const struct rte_flow_action_nvgre_encap *)
2880                                                 action->conf)->definition;
2881                 if (flow_dv_convert_encap_data(encap_data, res.buf,
2882                                                &res.size, error))
2883                         return -rte_errno;
2884         }
2885         if (flow_dv_zero_encap_udp_csum(res.buf, error))
2886                 return -rte_errno;
2887         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2888                 return rte_flow_error_set(error, EINVAL,
2889                                           RTE_FLOW_ERROR_TYPE_ACTION,
2890                                           NULL, "can't create L2 encap action");
2891         return 0;
2892 }
2893
2894 /**
2895  * Convert L2 decap action to DV specification.
2896  *
2897  * @param[in] dev
2898  *   Pointer to rte_eth_dev structure.
2899  * @param[in, out] dev_flow
2900  *   Pointer to the mlx5_flow.
2901  * @param[in] transfer
2902  *   Mark if the flow is E-Switch flow.
2903  * @param[out] error
2904  *   Pointer to the error structure.
2905  *
2906  * @return
2907  *   0 on success, a negative errno value otherwise and rte_errno is set.
2908  */
2909 static int
2910 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2911                                struct mlx5_flow *dev_flow,
2912                                uint8_t transfer,
2913                                struct rte_flow_error *error)
2914 {
2915         struct mlx5_flow_dv_encap_decap_resource res = {
2916                 .size = 0,
2917                 .reformat_type =
2918                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2919                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2920                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2921         };
2922
2923         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2924                 return rte_flow_error_set(error, EINVAL,
2925                                           RTE_FLOW_ERROR_TYPE_ACTION,
2926                                           NULL, "can't create L2 decap action");
2927         return 0;
2928 }
2929
2930 /**
2931  * Convert raw decap/encap (L3 tunnel) action to DV specification.
2932  *
2933  * @param[in] dev
2934  *   Pointer to rte_eth_dev structure.
2935  * @param[in] action
2936  *   Pointer to action structure.
2937  * @param[in, out] dev_flow
2938  *   Pointer to the mlx5_flow.
2939  * @param[in] attr
2940  *   Pointer to the flow attributes.
2941  * @param[out] error
2942  *   Pointer to the error structure.
2943  *
2944  * @return
2945  *   0 on success, a negative errno value otherwise and rte_errno is set.
2946  */
2947 static int
2948 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2949                                 const struct rte_flow_action *action,
2950                                 struct mlx5_flow *dev_flow,
2951                                 const struct rte_flow_attr *attr,
2952                                 struct rte_flow_error *error)
2953 {
2954         const struct rte_flow_action_raw_encap *encap_data;
2955         struct mlx5_flow_dv_encap_decap_resource res;
2956
2957         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2958         res.size = encap_data->size;
2959         memcpy(res.buf, encap_data->data, res.size);
2960         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2961                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2962                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2963         if (attr->transfer)
2964                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2965         else
2966                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2967                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2968         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2969                 return rte_flow_error_set(error, EINVAL,
2970                                           RTE_FLOW_ERROR_TYPE_ACTION,
2971                                           NULL, "can't create encap action");
2972         return 0;
2973 }
2974
2975 /**
2976  * Create action push VLAN.
2977  *
2978  * @param[in] dev
2979  *   Pointer to rte_eth_dev structure.
2980  * @param[in] attr
2981  *   Pointer to the flow attributes.
2982  * @param[in] vlan
2983  *   Pointer to the vlan to push to the Ethernet header.
2984  * @param[in, out] dev_flow
2985  *   Pointer to the mlx5_flow.
2986  * @param[out] error
2987  *   Pointer to the error structure.
2988  *
2989  * @return
2990  *   0 on success, a negative errno value otherwise and rte_errno is set.
2991  */
2992 static int
2993 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2994                                 const struct rte_flow_attr *attr,
2995                                 const struct rte_vlan_hdr *vlan,
2996                                 struct mlx5_flow *dev_flow,
2997                                 struct rte_flow_error *error)
2998 {
2999         struct mlx5_flow_dv_push_vlan_action_resource res;
3000
3001         res.vlan_tag =
3002                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3003                                  vlan->vlan_tci);
3004         if (attr->transfer)
3005                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3006         else
3007                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3008                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3009         return flow_dv_push_vlan_action_resource_register
3010                                             (dev, &res, dev_flow, error);
3011 }
3012
3013 /**
3014  * Validate the modify-header actions.
3015  *
3016  * @param[in] action_flags
3017  *   Holds the actions detected until now.
3018  * @param[in] action
3019  *   Pointer to the modify action.
3020  * @param[out] error
3021  *   Pointer to error structure.
3022  *
3023  * @return
3024  *   0 on success, a negative errno value otherwise and rte_errno is set.
3025  */
3026 static int
3027 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3028                                    const struct rte_flow_action *action,
3029                                    struct rte_flow_error *error)
3030 {
3031         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3032                 return rte_flow_error_set(error, EINVAL,
3033                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3034                                           NULL, "action configuration not set");
3035         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3036                 return rte_flow_error_set(error, EINVAL,
3037                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3038                                           "can't have encap action before"
3039                                           " modify action");
3040         return 0;
3041 }
3042
3043 /**
3044  * Validate the modify-header MAC address actions.
3045  *
3046  * @param[in] action_flags
3047  *   Holds the actions detected until now.
3048  * @param[in] action
3049  *   Pointer to the modify action.
3050  * @param[in] item_flags
3051  *   Holds the items detected.
3052  * @param[out] error
3053  *   Pointer to error structure.
3054  *
3055  * @return
3056  *   0 on success, a negative errno value otherwise and rte_errno is set.
3057  */
3058 static int
3059 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3060                                    const struct rte_flow_action *action,
3061                                    const uint64_t item_flags,
3062                                    struct rte_flow_error *error)
3063 {
3064         int ret = 0;
3065
3066         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3067         if (!ret) {
3068                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3069                         return rte_flow_error_set(error, EINVAL,
3070                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3071                                                   NULL,
3072                                                   "no L2 item in pattern");
3073         }
3074         return ret;
3075 }
3076
3077 /**
3078  * Validate the modify-header IPv4 address actions.
3079  *
3080  * @param[in] action_flags
3081  *   Holds the actions detected until now.
3082  * @param[in] action
3083  *   Pointer to the modify action.
3084  * @param[in] item_flags
3085  *   Holds the items detected.
3086  * @param[out] error
3087  *   Pointer to error structure.
3088  *
3089  * @return
3090  *   0 on success, a negative errno value otherwise and rte_errno is set.
3091  */
3092 static int
3093 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3094                                     const struct rte_flow_action *action,
3095                                     const uint64_t item_flags,
3096                                     struct rte_flow_error *error)
3097 {
3098         int ret = 0;
3099
3100         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3101         if (!ret) {
3102                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3103                         return rte_flow_error_set(error, EINVAL,
3104                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3105                                                   NULL,
3106                                                   "no ipv4 item in pattern");
3107         }
3108         return ret;
3109 }
3110
3111 /**
3112  * Validate the modify-header IPv6 address actions.
3113  *
3114  * @param[in] action_flags
3115  *   Holds the actions detected until now.
3116  * @param[in] action
3117  *   Pointer to the modify action.
3118  * @param[in] item_flags
3119  *   Holds the items detected.
3120  * @param[out] error
3121  *   Pointer to error structure.
3122  *
3123  * @return
3124  *   0 on success, a negative errno value otherwise and rte_errno is set.
3125  */
3126 static int
3127 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3128                                     const struct rte_flow_action *action,
3129                                     const uint64_t item_flags,
3130                                     struct rte_flow_error *error)
3131 {
3132         int ret = 0;
3133
3134         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3135         if (!ret) {
3136                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3137                         return rte_flow_error_set(error, EINVAL,
3138                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3139                                                   NULL,
3140                                                   "no ipv6 item in pattern");
3141         }
3142         return ret;
3143 }
3144
3145 /**
3146  * Validate the modify-header TP actions.
3147  *
3148  * @param[in] action_flags
3149  *   Holds the actions detected until now.
3150  * @param[in] action
3151  *   Pointer to the modify action.
3152  * @param[in] item_flags
3153  *   Holds the items detected.
3154  * @param[out] error
3155  *   Pointer to error structure.
3156  *
3157  * @return
3158  *   0 on success, a negative errno value otherwise and rte_errno is set.
3159  */
3160 static int
3161 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3162                                   const struct rte_flow_action *action,
3163                                   const uint64_t item_flags,
3164                                   struct rte_flow_error *error)
3165 {
3166         int ret = 0;
3167
3168         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3169         if (!ret) {
3170                 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3171                         return rte_flow_error_set(error, EINVAL,
3172                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3173                                                   NULL, "no transport layer "
3174                                                   "in pattern");
3175         }
3176         return ret;
3177 }
3178
3179 /**
3180  * Validate the modify-header actions of increment/decrement
3181  * TCP Sequence-number.
3182  *
3183  * @param[in] action_flags
3184  *   Holds the actions detected until now.
3185  * @param[in] action
3186  *   Pointer to the modify action.
3187  * @param[in] item_flags
3188  *   Holds the items detected.
3189  * @param[out] error
3190  *   Pointer to error structure.
3191  *
3192  * @return
3193  *   0 on success, a negative errno value otherwise and rte_errno is set.
3194  */
3195 static int
3196 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3197                                        const struct rte_flow_action *action,
3198                                        const uint64_t item_flags,
3199                                        struct rte_flow_error *error)
3200 {
3201         int ret = 0;
3202
3203         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3204         if (!ret) {
3205                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3206                         return rte_flow_error_set(error, EINVAL,
3207                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3208                                                   NULL, "no TCP item in"
3209                                                   " pattern");
3210                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3211                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3212                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3213                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3214                         return rte_flow_error_set(error, EINVAL,
3215                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3216                                                   NULL,
3217                                                   "cannot decrease and increase"
3218                                                   " TCP sequence number"
3219                                                   " at the same time");
3220         }
3221         return ret;
3222 }
3223
3224 /**
3225  * Validate the modify-header actions of increment/decrement
3226  * TCP Acknowledgment number.
3227  *
3228  * @param[in] action_flags
3229  *   Holds the actions detected until now.
3230  * @param[in] action
3231  *   Pointer to the modify action.
3232  * @param[in] item_flags
3233  *   Holds the items detected.
3234  * @param[out] error
3235  *   Pointer to error structure.
3236  *
3237  * @return
3238  *   0 on success, a negative errno value otherwise and rte_errno is set.
3239  */
3240 static int
3241 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3242                                        const struct rte_flow_action *action,
3243                                        const uint64_t item_flags,
3244                                        struct rte_flow_error *error)
3245 {
3246         int ret = 0;
3247
3248         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3249         if (!ret) {
3250                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3251                         return rte_flow_error_set(error, EINVAL,
3252                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3253                                                   NULL, "no TCP item in"
3254                                                   " pattern");
3255                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3256                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3257                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3258                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3259                         return rte_flow_error_set(error, EINVAL,
3260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3261                                                   NULL,
3262                                                   "cannot decrease and increase"
3263                                                   " TCP acknowledgment number"
3264                                                   " at the same time");
3265         }
3266         return ret;
3267 }
3268
3269 /**
3270  * Validate the modify-header TTL actions.
3271  *
3272  * @param[in] action_flags
3273  *   Holds the actions detected until now.
3274  * @param[in] action
3275  *   Pointer to the modify action.
3276  * @param[in] item_flags
3277  *   Holds the items detected.
3278  * @param[out] error
3279  *   Pointer to error structure.
3280  *
3281  * @return
3282  *   0 on success, a negative errno value otherwise and rte_errno is set.
3283  */
3284 static int
3285 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3286                                    const struct rte_flow_action *action,
3287                                    const uint64_t item_flags,
3288                                    struct rte_flow_error *error)
3289 {
3290         int ret = 0;
3291
3292         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3293         if (!ret) {
3294                 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3295                         return rte_flow_error_set(error, EINVAL,
3296                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3297                                                   NULL,
3298                                                   "no IP protocol in pattern");
3299         }
3300         return ret;
3301 }
3302
3303 /**
3304  * Validate jump action.
3305  *
3306  * @param[in] action
3307  *   Pointer to the jump action.
3308  * @param[in] action_flags
3309  *   Holds the actions detected until now.
3310  * @param[in] attributes
3311  *   Pointer to flow attributes
3312  * @param[in] external
3313  *   Action belongs to flow rule created by request external to PMD.
3314  * @param[out] error
3315  *   Pointer to error structure.
3316  *
3317  * @return
3318  *   0 on success, a negative errno value otherwise and rte_errno is set.
3319  */
3320 static int
3321 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3322                              uint64_t action_flags,
3323                              const struct rte_flow_attr *attributes,
3324                              bool external, struct rte_flow_error *error)
3325 {
3326         uint32_t target_group, table;
3327         int ret = 0;
3328
3329         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3330                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3331                 return rte_flow_error_set(error, EINVAL,
3332                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3333                                           "can't have 2 fate actions in"
3334                                           " same flow");
3335         if (action_flags & MLX5_FLOW_ACTION_METER)
3336                 return rte_flow_error_set(error, ENOTSUP,
3337                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3338                                           "jump with meter not support");
3339         if (!action->conf)
3340                 return rte_flow_error_set(error, EINVAL,
3341                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3342                                           NULL, "action configuration not set");
3343         target_group =
3344                 ((const struct rte_flow_action_jump *)action->conf)->group;
3345         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3346                                        true, &table, error);
3347         if (ret)
3348                 return ret;
3349         if (attributes->group == target_group)
3350                 return rte_flow_error_set(error, EINVAL,
3351                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3352                                           "target group must be other than"
3353                                           " the current flow group");
3354         return 0;
3355 }
3356
3357 /*
3358  * Validate the port_id action.
3359  *
3360  * @param[in] dev
3361  *   Pointer to rte_eth_dev structure.
3362  * @param[in] action_flags
3363  *   Bit-fields that holds the actions detected until now.
3364  * @param[in] action
3365  *   Port_id RTE action structure.
3366  * @param[in] attr
3367  *   Attributes of flow that includes this action.
3368  * @param[out] error
3369  *   Pointer to error structure.
3370  *
3371  * @return
3372  *   0 on success, a negative errno value otherwise and rte_errno is set.
3373  */
3374 static int
3375 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3376                                 uint64_t action_flags,
3377                                 const struct rte_flow_action *action,
3378                                 const struct rte_flow_attr *attr,
3379                                 struct rte_flow_error *error)
3380 {
3381         const struct rte_flow_action_port_id *port_id;
3382         struct mlx5_priv *act_priv;
3383         struct mlx5_priv *dev_priv;
3384         uint16_t port;
3385
3386         if (!attr->transfer)
3387                 return rte_flow_error_set(error, ENOTSUP,
3388                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3389                                           NULL,
3390                                           "port id action is valid in transfer"
3391                                           " mode only");
3392         if (!action || !action->conf)
3393                 return rte_flow_error_set(error, ENOTSUP,
3394                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3395                                           NULL,
3396                                           "port id action parameters must be"
3397                                           " specified");
3398         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3399                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3400                 return rte_flow_error_set(error, EINVAL,
3401                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3402                                           "can have only one fate actions in"
3403                                           " a flow");
3404         dev_priv = mlx5_dev_to_eswitch_info(dev);
3405         if (!dev_priv)
3406                 return rte_flow_error_set(error, rte_errno,
3407                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3408                                           NULL,
3409                                           "failed to obtain E-Switch info");
3410         port_id = action->conf;
3411         port = port_id->original ? dev->data->port_id : port_id->id;
3412         act_priv = mlx5_port_to_eswitch_info(port, false);
3413         if (!act_priv)
3414                 return rte_flow_error_set
3415                                 (error, rte_errno,
3416                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3417                                  "failed to obtain E-Switch port id for port");
3418         if (act_priv->domain_id != dev_priv->domain_id)
3419                 return rte_flow_error_set
3420                                 (error, EINVAL,
3421                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3422                                  "port does not belong to"
3423                                  " E-Switch being configured");
3424         return 0;
3425 }
3426
3427 /**
3428  * Get the maximum number of modify header actions.
3429  *
3430  * @param dev
3431  *   Pointer to rte_eth_dev structure.
3432  * @param flags
3433  *   Flags bits to check if root level.
3434  *
3435  * @return
3436  *   Max number of modify header actions device can support.
3437  */
3438 static unsigned int
3439 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3440 {
3441         /*
3442          * There's no way to directly query the max cap. Although it has to be
3443          * acquried by iterative trial, it is a safe assumption that more
3444          * actions are supported by FW if extensive metadata register is
3445          * supported. (Only in the root table)
3446          */
3447         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3448                 return MLX5_MAX_MODIFY_NUM;
3449         else
3450                 return mlx5_flow_ext_mreg_supported(dev) ?
3451                                         MLX5_ROOT_TBL_MODIFY_NUM :
3452                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3453 }
3454
3455 /**
3456  * Validate the meter action.
3457  *
3458  * @param[in] dev
3459  *   Pointer to rte_eth_dev structure.
3460  * @param[in] action_flags
3461  *   Bit-fields that holds the actions detected until now.
3462  * @param[in] action
3463  *   Pointer to the meter action.
3464  * @param[in] attr
3465  *   Attributes of flow that includes this action.
3466  * @param[out] error
3467  *   Pointer to error structure.
3468  *
3469  * @return
3470  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3471  */
3472 static int
3473 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3474                                 uint64_t action_flags,
3475                                 const struct rte_flow_action *action,
3476                                 const struct rte_flow_attr *attr,
3477                                 struct rte_flow_error *error)
3478 {
3479         struct mlx5_priv *priv = dev->data->dev_private;
3480         const struct rte_flow_action_meter *am = action->conf;
3481         struct mlx5_flow_meter *fm;
3482
3483         if (!am)
3484                 return rte_flow_error_set(error, EINVAL,
3485                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3486                                           "meter action conf is NULL");
3487
3488         if (action_flags & MLX5_FLOW_ACTION_METER)
3489                 return rte_flow_error_set(error, ENOTSUP,
3490                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3491                                           "meter chaining not support");
3492         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3493                 return rte_flow_error_set(error, ENOTSUP,
3494                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3495                                           "meter with jump not support");
3496         if (!priv->mtr_en)
3497                 return rte_flow_error_set(error, ENOTSUP,
3498                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3499                                           NULL,
3500                                           "meter action not supported");
3501         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3502         if (!fm)
3503                 return rte_flow_error_set(error, EINVAL,
3504                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3505                                           "Meter not found");
3506         if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3507               (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3508               (!fm->attr.egress && !attr->egress && attr->ingress))))
3509                 return rte_flow_error_set(error, EINVAL,
3510                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3511                                           "Flow attributes are either invalid "
3512                                           "or have a conflict with current "
3513                                           "meter attributes");
3514         return 0;
3515 }
3516
3517 /**
3518  * Validate the modify-header IPv4 DSCP actions.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3534                                          const struct rte_flow_action *action,
3535                                          const uint64_t item_flags,
3536                                          struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539
3540         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3541         if (!ret) {
3542                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3543                         return rte_flow_error_set(error, EINVAL,
3544                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3545                                                   NULL,
3546                                                   "no ipv4 item in pattern");
3547         }
3548         return ret;
3549 }
3550
3551 /**
3552  * Validate the modify-header IPv6 DSCP actions.
3553  *
3554  * @param[in] action_flags
3555  *   Holds the actions detected until now.
3556  * @param[in] action
3557  *   Pointer to the modify action.
3558  * @param[in] item_flags
3559  *   Holds the items detected.
3560  * @param[out] error
3561  *   Pointer to error structure.
3562  *
3563  * @return
3564  *   0 on success, a negative errno value otherwise and rte_errno is set.
3565  */
3566 static int
3567 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3568                                          const struct rte_flow_action *action,
3569                                          const uint64_t item_flags,
3570                                          struct rte_flow_error *error)
3571 {
3572         int ret = 0;
3573
3574         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3575         if (!ret) {
3576                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3577                         return rte_flow_error_set(error, EINVAL,
3578                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3579                                                   NULL,
3580                                                   "no ipv6 item in pattern");
3581         }
3582         return ret;
3583 }
3584
3585 /**
3586  * Find existing modify-header resource or create and register a new one.
3587  *
3588  * @param dev[in, out]
3589  *   Pointer to rte_eth_dev structure.
3590  * @param[in, out] resource
3591  *   Pointer to modify-header resource.
3592  * @parm[in, out] dev_flow
3593  *   Pointer to the dev_flow.
3594  * @param[out] error
3595  *   pointer to error structure.
3596  *
3597  * @return
3598  *   0 on success otherwise -errno and errno is set.
3599  */
3600 static int
3601 flow_dv_modify_hdr_resource_register
3602                         (struct rte_eth_dev *dev,
3603                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3604                          struct mlx5_flow *dev_flow,
3605                          struct rte_flow_error *error)
3606 {
3607         struct mlx5_priv *priv = dev->data->dev_private;
3608         struct mlx5_ibv_shared *sh = priv->sh;
3609         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3610         struct mlx5dv_dr_domain *ns;
3611         uint32_t actions_len;
3612
3613         resource->flags =
3614                 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3615         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3616                                     resource->flags))
3617                 return rte_flow_error_set(error, EOVERFLOW,
3618                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3619                                           "too many modify header items");
3620         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621                 ns = sh->fdb_domain;
3622         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3623                 ns = sh->tx_domain;
3624         else
3625                 ns = sh->rx_domain;
3626         /* Lookup a matching resource from cache. */
3627         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3628         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3629                 if (resource->ft_type == cache_resource->ft_type &&
3630                     resource->actions_num == cache_resource->actions_num &&
3631                     resource->flags == cache_resource->flags &&
3632                     !memcmp((const void *)resource->actions,
3633                             (const void *)cache_resource->actions,
3634                             actions_len)) {
3635                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3636                                 (void *)cache_resource,
3637                                 rte_atomic32_read(&cache_resource->refcnt));
3638                         rte_atomic32_inc(&cache_resource->refcnt);
3639                         dev_flow->dv.modify_hdr = cache_resource;
3640                         return 0;
3641                 }
3642         }
3643         /* Register new modify-header resource. */
3644         cache_resource = rte_calloc(__func__, 1,
3645                                     sizeof(*cache_resource) + actions_len, 0);
3646         if (!cache_resource)
3647                 return rte_flow_error_set(error, ENOMEM,
3648                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3649                                           "cannot allocate resource memory");
3650         *cache_resource = *resource;
3651         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3652         cache_resource->verbs_action =
3653                 mlx5_glue->dv_create_flow_action_modify_header
3654                                         (sh->ctx, cache_resource->ft_type, ns,
3655                                          cache_resource->flags, actions_len,
3656                                          (uint64_t *)cache_resource->actions);
3657         if (!cache_resource->verbs_action) {
3658                 rte_free(cache_resource);
3659                 return rte_flow_error_set(error, ENOMEM,
3660                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3661                                           NULL, "cannot create action");
3662         }
3663         rte_atomic32_init(&cache_resource->refcnt);
3664         rte_atomic32_inc(&cache_resource->refcnt);
3665         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3666         dev_flow->dv.modify_hdr = cache_resource;
3667         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3668                 (void *)cache_resource,
3669                 rte_atomic32_read(&cache_resource->refcnt));
3670         return 0;
3671 }
3672
3673 #define MLX5_CNT_CONTAINER_RESIZE 64
3674
3675 /**
3676  * Get or create a flow counter.
3677  *
3678  * @param[in] dev
3679  *   Pointer to the Ethernet device structure.
3680  * @param[in] shared
3681  *   Indicate if this counter is shared with other flows.
3682  * @param[in] id
3683  *   Counter identifier.
3684  *
3685  * @return
3686  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3687  */
3688 static struct mlx5_flow_counter *
3689 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3690                                uint32_t id)
3691 {
3692         struct mlx5_priv *priv = dev->data->dev_private;
3693         struct mlx5_flow_counter *cnt = NULL;
3694         struct mlx5_devx_obj *dcs = NULL;
3695
3696         if (!priv->config.devx) {
3697                 rte_errno = ENOTSUP;
3698                 return NULL;
3699         }
3700         if (shared) {
3701                 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3702                         if (cnt->shared && cnt->id == id) {
3703                                 cnt->ref_cnt++;
3704                                 return cnt;
3705                         }
3706                 }
3707         }
3708         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3709         if (!dcs)
3710                 return NULL;
3711         cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3712         if (!cnt) {
3713                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3714                 rte_errno = ENOMEM;
3715                 return NULL;
3716         }
3717         struct mlx5_flow_counter tmpl = {
3718                 .shared = shared,
3719                 .ref_cnt = 1,
3720                 .id = id,
3721                 .dcs = dcs,
3722         };
3723         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3724         if (!tmpl.action) {
3725                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3726                 rte_errno = errno;
3727                 rte_free(cnt);
3728                 return NULL;
3729         }
3730         *cnt = tmpl;
3731         TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3732         return cnt;
3733 }
3734
3735 /**
3736  * Release a flow counter.
3737  *
3738  * @param[in] dev
3739  *   Pointer to the Ethernet device structure.
3740  * @param[in] counter
3741  *   Pointer to the counter handler.
3742  */
3743 static void
3744 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3745                                  struct mlx5_flow_counter *counter)
3746 {
3747         struct mlx5_priv *priv = dev->data->dev_private;
3748
3749         if (!counter)
3750                 return;
3751         if (--counter->ref_cnt == 0) {
3752                 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3753                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3754                 rte_free(counter);
3755         }
3756 }
3757
3758 /**
3759  * Query a devx flow counter.
3760  *
3761  * @param[in] dev
3762  *   Pointer to the Ethernet device structure.
3763  * @param[in] cnt
3764  *   Pointer to the flow counter.
3765  * @param[out] pkts
3766  *   The statistics value of packets.
3767  * @param[out] bytes
3768  *   The statistics value of bytes.
3769  *
3770  * @return
3771  *   0 on success, otherwise a negative errno value and rte_errno is set.
3772  */
3773 static inline int
3774 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3775                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3776                      uint64_t *bytes)
3777 {
3778         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3779                                                 0, NULL, NULL, 0);
3780 }
3781
3782 /**
3783  * Get a pool by a counter.
3784  *
3785  * @param[in] cnt
3786  *   Pointer to the counter.
3787  *
3788  * @return
3789  *   The counter pool.
3790  */
3791 static struct mlx5_flow_counter_pool *
3792 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3793 {
3794         if (!cnt->batch) {
3795                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3796                 return (struct mlx5_flow_counter_pool *)cnt - 1;
3797         }
3798         return cnt->pool;
3799 }
3800
3801 /**
3802  * Get a pool by devx counter ID.
3803  *
3804  * @param[in] cont
3805  *   Pointer to the counter container.
3806  * @param[in] id
3807  *   The counter devx ID.
3808  *
3809  * @return
3810  *   The counter pool pointer if exists, NULL otherwise,
3811  */
3812 static struct mlx5_flow_counter_pool *
3813 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3814 {
3815         struct mlx5_flow_counter_pool *pool;
3816
3817         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3818                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3819                                 MLX5_COUNTERS_PER_POOL;
3820
3821                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3822                         return pool;
3823         };
3824         return NULL;
3825 }
3826
3827 /**
3828  * Allocate a new memory for the counter values wrapped by all the needed
3829  * management.
3830  *
3831  * @param[in] dev
3832  *   Pointer to the Ethernet device structure.
3833  * @param[in] raws_n
3834  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3835  *
3836  * @return
3837  *   The new memory management pointer on success, otherwise NULL and rte_errno
3838  *   is set.
3839  */
3840 static struct mlx5_counter_stats_mem_mng *
3841 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3842 {
3843         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3844                                         (dev->data->dev_private))->sh;
3845         struct mlx5_devx_mkey_attr mkey_attr;
3846         struct mlx5_counter_stats_mem_mng *mem_mng;
3847         volatile struct flow_counter_stats *raw_data;
3848         int size = (sizeof(struct flow_counter_stats) *
3849                         MLX5_COUNTERS_PER_POOL +
3850                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3851                         sizeof(struct mlx5_counter_stats_mem_mng);
3852         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3853         int i;
3854
3855         if (!mem) {
3856                 rte_errno = ENOMEM;
3857                 return NULL;
3858         }
3859         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3860         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3861         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3862                                                  IBV_ACCESS_LOCAL_WRITE);
3863         if (!mem_mng->umem) {
3864                 rte_errno = errno;
3865                 rte_free(mem);
3866                 return NULL;
3867         }
3868         mkey_attr.addr = (uintptr_t)mem;
3869         mkey_attr.size = size;
3870         mkey_attr.umem_id = mem_mng->umem->umem_id;
3871         mkey_attr.pd = sh->pdn;
3872         mkey_attr.log_entity_size = 0;
3873         mkey_attr.pg_access = 0;
3874         mkey_attr.klm_array = NULL;
3875         mkey_attr.klm_num = 0;
3876         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3877         if (!mem_mng->dm) {
3878                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3879                 rte_errno = errno;
3880                 rte_free(mem);
3881                 return NULL;
3882         }
3883         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3884         raw_data = (volatile struct flow_counter_stats *)mem;
3885         for (i = 0; i < raws_n; ++i) {
3886                 mem_mng->raws[i].mem_mng = mem_mng;
3887                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3888         }
3889         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3890         return mem_mng;
3891 }
3892
3893 /**
3894  * Resize a counter container.
3895  *
3896  * @param[in] dev
3897  *   Pointer to the Ethernet device structure.
3898  * @param[in] batch
3899  *   Whether the pool is for counter that was allocated by batch command.
3900  *
3901  * @return
3902  *   The new container pointer on success, otherwise NULL and rte_errno is set.
3903  */
3904 static struct mlx5_pools_container *
3905 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3906 {
3907         struct mlx5_priv *priv = dev->data->dev_private;
3908         struct mlx5_pools_container *cont =
3909                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3910         struct mlx5_pools_container *new_cont =
3911                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3912         struct mlx5_counter_stats_mem_mng *mem_mng;
3913         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3914         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3915         int i;
3916
3917         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3918                 /* The last resize still hasn't detected by the host thread. */
3919                 rte_errno = EAGAIN;
3920                 return NULL;
3921         }
3922         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3923         if (!new_cont->pools) {
3924                 rte_errno = ENOMEM;
3925                 return NULL;
3926         }
3927         if (cont->n)
3928                 memcpy(new_cont->pools, cont->pools, cont->n *
3929                        sizeof(struct mlx5_flow_counter_pool *));
3930         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3931                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3932         if (!mem_mng) {
3933                 rte_free(new_cont->pools);
3934                 return NULL;
3935         }
3936         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3937                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3938                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3939                                  i, next);
3940         new_cont->n = resize;
3941         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3942         TAILQ_INIT(&new_cont->pool_list);
3943         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3944         new_cont->init_mem_mng = mem_mng;
3945         rte_cio_wmb();
3946          /* Flip the master container. */
3947         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3948         return new_cont;
3949 }
3950
3951 /**
3952  * Query a devx flow counter.
3953  *
3954  * @param[in] dev
3955  *   Pointer to the Ethernet device structure.
3956  * @param[in] cnt
3957  *   Pointer to the flow counter.
3958  * @param[out] pkts
3959  *   The statistics value of packets.
3960  * @param[out] bytes
3961  *   The statistics value of bytes.
3962  *
3963  * @return
3964  *   0 on success, otherwise a negative errno value and rte_errno is set.
3965  */
3966 static inline int
3967 _flow_dv_query_count(struct rte_eth_dev *dev,
3968                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3969                      uint64_t *bytes)
3970 {
3971         struct mlx5_priv *priv = dev->data->dev_private;
3972         struct mlx5_flow_counter_pool *pool =
3973                         flow_dv_counter_pool_get(cnt);
3974         int offset = cnt - &pool->counters_raw[0];
3975
3976         if (priv->counter_fallback)
3977                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3978
3979         rte_spinlock_lock(&pool->sl);
3980         /*
3981          * The single counters allocation may allocate smaller ID than the
3982          * current allocated in parallel to the host reading.
3983          * In this case the new counter values must be reported as 0.
3984          */
3985         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3986                 *pkts = 0;
3987                 *bytes = 0;
3988         } else {
3989                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3990                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3991         }
3992         rte_spinlock_unlock(&pool->sl);
3993         return 0;
3994 }
3995
3996 /**
3997  * Create and initialize a new counter pool.
3998  *
3999  * @param[in] dev
4000  *   Pointer to the Ethernet device structure.
4001  * @param[out] dcs
4002  *   The devX counter handle.
4003  * @param[in] batch
4004  *   Whether the pool is for counter that was allocated by batch command.
4005  *
4006  * @return
4007  *   A new pool pointer on success, NULL otherwise and rte_errno is set.
4008  */
4009 static struct mlx5_flow_counter_pool *
4010 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4011                     uint32_t batch)
4012 {
4013         struct mlx5_priv *priv = dev->data->dev_private;
4014         struct mlx5_flow_counter_pool *pool;
4015         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4016                                                                0);
4017         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4018         uint32_t size;
4019
4020         if (cont->n == n_valid) {
4021                 cont = flow_dv_container_resize(dev, batch);
4022                 if (!cont)
4023                         return NULL;
4024         }
4025         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4026                         sizeof(struct mlx5_flow_counter);
4027         pool = rte_calloc(__func__, 1, size, 0);
4028         if (!pool) {
4029                 rte_errno = ENOMEM;
4030                 return NULL;
4031         }
4032         pool->min_dcs = dcs;
4033         pool->raw = cont->init_mem_mng->raws + n_valid %
4034                                                      MLX5_CNT_CONTAINER_RESIZE;
4035         pool->raw_hw = NULL;
4036         rte_spinlock_init(&pool->sl);
4037         /*
4038          * The generation of the new allocated counters in this pool is 0, 2 in
4039          * the pool generation makes all the counters valid for allocation.
4040          */
4041         rte_atomic64_set(&pool->query_gen, 0x2);
4042         TAILQ_INIT(&pool->counters);
4043         TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4044         cont->pools[n_valid] = pool;
4045         /* Pool initialization must be updated before host thread access. */
4046         rte_cio_wmb();
4047         rte_atomic16_add(&cont->n_valid, 1);
4048         return pool;
4049 }
4050
4051 /**
4052  * Prepare a new counter and/or a new counter pool.
4053  *
4054  * @param[in] dev
4055  *   Pointer to the Ethernet device structure.
4056  * @param[out] cnt_free
4057  *   Where to put the pointer of a new counter.
4058  * @param[in] batch
4059  *   Whether the pool is for counter that was allocated by batch command.
4060  *
4061  * @return
4062  *   The free counter pool pointer and @p cnt_free is set on success,
4063  *   NULL otherwise and rte_errno is set.
4064  */
4065 static struct mlx5_flow_counter_pool *
4066 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4067                              struct mlx5_flow_counter **cnt_free,
4068                              uint32_t batch)
4069 {
4070         struct mlx5_priv *priv = dev->data->dev_private;
4071         struct mlx5_flow_counter_pool *pool;
4072         struct mlx5_devx_obj *dcs = NULL;
4073         struct mlx5_flow_counter *cnt;
4074         uint32_t i;
4075
4076         if (!batch) {
4077                 /* bulk_bitmap must be 0 for single counter allocation. */
4078                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4079                 if (!dcs)
4080                         return NULL;
4081                 pool = flow_dv_find_pool_by_id
4082                         (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4083                 if (!pool) {
4084                         pool = flow_dv_pool_create(dev, dcs, batch);
4085                         if (!pool) {
4086                                 mlx5_devx_cmd_destroy(dcs);
4087                                 return NULL;
4088                         }
4089                 } else if (dcs->id < pool->min_dcs->id) {
4090                         rte_atomic64_set(&pool->a64_dcs,
4091                                          (int64_t)(uintptr_t)dcs);
4092                 }
4093                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4094                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4095                 cnt->dcs = dcs;
4096                 *cnt_free = cnt;
4097                 return pool;
4098         }
4099         /* bulk_bitmap is in 128 counters units. */
4100         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4101                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4102         if (!dcs) {
4103                 rte_errno = ENODATA;
4104                 return NULL;
4105         }
4106         pool = flow_dv_pool_create(dev, dcs, batch);
4107         if (!pool) {
4108                 mlx5_devx_cmd_destroy(dcs);
4109                 return NULL;
4110         }
4111         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4112                 cnt = &pool->counters_raw[i];
4113                 cnt->pool = pool;
4114                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4115         }
4116         *cnt_free = &pool->counters_raw[0];
4117         return pool;
4118 }
4119
4120 /**
4121  * Search for existed shared counter.
4122  *
4123  * @param[in] cont
4124  *   Pointer to the relevant counter pool container.
4125  * @param[in] id
4126  *   The shared counter ID to search.
4127  *
4128  * @return
4129  *   NULL if not existed, otherwise pointer to the shared counter.
4130  */
4131 static struct mlx5_flow_counter *
4132 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4133                               uint32_t id)
4134 {
4135         static struct mlx5_flow_counter *cnt;
4136         struct mlx5_flow_counter_pool *pool;
4137         int i;
4138
4139         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4140                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4141                         cnt = &pool->counters_raw[i];
4142                         if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4143                                 return cnt;
4144                 }
4145         }
4146         return NULL;
4147 }
4148
4149 /**
4150  * Allocate a flow counter.
4151  *
4152  * @param[in] dev
4153  *   Pointer to the Ethernet device structure.
4154  * @param[in] shared
4155  *   Indicate if this counter is shared with other flows.
4156  * @param[in] id
4157  *   Counter identifier.
4158  * @param[in] group
4159  *   Counter flow group.
4160  *
4161  * @return
4162  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
4163  */
4164 static struct mlx5_flow_counter *
4165 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4166                       uint16_t group)
4167 {
4168         struct mlx5_priv *priv = dev->data->dev_private;
4169         struct mlx5_flow_counter_pool *pool = NULL;
4170         struct mlx5_flow_counter *cnt_free = NULL;
4171         /*
4172          * Currently group 0 flow counter cannot be assigned to a flow if it is
4173          * not the first one in the batch counter allocation, so it is better
4174          * to allocate counters one by one for these flows in a separate
4175          * container.
4176          * A counter can be shared between different groups so need to take
4177          * shared counters from the single container.
4178          */
4179         uint32_t batch = (group && !shared) ? 1 : 0;
4180         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4181                                                                0);
4182
4183         if (priv->counter_fallback)
4184                 return flow_dv_counter_alloc_fallback(dev, shared, id);
4185         if (!priv->config.devx) {
4186                 rte_errno = ENOTSUP;
4187                 return NULL;
4188         }
4189         if (shared) {
4190                 cnt_free = flow_dv_counter_shared_search(cont, id);
4191                 if (cnt_free) {
4192                         if (cnt_free->ref_cnt + 1 == 0) {
4193                                 rte_errno = E2BIG;
4194                                 return NULL;
4195                         }
4196                         cnt_free->ref_cnt++;
4197                         return cnt_free;
4198                 }
4199         }
4200         /* Pools which has a free counters are in the start. */
4201         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4202                 /*
4203                  * The free counter reset values must be updated between the
4204                  * counter release to the counter allocation, so, at least one
4205                  * query must be done in this time. ensure it by saving the
4206                  * query generation in the release time.
4207                  * The free list is sorted according to the generation - so if
4208                  * the first one is not updated, all the others are not
4209                  * updated too.
4210                  */
4211                 cnt_free = TAILQ_FIRST(&pool->counters);
4212                 if (cnt_free && cnt_free->query_gen + 1 <
4213                     rte_atomic64_read(&pool->query_gen))
4214                         break;
4215                 cnt_free = NULL;
4216         }
4217         if (!cnt_free) {
4218                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4219                 if (!pool)
4220                         return NULL;
4221         }
4222         cnt_free->batch = batch;
4223         /* Create a DV counter action only in the first time usage. */
4224         if (!cnt_free->action) {
4225                 uint16_t offset;
4226                 struct mlx5_devx_obj *dcs;
4227
4228                 if (batch) {
4229                         offset = cnt_free - &pool->counters_raw[0];
4230                         dcs = pool->min_dcs;
4231                 } else {
4232                         offset = 0;
4233                         dcs = cnt_free->dcs;
4234                 }
4235                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4236                                         (dcs->obj, offset);
4237                 if (!cnt_free->action) {
4238                         rte_errno = errno;
4239                         return NULL;
4240                 }
4241         }
4242         /* Update the counter reset values. */
4243         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4244                                  &cnt_free->bytes))
4245                 return NULL;
4246         cnt_free->shared = shared;
4247         cnt_free->ref_cnt = 1;
4248         cnt_free->id = id;
4249         if (!priv->sh->cmng.query_thread_on)
4250                 /* Start the asynchronous batch query by the host thread. */
4251                 mlx5_set_query_alarm(priv->sh);
4252         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4253         if (TAILQ_EMPTY(&pool->counters)) {
4254                 /* Move the pool to the end of the container pool list. */
4255                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4256                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4257         }
4258         return cnt_free;
4259 }
4260
4261 /**
4262  * Release a flow counter.
4263  *
4264  * @param[in] dev
4265  *   Pointer to the Ethernet device structure.
4266  * @param[in] counter
4267  *   Pointer to the counter handler.
4268  */
4269 static void
4270 flow_dv_counter_release(struct rte_eth_dev *dev,
4271                         struct mlx5_flow_counter *counter)
4272 {
4273         struct mlx5_priv *priv = dev->data->dev_private;
4274
4275         if (!counter)
4276                 return;
4277         if (priv->counter_fallback) {
4278                 flow_dv_counter_release_fallback(dev, counter);
4279                 return;
4280         }
4281         if (--counter->ref_cnt == 0) {
4282                 struct mlx5_flow_counter_pool *pool =
4283                                 flow_dv_counter_pool_get(counter);
4284
4285                 /* Put the counter in the end - the last updated one. */
4286                 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4287                 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4288         }
4289 }
4290
4291 /**
4292  * Verify the @p attributes will be correctly understood by the NIC and store
4293  * them in the @p flow if everything is correct.
4294  *
4295  * @param[in] dev
4296  *   Pointer to dev struct.
4297  * @param[in] attributes
4298  *   Pointer to flow attributes
4299  * @param[in] external
4300  *   This flow rule is created by request external to PMD.
4301  * @param[out] error
4302  *   Pointer to error structure.
4303  *
4304  * @return
4305  *   0 on success, a negative errno value otherwise and rte_errno is set.
4306  */
4307 static int
4308 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4309                             const struct rte_flow_attr *attributes,
4310                             bool external __rte_unused,
4311                             struct rte_flow_error *error)
4312 {
4313         struct mlx5_priv *priv = dev->data->dev_private;
4314         uint32_t priority_max = priv->config.flow_prio - 1;
4315
4316 #ifndef HAVE_MLX5DV_DR
4317         if (attributes->group)
4318                 return rte_flow_error_set(error, ENOTSUP,
4319                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4320                                           NULL,
4321                                           "groups are not supported");
4322 #else
4323         uint32_t table;
4324         int ret;
4325
4326         ret = mlx5_flow_group_to_table(attributes, external,
4327                                        attributes->group, !!priv->fdb_def_rule,
4328                                        &table, error);
4329         if (ret)
4330                 return ret;
4331 #endif
4332         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4333             attributes->priority >= priority_max)
4334                 return rte_flow_error_set(error, ENOTSUP,
4335                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4336                                           NULL,
4337                                           "priority out of range");
4338         if (attributes->transfer) {
4339                 if (!priv->config.dv_esw_en)
4340                         return rte_flow_error_set
4341                                 (error, ENOTSUP,
4342                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4343                                  "E-Switch dr is not supported");
4344                 if (!(priv->representor || priv->master))
4345                         return rte_flow_error_set
4346                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4347                                  NULL, "E-Switch configuration can only be"
4348                                  " done by a master or a representor device");
4349                 if (attributes->egress)
4350                         return rte_flow_error_set
4351                                 (error, ENOTSUP,
4352                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4353                                  "egress is not supported");
4354         }
4355         if (!(attributes->egress ^ attributes->ingress))
4356                 return rte_flow_error_set(error, ENOTSUP,
4357                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4358                                           "must specify exactly one of "
4359                                           "ingress or egress");
4360         return 0;
4361 }
4362
4363 /**
4364  * Internal validation function. For validating both actions and items.
4365  *
4366  * @param[in] dev
4367  *   Pointer to the rte_eth_dev structure.
4368  * @param[in] attr
4369  *   Pointer to the flow attributes.
4370  * @param[in] items
4371  *   Pointer to the list of items.
4372  * @param[in] actions
4373  *   Pointer to the list of actions.
4374  * @param[in] external
4375  *   This flow rule is created by request external to PMD.
4376  * @param[out] error
4377  *   Pointer to the error structure.
4378  *
4379  * @return
4380  *   0 on success, a negative errno value otherwise and rte_errno is set.
4381  */
4382 static int
4383 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4384                  const struct rte_flow_item items[],
4385                  const struct rte_flow_action actions[],
4386                  bool external, struct rte_flow_error *error)
4387 {
4388         int ret;
4389         uint64_t action_flags = 0;
4390         uint64_t item_flags = 0;
4391         uint64_t last_item = 0;
4392         uint8_t next_protocol = 0xff;
4393         uint16_t ether_type = 0;
4394         int actions_n = 0;
4395         uint8_t item_ipv6_proto = 0;
4396         const struct rte_flow_item *gre_item = NULL;
4397         const struct rte_flow_action_raw_decap *decap;
4398         const struct rte_flow_action_raw_encap *encap;
4399         const struct rte_flow_action_rss *rss;
4400         struct rte_flow_item_tcp nic_tcp_mask = {
4401                 .hdr = {
4402                         .tcp_flags = 0xFF,
4403                         .src_port = RTE_BE16(UINT16_MAX),
4404                         .dst_port = RTE_BE16(UINT16_MAX),
4405                 }
4406         };
4407         struct mlx5_priv *priv = dev->data->dev_private;
4408         struct mlx5_dev_config *dev_conf = &priv->config;
4409         uint16_t queue_index = 0xFFFF;
4410
4411         if (items == NULL)
4412                 return -1;
4413         ret = flow_dv_validate_attributes(dev, attr, external, error);
4414         if (ret < 0)
4415                 return ret;
4416         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4417                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4418                 int type = items->type;
4419
4420                 switch (type) {
4421                 case RTE_FLOW_ITEM_TYPE_VOID:
4422                         break;
4423                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4424                         ret = flow_dv_validate_item_port_id
4425                                         (dev, items, attr, item_flags, error);
4426                         if (ret < 0)
4427                                 return ret;
4428                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4429                         break;
4430                 case RTE_FLOW_ITEM_TYPE_ETH:
4431                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4432                                                           error);
4433                         if (ret < 0)
4434                                 return ret;
4435                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4436                                              MLX5_FLOW_LAYER_OUTER_L2;
4437                         if (items->mask != NULL && items->spec != NULL) {
4438                                 ether_type =
4439                                         ((const struct rte_flow_item_eth *)
4440                                          items->spec)->type;
4441                                 ether_type &=
4442                                         ((const struct rte_flow_item_eth *)
4443                                          items->mask)->type;
4444                                 ether_type = rte_be_to_cpu_16(ether_type);
4445                         } else {
4446                                 ether_type = 0;
4447                         }
4448                         break;
4449                 case RTE_FLOW_ITEM_TYPE_VLAN:
4450                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4451                                                            dev, error);
4452                         if (ret < 0)
4453                                 return ret;
4454                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4455                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4456                         if (items->mask != NULL && items->spec != NULL) {
4457                                 ether_type =
4458                                         ((const struct rte_flow_item_vlan *)
4459                                          items->spec)->inner_type;
4460                                 ether_type &=
4461                                         ((const struct rte_flow_item_vlan *)
4462                                          items->mask)->inner_type;
4463                                 ether_type = rte_be_to_cpu_16(ether_type);
4464                         } else {
4465                                 ether_type = 0;
4466                         }
4467                         break;
4468                 case RTE_FLOW_ITEM_TYPE_IPV4:
4469                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4470                                                   &item_flags, &tunnel);
4471                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4472                                                            last_item,
4473                                                            ether_type, NULL,
4474                                                            error);
4475                         if (ret < 0)
4476                                 return ret;
4477                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4478                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4479                         if (items->mask != NULL &&
4480                             ((const struct rte_flow_item_ipv4 *)
4481                              items->mask)->hdr.next_proto_id) {
4482                                 next_protocol =
4483                                         ((const struct rte_flow_item_ipv4 *)
4484                                          (items->spec))->hdr.next_proto_id;
4485                                 next_protocol &=
4486                                         ((const struct rte_flow_item_ipv4 *)
4487                                          (items->mask))->hdr.next_proto_id;
4488                         } else {
4489                                 /* Reset for inner layer. */
4490                                 next_protocol = 0xff;
4491                         }
4492                         break;
4493                 case RTE_FLOW_ITEM_TYPE_IPV6:
4494                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4495                                                   &item_flags, &tunnel);
4496                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4497                                                            last_item,
4498                                                            ether_type, NULL,
4499                                                            error);
4500                         if (ret < 0)
4501                                 return ret;
4502                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4503                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4504                         if (items->mask != NULL &&
4505                             ((const struct rte_flow_item_ipv6 *)
4506                              items->mask)->hdr.proto) {
4507                                 item_ipv6_proto =
4508                                         ((const struct rte_flow_item_ipv6 *)
4509                                          items->spec)->hdr.proto;
4510                                 next_protocol =
4511                                         ((const struct rte_flow_item_ipv6 *)
4512                                          items->spec)->hdr.proto;
4513                                 next_protocol &=
4514                                         ((const struct rte_flow_item_ipv6 *)
4515                                          items->mask)->hdr.proto;
4516                         } else {
4517                                 /* Reset for inner layer. */
4518                                 next_protocol = 0xff;
4519                         }
4520                         break;
4521                 case RTE_FLOW_ITEM_TYPE_TCP:
4522                         ret = mlx5_flow_validate_item_tcp
4523                                                 (items, item_flags,
4524                                                  next_protocol,
4525                                                  &nic_tcp_mask,
4526                                                  error);
4527                         if (ret < 0)
4528                                 return ret;
4529                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4530                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4531                         break;
4532                 case RTE_FLOW_ITEM_TYPE_UDP:
4533                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4534                                                           next_protocol,
4535                                                           error);
4536                         if (ret < 0)
4537                                 return ret;
4538                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4539                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4540                         break;
4541                 case RTE_FLOW_ITEM_TYPE_GRE:
4542                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4543                                                           next_protocol, error);
4544                         if (ret < 0)
4545                                 return ret;
4546                         gre_item = items;
4547                         last_item = MLX5_FLOW_LAYER_GRE;
4548                         break;
4549                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4550                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4551                                                             next_protocol,
4552                                                             error);
4553                         if (ret < 0)
4554                                 return ret;
4555                         last_item = MLX5_FLOW_LAYER_NVGRE;
4556                         break;
4557                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4558                         ret = mlx5_flow_validate_item_gre_key
4559                                 (items, item_flags, gre_item, error);
4560                         if (ret < 0)
4561                                 return ret;
4562                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4563                         break;
4564                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4565                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4566                                                             error);
4567                         if (ret < 0)
4568                                 return ret;
4569                         last_item = MLX5_FLOW_LAYER_VXLAN;
4570                         break;
4571                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4572                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4573                                                                 item_flags, dev,
4574                                                                 error);
4575                         if (ret < 0)
4576                                 return ret;
4577                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4578                         break;
4579                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4580                         ret = mlx5_flow_validate_item_geneve(items,
4581                                                              item_flags, dev,
4582                                                              error);
4583                         if (ret < 0)
4584                                 return ret;
4585                         last_item = MLX5_FLOW_LAYER_GENEVE;
4586                         break;
4587                 case RTE_FLOW_ITEM_TYPE_MPLS:
4588                         ret = mlx5_flow_validate_item_mpls(dev, items,
4589                                                            item_flags,
4590                                                            last_item, error);
4591                         if (ret < 0)
4592                                 return ret;
4593                         last_item = MLX5_FLOW_LAYER_MPLS;
4594                         break;
4595
4596                 case RTE_FLOW_ITEM_TYPE_MARK:
4597                         ret = flow_dv_validate_item_mark(dev, items, attr,
4598                                                          error);
4599                         if (ret < 0)
4600                                 return ret;
4601                         last_item = MLX5_FLOW_ITEM_MARK;
4602                         break;
4603                 case RTE_FLOW_ITEM_TYPE_META:
4604                         ret = flow_dv_validate_item_meta(dev, items, attr,
4605                                                          error);
4606                         if (ret < 0)
4607                                 return ret;
4608                         last_item = MLX5_FLOW_ITEM_METADATA;
4609                         break;
4610                 case RTE_FLOW_ITEM_TYPE_ICMP:
4611                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4612                                                            next_protocol,
4613                                                            error);
4614                         if (ret < 0)
4615                                 return ret;
4616                         last_item = MLX5_FLOW_LAYER_ICMP;
4617                         break;
4618                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4619                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4620                                                             next_protocol,
4621                                                             error);
4622                         if (ret < 0)
4623                                 return ret;
4624                         last_item = MLX5_FLOW_LAYER_ICMP6;
4625                         break;
4626                 case RTE_FLOW_ITEM_TYPE_TAG:
4627                         ret = flow_dv_validate_item_tag(dev, items,
4628                                                         attr, error);
4629                         if (ret < 0)
4630                                 return ret;
4631                         last_item = MLX5_FLOW_ITEM_TAG;
4632                         break;
4633                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4634                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4635                         break;
4636                 case RTE_FLOW_ITEM_TYPE_GTP:
4637                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4638                                                         error);
4639                         if (ret < 0)
4640                                 return ret;
4641                         last_item = MLX5_FLOW_LAYER_GTP;
4642                         break;
4643                 default:
4644                         return rte_flow_error_set(error, ENOTSUP,
4645                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4646                                                   NULL, "item not supported");
4647                 }
4648                 item_flags |= last_item;
4649         }
4650         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4651                 int type = actions->type;
4652                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4653                         return rte_flow_error_set(error, ENOTSUP,
4654                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4655                                                   actions, "too many actions");
4656                 switch (type) {
4657                 case RTE_FLOW_ACTION_TYPE_VOID:
4658                         break;
4659                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4660                         ret = flow_dv_validate_action_port_id(dev,
4661                                                               action_flags,
4662                                                               actions,
4663                                                               attr,
4664                                                               error);
4665                         if (ret)
4666                                 return ret;
4667                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4668                         ++actions_n;
4669                         break;
4670                 case RTE_FLOW_ACTION_TYPE_FLAG:
4671                         ret = flow_dv_validate_action_flag(dev, action_flags,
4672                                                            attr, error);
4673                         if (ret < 0)
4674                                 return ret;
4675                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4676                                 /* Count all modify-header actions as one. */
4677                                 if (!(action_flags &
4678                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4679                                         ++actions_n;
4680                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4681                                                 MLX5_FLOW_ACTION_MARK_EXT;
4682                         } else {
4683                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4684                                 ++actions_n;
4685                         }
4686                         break;
4687                 case RTE_FLOW_ACTION_TYPE_MARK:
4688                         ret = flow_dv_validate_action_mark(dev, actions,
4689                                                            action_flags,
4690                                                            attr, error);
4691                         if (ret < 0)
4692                                 return ret;
4693                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4694                                 /* Count all modify-header actions as one. */
4695                                 if (!(action_flags &
4696                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4697                                         ++actions_n;
4698                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4699                                                 MLX5_FLOW_ACTION_MARK_EXT;
4700                         } else {
4701                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4702                                 ++actions_n;
4703                         }
4704                         break;
4705                 case RTE_FLOW_ACTION_TYPE_SET_META:
4706                         ret = flow_dv_validate_action_set_meta(dev, actions,
4707                                                                action_flags,
4708                                                                attr, error);
4709                         if (ret < 0)
4710                                 return ret;
4711                         /* Count all modify-header actions as one action. */
4712                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4713                                 ++actions_n;
4714                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4715                         break;
4716                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4717                         ret = flow_dv_validate_action_set_tag(dev, actions,
4718                                                               action_flags,
4719                                                               attr, error);
4720                         if (ret < 0)
4721                                 return ret;
4722                         /* Count all modify-header actions as one action. */
4723                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4724                                 ++actions_n;
4725                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4726                         break;
4727                 case RTE_FLOW_ACTION_TYPE_DROP:
4728                         ret = mlx5_flow_validate_action_drop(action_flags,
4729                                                              attr, error);
4730                         if (ret < 0)
4731                                 return ret;
4732                         action_flags |= MLX5_FLOW_ACTION_DROP;
4733                         ++actions_n;
4734                         break;
4735                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4736                         ret = mlx5_flow_validate_action_queue(actions,
4737                                                               action_flags, dev,
4738                                                               attr, error);
4739                         if (ret < 0)
4740                                 return ret;
4741                         queue_index = ((const struct rte_flow_action_queue *)
4742                                                         (actions->conf))->index;
4743                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4744                         ++actions_n;
4745                         break;
4746                 case RTE_FLOW_ACTION_TYPE_RSS:
4747                         rss = actions->conf;
4748                         ret = mlx5_flow_validate_action_rss(actions,
4749                                                             action_flags, dev,
4750                                                             attr, item_flags,
4751                                                             error);
4752                         if (ret < 0)
4753                                 return ret;
4754                         if (rss != NULL && rss->queue_num)
4755                                 queue_index = rss->queue[0];
4756                         action_flags |= MLX5_FLOW_ACTION_RSS;
4757                         ++actions_n;
4758                         break;
4759                 case RTE_FLOW_ACTION_TYPE_COUNT:
4760                         ret = flow_dv_validate_action_count(dev, error);
4761                         if (ret < 0)
4762                                 return ret;
4763                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4764                         ++actions_n;
4765                         break;
4766                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4767                         if (flow_dv_validate_action_pop_vlan(dev,
4768                                                              action_flags,
4769                                                              actions,
4770                                                              item_flags, attr,
4771                                                              error))
4772                                 return -rte_errno;
4773                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4774                         ++actions_n;
4775                         break;
4776                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4777                         ret = flow_dv_validate_action_push_vlan(action_flags,
4778                                                                 item_flags,
4779                                                                 actions, attr,
4780                                                                 error);
4781                         if (ret < 0)
4782                                 return ret;
4783                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4784                         ++actions_n;
4785                         break;
4786                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4787                         ret = flow_dv_validate_action_set_vlan_pcp
4788                                                 (action_flags, actions, error);
4789                         if (ret < 0)
4790                                 return ret;
4791                         /* Count PCP with push_vlan command. */
4792                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4793                         break;
4794                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4795                         ret = flow_dv_validate_action_set_vlan_vid
4796                                                 (item_flags, action_flags,
4797                                                  actions, error);
4798                         if (ret < 0)
4799                                 return ret;
4800                         /* Count VID with push_vlan command. */
4801                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4802                         break;
4803                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4804                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4805                         ret = flow_dv_validate_action_l2_encap(action_flags,
4806                                                                actions, error);
4807                         if (ret < 0)
4808                                 return ret;
4809                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
4810                         ++actions_n;
4811                         break;
4812                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4813                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4814                         ret = flow_dv_validate_action_decap(action_flags, attr,
4815                                                             error);
4816                         if (ret < 0)
4817                                 return ret;
4818                         action_flags |= MLX5_FLOW_ACTION_DECAP;
4819                         ++actions_n;
4820                         break;
4821                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4822                         ret = flow_dv_validate_action_raw_encap_decap
4823                                 (NULL, actions->conf, attr, &action_flags,
4824                                  &actions_n, error);
4825                         if (ret < 0)
4826                                 return ret;
4827                         break;
4828                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4829                         decap = actions->conf;
4830                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
4831                                 ;
4832                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4833                                 encap = NULL;
4834                                 actions--;
4835                         } else {
4836                                 encap = actions->conf;
4837                         }
4838                         ret = flow_dv_validate_action_raw_encap_decap
4839                                            (decap ? decap : &empty_decap, encap,
4840                                             attr, &action_flags, &actions_n,
4841                                             error);
4842                         if (ret < 0)
4843                                 return ret;
4844                         break;
4845                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4846                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4847                         ret = flow_dv_validate_action_modify_mac(action_flags,
4848                                                                  actions,
4849                                                                  item_flags,
4850                                                                  error);
4851                         if (ret < 0)
4852                                 return ret;
4853                         /* Count all modify-header actions as one action. */
4854                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4855                                 ++actions_n;
4856                         action_flags |= actions->type ==
4857                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4858                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
4859                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
4860                         break;
4861
4862                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4863                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4864                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
4865                                                                   actions,
4866                                                                   item_flags,
4867                                                                   error);
4868                         if (ret < 0)
4869                                 return ret;
4870                         /* Count all modify-header actions as one action. */
4871                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4872                                 ++actions_n;
4873                         action_flags |= actions->type ==
4874                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4875                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4876                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
4877                         break;
4878                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4879                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4880                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
4881                                                                   actions,
4882                                                                   item_flags,
4883                                                                   error);
4884                         if (ret < 0)
4885                                 return ret;
4886                         if (item_ipv6_proto == IPPROTO_ICMPV6)
4887                                 return rte_flow_error_set(error, ENOTSUP,
4888                                         RTE_FLOW_ERROR_TYPE_ACTION,
4889                                         actions,
4890                                         "Can't change header "
4891                                         "with ICMPv6 proto");
4892                         /* Count all modify-header actions as one action. */
4893                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4894                                 ++actions_n;
4895                         action_flags |= actions->type ==
4896                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4897                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4898                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
4899                         break;
4900                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4901                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4902                         ret = flow_dv_validate_action_modify_tp(action_flags,
4903                                                                 actions,
4904                                                                 item_flags,
4905                                                                 error);
4906                         if (ret < 0)
4907                                 return ret;
4908                         /* Count all modify-header actions as one action. */
4909                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4910                                 ++actions_n;
4911                         action_flags |= actions->type ==
4912                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4913                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
4914                                                 MLX5_FLOW_ACTION_SET_TP_DST;
4915                         break;
4916                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4917                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4918                         ret = flow_dv_validate_action_modify_ttl(action_flags,
4919                                                                  actions,
4920                                                                  item_flags,
4921                                                                  error);
4922                         if (ret < 0)
4923                                 return ret;
4924                         /* Count all modify-header actions as one action. */
4925                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4926                                 ++actions_n;
4927                         action_flags |= actions->type ==
4928                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
4929                                                 MLX5_FLOW_ACTION_SET_TTL :
4930                                                 MLX5_FLOW_ACTION_DEC_TTL;
4931                         break;
4932                 case RTE_FLOW_ACTION_TYPE_JUMP:
4933                         ret = flow_dv_validate_action_jump(actions,
4934                                                            action_flags,
4935                                                            attr, external,
4936                                                            error);
4937                         if (ret)
4938                                 return ret;
4939                         ++actions_n;
4940                         action_flags |= MLX5_FLOW_ACTION_JUMP;
4941                         break;
4942                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4943                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4944                         ret = flow_dv_validate_action_modify_tcp_seq
4945                                                                 (action_flags,
4946                                                                  actions,
4947                                                                  item_flags,
4948                                                                  error);
4949                         if (ret < 0)
4950                                 return ret;
4951                         /* Count all modify-header actions as one action. */
4952                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4953                                 ++actions_n;
4954                         action_flags |= actions->type ==
4955                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4956                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4957                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4958                         break;
4959                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4960                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4961                         ret = flow_dv_validate_action_modify_tcp_ack
4962                                                                 (action_flags,
4963                                                                  actions,
4964                                                                  item_flags,
4965                                                                  error);
4966                         if (ret < 0)
4967                                 return ret;
4968                         /* Count all modify-header actions as one action. */
4969                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4970                                 ++actions_n;
4971                         action_flags |= actions->type ==
4972                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4973                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
4974                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4975                         break;
4976                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4977                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4978                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4979                         break;
4980                 case RTE_FLOW_ACTION_TYPE_METER:
4981                         ret = mlx5_flow_validate_action_meter(dev,
4982                                                               action_flags,
4983                                                               actions, attr,
4984                                                               error);
4985                         if (ret < 0)
4986                                 return ret;
4987                         action_flags |= MLX5_FLOW_ACTION_METER;
4988                         ++actions_n;
4989                         break;
4990                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
4991                         ret = flow_dv_validate_action_modify_ipv4_dscp
4992                                                          (action_flags,
4993                                                           actions,
4994                                                           item_flags,
4995                                                           error);
4996                         if (ret < 0)
4997                                 return ret;
4998                         /* Count all modify-header actions as one action. */
4999                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5000                                 ++actions_n;
5001                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5002                         break;
5003                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5004                         ret = flow_dv_validate_action_modify_ipv6_dscp
5005                                                                 (action_flags,
5006                                                                  actions,
5007                                                                  item_flags,
5008                                                                  error);
5009                         if (ret < 0)
5010                                 return ret;
5011                         /* Count all modify-header actions as one action. */
5012                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5013                                 ++actions_n;
5014                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5015                         break;
5016                 default:
5017                         return rte_flow_error_set(error, ENOTSUP,
5018                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5019                                                   actions,
5020                                                   "action not supported");
5021                 }
5022         }
5023         /*
5024          * Validate the drop action mutual exclusion with other actions.
5025          * Drop action is mutually-exclusive with any other action, except for
5026          * Count action.
5027          */
5028         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5029             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5030                 return rte_flow_error_set(error, EINVAL,
5031                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5032                                           "Drop action is mutually-exclusive "
5033                                           "with any other action, except for "
5034                                           "Count action");
5035         /* Eswitch has few restrictions on using items and actions */
5036         if (attr->transfer) {
5037                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5038                     action_flags & MLX5_FLOW_ACTION_FLAG)
5039                         return rte_flow_error_set(error, ENOTSUP,
5040                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5041                                                   NULL,
5042                                                   "unsupported action FLAG");
5043                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5044                     action_flags & MLX5_FLOW_ACTION_MARK)
5045                         return rte_flow_error_set(error, ENOTSUP,
5046                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5047                                                   NULL,
5048                                                   "unsupported action MARK");
5049                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5050                         return rte_flow_error_set(error, ENOTSUP,
5051                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5052                                                   NULL,
5053                                                   "unsupported action QUEUE");
5054                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5055                         return rte_flow_error_set(error, ENOTSUP,
5056                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5057                                                   NULL,
5058                                                   "unsupported action RSS");
5059                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5060                         return rte_flow_error_set(error, EINVAL,
5061                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5062                                                   actions,
5063                                                   "no fate action is found");
5064         } else {
5065                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5066                         return rte_flow_error_set(error, EINVAL,
5067                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5068                                                   actions,
5069                                                   "no fate action is found");
5070         }
5071         /* Continue validation for Xcap actions.*/
5072         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5073             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5074                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5075                     MLX5_FLOW_XCAP_ACTIONS)
5076                         return rte_flow_error_set(error, ENOTSUP,
5077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5078                                                   NULL, "encap and decap "
5079                                                   "combination aren't supported");
5080                 if (!attr->transfer && attr->ingress && (action_flags &
5081                                                         MLX5_FLOW_ACTION_ENCAP))
5082                         return rte_flow_error_set(error, ENOTSUP,
5083                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5084                                                   NULL, "encap is not supported"
5085                                                   " for ingress traffic");
5086         }
5087         return 0;
5088 }
5089
5090 /**
5091  * Internal preparation function. Allocates the DV flow size,
5092  * this size is constant.
5093  *
5094  * @param[in] attr
5095  *   Pointer to the flow attributes.
5096  * @param[in] items
5097  *   Pointer to the list of items.
5098  * @param[in] actions
5099  *   Pointer to the list of actions.
5100  * @param[out] error
5101  *   Pointer to the error structure.
5102  *
5103  * @return
5104  *   Pointer to mlx5_flow object on success,
5105  *   otherwise NULL and rte_errno is set.
5106  */
5107 static struct mlx5_flow *
5108 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5109                 const struct rte_flow_item items[] __rte_unused,
5110                 const struct rte_flow_action actions[] __rte_unused,
5111                 struct rte_flow_error *error)
5112 {
5113         size_t size = sizeof(struct mlx5_flow);
5114         struct mlx5_flow *dev_flow;
5115
5116         dev_flow = rte_calloc(__func__, 1, size, 0);
5117         if (!dev_flow) {
5118                 rte_flow_error_set(error, ENOMEM,
5119                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5120                                    "not enough memory to create flow");
5121                 return NULL;
5122         }
5123         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5124         dev_flow->ingress = attr->ingress;
5125         dev_flow->transfer = attr->transfer;
5126         return dev_flow;
5127 }
5128
5129 #ifdef RTE_LIBRTE_MLX5_DEBUG
5130 /**
5131  * Sanity check for match mask and value. Similar to check_valid_spec() in
5132  * kernel driver. If unmasked bit is present in value, it returns failure.
5133  *
5134  * @param match_mask
5135  *   pointer to match mask buffer.
5136  * @param match_value
5137  *   pointer to match value buffer.
5138  *
5139  * @return
5140  *   0 if valid, -EINVAL otherwise.
5141  */
5142 static int
5143 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5144 {
5145         uint8_t *m = match_mask;
5146         uint8_t *v = match_value;
5147         unsigned int i;
5148
5149         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5150                 if (v[i] & ~m[i]) {
5151                         DRV_LOG(ERR,
5152                                 "match_value differs from match_criteria"
5153                                 " %p[%u] != %p[%u]",
5154                                 match_value, i, match_mask, i);
5155                         return -EINVAL;
5156                 }
5157         }
5158         return 0;
5159 }
5160 #endif
5161
5162 /**
5163  * Add Ethernet item to matcher and to the value.
5164  *
5165  * @param[in, out] matcher
5166  *   Flow matcher.
5167  * @param[in, out] key
5168  *   Flow matcher value.
5169  * @param[in] item
5170  *   Flow pattern to translate.
5171  * @param[in] inner
5172  *   Item is inner pattern.
5173  */
5174 static void
5175 flow_dv_translate_item_eth(void *matcher, void *key,
5176                            const struct rte_flow_item *item, int inner)
5177 {
5178         const struct rte_flow_item_eth *eth_m = item->mask;
5179         const struct rte_flow_item_eth *eth_v = item->spec;
5180         const struct rte_flow_item_eth nic_mask = {
5181                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5182                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5183                 .type = RTE_BE16(0xffff),
5184         };
5185         void *headers_m;
5186         void *headers_v;
5187         char *l24_v;
5188         unsigned int i;
5189
5190         if (!eth_v)
5191                 return;
5192         if (!eth_m)
5193                 eth_m = &nic_mask;
5194         if (inner) {
5195                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5196                                          inner_headers);
5197                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5198         } else {
5199                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5200                                          outer_headers);
5201                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5202         }
5203         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5204                &eth_m->dst, sizeof(eth_m->dst));
5205         /* The value must be in the range of the mask. */
5206         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5207         for (i = 0; i < sizeof(eth_m->dst); ++i)
5208                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5209         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5210                &eth_m->src, sizeof(eth_m->src));
5211         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5212         /* The value must be in the range of the mask. */
5213         for (i = 0; i < sizeof(eth_m->dst); ++i)
5214                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5215         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5216                  rte_be_to_cpu_16(eth_m->type));
5217         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5218         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5219         if (eth_v->type) {
5220                 /* When ethertype is present set mask for tagged VLAN. */
5221                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5222                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5223                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5224                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ))
5225                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5226                                  1);
5227         }
5228 }
5229
5230 /**
5231  * Add VLAN item to matcher and to the value.
5232  *
5233  * @param[in, out] dev_flow
5234  *   Flow descriptor.
5235  * @param[in, out] matcher
5236  *   Flow matcher.
5237  * @param[in, out] key
5238  *   Flow matcher value.
5239  * @param[in] item
5240  *   Flow pattern to translate.
5241  * @param[in] inner
5242  *   Item is inner pattern.
5243  */
5244 static void
5245 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5246                             void *matcher, void *key,
5247                             const struct rte_flow_item *item,
5248                             int inner)
5249 {
5250         const struct rte_flow_item_vlan *vlan_m = item->mask;
5251         const struct rte_flow_item_vlan *vlan_v = item->spec;
5252         void *headers_m;
5253         void *headers_v;
5254         uint16_t tci_m;
5255         uint16_t tci_v;
5256
5257         if (!vlan_v)
5258                 return;
5259         if (!vlan_m)
5260                 vlan_m = &rte_flow_item_vlan_mask;
5261         if (inner) {
5262                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5263                                          inner_headers);
5264                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5265         } else {
5266                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5267                                          outer_headers);
5268                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5269                 /*
5270                  * This is workaround, masks are not supported,
5271                  * and pre-validated.
5272                  */
5273                 dev_flow->dv.vf_vlan.tag =
5274                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5275         }
5276         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5277         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5278         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5279         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5280         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5281         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5282         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5283         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5284         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5285         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5286         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5287                  rte_be_to_cpu_16(vlan_m->inner_type));
5288         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5289                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5290 }
5291
5292 /**
5293  * Add IPV4 item to matcher and to the value.
5294  *
5295  * @param[in, out] matcher
5296  *   Flow matcher.
5297  * @param[in, out] key
5298  *   Flow matcher value.
5299  * @param[in] item
5300  *   Flow pattern to translate.
5301  * @param[in] inner
5302  *   Item is inner pattern.
5303  * @param[in] group
5304  *   The group to insert the rule.
5305  */
5306 static void
5307 flow_dv_translate_item_ipv4(void *matcher, void *key,
5308                             const struct rte_flow_item *item,
5309                             int inner, uint32_t group)
5310 {
5311         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5312         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5313         const struct rte_flow_item_ipv4 nic_mask = {
5314                 .hdr = {
5315                         .src_addr = RTE_BE32(0xffffffff),
5316                         .dst_addr = RTE_BE32(0xffffffff),
5317                         .type_of_service = 0xff,
5318                         .next_proto_id = 0xff,
5319                 },
5320         };
5321         void *headers_m;
5322         void *headers_v;
5323         char *l24_m;
5324         char *l24_v;
5325         uint8_t tos;
5326
5327         if (inner) {
5328                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5329                                          inner_headers);
5330                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5331         } else {
5332                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5333                                          outer_headers);
5334                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5335         }
5336         if (group == 0)
5337                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5338         else
5339                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5340         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5341         if (!ipv4_v)
5342                 return;
5343         if (!ipv4_m)
5344                 ipv4_m = &nic_mask;
5345         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5346                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5347         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5348                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5349         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5350         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5351         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5352                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5353         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5354                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5355         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5356         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5357         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5358         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5359                  ipv4_m->hdr.type_of_service);
5360         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5361         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5362                  ipv4_m->hdr.type_of_service >> 2);
5363         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5364         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5365                  ipv4_m->hdr.next_proto_id);
5366         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5367                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5368         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5369 }
5370
5371 /**
5372  * Add IPV6 item to matcher and to the value.
5373  *
5374  * @param[in, out] matcher
5375  *   Flow matcher.
5376  * @param[in, out] key
5377  *   Flow matcher value.
5378  * @param[in] item
5379  *   Flow pattern to translate.
5380  * @param[in] inner
5381  *   Item is inner pattern.
5382  * @param[in] group
5383  *   The group to insert the rule.
5384  */
5385 static void
5386 flow_dv_translate_item_ipv6(void *matcher, void *key,
5387                             const struct rte_flow_item *item,
5388                             int inner, uint32_t group)
5389 {
5390         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5391         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5392         const struct rte_flow_item_ipv6 nic_mask = {
5393                 .hdr = {
5394                         .src_addr =
5395                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5396                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5397                         .dst_addr =
5398                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5399                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5400                         .vtc_flow = RTE_BE32(0xffffffff),
5401                         .proto = 0xff,
5402                         .hop_limits = 0xff,
5403                 },
5404         };
5405         void *headers_m;
5406         void *headers_v;
5407         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5408         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5409         char *l24_m;
5410         char *l24_v;
5411         uint32_t vtc_m;
5412         uint32_t vtc_v;
5413         int i;
5414         int size;
5415
5416         if (inner) {
5417                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5418                                          inner_headers);
5419                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5420         } else {
5421                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5422                                          outer_headers);
5423                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5424         }
5425         if (group == 0)
5426                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5427         else
5428                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5429         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5430         if (!ipv6_v)
5431                 return;
5432         if (!ipv6_m)
5433                 ipv6_m = &nic_mask;
5434         size = sizeof(ipv6_m->hdr.dst_addr);
5435         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5436                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5437         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5438                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5439         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5440         for (i = 0; i < size; ++i)
5441                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5442         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5443                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5444         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5445                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5446         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5447         for (i = 0; i < size; ++i)
5448                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5449         /* TOS. */
5450         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5451         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5452         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5453         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5454         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5455         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5456         /* Label. */
5457         if (inner) {
5458                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5459                          vtc_m);
5460                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5461                          vtc_v);
5462         } else {
5463                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5464                          vtc_m);
5465                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5466                          vtc_v);
5467         }
5468         /* Protocol. */
5469         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5470                  ipv6_m->hdr.proto);
5471         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5472                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5473         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5474 }
5475
5476 /**
5477  * Add TCP item to matcher and to the value.
5478  *
5479  * @param[in, out] matcher
5480  *   Flow matcher.
5481  * @param[in, out] key
5482  *   Flow matcher value.
5483  * @param[in] item
5484  *   Flow pattern to translate.
5485  * @param[in] inner
5486  *   Item is inner pattern.
5487  */
5488 static void
5489 flow_dv_translate_item_tcp(void *matcher, void *key,
5490                            const struct rte_flow_item *item,
5491                            int inner)
5492 {
5493         const struct rte_flow_item_tcp *tcp_m = item->mask;
5494         const struct rte_flow_item_tcp *tcp_v = item->spec;
5495         void *headers_m;
5496         void *headers_v;
5497
5498         if (inner) {
5499                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5500                                          inner_headers);
5501                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5502         } else {
5503                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5504                                          outer_headers);
5505                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5506         }
5507         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5508         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5509         if (!tcp_v)
5510                 return;
5511         if (!tcp_m)
5512                 tcp_m = &rte_flow_item_tcp_mask;
5513         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5514                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5515         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5516                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5517         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5518                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5519         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5520                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5521         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5522                  tcp_m->hdr.tcp_flags);
5523         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5524                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5525 }
5526
5527 /**
5528  * Add UDP item to matcher and to the value.
5529  *
5530  * @param[in, out] matcher
5531  *   Flow matcher.
5532  * @param[in, out] key
5533  *   Flow matcher value.
5534  * @param[in] item
5535  *   Flow pattern to translate.
5536  * @param[in] inner
5537  *   Item is inner pattern.
5538  */
5539 static void
5540 flow_dv_translate_item_udp(void *matcher, void *key,
5541                            const struct rte_flow_item *item,
5542                            int inner)
5543 {
5544         const struct rte_flow_item_udp *udp_m = item->mask;
5545         const struct rte_flow_item_udp *udp_v = item->spec;
5546         void *headers_m;
5547         void *headers_v;
5548
5549         if (inner) {
5550                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5551                                          inner_headers);
5552                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5553         } else {
5554                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5555                                          outer_headers);
5556                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5557         }
5558         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5559         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5560         if (!udp_v)
5561                 return;
5562         if (!udp_m)
5563                 udp_m = &rte_flow_item_udp_mask;
5564         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5565                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5566         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5567                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5568         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5569                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5570         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5571                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5572 }
5573
5574 /**
5575  * Add GRE optional Key item to matcher and to the value.
5576  *
5577  * @param[in, out] matcher
5578  *   Flow matcher.
5579  * @param[in, out] key
5580  *   Flow matcher value.
5581  * @param[in] item
5582  *   Flow pattern to translate.
5583  * @param[in] inner
5584  *   Item is inner pattern.
5585  */
5586 static void
5587 flow_dv_translate_item_gre_key(void *matcher, void *key,
5588                                    const struct rte_flow_item *item)
5589 {
5590         const rte_be32_t *key_m = item->mask;
5591         const rte_be32_t *key_v = item->spec;
5592         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5593         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5594         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5595
5596         if (!key_v)
5597                 return;
5598         if (!key_m)
5599                 key_m = &gre_key_default_mask;
5600         /* GRE K bit must be on and should already be validated */
5601         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5602         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5603         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5604                  rte_be_to_cpu_32(*key_m) >> 8);
5605         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5606                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5607         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5608                  rte_be_to_cpu_32(*key_m) & 0xFF);
5609         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5610                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5611 }
5612
5613 /**
5614  * Add GRE item to matcher and to the value.
5615  *
5616  * @param[in, out] matcher
5617  *   Flow matcher.
5618  * @param[in, out] key
5619  *   Flow matcher value.
5620  * @param[in] item
5621  *   Flow pattern to translate.
5622  * @param[in] inner
5623  *   Item is inner pattern.
5624  */
5625 static void
5626 flow_dv_translate_item_gre(void *matcher, void *key,
5627                            const struct rte_flow_item *item,
5628                            int inner)
5629 {
5630         const struct rte_flow_item_gre *gre_m = item->mask;
5631         const struct rte_flow_item_gre *gre_v = item->spec;
5632         void *headers_m;
5633         void *headers_v;
5634         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5635         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5636         struct {
5637                 union {
5638                         __extension__
5639                         struct {
5640                                 uint16_t version:3;
5641                                 uint16_t rsvd0:9;
5642                                 uint16_t s_present:1;
5643                                 uint16_t k_present:1;
5644                                 uint16_t rsvd_bit1:1;
5645                                 uint16_t c_present:1;
5646                         };
5647                         uint16_t value;
5648                 };
5649         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5650
5651         if (inner) {
5652                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5653                                          inner_headers);
5654                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5655         } else {
5656                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5657                                          outer_headers);
5658                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5659         }
5660         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5661         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5662         if (!gre_v)
5663                 return;
5664         if (!gre_m)
5665                 gre_m = &rte_flow_item_gre_mask;
5666         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5667                  rte_be_to_cpu_16(gre_m->protocol));
5668         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5669                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5670         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5671         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5672         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5673                  gre_crks_rsvd0_ver_m.c_present);
5674         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5675                  gre_crks_rsvd0_ver_v.c_present &
5676                  gre_crks_rsvd0_ver_m.c_present);
5677         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5678                  gre_crks_rsvd0_ver_m.k_present);
5679         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5680                  gre_crks_rsvd0_ver_v.k_present &
5681                  gre_crks_rsvd0_ver_m.k_present);
5682         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5683                  gre_crks_rsvd0_ver_m.s_present);
5684         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5685                  gre_crks_rsvd0_ver_v.s_present &
5686                  gre_crks_rsvd0_ver_m.s_present);
5687 }
5688
5689 /**
5690  * Add NVGRE item to matcher and to the value.
5691  *
5692  * @param[in, out] matcher
5693  *   Flow matcher.
5694  * @param[in, out] key
5695  *   Flow matcher value.
5696  * @param[in] item
5697  *   Flow pattern to translate.
5698  * @param[in] inner
5699  *   Item is inner pattern.
5700  */
5701 static void
5702 flow_dv_translate_item_nvgre(void *matcher, void *key,
5703                              const struct rte_flow_item *item,
5704                              int inner)
5705 {
5706         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5707         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5708         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5709         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5710         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5711         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5712         char *gre_key_m;
5713         char *gre_key_v;
5714         int size;
5715         int i;
5716
5717         /* For NVGRE, GRE header fields must be set with defined values. */
5718         const struct rte_flow_item_gre gre_spec = {
5719                 .c_rsvd0_ver = RTE_BE16(0x2000),
5720                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5721         };
5722         const struct rte_flow_item_gre gre_mask = {
5723                 .c_rsvd0_ver = RTE_BE16(0xB000),
5724                 .protocol = RTE_BE16(UINT16_MAX),
5725         };
5726         const struct rte_flow_item gre_item = {
5727                 .spec = &gre_spec,
5728                 .mask = &gre_mask,
5729                 .last = NULL,
5730         };
5731         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5732         if (!nvgre_v)
5733                 return;
5734         if (!nvgre_m)
5735                 nvgre_m = &rte_flow_item_nvgre_mask;
5736         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5737         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5738         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5739         memcpy(gre_key_m, tni_flow_id_m, size);
5740         for (i = 0; i < size; ++i)
5741                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5742 }
5743
5744 /**
5745  * Add VXLAN item to matcher and to the value.
5746  *
5747  * @param[in, out] matcher
5748  *   Flow matcher.
5749  * @param[in, out] key
5750  *   Flow matcher value.
5751  * @param[in] item
5752  *   Flow pattern to translate.
5753  * @param[in] inner
5754  *   Item is inner pattern.
5755  */
5756 static void
5757 flow_dv_translate_item_vxlan(void *matcher, void *key,
5758                              const struct rte_flow_item *item,
5759                              int inner)
5760 {
5761         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5762         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5763         void *headers_m;
5764         void *headers_v;
5765         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5766         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5767         char *vni_m;
5768         char *vni_v;
5769         uint16_t dport;
5770         int size;
5771         int i;
5772
5773         if (inner) {
5774                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5775                                          inner_headers);
5776                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5777         } else {
5778                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5779                                          outer_headers);
5780                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5781         }
5782         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5783                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5784         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5785                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5786                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5787         }
5788         if (!vxlan_v)
5789                 return;
5790         if (!vxlan_m)
5791                 vxlan_m = &rte_flow_item_vxlan_mask;
5792         size = sizeof(vxlan_m->vni);
5793         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5794         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5795         memcpy(vni_m, vxlan_m->vni, size);
5796         for (i = 0; i < size; ++i)
5797                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5798 }
5799
5800 /**
5801  * Add VXLAN-GPE item to matcher and to the value.
5802  *
5803  * @param[in, out] matcher
5804  *   Flow matcher.
5805  * @param[in, out] key
5806  *   Flow matcher value.
5807  * @param[in] item
5808  *   Flow pattern to translate.
5809  * @param[in] inner
5810  *   Item is inner pattern.
5811  */
5812
5813 static void
5814 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5815                                  const struct rte_flow_item *item, int inner)
5816 {
5817         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5818         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5819         void *headers_m;
5820         void *headers_v;
5821         void *misc_m =
5822                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5823         void *misc_v =
5824                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5825         char *vni_m;
5826         char *vni_v;
5827         uint16_t dport;
5828         int size;
5829         int i;
5830         uint8_t flags_m = 0xff;
5831         uint8_t flags_v = 0xc;
5832
5833         if (inner) {
5834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5835                                          inner_headers);
5836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5837         } else {
5838                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5839                                          outer_headers);
5840                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5841         }
5842         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5843                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5844         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5845                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5846                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5847         }
5848         if (!vxlan_v)
5849                 return;
5850         if (!vxlan_m)
5851                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
5852         size = sizeof(vxlan_m->vni);
5853         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
5854         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
5855         memcpy(vni_m, vxlan_m->vni, size);
5856         for (i = 0; i < size; ++i)
5857                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5858         if (vxlan_m->flags) {
5859                 flags_m = vxlan_m->flags;
5860                 flags_v = vxlan_v->flags;
5861         }
5862         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
5863         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
5864         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
5865                  vxlan_m->protocol);
5866         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
5867                  vxlan_v->protocol);
5868 }
5869
5870 /**
5871  * Add Geneve item to matcher and to the value.
5872  *
5873  * @param[in, out] matcher
5874  *   Flow matcher.
5875  * @param[in, out] key
5876  *   Flow matcher value.
5877  * @param[in] item
5878  *   Flow pattern to translate.
5879  * @param[in] inner
5880  *   Item is inner pattern.
5881  */
5882
5883 static void
5884 flow_dv_translate_item_geneve(void *matcher, void *key,
5885                               const struct rte_flow_item *item, int inner)
5886 {
5887         const struct rte_flow_item_geneve *geneve_m = item->mask;
5888         const struct rte_flow_item_geneve *geneve_v = item->spec;
5889         void *headers_m;
5890         void *headers_v;
5891         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5892         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5893         uint16_t dport;
5894         uint16_t gbhdr_m;
5895         uint16_t gbhdr_v;
5896         char *vni_m;
5897         char *vni_v;
5898         size_t size, i;
5899
5900         if (inner) {
5901                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5902                                          inner_headers);
5903                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5904         } else {
5905                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5906                                          outer_headers);
5907                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5908         }
5909         dport = MLX5_UDP_PORT_GENEVE;
5910         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5911                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5912                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5913         }
5914         if (!geneve_v)
5915                 return;
5916         if (!geneve_m)
5917                 geneve_m = &rte_flow_item_geneve_mask;
5918         size = sizeof(geneve_m->vni);
5919         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5920         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5921         memcpy(vni_m, geneve_m->vni, size);
5922         for (i = 0; i < size; ++i)
5923                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5924         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5925                  rte_be_to_cpu_16(geneve_m->protocol));
5926         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5927                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5928         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5929         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5930         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5931                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5932         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5933                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5934         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5935                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5936         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5937                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5938                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5939 }
5940
5941 /**
5942  * Add MPLS item to matcher and to the value.
5943  *
5944  * @param[in, out] matcher
5945  *   Flow matcher.
5946  * @param[in, out] key
5947  *   Flow matcher value.
5948  * @param[in] item
5949  *   Flow pattern to translate.
5950  * @param[in] prev_layer
5951  *   The protocol layer indicated in previous item.
5952  * @param[in] inner
5953  *   Item is inner pattern.
5954  */
5955 static void
5956 flow_dv_translate_item_mpls(void *matcher, void *key,
5957                             const struct rte_flow_item *item,
5958                             uint64_t prev_layer,
5959                             int inner)
5960 {
5961         const uint32_t *in_mpls_m = item->mask;
5962         const uint32_t *in_mpls_v = item->spec;
5963         uint32_t *out_mpls_m = 0;
5964         uint32_t *out_mpls_v = 0;
5965         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5966         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5967         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5968                                      misc_parameters_2);
5969         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5970         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5971         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5972
5973         switch (prev_layer) {
5974         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5975                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5976                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5977                          MLX5_UDP_PORT_MPLS);
5978                 break;
5979         case MLX5_FLOW_LAYER_GRE:
5980                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5981                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5982                          RTE_ETHER_TYPE_MPLS);
5983                 break;
5984         default:
5985                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5986                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5987                          IPPROTO_MPLS);
5988                 break;
5989         }
5990         if (!in_mpls_v)
5991                 return;
5992         if (!in_mpls_m)
5993                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5994         switch (prev_layer) {
5995         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5996                 out_mpls_m =
5997                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5998                                                  outer_first_mpls_over_udp);
5999                 out_mpls_v =
6000                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6001                                                  outer_first_mpls_over_udp);
6002                 break;
6003         case MLX5_FLOW_LAYER_GRE:
6004                 out_mpls_m =
6005                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6006                                                  outer_first_mpls_over_gre);
6007                 out_mpls_v =
6008                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6009                                                  outer_first_mpls_over_gre);
6010                 break;
6011         default:
6012                 /* Inner MPLS not over GRE is not supported. */
6013                 if (!inner) {
6014                         out_mpls_m =
6015                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6016                                                          misc2_m,
6017                                                          outer_first_mpls);
6018                         out_mpls_v =
6019                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6020                                                          misc2_v,
6021                                                          outer_first_mpls);
6022                 }
6023                 break;
6024         }
6025         if (out_mpls_m && out_mpls_v) {
6026                 *out_mpls_m = *in_mpls_m;
6027                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6028         }
6029 }
6030
6031 /**
6032  * Add metadata register item to matcher
6033  *
6034  * @param[in, out] matcher
6035  *   Flow matcher.
6036  * @param[in, out] key
6037  *   Flow matcher value.
6038  * @param[in] reg_type
6039  *   Type of device metadata register
6040  * @param[in] value
6041  *   Register value
6042  * @param[in] mask
6043  *   Register mask
6044  */
6045 static void
6046 flow_dv_match_meta_reg(void *matcher, void *key,
6047                        enum modify_reg reg_type,
6048                        uint32_t data, uint32_t mask)
6049 {
6050         void *misc2_m =
6051                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6052         void *misc2_v =
6053                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6054         uint32_t temp;
6055
6056         data &= mask;
6057         switch (reg_type) {
6058         case REG_A:
6059                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6060                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6061                 break;
6062         case REG_B:
6063                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6064                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6065                 break;
6066         case REG_C_0:
6067                 /*
6068                  * The metadata register C0 field might be divided into
6069                  * source vport index and META item value, we should set
6070                  * this field according to specified mask, not as whole one.
6071                  */
6072                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6073                 temp |= mask;
6074                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6075                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6076                 temp &= ~mask;
6077                 temp |= data;
6078                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6079                 break;
6080         case REG_C_1:
6081                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6082                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6083                 break;
6084         case REG_C_2:
6085                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6086                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6087                 break;
6088         case REG_C_3:
6089                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6090                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6091                 break;
6092         case REG_C_4:
6093                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6094                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6095                 break;
6096         case REG_C_5:
6097                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6098                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6099                 break;
6100         case REG_C_6:
6101                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6102                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6103                 break;
6104         case REG_C_7:
6105                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6106                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6107                 break;
6108         default:
6109                 MLX5_ASSERT(false);
6110                 break;
6111         }
6112 }
6113
6114 /**
6115  * Add MARK item to matcher
6116  *
6117  * @param[in] dev
6118  *   The device to configure through.
6119  * @param[in, out] matcher
6120  *   Flow matcher.
6121  * @param[in, out] key
6122  *   Flow matcher value.
6123  * @param[in] item
6124  *   Flow pattern to translate.
6125  */
6126 static void
6127 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6128                             void *matcher, void *key,
6129                             const struct rte_flow_item *item)
6130 {
6131         struct mlx5_priv *priv = dev->data->dev_private;
6132         const struct rte_flow_item_mark *mark;
6133         uint32_t value;
6134         uint32_t mask;
6135
6136         mark = item->mask ? (const void *)item->mask :
6137                             &rte_flow_item_mark_mask;
6138         mask = mark->id & priv->sh->dv_mark_mask;
6139         mark = (const void *)item->spec;
6140         MLX5_ASSERT(mark);
6141         value = mark->id & priv->sh->dv_mark_mask & mask;
6142         if (mask) {
6143                 enum modify_reg reg;
6144
6145                 /* Get the metadata register index for the mark. */
6146                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6147                 MLX5_ASSERT(reg > 0);
6148                 if (reg == REG_C_0) {
6149                         struct mlx5_priv *priv = dev->data->dev_private;
6150                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6151                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6152
6153                         mask &= msk_c0;
6154                         mask <<= shl_c0;
6155                         value <<= shl_c0;
6156                 }
6157                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6158         }
6159 }
6160
6161 /**
6162  * Add META item to matcher
6163  *
6164  * @param[in] dev
6165  *   The devich to configure through.
6166  * @param[in, out] matcher
6167  *   Flow matcher.
6168  * @param[in, out] key
6169  *   Flow matcher value.
6170  * @param[in] attr
6171  *   Attributes of flow that includes this item.
6172  * @param[in] item
6173  *   Flow pattern to translate.
6174  */
6175 static void
6176 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6177                             void *matcher, void *key,
6178                             const struct rte_flow_attr *attr,
6179                             const struct rte_flow_item *item)
6180 {
6181         const struct rte_flow_item_meta *meta_m;
6182         const struct rte_flow_item_meta *meta_v;
6183
6184         meta_m = (const void *)item->mask;
6185         if (!meta_m)
6186                 meta_m = &rte_flow_item_meta_mask;
6187         meta_v = (const void *)item->spec;
6188         if (meta_v) {
6189                 int reg;
6190                 uint32_t value = meta_v->data;
6191                 uint32_t mask = meta_m->data;
6192
6193                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6194                 if (reg < 0)
6195                         return;
6196                 /*
6197                  * In datapath code there is no endianness
6198                  * coversions for perfromance reasons, all
6199                  * pattern conversions are done in rte_flow.
6200                  */
6201                 value = rte_cpu_to_be_32(value);
6202                 mask = rte_cpu_to_be_32(mask);
6203                 if (reg == REG_C_0) {
6204                         struct mlx5_priv *priv = dev->data->dev_private;
6205                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6206                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6207 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6208                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6209
6210                         value >>= shr_c0;
6211                         mask >>= shr_c0;
6212 #endif
6213                         value <<= shl_c0;
6214                         mask <<= shl_c0;
6215                         MLX5_ASSERT(msk_c0);
6216                         MLX5_ASSERT(!(~msk_c0 & mask));
6217                 }
6218                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6219         }
6220 }
6221
6222 /**
6223  * Add vport metadata Reg C0 item to matcher
6224  *
6225  * @param[in, out] matcher
6226  *   Flow matcher.
6227  * @param[in, out] key
6228  *   Flow matcher value.
6229  * @param[in] reg
6230  *   Flow pattern to translate.
6231  */
6232 static void
6233 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6234                                   uint32_t value, uint32_t mask)
6235 {
6236         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6237 }
6238
6239 /**
6240  * Add tag item to matcher
6241  *
6242  * @param[in] dev
6243  *   The devich to configure through.
6244  * @param[in, out] matcher
6245  *   Flow matcher.
6246  * @param[in, out] key
6247  *   Flow matcher value.
6248  * @param[in] item
6249  *   Flow pattern to translate.
6250  */
6251 static void
6252 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6253                                 void *matcher, void *key,
6254                                 const struct rte_flow_item *item)
6255 {
6256         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6257         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6258         uint32_t mask, value;
6259
6260         MLX5_ASSERT(tag_v);
6261         value = tag_v->data;
6262         mask = tag_m ? tag_m->data : UINT32_MAX;
6263         if (tag_v->id == REG_C_0) {
6264                 struct mlx5_priv *priv = dev->data->dev_private;
6265                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6266                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6267
6268                 mask &= msk_c0;
6269                 mask <<= shl_c0;
6270                 value <<= shl_c0;
6271         }
6272         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6273 }
6274
6275 /**
6276  * Add TAG item to matcher
6277  *
6278  * @param[in] dev
6279  *   The devich to configure through.
6280  * @param[in, out] matcher
6281  *   Flow matcher.
6282  * @param[in, out] key
6283  *   Flow matcher value.
6284  * @param[in] item
6285  *   Flow pattern to translate.
6286  */
6287 static void
6288 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6289                            void *matcher, void *key,
6290                            const struct rte_flow_item *item)
6291 {
6292         const struct rte_flow_item_tag *tag_v = item->spec;
6293         const struct rte_flow_item_tag *tag_m = item->mask;
6294         enum modify_reg reg;
6295
6296         MLX5_ASSERT(tag_v);
6297         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6298         /* Get the metadata register index for the tag. */
6299         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6300         MLX5_ASSERT(reg > 0);
6301         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6302 }
6303
6304 /**
6305  * Add source vport match to the specified matcher.
6306  *
6307  * @param[in, out] matcher
6308  *   Flow matcher.
6309  * @param[in, out] key
6310  *   Flow matcher value.
6311  * @param[in] port
6312  *   Source vport value to match
6313  * @param[in] mask
6314  *   Mask
6315  */
6316 static void
6317 flow_dv_translate_item_source_vport(void *matcher, void *key,
6318                                     int16_t port, uint16_t mask)
6319 {
6320         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6321         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6322
6323         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6324         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6325 }
6326
6327 /**
6328  * Translate port-id item to eswitch match on  port-id.
6329  *
6330  * @param[in] dev
6331  *   The devich to configure through.
6332  * @param[in, out] matcher
6333  *   Flow matcher.
6334  * @param[in, out] key
6335  *   Flow matcher value.
6336  * @param[in] item
6337  *   Flow pattern to translate.
6338  *
6339  * @return
6340  *   0 on success, a negative errno value otherwise.
6341  */
6342 static int
6343 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6344                                void *key, const struct rte_flow_item *item)
6345 {
6346         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6347         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6348         struct mlx5_priv *priv;
6349         uint16_t mask, id;
6350
6351         mask = pid_m ? pid_m->id : 0xffff;
6352         id = pid_v ? pid_v->id : dev->data->port_id;
6353         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6354         if (!priv)
6355                 return -rte_errno;
6356         /* Translate to vport field or to metadata, depending on mode. */
6357         if (priv->vport_meta_mask)
6358                 flow_dv_translate_item_meta_vport(matcher, key,
6359                                                   priv->vport_meta_tag,
6360                                                   priv->vport_meta_mask);
6361         else
6362                 flow_dv_translate_item_source_vport(matcher, key,
6363                                                     priv->vport_id, mask);
6364         return 0;
6365 }
6366
6367 /**
6368  * Add ICMP6 item to matcher and to the value.
6369  *
6370  * @param[in, out] matcher
6371  *   Flow matcher.
6372  * @param[in, out] key
6373  *   Flow matcher value.
6374  * @param[in] item
6375  *   Flow pattern to translate.
6376  * @param[in] inner
6377  *   Item is inner pattern.
6378  */
6379 static void
6380 flow_dv_translate_item_icmp6(void *matcher, void *key,
6381                               const struct rte_flow_item *item,
6382                               int inner)
6383 {
6384         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6385         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6386         void *headers_m;
6387         void *headers_v;
6388         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6389                                      misc_parameters_3);
6390         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6391         if (inner) {
6392                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6393                                          inner_headers);
6394                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6395         } else {
6396                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6397                                          outer_headers);
6398                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6399         }
6400         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6401         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6402         if (!icmp6_v)
6403                 return;
6404         if (!icmp6_m)
6405                 icmp6_m = &rte_flow_item_icmp6_mask;
6406         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6407         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6408                  icmp6_v->type & icmp6_m->type);
6409         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6410         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6411                  icmp6_v->code & icmp6_m->code);
6412 }
6413
6414 /**
6415  * Add ICMP item to matcher and to the value.
6416  *
6417  * @param[in, out] matcher
6418  *   Flow matcher.
6419  * @param[in, out] key
6420  *   Flow matcher value.
6421  * @param[in] item
6422  *   Flow pattern to translate.
6423  * @param[in] inner
6424  *   Item is inner pattern.
6425  */
6426 static void
6427 flow_dv_translate_item_icmp(void *matcher, void *key,
6428                             const struct rte_flow_item *item,
6429                             int inner)
6430 {
6431         const struct rte_flow_item_icmp *icmp_m = item->mask;
6432         const struct rte_flow_item_icmp *icmp_v = item->spec;
6433         void *headers_m;
6434         void *headers_v;
6435         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6436                                      misc_parameters_3);
6437         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6438         if (inner) {
6439                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6440                                          inner_headers);
6441                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6442         } else {
6443                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6444                                          outer_headers);
6445                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6446         }
6447         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6448         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6449         if (!icmp_v)
6450                 return;
6451         if (!icmp_m)
6452                 icmp_m = &rte_flow_item_icmp_mask;
6453         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6454                  icmp_m->hdr.icmp_type);
6455         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6456                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6457         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6458                  icmp_m->hdr.icmp_code);
6459         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6460                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6461 }
6462
6463 /**
6464  * Add GTP item to matcher and to the value.
6465  *
6466  * @param[in, out] matcher
6467  *   Flow matcher.
6468  * @param[in, out] key
6469  *   Flow matcher value.
6470  * @param[in] item
6471  *   Flow pattern to translate.
6472  * @param[in] inner
6473  *   Item is inner pattern.
6474  */
6475 static void
6476 flow_dv_translate_item_gtp(void *matcher, void *key,
6477                            const struct rte_flow_item *item, int inner)
6478 {
6479         const struct rte_flow_item_gtp *gtp_m = item->mask;
6480         const struct rte_flow_item_gtp *gtp_v = item->spec;
6481         void *headers_m;
6482         void *headers_v;
6483         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6484                                      misc_parameters_3);
6485         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6486         uint16_t dport = RTE_GTPU_UDP_PORT;
6487
6488         if (inner) {
6489                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6490                                          inner_headers);
6491                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6492         } else {
6493                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6494                                          outer_headers);
6495                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6496         }
6497         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6498                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6499                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6500         }
6501         if (!gtp_v)
6502                 return;
6503         if (!gtp_m)
6504                 gtp_m = &rte_flow_item_gtp_mask;
6505         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6506         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6507                  gtp_v->msg_type & gtp_m->msg_type);
6508         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6509                  rte_be_to_cpu_32(gtp_m->teid));
6510         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6511                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6512 }
6513
6514 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6515
6516 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6517         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6518                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6519
6520 /**
6521  * Calculate flow matcher enable bitmap.
6522  *
6523  * @param match_criteria
6524  *   Pointer to flow matcher criteria.
6525  *
6526  * @return
6527  *   Bitmap of enabled fields.
6528  */
6529 static uint8_t
6530 flow_dv_matcher_enable(uint32_t *match_criteria)
6531 {
6532         uint8_t match_criteria_enable;
6533
6534         match_criteria_enable =
6535                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6536                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6537         match_criteria_enable |=
6538                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6539                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6540         match_criteria_enable |=
6541                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6542                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6543         match_criteria_enable |=
6544                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6545                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6546         match_criteria_enable |=
6547                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6548                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6549         return match_criteria_enable;
6550 }
6551
6552
6553 /**
6554  * Get a flow table.
6555  *
6556  * @param[in, out] dev
6557  *   Pointer to rte_eth_dev structure.
6558  * @param[in] table_id
6559  *   Table id to use.
6560  * @param[in] egress
6561  *   Direction of the table.
6562  * @param[in] transfer
6563  *   E-Switch or NIC flow.
6564  * @param[out] error
6565  *   pointer to error structure.
6566  *
6567  * @return
6568  *   Returns tables resource based on the index, NULL in case of failed.
6569  */
6570 static struct mlx5_flow_tbl_resource *
6571 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6572                          uint32_t table_id, uint8_t egress,
6573                          uint8_t transfer,
6574                          struct rte_flow_error *error)
6575 {
6576         struct mlx5_priv *priv = dev->data->dev_private;
6577         struct mlx5_ibv_shared *sh = priv->sh;
6578         struct mlx5_flow_tbl_resource *tbl;
6579         union mlx5_flow_tbl_key table_key = {
6580                 {
6581                         .table_id = table_id,
6582                         .reserved = 0,
6583                         .domain = !!transfer,
6584                         .direction = !!egress,
6585                 }
6586         };
6587         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6588                                                          table_key.v64);
6589         struct mlx5_flow_tbl_data_entry *tbl_data;
6590         int ret;
6591         void *domain;
6592
6593         if (pos) {
6594                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6595                                         entry);
6596                 tbl = &tbl_data->tbl;
6597                 rte_atomic32_inc(&tbl->refcnt);
6598                 return tbl;
6599         }
6600         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6601         if (!tbl_data) {
6602                 rte_flow_error_set(error, ENOMEM,
6603                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6604                                    NULL,
6605                                    "cannot allocate flow table data entry");
6606                 return NULL;
6607         }
6608         tbl = &tbl_data->tbl;
6609         pos = &tbl_data->entry;
6610         if (transfer)
6611                 domain = sh->fdb_domain;
6612         else if (egress)
6613                 domain = sh->tx_domain;
6614         else
6615                 domain = sh->rx_domain;
6616         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6617         if (!tbl->obj) {
6618                 rte_flow_error_set(error, ENOMEM,
6619                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6620                                    NULL, "cannot create flow table object");
6621                 rte_free(tbl_data);
6622                 return NULL;
6623         }
6624         /*
6625          * No multi-threads now, but still better to initialize the reference
6626          * count before insert it into the hash list.
6627          */
6628         rte_atomic32_init(&tbl->refcnt);
6629         /* Jump action reference count is initialized here. */
6630         rte_atomic32_init(&tbl_data->jump.refcnt);
6631         pos->key = table_key.v64;
6632         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6633         if (ret < 0) {
6634                 rte_flow_error_set(error, -ret,
6635                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6636                                    "cannot insert flow table data entry");
6637                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6638                 rte_free(tbl_data);
6639         }
6640         rte_atomic32_inc(&tbl->refcnt);
6641         return tbl;
6642 }
6643
6644 /**
6645  * Release a flow table.
6646  *
6647  * @param[in] dev
6648  *   Pointer to rte_eth_dev structure.
6649  * @param[in] tbl
6650  *   Table resource to be released.
6651  *
6652  * @return
6653  *   Returns 0 if table was released, else return 1;
6654  */
6655 static int
6656 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6657                              struct mlx5_flow_tbl_resource *tbl)
6658 {
6659         struct mlx5_priv *priv = dev->data->dev_private;
6660         struct mlx5_ibv_shared *sh = priv->sh;
6661         struct mlx5_flow_tbl_data_entry *tbl_data =
6662                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6663
6664         if (!tbl)
6665                 return 0;
6666         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6667                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6668
6669                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6670                 tbl->obj = NULL;
6671                 /* remove the entry from the hash list and free memory. */
6672                 mlx5_hlist_remove(sh->flow_tbls, pos);
6673                 rte_free(tbl_data);
6674                 return 0;
6675         }
6676         return 1;
6677 }
6678
6679 /**
6680  * Register the flow matcher.
6681  *
6682  * @param[in, out] dev
6683  *   Pointer to rte_eth_dev structure.
6684  * @param[in, out] matcher
6685  *   Pointer to flow matcher.
6686  * @param[in, out] key
6687  *   Pointer to flow table key.
6688  * @parm[in, out] dev_flow
6689  *   Pointer to the dev_flow.
6690  * @param[out] error
6691  *   pointer to error structure.
6692  *
6693  * @return
6694  *   0 on success otherwise -errno and errno is set.
6695  */
6696 static int
6697 flow_dv_matcher_register(struct rte_eth_dev *dev,
6698                          struct mlx5_flow_dv_matcher *matcher,
6699                          union mlx5_flow_tbl_key *key,
6700                          struct mlx5_flow *dev_flow,
6701                          struct rte_flow_error *error)
6702 {
6703         struct mlx5_priv *priv = dev->data->dev_private;
6704         struct mlx5_ibv_shared *sh = priv->sh;
6705         struct mlx5_flow_dv_matcher *cache_matcher;
6706         struct mlx5dv_flow_matcher_attr dv_attr = {
6707                 .type = IBV_FLOW_ATTR_NORMAL,
6708                 .match_mask = (void *)&matcher->mask,
6709         };
6710         struct mlx5_flow_tbl_resource *tbl;
6711         struct mlx5_flow_tbl_data_entry *tbl_data;
6712
6713         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6714                                        key->domain, error);
6715         if (!tbl)
6716                 return -rte_errno;      /* No need to refill the error info */
6717         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6718         /* Lookup from cache. */
6719         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6720                 if (matcher->crc == cache_matcher->crc &&
6721                     matcher->priority == cache_matcher->priority &&
6722                     !memcmp((const void *)matcher->mask.buf,
6723                             (const void *)cache_matcher->mask.buf,
6724                             cache_matcher->mask.size)) {
6725                         DRV_LOG(DEBUG,
6726                                 "%s group %u priority %hd use %s "
6727                                 "matcher %p: refcnt %d++",
6728                                 key->domain ? "FDB" : "NIC", key->table_id,
6729                                 cache_matcher->priority,
6730                                 key->direction ? "tx" : "rx",
6731                                 (void *)cache_matcher,
6732                                 rte_atomic32_read(&cache_matcher->refcnt));
6733                         rte_atomic32_inc(&cache_matcher->refcnt);
6734                         dev_flow->dv.matcher = cache_matcher;
6735                         /* old matcher should not make the table ref++. */
6736                         flow_dv_tbl_resource_release(dev, tbl);
6737                         return 0;
6738                 }
6739         }
6740         /* Register new matcher. */
6741         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6742         if (!cache_matcher) {
6743                 flow_dv_tbl_resource_release(dev, tbl);
6744                 return rte_flow_error_set(error, ENOMEM,
6745                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6746                                           "cannot allocate matcher memory");
6747         }
6748         *cache_matcher = *matcher;
6749         dv_attr.match_criteria_enable =
6750                 flow_dv_matcher_enable(cache_matcher->mask.buf);
6751         dv_attr.priority = matcher->priority;
6752         if (key->direction)
6753                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6754         cache_matcher->matcher_object =
6755                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6756         if (!cache_matcher->matcher_object) {
6757                 rte_free(cache_matcher);
6758 #ifdef HAVE_MLX5DV_DR
6759                 flow_dv_tbl_resource_release(dev, tbl);
6760 #endif
6761                 return rte_flow_error_set(error, ENOMEM,
6762                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6763                                           NULL, "cannot create matcher");
6764         }
6765         /* Save the table information */
6766         cache_matcher->tbl = tbl;
6767         rte_atomic32_init(&cache_matcher->refcnt);
6768         /* only matcher ref++, table ref++ already done above in get API. */
6769         rte_atomic32_inc(&cache_matcher->refcnt);
6770         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6771         dev_flow->dv.matcher = cache_matcher;
6772         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6773                 key->domain ? "FDB" : "NIC", key->table_id,
6774                 cache_matcher->priority,
6775                 key->direction ? "tx" : "rx", (void *)cache_matcher,
6776                 rte_atomic32_read(&cache_matcher->refcnt));
6777         return 0;
6778 }
6779
6780 /**
6781  * Find existing tag resource or create and register a new one.
6782  *
6783  * @param dev[in, out]
6784  *   Pointer to rte_eth_dev structure.
6785  * @param[in, out] tag_be24
6786  *   Tag value in big endian then R-shift 8.
6787  * @parm[in, out] dev_flow
6788  *   Pointer to the dev_flow.
6789  * @param[out] error
6790  *   pointer to error structure.
6791  *
6792  * @return
6793  *   0 on success otherwise -errno and errno is set.
6794  */
6795 static int
6796 flow_dv_tag_resource_register
6797                         (struct rte_eth_dev *dev,
6798                          uint32_t tag_be24,
6799                          struct mlx5_flow *dev_flow,
6800                          struct rte_flow_error *error)
6801 {
6802         struct mlx5_priv *priv = dev->data->dev_private;
6803         struct mlx5_ibv_shared *sh = priv->sh;
6804         struct mlx5_flow_dv_tag_resource *cache_resource;
6805         struct mlx5_hlist_entry *entry;
6806
6807         /* Lookup a matching resource from cache. */
6808         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6809         if (entry) {
6810                 cache_resource = container_of
6811                         (entry, struct mlx5_flow_dv_tag_resource, entry);
6812                 rte_atomic32_inc(&cache_resource->refcnt);
6813                 dev_flow->dv.tag_resource = cache_resource;
6814                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6815                         (void *)cache_resource,
6816                         rte_atomic32_read(&cache_resource->refcnt));
6817                 return 0;
6818         }
6819         /* Register new resource. */
6820         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6821         if (!cache_resource)
6822                 return rte_flow_error_set(error, ENOMEM,
6823                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6824                                           "cannot allocate resource memory");
6825         cache_resource->entry.key = (uint64_t)tag_be24;
6826         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6827         if (!cache_resource->action) {
6828                 rte_free(cache_resource);
6829                 return rte_flow_error_set(error, ENOMEM,
6830                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6831                                           NULL, "cannot create action");
6832         }
6833         rte_atomic32_init(&cache_resource->refcnt);
6834         rte_atomic32_inc(&cache_resource->refcnt);
6835         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6836                 mlx5_glue->destroy_flow_action(cache_resource->action);
6837                 rte_free(cache_resource);
6838                 return rte_flow_error_set(error, EEXIST,
6839                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6840                                           NULL, "cannot insert tag");
6841         }
6842         dev_flow->dv.tag_resource = cache_resource;
6843         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6844                 (void *)cache_resource,
6845                 rte_atomic32_read(&cache_resource->refcnt));
6846         return 0;
6847 }
6848
6849 /**
6850  * Release the tag.
6851  *
6852  * @param dev
6853  *   Pointer to Ethernet device.
6854  * @param flow
6855  *   Pointer to mlx5_flow.
6856  *
6857  * @return
6858  *   1 while a reference on it exists, 0 when freed.
6859  */
6860 static int
6861 flow_dv_tag_release(struct rte_eth_dev *dev,
6862                     struct mlx5_flow_dv_tag_resource *tag)
6863 {
6864         struct mlx5_priv *priv = dev->data->dev_private;
6865         struct mlx5_ibv_shared *sh = priv->sh;
6866
6867         MLX5_ASSERT(tag);
6868         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6869                 dev->data->port_id, (void *)tag,
6870                 rte_atomic32_read(&tag->refcnt));
6871         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6872                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6873                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6874                 DRV_LOG(DEBUG, "port %u tag %p: removed",
6875                         dev->data->port_id, (void *)tag);
6876                 rte_free(tag);
6877                 return 0;
6878         }
6879         return 1;
6880 }
6881
6882 /**
6883  * Translate port ID action to vport.
6884  *
6885  * @param[in] dev
6886  *   Pointer to rte_eth_dev structure.
6887  * @param[in] action
6888  *   Pointer to the port ID action.
6889  * @param[out] dst_port_id
6890  *   The target port ID.
6891  * @param[out] error
6892  *   Pointer to the error structure.
6893  *
6894  * @return
6895  *   0 on success, a negative errno value otherwise and rte_errno is set.
6896  */
6897 static int
6898 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6899                                  const struct rte_flow_action *action,
6900                                  uint32_t *dst_port_id,
6901                                  struct rte_flow_error *error)
6902 {
6903         uint32_t port;
6904         struct mlx5_priv *priv;
6905         const struct rte_flow_action_port_id *conf =
6906                         (const struct rte_flow_action_port_id *)action->conf;
6907
6908         port = conf->original ? dev->data->port_id : conf->id;
6909         priv = mlx5_port_to_eswitch_info(port, false);
6910         if (!priv)
6911                 return rte_flow_error_set(error, -rte_errno,
6912                                           RTE_FLOW_ERROR_TYPE_ACTION,
6913                                           NULL,
6914                                           "No eswitch info was found for port");
6915 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6916         /*
6917          * This parameter is transferred to
6918          * mlx5dv_dr_action_create_dest_ib_port().
6919          */
6920         *dst_port_id = priv->ibv_port;
6921 #else
6922         /*
6923          * Legacy mode, no LAG configurations is supported.
6924          * This parameter is transferred to
6925          * mlx5dv_dr_action_create_dest_vport().
6926          */
6927         *dst_port_id = priv->vport_id;
6928 #endif
6929         return 0;
6930 }
6931
6932 /**
6933  * Add Tx queue matcher
6934  *
6935  * @param[in] dev
6936  *   Pointer to the dev struct.
6937  * @param[in, out] matcher
6938  *   Flow matcher.
6939  * @param[in, out] key
6940  *   Flow matcher value.
6941  * @param[in] item
6942  *   Flow pattern to translate.
6943  * @param[in] inner
6944  *   Item is inner pattern.
6945  */
6946 static void
6947 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6948                                 void *matcher, void *key,
6949                                 const struct rte_flow_item *item)
6950 {
6951         const struct mlx5_rte_flow_item_tx_queue *queue_m;
6952         const struct mlx5_rte_flow_item_tx_queue *queue_v;
6953         void *misc_m =
6954                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6955         void *misc_v =
6956                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6957         struct mlx5_txq_ctrl *txq;
6958         uint32_t queue;
6959
6960
6961         queue_m = (const void *)item->mask;
6962         if (!queue_m)
6963                 return;
6964         queue_v = (const void *)item->spec;
6965         if (!queue_v)
6966                 return;
6967         txq = mlx5_txq_get(dev, queue_v->queue);
6968         if (!txq)
6969                 return;
6970         queue = txq->obj->sq->id;
6971         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6972         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6973                  queue & queue_m->queue);
6974         mlx5_txq_release(dev, queue_v->queue);
6975 }
6976
6977 /**
6978  * Set the hash fields according to the @p flow information.
6979  *
6980  * @param[in] dev_flow
6981  *   Pointer to the mlx5_flow.
6982  */
6983 static void
6984 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6985 {
6986         struct rte_flow *flow = dev_flow->flow;
6987         uint64_t items = dev_flow->layers;
6988         int rss_inner = 0;
6989         uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
6990
6991         dev_flow->hash_fields = 0;
6992 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
6993         if (flow->rss.level >= 2) {
6994                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
6995                 rss_inner = 1;
6996         }
6997 #endif
6998         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
6999             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7000                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7001                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7002                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7003                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7004                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7005                         else
7006                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7007                 }
7008         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7009                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7010                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7011                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7012                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7013                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7014                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7015                         else
7016                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7017                 }
7018         }
7019         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7020             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7021                 if (rss_types & ETH_RSS_UDP) {
7022                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7023                                 dev_flow->hash_fields |=
7024                                                 IBV_RX_HASH_SRC_PORT_UDP;
7025                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7026                                 dev_flow->hash_fields |=
7027                                                 IBV_RX_HASH_DST_PORT_UDP;
7028                         else
7029                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7030                 }
7031         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7032                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7033                 if (rss_types & ETH_RSS_TCP) {
7034                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7035                                 dev_flow->hash_fields |=
7036                                                 IBV_RX_HASH_SRC_PORT_TCP;
7037                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7038                                 dev_flow->hash_fields |=
7039                                                 IBV_RX_HASH_DST_PORT_TCP;
7040                         else
7041                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7042                 }
7043         }
7044 }
7045
7046 /**
7047  * Fill the flow with DV spec, lock free
7048  * (mutex should be acquired by caller).
7049  *
7050  * @param[in] dev
7051  *   Pointer to rte_eth_dev structure.
7052  * @param[in, out] dev_flow
7053  *   Pointer to the sub flow.
7054  * @param[in] attr
7055  *   Pointer to the flow attributes.
7056  * @param[in] items
7057  *   Pointer to the list of items.
7058  * @param[in] actions
7059  *   Pointer to the list of actions.
7060  * @param[out] error
7061  *   Pointer to the error structure.
7062  *
7063  * @return
7064  *   0 on success, a negative errno value otherwise and rte_errno is set.
7065  */
7066 static int
7067 __flow_dv_translate(struct rte_eth_dev *dev,
7068                     struct mlx5_flow *dev_flow,
7069                     const struct rte_flow_attr *attr,
7070                     const struct rte_flow_item items[],
7071                     const struct rte_flow_action actions[],
7072                     struct rte_flow_error *error)
7073 {
7074         struct mlx5_priv *priv = dev->data->dev_private;
7075         struct mlx5_dev_config *dev_conf = &priv->config;
7076         struct rte_flow *flow = dev_flow->flow;
7077         uint64_t item_flags = 0;
7078         uint64_t last_item = 0;
7079         uint64_t action_flags = 0;
7080         uint64_t priority = attr->priority;
7081         struct mlx5_flow_dv_matcher matcher = {
7082                 .mask = {
7083                         .size = sizeof(matcher.mask.buf),
7084                 },
7085         };
7086         int actions_n = 0;
7087         bool actions_end = false;
7088         union {
7089                 struct mlx5_flow_dv_modify_hdr_resource res;
7090                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7091                             sizeof(struct mlx5_modification_cmd) *
7092                             (MLX5_MAX_MODIFY_NUM + 1)];
7093         } mhdr_dummy;
7094         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7095         union flow_dv_attr flow_attr = { .attr = 0 };
7096         uint32_t tag_be;
7097         union mlx5_flow_tbl_key tbl_key;
7098         uint32_t modify_action_position = UINT32_MAX;
7099         void *match_mask = matcher.mask.buf;
7100         void *match_value = dev_flow->dv.value.buf;
7101         uint8_t next_protocol = 0xff;
7102         struct rte_vlan_hdr vlan = { 0 };
7103         uint32_t table;
7104         int ret = 0;
7105
7106         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7107                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7108         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7109                                        !!priv->fdb_def_rule, &table, error);
7110         if (ret)
7111                 return ret;
7112         dev_flow->group = table;
7113         if (attr->transfer)
7114                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7115         if (priority == MLX5_FLOW_PRIO_RSVD)
7116                 priority = dev_conf->flow_prio - 1;
7117         /* number of actions must be set to 0 in case of dirty stack. */
7118         mhdr_res->actions_num = 0;
7119         for (; !actions_end ; actions++) {
7120                 const struct rte_flow_action_queue *queue;
7121                 const struct rte_flow_action_rss *rss;
7122                 const struct rte_flow_action *action = actions;
7123                 const struct rte_flow_action_count *count = action->conf;
7124                 const uint8_t *rss_key;
7125                 const struct rte_flow_action_jump *jump_data;
7126                 const struct rte_flow_action_meter *mtr;
7127                 struct mlx5_flow_tbl_resource *tbl;
7128                 uint32_t port_id = 0;
7129                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7130                 int action_type = actions->type;
7131                 const struct rte_flow_action *found_action = NULL;
7132
7133                 switch (action_type) {
7134                 case RTE_FLOW_ACTION_TYPE_VOID:
7135                         break;
7136                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7137                         if (flow_dv_translate_action_port_id(dev, action,
7138                                                              &port_id, error))
7139                                 return -rte_errno;
7140                         port_id_resource.port_id = port_id;
7141                         if (flow_dv_port_id_action_resource_register
7142                             (dev, &port_id_resource, dev_flow, error))
7143                                 return -rte_errno;
7144                         dev_flow->dv.actions[actions_n++] =
7145                                 dev_flow->dv.port_id_action->action;
7146                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7147                         break;
7148                 case RTE_FLOW_ACTION_TYPE_FLAG:
7149                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7150                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7151                                 struct rte_flow_action_mark mark = {
7152                                         .id = MLX5_FLOW_MARK_DEFAULT,
7153                                 };
7154
7155                                 if (flow_dv_convert_action_mark(dev, &mark,
7156                                                                 mhdr_res,
7157                                                                 error))
7158                                         return -rte_errno;
7159                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7160                                 break;
7161                         }
7162                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7163                         if (!dev_flow->dv.tag_resource)
7164                                 if (flow_dv_tag_resource_register
7165                                     (dev, tag_be, dev_flow, error))
7166                                         return -rte_errno;
7167                         dev_flow->dv.actions[actions_n++] =
7168                                 dev_flow->dv.tag_resource->action;
7169                         break;
7170                 case RTE_FLOW_ACTION_TYPE_MARK:
7171                         action_flags |= MLX5_FLOW_ACTION_MARK;
7172                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7173                                 const struct rte_flow_action_mark *mark =
7174                                         (const struct rte_flow_action_mark *)
7175                                                 actions->conf;
7176
7177                                 if (flow_dv_convert_action_mark(dev, mark,
7178                                                                 mhdr_res,
7179                                                                 error))
7180                                         return -rte_errno;
7181                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7182                                 break;
7183                         }
7184                         /* Fall-through */
7185                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7186                         /* Legacy (non-extensive) MARK action. */
7187                         tag_be = mlx5_flow_mark_set
7188                               (((const struct rte_flow_action_mark *)
7189                                (actions->conf))->id);
7190                         if (!dev_flow->dv.tag_resource)
7191                                 if (flow_dv_tag_resource_register
7192                                     (dev, tag_be, dev_flow, error))
7193                                         return -rte_errno;
7194                         dev_flow->dv.actions[actions_n++] =
7195                                 dev_flow->dv.tag_resource->action;
7196                         break;
7197                 case RTE_FLOW_ACTION_TYPE_SET_META:
7198                         if (flow_dv_convert_action_set_meta
7199                                 (dev, mhdr_res, attr,
7200                                  (const struct rte_flow_action_set_meta *)
7201                                   actions->conf, error))
7202                                 return -rte_errno;
7203                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7204                         break;
7205                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7206                         if (flow_dv_convert_action_set_tag
7207                                 (dev, mhdr_res,
7208                                  (const struct rte_flow_action_set_tag *)
7209                                   actions->conf, error))
7210                                 return -rte_errno;
7211                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7212                         break;
7213                 case RTE_FLOW_ACTION_TYPE_DROP:
7214                         action_flags |= MLX5_FLOW_ACTION_DROP;
7215                         break;
7216                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7217                         MLX5_ASSERT(flow->rss.queue);
7218                         queue = actions->conf;
7219                         flow->rss.queue_num = 1;
7220                         (*flow->rss.queue)[0] = queue->index;
7221                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7222                         break;
7223                 case RTE_FLOW_ACTION_TYPE_RSS:
7224                         MLX5_ASSERT(flow->rss.queue);
7225                         rss = actions->conf;
7226                         if (flow->rss.queue)
7227                                 memcpy((*flow->rss.queue), rss->queue,
7228                                        rss->queue_num * sizeof(uint16_t));
7229                         flow->rss.queue_num = rss->queue_num;
7230                         /* NULL RSS key indicates default RSS key. */
7231                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7232                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7233                         /*
7234                          * rss->level and rss.types should be set in advance
7235                          * when expanding items for RSS.
7236                          */
7237                         action_flags |= MLX5_FLOW_ACTION_RSS;
7238                         break;
7239                 case RTE_FLOW_ACTION_TYPE_COUNT:
7240                         if (!dev_conf->devx) {
7241                                 rte_errno = ENOTSUP;
7242                                 goto cnt_err;
7243                         }
7244                         flow->counter = flow_dv_counter_alloc(dev,
7245                                                               count->shared,
7246                                                               count->id,
7247                                                               dev_flow->group);
7248                         if (flow->counter == NULL)
7249                                 goto cnt_err;
7250                         dev_flow->dv.actions[actions_n++] =
7251                                 flow->counter->action;
7252                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7253                         break;
7254 cnt_err:
7255                         if (rte_errno == ENOTSUP)
7256                                 return rte_flow_error_set
7257                                               (error, ENOTSUP,
7258                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7259                                                NULL,
7260                                                "count action not supported");
7261                         else
7262                                 return rte_flow_error_set
7263                                                 (error, rte_errno,
7264                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7265                                                  action,
7266                                                  "cannot create counter"
7267                                                   " object.");
7268                         break;
7269                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7270                         dev_flow->dv.actions[actions_n++] =
7271                                                 priv->sh->pop_vlan_action;
7272                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7273                         break;
7274                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7275                         flow_dev_get_vlan_info_from_items(items, &vlan);
7276                         vlan.eth_proto = rte_be_to_cpu_16
7277                              ((((const struct rte_flow_action_of_push_vlan *)
7278                                                    actions->conf)->ethertype));
7279                         found_action = mlx5_flow_find_action
7280                                         (actions + 1,
7281                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7282                         if (found_action)
7283                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7284                         found_action = mlx5_flow_find_action
7285                                         (actions + 1,
7286                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7287                         if (found_action)
7288                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7289                         if (flow_dv_create_action_push_vlan
7290                                             (dev, attr, &vlan, dev_flow, error))
7291                                 return -rte_errno;
7292                         dev_flow->dv.actions[actions_n++] =
7293                                            dev_flow->dv.push_vlan_res->action;
7294                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7295                         break;
7296                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7297                         /* of_vlan_push action handled this action */
7298                         MLX5_ASSERT(action_flags &
7299                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7300                         break;
7301                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7302                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7303                                 break;
7304                         flow_dev_get_vlan_info_from_items(items, &vlan);
7305                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7306                         /* If no VLAN push - this is a modify header action */
7307                         if (flow_dv_convert_action_modify_vlan_vid
7308                                                 (mhdr_res, actions, error))
7309                                 return -rte_errno;
7310                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7311                         break;
7312                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7313                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7314                         if (flow_dv_create_action_l2_encap(dev, actions,
7315                                                            dev_flow,
7316                                                            attr->transfer,
7317                                                            error))
7318                                 return -rte_errno;
7319                         dev_flow->dv.actions[actions_n++] =
7320                                 dev_flow->dv.encap_decap->verbs_action;
7321                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7322                         break;
7323                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7324                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7325                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7326                                                            attr->transfer,
7327                                                            error))
7328                                 return -rte_errno;
7329                         dev_flow->dv.actions[actions_n++] =
7330                                 dev_flow->dv.encap_decap->verbs_action;
7331                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7332                         break;
7333                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7334                         /* Handle encap with preceding decap. */
7335                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7336                                 if (flow_dv_create_action_raw_encap
7337                                         (dev, actions, dev_flow, attr, error))
7338                                         return -rte_errno;
7339                                 dev_flow->dv.actions[actions_n++] =
7340                                         dev_flow->dv.encap_decap->verbs_action;
7341                         } else {
7342                                 /* Handle encap without preceding decap. */
7343                                 if (flow_dv_create_action_l2_encap
7344                                     (dev, actions, dev_flow, attr->transfer,
7345                                      error))
7346                                         return -rte_errno;
7347                                 dev_flow->dv.actions[actions_n++] =
7348                                         dev_flow->dv.encap_decap->verbs_action;
7349                         }
7350                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7351                         break;
7352                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7353                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7354                                 ;
7355                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7356                                 if (flow_dv_create_action_l2_decap
7357                                     (dev, dev_flow, attr->transfer, error))
7358                                         return -rte_errno;
7359                                 dev_flow->dv.actions[actions_n++] =
7360                                         dev_flow->dv.encap_decap->verbs_action;
7361                         }
7362                         /* If decap is followed by encap, handle it at encap. */
7363                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7364                         break;
7365                 case RTE_FLOW_ACTION_TYPE_JUMP:
7366                         jump_data = action->conf;
7367                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7368                                                        jump_data->group,
7369                                                        !!priv->fdb_def_rule,
7370                                                        &table, error);
7371                         if (ret)
7372                                 return ret;
7373                         tbl = flow_dv_tbl_resource_get(dev, table,
7374                                                        attr->egress,
7375                                                        attr->transfer, error);
7376                         if (!tbl)
7377                                 return rte_flow_error_set
7378                                                 (error, errno,
7379                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7380                                                  NULL,
7381                                                  "cannot create jump action.");
7382                         if (flow_dv_jump_tbl_resource_register
7383                             (dev, tbl, dev_flow, error)) {
7384                                 flow_dv_tbl_resource_release(dev, tbl);
7385                                 return rte_flow_error_set
7386                                                 (error, errno,
7387                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7388                                                  NULL,
7389                                                  "cannot create jump action.");
7390                         }
7391                         dev_flow->dv.actions[actions_n++] =
7392                                 dev_flow->dv.jump->action;
7393                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7394                         break;
7395                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7396                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7397                         if (flow_dv_convert_action_modify_mac
7398                                         (mhdr_res, actions, error))
7399                                 return -rte_errno;
7400                         action_flags |= actions->type ==
7401                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7402                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7403                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7404                         break;
7405                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7406                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7407                         if (flow_dv_convert_action_modify_ipv4
7408                                         (mhdr_res, actions, error))
7409                                 return -rte_errno;
7410                         action_flags |= actions->type ==
7411                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7412                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7413                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7414                         break;
7415                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7416                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7417                         if (flow_dv_convert_action_modify_ipv6
7418                                         (mhdr_res, actions, error))
7419                                 return -rte_errno;
7420                         action_flags |= actions->type ==
7421                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7422                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7423                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7424                         break;
7425                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7426                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7427                         if (flow_dv_convert_action_modify_tp
7428                                         (mhdr_res, actions, items,
7429                                          &flow_attr, error))
7430                                 return -rte_errno;
7431                         action_flags |= actions->type ==
7432                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7433                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7434                                         MLX5_FLOW_ACTION_SET_TP_DST;
7435                         break;
7436                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7437                         if (flow_dv_convert_action_modify_dec_ttl
7438                                         (mhdr_res, items, &flow_attr, error))
7439                                 return -rte_errno;
7440                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7441                         break;
7442                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7443                         if (flow_dv_convert_action_modify_ttl
7444                                         (mhdr_res, actions, items,
7445                                          &flow_attr, error))
7446                                 return -rte_errno;
7447                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7448                         break;
7449                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7450                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7451                         if (flow_dv_convert_action_modify_tcp_seq
7452                                         (mhdr_res, actions, error))
7453                                 return -rte_errno;
7454                         action_flags |= actions->type ==
7455                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7456                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7457                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7458                         break;
7459
7460                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7461                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7462                         if (flow_dv_convert_action_modify_tcp_ack
7463                                         (mhdr_res, actions, error))
7464                                 return -rte_errno;
7465                         action_flags |= actions->type ==
7466                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7467                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7468                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7469                         break;
7470                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7471                         if (flow_dv_convert_action_set_reg
7472                                         (mhdr_res, actions, error))
7473                                 return -rte_errno;
7474                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7475                         break;
7476                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7477                         if (flow_dv_convert_action_copy_mreg
7478                                         (dev, mhdr_res, actions, error))
7479                                 return -rte_errno;
7480                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7481                         break;
7482                 case RTE_FLOW_ACTION_TYPE_METER:
7483                         mtr = actions->conf;
7484                         if (!flow->meter) {
7485                                 flow->meter = mlx5_flow_meter_attach(priv,
7486                                                         mtr->mtr_id, attr,
7487                                                         error);
7488                                 if (!flow->meter)
7489                                         return rte_flow_error_set(error,
7490                                                 rte_errno,
7491                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7492                                                 NULL,
7493                                                 "meter not found "
7494                                                 "or invalid parameters");
7495                         }
7496                         /* Set the meter action. */
7497                         dev_flow->dv.actions[actions_n++] =
7498                                 flow->meter->mfts->meter_action;
7499                         action_flags |= MLX5_FLOW_ACTION_METER;
7500                         break;
7501                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7502                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7503                                                               actions, error))
7504                                 return -rte_errno;
7505                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7506                         break;
7507                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7508                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7509                                                               actions, error))
7510                                 return -rte_errno;
7511                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7512                         break;
7513                 case RTE_FLOW_ACTION_TYPE_END:
7514                         actions_end = true;
7515                         if (mhdr_res->actions_num) {
7516                                 /* create modify action if needed. */
7517                                 if (flow_dv_modify_hdr_resource_register
7518                                         (dev, mhdr_res, dev_flow, error))
7519                                         return -rte_errno;
7520                                 dev_flow->dv.actions[modify_action_position] =
7521                                         dev_flow->dv.modify_hdr->verbs_action;
7522                         }
7523                         break;
7524                 default:
7525                         break;
7526                 }
7527                 if (mhdr_res->actions_num &&
7528                     modify_action_position == UINT32_MAX)
7529                         modify_action_position = actions_n++;
7530         }
7531         dev_flow->dv.actions_n = actions_n;
7532         dev_flow->actions = action_flags;
7533         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7534                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7535                 int item_type = items->type;
7536
7537                 switch (item_type) {
7538                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7539                         flow_dv_translate_item_port_id(dev, match_mask,
7540                                                        match_value, items);
7541                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7542                         break;
7543                 case RTE_FLOW_ITEM_TYPE_ETH:
7544                         flow_dv_translate_item_eth(match_mask, match_value,
7545                                                    items, tunnel);
7546                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7547                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7548                                              MLX5_FLOW_LAYER_OUTER_L2;
7549                         break;
7550                 case RTE_FLOW_ITEM_TYPE_VLAN:
7551                         flow_dv_translate_item_vlan(dev_flow,
7552                                                     match_mask, match_value,
7553                                                     items, tunnel);
7554                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7555                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7556                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7557                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7558                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7559                         break;
7560                 case RTE_FLOW_ITEM_TYPE_IPV4:
7561                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7562                                                   &item_flags, &tunnel);
7563                         flow_dv_translate_item_ipv4(match_mask, match_value,
7564                                                     items, tunnel,
7565                                                     dev_flow->group);
7566                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7567                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7568                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7569                         if (items->mask != NULL &&
7570                             ((const struct rte_flow_item_ipv4 *)
7571                              items->mask)->hdr.next_proto_id) {
7572                                 next_protocol =
7573                                         ((const struct rte_flow_item_ipv4 *)
7574                                          (items->spec))->hdr.next_proto_id;
7575                                 next_protocol &=
7576                                         ((const struct rte_flow_item_ipv4 *)
7577                                          (items->mask))->hdr.next_proto_id;
7578                         } else {
7579                                 /* Reset for inner layer. */
7580                                 next_protocol = 0xff;
7581                         }
7582                         break;
7583                 case RTE_FLOW_ITEM_TYPE_IPV6:
7584                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7585                                                   &item_flags, &tunnel);
7586                         flow_dv_translate_item_ipv6(match_mask, match_value,
7587                                                     items, tunnel,
7588                                                     dev_flow->group);
7589                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7590                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7591                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7592                         if (items->mask != NULL &&
7593                             ((const struct rte_flow_item_ipv6 *)
7594                              items->mask)->hdr.proto) {
7595                                 next_protocol =
7596                                         ((const struct rte_flow_item_ipv6 *)
7597                                          items->spec)->hdr.proto;
7598                                 next_protocol &=
7599                                         ((const struct rte_flow_item_ipv6 *)
7600                                          items->mask)->hdr.proto;
7601                         } else {
7602                                 /* Reset for inner layer. */
7603                                 next_protocol = 0xff;
7604                         }
7605                         break;
7606                 case RTE_FLOW_ITEM_TYPE_TCP:
7607                         flow_dv_translate_item_tcp(match_mask, match_value,
7608                                                    items, tunnel);
7609                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7610                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7611                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7612                         break;
7613                 case RTE_FLOW_ITEM_TYPE_UDP:
7614                         flow_dv_translate_item_udp(match_mask, match_value,
7615                                                    items, tunnel);
7616                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7617                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7618                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7619                         break;
7620                 case RTE_FLOW_ITEM_TYPE_GRE:
7621                         flow_dv_translate_item_gre(match_mask, match_value,
7622                                                    items, tunnel);
7623                         matcher.priority = flow->rss.level >= 2 ?
7624                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7625                         last_item = MLX5_FLOW_LAYER_GRE;
7626                         break;
7627                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7628                         flow_dv_translate_item_gre_key(match_mask,
7629                                                        match_value, items);
7630                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7631                         break;
7632                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7633                         flow_dv_translate_item_nvgre(match_mask, match_value,
7634                                                      items, tunnel);
7635                         matcher.priority = flow->rss.level >= 2 ?
7636                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7637                         last_item = MLX5_FLOW_LAYER_GRE;
7638                         break;
7639                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7640                         flow_dv_translate_item_vxlan(match_mask, match_value,
7641                                                      items, tunnel);
7642                         matcher.priority = flow->rss.level >= 2 ?
7643                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7644                         last_item = MLX5_FLOW_LAYER_VXLAN;
7645                         break;
7646                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7647                         flow_dv_translate_item_vxlan_gpe(match_mask,
7648                                                          match_value, items,
7649                                                          tunnel);
7650                         matcher.priority = flow->rss.level >= 2 ?
7651                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7652                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7653                         break;
7654                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7655                         flow_dv_translate_item_geneve(match_mask, match_value,
7656                                                       items, tunnel);
7657                         matcher.priority = flow->rss.level >= 2 ?
7658                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7659                         last_item = MLX5_FLOW_LAYER_GENEVE;
7660                         break;
7661                 case RTE_FLOW_ITEM_TYPE_MPLS:
7662                         flow_dv_translate_item_mpls(match_mask, match_value,
7663                                                     items, last_item, tunnel);
7664                         matcher.priority = flow->rss.level >= 2 ?
7665                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7666                         last_item = MLX5_FLOW_LAYER_MPLS;
7667                         break;
7668                 case RTE_FLOW_ITEM_TYPE_MARK:
7669                         flow_dv_translate_item_mark(dev, match_mask,
7670                                                     match_value, items);
7671                         last_item = MLX5_FLOW_ITEM_MARK;
7672                         break;
7673                 case RTE_FLOW_ITEM_TYPE_META:
7674                         flow_dv_translate_item_meta(dev, match_mask,
7675                                                     match_value, attr, items);
7676                         last_item = MLX5_FLOW_ITEM_METADATA;
7677                         break;
7678                 case RTE_FLOW_ITEM_TYPE_ICMP:
7679                         flow_dv_translate_item_icmp(match_mask, match_value,
7680                                                     items, tunnel);
7681                         last_item = MLX5_FLOW_LAYER_ICMP;
7682                         break;
7683                 case RTE_FLOW_ITEM_TYPE_ICMP6:
7684                         flow_dv_translate_item_icmp6(match_mask, match_value,
7685                                                       items, tunnel);
7686                         last_item = MLX5_FLOW_LAYER_ICMP6;
7687                         break;
7688                 case RTE_FLOW_ITEM_TYPE_TAG:
7689                         flow_dv_translate_item_tag(dev, match_mask,
7690                                                    match_value, items);
7691                         last_item = MLX5_FLOW_ITEM_TAG;
7692                         break;
7693                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7694                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
7695                                                         match_value, items);
7696                         last_item = MLX5_FLOW_ITEM_TAG;
7697                         break;
7698                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7699                         flow_dv_translate_item_tx_queue(dev, match_mask,
7700                                                         match_value,
7701                                                         items);
7702                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7703                         break;
7704                 case RTE_FLOW_ITEM_TYPE_GTP:
7705                         flow_dv_translate_item_gtp(match_mask, match_value,
7706                                                    items, tunnel);
7707                         matcher.priority = flow->rss.level >= 2 ?
7708                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7709                         last_item = MLX5_FLOW_LAYER_GTP;
7710                         break;
7711                 default:
7712                         break;
7713                 }
7714                 item_flags |= last_item;
7715         }
7716         /*
7717          * When E-Switch mode is enabled, we have two cases where we need to
7718          * set the source port manually.
7719          * The first one, is in case of Nic steering rule, and the second is
7720          * E-Switch rule where no port_id item was found. In both cases
7721          * the source port is set according the current port in use.
7722          */
7723         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7724             (priv->representor || priv->master)) {
7725                 if (flow_dv_translate_item_port_id(dev, match_mask,
7726                                                    match_value, NULL))
7727                         return -rte_errno;
7728         }
7729 #ifdef RTE_LIBRTE_MLX5_DEBUG
7730         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7731                                               dev_flow->dv.value.buf));
7732 #endif
7733         dev_flow->layers = item_flags;
7734         if (action_flags & MLX5_FLOW_ACTION_RSS)
7735                 flow_dv_hashfields_set(dev_flow);
7736         /* Register matcher. */
7737         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7738                                     matcher.mask.size);
7739         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7740                                                      matcher.priority);
7741         /* reserved field no needs to be set to 0 here. */
7742         tbl_key.domain = attr->transfer;
7743         tbl_key.direction = attr->egress;
7744         tbl_key.table_id = dev_flow->group;
7745         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7746                 return -rte_errno;
7747         return 0;
7748 }
7749
7750 /**
7751  * Apply the flow to the NIC, lock free,
7752  * (mutex should be acquired by caller).
7753  *
7754  * @param[in] dev
7755  *   Pointer to the Ethernet device structure.
7756  * @param[in, out] flow
7757  *   Pointer to flow structure.
7758  * @param[out] error
7759  *   Pointer to error structure.
7760  *
7761  * @return
7762  *   0 on success, a negative errno value otherwise and rte_errno is set.
7763  */
7764 static int
7765 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7766                 struct rte_flow_error *error)
7767 {
7768         struct mlx5_flow_dv *dv;
7769         struct mlx5_flow *dev_flow;
7770         struct mlx5_priv *priv = dev->data->dev_private;
7771         int n;
7772         int err;
7773
7774         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7775                 dv = &dev_flow->dv;
7776                 n = dv->actions_n;
7777                 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7778                         if (dev_flow->transfer) {
7779                                 dv->actions[n++] = priv->sh->esw_drop_action;
7780                         } else {
7781                                 dv->hrxq = mlx5_hrxq_drop_new(dev);
7782                                 if (!dv->hrxq) {
7783                                         rte_flow_error_set
7784                                                 (error, errno,
7785                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7786                                                  NULL,
7787                                                  "cannot get drop hash queue");
7788                                         goto error;
7789                                 }
7790                                 dv->actions[n++] = dv->hrxq->action;
7791                         }
7792                 } else if (dev_flow->actions &
7793                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7794                         struct mlx5_hrxq *hrxq;
7795
7796                         MLX5_ASSERT(flow->rss.queue);
7797                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7798                                              MLX5_RSS_HASH_KEY_LEN,
7799                                              dev_flow->hash_fields,
7800                                              (*flow->rss.queue),
7801                                              flow->rss.queue_num);
7802                         if (!hrxq) {
7803                                 hrxq = mlx5_hrxq_new
7804                                         (dev, flow->rss.key,
7805                                          MLX5_RSS_HASH_KEY_LEN,
7806                                          dev_flow->hash_fields,
7807                                          (*flow->rss.queue),
7808                                          flow->rss.queue_num,
7809                                          !!(dev_flow->layers &
7810                                             MLX5_FLOW_LAYER_TUNNEL));
7811                         }
7812                         if (!hrxq) {
7813                                 rte_flow_error_set
7814                                         (error, rte_errno,
7815                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7816                                          "cannot get hash queue");
7817                                 goto error;
7818                         }
7819                         dv->hrxq = hrxq;
7820                         dv->actions[n++] = dv->hrxq->action;
7821                 }
7822                 dv->flow =
7823                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7824                                                   (void *)&dv->value, n,
7825                                                   dv->actions);
7826                 if (!dv->flow) {
7827                         rte_flow_error_set(error, errno,
7828                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7829                                            NULL,
7830                                            "hardware refuses to create flow");
7831                         goto error;
7832                 }
7833                 if (priv->vmwa_context &&
7834                     dev_flow->dv.vf_vlan.tag &&
7835                     !dev_flow->dv.vf_vlan.created) {
7836                         /*
7837                          * The rule contains the VLAN pattern.
7838                          * For VF we are going to create VLAN
7839                          * interface to make hypervisor set correct
7840                          * e-Switch vport context.
7841                          */
7842                         mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7843                 }
7844         }
7845         return 0;
7846 error:
7847         err = rte_errno; /* Save rte_errno before cleanup. */
7848         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7849                 struct mlx5_flow_dv *dv = &dev_flow->dv;
7850                 if (dv->hrxq) {
7851                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7852                                 mlx5_hrxq_drop_release(dev);
7853                         else
7854                                 mlx5_hrxq_release(dev, dv->hrxq);
7855                         dv->hrxq = NULL;
7856                 }
7857                 if (dev_flow->dv.vf_vlan.tag &&
7858                     dev_flow->dv.vf_vlan.created)
7859                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7860         }
7861         rte_errno = err; /* Restore rte_errno. */
7862         return -rte_errno;
7863 }
7864
7865 /**
7866  * Release the flow matcher.
7867  *
7868  * @param dev
7869  *   Pointer to Ethernet device.
7870  * @param flow
7871  *   Pointer to mlx5_flow.
7872  *
7873  * @return
7874  *   1 while a reference on it exists, 0 when freed.
7875  */
7876 static int
7877 flow_dv_matcher_release(struct rte_eth_dev *dev,
7878                         struct mlx5_flow *flow)
7879 {
7880         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7881
7882         MLX5_ASSERT(matcher->matcher_object);
7883         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7884                 dev->data->port_id, (void *)matcher,
7885                 rte_atomic32_read(&matcher->refcnt));
7886         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7887                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7888                            (matcher->matcher_object));
7889                 LIST_REMOVE(matcher, next);
7890                 /* table ref-- in release interface. */
7891                 flow_dv_tbl_resource_release(dev, matcher->tbl);
7892                 rte_free(matcher);
7893                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7894                         dev->data->port_id, (void *)matcher);
7895                 return 0;
7896         }
7897         return 1;
7898 }
7899
7900 /**
7901  * Release an encap/decap resource.
7902  *
7903  * @param flow
7904  *   Pointer to mlx5_flow.
7905  *
7906  * @return
7907  *   1 while a reference on it exists, 0 when freed.
7908  */
7909 static int
7910 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7911 {
7912         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7913                                                 flow->dv.encap_decap;
7914
7915         MLX5_ASSERT(cache_resource->verbs_action);
7916         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7917                 (void *)cache_resource,
7918                 rte_atomic32_read(&cache_resource->refcnt));
7919         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7920                 claim_zero(mlx5_glue->destroy_flow_action
7921                                 (cache_resource->verbs_action));
7922                 LIST_REMOVE(cache_resource, next);
7923                 rte_free(cache_resource);
7924                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7925                         (void *)cache_resource);
7926                 return 0;
7927         }
7928         return 1;
7929 }
7930
7931 /**
7932  * Release an jump to table action resource.
7933  *
7934  * @param dev
7935  *   Pointer to Ethernet device.
7936  * @param flow
7937  *   Pointer to mlx5_flow.
7938  *
7939  * @return
7940  *   1 while a reference on it exists, 0 when freed.
7941  */
7942 static int
7943 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7944                                   struct mlx5_flow *flow)
7945 {
7946         struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7947         struct mlx5_flow_tbl_data_entry *tbl_data =
7948                         container_of(cache_resource,
7949                                      struct mlx5_flow_tbl_data_entry, jump);
7950
7951         MLX5_ASSERT(cache_resource->action);
7952         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7953                 (void *)cache_resource,
7954                 rte_atomic32_read(&cache_resource->refcnt));
7955         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7956                 claim_zero(mlx5_glue->destroy_flow_action
7957                                 (cache_resource->action));
7958                 /* jump action memory free is inside the table release. */
7959                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7960                 DRV_LOG(DEBUG, "jump table resource %p: removed",
7961                         (void *)cache_resource);
7962                 return 0;
7963         }
7964         return 1;
7965 }
7966
7967 /**
7968  * Release a modify-header resource.
7969  *
7970  * @param flow
7971  *   Pointer to mlx5_flow.
7972  *
7973  * @return
7974  *   1 while a reference on it exists, 0 when freed.
7975  */
7976 static int
7977 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7978 {
7979         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7980                                                 flow->dv.modify_hdr;
7981
7982         MLX5_ASSERT(cache_resource->verbs_action);
7983         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7984                 (void *)cache_resource,
7985                 rte_atomic32_read(&cache_resource->refcnt));
7986         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7987                 claim_zero(mlx5_glue->destroy_flow_action
7988                                 (cache_resource->verbs_action));
7989                 LIST_REMOVE(cache_resource, next);
7990                 rte_free(cache_resource);
7991                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7992                         (void *)cache_resource);
7993                 return 0;
7994         }
7995         return 1;
7996 }
7997
7998 /**
7999  * Release port ID action resource.
8000  *
8001  * @param flow
8002  *   Pointer to mlx5_flow.
8003  *
8004  * @return
8005  *   1 while a reference on it exists, 0 when freed.
8006  */
8007 static int
8008 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8009 {
8010         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8011                 flow->dv.port_id_action;
8012
8013         MLX5_ASSERT(cache_resource->action);
8014         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8015                 (void *)cache_resource,
8016                 rte_atomic32_read(&cache_resource->refcnt));
8017         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8018                 claim_zero(mlx5_glue->destroy_flow_action
8019                                 (cache_resource->action));
8020                 LIST_REMOVE(cache_resource, next);
8021                 rte_free(cache_resource);
8022                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8023                         (void *)cache_resource);
8024                 return 0;
8025         }
8026         return 1;
8027 }
8028
8029 /**
8030  * Release push vlan action resource.
8031  *
8032  * @param flow
8033  *   Pointer to mlx5_flow.
8034  *
8035  * @return
8036  *   1 while a reference on it exists, 0 when freed.
8037  */
8038 static int
8039 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8040 {
8041         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8042                 flow->dv.push_vlan_res;
8043
8044         MLX5_ASSERT(cache_resource->action);
8045         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8046                 (void *)cache_resource,
8047                 rte_atomic32_read(&cache_resource->refcnt));
8048         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8049                 claim_zero(mlx5_glue->destroy_flow_action
8050                                 (cache_resource->action));
8051                 LIST_REMOVE(cache_resource, next);
8052                 rte_free(cache_resource);
8053                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8054                         (void *)cache_resource);
8055                 return 0;
8056         }
8057         return 1;
8058 }
8059
8060 /**
8061  * Remove the flow from the NIC but keeps it in memory.
8062  * Lock free, (mutex should be acquired by caller).
8063  *
8064  * @param[in] dev
8065  *   Pointer to Ethernet device.
8066  * @param[in, out] flow
8067  *   Pointer to flow structure.
8068  */
8069 static void
8070 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8071 {
8072         struct mlx5_flow_dv *dv;
8073         struct mlx5_flow *dev_flow;
8074
8075         if (!flow)
8076                 return;
8077         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8078                 dv = &dev_flow->dv;
8079                 if (dv->flow) {
8080                         claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8081                         dv->flow = NULL;
8082                 }
8083                 if (dv->hrxq) {
8084                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8085                                 mlx5_hrxq_drop_release(dev);
8086                         else
8087                                 mlx5_hrxq_release(dev, dv->hrxq);
8088                         dv->hrxq = NULL;
8089                 }
8090                 if (dev_flow->dv.vf_vlan.tag &&
8091                     dev_flow->dv.vf_vlan.created)
8092                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8093         }
8094 }
8095
8096 /**
8097  * Remove the flow from the NIC and the memory.
8098  * Lock free, (mutex should be acquired by caller).
8099  *
8100  * @param[in] dev
8101  *   Pointer to the Ethernet device structure.
8102  * @param[in, out] flow
8103  *   Pointer to flow structure.
8104  */
8105 static void
8106 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8107 {
8108         struct mlx5_flow *dev_flow;
8109
8110         if (!flow)
8111                 return;
8112         __flow_dv_remove(dev, flow);
8113         if (flow->counter) {
8114                 flow_dv_counter_release(dev, flow->counter);
8115                 flow->counter = NULL;
8116         }
8117         if (flow->meter) {
8118                 mlx5_flow_meter_detach(flow->meter);
8119                 flow->meter = NULL;
8120         }
8121         while (!LIST_EMPTY(&flow->dev_flows)) {
8122                 dev_flow = LIST_FIRST(&flow->dev_flows);
8123                 LIST_REMOVE(dev_flow, next);
8124                 if (dev_flow->dv.matcher)
8125                         flow_dv_matcher_release(dev, dev_flow);
8126                 if (dev_flow->dv.encap_decap)
8127                         flow_dv_encap_decap_resource_release(dev_flow);
8128                 if (dev_flow->dv.modify_hdr)
8129                         flow_dv_modify_hdr_resource_release(dev_flow);
8130                 if (dev_flow->dv.jump)
8131                         flow_dv_jump_tbl_resource_release(dev, dev_flow);
8132                 if (dev_flow->dv.port_id_action)
8133                         flow_dv_port_id_action_resource_release(dev_flow);
8134                 if (dev_flow->dv.push_vlan_res)
8135                         flow_dv_push_vlan_action_resource_release(dev_flow);
8136                 if (dev_flow->dv.tag_resource)
8137                         flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8138                 rte_free(dev_flow);
8139         }
8140 }
8141
8142 /**
8143  * Query a dv flow  rule for its statistics via devx.
8144  *
8145  * @param[in] dev
8146  *   Pointer to Ethernet device.
8147  * @param[in] flow
8148  *   Pointer to the sub flow.
8149  * @param[out] data
8150  *   data retrieved by the query.
8151  * @param[out] error
8152  *   Perform verbose error reporting if not NULL.
8153  *
8154  * @return
8155  *   0 on success, a negative errno value otherwise and rte_errno is set.
8156  */
8157 static int
8158 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8159                     void *data, struct rte_flow_error *error)
8160 {
8161         struct mlx5_priv *priv = dev->data->dev_private;
8162         struct rte_flow_query_count *qc = data;
8163
8164         if (!priv->config.devx)
8165                 return rte_flow_error_set(error, ENOTSUP,
8166                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8167                                           NULL,
8168                                           "counters are not supported");
8169         if (flow->counter) {
8170                 uint64_t pkts, bytes;
8171                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8172                                                &bytes);
8173
8174                 if (err)
8175                         return rte_flow_error_set(error, -err,
8176                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8177                                         NULL, "cannot read counters");
8178                 qc->hits_set = 1;
8179                 qc->bytes_set = 1;
8180                 qc->hits = pkts - flow->counter->hits;
8181                 qc->bytes = bytes - flow->counter->bytes;
8182                 if (qc->reset) {
8183                         flow->counter->hits = pkts;
8184                         flow->counter->bytes = bytes;
8185                 }
8186                 return 0;
8187         }
8188         return rte_flow_error_set(error, EINVAL,
8189                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8190                                   NULL,
8191                                   "counters are not available");
8192 }
8193
8194 /**
8195  * Query a flow.
8196  *
8197  * @see rte_flow_query()
8198  * @see rte_flow_ops
8199  */
8200 static int
8201 flow_dv_query(struct rte_eth_dev *dev,
8202               struct rte_flow *flow __rte_unused,
8203               const struct rte_flow_action *actions __rte_unused,
8204               void *data __rte_unused,
8205               struct rte_flow_error *error __rte_unused)
8206 {
8207         int ret = -EINVAL;
8208
8209         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8210                 switch (actions->type) {
8211                 case RTE_FLOW_ACTION_TYPE_VOID:
8212                         break;
8213                 case RTE_FLOW_ACTION_TYPE_COUNT:
8214                         ret = flow_dv_query_count(dev, flow, data, error);
8215                         break;
8216                 default:
8217                         return rte_flow_error_set(error, ENOTSUP,
8218                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8219                                                   actions,
8220                                                   "action not supported");
8221                 }
8222         }
8223         return ret;
8224 }
8225
8226 /**
8227  * Destroy the meter table set.
8228  * Lock free, (mutex should be acquired by caller).
8229  *
8230  * @param[in] dev
8231  *   Pointer to Ethernet device.
8232  * @param[in] tbl
8233  *   Pointer to the meter table set.
8234  *
8235  * @return
8236  *   Always 0.
8237  */
8238 static int
8239 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8240                         struct mlx5_meter_domains_infos *tbl)
8241 {
8242         struct mlx5_priv *priv = dev->data->dev_private;
8243         struct mlx5_meter_domains_infos *mtd =
8244                                 (struct mlx5_meter_domains_infos *)tbl;
8245
8246         if (!mtd || !priv->config.dv_flow_en)
8247                 return 0;
8248         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8249                 claim_zero(mlx5_glue->dv_destroy_flow
8250                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8251         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8252                 claim_zero(mlx5_glue->dv_destroy_flow
8253                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8254         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8255                 claim_zero(mlx5_glue->dv_destroy_flow
8256                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8257         if (mtd->egress.color_matcher)
8258                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8259                           (mtd->egress.color_matcher));
8260         if (mtd->egress.any_matcher)
8261                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8262                           (mtd->egress.any_matcher));
8263         if (mtd->egress.tbl)
8264                 claim_zero(flow_dv_tbl_resource_release(dev,
8265                                                         mtd->egress.tbl));
8266         if (mtd->ingress.color_matcher)
8267                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8268                           (mtd->ingress.color_matcher));
8269         if (mtd->ingress.any_matcher)
8270                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8271                           (mtd->ingress.any_matcher));
8272         if (mtd->ingress.tbl)
8273                 claim_zero(flow_dv_tbl_resource_release(dev,
8274                                                         mtd->ingress.tbl));
8275         if (mtd->transfer.color_matcher)
8276                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8277                           (mtd->transfer.color_matcher));
8278         if (mtd->transfer.any_matcher)
8279                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8280                           (mtd->transfer.any_matcher));
8281         if (mtd->transfer.tbl)
8282                 claim_zero(flow_dv_tbl_resource_release(dev,
8283                                                         mtd->transfer.tbl));
8284         if (mtd->drop_actn)
8285                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8286         rte_free(mtd);
8287         return 0;
8288 }
8289
8290 /* Number of meter flow actions, count and jump or count and drop. */
8291 #define METER_ACTIONS 2
8292
8293 /**
8294  * Create specify domain meter table and suffix table.
8295  *
8296  * @param[in] dev
8297  *   Pointer to Ethernet device.
8298  * @param[in,out] mtb
8299  *   Pointer to DV meter table set.
8300  * @param[in] egress
8301  *   Table attribute.
8302  * @param[in] transfer
8303  *   Table attribute.
8304  * @param[in] color_reg_c_idx
8305  *   Reg C index for color match.
8306  *
8307  * @return
8308  *   0 on success, -1 otherwise and rte_errno is set.
8309  */
8310 static int
8311 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8312                            struct mlx5_meter_domains_infos *mtb,
8313                            uint8_t egress, uint8_t transfer,
8314                            uint32_t color_reg_c_idx)
8315 {
8316         struct mlx5_priv *priv = dev->data->dev_private;
8317         struct mlx5_ibv_shared *sh = priv->sh;
8318         struct mlx5_flow_dv_match_params mask = {
8319                 .size = sizeof(mask.buf),
8320         };
8321         struct mlx5_flow_dv_match_params value = {
8322                 .size = sizeof(value.buf),
8323         };
8324         struct mlx5dv_flow_matcher_attr dv_attr = {
8325                 .type = IBV_FLOW_ATTR_NORMAL,
8326                 .priority = 0,
8327                 .match_criteria_enable = 0,
8328                 .match_mask = (void *)&mask,
8329         };
8330         void *actions[METER_ACTIONS];
8331         struct mlx5_flow_tbl_resource **sfx_tbl;
8332         struct mlx5_meter_domain_info *dtb;
8333         struct rte_flow_error error;
8334         int i = 0;
8335
8336         if (transfer) {
8337                 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8338                 dtb = &mtb->transfer;
8339         } else if (egress) {
8340                 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8341                 dtb = &mtb->egress;
8342         } else {
8343                 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8344                 dtb = &mtb->ingress;
8345         }
8346         /* If the suffix table in missing, create it. */
8347         if (!(*sfx_tbl)) {
8348                 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8349                                                 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8350                                                 egress, transfer, &error);
8351                 if (!(*sfx_tbl)) {
8352                         DRV_LOG(ERR, "Failed to create meter suffix table.");
8353                         return -1;
8354                 }
8355         }
8356         /* Create the meter table with METER level. */
8357         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8358                                             egress, transfer, &error);
8359         if (!dtb->tbl) {
8360                 DRV_LOG(ERR, "Failed to create meter policer table.");
8361                 return -1;
8362         }
8363         /* Create matchers, Any and Color. */
8364         dv_attr.priority = 3;
8365         dv_attr.match_criteria_enable = 0;
8366         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8367                                                              &dv_attr,
8368                                                              dtb->tbl->obj);
8369         if (!dtb->any_matcher) {
8370                 DRV_LOG(ERR, "Failed to create meter"
8371                              " policer default matcher.");
8372                 goto error_exit;
8373         }
8374         dv_attr.priority = 0;
8375         dv_attr.match_criteria_enable =
8376                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8377         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8378                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8379         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8380                                                                &dv_attr,
8381                                                                dtb->tbl->obj);
8382         if (!dtb->color_matcher) {
8383                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8384                 goto error_exit;
8385         }
8386         if (mtb->count_actns[RTE_MTR_DROPPED])
8387                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8388         actions[i++] = mtb->drop_actn;
8389         /* Default rule: lowest priority, match any, actions: drop. */
8390         dtb->policer_rules[RTE_MTR_DROPPED] =
8391                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8392                                                  (void *)&value, i, actions);
8393         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8394                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8395                 goto error_exit;
8396         }
8397         return 0;
8398 error_exit:
8399         return -1;
8400 }
8401
8402 /**
8403  * Create the needed meter and suffix tables.
8404  * Lock free, (mutex should be acquired by caller).
8405  *
8406  * @param[in] dev
8407  *   Pointer to Ethernet device.
8408  * @param[in] fm
8409  *   Pointer to the flow meter.
8410  *
8411  * @return
8412  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8413  */
8414 static struct mlx5_meter_domains_infos *
8415 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8416                        const struct mlx5_flow_meter *fm)
8417 {
8418         struct mlx5_priv *priv = dev->data->dev_private;
8419         struct mlx5_meter_domains_infos *mtb;
8420         int ret;
8421         int i;
8422
8423         if (!priv->mtr_en) {
8424                 rte_errno = ENOTSUP;
8425                 return NULL;
8426         }
8427         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8428         if (!mtb) {
8429                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8430                 return NULL;
8431         }
8432         /* Create meter count actions */
8433         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8434                 if (!fm->policer_stats.cnt[i])
8435                         continue;
8436                 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8437         }
8438         /* Create drop action. */
8439         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8440         if (!mtb->drop_actn) {
8441                 DRV_LOG(ERR, "Failed to create drop action.");
8442                 goto error_exit;
8443         }
8444         /* Egress meter table. */
8445         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8446         if (ret) {
8447                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8448                 goto error_exit;
8449         }
8450         /* Ingress meter table. */
8451         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8452         if (ret) {
8453                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8454                 goto error_exit;
8455         }
8456         /* FDB meter table. */
8457         if (priv->config.dv_esw_en) {
8458                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8459                                                  priv->mtr_color_reg);
8460                 if (ret) {
8461                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8462                         goto error_exit;
8463                 }
8464         }
8465         return mtb;
8466 error_exit:
8467         flow_dv_destroy_mtr_tbl(dev, mtb);
8468         return NULL;
8469 }
8470
8471 /**
8472  * Destroy domain policer rule.
8473  *
8474  * @param[in] dt
8475  *   Pointer to domain table.
8476  */
8477 static void
8478 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8479 {
8480         int i;
8481
8482         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8483                 if (dt->policer_rules[i]) {
8484                         claim_zero(mlx5_glue->dv_destroy_flow
8485                                   (dt->policer_rules[i]));
8486                         dt->policer_rules[i] = NULL;
8487                 }
8488         }
8489         if (dt->jump_actn) {
8490                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8491                 dt->jump_actn = NULL;
8492         }
8493 }
8494
8495 /**
8496  * Destroy policer rules.
8497  *
8498  * @param[in] dev
8499  *   Pointer to Ethernet device.
8500  * @param[in] fm
8501  *   Pointer to flow meter structure.
8502  * @param[in] attr
8503  *   Pointer to flow attributes.
8504  *
8505  * @return
8506  *   Always 0.
8507  */
8508 static int
8509 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8510                               const struct mlx5_flow_meter *fm,
8511                               const struct rte_flow_attr *attr)
8512 {
8513         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8514
8515         if (!mtb)
8516                 return 0;
8517         if (attr->egress)
8518                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8519         if (attr->ingress)
8520                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8521         if (attr->transfer)
8522                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8523         return 0;
8524 }
8525
8526 /**
8527  * Create specify domain meter policer rule.
8528  *
8529  * @param[in] fm
8530  *   Pointer to flow meter structure.
8531  * @param[in] mtb
8532  *   Pointer to DV meter table set.
8533  * @param[in] sfx_tb
8534  *   Pointer to suffix table.
8535  * @param[in] mtr_reg_c
8536  *   Color match REG_C.
8537  *
8538  * @return
8539  *   0 on success, -1 otherwise.
8540  */
8541 static int
8542 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8543                                     struct mlx5_meter_domain_info *dtb,
8544                                     struct mlx5_flow_tbl_resource *sfx_tb,
8545                                     uint8_t mtr_reg_c)
8546 {
8547         struct mlx5_flow_dv_match_params matcher = {
8548                 .size = sizeof(matcher.buf),
8549         };
8550         struct mlx5_flow_dv_match_params value = {
8551                 .size = sizeof(value.buf),
8552         };
8553         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8554         void *actions[METER_ACTIONS];
8555         int i;
8556
8557         /* Create jump action. */
8558         if (!sfx_tb)
8559                 return -1;
8560         if (!dtb->jump_actn)
8561                 dtb->jump_actn =
8562                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
8563                                                         (sfx_tb->obj);
8564         if (!dtb->jump_actn) {
8565                 DRV_LOG(ERR, "Failed to create policer jump action.");
8566                 goto error;
8567         }
8568         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8569                 int j = 0;
8570
8571                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8572                                        rte_col_2_mlx5_col(i), UINT8_MAX);
8573                 if (mtb->count_actns[i])
8574                         actions[j++] = mtb->count_actns[i];
8575                 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8576                         actions[j++] = mtb->drop_actn;
8577                 else
8578                         actions[j++] = dtb->jump_actn;
8579                 dtb->policer_rules[i] =
8580                         mlx5_glue->dv_create_flow(dtb->color_matcher,
8581                                                  (void *)&value,
8582                                                   j, actions);
8583                 if (!dtb->policer_rules[i]) {
8584                         DRV_LOG(ERR, "Failed to create policer rule.");
8585                         goto error;
8586                 }
8587         }
8588         return 0;
8589 error:
8590         rte_errno = errno;
8591         return -1;
8592 }
8593
8594 /**
8595  * Create policer rules.
8596  *
8597  * @param[in] dev
8598  *   Pointer to Ethernet device.
8599  * @param[in] fm
8600  *   Pointer to flow meter structure.
8601  * @param[in] attr
8602  *   Pointer to flow attributes.
8603  *
8604  * @return
8605  *   0 on success, -1 otherwise.
8606  */
8607 static int
8608 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8609                              struct mlx5_flow_meter *fm,
8610                              const struct rte_flow_attr *attr)
8611 {
8612         struct mlx5_priv *priv = dev->data->dev_private;
8613         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8614         int ret;
8615
8616         if (attr->egress) {
8617                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8618                                                 priv->sh->tx_mtr_sfx_tbl,
8619                                                 priv->mtr_color_reg);
8620                 if (ret) {
8621                         DRV_LOG(ERR, "Failed to create egress policer.");
8622                         goto error;
8623                 }
8624         }
8625         if (attr->ingress) {
8626                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8627                                                 priv->sh->rx_mtr_sfx_tbl,
8628                                                 priv->mtr_color_reg);
8629                 if (ret) {
8630                         DRV_LOG(ERR, "Failed to create ingress policer.");
8631                         goto error;
8632                 }
8633         }
8634         if (attr->transfer) {
8635                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8636                                                 priv->sh->fdb_mtr_sfx_tbl,
8637                                                 priv->mtr_color_reg);
8638                 if (ret) {
8639                         DRV_LOG(ERR, "Failed to create transfer policer.");
8640                         goto error;
8641                 }
8642         }
8643         return 0;
8644 error:
8645         flow_dv_destroy_policer_rules(dev, fm, attr);
8646         return -1;
8647 }
8648
8649 /**
8650  * Query a devx counter.
8651  *
8652  * @param[in] dev
8653  *   Pointer to the Ethernet device structure.
8654  * @param[in] cnt
8655  *   Pointer to the flow counter.
8656  * @param[in] clear
8657  *   Set to clear the counter statistics.
8658  * @param[out] pkts
8659  *   The statistics value of packets.
8660  * @param[out] bytes
8661  *   The statistics value of bytes.
8662  *
8663  * @return
8664  *   0 on success, otherwise return -1.
8665  */
8666 static int
8667 flow_dv_counter_query(struct rte_eth_dev *dev,
8668                       struct mlx5_flow_counter *cnt, bool clear,
8669                       uint64_t *pkts, uint64_t *bytes)
8670 {
8671         struct mlx5_priv *priv = dev->data->dev_private;
8672         uint64_t inn_pkts, inn_bytes;
8673         int ret;
8674
8675         if (!priv->config.devx)
8676                 return -1;
8677         ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8678         if (ret)
8679                 return -1;
8680         *pkts = inn_pkts - cnt->hits;
8681         *bytes = inn_bytes - cnt->bytes;
8682         if (clear) {
8683                 cnt->hits = inn_pkts;
8684                 cnt->bytes = inn_bytes;
8685         }
8686         return 0;
8687 }
8688
8689 /*
8690  * Mutex-protected thunk to lock-free  __flow_dv_translate().
8691  */
8692 static int
8693 flow_dv_translate(struct rte_eth_dev *dev,
8694                   struct mlx5_flow *dev_flow,
8695                   const struct rte_flow_attr *attr,
8696                   const struct rte_flow_item items[],
8697                   const struct rte_flow_action actions[],
8698                   struct rte_flow_error *error)
8699 {
8700         int ret;
8701
8702         flow_dv_shared_lock(dev);
8703         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8704         flow_dv_shared_unlock(dev);
8705         return ret;
8706 }
8707
8708 /*
8709  * Mutex-protected thunk to lock-free  __flow_dv_apply().
8710  */
8711 static int
8712 flow_dv_apply(struct rte_eth_dev *dev,
8713               struct rte_flow *flow,
8714               struct rte_flow_error *error)
8715 {
8716         int ret;
8717
8718         flow_dv_shared_lock(dev);
8719         ret = __flow_dv_apply(dev, flow, error);
8720         flow_dv_shared_unlock(dev);
8721         return ret;
8722 }
8723
8724 /*
8725  * Mutex-protected thunk to lock-free __flow_dv_remove().
8726  */
8727 static void
8728 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8729 {
8730         flow_dv_shared_lock(dev);
8731         __flow_dv_remove(dev, flow);
8732         flow_dv_shared_unlock(dev);
8733 }
8734
8735 /*
8736  * Mutex-protected thunk to lock-free __flow_dv_destroy().
8737  */
8738 static void
8739 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8740 {
8741         flow_dv_shared_lock(dev);
8742         __flow_dv_destroy(dev, flow);
8743         flow_dv_shared_unlock(dev);
8744 }
8745
8746 /*
8747  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8748  */
8749 static struct mlx5_flow_counter *
8750 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8751 {
8752         struct mlx5_flow_counter *cnt;
8753
8754         flow_dv_shared_lock(dev);
8755         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8756         flow_dv_shared_unlock(dev);
8757         return cnt;
8758 }
8759
8760 /*
8761  * Mutex-protected thunk to lock-free flow_dv_counter_release().
8762  */
8763 static void
8764 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8765 {
8766         flow_dv_shared_lock(dev);
8767         flow_dv_counter_release(dev, cnt);
8768         flow_dv_shared_unlock(dev);
8769 }
8770
8771 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8772         .validate = flow_dv_validate,
8773         .prepare = flow_dv_prepare,
8774         .translate = flow_dv_translate,
8775         .apply = flow_dv_apply,
8776         .remove = flow_dv_remove,
8777         .destroy = flow_dv_destroy,
8778         .query = flow_dv_query,
8779         .create_mtr_tbls = flow_dv_create_mtr_tbl,
8780         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8781         .create_policer_rules = flow_dv_create_policer_rules,
8782         .destroy_policer_rules = flow_dv_destroy_policer_rules,
8783         .counter_alloc = flow_dv_counter_allocate,
8784         .counter_free = flow_dv_counter_free,
8785         .counter_query = flow_dv_counter_query,
8786 };
8787
8788 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */