drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30
  31 #include "mlx5.h"
  32 #include "mlx5_defs.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35 #include "mlx5_prm.h"
  36 #include "mlx5_rxtx.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 /**
  74  * Initialize flow attributes structure according to flow items' types.
  75  *
  76  * @param[in] item
  77  *   Pointer to item specification.
  78  * @param[out] attr
  79  *   Pointer to flow attributes structure.
  80  */
  81 static void
  82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
  83 {
  84         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
  85                 switch (item->type) {
  86                 case RTE_FLOW_ITEM_TYPE_IPV4:
  87                         attr->ipv4 = 1;
  88                         break;
  89                 case RTE_FLOW_ITEM_TYPE_IPV6:
  90                         attr->ipv6 = 1;
  91                         break;
  92                 case RTE_FLOW_ITEM_TYPE_UDP:
  93                         attr->udp = 1;
  94                         break;
  95                 case RTE_FLOW_ITEM_TYPE_TCP:
  96                         attr->tcp = 1;
  97                         break;
  98                 default:
  99                         break;
 100                 }
 101         }
 102         attr->valid = 1;
 103 }
 104
 105 struct field_modify_info {
 106         uint32_t size; /* Size of field in protocol header, in bytes. */
 107         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 108         enum mlx5_modification_field id;
 109 };
 110
 111 struct field_modify_info modify_eth[] = {
 112         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 113         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 114         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 115         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 116         {0, 0, 0},
 117 };
 118
 119 struct field_modify_info modify_vlan_out_first_vid[] = {
 120         /* Size in bits !!! */
 121         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 122         {0, 0, 0},
 123 };
 124
 125 struct field_modify_info modify_ipv4[] = {
 126         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 127         {4, 12, MLX5_MODI_OUT_SIPV4},
 128         {4, 16, MLX5_MODI_OUT_DIPV4},
 129         {0, 0, 0},
 130 };
 131
 132 struct field_modify_info modify_ipv6[] = {
 133         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 134         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 135         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 136         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 137         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 138         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 139         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 140         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 141         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 142         {0, 0, 0},
 143 };
 144
 145 struct field_modify_info modify_udp[] = {
 146         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 147         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 148         {0, 0, 0},
 149 };
 150
 151 struct field_modify_info modify_tcp[] = {
 152         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 153         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 154         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 155         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 156         {0, 0, 0},
 157 };
 158
 159 static void
 160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 161                           uint8_t next_protocol, uint64_t *item_flags,
 162                           int *tunnel)
 163 {
 164         assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 165                item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 166         if (next_protocol == IPPROTO_IPIP) {
 167                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 168                 *tunnel = 1;
 169         }
 170         if (next_protocol == IPPROTO_IPV6) {
 171                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 172                 *tunnel = 1;
 173         }
 174 }
 175
 176 /**
 177  * Acquire the synchronizing object to protect multithreaded access
 178  * to shared dv context. Lock occurs only if context is actually
 179  * shared, i.e. we have multiport IB device and representors are
 180  * created.
 181  *
 182  * @param[in] dev
 183  *   Pointer to the rte_eth_dev structure.
 184  */
 185 static void
 186 flow_d_shared_lock(struct rte_eth_dev *dev)
 187 {
 188         struct mlx5_priv *priv = dev->data->dev_private;
 189         struct mlx5_ibv_shared *sh = priv->sh;
 190
 191         if (sh->dv_refcnt > 1) {
 192                 int ret;
 193
 194                 ret = pthread_mutex_lock(&sh->dv_mutex);
 195                 assert(!ret);
 196                 (void)ret;
 197         }
 198 }
 199
 200 static void
 201 flow_d_shared_unlock(struct rte_eth_dev *dev)
 202 {
 203         struct mlx5_priv *priv = dev->data->dev_private;
 204         struct mlx5_ibv_shared *sh = priv->sh;
 205
 206         if (sh->dv_refcnt > 1) {
 207                 int ret;
 208
 209                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 210                 assert(!ret);
 211                 (void)ret;
 212         }
 213 }
 214
 215 /* Update VLAN's VID/PCP based on input rte_flow_action.
 216  *
 217  * @param[in] action
 218  *   Pointer to struct rte_flow_action.
 219  * @param[out] vlan
 220  *   Pointer to struct rte_vlan_hdr.
 221  */
 222 static void
 223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 224                          struct rte_vlan_hdr *vlan)
 225 {
 226         uint16_t vlan_tci;
 227         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 228                 vlan_tci =
 229                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 230                                                action->conf)->vlan_pcp;
 231                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 232                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 233                 vlan->vlan_tci |= vlan_tci;
 234         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 235                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 236                 vlan->vlan_tci |= rte_be_to_cpu_16
 237                     (((const struct rte_flow_action_of_set_vlan_vid *)
 238                                              action->conf)->vlan_vid);
 239         }
 240 }
 241
 242 /**
 243  * Convert modify-header action to DV specification.
 244  *
 245  * @param[in] item
 246  *   Pointer to item specification.
 247  * @param[in] field
 248  *   Pointer to field modification information.
 249  * @param[in,out] resource
 250  *   Pointer to the modify-header resource.
 251  * @param[in] type
 252  *   Type of modification.
 253  * @param[out] error
 254  *   Pointer to the error structure.
 255  *
 256  * @return
 257  *   0 on success, a negative errno value otherwise and rte_errno is set.
 258  */
 259 static int
 260 flow_dv_convert_modify_action(struct rte_flow_item *item,
 261                               struct field_modify_info *field,
 262                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 263                               uint32_t type,
 264                               struct rte_flow_error *error)
 265 {
 266         uint32_t i = resource->actions_num;
 267         struct mlx5_modification_cmd *actions = resource->actions;
 268         const uint8_t *spec = item->spec;
 269         const uint8_t *mask = item->mask;
 270         uint32_t set;
 271
 272         while (field->size) {
 273                 set = 0;
 274                 /* Generate modify command for each mask segment. */
 275                 memcpy(&set, &mask[field->offset], field->size);
 276                 if (set) {
 277                         if (i >= MLX5_MODIFY_NUM)
 278                                 return rte_flow_error_set(error, EINVAL,
 279                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 280                                          "too many items to modify");
 281                         actions[i].action_type = type;
 282                         actions[i].field = field->id;
 283                         actions[i].length = field->size ==
 284                                         4 ? 0 : field->size * 8;
 285                         rte_memcpy(&actions[i].data[4 - field->size],
 286                                    &spec[field->offset], field->size);
 287                         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 288                         ++i;
 289                 }
 290                 if (resource->actions_num != i)
 291                         resource->actions_num = i;
 292                 field++;
 293         }
 294         if (!resource->actions_num)
 295                 return rte_flow_error_set(error, EINVAL,
 296                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 297                                           "invalid modification flow item");
 298         return 0;
 299 }
 300
 301 /**
 302  * Convert modify-header set IPv4 address action to DV specification.
 303  *
 304  * @param[in,out] resource
 305  *   Pointer to the modify-header resource.
 306  * @param[in] action
 307  *   Pointer to action specification.
 308  * @param[out] error
 309  *   Pointer to the error structure.
 310  *
 311  * @return
 312  *   0 on success, a negative errno value otherwise and rte_errno is set.
 313  */
 314 static int
 315 flow_dv_convert_action_modify_ipv4
 316                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 317                          const struct rte_flow_action *action,
 318                          struct rte_flow_error *error)
 319 {
 320         const struct rte_flow_action_set_ipv4 *conf =
 321                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 322         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 323         struct rte_flow_item_ipv4 ipv4;
 324         struct rte_flow_item_ipv4 ipv4_mask;
 325
 326         memset(&ipv4, 0, sizeof(ipv4));
 327         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 328         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 329                 ipv4.hdr.src_addr = conf->ipv4_addr;
 330                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 331         } else {
 332                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 333                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 334         }
 335         item.spec = &ipv4;
 336         item.mask = &ipv4_mask;
 337         return flow_dv_convert_modify_action(&item, modify_ipv4, resource,
 338                                              MLX5_MODIFICATION_TYPE_SET, error);
 339 }
 340
 341 /**
 342  * Convert modify-header set IPv6 address action to DV specification.
 343  *
 344  * @param[in,out] resource
 345  *   Pointer to the modify-header resource.
 346  * @param[in] action
 347  *   Pointer to action specification.
 348  * @param[out] error
 349  *   Pointer to the error structure.
 350  *
 351  * @return
 352  *   0 on success, a negative errno value otherwise and rte_errno is set.
 353  */
 354 static int
 355 flow_dv_convert_action_modify_ipv6
 356                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 357                          const struct rte_flow_action *action,
 358                          struct rte_flow_error *error)
 359 {
 360         const struct rte_flow_action_set_ipv6 *conf =
 361                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 362         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 363         struct rte_flow_item_ipv6 ipv6;
 364         struct rte_flow_item_ipv6 ipv6_mask;
 365
 366         memset(&ipv6, 0, sizeof(ipv6));
 367         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 368         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 369                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 370                        sizeof(ipv6.hdr.src_addr));
 371                 memcpy(&ipv6_mask.hdr.src_addr,
 372                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 373                        sizeof(ipv6.hdr.src_addr));
 374         } else {
 375                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 376                        sizeof(ipv6.hdr.dst_addr));
 377                 memcpy(&ipv6_mask.hdr.dst_addr,
 378                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 379                        sizeof(ipv6.hdr.dst_addr));
 380         }
 381         item.spec = &ipv6;
 382         item.mask = &ipv6_mask;
 383         return flow_dv_convert_modify_action(&item, modify_ipv6, resource,
 384                                              MLX5_MODIFICATION_TYPE_SET, error);
 385 }
 386
 387 /**
 388  * Convert modify-header set MAC address action to DV specification.
 389  *
 390  * @param[in,out] resource
 391  *   Pointer to the modify-header resource.
 392  * @param[in] action
 393  *   Pointer to action specification.
 394  * @param[out] error
 395  *   Pointer to the error structure.
 396  *
 397  * @return
 398  *   0 on success, a negative errno value otherwise and rte_errno is set.
 399  */
 400 static int
 401 flow_dv_convert_action_modify_mac
 402                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 403                          const struct rte_flow_action *action,
 404                          struct rte_flow_error *error)
 405 {
 406         const struct rte_flow_action_set_mac *conf =
 407                 (const struct rte_flow_action_set_mac *)(action->conf);
 408         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 409         struct rte_flow_item_eth eth;
 410         struct rte_flow_item_eth eth_mask;
 411
 412         memset(&eth, 0, sizeof(eth));
 413         memset(&eth_mask, 0, sizeof(eth_mask));
 414         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 415                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 416                        sizeof(eth.src.addr_bytes));
 417                 memcpy(&eth_mask.src.addr_bytes,
 418                        &rte_flow_item_eth_mask.src.addr_bytes,
 419                        sizeof(eth_mask.src.addr_bytes));
 420         } else {
 421                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 422                        sizeof(eth.dst.addr_bytes));
 423                 memcpy(&eth_mask.dst.addr_bytes,
 424                        &rte_flow_item_eth_mask.dst.addr_bytes,
 425                        sizeof(eth_mask.dst.addr_bytes));
 426         }
 427         item.spec = &eth;
 428         item.mask = &eth_mask;
 429         return flow_dv_convert_modify_action(&item, modify_eth, resource,
 430                                              MLX5_MODIFICATION_TYPE_SET, error);
 431 }
 432
 433 /**
 434  * Convert modify-header set VLAN VID action to DV specification.
 435  *
 436  * @param[in,out] resource
 437  *   Pointer to the modify-header resource.
 438  * @param[in] action
 439  *   Pointer to action specification.
 440  * @param[out] error
 441  *   Pointer to the error structure.
 442  *
 443  * @return
 444  *   0 on success, a negative errno value otherwise and rte_errno is set.
 445  */
 446 static int
 447 flow_dv_convert_action_modify_vlan_vid
 448                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 449                          const struct rte_flow_action *action,
 450                          struct rte_flow_error *error)
 451 {
 452         const struct rte_flow_action_of_set_vlan_vid *conf =
 453                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 454         int i = resource->actions_num;
 455         struct mlx5_modification_cmd *actions = &resource->actions[i];
 456         struct field_modify_info *field = modify_vlan_out_first_vid;
 457
 458         if (i >= MLX5_MODIFY_NUM)
 459                 return rte_flow_error_set(error, EINVAL,
 460                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 461                          "too many items to modify");
 462         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 463         actions[i].field = field->id;
 464         actions[i].length = field->size;
 465         actions[i].offset = field->offset;
 466         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 467         actions[i].data1 = conf->vlan_vid;
 468         actions[i].data1 = actions[i].data1 << 16;
 469         resource->actions_num = ++i;
 470         return 0;
 471 }
 472
 473 /**
 474  * Convert modify-header set TP action to DV specification.
 475  *
 476  * @param[in,out] resource
 477  *   Pointer to the modify-header resource.
 478  * @param[in] action
 479  *   Pointer to action specification.
 480  * @param[in] items
 481  *   Pointer to rte_flow_item objects list.
 482  * @param[in] attr
 483  *   Pointer to flow attributes structure.
 484  * @param[out] error
 485  *   Pointer to the error structure.
 486  *
 487  * @return
 488  *   0 on success, a negative errno value otherwise and rte_errno is set.
 489  */
 490 static int
 491 flow_dv_convert_action_modify_tp
 492                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 493                          const struct rte_flow_action *action,
 494                          const struct rte_flow_item *items,
 495                          union flow_dv_attr *attr,
 496                          struct rte_flow_error *error)
 497 {
 498         const struct rte_flow_action_set_tp *conf =
 499                 (const struct rte_flow_action_set_tp *)(action->conf);
 500         struct rte_flow_item item;
 501         struct rte_flow_item_udp udp;
 502         struct rte_flow_item_udp udp_mask;
 503         struct rte_flow_item_tcp tcp;
 504         struct rte_flow_item_tcp tcp_mask;
 505         struct field_modify_info *field;
 506
 507         if (!attr->valid)
 508                 flow_dv_attr_init(items, attr);
 509         if (attr->udp) {
 510                 memset(&udp, 0, sizeof(udp));
 511                 memset(&udp_mask, 0, sizeof(udp_mask));
 512                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 513                         udp.hdr.src_port = conf->port;
 514                         udp_mask.hdr.src_port =
 515                                         rte_flow_item_udp_mask.hdr.src_port;
 516                 } else {
 517                         udp.hdr.dst_port = conf->port;
 518                         udp_mask.hdr.dst_port =
 519                                         rte_flow_item_udp_mask.hdr.dst_port;
 520                 }
 521                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 522                 item.spec = &udp;
 523                 item.mask = &udp_mask;
 524                 field = modify_udp;
 525         }
 526         if (attr->tcp) {
 527                 memset(&tcp, 0, sizeof(tcp));
 528                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 529                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 530                         tcp.hdr.src_port = conf->port;
 531                         tcp_mask.hdr.src_port =
 532                                         rte_flow_item_tcp_mask.hdr.src_port;
 533                 } else {
 534                         tcp.hdr.dst_port = conf->port;
 535                         tcp_mask.hdr.dst_port =
 536                                         rte_flow_item_tcp_mask.hdr.dst_port;
 537                 }
 538                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 539                 item.spec = &tcp;
 540                 item.mask = &tcp_mask;
 541                 field = modify_tcp;
 542         }
 543         return flow_dv_convert_modify_action(&item, field, resource,
 544                                              MLX5_MODIFICATION_TYPE_SET, error);
 545 }
 546
 547 /**
 548  * Convert modify-header set TTL action to DV specification.
 549  *
 550  * @param[in,out] resource
 551  *   Pointer to the modify-header resource.
 552  * @param[in] action
 553  *   Pointer to action specification.
 554  * @param[in] items
 555  *   Pointer to rte_flow_item objects list.
 556  * @param[in] attr
 557  *   Pointer to flow attributes structure.
 558  * @param[out] error
 559  *   Pointer to the error structure.
 560  *
 561  * @return
 562  *   0 on success, a negative errno value otherwise and rte_errno is set.
 563  */
 564 static int
 565 flow_dv_convert_action_modify_ttl
 566                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 567                          const struct rte_flow_action *action,
 568                          const struct rte_flow_item *items,
 569                          union flow_dv_attr *attr,
 570                          struct rte_flow_error *error)
 571 {
 572         const struct rte_flow_action_set_ttl *conf =
 573                 (const struct rte_flow_action_set_ttl *)(action->conf);
 574         struct rte_flow_item item;
 575         struct rte_flow_item_ipv4 ipv4;
 576         struct rte_flow_item_ipv4 ipv4_mask;
 577         struct rte_flow_item_ipv6 ipv6;
 578         struct rte_flow_item_ipv6 ipv6_mask;
 579         struct field_modify_info *field;
 580
 581         if (!attr->valid)
 582                 flow_dv_attr_init(items, attr);
 583         if (attr->ipv4) {
 584                 memset(&ipv4, 0, sizeof(ipv4));
 585                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 586                 ipv4.hdr.time_to_live = conf->ttl_value;
 587                 ipv4_mask.hdr.time_to_live = 0xFF;
 588                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 589                 item.spec = &ipv4;
 590                 item.mask = &ipv4_mask;
 591                 field = modify_ipv4;
 592         }
 593         if (attr->ipv6) {
 594                 memset(&ipv6, 0, sizeof(ipv6));
 595                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 596                 ipv6.hdr.hop_limits = conf->ttl_value;
 597                 ipv6_mask.hdr.hop_limits = 0xFF;
 598                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 599                 item.spec = &ipv6;
 600                 item.mask = &ipv6_mask;
 601                 field = modify_ipv6;
 602         }
 603         return flow_dv_convert_modify_action(&item, field, resource,
 604                                              MLX5_MODIFICATION_TYPE_SET, error);
 605 }
 606
 607 /**
 608  * Convert modify-header decrement TTL action to DV specification.
 609  *
 610  * @param[in,out] resource
 611  *   Pointer to the modify-header resource.
 612  * @param[in] action
 613  *   Pointer to action specification.
 614  * @param[in] items
 615  *   Pointer to rte_flow_item objects list.
 616  * @param[in] attr
 617  *   Pointer to flow attributes structure.
 618  * @param[out] error
 619  *   Pointer to the error structure.
 620  *
 621  * @return
 622  *   0 on success, a negative errno value otherwise and rte_errno is set.
 623  */
 624 static int
 625 flow_dv_convert_action_modify_dec_ttl
 626                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 627                          const struct rte_flow_item *items,
 628                          union flow_dv_attr *attr,
 629                          struct rte_flow_error *error)
 630 {
 631         struct rte_flow_item item;
 632         struct rte_flow_item_ipv4 ipv4;
 633         struct rte_flow_item_ipv4 ipv4_mask;
 634         struct rte_flow_item_ipv6 ipv6;
 635         struct rte_flow_item_ipv6 ipv6_mask;
 636         struct field_modify_info *field;
 637
 638         if (!attr->valid)
 639                 flow_dv_attr_init(items, attr);
 640         if (attr->ipv4) {
 641                 memset(&ipv4, 0, sizeof(ipv4));
 642                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 643                 ipv4.hdr.time_to_live = 0xFF;
 644                 ipv4_mask.hdr.time_to_live = 0xFF;
 645                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 646                 item.spec = &ipv4;
 647                 item.mask = &ipv4_mask;
 648                 field = modify_ipv4;
 649         }
 650         if (attr->ipv6) {
 651                 memset(&ipv6, 0, sizeof(ipv6));
 652                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 653                 ipv6.hdr.hop_limits = 0xFF;
 654                 ipv6_mask.hdr.hop_limits = 0xFF;
 655                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 656                 item.spec = &ipv6;
 657                 item.mask = &ipv6_mask;
 658                 field = modify_ipv6;
 659         }
 660         return flow_dv_convert_modify_action(&item, field, resource,
 661                                              MLX5_MODIFICATION_TYPE_ADD, error);
 662 }
 663
 664 /**
 665  * Convert modify-header increment/decrement TCP Sequence number
 666  * to DV specification.
 667  *
 668  * @param[in,out] resource
 669  *   Pointer to the modify-header resource.
 670  * @param[in] action
 671  *   Pointer to action specification.
 672  * @param[out] error
 673  *   Pointer to the error structure.
 674  *
 675  * @return
 676  *   0 on success, a negative errno value otherwise and rte_errno is set.
 677  */
 678 static int
 679 flow_dv_convert_action_modify_tcp_seq
 680                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 681                          const struct rte_flow_action *action,
 682                          struct rte_flow_error *error)
 683 {
 684         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 685         uint64_t value = rte_be_to_cpu_32(*conf);
 686         struct rte_flow_item item;
 687         struct rte_flow_item_tcp tcp;
 688         struct rte_flow_item_tcp tcp_mask;
 689
 690         memset(&tcp, 0, sizeof(tcp));
 691         memset(&tcp_mask, 0, sizeof(tcp_mask));
 692         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 693                 /*
 694                  * The HW has no decrement operation, only increment operation.
 695                  * To simulate decrement X from Y using increment operation
 696                  * we need to add UINT32_MAX X times to Y.
 697                  * Each adding of UINT32_MAX decrements Y by 1.
 698                  */
 699                 value *= UINT32_MAX;
 700         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 701         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 702         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 703         item.spec = &tcp;
 704         item.mask = &tcp_mask;
 705         return flow_dv_convert_modify_action(&item, modify_tcp, resource,
 706                                              MLX5_MODIFICATION_TYPE_ADD, error);
 707 }
 708
 709 /**
 710  * Convert modify-header increment/decrement TCP Acknowledgment number
 711  * to DV specification.
 712  *
 713  * @param[in,out] resource
 714  *   Pointer to the modify-header resource.
 715  * @param[in] action
 716  *   Pointer to action specification.
 717  * @param[out] error
 718  *   Pointer to the error structure.
 719  *
 720  * @return
 721  *   0 on success, a negative errno value otherwise and rte_errno is set.
 722  */
 723 static int
 724 flow_dv_convert_action_modify_tcp_ack
 725                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 726                          const struct rte_flow_action *action,
 727                          struct rte_flow_error *error)
 728 {
 729         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 730         uint64_t value = rte_be_to_cpu_32(*conf);
 731         struct rte_flow_item item;
 732         struct rte_flow_item_tcp tcp;
 733         struct rte_flow_item_tcp tcp_mask;
 734
 735         memset(&tcp, 0, sizeof(tcp));
 736         memset(&tcp_mask, 0, sizeof(tcp_mask));
 737         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 738                 /*
 739                  * The HW has no decrement operation, only increment operation.
 740                  * To simulate decrement X from Y using increment operation
 741                  * we need to add UINT32_MAX X times to Y.
 742                  * Each adding of UINT32_MAX decrements Y by 1.
 743                  */
 744                 value *= UINT32_MAX;
 745         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 746         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 747         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 748         item.spec = &tcp;
 749         item.mask = &tcp_mask;
 750         return flow_dv_convert_modify_action(&item, modify_tcp, resource,
 751                                              MLX5_MODIFICATION_TYPE_ADD, error);
 752 }
 753
 754 static enum mlx5_modification_field reg_to_field[] = {
 755         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 756         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 757         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 758         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 759         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 760         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 761         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 762         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 763         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 764         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 765 };
 766
 767 /**
 768  * Convert register set to DV specification.
 769  *
 770  * @param[in,out] resource
 771  *   Pointer to the modify-header resource.
 772  * @param[in] action
 773  *   Pointer to action specification.
 774  * @param[out] error
 775  *   Pointer to the error structure.
 776  *
 777  * @return
 778  *   0 on success, a negative errno value otherwise and rte_errno is set.
 779  */
 780 static int
 781 flow_dv_convert_action_set_reg
 782                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 783                          const struct rte_flow_action *action,
 784                          struct rte_flow_error *error)
 785 {
 786         const struct mlx5_rte_flow_action_set_tag *conf = (action->conf);
 787         struct mlx5_modification_cmd *actions = resource->actions;
 788         uint32_t i = resource->actions_num;
 789
 790         if (i >= MLX5_MODIFY_NUM)
 791                 return rte_flow_error_set(error, EINVAL,
 792                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 793                                           "too many items to modify");
 794         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 795         actions[i].field = reg_to_field[conf->id];
 796         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 797         actions[i].data1 = conf->data;
 798         ++i;
 799         resource->actions_num = i;
 800         if (!resource->actions_num)
 801                 return rte_flow_error_set(error, EINVAL,
 802                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 803                                           "invalid modification flow item");
 804         return 0;
 805 }
 806
 807 /**
 808  * Validate META item.
 809  *
 810  * @param[in] dev
 811  *   Pointer to the rte_eth_dev structure.
 812  * @param[in] item
 813  *   Item specification.
 814  * @param[in] attr
 815  *   Attributes of flow that includes this item.
 816  * @param[out] error
 817  *   Pointer to error structure.
 818  *
 819  * @return
 820  *   0 on success, a negative errno value otherwise and rte_errno is set.
 821  */
 822 static int
 823 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
 824                            const struct rte_flow_item *item,
 825                            const struct rte_flow_attr *attr,
 826                            struct rte_flow_error *error)
 827 {
 828         const struct rte_flow_item_meta *spec = item->spec;
 829         const struct rte_flow_item_meta *mask = item->mask;
 830         const struct rte_flow_item_meta nic_mask = {
 831                 .data = RTE_BE32(UINT32_MAX)
 832         };
 833         int ret;
 834         uint64_t offloads = dev->data->dev_conf.txmode.offloads;
 835
 836         if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
 837                 return rte_flow_error_set(error, EPERM,
 838                                           RTE_FLOW_ERROR_TYPE_ITEM,
 839                                           NULL,
 840                                           "match on metadata offload "
 841                                           "configuration is off for this port");
 842         if (!spec)
 843                 return rte_flow_error_set(error, EINVAL,
 844                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
 845                                           item->spec,
 846                                           "data cannot be empty");
 847         if (!spec->data)
 848                 return rte_flow_error_set(error, EINVAL,
 849                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
 850                                           NULL,
 851                                           "data cannot be zero");
 852         if (!mask)
 853                 mask = &rte_flow_item_meta_mask;
 854         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
 855                                         (const uint8_t *)&nic_mask,
 856                                         sizeof(struct rte_flow_item_meta),
 857                                         error);
 858         if (ret < 0)
 859                 return ret;
 860         if (attr->ingress)
 861                 return rte_flow_error_set(error, ENOTSUP,
 862                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 863                                           NULL,
 864                                           "pattern not supported for ingress");
 865         return 0;
 866 }
 867
 868 /**
 869  * Validate vport item.
 870  *
 871  * @param[in] dev
 872  *   Pointer to the rte_eth_dev structure.
 873  * @param[in] item
 874  *   Item specification.
 875  * @param[in] attr
 876  *   Attributes of flow that includes this item.
 877  * @param[in] item_flags
 878  *   Bit-fields that holds the items detected until now.
 879  * @param[out] error
 880  *   Pointer to error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
 887                               const struct rte_flow_item *item,
 888                               const struct rte_flow_attr *attr,
 889                               uint64_t item_flags,
 890                               struct rte_flow_error *error)
 891 {
 892         const struct rte_flow_item_port_id *spec = item->spec;
 893         const struct rte_flow_item_port_id *mask = item->mask;
 894         const struct rte_flow_item_port_id switch_mask = {
 895                         .id = 0xffffffff,
 896         };
 897         struct mlx5_priv *esw_priv;
 898         struct mlx5_priv *dev_priv;
 899         int ret;
 900
 901         if (!attr->transfer)
 902                 return rte_flow_error_set(error, EINVAL,
 903                                           RTE_FLOW_ERROR_TYPE_ITEM,
 904                                           NULL,
 905                                           "match on port id is valid only"
 906                                           " when transfer flag is enabled");
 907         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
 908                 return rte_flow_error_set(error, ENOTSUP,
 909                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
 910                                           "multiple source ports are not"
 911                                           " supported");
 912         if (!mask)
 913                 mask = &switch_mask;
 914         if (mask->id != 0xffffffff)
 915                 return rte_flow_error_set(error, ENOTSUP,
 916                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
 917                                            mask,
 918                                            "no support for partial mask on"
 919                                            " \"id\" field");
 920         ret = mlx5_flow_item_acceptable
 921                                 (item, (const uint8_t *)mask,
 922                                  (const uint8_t *)&rte_flow_item_port_id_mask,
 923                                  sizeof(struct rte_flow_item_port_id),
 924                                  error);
 925         if (ret)
 926                 return ret;
 927         if (!spec)
 928                 return 0;
 929         esw_priv = mlx5_port_to_eswitch_info(spec->id);
 930         if (!esw_priv)
 931                 return rte_flow_error_set(error, rte_errno,
 932                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
 933                                           "failed to obtain E-Switch info for"
 934                                           " port");
 935         dev_priv = mlx5_dev_to_eswitch_info(dev);
 936         if (!dev_priv)
 937                 return rte_flow_error_set(error, rte_errno,
 938                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 939                                           NULL,
 940                                           "failed to obtain E-Switch info");
 941         if (esw_priv->domain_id != dev_priv->domain_id)
 942                 return rte_flow_error_set(error, EINVAL,
 943                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
 944                                           "cannot match on a port from a"
 945                                           " different E-Switch");
 946         return 0;
 947 }
 948
 949 /**
 950  * Validate the pop VLAN action.
 951  *
 952  * @param[in] dev
 953  *   Pointer to the rte_eth_dev structure.
 954  * @param[in] action_flags
 955  *   Holds the actions detected until now.
 956  * @param[in] action
 957  *   Pointer to the pop vlan action.
 958  * @param[in] item_flags
 959  *   The items found in this flow rule.
 960  * @param[in] attr
 961  *   Pointer to flow attributes.
 962  * @param[out] error
 963  *   Pointer to error structure.
 964  *
 965  * @return
 966  *   0 on success, a negative errno value otherwise and rte_errno is set.
 967  */
 968 static int
 969 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
 970                                  uint64_t action_flags,
 971                                  const struct rte_flow_action *action,
 972                                  uint64_t item_flags,
 973                                  const struct rte_flow_attr *attr,
 974                                  struct rte_flow_error *error)
 975 {
 976         struct mlx5_priv *priv = dev->data->dev_private;
 977
 978         (void)action;
 979         (void)attr;
 980         if (!priv->sh->pop_vlan_action)
 981                 return rte_flow_error_set(error, ENOTSUP,
 982                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 983                                           NULL,
 984                                           "pop vlan action is not supported");
 985         /*
 986          * Check for inconsistencies:
 987          *  fail strip_vlan in a flow that matches packets without VLAN tags.
 988          *  fail strip_vlan in a flow that matches packets without explicitly a
 989          *  matching on VLAN tag ?
 990          */
 991         if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
 992                 return rte_flow_error_set(error, ENOTSUP,
 993                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 994                                           NULL,
 995                                           "no support for multiple vlan pop "
 996                                           "actions");
 997         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
 998                 return rte_flow_error_set(error, ENOTSUP,
 999                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1000                                           NULL,
1001                                           "cannot pop vlan without a "
1002                                           "match on (outer) vlan in the flow");
1003         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1004                 return rte_flow_error_set(error, EINVAL,
1005                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1006                                           "wrong action order, port_id should "
1007                                           "be after pop VLAN action");
1008         return 0;
1009 }
1010
1011 /**
1012  * Get VLAN default info from vlan match info.
1013  *
1014  * @param[in] dev
1015  *   Pointer to the rte_eth_dev structure.
1016  * @param[in] item
1017  *   the list of item specifications.
1018  * @param[out] vlan
1019  *   pointer VLAN info to fill to.
1020  * @param[out] error
1021  *   Pointer to error structure.
1022  *
1023  * @return
1024  *   0 on success, a negative errno value otherwise and rte_errno is set.
1025  */
1026 static void
1027 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1028                                   struct rte_vlan_hdr *vlan)
1029 {
1030         const struct rte_flow_item_vlan nic_mask = {
1031                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1032                                 MLX5DV_FLOW_VLAN_VID_MASK),
1033                 .inner_type = RTE_BE16(0xffff),
1034         };
1035
1036         if (items == NULL)
1037                 return;
1038         for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1039                items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1040                 ;
1041         if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1042                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1043                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1044
1045                 if (!vlan_m)
1046                         vlan_m = &nic_mask;
1047                 /* Only full match values are accepted */
1048                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1049                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1050                         vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1051                         vlan->vlan_tci |=
1052                                 rte_be_to_cpu_16(vlan_v->tci &
1053                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1054                 }
1055                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1056                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1057                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1058                         vlan->vlan_tci |=
1059                                 rte_be_to_cpu_16(vlan_v->tci &
1060                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1061                 }
1062                 if (vlan_m->inner_type == nic_mask.inner_type)
1063                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1064                                                            vlan_m->inner_type);
1065         }
1066 }
1067
1068 /**
1069  * Validate the push VLAN action.
1070  *
1071  * @param[in] action_flags
1072  *   Holds the actions detected until now.
1073  * @param[in] action
1074  *   Pointer to the encap action.
1075  * @param[in] attr
1076  *   Pointer to flow attributes
1077  * @param[out] error
1078  *   Pointer to error structure.
1079  *
1080  * @return
1081  *   0 on success, a negative errno value otherwise and rte_errno is set.
1082  */
1083 static int
1084 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1085                                   uint64_t item_flags,
1086                                   const struct rte_flow_action *action,
1087                                   const struct rte_flow_attr *attr,
1088                                   struct rte_flow_error *error)
1089 {
1090         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1091
1092         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1093             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1094                 return rte_flow_error_set(error, EINVAL,
1095                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1096                                           "invalid vlan ethertype");
1097         if (action_flags &
1098                 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1099                 return rte_flow_error_set(error, ENOTSUP,
1100                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1101                                           "no support for multiple VLAN "
1102                                           "actions");
1103         if (!mlx5_flow_find_action
1104                         (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1105             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1106                 return rte_flow_error_set(error, ENOTSUP,
1107                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
1108                                 "push VLAN needs to match on VLAN in order to "
1109                                 "get VLAN VID information because there is "
1110                                 "no followed set VLAN VID action");
1111         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1112                 return rte_flow_error_set(error, EINVAL,
1113                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1114                                           "wrong action order, port_id should "
1115                                           "be after push VLAN");
1116         (void)attr;
1117         return 0;
1118 }
1119
1120 /**
1121  * Validate the set VLAN PCP.
1122  *
1123  * @param[in] action_flags
1124  *   Holds the actions detected until now.
1125  * @param[in] actions
1126  *   Pointer to the list of actions remaining in the flow rule.
1127  * @param[in] attr
1128  *   Pointer to flow attributes
1129  * @param[out] error
1130  *   Pointer to error structure.
1131  *
1132  * @return
1133  *   0 on success, a negative errno value otherwise and rte_errno is set.
1134  */
1135 static int
1136 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1137                                      const struct rte_flow_action actions[],
1138                                      struct rte_flow_error *error)
1139 {
1140         const struct rte_flow_action *action = actions;
1141         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1142
1143         if (conf->vlan_pcp > 7)
1144                 return rte_flow_error_set(error, EINVAL,
1145                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1146                                           "VLAN PCP value is too big");
1147         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1148                 return rte_flow_error_set(error, ENOTSUP,
1149                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1150                                           "set VLAN PCP action must follow "
1151                                           "the push VLAN action");
1152         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1153                 return rte_flow_error_set(error, ENOTSUP,
1154                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1155                                           "Multiple VLAN PCP modification are "
1156                                           "not supported");
1157         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1158                 return rte_flow_error_set(error, EINVAL,
1159                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1160                                           "wrong action order, port_id should "
1161                                           "be after set VLAN PCP");
1162         return 0;
1163 }
1164
1165 /**
1166  * Validate the set VLAN VID.
1167  *
1168  * @param[in] item_flags
1169  *   Holds the items detected in this rule.
1170  * @param[in] actions
1171  *   Pointer to the list of actions remaining in the flow rule.
1172  * @param[in] attr
1173  *   Pointer to flow attributes
1174  * @param[out] error
1175  *   Pointer to error structure.
1176  *
1177  * @return
1178  *   0 on success, a negative errno value otherwise and rte_errno is set.
1179  */
1180 static int
1181 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1182                                      uint64_t action_flags,
1183                                      const struct rte_flow_action actions[],
1184                                      struct rte_flow_error *error)
1185 {
1186         const struct rte_flow_action *action = actions;
1187         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1188
1189         if (conf->vlan_vid > RTE_BE16(0xFFE))
1190                 return rte_flow_error_set(error, EINVAL,
1191                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1192                                           "VLAN VID value is too big");
1193         /* there is an of_push_vlan action before us */
1194         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1195                 if (mlx5_flow_find_action(actions + 1,
1196                                           RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1197                         return rte_flow_error_set(error, ENOTSUP,
1198                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
1199                                         "Multiple VLAN VID modifications are "
1200                                         "not supported");
1201                 else
1202                         return 0;
1203         }
1204
1205         /*
1206          * Action is on an existing VLAN header:
1207          *    Need to verify this is a single modify CID action.
1208          *   Rule mast include a match on outer VLAN.
1209          */
1210         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1211                 return rte_flow_error_set(error, ENOTSUP,
1212                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1213                                           "Multiple VLAN VID modifications are "
1214                                           "not supported");
1215         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1216                 return rte_flow_error_set(error, EINVAL,
1217                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1218                                           "match on VLAN is required in order "
1219                                           "to set VLAN VID");
1220         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1221                 return rte_flow_error_set(error, EINVAL,
1222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1223                                           "wrong action order, port_id should "
1224                                           "be after set VLAN VID");
1225         return 0;
1226 }
1227
1228 /**
1229  * Validate count action.
1230  *
1231  * @param[in] dev
1232  *   device otr.
1233  * @param[out] error
1234  *   Pointer to error structure.
1235  *
1236  * @return
1237  *   0 on success, a negative errno value otherwise and rte_errno is set.
1238  */
1239 static int
1240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1241                               struct rte_flow_error *error)
1242 {
1243         struct mlx5_priv *priv = dev->data->dev_private;
1244
1245         if (!priv->config.devx)
1246                 goto notsup_err;
1247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1248         return 0;
1249 #endif
1250 notsup_err:
1251         return rte_flow_error_set
1252                       (error, ENOTSUP,
1253                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1254                        NULL,
1255                        "count action not supported");
1256 }
1257
1258 /**
1259  * Validate the L2 encap action.
1260  *
1261  * @param[in] action_flags
1262  *   Holds the actions detected until now.
1263  * @param[in] action
1264  *   Pointer to the encap action.
1265  * @param[in] attr
1266  *   Pointer to flow attributes
1267  * @param[out] error
1268  *   Pointer to error structure.
1269  *
1270  * @return
1271  *   0 on success, a negative errno value otherwise and rte_errno is set.
1272  */
1273 static int
1274 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1275                                  const struct rte_flow_action *action,
1276                                  const struct rte_flow_attr *attr,
1277                                  struct rte_flow_error *error)
1278 {
1279         if (!(action->conf))
1280                 return rte_flow_error_set(error, EINVAL,
1281                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1282                                           "configuration cannot be null");
1283         if (action_flags & MLX5_FLOW_ACTION_DROP)
1284                 return rte_flow_error_set(error, EINVAL,
1285                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1286                                           "can't drop and encap in same flow");
1287         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1288                 return rte_flow_error_set(error, EINVAL,
1289                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1290                                           "can only have a single encap or"
1291                                           " decap action in a flow");
1292         if (!attr->transfer && attr->ingress)
1293                 return rte_flow_error_set(error, ENOTSUP,
1294                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1295                                           NULL,
1296                                           "encap action not supported for "
1297                                           "ingress");
1298         return 0;
1299 }
1300
1301 /**
1302  * Validate the L2 decap action.
1303  *
1304  * @param[in] action_flags
1305  *   Holds the actions detected until now.
1306  * @param[in] attr
1307  *   Pointer to flow attributes
1308  * @param[out] error
1309  *   Pointer to error structure.
1310  *
1311  * @return
1312  *   0 on success, a negative errno value otherwise and rte_errno is set.
1313  */
1314 static int
1315 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1316                                  const struct rte_flow_attr *attr,
1317                                  struct rte_flow_error *error)
1318 {
1319         if (action_flags & MLX5_FLOW_ACTION_DROP)
1320                 return rte_flow_error_set(error, EINVAL,
1321                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1322                                           "can't drop and decap in same flow");
1323         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1324                 return rte_flow_error_set(error, EINVAL,
1325                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1326                                           "can only have a single encap or"
1327                                           " decap action in a flow");
1328         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1329                 return rte_flow_error_set(error, EINVAL,
1330                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1331                                           "can't have decap action after"
1332                                           " modify action");
1333         if (attr->egress)
1334                 return rte_flow_error_set(error, ENOTSUP,
1335                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1336                                           NULL,
1337                                           "decap action not supported for "
1338                                           "egress");
1339         return 0;
1340 }
1341
1342 /**
1343  * Validate the raw encap action.
1344  *
1345  * @param[in] action_flags
1346  *   Holds the actions detected until now.
1347  * @param[in] action
1348  *   Pointer to the encap action.
1349  * @param[in] attr
1350  *   Pointer to flow attributes
1351  * @param[out] error
1352  *   Pointer to error structure.
1353  *
1354  * @return
1355  *   0 on success, a negative errno value otherwise and rte_errno is set.
1356  */
1357 static int
1358 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1359                                   const struct rte_flow_action *action,
1360                                   const struct rte_flow_attr *attr,
1361                                   struct rte_flow_error *error)
1362 {
1363         const struct rte_flow_action_raw_encap *raw_encap =
1364                 (const struct rte_flow_action_raw_encap *)action->conf;
1365         if (!(action->conf))
1366                 return rte_flow_error_set(error, EINVAL,
1367                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1368                                           "configuration cannot be null");
1369         if (action_flags & MLX5_FLOW_ACTION_DROP)
1370                 return rte_flow_error_set(error, EINVAL,
1371                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1372                                           "can't drop and encap in same flow");
1373         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1374                 return rte_flow_error_set(error, EINVAL,
1375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1376                                           "can only have a single encap"
1377                                           " action in a flow");
1378         /* encap without preceding decap is not supported for ingress */
1379         if (!attr->transfer &&  attr->ingress &&
1380             !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1381                 return rte_flow_error_set(error, ENOTSUP,
1382                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1383                                           NULL,
1384                                           "encap action not supported for "
1385                                           "ingress");
1386         if (!raw_encap->size || !raw_encap->data)
1387                 return rte_flow_error_set(error, EINVAL,
1388                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1389                                           "raw encap data cannot be empty");
1390         return 0;
1391 }
1392
1393 /**
1394  * Validate the raw decap action.
1395  *
1396  * @param[in] action_flags
1397  *   Holds the actions detected until now.
1398  * @param[in] action
1399  *   Pointer to the encap action.
1400  * @param[in] attr
1401  *   Pointer to flow attributes
1402  * @param[out] error
1403  *   Pointer to error structure.
1404  *
1405  * @return
1406  *   0 on success, a negative errno value otherwise and rte_errno is set.
1407  */
1408 static int
1409 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1410                                   const struct rte_flow_action *action,
1411                                   const struct rte_flow_attr *attr,
1412                                   struct rte_flow_error *error)
1413 {
1414         if (action_flags & MLX5_FLOW_ACTION_DROP)
1415                 return rte_flow_error_set(error, EINVAL,
1416                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1417                                           "can't drop and decap in same flow");
1418         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1419                 return rte_flow_error_set(error, EINVAL,
1420                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1421                                           "can't have encap action before"
1422                                           " decap action");
1423         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1424                 return rte_flow_error_set(error, EINVAL,
1425                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1426                                           "can only have a single decap"
1427                                           " action in a flow");
1428         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1431                                           "can't have decap action after"
1432                                           " modify action");
1433         /* decap action is valid on egress only if it is followed by encap */
1434         if (attr->egress) {
1435                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1436                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1437                        action++) {
1438                 }
1439                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1440                         return rte_flow_error_set
1441                                         (error, ENOTSUP,
1442                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1443                                          NULL, "decap action not supported"
1444                                          " for egress");
1445         }
1446         return 0;
1447 }
1448
1449 /**
1450  * Find existing encap/decap resource or create and register a new one.
1451  *
1452  * @param dev[in, out]
1453  *   Pointer to rte_eth_dev structure.
1454  * @param[in, out] resource
1455  *   Pointer to encap/decap resource.
1456  * @parm[in, out] dev_flow
1457  *   Pointer to the dev_flow.
1458  * @param[out] error
1459  *   pointer to error structure.
1460  *
1461  * @return
1462  *   0 on success otherwise -errno and errno is set.
1463  */
1464 static int
1465 flow_dv_encap_decap_resource_register
1466                         (struct rte_eth_dev *dev,
1467                          struct mlx5_flow_dv_encap_decap_resource *resource,
1468                          struct mlx5_flow *dev_flow,
1469                          struct rte_flow_error *error)
1470 {
1471         struct mlx5_priv *priv = dev->data->dev_private;
1472         struct mlx5_ibv_shared *sh = priv->sh;
1473         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1474         struct rte_flow *flow = dev_flow->flow;
1475         struct mlx5dv_dr_domain *domain;
1476
1477         resource->flags = flow->group ? 0 : 1;
1478         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1479                 domain = sh->fdb_domain;
1480         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1481                 domain = sh->rx_domain;
1482         else
1483                 domain = sh->tx_domain;
1484
1485         /* Lookup a matching resource from cache. */
1486         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1487                 if (resource->reformat_type == cache_resource->reformat_type &&
1488                     resource->ft_type == cache_resource->ft_type &&
1489                     resource->flags == cache_resource->flags &&
1490                     resource->size == cache_resource->size &&
1491                     !memcmp((const void *)resource->buf,
1492                             (const void *)cache_resource->buf,
1493                             resource->size)) {
1494                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1495                                 (void *)cache_resource,
1496                                 rte_atomic32_read(&cache_resource->refcnt));
1497                         rte_atomic32_inc(&cache_resource->refcnt);
1498                         dev_flow->dv.encap_decap = cache_resource;
1499                         return 0;
1500                 }
1501         }
1502         /* Register new encap/decap resource. */
1503         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1504         if (!cache_resource)
1505                 return rte_flow_error_set(error, ENOMEM,
1506                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1507                                           "cannot allocate resource memory");
1508         *cache_resource = *resource;
1509         cache_resource->verbs_action =
1510                 mlx5_glue->dv_create_flow_action_packet_reformat
1511                         (sh->ctx, cache_resource->reformat_type,
1512                          cache_resource->ft_type, domain, cache_resource->flags,
1513                          cache_resource->size,
1514                          (cache_resource->size ? cache_resource->buf : NULL));
1515         if (!cache_resource->verbs_action) {
1516                 rte_free(cache_resource);
1517                 return rte_flow_error_set(error, ENOMEM,
1518                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1519                                           NULL, "cannot create action");
1520         }
1521         rte_atomic32_init(&cache_resource->refcnt);
1522         rte_atomic32_inc(&cache_resource->refcnt);
1523         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1524         dev_flow->dv.encap_decap = cache_resource;
1525         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1526                 (void *)cache_resource,
1527                 rte_atomic32_read(&cache_resource->refcnt));
1528         return 0;
1529 }
1530
1531 /**
1532  * Find existing table jump resource or create and register a new one.
1533  *
1534  * @param dev[in, out]
1535  *   Pointer to rte_eth_dev structure.
1536  * @param[in, out] resource
1537  *   Pointer to jump table resource.
1538  * @parm[in, out] dev_flow
1539  *   Pointer to the dev_flow.
1540  * @param[out] error
1541  *   pointer to error structure.
1542  *
1543  * @return
1544  *   0 on success otherwise -errno and errno is set.
1545  */
1546 static int
1547 flow_dv_jump_tbl_resource_register
1548                         (struct rte_eth_dev *dev,
1549                          struct mlx5_flow_dv_jump_tbl_resource *resource,
1550                          struct mlx5_flow *dev_flow,
1551                          struct rte_flow_error *error)
1552 {
1553         struct mlx5_priv *priv = dev->data->dev_private;
1554         struct mlx5_ibv_shared *sh = priv->sh;
1555         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1556
1557         /* Lookup a matching resource from cache. */
1558         LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1559                 if (resource->tbl == cache_resource->tbl) {
1560                         DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1561                                 (void *)cache_resource,
1562                                 rte_atomic32_read(&cache_resource->refcnt));
1563                         rte_atomic32_inc(&cache_resource->refcnt);
1564                         dev_flow->dv.jump = cache_resource;
1565                         return 0;
1566                 }
1567         }
1568         /* Register new jump table resource. */
1569         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1570         if (!cache_resource)
1571                 return rte_flow_error_set(error, ENOMEM,
1572                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1573                                           "cannot allocate resource memory");
1574         *cache_resource = *resource;
1575         cache_resource->action =
1576                 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1577                 (resource->tbl->obj);
1578         if (!cache_resource->action) {
1579                 rte_free(cache_resource);
1580                 return rte_flow_error_set(error, ENOMEM,
1581                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1582                                           NULL, "cannot create action");
1583         }
1584         rte_atomic32_init(&cache_resource->refcnt);
1585         rte_atomic32_inc(&cache_resource->refcnt);
1586         LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1587         dev_flow->dv.jump = cache_resource;
1588         DRV_LOG(DEBUG, "new jump table  resource %p: refcnt %d++",
1589                 (void *)cache_resource,
1590                 rte_atomic32_read(&cache_resource->refcnt));
1591         return 0;
1592 }
1593
1594 /**
1595  * Find existing table port ID resource or create and register a new one.
1596  *
1597  * @param dev[in, out]
1598  *   Pointer to rte_eth_dev structure.
1599  * @param[in, out] resource
1600  *   Pointer to port ID action resource.
1601  * @parm[in, out] dev_flow
1602  *   Pointer to the dev_flow.
1603  * @param[out] error
1604  *   pointer to error structure.
1605  *
1606  * @return
1607  *   0 on success otherwise -errno and errno is set.
1608  */
1609 static int
1610 flow_dv_port_id_action_resource_register
1611                         (struct rte_eth_dev *dev,
1612                          struct mlx5_flow_dv_port_id_action_resource *resource,
1613                          struct mlx5_flow *dev_flow,
1614                          struct rte_flow_error *error)
1615 {
1616         struct mlx5_priv *priv = dev->data->dev_private;
1617         struct mlx5_ibv_shared *sh = priv->sh;
1618         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1619
1620         /* Lookup a matching resource from cache. */
1621         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1622                 if (resource->port_id == cache_resource->port_id) {
1623                         DRV_LOG(DEBUG, "port id action resource resource %p: "
1624                                 "refcnt %d++",
1625                                 (void *)cache_resource,
1626                                 rte_atomic32_read(&cache_resource->refcnt));
1627                         rte_atomic32_inc(&cache_resource->refcnt);
1628                         dev_flow->dv.port_id_action = cache_resource;
1629                         return 0;
1630                 }
1631         }
1632         /* Register new port id action resource. */
1633         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1634         if (!cache_resource)
1635                 return rte_flow_error_set(error, ENOMEM,
1636                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1637                                           "cannot allocate resource memory");
1638         *cache_resource = *resource;
1639         cache_resource->action =
1640                 mlx5_glue->dr_create_flow_action_dest_vport
1641                         (priv->sh->fdb_domain, resource->port_id);
1642         if (!cache_resource->action) {
1643                 rte_free(cache_resource);
1644                 return rte_flow_error_set(error, ENOMEM,
1645                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1646                                           NULL, "cannot create action");
1647         }
1648         rte_atomic32_init(&cache_resource->refcnt);
1649         rte_atomic32_inc(&cache_resource->refcnt);
1650         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1651         dev_flow->dv.port_id_action = cache_resource;
1652         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1653                 (void *)cache_resource,
1654                 rte_atomic32_read(&cache_resource->refcnt));
1655         return 0;
1656 }
1657
1658 /**
1659  * Find existing push vlan resource or create and register a new one.
1660  *
1661  * @param dev[in, out]
1662  *   Pointer to rte_eth_dev structure.
1663  * @param[in, out] resource
1664  *   Pointer to port ID action resource.
1665  * @parm[in, out] dev_flow
1666  *   Pointer to the dev_flow.
1667  * @param[out] error
1668  *   pointer to error structure.
1669  *
1670  * @return
1671  *   0 on success otherwise -errno and errno is set.
1672  */
1673 static int
1674 flow_dv_push_vlan_action_resource_register
1675                        (struct rte_eth_dev *dev,
1676                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
1677                         struct mlx5_flow *dev_flow,
1678                         struct rte_flow_error *error)
1679 {
1680         struct mlx5_priv *priv = dev->data->dev_private;
1681         struct mlx5_ibv_shared *sh = priv->sh;
1682         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1683         struct mlx5dv_dr_domain *domain;
1684
1685         /* Lookup a matching resource from cache. */
1686         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1687                 if (resource->vlan_tag == cache_resource->vlan_tag &&
1688                     resource->ft_type == cache_resource->ft_type) {
1689                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1690                                 "refcnt %d++",
1691                                 (void *)cache_resource,
1692                                 rte_atomic32_read(&cache_resource->refcnt));
1693                         rte_atomic32_inc(&cache_resource->refcnt);
1694                         dev_flow->dv.push_vlan_res = cache_resource;
1695                         return 0;
1696                 }
1697         }
1698         /* Register new push_vlan action resource. */
1699         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1700         if (!cache_resource)
1701                 return rte_flow_error_set(error, ENOMEM,
1702                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1703                                           "cannot allocate resource memory");
1704         *cache_resource = *resource;
1705         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1706                 domain = sh->fdb_domain;
1707         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1708                 domain = sh->rx_domain;
1709         else
1710                 domain = sh->tx_domain;
1711         cache_resource->action =
1712                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1713                                                            resource->vlan_tag);
1714         if (!cache_resource->action) {
1715                 rte_free(cache_resource);
1716                 return rte_flow_error_set(error, ENOMEM,
1717                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1718                                           NULL, "cannot create action");
1719         }
1720         rte_atomic32_init(&cache_resource->refcnt);
1721         rte_atomic32_inc(&cache_resource->refcnt);
1722         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1723         dev_flow->dv.push_vlan_res = cache_resource;
1724         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1725                 (void *)cache_resource,
1726                 rte_atomic32_read(&cache_resource->refcnt));
1727         return 0;
1728 }
1729 /**
1730  * Get the size of specific rte_flow_item_type
1731  *
1732  * @param[in] item_type
1733  *   Tested rte_flow_item_type.
1734  *
1735  * @return
1736  *   sizeof struct item_type, 0 if void or irrelevant.
1737  */
1738 static size_t
1739 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1740 {
1741         size_t retval;
1742
1743         switch (item_type) {
1744         case RTE_FLOW_ITEM_TYPE_ETH:
1745                 retval = sizeof(struct rte_flow_item_eth);
1746                 break;
1747         case RTE_FLOW_ITEM_TYPE_VLAN:
1748                 retval = sizeof(struct rte_flow_item_vlan);
1749                 break;
1750         case RTE_FLOW_ITEM_TYPE_IPV4:
1751                 retval = sizeof(struct rte_flow_item_ipv4);
1752                 break;
1753         case RTE_FLOW_ITEM_TYPE_IPV6:
1754                 retval = sizeof(struct rte_flow_item_ipv6);
1755                 break;
1756         case RTE_FLOW_ITEM_TYPE_UDP:
1757                 retval = sizeof(struct rte_flow_item_udp);
1758                 break;
1759         case RTE_FLOW_ITEM_TYPE_TCP:
1760                 retval = sizeof(struct rte_flow_item_tcp);
1761                 break;
1762         case RTE_FLOW_ITEM_TYPE_VXLAN:
1763                 retval = sizeof(struct rte_flow_item_vxlan);
1764                 break;
1765         case RTE_FLOW_ITEM_TYPE_GRE:
1766                 retval = sizeof(struct rte_flow_item_gre);
1767                 break;
1768         case RTE_FLOW_ITEM_TYPE_NVGRE:
1769                 retval = sizeof(struct rte_flow_item_nvgre);
1770                 break;
1771         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1772                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1773                 break;
1774         case RTE_FLOW_ITEM_TYPE_MPLS:
1775                 retval = sizeof(struct rte_flow_item_mpls);
1776                 break;
1777         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1778         default:
1779                 retval = 0;
1780                 break;
1781         }
1782         return retval;
1783 }
1784
1785 #define MLX5_ENCAP_IPV4_VERSION         0x40
1786 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
1787 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
1788 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
1789 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
1790 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
1791 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
1792
1793 /**
1794  * Convert the encap action data from list of rte_flow_item to raw buffer
1795  *
1796  * @param[in] items
1797  *   Pointer to rte_flow_item objects list.
1798  * @param[out] buf
1799  *   Pointer to the output buffer.
1800  * @param[out] size
1801  *   Pointer to the output buffer size.
1802  * @param[out] error
1803  *   Pointer to the error structure.
1804  *
1805  * @return
1806  *   0 on success, a negative errno value otherwise and rte_errno is set.
1807  */
1808 static int
1809 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1810                            size_t *size, struct rte_flow_error *error)
1811 {
1812         struct rte_ether_hdr *eth = NULL;
1813         struct rte_vlan_hdr *vlan = NULL;
1814         struct rte_ipv4_hdr *ipv4 = NULL;
1815         struct rte_ipv6_hdr *ipv6 = NULL;
1816         struct rte_udp_hdr *udp = NULL;
1817         struct rte_vxlan_hdr *vxlan = NULL;
1818         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1819         struct rte_gre_hdr *gre = NULL;
1820         size_t len;
1821         size_t temp_size = 0;
1822
1823         if (!items)
1824                 return rte_flow_error_set(error, EINVAL,
1825                                           RTE_FLOW_ERROR_TYPE_ACTION,
1826                                           NULL, "invalid empty data");
1827         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1828                 len = flow_dv_get_item_len(items->type);
1829                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1830                         return rte_flow_error_set(error, EINVAL,
1831                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1832                                                   (void *)items->type,
1833                                                   "items total size is too big"
1834                                                   " for encap action");
1835                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1836                 switch (items->type) {
1837                 case RTE_FLOW_ITEM_TYPE_ETH:
1838                         eth = (struct rte_ether_hdr *)&buf[temp_size];
1839                         break;
1840                 case RTE_FLOW_ITEM_TYPE_VLAN:
1841                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1842                         if (!eth)
1843                                 return rte_flow_error_set(error, EINVAL,
1844                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1845                                                 (void *)items->type,
1846                                                 "eth header not found");
1847                         if (!eth->ether_type)
1848                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1849                         break;
1850                 case RTE_FLOW_ITEM_TYPE_IPV4:
1851                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
1852                         if (!vlan && !eth)
1853                                 return rte_flow_error_set(error, EINVAL,
1854                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1855                                                 (void *)items->type,
1856                                                 "neither eth nor vlan"
1857                                                 " header found");
1858                         if (vlan && !vlan->eth_proto)
1859                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1860                         else if (eth && !eth->ether_type)
1861                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
1862                         if (!ipv4->version_ihl)
1863                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
1864                                                     MLX5_ENCAP_IPV4_IHL_MIN;
1865                         if (!ipv4->time_to_live)
1866                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
1867                         break;
1868                 case RTE_FLOW_ITEM_TYPE_IPV6:
1869                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
1870                         if (!vlan && !eth)
1871                                 return rte_flow_error_set(error, EINVAL,
1872                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1873                                                 (void *)items->type,
1874                                                 "neither eth nor vlan"
1875                                                 " header found");
1876                         if (vlan && !vlan->eth_proto)
1877                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1878                         else if (eth && !eth->ether_type)
1879                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
1880                         if (!ipv6->vtc_flow)
1881                                 ipv6->vtc_flow =
1882                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
1883                         if (!ipv6->hop_limits)
1884                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
1885                         break;
1886                 case RTE_FLOW_ITEM_TYPE_UDP:
1887                         udp = (struct rte_udp_hdr *)&buf[temp_size];
1888                         if (!ipv4 && !ipv6)
1889                                 return rte_flow_error_set(error, EINVAL,
1890                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1891                                                 (void *)items->type,
1892                                                 "ip header not found");
1893                         if (ipv4 && !ipv4->next_proto_id)
1894                                 ipv4->next_proto_id = IPPROTO_UDP;
1895                         else if (ipv6 && !ipv6->proto)
1896                                 ipv6->proto = IPPROTO_UDP;
1897                         break;
1898                 case RTE_FLOW_ITEM_TYPE_VXLAN:
1899                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
1900                         if (!udp)
1901                                 return rte_flow_error_set(error, EINVAL,
1902                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1903                                                 (void *)items->type,
1904                                                 "udp header not found");
1905                         if (!udp->dst_port)
1906                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
1907                         if (!vxlan->vx_flags)
1908                                 vxlan->vx_flags =
1909                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
1910                         break;
1911                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1912                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
1913                         if (!udp)
1914                                 return rte_flow_error_set(error, EINVAL,
1915                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1916                                                 (void *)items->type,
1917                                                 "udp header not found");
1918                         if (!vxlan_gpe->proto)
1919                                 return rte_flow_error_set(error, EINVAL,
1920                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1921                                                 (void *)items->type,
1922                                                 "next protocol not found");
1923                         if (!udp->dst_port)
1924                                 udp->dst_port =
1925                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
1926                         if (!vxlan_gpe->vx_flags)
1927                                 vxlan_gpe->vx_flags =
1928                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
1929                         break;
1930                 case RTE_FLOW_ITEM_TYPE_GRE:
1931                 case RTE_FLOW_ITEM_TYPE_NVGRE:
1932                         gre = (struct rte_gre_hdr *)&buf[temp_size];
1933                         if (!gre->proto)
1934                                 return rte_flow_error_set(error, EINVAL,
1935                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1936                                                 (void *)items->type,
1937                                                 "next protocol not found");
1938                         if (!ipv4 && !ipv6)
1939                                 return rte_flow_error_set(error, EINVAL,
1940                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1941                                                 (void *)items->type,
1942                                                 "ip header not found");
1943                         if (ipv4 && !ipv4->next_proto_id)
1944                                 ipv4->next_proto_id = IPPROTO_GRE;
1945                         else if (ipv6 && !ipv6->proto)
1946                                 ipv6->proto = IPPROTO_GRE;
1947                         break;
1948                 case RTE_FLOW_ITEM_TYPE_VOID:
1949                         break;
1950                 default:
1951                         return rte_flow_error_set(error, EINVAL,
1952                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1953                                                   (void *)items->type,
1954                                                   "unsupported item type");
1955                         break;
1956                 }
1957                 temp_size += len;
1958         }
1959         *size = temp_size;
1960         return 0;
1961 }
1962
1963 static int
1964 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
1965 {
1966         struct rte_ether_hdr *eth = NULL;
1967         struct rte_vlan_hdr *vlan = NULL;
1968         struct rte_ipv6_hdr *ipv6 = NULL;
1969         struct rte_udp_hdr *udp = NULL;
1970         char *next_hdr;
1971         uint16_t proto;
1972
1973         eth = (struct rte_ether_hdr *)data;
1974         next_hdr = (char *)(eth + 1);
1975         proto = RTE_BE16(eth->ether_type);
1976
1977         /* VLAN skipping */
1978         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
1979                 vlan = (struct rte_vlan_hdr *)next_hdr;
1980                 proto = RTE_BE16(vlan->eth_proto);
1981                 next_hdr += sizeof(struct rte_vlan_hdr);
1982         }
1983
1984         /* HW calculates IPv4 csum. no need to proceed */
1985         if (proto == RTE_ETHER_TYPE_IPV4)
1986                 return 0;
1987
1988         /* non IPv4/IPv6 header. not supported */
1989         if (proto != RTE_ETHER_TYPE_IPV6) {
1990                 return rte_flow_error_set(error, ENOTSUP,
1991                                           RTE_FLOW_ERROR_TYPE_ACTION,
1992                                           NULL, "Cannot offload non IPv4/IPv6");
1993         }
1994
1995         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
1996
1997         /* ignore non UDP */
1998         if (ipv6->proto != IPPROTO_UDP)
1999                 return 0;
2000
2001         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2002         udp->dgram_cksum = 0;
2003
2004         return 0;
2005 }
2006
2007 /**
2008  * Convert L2 encap action to DV specification.
2009  *
2010  * @param[in] dev
2011  *   Pointer to rte_eth_dev structure.
2012  * @param[in] action
2013  *   Pointer to action structure.
2014  * @param[in, out] dev_flow
2015  *   Pointer to the mlx5_flow.
2016  * @param[in] transfer
2017  *   Mark if the flow is E-Switch flow.
2018  * @param[out] error
2019  *   Pointer to the error structure.
2020  *
2021  * @return
2022  *   0 on success, a negative errno value otherwise and rte_errno is set.
2023  */
2024 static int
2025 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2026                                const struct rte_flow_action *action,
2027                                struct mlx5_flow *dev_flow,
2028                                uint8_t transfer,
2029                                struct rte_flow_error *error)
2030 {
2031         const struct rte_flow_item *encap_data;
2032         const struct rte_flow_action_raw_encap *raw_encap_data;
2033         struct mlx5_flow_dv_encap_decap_resource res = {
2034                 .reformat_type =
2035                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2036                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2037                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2038         };
2039
2040         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2041                 raw_encap_data =
2042                         (const struct rte_flow_action_raw_encap *)action->conf;
2043                 res.size = raw_encap_data->size;
2044                 memcpy(res.buf, raw_encap_data->data, res.size);
2045                 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2046                         return -rte_errno;
2047         } else {
2048                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2049                         encap_data =
2050                                 ((const struct rte_flow_action_vxlan_encap *)
2051                                                 action->conf)->definition;
2052                 else
2053                         encap_data =
2054                                 ((const struct rte_flow_action_nvgre_encap *)
2055                                                 action->conf)->definition;
2056                 if (flow_dv_convert_encap_data(encap_data, res.buf,
2057                                                &res.size, error))
2058                         return -rte_errno;
2059         }
2060         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2061                 return rte_flow_error_set(error, EINVAL,
2062                                           RTE_FLOW_ERROR_TYPE_ACTION,
2063                                           NULL, "can't create L2 encap action");
2064         return 0;
2065 }
2066
2067 /**
2068  * Convert L2 decap action to DV specification.
2069  *
2070  * @param[in] dev
2071  *   Pointer to rte_eth_dev structure.
2072  * @param[in, out] dev_flow
2073  *   Pointer to the mlx5_flow.
2074  * @param[in] transfer
2075  *   Mark if the flow is E-Switch flow.
2076  * @param[out] error
2077  *   Pointer to the error structure.
2078  *
2079  * @return
2080  *   0 on success, a negative errno value otherwise and rte_errno is set.
2081  */
2082 static int
2083 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2084                                struct mlx5_flow *dev_flow,
2085                                uint8_t transfer,
2086                                struct rte_flow_error *error)
2087 {
2088         struct mlx5_flow_dv_encap_decap_resource res = {
2089                 .size = 0,
2090                 .reformat_type =
2091                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2092                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2093                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2094         };
2095
2096         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2097                 return rte_flow_error_set(error, EINVAL,
2098                                           RTE_FLOW_ERROR_TYPE_ACTION,
2099                                           NULL, "can't create L2 decap action");
2100         return 0;
2101 }
2102
2103 /**
2104  * Convert raw decap/encap (L3 tunnel) action to DV specification.
2105  *
2106  * @param[in] dev
2107  *   Pointer to rte_eth_dev structure.
2108  * @param[in] action
2109  *   Pointer to action structure.
2110  * @param[in, out] dev_flow
2111  *   Pointer to the mlx5_flow.
2112  * @param[in] attr
2113  *   Pointer to the flow attributes.
2114  * @param[out] error
2115  *   Pointer to the error structure.
2116  *
2117  * @return
2118  *   0 on success, a negative errno value otherwise and rte_errno is set.
2119  */
2120 static int
2121 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2122                                 const struct rte_flow_action *action,
2123                                 struct mlx5_flow *dev_flow,
2124                                 const struct rte_flow_attr *attr,
2125                                 struct rte_flow_error *error)
2126 {
2127         const struct rte_flow_action_raw_encap *encap_data;
2128         struct mlx5_flow_dv_encap_decap_resource res;
2129
2130         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2131         res.size = encap_data->size;
2132         memcpy(res.buf, encap_data->data, res.size);
2133         res.reformat_type = attr->egress ?
2134                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2135                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2136         if (attr->transfer)
2137                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2138         else
2139                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2140                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2141         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2142                 return rte_flow_error_set(error, EINVAL,
2143                                           RTE_FLOW_ERROR_TYPE_ACTION,
2144                                           NULL, "can't create encap action");
2145         return 0;
2146 }
2147
2148 /**
2149  * Create action push VLAN.
2150  *
2151  * @param[in] dev
2152  *   Pointer to rte_eth_dev structure.
2153  * @param[in] vlan_tag
2154  *   the vlan tag to push to the Ethernet header.
2155  * @param[in, out] dev_flow
2156  *   Pointer to the mlx5_flow.
2157  * @param[in] attr
2158  *   Pointer to the flow attributes.
2159  * @param[out] error
2160  *   Pointer to the error structure.
2161  *
2162  * @return
2163  *   0 on success, a negative errno value otherwise and rte_errno is set.
2164  */
2165 static int
2166 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2167                                 const struct rte_flow_attr *attr,
2168                                 const struct rte_vlan_hdr *vlan,
2169                                 struct mlx5_flow *dev_flow,
2170                                 struct rte_flow_error *error)
2171 {
2172         struct mlx5_flow_dv_push_vlan_action_resource res;
2173
2174         res.vlan_tag =
2175                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2176                                  vlan->vlan_tci);
2177         if (attr->transfer)
2178                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2179         else
2180                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2181                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2182         return flow_dv_push_vlan_action_resource_register
2183                                             (dev, &res, dev_flow, error);
2184 }
2185
2186 /**
2187  * Validate the modify-header actions.
2188  *
2189  * @param[in] action_flags
2190  *   Holds the actions detected until now.
2191  * @param[in] action
2192  *   Pointer to the modify action.
2193  * @param[out] error
2194  *   Pointer to error structure.
2195  *
2196  * @return
2197  *   0 on success, a negative errno value otherwise and rte_errno is set.
2198  */
2199 static int
2200 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2201                                    const struct rte_flow_action *action,
2202                                    struct rte_flow_error *error)
2203 {
2204         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2205                 return rte_flow_error_set(error, EINVAL,
2206                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2207                                           NULL, "action configuration not set");
2208         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2209                 return rte_flow_error_set(error, EINVAL,
2210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2211                                           "can't have encap action before"
2212                                           " modify action");
2213         return 0;
2214 }
2215
2216 /**
2217  * Validate the modify-header MAC address actions.
2218  *
2219  * @param[in] action_flags
2220  *   Holds the actions detected until now.
2221  * @param[in] action
2222  *   Pointer to the modify action.
2223  * @param[in] item_flags
2224  *   Holds the items detected.
2225  * @param[out] error
2226  *   Pointer to error structure.
2227  *
2228  * @return
2229  *   0 on success, a negative errno value otherwise and rte_errno is set.
2230  */
2231 static int
2232 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2233                                    const struct rte_flow_action *action,
2234                                    const uint64_t item_flags,
2235                                    struct rte_flow_error *error)
2236 {
2237         int ret = 0;
2238
2239         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2240         if (!ret) {
2241                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2242                         return rte_flow_error_set(error, EINVAL,
2243                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2244                                                   NULL,
2245                                                   "no L2 item in pattern");
2246         }
2247         return ret;
2248 }
2249
2250 /**
2251  * Validate the modify-header IPv4 address actions.
2252  *
2253  * @param[in] action_flags
2254  *   Holds the actions detected until now.
2255  * @param[in] action
2256  *   Pointer to the modify action.
2257  * @param[in] item_flags
2258  *   Holds the items detected.
2259  * @param[out] error
2260  *   Pointer to error structure.
2261  *
2262  * @return
2263  *   0 on success, a negative errno value otherwise and rte_errno is set.
2264  */
2265 static int
2266 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2267                                     const struct rte_flow_action *action,
2268                                     const uint64_t item_flags,
2269                                     struct rte_flow_error *error)
2270 {
2271         int ret = 0;
2272
2273         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2274         if (!ret) {
2275                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2276                         return rte_flow_error_set(error, EINVAL,
2277                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2278                                                   NULL,
2279                                                   "no ipv4 item in pattern");
2280         }
2281         return ret;
2282 }
2283
2284 /**
2285  * Validate the modify-header IPv6 address actions.
2286  *
2287  * @param[in] action_flags
2288  *   Holds the actions detected until now.
2289  * @param[in] action
2290  *   Pointer to the modify action.
2291  * @param[in] item_flags
2292  *   Holds the items detected.
2293  * @param[out] error
2294  *   Pointer to error structure.
2295  *
2296  * @return
2297  *   0 on success, a negative errno value otherwise and rte_errno is set.
2298  */
2299 static int
2300 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2301                                     const struct rte_flow_action *action,
2302                                     const uint64_t item_flags,
2303                                     struct rte_flow_error *error)
2304 {
2305         int ret = 0;
2306
2307         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2308         if (!ret) {
2309                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2310                         return rte_flow_error_set(error, EINVAL,
2311                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2312                                                   NULL,
2313                                                   "no ipv6 item in pattern");
2314         }
2315         return ret;
2316 }
2317
2318 /**
2319  * Validate the modify-header TP actions.
2320  *
2321  * @param[in] action_flags
2322  *   Holds the actions detected until now.
2323  * @param[in] action
2324  *   Pointer to the modify action.
2325  * @param[in] item_flags
2326  *   Holds the items detected.
2327  * @param[out] error
2328  *   Pointer to error structure.
2329  *
2330  * @return
2331  *   0 on success, a negative errno value otherwise and rte_errno is set.
2332  */
2333 static int
2334 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2335                                   const struct rte_flow_action *action,
2336                                   const uint64_t item_flags,
2337                                   struct rte_flow_error *error)
2338 {
2339         int ret = 0;
2340
2341         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2342         if (!ret) {
2343                 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2344                         return rte_flow_error_set(error, EINVAL,
2345                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2346                                                   NULL, "no transport layer "
2347                                                   "in pattern");
2348         }
2349         return ret;
2350 }
2351
2352 /**
2353  * Validate the modify-header actions of increment/decrement
2354  * TCP Sequence-number.
2355  *
2356  * @param[in] action_flags
2357  *   Holds the actions detected until now.
2358  * @param[in] action
2359  *   Pointer to the modify action.
2360  * @param[in] item_flags
2361  *   Holds the items detected.
2362  * @param[out] error
2363  *   Pointer to error structure.
2364  *
2365  * @return
2366  *   0 on success, a negative errno value otherwise and rte_errno is set.
2367  */
2368 static int
2369 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2370                                        const struct rte_flow_action *action,
2371                                        const uint64_t item_flags,
2372                                        struct rte_flow_error *error)
2373 {
2374         int ret = 0;
2375
2376         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2377         if (!ret) {
2378                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2379                         return rte_flow_error_set(error, EINVAL,
2380                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2381                                                   NULL, "no TCP item in"
2382                                                   " pattern");
2383                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2384                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2385                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2386                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2387                         return rte_flow_error_set(error, EINVAL,
2388                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2389                                                   NULL,
2390                                                   "cannot decrease and increase"
2391                                                   " TCP sequence number"
2392                                                   " at the same time");
2393         }
2394         return ret;
2395 }
2396
2397 /**
2398  * Validate the modify-header actions of increment/decrement
2399  * TCP Acknowledgment number.
2400  *
2401  * @param[in] action_flags
2402  *   Holds the actions detected until now.
2403  * @param[in] action
2404  *   Pointer to the modify action.
2405  * @param[in] item_flags
2406  *   Holds the items detected.
2407  * @param[out] error
2408  *   Pointer to error structure.
2409  *
2410  * @return
2411  *   0 on success, a negative errno value otherwise and rte_errno is set.
2412  */
2413 static int
2414 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2415                                        const struct rte_flow_action *action,
2416                                        const uint64_t item_flags,
2417                                        struct rte_flow_error *error)
2418 {
2419         int ret = 0;
2420
2421         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2422         if (!ret) {
2423                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2424                         return rte_flow_error_set(error, EINVAL,
2425                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2426                                                   NULL, "no TCP item in"
2427                                                   " pattern");
2428                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2429                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2430                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2431                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2432                         return rte_flow_error_set(error, EINVAL,
2433                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2434                                                   NULL,
2435                                                   "cannot decrease and increase"
2436                                                   " TCP acknowledgment number"
2437                                                   " at the same time");
2438         }
2439         return ret;
2440 }
2441
2442 /**
2443  * Validate the modify-header TTL actions.
2444  *
2445  * @param[in] action_flags
2446  *   Holds the actions detected until now.
2447  * @param[in] action
2448  *   Pointer to the modify action.
2449  * @param[in] item_flags
2450  *   Holds the items detected.
2451  * @param[out] error
2452  *   Pointer to error structure.
2453  *
2454  * @return
2455  *   0 on success, a negative errno value otherwise and rte_errno is set.
2456  */
2457 static int
2458 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2459                                    const struct rte_flow_action *action,
2460                                    const uint64_t item_flags,
2461                                    struct rte_flow_error *error)
2462 {
2463         int ret = 0;
2464
2465         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2466         if (!ret) {
2467                 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2468                         return rte_flow_error_set(error, EINVAL,
2469                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2470                                                   NULL,
2471                                                   "no IP protocol in pattern");
2472         }
2473         return ret;
2474 }
2475
2476 /**
2477  * Validate jump action.
2478  *
2479  * @param[in] action
2480  *   Pointer to the jump action.
2481  * @param[in] action_flags
2482  *   Holds the actions detected until now.
2483  * @param[in] attributes
2484  *   Pointer to flow attributes
2485  * @param[in] external
2486  *   Action belongs to flow rule created by request external to PMD.
2487  * @param[out] error
2488  *   Pointer to error structure.
2489  *
2490  * @return
2491  *   0 on success, a negative errno value otherwise and rte_errno is set.
2492  */
2493 static int
2494 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2495                              uint64_t action_flags,
2496                              const struct rte_flow_attr *attributes,
2497                              bool external, struct rte_flow_error *error)
2498 {
2499         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2500                                                     MLX5_MAX_TABLES;
2501         uint32_t target_group, table;
2502         int ret = 0;
2503
2504         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2505                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2506                 return rte_flow_error_set(error, EINVAL,
2507                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2508                                           "can't have 2 fate actions in"
2509                                           " same flow");
2510         if (!action->conf)
2511                 return rte_flow_error_set(error, EINVAL,
2512                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2513                                           NULL, "action configuration not set");
2514         target_group =
2515                 ((const struct rte_flow_action_jump *)action->conf)->group;
2516         ret = mlx5_flow_group_to_table(attributes, external, target_group,
2517                                        &table, error);
2518         if (ret)
2519                 return ret;
2520         if (table >= max_group)
2521                 return rte_flow_error_set(error, EINVAL,
2522                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2523                                           "target group index out of range");
2524         if (attributes->group >= target_group)
2525                 return rte_flow_error_set(error, EINVAL,
2526                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2527                                           "target group must be higher than"
2528                                           " the current flow group");
2529         return 0;
2530 }
2531
2532 /*
2533  * Validate the port_id action.
2534  *
2535  * @param[in] dev
2536  *   Pointer to rte_eth_dev structure.
2537  * @param[in] action_flags
2538  *   Bit-fields that holds the actions detected until now.
2539  * @param[in] action
2540  *   Port_id RTE action structure.
2541  * @param[in] attr
2542  *   Attributes of flow that includes this action.
2543  * @param[out] error
2544  *   Pointer to error structure.
2545  *
2546  * @return
2547  *   0 on success, a negative errno value otherwise and rte_errno is set.
2548  */
2549 static int
2550 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2551                                 uint64_t action_flags,
2552                                 const struct rte_flow_action *action,
2553                                 const struct rte_flow_attr *attr,
2554                                 struct rte_flow_error *error)
2555 {
2556         const struct rte_flow_action_port_id *port_id;
2557         struct mlx5_priv *act_priv;
2558         struct mlx5_priv *dev_priv;
2559         uint16_t port;
2560
2561         if (!attr->transfer)
2562                 return rte_flow_error_set(error, ENOTSUP,
2563                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564                                           NULL,
2565                                           "port id action is valid in transfer"
2566                                           " mode only");
2567         if (!action || !action->conf)
2568                 return rte_flow_error_set(error, ENOTSUP,
2569                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2570                                           NULL,
2571                                           "port id action parameters must be"
2572                                           " specified");
2573         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2574                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2575                 return rte_flow_error_set(error, EINVAL,
2576                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2577                                           "can have only one fate actions in"
2578                                           " a flow");
2579         dev_priv = mlx5_dev_to_eswitch_info(dev);
2580         if (!dev_priv)
2581                 return rte_flow_error_set(error, rte_errno,
2582                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2583                                           NULL,
2584                                           "failed to obtain E-Switch info");
2585         port_id = action->conf;
2586         port = port_id->original ? dev->data->port_id : port_id->id;
2587         act_priv = mlx5_port_to_eswitch_info(port);
2588         if (!act_priv)
2589                 return rte_flow_error_set
2590                                 (error, rte_errno,
2591                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2592                                  "failed to obtain E-Switch port id for port");
2593         if (act_priv->domain_id != dev_priv->domain_id)
2594                 return rte_flow_error_set
2595                                 (error, EINVAL,
2596                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2597                                  "port does not belong to"
2598                                  " E-Switch being configured");
2599         return 0;
2600 }
2601
2602 /**
2603  * Find existing modify-header resource or create and register a new one.
2604  *
2605  * @param dev[in, out]
2606  *   Pointer to rte_eth_dev structure.
2607  * @param[in, out] resource
2608  *   Pointer to modify-header resource.
2609  * @parm[in, out] dev_flow
2610  *   Pointer to the dev_flow.
2611  * @param[out] error
2612  *   pointer to error structure.
2613  *
2614  * @return
2615  *   0 on success otherwise -errno and errno is set.
2616  */
2617 static int
2618 flow_dv_modify_hdr_resource_register
2619                         (struct rte_eth_dev *dev,
2620                          struct mlx5_flow_dv_modify_hdr_resource *resource,
2621                          struct mlx5_flow *dev_flow,
2622                          struct rte_flow_error *error)
2623 {
2624         struct mlx5_priv *priv = dev->data->dev_private;
2625         struct mlx5_ibv_shared *sh = priv->sh;
2626         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2627         struct mlx5dv_dr_domain *ns;
2628
2629         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2630                 ns = sh->fdb_domain;
2631         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2632                 ns = sh->tx_domain;
2633         else
2634                 ns = sh->rx_domain;
2635         resource->flags =
2636                 dev_flow->flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2637         /* Lookup a matching resource from cache. */
2638         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2639                 if (resource->ft_type == cache_resource->ft_type &&
2640                     resource->actions_num == cache_resource->actions_num &&
2641                     resource->flags == cache_resource->flags &&
2642                     !memcmp((const void *)resource->actions,
2643                             (const void *)cache_resource->actions,
2644                             (resource->actions_num *
2645                                             sizeof(resource->actions[0])))) {
2646                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2647                                 (void *)cache_resource,
2648                                 rte_atomic32_read(&cache_resource->refcnt));
2649                         rte_atomic32_inc(&cache_resource->refcnt);
2650                         dev_flow->dv.modify_hdr = cache_resource;
2651                         return 0;
2652                 }
2653         }
2654         /* Register new modify-header resource. */
2655         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2656         if (!cache_resource)
2657                 return rte_flow_error_set(error, ENOMEM,
2658                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2659                                           "cannot allocate resource memory");
2660         *cache_resource = *resource;
2661         cache_resource->verbs_action =
2662                 mlx5_glue->dv_create_flow_action_modify_header
2663                                         (sh->ctx, cache_resource->ft_type,
2664                                          ns, cache_resource->flags,
2665                                          cache_resource->actions_num *
2666                                          sizeof(cache_resource->actions[0]),
2667                                          (uint64_t *)cache_resource->actions);
2668         if (!cache_resource->verbs_action) {
2669                 rte_free(cache_resource);
2670                 return rte_flow_error_set(error, ENOMEM,
2671                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2672                                           NULL, "cannot create action");
2673         }
2674         rte_atomic32_init(&cache_resource->refcnt);
2675         rte_atomic32_inc(&cache_resource->refcnt);
2676         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2677         dev_flow->dv.modify_hdr = cache_resource;
2678         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2679                 (void *)cache_resource,
2680                 rte_atomic32_read(&cache_resource->refcnt));
2681         return 0;
2682 }
2683
2684 #define MLX5_CNT_CONTAINER_RESIZE 64
2685
2686 /**
2687  * Get or create a flow counter.
2688  *
2689  * @param[in] dev
2690  *   Pointer to the Ethernet device structure.
2691  * @param[in] shared
2692  *   Indicate if this counter is shared with other flows.
2693  * @param[in] id
2694  *   Counter identifier.
2695  *
2696  * @return
2697  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
2698  */
2699 static struct mlx5_flow_counter *
2700 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2701                                uint32_t id)
2702 {
2703         struct mlx5_priv *priv = dev->data->dev_private;
2704         struct mlx5_flow_counter *cnt = NULL;
2705         struct mlx5_devx_obj *dcs = NULL;
2706
2707         if (!priv->config.devx) {
2708                 rte_errno = ENOTSUP;
2709                 return NULL;
2710         }
2711         if (shared) {
2712                 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2713                         if (cnt->shared && cnt->id == id) {
2714                                 cnt->ref_cnt++;
2715                                 return cnt;
2716                         }
2717                 }
2718         }
2719         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2720         if (!dcs)
2721                 return NULL;
2722         cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2723         if (!cnt) {
2724                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2725                 rte_errno = ENOMEM;
2726                 return NULL;
2727         }
2728         struct mlx5_flow_counter tmpl = {
2729                 .shared = shared,
2730                 .ref_cnt = 1,
2731                 .id = id,
2732                 .dcs = dcs,
2733         };
2734         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2735         if (!tmpl.action) {
2736                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2737                 rte_errno = errno;
2738                 rte_free(cnt);
2739                 return NULL;
2740         }
2741         *cnt = tmpl;
2742         TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2743         return cnt;
2744 }
2745
2746 /**
2747  * Release a flow counter.
2748  *
2749  * @param[in] dev
2750  *   Pointer to the Ethernet device structure.
2751  * @param[in] counter
2752  *   Pointer to the counter handler.
2753  */
2754 static void
2755 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2756                                  struct mlx5_flow_counter *counter)
2757 {
2758         struct mlx5_priv *priv = dev->data->dev_private;
2759
2760         if (!counter)
2761                 return;
2762         if (--counter->ref_cnt == 0) {
2763                 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2764                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2765                 rte_free(counter);
2766         }
2767 }
2768
2769 /**
2770  * Query a devx flow counter.
2771  *
2772  * @param[in] dev
2773  *   Pointer to the Ethernet device structure.
2774  * @param[in] cnt
2775  *   Pointer to the flow counter.
2776  * @param[out] pkts
2777  *   The statistics value of packets.
2778  * @param[out] bytes
2779  *   The statistics value of bytes.
2780  *
2781  * @return
2782  *   0 on success, otherwise a negative errno value and rte_errno is set.
2783  */
2784 static inline int
2785 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2786                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
2787                      uint64_t *bytes)
2788 {
2789         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2790                                                 0, NULL, NULL, 0);
2791 }
2792
2793 /**
2794  * Get a pool by a counter.
2795  *
2796  * @param[in] cnt
2797  *   Pointer to the counter.
2798  *
2799  * @return
2800  *   The counter pool.
2801  */
2802 static struct mlx5_flow_counter_pool *
2803 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2804 {
2805         if (!cnt->batch) {
2806                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2807                 return (struct mlx5_flow_counter_pool *)cnt - 1;
2808         }
2809         return cnt->pool;
2810 }
2811
2812 /**
2813  * Get a pool by devx counter ID.
2814  *
2815  * @param[in] cont
2816  *   Pointer to the counter container.
2817  * @param[in] id
2818  *   The counter devx ID.
2819  *
2820  * @return
2821  *   The counter pool pointer if exists, NULL otherwise,
2822  */
2823 static struct mlx5_flow_counter_pool *
2824 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2825 {
2826         struct mlx5_flow_counter_pool *pool;
2827
2828         TAILQ_FOREACH(pool, &cont->pool_list, next) {
2829                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
2830                                 MLX5_COUNTERS_PER_POOL;
2831
2832                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
2833                         return pool;
2834         };
2835         return NULL;
2836 }
2837
2838 /**
2839  * Allocate a new memory for the counter values wrapped by all the needed
2840  * management.
2841  *
2842  * @param[in] dev
2843  *   Pointer to the Ethernet device structure.
2844  * @param[in] raws_n
2845  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
2846  *
2847  * @return
2848  *   The new memory management pointer on success, otherwise NULL and rte_errno
2849  *   is set.
2850  */
2851 static struct mlx5_counter_stats_mem_mng *
2852 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
2853 {
2854         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
2855                                         (dev->data->dev_private))->sh;
2856         struct mlx5_devx_mkey_attr mkey_attr;
2857         struct mlx5_counter_stats_mem_mng *mem_mng;
2858         volatile struct flow_counter_stats *raw_data;
2859         int size = (sizeof(struct flow_counter_stats) *
2860                         MLX5_COUNTERS_PER_POOL +
2861                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
2862                         sizeof(struct mlx5_counter_stats_mem_mng);
2863         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
2864         int i;
2865
2866         if (!mem) {
2867                 rte_errno = ENOMEM;
2868                 return NULL;
2869         }
2870         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
2871         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
2872         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
2873                                                  IBV_ACCESS_LOCAL_WRITE);
2874         if (!mem_mng->umem) {
2875                 rte_errno = errno;
2876                 rte_free(mem);
2877                 return NULL;
2878         }
2879         mkey_attr.addr = (uintptr_t)mem;
2880         mkey_attr.size = size;
2881         mkey_attr.umem_id = mem_mng->umem->umem_id;
2882         mkey_attr.pd = sh->pdn;
2883         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
2884         if (!mem_mng->dm) {
2885                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
2886                 rte_errno = errno;
2887                 rte_free(mem);
2888                 return NULL;
2889         }
2890         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
2891         raw_data = (volatile struct flow_counter_stats *)mem;
2892         for (i = 0; i < raws_n; ++i) {
2893                 mem_mng->raws[i].mem_mng = mem_mng;
2894                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
2895         }
2896         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
2897         return mem_mng;
2898 }
2899
2900 /**
2901  * Resize a counter container.
2902  *
2903  * @param[in] dev
2904  *   Pointer to the Ethernet device structure.
2905  * @param[in] batch
2906  *   Whether the pool is for counter that was allocated by batch command.
2907  *
2908  * @return
2909  *   The new container pointer on success, otherwise NULL and rte_errno is set.
2910  */
2911 static struct mlx5_pools_container *
2912 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
2913 {
2914         struct mlx5_priv *priv = dev->data->dev_private;
2915         struct mlx5_pools_container *cont =
2916                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
2917         struct mlx5_pools_container *new_cont =
2918                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
2919         struct mlx5_counter_stats_mem_mng *mem_mng;
2920         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
2921         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
2922         int i;
2923
2924         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
2925                 /* The last resize still hasn't detected by the host thread. */
2926                 rte_errno = EAGAIN;
2927                 return NULL;
2928         }
2929         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
2930         if (!new_cont->pools) {
2931                 rte_errno = ENOMEM;
2932                 return NULL;
2933         }
2934         if (cont->n)
2935                 memcpy(new_cont->pools, cont->pools, cont->n *
2936                        sizeof(struct mlx5_flow_counter_pool *));
2937         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
2938                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
2939         if (!mem_mng) {
2940                 rte_free(new_cont->pools);
2941                 return NULL;
2942         }
2943         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
2944                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
2945                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
2946                                  i, next);
2947         new_cont->n = resize;
2948         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
2949         TAILQ_INIT(&new_cont->pool_list);
2950         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
2951         new_cont->init_mem_mng = mem_mng;
2952         rte_cio_wmb();
2953          /* Flip the master container. */
2954         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
2955         return new_cont;
2956 }
2957
2958 /**
2959  * Query a devx flow counter.
2960  *
2961  * @param[in] dev
2962  *   Pointer to the Ethernet device structure.
2963  * @param[in] cnt
2964  *   Pointer to the flow counter.
2965  * @param[out] pkts
2966  *   The statistics value of packets.
2967  * @param[out] bytes
2968  *   The statistics value of bytes.
2969  *
2970  * @return
2971  *   0 on success, otherwise a negative errno value and rte_errno is set.
2972  */
2973 static inline int
2974 _flow_dv_query_count(struct rte_eth_dev *dev,
2975                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
2976                      uint64_t *bytes)
2977 {
2978         struct mlx5_priv *priv = dev->data->dev_private;
2979         struct mlx5_flow_counter_pool *pool =
2980                         flow_dv_counter_pool_get(cnt);
2981         int offset = cnt - &pool->counters_raw[0];
2982
2983         if (priv->counter_fallback)
2984                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
2985
2986         rte_spinlock_lock(&pool->sl);
2987         /*
2988          * The single counters allocation may allocate smaller ID than the
2989          * current allocated in parallel to the host reading.
2990          * In this case the new counter values must be reported as 0.
2991          */
2992         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
2993                 *pkts = 0;
2994                 *bytes = 0;
2995         } else {
2996                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
2997                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
2998         }
2999         rte_spinlock_unlock(&pool->sl);
3000         return 0;
3001 }
3002
3003 /**
3004  * Create and initialize a new counter pool.
3005  *
3006  * @param[in] dev
3007  *   Pointer to the Ethernet device structure.
3008  * @param[out] dcs
3009  *   The devX counter handle.
3010  * @param[in] batch
3011  *   Whether the pool is for counter that was allocated by batch command.
3012  *
3013  * @return
3014  *   A new pool pointer on success, NULL otherwise and rte_errno is set.
3015  */
3016 static struct mlx5_flow_counter_pool *
3017 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3018                     uint32_t batch)
3019 {
3020         struct mlx5_priv *priv = dev->data->dev_private;
3021         struct mlx5_flow_counter_pool *pool;
3022         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3023                                                                0);
3024         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3025         uint32_t size;
3026
3027         if (cont->n == n_valid) {
3028                 cont = flow_dv_container_resize(dev, batch);
3029                 if (!cont)
3030                         return NULL;
3031         }
3032         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3033                         sizeof(struct mlx5_flow_counter);
3034         pool = rte_calloc(__func__, 1, size, 0);
3035         if (!pool) {
3036                 rte_errno = ENOMEM;
3037                 return NULL;
3038         }
3039         pool->min_dcs = dcs;
3040         pool->raw = cont->init_mem_mng->raws + n_valid %
3041                                                      MLX5_CNT_CONTAINER_RESIZE;
3042         pool->raw_hw = NULL;
3043         rte_spinlock_init(&pool->sl);
3044         /*
3045          * The generation of the new allocated counters in this pool is 0, 2 in
3046          * the pool generation makes all the counters valid for allocation.
3047          */
3048         rte_atomic64_set(&pool->query_gen, 0x2);
3049         TAILQ_INIT(&pool->counters);
3050         TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3051         cont->pools[n_valid] = pool;
3052         /* Pool initialization must be updated before host thread access. */
3053         rte_cio_wmb();
3054         rte_atomic16_add(&cont->n_valid, 1);
3055         return pool;
3056 }
3057
3058 /**
3059  * Prepare a new counter and/or a new counter pool.
3060  *
3061  * @param[in] dev
3062  *   Pointer to the Ethernet device structure.
3063  * @param[out] cnt_free
3064  *   Where to put the pointer of a new counter.
3065  * @param[in] batch
3066  *   Whether the pool is for counter that was allocated by batch command.
3067  *
3068  * @return
3069  *   The free counter pool pointer and @p cnt_free is set on success,
3070  *   NULL otherwise and rte_errno is set.
3071  */
3072 static struct mlx5_flow_counter_pool *
3073 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3074                              struct mlx5_flow_counter **cnt_free,
3075                              uint32_t batch)
3076 {
3077         struct mlx5_priv *priv = dev->data->dev_private;
3078         struct mlx5_flow_counter_pool *pool;
3079         struct mlx5_devx_obj *dcs = NULL;
3080         struct mlx5_flow_counter *cnt;
3081         uint32_t i;
3082
3083         if (!batch) {
3084                 /* bulk_bitmap must be 0 for single counter allocation. */
3085                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3086                 if (!dcs)
3087                         return NULL;
3088                 pool = flow_dv_find_pool_by_id
3089                         (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3090                 if (!pool) {
3091                         pool = flow_dv_pool_create(dev, dcs, batch);
3092                         if (!pool) {
3093                                 mlx5_devx_cmd_destroy(dcs);
3094                                 return NULL;
3095                         }
3096                 } else if (dcs->id < pool->min_dcs->id) {
3097                         rte_atomic64_set(&pool->a64_dcs,
3098                                          (int64_t)(uintptr_t)dcs);
3099                 }
3100                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3101                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3102                 cnt->dcs = dcs;
3103                 *cnt_free = cnt;
3104                 return pool;
3105         }
3106         /* bulk_bitmap is in 128 counters units. */
3107         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3108                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3109         if (!dcs) {
3110                 rte_errno = ENODATA;
3111                 return NULL;
3112         }
3113         pool = flow_dv_pool_create(dev, dcs, batch);
3114         if (!pool) {
3115                 mlx5_devx_cmd_destroy(dcs);
3116                 return NULL;
3117         }
3118         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3119                 cnt = &pool->counters_raw[i];
3120                 cnt->pool = pool;
3121                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3122         }
3123         *cnt_free = &pool->counters_raw[0];
3124         return pool;
3125 }
3126
3127 /**
3128  * Search for existed shared counter.
3129  *
3130  * @param[in] cont
3131  *   Pointer to the relevant counter pool container.
3132  * @param[in] id
3133  *   The shared counter ID to search.
3134  *
3135  * @return
3136  *   NULL if not existed, otherwise pointer to the shared counter.
3137  */
3138 static struct mlx5_flow_counter *
3139 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3140                               uint32_t id)
3141 {
3142         static struct mlx5_flow_counter *cnt;
3143         struct mlx5_flow_counter_pool *pool;
3144         int i;
3145
3146         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3147                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3148                         cnt = &pool->counters_raw[i];
3149                         if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3150                                 return cnt;
3151                 }
3152         }
3153         return NULL;
3154 }
3155
3156 /**
3157  * Allocate a flow counter.
3158  *
3159  * @param[in] dev
3160  *   Pointer to the Ethernet device structure.
3161  * @param[in] shared
3162  *   Indicate if this counter is shared with other flows.
3163  * @param[in] id
3164  *   Counter identifier.
3165  * @param[in] group
3166  *   Counter flow group.
3167  *
3168  * @return
3169  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3170  */
3171 static struct mlx5_flow_counter *
3172 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3173                       uint16_t group)
3174 {
3175         struct mlx5_priv *priv = dev->data->dev_private;
3176         struct mlx5_flow_counter_pool *pool = NULL;
3177         struct mlx5_flow_counter *cnt_free = NULL;
3178         /*
3179          * Currently group 0 flow counter cannot be assigned to a flow if it is
3180          * not the first one in the batch counter allocation, so it is better
3181          * to allocate counters one by one for these flows in a separate
3182          * container.
3183          * A counter can be shared between different groups so need to take
3184          * shared counters from the single container.
3185          */
3186         uint32_t batch = (group && !shared) ? 1 : 0;
3187         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3188                                                                0);
3189
3190         if (priv->counter_fallback)
3191                 return flow_dv_counter_alloc_fallback(dev, shared, id);
3192         if (!priv->config.devx) {
3193                 rte_errno = ENOTSUP;
3194                 return NULL;
3195         }
3196         if (shared) {
3197                 cnt_free = flow_dv_counter_shared_search(cont, id);
3198                 if (cnt_free) {
3199                         if (cnt_free->ref_cnt + 1 == 0) {
3200                                 rte_errno = E2BIG;
3201                                 return NULL;
3202                         }
3203                         cnt_free->ref_cnt++;
3204                         return cnt_free;
3205                 }
3206         }
3207         /* Pools which has a free counters are in the start. */
3208         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3209                 /*
3210                  * The free counter reset values must be updated between the
3211                  * counter release to the counter allocation, so, at least one
3212                  * query must be done in this time. ensure it by saving the
3213                  * query generation in the release time.
3214                  * The free list is sorted according to the generation - so if
3215                  * the first one is not updated, all the others are not
3216                  * updated too.
3217                  */
3218                 cnt_free = TAILQ_FIRST(&pool->counters);
3219                 if (cnt_free && cnt_free->query_gen + 1 <
3220                     rte_atomic64_read(&pool->query_gen))
3221                         break;
3222                 cnt_free = NULL;
3223         }
3224         if (!cnt_free) {
3225                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3226                 if (!pool)
3227                         return NULL;
3228         }
3229         cnt_free->batch = batch;
3230         /* Create a DV counter action only in the first time usage. */
3231         if (!cnt_free->action) {
3232                 uint16_t offset;
3233                 struct mlx5_devx_obj *dcs;
3234
3235                 if (batch) {
3236                         offset = cnt_free - &pool->counters_raw[0];
3237                         dcs = pool->min_dcs;
3238                 } else {
3239                         offset = 0;
3240                         dcs = cnt_free->dcs;
3241                 }
3242                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3243                                         (dcs->obj, offset);
3244                 if (!cnt_free->action) {
3245                         rte_errno = errno;
3246                         return NULL;
3247                 }
3248         }
3249         /* Update the counter reset values. */
3250         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3251                                  &cnt_free->bytes))
3252                 return NULL;
3253         cnt_free->shared = shared;
3254         cnt_free->ref_cnt = 1;
3255         cnt_free->id = id;
3256         if (!priv->sh->cmng.query_thread_on)
3257                 /* Start the asynchronous batch query by the host thread. */
3258                 mlx5_set_query_alarm(priv->sh);
3259         TAILQ_REMOVE(&pool->counters, cnt_free, next);
3260         if (TAILQ_EMPTY(&pool->counters)) {
3261                 /* Move the pool to the end of the container pool list. */
3262                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3263                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3264         }
3265         return cnt_free;
3266 }
3267
3268 /**
3269  * Release a flow counter.
3270  *
3271  * @param[in] dev
3272  *   Pointer to the Ethernet device structure.
3273  * @param[in] counter
3274  *   Pointer to the counter handler.
3275  */
3276 static void
3277 flow_dv_counter_release(struct rte_eth_dev *dev,
3278                         struct mlx5_flow_counter *counter)
3279 {
3280         struct mlx5_priv *priv = dev->data->dev_private;
3281
3282         if (!counter)
3283                 return;
3284         if (priv->counter_fallback) {
3285                 flow_dv_counter_release_fallback(dev, counter);
3286                 return;
3287         }
3288         if (--counter->ref_cnt == 0) {
3289                 struct mlx5_flow_counter_pool *pool =
3290                                 flow_dv_counter_pool_get(counter);
3291
3292                 /* Put the counter in the end - the last updated one. */
3293                 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3294                 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3295         }
3296 }
3297
3298 /**
3299  * Verify the @p attributes will be correctly understood by the NIC and store
3300  * them in the @p flow if everything is correct.
3301  *
3302  * @param[in] dev
3303  *   Pointer to dev struct.
3304  * @param[in] attributes
3305  *   Pointer to flow attributes
3306  * @param[in] external
3307  *   This flow rule is created by request external to PMD.
3308  * @param[out] error
3309  *   Pointer to error structure.
3310  *
3311  * @return
3312  *   0 on success, a negative errno value otherwise and rte_errno is set.
3313  */
3314 static int
3315 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3316                             const struct rte_flow_attr *attributes,
3317                             bool external __rte_unused,
3318                             struct rte_flow_error *error)
3319 {
3320         struct mlx5_priv *priv = dev->data->dev_private;
3321         uint32_t priority_max = priv->config.flow_prio - 1;
3322
3323 #ifndef HAVE_MLX5DV_DR
3324         if (attributes->group)
3325                 return rte_flow_error_set(error, ENOTSUP,
3326                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3327                                           NULL,
3328                                           "groups are not supported");
3329 #else
3330         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3331                                                     MLX5_MAX_TABLES;
3332         uint32_t table;
3333         int ret;
3334
3335         ret = mlx5_flow_group_to_table(attributes, external,
3336                                        attributes->group,
3337                                        &table, error);
3338         if (ret)
3339                 return ret;
3340         if (table >= max_group)
3341                 return rte_flow_error_set(error, EINVAL,
3342                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3343                                           "group index out of range");
3344 #endif
3345         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3346             attributes->priority >= priority_max)
3347                 return rte_flow_error_set(error, ENOTSUP,
3348                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3349                                           NULL,
3350                                           "priority out of range");
3351         if (attributes->transfer) {
3352                 if (!priv->config.dv_esw_en)
3353                         return rte_flow_error_set
3354                                 (error, ENOTSUP,
3355                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3356                                  "E-Switch dr is not supported");
3357                 if (!(priv->representor || priv->master))
3358                         return rte_flow_error_set
3359                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3360                                  NULL, "E-Switch configuration can only be"
3361                                  " done by a master or a representor device");
3362                 if (attributes->egress)
3363                         return rte_flow_error_set
3364                                 (error, ENOTSUP,
3365                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3366                                  "egress is not supported");
3367         }
3368         if (!(attributes->egress ^ attributes->ingress))
3369                 return rte_flow_error_set(error, ENOTSUP,
3370                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3371                                           "must specify exactly one of "
3372                                           "ingress or egress");
3373         return 0;
3374 }
3375
3376 /**
3377  * Internal validation function. For validating both actions and items.
3378  *
3379  * @param[in] dev
3380  *   Pointer to the rte_eth_dev structure.
3381  * @param[in] attr
3382  *   Pointer to the flow attributes.
3383  * @param[in] items
3384  *   Pointer to the list of items.
3385  * @param[in] actions
3386  *   Pointer to the list of actions.
3387  * @param[in] external
3388  *   This flow rule is created by request external to PMD.
3389  * @param[out] error
3390  *   Pointer to the error structure.
3391  *
3392  * @return
3393  *   0 on success, a negative errno value otherwise and rte_errno is set.
3394  */
3395 static int
3396 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3397                  const struct rte_flow_item items[],
3398                  const struct rte_flow_action actions[],
3399                  bool external, struct rte_flow_error *error)
3400 {
3401         int ret;
3402         uint64_t action_flags = 0;
3403         uint64_t item_flags = 0;
3404         uint64_t last_item = 0;
3405         uint8_t next_protocol = 0xff;
3406         int actions_n = 0;
3407         const struct rte_flow_item *gre_item = NULL;
3408         struct rte_flow_item_tcp nic_tcp_mask = {
3409                 .hdr = {
3410                         .tcp_flags = 0xFF,
3411                         .src_port = RTE_BE16(UINT16_MAX),
3412                         .dst_port = RTE_BE16(UINT16_MAX),
3413                 }
3414         };
3415
3416         if (items == NULL)
3417                 return -1;
3418         ret = flow_dv_validate_attributes(dev, attr, external, error);
3419         if (ret < 0)
3420                 return ret;
3421         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3422                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3423                 int type = items->type;
3424
3425                 switch (type) {
3426                 case RTE_FLOW_ITEM_TYPE_VOID:
3427                         break;
3428                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3429                         ret = flow_dv_validate_item_port_id
3430                                         (dev, items, attr, item_flags, error);
3431                         if (ret < 0)
3432                                 return ret;
3433                         last_item = MLX5_FLOW_ITEM_PORT_ID;
3434                         break;
3435                 case RTE_FLOW_ITEM_TYPE_ETH:
3436                         ret = mlx5_flow_validate_item_eth(items, item_flags,
3437                                                           error);
3438                         if (ret < 0)
3439                                 return ret;
3440                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3441                                              MLX5_FLOW_LAYER_OUTER_L2;
3442                         break;
3443                 case RTE_FLOW_ITEM_TYPE_VLAN:
3444                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
3445                                                            dev, error);
3446                         if (ret < 0)
3447                                 return ret;
3448                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3449                                              MLX5_FLOW_LAYER_OUTER_VLAN;
3450                         break;
3451                 case RTE_FLOW_ITEM_TYPE_IPV4:
3452                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3453                                                   &item_flags, &tunnel);
3454                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3455                                                            NULL, error);
3456                         if (ret < 0)
3457                                 return ret;
3458                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3459                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3460                         if (items->mask != NULL &&
3461                             ((const struct rte_flow_item_ipv4 *)
3462                              items->mask)->hdr.next_proto_id) {
3463                                 next_protocol =
3464                                         ((const struct rte_flow_item_ipv4 *)
3465                                          (items->spec))->hdr.next_proto_id;
3466                                 next_protocol &=
3467                                         ((const struct rte_flow_item_ipv4 *)
3468                                          (items->mask))->hdr.next_proto_id;
3469                         } else {
3470                                 /* Reset for inner layer. */
3471                                 next_protocol = 0xff;
3472                         }
3473                         break;
3474                 case RTE_FLOW_ITEM_TYPE_IPV6:
3475                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3476                                                   &item_flags, &tunnel);
3477                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3478                                                            NULL, error);
3479                         if (ret < 0)
3480                                 return ret;
3481                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3482                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3483                         if (items->mask != NULL &&
3484                             ((const struct rte_flow_item_ipv6 *)
3485                              items->mask)->hdr.proto) {
3486                                 next_protocol =
3487                                         ((const struct rte_flow_item_ipv6 *)
3488                                          items->spec)->hdr.proto;
3489                                 next_protocol &=
3490                                         ((const struct rte_flow_item_ipv6 *)
3491                                          items->mask)->hdr.proto;
3492                         } else {
3493                                 /* Reset for inner layer. */
3494                                 next_protocol = 0xff;
3495                         }
3496                         break;
3497                 case RTE_FLOW_ITEM_TYPE_TCP:
3498                         ret = mlx5_flow_validate_item_tcp
3499                                                 (items, item_flags,
3500                                                  next_protocol,
3501                                                  &nic_tcp_mask,
3502                                                  error);
3503                         if (ret < 0)
3504                                 return ret;
3505                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3506                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
3507                         break;
3508                 case RTE_FLOW_ITEM_TYPE_UDP:
3509                         ret = mlx5_flow_validate_item_udp(items, item_flags,
3510                                                           next_protocol,
3511                                                           error);
3512                         if (ret < 0)
3513                                 return ret;
3514                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3515                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
3516                         break;
3517                 case RTE_FLOW_ITEM_TYPE_GRE:
3518                         ret = mlx5_flow_validate_item_gre(items, item_flags,
3519                                                           next_protocol, error);
3520                         if (ret < 0)
3521                                 return ret;
3522                         gre_item = items;
3523                         last_item = MLX5_FLOW_LAYER_GRE;
3524                         break;
3525                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3526                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3527                                                             next_protocol,
3528                                                             error);
3529                         if (ret < 0)
3530                                 return ret;
3531                         last_item = MLX5_FLOW_LAYER_NVGRE;
3532                         break;
3533                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3534                         ret = mlx5_flow_validate_item_gre_key
3535                                 (items, item_flags, gre_item, error);
3536                         if (ret < 0)
3537                                 return ret;
3538                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
3539                         break;
3540                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3541                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3542                                                             error);
3543                         if (ret < 0)
3544                                 return ret;
3545                         last_item = MLX5_FLOW_LAYER_VXLAN;
3546                         break;
3547                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3548                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
3549                                                                 item_flags, dev,
3550                                                                 error);
3551                         if (ret < 0)
3552                                 return ret;
3553                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3554                         break;
3555                 case RTE_FLOW_ITEM_TYPE_GENEVE:
3556                         ret = mlx5_flow_validate_item_geneve(items,
3557                                                              item_flags, dev,
3558                                                              error);
3559                         if (ret < 0)
3560                                 return ret;
3561                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3562                         break;
3563                 case RTE_FLOW_ITEM_TYPE_MPLS:
3564                         ret = mlx5_flow_validate_item_mpls(dev, items,
3565                                                            item_flags,
3566                                                            last_item, error);
3567                         if (ret < 0)
3568                                 return ret;
3569                         last_item = MLX5_FLOW_LAYER_MPLS;
3570                         break;
3571                 case RTE_FLOW_ITEM_TYPE_META:
3572                         ret = flow_dv_validate_item_meta(dev, items, attr,
3573                                                          error);
3574                         if (ret < 0)
3575                                 return ret;
3576                         last_item = MLX5_FLOW_ITEM_METADATA;
3577                         break;
3578                 case RTE_FLOW_ITEM_TYPE_ICMP:
3579                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
3580                                                            next_protocol,
3581                                                            error);
3582                         if (ret < 0)
3583                                 return ret;
3584                         last_item = MLX5_FLOW_LAYER_ICMP;
3585                         break;
3586                 case RTE_FLOW_ITEM_TYPE_ICMP6:
3587                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3588                                                             next_protocol,
3589                                                             error);
3590                         if (ret < 0)
3591                                 return ret;
3592                         last_item = MLX5_FLOW_LAYER_ICMP6;
3593                         break;
3594                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3595                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3596                         break;
3597                 default:
3598                         return rte_flow_error_set(error, ENOTSUP,
3599                                                   RTE_FLOW_ERROR_TYPE_ITEM,
3600                                                   NULL, "item not supported");
3601                 }
3602                 item_flags |= last_item;
3603         }
3604         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3605                 int type = actions->type;
3606                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3607                         return rte_flow_error_set(error, ENOTSUP,
3608                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3609                                                   actions, "too many actions");
3610                 switch (type) {
3611                 case RTE_FLOW_ACTION_TYPE_VOID:
3612                         break;
3613                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3614                         ret = flow_dv_validate_action_port_id(dev,
3615                                                               action_flags,
3616                                                               actions,
3617                                                               attr,
3618                                                               error);
3619                         if (ret)
3620                                 return ret;
3621                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3622                         ++actions_n;
3623                         break;
3624                 case RTE_FLOW_ACTION_TYPE_FLAG:
3625                         ret = mlx5_flow_validate_action_flag(action_flags,
3626                                                              attr, error);
3627                         if (ret < 0)
3628                                 return ret;
3629                         action_flags |= MLX5_FLOW_ACTION_FLAG;
3630                         ++actions_n;
3631                         break;
3632                 case RTE_FLOW_ACTION_TYPE_MARK:
3633                         ret = mlx5_flow_validate_action_mark(actions,
3634                                                              action_flags,
3635                                                              attr, error);
3636                         if (ret < 0)
3637                                 return ret;
3638                         action_flags |= MLX5_FLOW_ACTION_MARK;
3639                         ++actions_n;
3640                         break;
3641                 case RTE_FLOW_ACTION_TYPE_DROP:
3642                         ret = mlx5_flow_validate_action_drop(action_flags,
3643                                                              attr, error);
3644                         if (ret < 0)
3645                                 return ret;
3646                         action_flags |= MLX5_FLOW_ACTION_DROP;
3647                         ++actions_n;
3648                         break;
3649                 case RTE_FLOW_ACTION_TYPE_QUEUE:
3650                         ret = mlx5_flow_validate_action_queue(actions,
3651                                                               action_flags, dev,
3652                                                               attr, error);
3653                         if (ret < 0)
3654                                 return ret;
3655                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
3656                         ++actions_n;
3657                         break;
3658                 case RTE_FLOW_ACTION_TYPE_RSS:
3659                         ret = mlx5_flow_validate_action_rss(actions,
3660                                                             action_flags, dev,
3661                                                             attr, item_flags,
3662                                                             error);
3663                         if (ret < 0)
3664                                 return ret;
3665                         action_flags |= MLX5_FLOW_ACTION_RSS;
3666                         ++actions_n;
3667                         break;
3668                 case RTE_FLOW_ACTION_TYPE_COUNT:
3669                         ret = flow_dv_validate_action_count(dev, error);
3670                         if (ret < 0)
3671                                 return ret;
3672                         action_flags |= MLX5_FLOW_ACTION_COUNT;
3673                         ++actions_n;
3674                         break;
3675                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3676                         if (flow_dv_validate_action_pop_vlan(dev,
3677                                                              action_flags,
3678                                                              actions,
3679                                                              item_flags, attr,
3680                                                              error))
3681                                 return -rte_errno;
3682                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3683                         ++actions_n;
3684                         break;
3685                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3686                         ret = flow_dv_validate_action_push_vlan(action_flags,
3687                                                                 item_flags,
3688                                                                 actions, attr,
3689                                                                 error);
3690                         if (ret < 0)
3691                                 return ret;
3692                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3693                         ++actions_n;
3694                         break;
3695                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3696                         ret = flow_dv_validate_action_set_vlan_pcp
3697                                                 (action_flags, actions, error);
3698                         if (ret < 0)
3699                                 return ret;
3700                         /* Count PCP with push_vlan command. */
3701                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3702                         break;
3703                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3704                         ret = flow_dv_validate_action_set_vlan_vid
3705                                                 (item_flags, action_flags,
3706                                                  actions, error);
3707                         if (ret < 0)
3708                                 return ret;
3709                         /* Count VID with push_vlan command. */
3710                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3711                         break;
3712                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3713                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3714                         ret = flow_dv_validate_action_l2_encap(action_flags,
3715                                                                actions, attr,
3716                                                                error);
3717                         if (ret < 0)
3718                                 return ret;
3719                         action_flags |= actions->type ==
3720                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3721                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
3722                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
3723                         ++actions_n;
3724                         break;
3725                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3726                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3727                         ret = flow_dv_validate_action_l2_decap(action_flags,
3728                                                                attr, error);
3729                         if (ret < 0)
3730                                 return ret;
3731                         action_flags |= actions->type ==
3732                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3733                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
3734                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
3735                         ++actions_n;
3736                         break;
3737                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3738                         ret = flow_dv_validate_action_raw_encap(action_flags,
3739                                                                 actions, attr,
3740                                                                 error);
3741                         if (ret < 0)
3742                                 return ret;
3743                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3744                         ++actions_n;
3745                         break;
3746                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3747                         ret = flow_dv_validate_action_raw_decap(action_flags,
3748                                                                 actions, attr,
3749                                                                 error);
3750                         if (ret < 0)
3751                                 return ret;
3752                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3753                         ++actions_n;
3754                         break;
3755                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3756                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3757                         ret = flow_dv_validate_action_modify_mac(action_flags,
3758                                                                  actions,
3759                                                                  item_flags,
3760                                                                  error);
3761                         if (ret < 0)
3762                                 return ret;
3763                         /* Count all modify-header actions as one action. */
3764                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3765                                 ++actions_n;
3766                         action_flags |= actions->type ==
3767                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3768                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
3769                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
3770                         break;
3771
3772                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3773                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3774                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
3775                                                                   actions,
3776                                                                   item_flags,
3777                                                                   error);
3778                         if (ret < 0)
3779                                 return ret;
3780                         /* Count all modify-header actions as one action. */
3781                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3782                                 ++actions_n;
3783                         action_flags |= actions->type ==
3784                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3785                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3786                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
3787                         break;
3788                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3789                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3790                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
3791                                                                   actions,
3792                                                                   item_flags,
3793                                                                   error);
3794                         if (ret < 0)
3795                                 return ret;
3796                         /* Count all modify-header actions as one action. */
3797                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3798                                 ++actions_n;
3799                         action_flags |= actions->type ==
3800                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
3801                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
3802                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
3803                         break;
3804                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
3805                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
3806                         ret = flow_dv_validate_action_modify_tp(action_flags,
3807                                                                 actions,
3808                                                                 item_flags,
3809                                                                 error);
3810                         if (ret < 0)
3811                                 return ret;
3812                         /* Count all modify-header actions as one action. */
3813                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3814                                 ++actions_n;
3815                         action_flags |= actions->type ==
3816                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
3817                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
3818                                                 MLX5_FLOW_ACTION_SET_TP_DST;
3819                         break;
3820                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
3821                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
3822                         ret = flow_dv_validate_action_modify_ttl(action_flags,
3823                                                                  actions,
3824                                                                  item_flags,
3825                                                                  error);
3826                         if (ret < 0)
3827                                 return ret;
3828                         /* Count all modify-header actions as one action. */
3829                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3830                                 ++actions_n;
3831                         action_flags |= actions->type ==
3832                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
3833                                                 MLX5_FLOW_ACTION_SET_TTL :
3834                                                 MLX5_FLOW_ACTION_DEC_TTL;
3835                         break;
3836                 case RTE_FLOW_ACTION_TYPE_JUMP:
3837                         ret = flow_dv_validate_action_jump(actions,
3838                                                            action_flags,
3839                                                            attr, external,
3840                                                            error);
3841                         if (ret)
3842                                 return ret;
3843                         ++actions_n;
3844                         action_flags |= MLX5_FLOW_ACTION_JUMP;
3845                         break;
3846                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
3847                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
3848                         ret = flow_dv_validate_action_modify_tcp_seq
3849                                                                 (action_flags,
3850                                                                  actions,
3851                                                                  item_flags,
3852                                                                  error);
3853                         if (ret < 0)
3854                                 return ret;
3855                         /* Count all modify-header actions as one action. */
3856                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3857                                 ++actions_n;
3858                         action_flags |= actions->type ==
3859                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
3860                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
3861                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
3862                         break;
3863                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
3864                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
3865                         ret = flow_dv_validate_action_modify_tcp_ack
3866                                                                 (action_flags,
3867                                                                  actions,
3868                                                                  item_flags,
3869                                                                  error);
3870                         if (ret < 0)
3871                                 return ret;
3872                         /* Count all modify-header actions as one action. */
3873                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3874                                 ++actions_n;
3875                         action_flags |= actions->type ==
3876                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
3877                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
3878                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
3879                         break;
3880                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
3881                         break;
3882                 default:
3883                         return rte_flow_error_set(error, ENOTSUP,
3884                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3885                                                   actions,
3886                                                   "action not supported");
3887                 }
3888         }
3889         if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
3890             (action_flags & MLX5_FLOW_VLAN_ACTIONS))
3891                 return rte_flow_error_set(error, ENOTSUP,
3892                                           RTE_FLOW_ERROR_TYPE_ACTION,
3893                                           actions,
3894                                           "can't have vxlan and vlan"
3895                                           " actions in the same rule");
3896         /* Eswitch has few restrictions on using items and actions */
3897         if (attr->transfer) {
3898                 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3899                         return rte_flow_error_set(error, ENOTSUP,
3900                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3901                                                   NULL,
3902                                                   "unsupported action FLAG");
3903                 if (action_flags & MLX5_FLOW_ACTION_MARK)
3904                         return rte_flow_error_set(error, ENOTSUP,
3905                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3906                                                   NULL,
3907                                                   "unsupported action MARK");
3908                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
3909                         return rte_flow_error_set(error, ENOTSUP,
3910                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3911                                                   NULL,
3912                                                   "unsupported action QUEUE");
3913                 if (action_flags & MLX5_FLOW_ACTION_RSS)
3914                         return rte_flow_error_set(error, ENOTSUP,
3915                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3916                                                   NULL,
3917                                                   "unsupported action RSS");
3918                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3919                         return rte_flow_error_set(error, EINVAL,
3920                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3921                                                   actions,
3922                                                   "no fate action is found");
3923         } else {
3924                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
3925                         return rte_flow_error_set(error, EINVAL,
3926                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3927                                                   actions,
3928                                                   "no fate action is found");
3929         }
3930         return 0;
3931 }
3932
3933 /**
3934  * Internal preparation function. Allocates the DV flow size,
3935  * this size is constant.
3936  *
3937  * @param[in] attr
3938  *   Pointer to the flow attributes.
3939  * @param[in] items
3940  *   Pointer to the list of items.
3941  * @param[in] actions
3942  *   Pointer to the list of actions.
3943  * @param[out] error
3944  *   Pointer to the error structure.
3945  *
3946  * @return
3947  *   Pointer to mlx5_flow object on success,
3948  *   otherwise NULL and rte_errno is set.
3949  */
3950 static struct mlx5_flow *
3951 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
3952                 const struct rte_flow_item items[] __rte_unused,
3953                 const struct rte_flow_action actions[] __rte_unused,
3954                 struct rte_flow_error *error)
3955 {
3956         uint32_t size = sizeof(struct mlx5_flow);
3957         struct mlx5_flow *flow;
3958
3959         flow = rte_calloc(__func__, 1, size, 0);
3960         if (!flow) {
3961                 rte_flow_error_set(error, ENOMEM,
3962                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3963                                    "not enough memory to create flow");
3964                 return NULL;
3965         }
3966         flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
3967         return flow;
3968 }
3969
3970 #ifndef NDEBUG
3971 /**
3972  * Sanity check for match mask and value. Similar to check_valid_spec() in
3973  * kernel driver. If unmasked bit is present in value, it returns failure.
3974  *
3975  * @param match_mask
3976  *   pointer to match mask buffer.
3977  * @param match_value
3978  *   pointer to match value buffer.
3979  *
3980  * @return
3981  *   0 if valid, -EINVAL otherwise.
3982  */
3983 static int
3984 flow_dv_check_valid_spec(void *match_mask, void *match_value)
3985 {
3986         uint8_t *m = match_mask;
3987         uint8_t *v = match_value;
3988         unsigned int i;
3989
3990         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
3991                 if (v[i] & ~m[i]) {
3992                         DRV_LOG(ERR,
3993                                 "match_value differs from match_criteria"
3994                                 " %p[%u] != %p[%u]",
3995                                 match_value, i, match_mask, i);
3996                         return -EINVAL;
3997                 }
3998         }
3999         return 0;
4000 }
4001 #endif
4002
4003 /**
4004  * Add Ethernet item to matcher and to the value.
4005  *
4006  * @param[in, out] matcher
4007  *   Flow matcher.
4008  * @param[in, out] key
4009  *   Flow matcher value.
4010  * @param[in] item
4011  *   Flow pattern to translate.
4012  * @param[in] inner
4013  *   Item is inner pattern.
4014  */
4015 static void
4016 flow_dv_translate_item_eth(void *matcher, void *key,
4017                            const struct rte_flow_item *item, int inner)
4018 {
4019         const struct rte_flow_item_eth *eth_m = item->mask;
4020         const struct rte_flow_item_eth *eth_v = item->spec;
4021         const struct rte_flow_item_eth nic_mask = {
4022                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4023                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4024                 .type = RTE_BE16(0xffff),
4025         };
4026         void *headers_m;
4027         void *headers_v;
4028         char *l24_v;
4029         unsigned int i;
4030
4031         if (!eth_v)
4032                 return;
4033         if (!eth_m)
4034                 eth_m = &nic_mask;
4035         if (inner) {
4036                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4037                                          inner_headers);
4038                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4039         } else {
4040                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4041                                          outer_headers);
4042                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4043         }
4044         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4045                &eth_m->dst, sizeof(eth_m->dst));
4046         /* The value must be in the range of the mask. */
4047         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4048         for (i = 0; i < sizeof(eth_m->dst); ++i)
4049                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4050         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4051                &eth_m->src, sizeof(eth_m->src));
4052         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4053         /* The value must be in the range of the mask. */
4054         for (i = 0; i < sizeof(eth_m->dst); ++i)
4055                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4056         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4057                  rte_be_to_cpu_16(eth_m->type));
4058         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4059         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4060 }
4061
4062 /**
4063  * Add VLAN item to matcher and to the value.
4064  *
4065  * @param[in, out] dev_flow
4066  *   Flow descriptor.
4067  * @param[in, out] matcher
4068  *   Flow matcher.
4069  * @param[in, out] key
4070  *   Flow matcher value.
4071  * @param[in] item
4072  *   Flow pattern to translate.
4073  * @param[in] inner
4074  *   Item is inner pattern.
4075  */
4076 static void
4077 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4078                             void *matcher, void *key,
4079                             const struct rte_flow_item *item,
4080                             int inner)
4081 {
4082         const struct rte_flow_item_vlan *vlan_m = item->mask;
4083         const struct rte_flow_item_vlan *vlan_v = item->spec;
4084         void *headers_m;
4085         void *headers_v;
4086         uint16_t tci_m;
4087         uint16_t tci_v;
4088
4089         if (!vlan_v)
4090                 return;
4091         if (!vlan_m)
4092                 vlan_m = &rte_flow_item_vlan_mask;
4093         if (inner) {
4094                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4095                                          inner_headers);
4096                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4097         } else {
4098                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4099                                          outer_headers);
4100                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4101                 /*
4102                  * This is workaround, masks are not supported,
4103                  * and pre-validated.
4104                  */
4105                 dev_flow->dv.vf_vlan.tag =
4106                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4107         }
4108         tci_m = rte_be_to_cpu_16(vlan_m->tci);
4109         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4110         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4111         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4112         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4113         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4114         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4115         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4116         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4117         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4118         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4119                  rte_be_to_cpu_16(vlan_m->inner_type));
4120         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4121                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4122 }
4123
4124 /**
4125  * Add IPV4 item to matcher and to the value.
4126  *
4127  * @param[in, out] matcher
4128  *   Flow matcher.
4129  * @param[in, out] key
4130  *   Flow matcher value.
4131  * @param[in] item
4132  *   Flow pattern to translate.
4133  * @param[in] inner
4134  *   Item is inner pattern.
4135  * @param[in] group
4136  *   The group to insert the rule.
4137  */
4138 static void
4139 flow_dv_translate_item_ipv4(void *matcher, void *key,
4140                             const struct rte_flow_item *item,
4141                             int inner, uint32_t group)
4142 {
4143         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4144         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4145         const struct rte_flow_item_ipv4 nic_mask = {
4146                 .hdr = {
4147                         .src_addr = RTE_BE32(0xffffffff),
4148                         .dst_addr = RTE_BE32(0xffffffff),
4149                         .type_of_service = 0xff,
4150                         .next_proto_id = 0xff,
4151                 },
4152         };
4153         void *headers_m;
4154         void *headers_v;
4155         char *l24_m;
4156         char *l24_v;
4157         uint8_t tos;
4158
4159         if (inner) {
4160                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4161                                          inner_headers);
4162                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4163         } else {
4164                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4165                                          outer_headers);
4166                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4167         }
4168         if (group == 0)
4169                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4170         else
4171                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4172         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4173         if (!ipv4_v)
4174                 return;
4175         if (!ipv4_m)
4176                 ipv4_m = &nic_mask;
4177         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4178                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4179         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4180                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4181         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4182         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4183         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4184                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4185         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4186                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4187         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4188         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4189         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4190         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4191                  ipv4_m->hdr.type_of_service);
4192         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4193         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4194                  ipv4_m->hdr.type_of_service >> 2);
4195         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4196         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4197                  ipv4_m->hdr.next_proto_id);
4198         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4199                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4200 }
4201
4202 /**
4203  * Add IPV6 item to matcher and to the value.
4204  *
4205  * @param[in, out] matcher
4206  *   Flow matcher.
4207  * @param[in, out] key
4208  *   Flow matcher value.
4209  * @param[in] item
4210  *   Flow pattern to translate.
4211  * @param[in] inner
4212  *   Item is inner pattern.
4213  * @param[in] group
4214  *   The group to insert the rule.
4215  */
4216 static void
4217 flow_dv_translate_item_ipv6(void *matcher, void *key,
4218                             const struct rte_flow_item *item,
4219                             int inner, uint32_t group)
4220 {
4221         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4222         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4223         const struct rte_flow_item_ipv6 nic_mask = {
4224                 .hdr = {
4225                         .src_addr =
4226                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4227                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4228                         .dst_addr =
4229                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4230                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4231                         .vtc_flow = RTE_BE32(0xffffffff),
4232                         .proto = 0xff,
4233                         .hop_limits = 0xff,
4234                 },
4235         };
4236         void *headers_m;
4237         void *headers_v;
4238         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4239         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4240         char *l24_m;
4241         char *l24_v;
4242         uint32_t vtc_m;
4243         uint32_t vtc_v;
4244         int i;
4245         int size;
4246
4247         if (inner) {
4248                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4249                                          inner_headers);
4250                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4251         } else {
4252                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4253                                          outer_headers);
4254                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4255         }
4256         if (group == 0)
4257                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4258         else
4259                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4260         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4261         if (!ipv6_v)
4262                 return;
4263         if (!ipv6_m)
4264                 ipv6_m = &nic_mask;
4265         size = sizeof(ipv6_m->hdr.dst_addr);
4266         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4267                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4268         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4269                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4270         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4271         for (i = 0; i < size; ++i)
4272                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4273         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4274                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4275         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4276                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4277         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4278         for (i = 0; i < size; ++i)
4279                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4280         /* TOS. */
4281         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4282         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4283         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4284         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4285         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4286         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4287         /* Label. */
4288         if (inner) {
4289                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4290                          vtc_m);
4291                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4292                          vtc_v);
4293         } else {
4294                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4295                          vtc_m);
4296                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4297                          vtc_v);
4298         }
4299         /* Protocol. */
4300         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4301                  ipv6_m->hdr.proto);
4302         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4303                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4304 }
4305
4306 /**
4307  * Add TCP item to matcher and to the value.
4308  *
4309  * @param[in, out] matcher
4310  *   Flow matcher.
4311  * @param[in, out] key
4312  *   Flow matcher value.
4313  * @param[in] item
4314  *   Flow pattern to translate.
4315  * @param[in] inner
4316  *   Item is inner pattern.
4317  */
4318 static void
4319 flow_dv_translate_item_tcp(void *matcher, void *key,
4320                            const struct rte_flow_item *item,
4321                            int inner)
4322 {
4323         const struct rte_flow_item_tcp *tcp_m = item->mask;
4324         const struct rte_flow_item_tcp *tcp_v = item->spec;
4325         void *headers_m;
4326         void *headers_v;
4327
4328         if (inner) {
4329                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4330                                          inner_headers);
4331                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4332         } else {
4333                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4334                                          outer_headers);
4335                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4336         }
4337         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4338         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4339         if (!tcp_v)
4340                 return;
4341         if (!tcp_m)
4342                 tcp_m = &rte_flow_item_tcp_mask;
4343         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4344                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
4345         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4346                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4347         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4348                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4349         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4350                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4351         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4352                  tcp_m->hdr.tcp_flags);
4353         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4354                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4355 }
4356
4357 /**
4358  * Add UDP item to matcher and to the value.
4359  *
4360  * @param[in, out] matcher
4361  *   Flow matcher.
4362  * @param[in, out] key
4363  *   Flow matcher value.
4364  * @param[in] item
4365  *   Flow pattern to translate.
4366  * @param[in] inner
4367  *   Item is inner pattern.
4368  */
4369 static void
4370 flow_dv_translate_item_udp(void *matcher, void *key,
4371                            const struct rte_flow_item *item,
4372                            int inner)
4373 {
4374         const struct rte_flow_item_udp *udp_m = item->mask;
4375         const struct rte_flow_item_udp *udp_v = item->spec;
4376         void *headers_m;
4377         void *headers_v;
4378
4379         if (inner) {
4380                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4381                                          inner_headers);
4382                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4383         } else {
4384                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4385                                          outer_headers);
4386                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4387         }
4388         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4389         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4390         if (!udp_v)
4391                 return;
4392         if (!udp_m)
4393                 udp_m = &rte_flow_item_udp_mask;
4394         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4395                  rte_be_to_cpu_16(udp_m->hdr.src_port));
4396         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4397                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4398         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4399                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
4400         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4401                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4402 }
4403
4404 /**
4405  * Add GRE optional Key item to matcher and to the value.
4406  *
4407  * @param[in, out] matcher
4408  *   Flow matcher.
4409  * @param[in, out] key
4410  *   Flow matcher value.
4411  * @param[in] item
4412  *   Flow pattern to translate.
4413  * @param[in] inner
4414  *   Item is inner pattern.
4415  */
4416 static void
4417 flow_dv_translate_item_gre_key(void *matcher, void *key,
4418                                    const struct rte_flow_item *item)
4419 {
4420         const rte_be32_t *key_m = item->mask;
4421         const rte_be32_t *key_v = item->spec;
4422         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4423         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4424         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4425
4426         if (!key_v)
4427                 return;
4428         if (!key_m)
4429                 key_m = &gre_key_default_mask;
4430         /* GRE K bit must be on and should already be validated */
4431         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4432         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4433         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4434                  rte_be_to_cpu_32(*key_m) >> 8);
4435         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4436                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4437         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4438                  rte_be_to_cpu_32(*key_m) & 0xFF);
4439         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4440                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4441 }
4442
4443 /**
4444  * Add GRE item to matcher and to the value.
4445  *
4446  * @param[in, out] matcher
4447  *   Flow matcher.
4448  * @param[in, out] key
4449  *   Flow matcher value.
4450  * @param[in] item
4451  *   Flow pattern to translate.
4452  * @param[in] inner
4453  *   Item is inner pattern.
4454  */
4455 static void
4456 flow_dv_translate_item_gre(void *matcher, void *key,
4457                            const struct rte_flow_item *item,
4458                            int inner)
4459 {
4460         const struct rte_flow_item_gre *gre_m = item->mask;
4461         const struct rte_flow_item_gre *gre_v = item->spec;
4462         void *headers_m;
4463         void *headers_v;
4464         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4465         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4466         struct {
4467                 union {
4468                         __extension__
4469                         struct {
4470                                 uint16_t version:3;
4471                                 uint16_t rsvd0:9;
4472                                 uint16_t s_present:1;
4473                                 uint16_t k_present:1;
4474                                 uint16_t rsvd_bit1:1;
4475                                 uint16_t c_present:1;
4476                         };
4477                         uint16_t value;
4478                 };
4479         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4480
4481         if (inner) {
4482                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4483                                          inner_headers);
4484                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4485         } else {
4486                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4487                                          outer_headers);
4488                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4489         }
4490         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4491         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4492         if (!gre_v)
4493                 return;
4494         if (!gre_m)
4495                 gre_m = &rte_flow_item_gre_mask;
4496         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4497                  rte_be_to_cpu_16(gre_m->protocol));
4498         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4499                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4500         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4501         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4502         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4503                  gre_crks_rsvd0_ver_m.c_present);
4504         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4505                  gre_crks_rsvd0_ver_v.c_present &
4506                  gre_crks_rsvd0_ver_m.c_present);
4507         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4508                  gre_crks_rsvd0_ver_m.k_present);
4509         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4510                  gre_crks_rsvd0_ver_v.k_present &
4511                  gre_crks_rsvd0_ver_m.k_present);
4512         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4513                  gre_crks_rsvd0_ver_m.s_present);
4514         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4515                  gre_crks_rsvd0_ver_v.s_present &
4516                  gre_crks_rsvd0_ver_m.s_present);
4517 }
4518
4519 /**
4520  * Add NVGRE item to matcher and to the value.
4521  *
4522  * @param[in, out] matcher
4523  *   Flow matcher.
4524  * @param[in, out] key
4525  *   Flow matcher value.
4526  * @param[in] item
4527  *   Flow pattern to translate.
4528  * @param[in] inner
4529  *   Item is inner pattern.
4530  */
4531 static void
4532 flow_dv_translate_item_nvgre(void *matcher, void *key,
4533                              const struct rte_flow_item *item,
4534                              int inner)
4535 {
4536         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4537         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4538         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4539         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4540         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4541         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4542         char *gre_key_m;
4543         char *gre_key_v;
4544         int size;
4545         int i;
4546
4547         /* For NVGRE, GRE header fields must be set with defined values. */
4548         const struct rte_flow_item_gre gre_spec = {
4549                 .c_rsvd0_ver = RTE_BE16(0x2000),
4550                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4551         };
4552         const struct rte_flow_item_gre gre_mask = {
4553                 .c_rsvd0_ver = RTE_BE16(0xB000),
4554                 .protocol = RTE_BE16(UINT16_MAX),
4555         };
4556         const struct rte_flow_item gre_item = {
4557                 .spec = &gre_spec,
4558                 .mask = &gre_mask,
4559                 .last = NULL,
4560         };
4561         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4562         if (!nvgre_v)
4563                 return;
4564         if (!nvgre_m)
4565                 nvgre_m = &rte_flow_item_nvgre_mask;
4566         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4567         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4568         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4569         memcpy(gre_key_m, tni_flow_id_m, size);
4570         for (i = 0; i < size; ++i)
4571                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4572 }
4573
4574 /**
4575  * Add VXLAN item to matcher and to the value.
4576  *
4577  * @param[in, out] matcher
4578  *   Flow matcher.
4579  * @param[in, out] key
4580  *   Flow matcher value.
4581  * @param[in] item
4582  *   Flow pattern to translate.
4583  * @param[in] inner
4584  *   Item is inner pattern.
4585  */
4586 static void
4587 flow_dv_translate_item_vxlan(void *matcher, void *key,
4588                              const struct rte_flow_item *item,
4589                              int inner)
4590 {
4591         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4592         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4593         void *headers_m;
4594         void *headers_v;
4595         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4596         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4597         char *vni_m;
4598         char *vni_v;
4599         uint16_t dport;
4600         int size;
4601         int i;
4602
4603         if (inner) {
4604                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4605                                          inner_headers);
4606                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4607         } else {
4608                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4609                                          outer_headers);
4610                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4611         }
4612         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4613                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4614         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4615                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4616                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4617         }
4618         if (!vxlan_v)
4619                 return;
4620         if (!vxlan_m)
4621                 vxlan_m = &rte_flow_item_vxlan_mask;
4622         size = sizeof(vxlan_m->vni);
4623         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4624         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4625         memcpy(vni_m, vxlan_m->vni, size);
4626         for (i = 0; i < size; ++i)
4627                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4628 }
4629
4630 /**
4631  * Add Geneve item to matcher and to the value.
4632  *
4633  * @param[in, out] matcher
4634  *   Flow matcher.
4635  * @param[in, out] key
4636  *   Flow matcher value.
4637  * @param[in] item
4638  *   Flow pattern to translate.
4639  * @param[in] inner
4640  *   Item is inner pattern.
4641  */
4642
4643 static void
4644 flow_dv_translate_item_geneve(void *matcher, void *key,
4645                               const struct rte_flow_item *item, int inner)
4646 {
4647         const struct rte_flow_item_geneve *geneve_m = item->mask;
4648         const struct rte_flow_item_geneve *geneve_v = item->spec;
4649         void *headers_m;
4650         void *headers_v;
4651         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4652         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4653         uint16_t dport;
4654         uint16_t gbhdr_m;
4655         uint16_t gbhdr_v;
4656         char *vni_m;
4657         char *vni_v;
4658         size_t size, i;
4659
4660         if (inner) {
4661                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4662                                          inner_headers);
4663                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4664         } else {
4665                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4666                                          outer_headers);
4667                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4668         }
4669         dport = MLX5_UDP_PORT_GENEVE;
4670         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4671                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4672                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4673         }
4674         if (!geneve_v)
4675                 return;
4676         if (!geneve_m)
4677                 geneve_m = &rte_flow_item_geneve_mask;
4678         size = sizeof(geneve_m->vni);
4679         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4680         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4681         memcpy(vni_m, geneve_m->vni, size);
4682         for (i = 0; i < size; ++i)
4683                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4684         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4685                  rte_be_to_cpu_16(geneve_m->protocol));
4686         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4687                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4688         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4689         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4690         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4691                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4692         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4693                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4694         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4695                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4696         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4697                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4698                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4699 }
4700
4701 /**
4702  * Add MPLS item to matcher and to the value.
4703  *
4704  * @param[in, out] matcher
4705  *   Flow matcher.
4706  * @param[in, out] key
4707  *   Flow matcher value.
4708  * @param[in] item
4709  *   Flow pattern to translate.
4710  * @param[in] prev_layer
4711  *   The protocol layer indicated in previous item.
4712  * @param[in] inner
4713  *   Item is inner pattern.
4714  */
4715 static void
4716 flow_dv_translate_item_mpls(void *matcher, void *key,
4717                             const struct rte_flow_item *item,
4718                             uint64_t prev_layer,
4719                             int inner)
4720 {
4721         const uint32_t *in_mpls_m = item->mask;
4722         const uint32_t *in_mpls_v = item->spec;
4723         uint32_t *out_mpls_m = 0;
4724         uint32_t *out_mpls_v = 0;
4725         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4726         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4727         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4728                                      misc_parameters_2);
4729         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4730         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4731         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4732
4733         switch (prev_layer) {
4734         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4735                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4736                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4737                          MLX5_UDP_PORT_MPLS);
4738                 break;
4739         case MLX5_FLOW_LAYER_GRE:
4740                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4741                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4742                          RTE_ETHER_TYPE_MPLS);
4743                 break;
4744         default:
4745                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4746                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4747                          IPPROTO_MPLS);
4748                 break;
4749         }
4750         if (!in_mpls_v)
4751                 return;
4752         if (!in_mpls_m)
4753                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4754         switch (prev_layer) {
4755         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4756                 out_mpls_m =
4757                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4758                                                  outer_first_mpls_over_udp);
4759                 out_mpls_v =
4760                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4761                                                  outer_first_mpls_over_udp);
4762                 break;
4763         case MLX5_FLOW_LAYER_GRE:
4764                 out_mpls_m =
4765                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4766                                                  outer_first_mpls_over_gre);
4767                 out_mpls_v =
4768                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4769                                                  outer_first_mpls_over_gre);
4770                 break;
4771         default:
4772                 /* Inner MPLS not over GRE is not supported. */
4773                 if (!inner) {
4774                         out_mpls_m =
4775                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4776                                                          misc2_m,
4777                                                          outer_first_mpls);
4778                         out_mpls_v =
4779                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4780                                                          misc2_v,
4781                                                          outer_first_mpls);
4782                 }
4783                 break;
4784         }
4785         if (out_mpls_m && out_mpls_v) {
4786                 *out_mpls_m = *in_mpls_m;
4787                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4788         }
4789 }
4790
4791 /**
4792  * Add META item to matcher
4793  *
4794  * @param[in, out] matcher
4795  *   Flow matcher.
4796  * @param[in, out] key
4797  *   Flow matcher value.
4798  * @param[in] item
4799  *   Flow pattern to translate.
4800  * @param[in] inner
4801  *   Item is inner pattern.
4802  */
4803 static void
4804 flow_dv_translate_item_meta(void *matcher, void *key,
4805                             const struct rte_flow_item *item)
4806 {
4807         const struct rte_flow_item_meta *meta_m;
4808         const struct rte_flow_item_meta *meta_v;
4809         void *misc2_m =
4810                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4811         void *misc2_v =
4812                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4813
4814         meta_m = (const void *)item->mask;
4815         if (!meta_m)
4816                 meta_m = &rte_flow_item_meta_mask;
4817         meta_v = (const void *)item->spec;
4818         if (meta_v) {
4819                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4820                          rte_be_to_cpu_32(meta_m->data));
4821                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4822                          rte_be_to_cpu_32(meta_v->data & meta_m->data));
4823         }
4824 }
4825
4826 /**
4827  * Add vport metadata Reg C0 item to matcher
4828  *
4829  * @param[in, out] matcher
4830  *   Flow matcher.
4831  * @param[in, out] key
4832  *   Flow matcher value.
4833  * @param[in] reg
4834  *   Flow pattern to translate.
4835  */
4836 static void
4837 flow_dv_translate_item_meta_vport(void *matcher, void *key,
4838                                   uint32_t value, uint32_t mask)
4839 {
4840         void *misc2_m =
4841                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4842         void *misc2_v =
4843                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4844
4845         MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
4846         MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, value);
4847 }
4848
4849 /**
4850  * Add tag item to matcher
4851  *
4852  * @param[in, out] matcher
4853  *   Flow matcher.
4854  * @param[in, out] key
4855  *   Flow matcher value.
4856  * @param[in] item
4857  *   Flow pattern to translate.
4858  */
4859 static void
4860 flow_dv_translate_item_tag(void *matcher, void *key,
4861                            const struct rte_flow_item *item)
4862 {
4863         void *misc2_m =
4864                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
4865         void *misc2_v =
4866                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4867         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
4868         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
4869         enum modify_reg reg = tag_v->id;
4870         rte_be32_t value = tag_v->data;
4871         rte_be32_t mask = tag_m->data;
4872
4873         switch (reg) {
4874         case REG_A:
4875                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
4876                                 rte_be_to_cpu_32(mask));
4877                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
4878                                 rte_be_to_cpu_32(value));
4879                 break;
4880         case REG_B:
4881                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b,
4882                                  rte_be_to_cpu_32(mask));
4883                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b,
4884                                 rte_be_to_cpu_32(value));
4885                 break;
4886         case REG_C_0:
4887                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0,
4888                                  rte_be_to_cpu_32(mask));
4889                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0,
4890                                 rte_be_to_cpu_32(value));
4891                 break;
4892         case REG_C_1:
4893                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1,
4894                                  rte_be_to_cpu_32(mask));
4895                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1,
4896                                 rte_be_to_cpu_32(value));
4897                 break;
4898         case REG_C_2:
4899                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2,
4900                                  rte_be_to_cpu_32(mask));
4901                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2,
4902                                 rte_be_to_cpu_32(value));
4903                 break;
4904         case REG_C_3:
4905                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3,
4906                                  rte_be_to_cpu_32(mask));
4907                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3,
4908                                 rte_be_to_cpu_32(value));
4909                 break;
4910         case REG_C_4:
4911                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4,
4912                                  rte_be_to_cpu_32(mask));
4913                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4,
4914                                 rte_be_to_cpu_32(value));
4915                 break;
4916         case REG_C_5:
4917                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5,
4918                                  rte_be_to_cpu_32(mask));
4919                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5,
4920                                 rte_be_to_cpu_32(value));
4921                 break;
4922         case REG_C_6:
4923                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6,
4924                                  rte_be_to_cpu_32(mask));
4925                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6,
4926                                 rte_be_to_cpu_32(value));
4927                 break;
4928         case REG_C_7:
4929                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7,
4930                                  rte_be_to_cpu_32(mask));
4931                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7,
4932                                 rte_be_to_cpu_32(value));
4933                 break;
4934         }
4935 }
4936
4937 /**
4938  * Add source vport match to the specified matcher.
4939  *
4940  * @param[in, out] matcher
4941  *   Flow matcher.
4942  * @param[in, out] key
4943  *   Flow matcher value.
4944  * @param[in] port
4945  *   Source vport value to match
4946  * @param[in] mask
4947  *   Mask
4948  */
4949 static void
4950 flow_dv_translate_item_source_vport(void *matcher, void *key,
4951                                     int16_t port, uint16_t mask)
4952 {
4953         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4954         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4955
4956         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
4957         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
4958 }
4959
4960 /**
4961  * Translate port-id item to eswitch match on  port-id.
4962  *
4963  * @param[in] dev
4964  *   The devich to configure through.
4965  * @param[in, out] matcher
4966  *   Flow matcher.
4967  * @param[in, out] key
4968  *   Flow matcher value.
4969  * @param[in] item
4970  *   Flow pattern to translate.
4971  *
4972  * @return
4973  *   0 on success, a negative errno value otherwise.
4974  */
4975 static int
4976 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
4977                                void *key, const struct rte_flow_item *item)
4978 {
4979         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
4980         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
4981         struct mlx5_priv *priv;
4982         uint16_t mask, id;
4983
4984         mask = pid_m ? pid_m->id : 0xffff;
4985         id = pid_v ? pid_v->id : dev->data->port_id;
4986         priv = mlx5_port_to_eswitch_info(id);
4987         if (!priv)
4988                 return -rte_errno;
4989         /* Translate to vport field or to metadata, depending on mode. */
4990         if (priv->vport_meta_mask)
4991                 flow_dv_translate_item_meta_vport(matcher, key,
4992                                                   priv->vport_meta_tag,
4993                                                   priv->vport_meta_mask);
4994         else
4995                 flow_dv_translate_item_source_vport(matcher, key,
4996                                                     priv->vport_id, mask);
4997         return 0;
4998 }
4999
5000 /**
5001  * Add ICMP6 item to matcher and to the value.
5002  *
5003  * @param[in, out] matcher
5004  *   Flow matcher.
5005  * @param[in, out] key
5006  *   Flow matcher value.
5007  * @param[in] item
5008  *   Flow pattern to translate.
5009  * @param[in] inner
5010  *   Item is inner pattern.
5011  */
5012 static void
5013 flow_dv_translate_item_icmp6(void *matcher, void *key,
5014                               const struct rte_flow_item *item,
5015                               int inner)
5016 {
5017         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5018         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5019         void *headers_m;
5020         void *headers_v;
5021         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5022                                      misc_parameters_3);
5023         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5024         if (inner) {
5025                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5026                                          inner_headers);
5027                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5028         } else {
5029                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5030                                          outer_headers);
5031                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5032         }
5033         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5034         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5035         if (!icmp6_v)
5036                 return;
5037         if (!icmp6_m)
5038                 icmp6_m = &rte_flow_item_icmp6_mask;
5039         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5040         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5041                  icmp6_v->type & icmp6_m->type);
5042         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5043         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5044                  icmp6_v->code & icmp6_m->code);
5045 }
5046
5047 /**
5048  * Add ICMP item to matcher and to the value.
5049  *
5050  * @param[in, out] matcher
5051  *   Flow matcher.
5052  * @param[in, out] key
5053  *   Flow matcher value.
5054  * @param[in] item
5055  *   Flow pattern to translate.
5056  * @param[in] inner
5057  *   Item is inner pattern.
5058  */
5059 static void
5060 flow_dv_translate_item_icmp(void *matcher, void *key,
5061                             const struct rte_flow_item *item,
5062                             int inner)
5063 {
5064         const struct rte_flow_item_icmp *icmp_m = item->mask;
5065         const struct rte_flow_item_icmp *icmp_v = item->spec;
5066         void *headers_m;
5067         void *headers_v;
5068         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5069                                      misc_parameters_3);
5070         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5071         if (inner) {
5072                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5073                                          inner_headers);
5074                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5075         } else {
5076                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5077                                          outer_headers);
5078                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5079         }
5080         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5081         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5082         if (!icmp_v)
5083                 return;
5084         if (!icmp_m)
5085                 icmp_m = &rte_flow_item_icmp_mask;
5086         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5087                  icmp_m->hdr.icmp_type);
5088         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5089                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5090         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5091                  icmp_m->hdr.icmp_code);
5092         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5093                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5094 }
5095
5096 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5097
5098 #define HEADER_IS_ZERO(match_criteria, headers)                              \
5099         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
5100                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5101
5102 /**
5103  * Calculate flow matcher enable bitmap.
5104  *
5105  * @param match_criteria
5106  *   Pointer to flow matcher criteria.
5107  *
5108  * @return
5109  *   Bitmap of enabled fields.
5110  */
5111 static uint8_t
5112 flow_dv_matcher_enable(uint32_t *match_criteria)
5113 {
5114         uint8_t match_criteria_enable;
5115
5116         match_criteria_enable =
5117                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5118                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5119         match_criteria_enable |=
5120                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5121                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5122         match_criteria_enable |=
5123                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5124                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5125         match_criteria_enable |=
5126                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5127                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5128         match_criteria_enable |=
5129                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5130                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5131         return match_criteria_enable;
5132 }
5133
5134
5135 /**
5136  * Get a flow table.
5137  *
5138  * @param dev[in, out]
5139  *   Pointer to rte_eth_dev structure.
5140  * @param[in] table_id
5141  *   Table id to use.
5142  * @param[in] egress
5143  *   Direction of the table.
5144  * @param[in] transfer
5145  *   E-Switch or NIC flow.
5146  * @param[out] error
5147  *   pointer to error structure.
5148  *
5149  * @return
5150  *   Returns tables resource based on the index, NULL in case of failed.
5151  */
5152 static struct mlx5_flow_tbl_resource *
5153 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5154                          uint32_t table_id, uint8_t egress,
5155                          uint8_t transfer,
5156                          struct rte_flow_error *error)
5157 {
5158         struct mlx5_priv *priv = dev->data->dev_private;
5159         struct mlx5_ibv_shared *sh = priv->sh;
5160         struct mlx5_flow_tbl_resource *tbl;
5161
5162 #ifdef HAVE_MLX5DV_DR
5163         if (transfer) {
5164                 tbl = &sh->fdb_tbl[table_id];
5165                 if (!tbl->obj)
5166                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5167                                 (sh->fdb_domain, table_id);
5168         } else if (egress) {
5169                 tbl = &sh->tx_tbl[table_id];
5170                 if (!tbl->obj)
5171                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5172                                 (sh->tx_domain, table_id);
5173         } else {
5174                 tbl = &sh->rx_tbl[table_id];
5175                 if (!tbl->obj)
5176                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5177                                 (sh->rx_domain, table_id);
5178         }
5179         if (!tbl->obj) {
5180                 rte_flow_error_set(error, ENOMEM,
5181                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5182                                    NULL, "cannot create table");
5183                 return NULL;
5184         }
5185         rte_atomic32_inc(&tbl->refcnt);
5186         return tbl;
5187 #else
5188         (void)error;
5189         (void)tbl;
5190         if (transfer)
5191                 return &sh->fdb_tbl[table_id];
5192         else if (egress)
5193                 return &sh->tx_tbl[table_id];
5194         else
5195                 return &sh->rx_tbl[table_id];
5196 #endif
5197 }
5198
5199 /**
5200  * Release a flow table.
5201  *
5202  * @param[in] tbl
5203  *   Table resource to be released.
5204  *
5205  * @return
5206  *   Returns 0 if table was released, else return 1;
5207  */
5208 static int
5209 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5210 {
5211         if (!tbl)
5212                 return 0;
5213         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5214                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5215                 tbl->obj = NULL;
5216                 return 0;
5217         }
5218         return 1;
5219 }
5220
5221 /**
5222  * Register the flow matcher.
5223  *
5224  * @param dev[in, out]
5225  *   Pointer to rte_eth_dev structure.
5226  * @param[in, out] matcher
5227  *   Pointer to flow matcher.
5228  * @parm[in, out] dev_flow
5229  *   Pointer to the dev_flow.
5230  * @param[out] error
5231  *   pointer to error structure.
5232  *
5233  * @return
5234  *   0 on success otherwise -errno and errno is set.
5235  */
5236 static int
5237 flow_dv_matcher_register(struct rte_eth_dev *dev,
5238                          struct mlx5_flow_dv_matcher *matcher,
5239                          struct mlx5_flow *dev_flow,
5240                          struct rte_flow_error *error)
5241 {
5242         struct mlx5_priv *priv = dev->data->dev_private;
5243         struct mlx5_ibv_shared *sh = priv->sh;
5244         struct mlx5_flow_dv_matcher *cache_matcher;
5245         struct mlx5dv_flow_matcher_attr dv_attr = {
5246                 .type = IBV_FLOW_ATTR_NORMAL,
5247                 .match_mask = (void *)&matcher->mask,
5248         };
5249         struct mlx5_flow_tbl_resource *tbl = NULL;
5250
5251         /* Lookup from cache. */
5252         LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5253                 if (matcher->crc == cache_matcher->crc &&
5254                     matcher->priority == cache_matcher->priority &&
5255                     matcher->egress == cache_matcher->egress &&
5256                     matcher->group == cache_matcher->group &&
5257                     matcher->transfer == cache_matcher->transfer &&
5258                     !memcmp((const void *)matcher->mask.buf,
5259                             (const void *)cache_matcher->mask.buf,
5260                             cache_matcher->mask.size)) {
5261                         DRV_LOG(DEBUG,
5262                                 "priority %hd use %s matcher %p: refcnt %d++",
5263                                 cache_matcher->priority,
5264                                 cache_matcher->egress ? "tx" : "rx",
5265                                 (void *)cache_matcher,
5266                                 rte_atomic32_read(&cache_matcher->refcnt));
5267                         rte_atomic32_inc(&cache_matcher->refcnt);
5268                         dev_flow->dv.matcher = cache_matcher;
5269                         return 0;
5270                 }
5271         }
5272         /* Register new matcher. */
5273         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5274         if (!cache_matcher)
5275                 return rte_flow_error_set(error, ENOMEM,
5276                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5277                                           "cannot allocate matcher memory");
5278         tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5279                                        matcher->egress, matcher->transfer,
5280                                        error);
5281         if (!tbl) {
5282                 rte_free(cache_matcher);
5283                 return rte_flow_error_set(error, ENOMEM,
5284                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5285                                           NULL, "cannot create table");
5286         }
5287         *cache_matcher = *matcher;
5288         dv_attr.match_criteria_enable =
5289                 flow_dv_matcher_enable(cache_matcher->mask.buf);
5290         dv_attr.priority = matcher->priority;
5291         if (matcher->egress)
5292                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5293         cache_matcher->matcher_object =
5294                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5295         if (!cache_matcher->matcher_object) {
5296                 rte_free(cache_matcher);
5297 #ifdef HAVE_MLX5DV_DR
5298                 flow_dv_tbl_resource_release(tbl);
5299 #endif
5300                 return rte_flow_error_set(error, ENOMEM,
5301                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5302                                           NULL, "cannot create matcher");
5303         }
5304         rte_atomic32_inc(&cache_matcher->refcnt);
5305         LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5306         dev_flow->dv.matcher = cache_matcher;
5307         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5308                 cache_matcher->priority,
5309                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5310                 rte_atomic32_read(&cache_matcher->refcnt));
5311         rte_atomic32_inc(&tbl->refcnt);
5312         return 0;
5313 }
5314
5315 /**
5316  * Find existing tag resource or create and register a new one.
5317  *
5318  * @param dev[in, out]
5319  *   Pointer to rte_eth_dev structure.
5320  * @param[in, out] resource
5321  *   Pointer to tag resource.
5322  * @parm[in, out] dev_flow
5323  *   Pointer to the dev_flow.
5324  * @param[out] error
5325  *   pointer to error structure.
5326  *
5327  * @return
5328  *   0 on success otherwise -errno and errno is set.
5329  */
5330 static int
5331 flow_dv_tag_resource_register
5332                         (struct rte_eth_dev *dev,
5333                          struct mlx5_flow_dv_tag_resource *resource,
5334                          struct mlx5_flow *dev_flow,
5335                          struct rte_flow_error *error)
5336 {
5337         struct mlx5_priv *priv = dev->data->dev_private;
5338         struct mlx5_ibv_shared *sh = priv->sh;
5339         struct mlx5_flow_dv_tag_resource *cache_resource;
5340
5341         /* Lookup a matching resource from cache. */
5342         LIST_FOREACH(cache_resource, &sh->tags, next) {
5343                 if (resource->tag == cache_resource->tag) {
5344                         DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5345                                 (void *)cache_resource,
5346                                 rte_atomic32_read(&cache_resource->refcnt));
5347                         rte_atomic32_inc(&cache_resource->refcnt);
5348                         dev_flow->flow->tag_resource = cache_resource;
5349                         return 0;
5350                 }
5351         }
5352         /* Register new  resource. */
5353         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5354         if (!cache_resource)
5355                 return rte_flow_error_set(error, ENOMEM,
5356                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5357                                           "cannot allocate resource memory");
5358         *cache_resource = *resource;
5359         cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5360                 (resource->tag);
5361         if (!cache_resource->action) {
5362                 rte_free(cache_resource);
5363                 return rte_flow_error_set(error, ENOMEM,
5364                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5365                                           NULL, "cannot create action");
5366         }
5367         rte_atomic32_init(&cache_resource->refcnt);
5368         rte_atomic32_inc(&cache_resource->refcnt);
5369         LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5370         dev_flow->flow->tag_resource = cache_resource;
5371         DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5372                 (void *)cache_resource,
5373                 rte_atomic32_read(&cache_resource->refcnt));
5374         return 0;
5375 }
5376
5377 /**
5378  * Release the tag.
5379  *
5380  * @param dev
5381  *   Pointer to Ethernet device.
5382  * @param flow
5383  *   Pointer to mlx5_flow.
5384  *
5385  * @return
5386  *   1 while a reference on it exists, 0 when freed.
5387  */
5388 static int
5389 flow_dv_tag_release(struct rte_eth_dev *dev,
5390                     struct mlx5_flow_dv_tag_resource *tag)
5391 {
5392         assert(tag);
5393         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5394                 dev->data->port_id, (void *)tag,
5395                 rte_atomic32_read(&tag->refcnt));
5396         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5397                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5398                 LIST_REMOVE(tag, next);
5399                 DRV_LOG(DEBUG, "port %u tag %p: removed",
5400                         dev->data->port_id, (void *)tag);
5401                 rte_free(tag);
5402                 return 0;
5403         }
5404         return 1;
5405 }
5406
5407 /**
5408  * Translate port ID action to vport.
5409  *
5410  * @param[in] dev
5411  *   Pointer to rte_eth_dev structure.
5412  * @param[in] action
5413  *   Pointer to the port ID action.
5414  * @param[out] dst_port_id
5415  *   The target port ID.
5416  * @param[out] error
5417  *   Pointer to the error structure.
5418  *
5419  * @return
5420  *   0 on success, a negative errno value otherwise and rte_errno is set.
5421  */
5422 static int
5423 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5424                                  const struct rte_flow_action *action,
5425                                  uint32_t *dst_port_id,
5426                                  struct rte_flow_error *error)
5427 {
5428         uint32_t port;
5429         struct mlx5_priv *priv;
5430         const struct rte_flow_action_port_id *conf =
5431                         (const struct rte_flow_action_port_id *)action->conf;
5432
5433         port = conf->original ? dev->data->port_id : conf->id;
5434         priv = mlx5_port_to_eswitch_info(port);
5435         if (!priv)
5436                 return rte_flow_error_set(error, -rte_errno,
5437                                           RTE_FLOW_ERROR_TYPE_ACTION,
5438                                           NULL,
5439                                           "No eswitch info was found for port");
5440         if (priv->vport_meta_mask)
5441                 *dst_port_id = priv->vport_meta_tag;
5442         else
5443                 *dst_port_id = priv->vport_id;
5444         return 0;
5445 }
5446
5447 /**
5448  * Add Tx queue matcher
5449  *
5450  * @param[in] dev
5451  *   Pointer to the dev struct.
5452  * @param[in, out] matcher
5453  *   Flow matcher.
5454  * @param[in, out] key
5455  *   Flow matcher value.
5456  * @param[in] item
5457  *   Flow pattern to translate.
5458  * @param[in] inner
5459  *   Item is inner pattern.
5460  */
5461 static void
5462 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5463                                 void *matcher, void *key,
5464                                 const struct rte_flow_item *item)
5465 {
5466         const struct mlx5_rte_flow_item_tx_queue *queue_m;
5467         const struct mlx5_rte_flow_item_tx_queue *queue_v;
5468         void *misc_m =
5469                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5470         void *misc_v =
5471                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5472         struct mlx5_txq_ctrl *txq;
5473         uint32_t queue;
5474
5475
5476         queue_m = (const void *)item->mask;
5477         if (!queue_m)
5478                 return;
5479         queue_v = (const void *)item->spec;
5480         if (!queue_v)
5481                 return;
5482         txq = mlx5_txq_get(dev, queue_v->queue);
5483         if (!txq)
5484                 return;
5485         queue = txq->obj->sq->id;
5486         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5487         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5488                  queue & queue_m->queue);
5489         mlx5_txq_release(dev, queue_v->queue);
5490 }
5491
5492 /**
5493  * Fill the flow with DV spec.
5494  *
5495  * @param[in] dev
5496  *   Pointer to rte_eth_dev structure.
5497  * @param[in, out] dev_flow
5498  *   Pointer to the sub flow.
5499  * @param[in] attr
5500  *   Pointer to the flow attributes.
5501  * @param[in] items
5502  *   Pointer to the list of items.
5503  * @param[in] actions
5504  *   Pointer to the list of actions.
5505  * @param[out] error
5506  *   Pointer to the error structure.
5507  *
5508  * @return
5509  *   0 on success, a negative errno value otherwise and rte_errno is set.
5510  */
5511 static int
5512 flow_dv_translate(struct rte_eth_dev *dev,
5513                   struct mlx5_flow *dev_flow,
5514                   const struct rte_flow_attr *attr,
5515                   const struct rte_flow_item items[],
5516                   const struct rte_flow_action actions[],
5517                   struct rte_flow_error *error)
5518 {
5519         struct mlx5_priv *priv = dev->data->dev_private;
5520         struct rte_flow *flow = dev_flow->flow;
5521         uint64_t item_flags = 0;
5522         uint64_t last_item = 0;
5523         uint64_t action_flags = 0;
5524         uint64_t priority = attr->priority;
5525         struct mlx5_flow_dv_matcher matcher = {
5526                 .mask = {
5527                         .size = sizeof(matcher.mask.buf),
5528                 },
5529         };
5530         int actions_n = 0;
5531         bool actions_end = false;
5532         struct mlx5_flow_dv_modify_hdr_resource res = {
5533                 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5534                                           MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5535         };
5536         union flow_dv_attr flow_attr = { .attr = 0 };
5537         struct mlx5_flow_dv_tag_resource tag_resource;
5538         uint32_t modify_action_position = UINT32_MAX;
5539         void *match_mask = matcher.mask.buf;
5540         void *match_value = dev_flow->dv.value.buf;
5541         uint8_t next_protocol = 0xff;
5542         struct rte_vlan_hdr vlan = { 0 };
5543         uint32_t table;
5544         int ret = 0;
5545
5546         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5547                                        &table, error);
5548         if (ret)
5549                 return ret;
5550         flow->group = table;
5551         if (attr->transfer)
5552                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5553         if (priority == MLX5_FLOW_PRIO_RSVD)
5554                 priority = priv->config.flow_prio - 1;
5555         for (; !actions_end ; actions++) {
5556                 const struct rte_flow_action_queue *queue;
5557                 const struct rte_flow_action_rss *rss;
5558                 const struct rte_flow_action *action = actions;
5559                 const struct rte_flow_action_count *count = action->conf;
5560                 const uint8_t *rss_key;
5561                 const struct rte_flow_action_jump *jump_data;
5562                 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5563                 struct mlx5_flow_tbl_resource *tbl;
5564                 uint32_t port_id = 0;
5565                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5566                 int action_type = actions->type;
5567                 const struct rte_flow_action *found_action = NULL;
5568
5569                 switch (action_type) {
5570                 case RTE_FLOW_ACTION_TYPE_VOID:
5571                         break;
5572                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5573                         if (flow_dv_translate_action_port_id(dev, action,
5574                                                              &port_id, error))
5575                                 return -rte_errno;
5576                         port_id_resource.port_id = port_id;
5577                         if (flow_dv_port_id_action_resource_register
5578                             (dev, &port_id_resource, dev_flow, error))
5579                                 return -rte_errno;
5580                         dev_flow->dv.actions[actions_n++] =
5581                                 dev_flow->dv.port_id_action->action;
5582                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5583                         break;
5584                 case RTE_FLOW_ACTION_TYPE_FLAG:
5585                         tag_resource.tag =
5586                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5587                         if (!flow->tag_resource)
5588                                 if (flow_dv_tag_resource_register
5589                                     (dev, &tag_resource, dev_flow, error))
5590                                         return errno;
5591                         dev_flow->dv.actions[actions_n++] =
5592                                 flow->tag_resource->action;
5593                         action_flags |= MLX5_FLOW_ACTION_FLAG;
5594                         break;
5595                 case RTE_FLOW_ACTION_TYPE_MARK:
5596                         tag_resource.tag = mlx5_flow_mark_set
5597                               (((const struct rte_flow_action_mark *)
5598                                (actions->conf))->id);
5599                         if (!flow->tag_resource)
5600                                 if (flow_dv_tag_resource_register
5601                                     (dev, &tag_resource, dev_flow, error))
5602                                         return errno;
5603                         dev_flow->dv.actions[actions_n++] =
5604                                 flow->tag_resource->action;
5605                         action_flags |= MLX5_FLOW_ACTION_MARK;
5606                         break;
5607                 case RTE_FLOW_ACTION_TYPE_DROP:
5608                         action_flags |= MLX5_FLOW_ACTION_DROP;
5609                         break;
5610                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5611                         queue = actions->conf;
5612                         flow->rss.queue_num = 1;
5613                         (*flow->queue)[0] = queue->index;
5614                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5615                         break;
5616                 case RTE_FLOW_ACTION_TYPE_RSS:
5617                         rss = actions->conf;
5618                         if (flow->queue)
5619                                 memcpy((*flow->queue), rss->queue,
5620                                        rss->queue_num * sizeof(uint16_t));
5621                         flow->rss.queue_num = rss->queue_num;
5622                         /* NULL RSS key indicates default RSS key. */
5623                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
5624                         memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5625                         /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
5626                         flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
5627                         flow->rss.level = rss->level;
5628                         action_flags |= MLX5_FLOW_ACTION_RSS;
5629                         break;
5630                 case RTE_FLOW_ACTION_TYPE_COUNT:
5631                         if (!priv->config.devx) {
5632                                 rte_errno = ENOTSUP;
5633                                 goto cnt_err;
5634                         }
5635                         flow->counter = flow_dv_counter_alloc(dev,
5636                                                               count->shared,
5637                                                               count->id,
5638                                                               flow->group);
5639                         if (flow->counter == NULL)
5640                                 goto cnt_err;
5641                         dev_flow->dv.actions[actions_n++] =
5642                                 flow->counter->action;
5643                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5644                         break;
5645 cnt_err:
5646                         if (rte_errno == ENOTSUP)
5647                                 return rte_flow_error_set
5648                                               (error, ENOTSUP,
5649                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5650                                                NULL,
5651                                                "count action not supported");
5652                         else
5653                                 return rte_flow_error_set
5654                                                 (error, rte_errno,
5655                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5656                                                  action,
5657                                                  "cannot create counter"
5658                                                   " object.");
5659                         break;
5660                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5661                         dev_flow->dv.actions[actions_n++] =
5662                                                 priv->sh->pop_vlan_action;
5663                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5664                         break;
5665                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5666                         flow_dev_get_vlan_info_from_items(items, &vlan);
5667                         vlan.eth_proto = rte_be_to_cpu_16
5668                              ((((const struct rte_flow_action_of_push_vlan *)
5669                                                    actions->conf)->ethertype));
5670                         found_action = mlx5_flow_find_action
5671                                         (actions + 1,
5672                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5673                         if (found_action)
5674                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5675                         found_action = mlx5_flow_find_action
5676                                         (actions + 1,
5677                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5678                         if (found_action)
5679                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5680                         if (flow_dv_create_action_push_vlan
5681                                             (dev, attr, &vlan, dev_flow, error))
5682                                 return -rte_errno;
5683                         dev_flow->dv.actions[actions_n++] =
5684                                            dev_flow->dv.push_vlan_res->action;
5685                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5686                         break;
5687                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5688                         /* of_vlan_push action handled this action */
5689                         assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5690                         break;
5691                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5692                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5693                                 break;
5694                         flow_dev_get_vlan_info_from_items(items, &vlan);
5695                         mlx5_update_vlan_vid_pcp(actions, &vlan);
5696                         /* If no VLAN push - this is a modify header action */
5697                         if (flow_dv_convert_action_modify_vlan_vid
5698                                                         (&res, actions, error))
5699                                 return -rte_errno;
5700                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5701                         break;
5702                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5703                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5704                         if (flow_dv_create_action_l2_encap(dev, actions,
5705                                                            dev_flow,
5706                                                            attr->transfer,
5707                                                            error))
5708                                 return -rte_errno;
5709                         dev_flow->dv.actions[actions_n++] =
5710                                 dev_flow->dv.encap_decap->verbs_action;
5711                         action_flags |= actions->type ==
5712                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5713                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
5714                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
5715                         break;
5716                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5717                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5718                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
5719                                                            attr->transfer,
5720                                                            error))
5721                                 return -rte_errno;
5722                         dev_flow->dv.actions[actions_n++] =
5723                                 dev_flow->dv.encap_decap->verbs_action;
5724                         action_flags |= actions->type ==
5725                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5726                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
5727                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
5728                         break;
5729                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5730                         /* Handle encap with preceding decap. */
5731                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5732                                 if (flow_dv_create_action_raw_encap
5733                                         (dev, actions, dev_flow, attr, error))
5734                                         return -rte_errno;
5735                                 dev_flow->dv.actions[actions_n++] =
5736                                         dev_flow->dv.encap_decap->verbs_action;
5737                         } else {
5738                                 /* Handle encap without preceding decap. */
5739                                 if (flow_dv_create_action_l2_encap
5740                                     (dev, actions, dev_flow, attr->transfer,
5741                                      error))
5742                                         return -rte_errno;
5743                                 dev_flow->dv.actions[actions_n++] =
5744                                         dev_flow->dv.encap_decap->verbs_action;
5745                         }
5746                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5747                         break;
5748                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5749                         /* Check if this decap is followed by encap. */
5750                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5751                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5752                                action++) {
5753                         }
5754                         /* Handle decap only if it isn't followed by encap. */
5755                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5756                                 if (flow_dv_create_action_l2_decap
5757                                     (dev, dev_flow, attr->transfer, error))
5758                                         return -rte_errno;
5759                                 dev_flow->dv.actions[actions_n++] =
5760                                         dev_flow->dv.encap_decap->verbs_action;
5761                         }
5762                         /* If decap is followed by encap, handle it at encap. */
5763                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5764                         break;
5765                 case RTE_FLOW_ACTION_TYPE_JUMP:
5766                         jump_data = action->conf;
5767                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5768                                                        jump_data->group, &table,
5769                                                        error);
5770                         if (ret)
5771                                 return ret;
5772                         tbl = flow_dv_tbl_resource_get(dev, table,
5773                                                        attr->egress,
5774                                                        attr->transfer, error);
5775                         if (!tbl)
5776                                 return rte_flow_error_set
5777                                                 (error, errno,
5778                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5779                                                  NULL,
5780                                                  "cannot create jump action.");
5781                         jump_tbl_resource.tbl = tbl;
5782                         if (flow_dv_jump_tbl_resource_register
5783                             (dev, &jump_tbl_resource, dev_flow, error)) {
5784                                 flow_dv_tbl_resource_release(tbl);
5785                                 return rte_flow_error_set
5786                                                 (error, errno,
5787                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5788                                                  NULL,
5789                                                  "cannot create jump action.");
5790                         }
5791                         dev_flow->dv.actions[actions_n++] =
5792                                 dev_flow->dv.jump->action;
5793                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5794                         break;
5795                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5796                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5797                         if (flow_dv_convert_action_modify_mac(&res, actions,
5798                                                               error))
5799                                 return -rte_errno;
5800                         action_flags |= actions->type ==
5801                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5802                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
5803                                         MLX5_FLOW_ACTION_SET_MAC_DST;
5804                         break;
5805                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5806                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5807                         if (flow_dv_convert_action_modify_ipv4(&res, actions,
5808                                                                error))
5809                                 return -rte_errno;
5810                         action_flags |= actions->type ==
5811                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5812                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
5813                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
5814                         break;
5815                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5816                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5817                         if (flow_dv_convert_action_modify_ipv6(&res, actions,
5818                                                                error))
5819                                 return -rte_errno;
5820                         action_flags |= actions->type ==
5821                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5822                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
5823                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
5824                         break;
5825                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5826                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5827                         if (flow_dv_convert_action_modify_tp(&res, actions,
5828                                                              items, &flow_attr,
5829                                                              error))
5830                                 return -rte_errno;
5831                         action_flags |= actions->type ==
5832                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5833                                         MLX5_FLOW_ACTION_SET_TP_SRC :
5834                                         MLX5_FLOW_ACTION_SET_TP_DST;
5835                         break;
5836                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5837                         if (flow_dv_convert_action_modify_dec_ttl(&res, items,
5838                                                                   &flow_attr,
5839                                                                   error))
5840                                 return -rte_errno;
5841                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
5842                         break;
5843                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5844                         if (flow_dv_convert_action_modify_ttl(&res, actions,
5845                                                              items, &flow_attr,
5846                                                              error))
5847                                 return -rte_errno;
5848                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5851                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5852                         if (flow_dv_convert_action_modify_tcp_seq(&res, actions,
5853                                                                   error))
5854                                 return -rte_errno;
5855                         action_flags |= actions->type ==
5856                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5857                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
5858                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5859                         break;
5860
5861                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5862                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5863                         if (flow_dv_convert_action_modify_tcp_ack(&res, actions,
5864                                                                   error))
5865                                 return -rte_errno;
5866                         action_flags |= actions->type ==
5867                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5868                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
5869                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
5870                         break;
5871                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5872                         if (flow_dv_convert_action_set_reg(&res, actions,
5873                                                            error))
5874                                 return -rte_errno;
5875                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5876                         break;
5877                 case RTE_FLOW_ACTION_TYPE_END:
5878                         actions_end = true;
5879                         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
5880                                 /* create modify action if needed. */
5881                                 if (flow_dv_modify_hdr_resource_register
5882                                                                 (dev, &res,
5883                                                                  dev_flow,
5884                                                                  error))
5885                                         return -rte_errno;
5886                                 dev_flow->dv.actions[modify_action_position] =
5887                                         dev_flow->dv.modify_hdr->verbs_action;
5888                         }
5889                         break;
5890                 default:
5891                         break;
5892                 }
5893                 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
5894                     modify_action_position == UINT32_MAX)
5895                         modify_action_position = actions_n++;
5896         }
5897         dev_flow->dv.actions_n = actions_n;
5898         dev_flow->actions = action_flags;
5899         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5900                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5901                 int item_type = items->type;
5902
5903                 switch (item_type) {
5904                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5905                         flow_dv_translate_item_port_id(dev, match_mask,
5906                                                        match_value, items);
5907                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5908                         break;
5909                 case RTE_FLOW_ITEM_TYPE_ETH:
5910                         flow_dv_translate_item_eth(match_mask, match_value,
5911                                                    items, tunnel);
5912                         matcher.priority = MLX5_PRIORITY_MAP_L2;
5913                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5914                                              MLX5_FLOW_LAYER_OUTER_L2;
5915                         break;
5916                 case RTE_FLOW_ITEM_TYPE_VLAN:
5917                         flow_dv_translate_item_vlan(dev_flow,
5918                                                     match_mask, match_value,
5919                                                     items, tunnel);
5920                         matcher.priority = MLX5_PRIORITY_MAP_L2;
5921                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
5922                                               MLX5_FLOW_LAYER_INNER_VLAN) :
5923                                              (MLX5_FLOW_LAYER_OUTER_L2 |
5924                                               MLX5_FLOW_LAYER_OUTER_VLAN);
5925                         break;
5926                 case RTE_FLOW_ITEM_TYPE_IPV4:
5927                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5928                                                   &item_flags, &tunnel);
5929                         flow_dv_translate_item_ipv4(match_mask, match_value,
5930                                                     items, tunnel, flow->group);
5931                         matcher.priority = MLX5_PRIORITY_MAP_L3;
5932                         dev_flow->dv.hash_fields |=
5933                                 mlx5_flow_hashfields_adjust
5934                                         (dev_flow, tunnel,
5935                                          MLX5_IPV4_LAYER_TYPES,
5936                                          MLX5_IPV4_IBV_RX_HASH);
5937                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5938                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5939                         if (items->mask != NULL &&
5940                             ((const struct rte_flow_item_ipv4 *)
5941                              items->mask)->hdr.next_proto_id) {
5942                                 next_protocol =
5943                                         ((const struct rte_flow_item_ipv4 *)
5944                                          (items->spec))->hdr.next_proto_id;
5945                                 next_protocol &=
5946                                         ((const struct rte_flow_item_ipv4 *)
5947                                          (items->mask))->hdr.next_proto_id;
5948                         } else {
5949                                 /* Reset for inner layer. */
5950                                 next_protocol = 0xff;
5951                         }
5952                         break;
5953                 case RTE_FLOW_ITEM_TYPE_IPV6:
5954                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5955                                                   &item_flags, &tunnel);
5956                         flow_dv_translate_item_ipv6(match_mask, match_value,
5957                                                     items, tunnel, flow->group);
5958                         matcher.priority = MLX5_PRIORITY_MAP_L3;
5959                         dev_flow->dv.hash_fields |=
5960                                 mlx5_flow_hashfields_adjust
5961                                         (dev_flow, tunnel,
5962                                          MLX5_IPV6_LAYER_TYPES,
5963                                          MLX5_IPV6_IBV_RX_HASH);
5964                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5965                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5966                         if (items->mask != NULL &&
5967                             ((const struct rte_flow_item_ipv6 *)
5968                              items->mask)->hdr.proto) {
5969                                 next_protocol =
5970                                         ((const struct rte_flow_item_ipv6 *)
5971                                          items->spec)->hdr.proto;
5972                                 next_protocol &=
5973                                         ((const struct rte_flow_item_ipv6 *)
5974                                          items->mask)->hdr.proto;
5975                         } else {
5976                                 /* Reset for inner layer. */
5977                                 next_protocol = 0xff;
5978                         }
5979                         break;
5980                 case RTE_FLOW_ITEM_TYPE_TCP:
5981                         flow_dv_translate_item_tcp(match_mask, match_value,
5982                                                    items, tunnel);
5983                         matcher.priority = MLX5_PRIORITY_MAP_L4;
5984                         dev_flow->dv.hash_fields |=
5985                                 mlx5_flow_hashfields_adjust
5986                                         (dev_flow, tunnel, ETH_RSS_TCP,
5987                                          IBV_RX_HASH_SRC_PORT_TCP |
5988                                          IBV_RX_HASH_DST_PORT_TCP);
5989                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5990                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5991                         break;
5992                 case RTE_FLOW_ITEM_TYPE_UDP:
5993                         flow_dv_translate_item_udp(match_mask, match_value,
5994                                                    items, tunnel);
5995                         matcher.priority = MLX5_PRIORITY_MAP_L4;
5996                         dev_flow->dv.hash_fields |=
5997                                 mlx5_flow_hashfields_adjust
5998                                         (dev_flow, tunnel, ETH_RSS_UDP,
5999                                          IBV_RX_HASH_SRC_PORT_UDP |
6000                                          IBV_RX_HASH_DST_PORT_UDP);
6001                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6002                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6003                         break;
6004                 case RTE_FLOW_ITEM_TYPE_GRE:
6005                         flow_dv_translate_item_gre(match_mask, match_value,
6006                                                    items, tunnel);
6007                         last_item = MLX5_FLOW_LAYER_GRE;
6008                         break;
6009                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6010                         flow_dv_translate_item_gre_key(match_mask,
6011                                                        match_value, items);
6012                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6013                         break;
6014                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6015                         flow_dv_translate_item_nvgre(match_mask, match_value,
6016                                                      items, tunnel);
6017                         last_item = MLX5_FLOW_LAYER_GRE;
6018                         break;
6019                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6020                         flow_dv_translate_item_vxlan(match_mask, match_value,
6021                                                      items, tunnel);
6022                         last_item = MLX5_FLOW_LAYER_VXLAN;
6023                         break;
6024                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6025                         flow_dv_translate_item_vxlan(match_mask, match_value,
6026                                                      items, tunnel);
6027                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6028                         break;
6029                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6030                         flow_dv_translate_item_geneve(match_mask, match_value,
6031                                                       items, tunnel);
6032                         last_item = MLX5_FLOW_LAYER_GENEVE;
6033                         break;
6034                 case RTE_FLOW_ITEM_TYPE_MPLS:
6035                         flow_dv_translate_item_mpls(match_mask, match_value,
6036                                                     items, last_item, tunnel);
6037                         last_item = MLX5_FLOW_LAYER_MPLS;
6038                         break;
6039                 case RTE_FLOW_ITEM_TYPE_META:
6040                         flow_dv_translate_item_meta(match_mask, match_value,
6041                                                     items);
6042                         last_item = MLX5_FLOW_ITEM_METADATA;
6043                         break;
6044                 case RTE_FLOW_ITEM_TYPE_ICMP:
6045                         flow_dv_translate_item_icmp(match_mask, match_value,
6046                                                     items, tunnel);
6047                         last_item = MLX5_FLOW_LAYER_ICMP;
6048                         break;
6049                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6050                         flow_dv_translate_item_icmp6(match_mask, match_value,
6051                                                       items, tunnel);
6052                         last_item = MLX5_FLOW_LAYER_ICMP6;
6053                         break;
6054                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6055                         flow_dv_translate_item_tag(match_mask, match_value,
6056                                                    items);
6057                         last_item = MLX5_FLOW_ITEM_TAG;
6058                         break;
6059                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6060                         flow_dv_translate_item_tx_queue(dev, match_mask,
6061                                                         match_value,
6062                                                         items);
6063                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6064                         break;
6065                 default:
6066                         break;
6067                 }
6068                 item_flags |= last_item;
6069         }
6070         /*
6071          * In case of ingress traffic when E-Switch mode is enabled,
6072          * we have two cases where we need to set the source port manually.
6073          * The first one, is in case of Nic steering rule, and the second is
6074          * E-Switch rule where no port_id item was found. In both cases
6075          * the source port is set according the current port in use.
6076          */
6077         if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6078             (priv->representor || priv->master)) {
6079                 if (flow_dv_translate_item_port_id(dev, match_mask,
6080                                                    match_value, NULL))
6081                         return -rte_errno;
6082         }
6083         assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6084                                          dev_flow->dv.value.buf));
6085         dev_flow->layers = item_flags;
6086         /* Register matcher. */
6087         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6088                                     matcher.mask.size);
6089         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6090                                                      matcher.priority);
6091         matcher.egress = attr->egress;
6092         matcher.group = flow->group;
6093         matcher.transfer = attr->transfer;
6094         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6095                 return -rte_errno;
6096         return 0;
6097 }
6098
6099 /**
6100  * Apply the flow to the NIC.
6101  *
6102  * @param[in] dev
6103  *   Pointer to the Ethernet device structure.
6104  * @param[in, out] flow
6105  *   Pointer to flow structure.
6106  * @param[out] error
6107  *   Pointer to error structure.
6108  *
6109  * @return
6110  *   0 on success, a negative errno value otherwise and rte_errno is set.
6111  */
6112 static int
6113 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6114               struct rte_flow_error *error)
6115 {
6116         struct mlx5_flow_dv *dv;
6117         struct mlx5_flow *dev_flow;
6118         struct mlx5_priv *priv = dev->data->dev_private;
6119         int n;
6120         int err;
6121
6122         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6123                 dv = &dev_flow->dv;
6124                 n = dv->actions_n;
6125                 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6126                         if (flow->transfer) {
6127                                 dv->actions[n++] = priv->sh->esw_drop_action;
6128                         } else {
6129                                 dv->hrxq = mlx5_hrxq_drop_new(dev);
6130                                 if (!dv->hrxq) {
6131                                         rte_flow_error_set
6132                                                 (error, errno,
6133                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6134                                                  NULL,
6135                                                  "cannot get drop hash queue");
6136                                         goto error;
6137                                 }
6138                                 dv->actions[n++] = dv->hrxq->action;
6139                         }
6140                 } else if (dev_flow->actions &
6141                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6142                         struct mlx5_hrxq *hrxq;
6143
6144                         hrxq = mlx5_hrxq_get(dev, flow->key,
6145                                              MLX5_RSS_HASH_KEY_LEN,
6146                                              dv->hash_fields,
6147                                              (*flow->queue),
6148                                              flow->rss.queue_num);
6149                         if (!hrxq) {
6150                                 hrxq = mlx5_hrxq_new
6151                                         (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
6152                                          dv->hash_fields, (*flow->queue),
6153                                          flow->rss.queue_num,
6154                                          !!(dev_flow->layers &
6155                                             MLX5_FLOW_LAYER_TUNNEL));
6156                         }
6157                         if (!hrxq) {
6158                                 rte_flow_error_set
6159                                         (error, rte_errno,
6160                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6161                                          "cannot get hash queue");
6162                                 goto error;
6163                         }
6164                         dv->hrxq = hrxq;
6165                         dv->actions[n++] = dv->hrxq->action;
6166                 }
6167                 dv->flow =
6168                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6169                                                   (void *)&dv->value, n,
6170                                                   dv->actions);
6171                 if (!dv->flow) {
6172                         rte_flow_error_set(error, errno,
6173                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6174                                            NULL,
6175                                            "hardware refuses to create flow");
6176                         goto error;
6177                 }
6178                 if (priv->vmwa_context &&
6179                     dev_flow->dv.vf_vlan.tag &&
6180                     !dev_flow->dv.vf_vlan.created) {
6181                         /*
6182                          * The rule contains the VLAN pattern.
6183                          * For VF we are going to create VLAN
6184                          * interface to make hypervisor set correct
6185                          * e-Switch vport context.
6186                          */
6187                         mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6188                 }
6189         }
6190         return 0;
6191 error:
6192         err = rte_errno; /* Save rte_errno before cleanup. */
6193         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6194                 struct mlx5_flow_dv *dv = &dev_flow->dv;
6195                 if (dv->hrxq) {
6196                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6197                                 mlx5_hrxq_drop_release(dev);
6198                         else
6199                                 mlx5_hrxq_release(dev, dv->hrxq);
6200                         dv->hrxq = NULL;
6201                 }
6202                 if (dev_flow->dv.vf_vlan.tag &&
6203                     dev_flow->dv.vf_vlan.created)
6204                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6205         }
6206         rte_errno = err; /* Restore rte_errno. */
6207         return -rte_errno;
6208 }
6209
6210 /**
6211  * Release the flow matcher.
6212  *
6213  * @param dev
6214  *   Pointer to Ethernet device.
6215  * @param flow
6216  *   Pointer to mlx5_flow.
6217  *
6218  * @return
6219  *   1 while a reference on it exists, 0 when freed.
6220  */
6221 static int
6222 flow_dv_matcher_release(struct rte_eth_dev *dev,
6223                         struct mlx5_flow *flow)
6224 {
6225         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6226         struct mlx5_priv *priv = dev->data->dev_private;
6227         struct mlx5_ibv_shared *sh = priv->sh;
6228         struct mlx5_flow_tbl_resource *tbl;
6229
6230         assert(matcher->matcher_object);
6231         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6232                 dev->data->port_id, (void *)matcher,
6233                 rte_atomic32_read(&matcher->refcnt));
6234         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6235                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6236                            (matcher->matcher_object));
6237                 LIST_REMOVE(matcher, next);
6238                 if (matcher->egress)
6239                         tbl = &sh->tx_tbl[matcher->group];
6240                 else
6241                         tbl = &sh->rx_tbl[matcher->group];
6242                 flow_dv_tbl_resource_release(tbl);
6243                 rte_free(matcher);
6244                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6245                         dev->data->port_id, (void *)matcher);
6246                 return 0;
6247         }
6248         return 1;
6249 }
6250
6251 /**
6252  * Release an encap/decap resource.
6253  *
6254  * @param flow
6255  *   Pointer to mlx5_flow.
6256  *
6257  * @return
6258  *   1 while a reference on it exists, 0 when freed.
6259  */
6260 static int
6261 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6262 {
6263         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6264                                                 flow->dv.encap_decap;
6265
6266         assert(cache_resource->verbs_action);
6267         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6268                 (void *)cache_resource,
6269                 rte_atomic32_read(&cache_resource->refcnt));
6270         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6271                 claim_zero(mlx5_glue->destroy_flow_action
6272                                 (cache_resource->verbs_action));
6273                 LIST_REMOVE(cache_resource, next);
6274                 rte_free(cache_resource);
6275                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6276                         (void *)cache_resource);
6277                 return 0;
6278         }
6279         return 1;
6280 }
6281
6282 /**
6283  * Release an jump to table action resource.
6284  *
6285  * @param flow
6286  *   Pointer to mlx5_flow.
6287  *
6288  * @return
6289  *   1 while a reference on it exists, 0 when freed.
6290  */
6291 static int
6292 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6293 {
6294         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6295                                                 flow->dv.jump;
6296
6297         assert(cache_resource->action);
6298         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6299                 (void *)cache_resource,
6300                 rte_atomic32_read(&cache_resource->refcnt));
6301         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6302                 claim_zero(mlx5_glue->destroy_flow_action
6303                                 (cache_resource->action));
6304                 LIST_REMOVE(cache_resource, next);
6305                 flow_dv_tbl_resource_release(cache_resource->tbl);
6306                 rte_free(cache_resource);
6307                 DRV_LOG(DEBUG, "jump table resource %p: removed",
6308                         (void *)cache_resource);
6309                 return 0;
6310         }
6311         return 1;
6312 }
6313
6314 /**
6315  * Release a modify-header resource.
6316  *
6317  * @param flow
6318  *   Pointer to mlx5_flow.
6319  *
6320  * @return
6321  *   1 while a reference on it exists, 0 when freed.
6322  */
6323 static int
6324 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6325 {
6326         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6327                                                 flow->dv.modify_hdr;
6328
6329         assert(cache_resource->verbs_action);
6330         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6331                 (void *)cache_resource,
6332                 rte_atomic32_read(&cache_resource->refcnt));
6333         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6334                 claim_zero(mlx5_glue->destroy_flow_action
6335                                 (cache_resource->verbs_action));
6336                 LIST_REMOVE(cache_resource, next);
6337                 rte_free(cache_resource);
6338                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6339                         (void *)cache_resource);
6340                 return 0;
6341         }
6342         return 1;
6343 }
6344
6345 /**
6346  * Release port ID action resource.
6347  *
6348  * @param flow
6349  *   Pointer to mlx5_flow.
6350  *
6351  * @return
6352  *   1 while a reference on it exists, 0 when freed.
6353  */
6354 static int
6355 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6356 {
6357         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6358                 flow->dv.port_id_action;
6359
6360         assert(cache_resource->action);
6361         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6362                 (void *)cache_resource,
6363                 rte_atomic32_read(&cache_resource->refcnt));
6364         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6365                 claim_zero(mlx5_glue->destroy_flow_action
6366                                 (cache_resource->action));
6367                 LIST_REMOVE(cache_resource, next);
6368                 rte_free(cache_resource);
6369                 DRV_LOG(DEBUG, "port id action resource %p: removed",
6370                         (void *)cache_resource);
6371                 return 0;
6372         }
6373         return 1;
6374 }
6375
6376 /**
6377  * Release push vlan action resource.
6378  *
6379  * @param flow
6380  *   Pointer to mlx5_flow.
6381  *
6382  * @return
6383  *   1 while a reference on it exists, 0 when freed.
6384  */
6385 static int
6386 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6387 {
6388         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6389                 flow->dv.push_vlan_res;
6390
6391         assert(cache_resource->action);
6392         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6393                 (void *)cache_resource,
6394                 rte_atomic32_read(&cache_resource->refcnt));
6395         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6396                 claim_zero(mlx5_glue->destroy_flow_action
6397                                 (cache_resource->action));
6398                 LIST_REMOVE(cache_resource, next);
6399                 rte_free(cache_resource);
6400                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6401                         (void *)cache_resource);
6402                 return 0;
6403         }
6404         return 1;
6405 }
6406
6407 /**
6408  * Remove the flow from the NIC but keeps it in memory.
6409  *
6410  * @param[in] dev
6411  *   Pointer to Ethernet device.
6412  * @param[in, out] flow
6413  *   Pointer to flow structure.
6414  */
6415 static void
6416 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6417 {
6418         struct mlx5_flow_dv *dv;
6419         struct mlx5_flow *dev_flow;
6420
6421         if (!flow)
6422                 return;
6423         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6424                 dv = &dev_flow->dv;
6425                 if (dv->flow) {
6426                         claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6427                         dv->flow = NULL;
6428                 }
6429                 if (dv->hrxq) {
6430                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6431                                 mlx5_hrxq_drop_release(dev);
6432                         else
6433                                 mlx5_hrxq_release(dev, dv->hrxq);
6434                         dv->hrxq = NULL;
6435                 }
6436                 if (dev_flow->dv.vf_vlan.tag &&
6437                     dev_flow->dv.vf_vlan.created)
6438                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6439         }
6440 }
6441
6442 /**
6443  * Remove the flow from the NIC and the memory.
6444  *
6445  * @param[in] dev
6446  *   Pointer to the Ethernet device structure.
6447  * @param[in, out] flow
6448  *   Pointer to flow structure.
6449  */
6450 static void
6451 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6452 {
6453         struct mlx5_flow *dev_flow;
6454
6455         if (!flow)
6456                 return;
6457         flow_dv_remove(dev, flow);
6458         if (flow->counter) {
6459                 flow_dv_counter_release(dev, flow->counter);
6460                 flow->counter = NULL;
6461         }
6462         if (flow->tag_resource) {
6463                 flow_dv_tag_release(dev, flow->tag_resource);
6464                 flow->tag_resource = NULL;
6465         }
6466         while (!LIST_EMPTY(&flow->dev_flows)) {
6467                 dev_flow = LIST_FIRST(&flow->dev_flows);
6468                 LIST_REMOVE(dev_flow, next);
6469                 if (dev_flow->dv.matcher)
6470                         flow_dv_matcher_release(dev, dev_flow);
6471                 if (dev_flow->dv.encap_decap)
6472                         flow_dv_encap_decap_resource_release(dev_flow);
6473                 if (dev_flow->dv.modify_hdr)
6474                         flow_dv_modify_hdr_resource_release(dev_flow);
6475                 if (dev_flow->dv.jump)
6476                         flow_dv_jump_tbl_resource_release(dev_flow);
6477                 if (dev_flow->dv.port_id_action)
6478                         flow_dv_port_id_action_resource_release(dev_flow);
6479                 if (dev_flow->dv.push_vlan_res)
6480                         flow_dv_push_vlan_action_resource_release(dev_flow);
6481                 rte_free(dev_flow);
6482         }
6483 }
6484
6485 /**
6486  * Query a dv flow  rule for its statistics via devx.
6487  *
6488  * @param[in] dev
6489  *   Pointer to Ethernet device.
6490  * @param[in] flow
6491  *   Pointer to the sub flow.
6492  * @param[out] data
6493  *   data retrieved by the query.
6494  * @param[out] error
6495  *   Perform verbose error reporting if not NULL.
6496  *
6497  * @return
6498  *   0 on success, a negative errno value otherwise and rte_errno is set.
6499  */
6500 static int
6501 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6502                     void *data, struct rte_flow_error *error)
6503 {
6504         struct mlx5_priv *priv = dev->data->dev_private;
6505         struct rte_flow_query_count *qc = data;
6506
6507         if (!priv->config.devx)
6508                 return rte_flow_error_set(error, ENOTSUP,
6509                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6510                                           NULL,
6511                                           "counters are not supported");
6512         if (flow->counter) {
6513                 uint64_t pkts, bytes;
6514                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6515                                                &bytes);
6516
6517                 if (err)
6518                         return rte_flow_error_set(error, -err,
6519                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6520                                         NULL, "cannot read counters");
6521                 qc->hits_set = 1;
6522                 qc->bytes_set = 1;
6523                 qc->hits = pkts - flow->counter->hits;
6524                 qc->bytes = bytes - flow->counter->bytes;
6525                 if (qc->reset) {
6526                         flow->counter->hits = pkts;
6527                         flow->counter->bytes = bytes;
6528                 }
6529                 return 0;
6530         }
6531         return rte_flow_error_set(error, EINVAL,
6532                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6533                                   NULL,
6534                                   "counters are not available");
6535 }
6536
6537 /**
6538  * Query a flow.
6539  *
6540  * @see rte_flow_query()
6541  * @see rte_flow_ops
6542  */
6543 static int
6544 flow_dv_query(struct rte_eth_dev *dev,
6545               struct rte_flow *flow __rte_unused,
6546               const struct rte_flow_action *actions __rte_unused,
6547               void *data __rte_unused,
6548               struct rte_flow_error *error __rte_unused)
6549 {
6550         int ret = -EINVAL;
6551
6552         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6553                 switch (actions->type) {
6554                 case RTE_FLOW_ACTION_TYPE_VOID:
6555                         break;
6556                 case RTE_FLOW_ACTION_TYPE_COUNT:
6557                         ret = flow_dv_query_count(dev, flow, data, error);
6558                         break;
6559                 default:
6560                         return rte_flow_error_set(error, ENOTSUP,
6561                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6562                                                   actions,
6563                                                   "action not supported");
6564                 }
6565         }
6566         return ret;
6567 }
6568
6569 /*
6570  * Mutex-protected thunk to flow_dv_translate().
6571  */
6572 static int
6573 flow_d_translate(struct rte_eth_dev *dev,
6574                  struct mlx5_flow *dev_flow,
6575                  const struct rte_flow_attr *attr,
6576                  const struct rte_flow_item items[],
6577                  const struct rte_flow_action actions[],
6578                  struct rte_flow_error *error)
6579 {
6580         int ret;
6581
6582         flow_d_shared_lock(dev);
6583         ret = flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6584         flow_d_shared_unlock(dev);
6585         return ret;
6586 }
6587
6588 /*
6589  * Mutex-protected thunk to flow_dv_apply().
6590  */
6591 static int
6592 flow_d_apply(struct rte_eth_dev *dev,
6593              struct rte_flow *flow,
6594              struct rte_flow_error *error)
6595 {
6596         int ret;
6597
6598         flow_d_shared_lock(dev);
6599         ret = flow_dv_apply(dev, flow, error);
6600         flow_d_shared_unlock(dev);
6601         return ret;
6602 }
6603
6604 /*
6605  * Mutex-protected thunk to flow_dv_remove().
6606  */
6607 static void
6608 flow_d_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6609 {
6610         flow_d_shared_lock(dev);
6611         flow_dv_remove(dev, flow);
6612         flow_d_shared_unlock(dev);
6613 }
6614
6615 /*
6616  * Mutex-protected thunk to flow_dv_destroy().
6617  */
6618 static void
6619 flow_d_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6620 {
6621         flow_d_shared_lock(dev);
6622         flow_dv_destroy(dev, flow);
6623         flow_d_shared_unlock(dev);
6624 }
6625
6626 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6627         .validate = flow_dv_validate,
6628         .prepare = flow_dv_prepare,
6629         .translate = flow_d_translate,
6630         .apply = flow_d_apply,
6631         .remove = flow_d_remove,
6632         .destroy = flow_d_destroy,
6633         .query = flow_dv_query,
6634 };
6635
6636 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */