drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rx.h"
  36 #include "mlx5_tx.h"
  37 #include "rte_pmd_mlx5.h"
  38
  39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  40
  41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  43 #endif
  44
  45 #ifndef HAVE_MLX5DV_DR_ESWITCH
  46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  48 #endif
  49 #endif
  50
  51 #ifndef HAVE_MLX5DV_DR
  52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  53 #endif
  54
  55 /* VLAN header definitions */
  56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  61
  62 union flow_dv_attr {
  63         struct {
  64                 uint32_t valid:1;
  65                 uint32_t ipv4:1;
  66                 uint32_t ipv6:1;
  67                 uint32_t tcp:1;
  68                 uint32_t udp:1;
  69                 uint32_t reserved:27;
  70         };
  71         uint32_t attr;
  72 };
  73
  74 static int
  75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  76                              struct mlx5_flow_tbl_resource *tbl);
  77
  78 static int
  79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  80                                      uint32_t encap_decap_idx);
  81
  82 static int
  83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  84                                         uint32_t port_id);
  85 static void
  86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  87
  88 static int
  89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  90                                   uint32_t rix_jump);
  91
  92 /**
  93  * Initialize flow attributes structure according to flow items' types.
  94  *
  95  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  96  * mode. For tunnel mode, the items to be modified are the outermost ones.
  97  *
  98  * @param[in] item
  99  *   Pointer to item specification.
 100  * @param[out] attr
 101  *   Pointer to flow attributes structure.
 102  * @param[in] dev_flow
 103  *   Pointer to the sub flow.
 104  * @param[in] tunnel_decap
 105  *   Whether action is after tunnel decapsulation.
 106  */
 107 static void
 108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 109                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 110 {
 111         uint64_t layers = dev_flow->handle->layers;
 112
 113         /*
 114          * If layers is already initialized, it means this dev_flow is the
 115          * suffix flow, the layers flags is set by the prefix flow. Need to
 116          * use the layer flags from prefix flow as the suffix flow may not
 117          * have the user defined items as the flow is split.
 118          */
 119         if (layers) {
 120                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 121                         attr->ipv4 = 1;
 122                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 123                         attr->ipv6 = 1;
 124                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 125                         attr->tcp = 1;
 126                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 127                         attr->udp = 1;
 128                 attr->valid = 1;
 129                 return;
 130         }
 131         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 132                 uint8_t next_protocol = 0xff;
 133                 switch (item->type) {
 134                 case RTE_FLOW_ITEM_TYPE_GRE:
 135                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 137                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 138                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 139                 case RTE_FLOW_ITEM_TYPE_MPLS:
 140                         if (tunnel_decap)
 141                                 attr->attr = 0;
 142                         break;
 143                 case RTE_FLOW_ITEM_TYPE_IPV4:
 144                         if (!attr->ipv6)
 145                                 attr->ipv4 = 1;
 146                         if (item->mask != NULL &&
 147                             ((const struct rte_flow_item_ipv4 *)
 148                             item->mask)->hdr.next_proto_id)
 149                                 next_protocol =
 150                                     ((const struct rte_flow_item_ipv4 *)
 151                                       (item->spec))->hdr.next_proto_id &
 152                                     ((const struct rte_flow_item_ipv4 *)
 153                                       (item->mask))->hdr.next_proto_id;
 154                         if ((next_protocol == IPPROTO_IPIP ||
 155                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 156                                 attr->attr = 0;
 157                         break;
 158                 case RTE_FLOW_ITEM_TYPE_IPV6:
 159                         if (!attr->ipv4)
 160                                 attr->ipv6 = 1;
 161                         if (item->mask != NULL &&
 162                             ((const struct rte_flow_item_ipv6 *)
 163                             item->mask)->hdr.proto)
 164                                 next_protocol =
 165                                     ((const struct rte_flow_item_ipv6 *)
 166                                       (item->spec))->hdr.proto &
 167                                     ((const struct rte_flow_item_ipv6 *)
 168                                       (item->mask))->hdr.proto;
 169                         if ((next_protocol == IPPROTO_IPIP ||
 170                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 171                                 attr->attr = 0;
 172                         break;
 173                 case RTE_FLOW_ITEM_TYPE_UDP:
 174                         if (!attr->tcp)
 175                                 attr->udp = 1;
 176                         break;
 177                 case RTE_FLOW_ITEM_TYPE_TCP:
 178                         if (!attr->udp)
 179                                 attr->tcp = 1;
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         }
 185         attr->valid = 1;
 186 }
 187
 188 /**
 189  * Convert rte_mtr_color to mlx5 color.
 190  *
 191  * @param[in] rcol
 192  *   rte_mtr_color.
 193  *
 194  * @return
 195  *   mlx5 color.
 196  */
 197 static int
 198 rte_col_2_mlx5_col(enum rte_color rcol)
 199 {
 200         switch (rcol) {
 201         case RTE_COLOR_GREEN:
 202                 return MLX5_FLOW_COLOR_GREEN;
 203         case RTE_COLOR_YELLOW:
 204                 return MLX5_FLOW_COLOR_YELLOW;
 205         case RTE_COLOR_RED:
 206                 return MLX5_FLOW_COLOR_RED;
 207         default:
 208                 break;
 209         }
 210         return MLX5_FLOW_COLOR_UNDEFINED;
 211 }
 212
 213 struct field_modify_info {
 214         uint32_t size; /* Size of field in protocol header, in bytes. */
 215         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 216         enum mlx5_modification_field id;
 217 };
 218
 219 struct field_modify_info modify_eth[] = {
 220         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 221         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 222         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 223         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 224         {0, 0, 0},
 225 };
 226
 227 struct field_modify_info modify_vlan_out_first_vid[] = {
 228         /* Size in bits !!! */
 229         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 230         {0, 0, 0},
 231 };
 232
 233 struct field_modify_info modify_ipv4[] = {
 234         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 235         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 236         {4, 12, MLX5_MODI_OUT_SIPV4},
 237         {4, 16, MLX5_MODI_OUT_DIPV4},
 238         {0, 0, 0},
 239 };
 240
 241 struct field_modify_info modify_ipv6[] = {
 242         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 243         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 244         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 245         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 246         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 247         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 248         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 249         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 250         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 251         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 252         {0, 0, 0},
 253 };
 254
 255 struct field_modify_info modify_udp[] = {
 256         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 257         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 258         {0, 0, 0},
 259 };
 260
 261 struct field_modify_info modify_tcp[] = {
 262         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 263         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 264         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 265         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 266         {0, 0, 0},
 267 };
 268
 269 static void
 270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 271                           uint8_t next_protocol, uint64_t *item_flags,
 272                           int *tunnel)
 273 {
 274         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 275                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 276         if (next_protocol == IPPROTO_IPIP) {
 277                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 278                 *tunnel = 1;
 279         }
 280         if (next_protocol == IPPROTO_IPV6) {
 281                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 282                 *tunnel = 1;
 283         }
 284 }
 285
 286 /* Update VLAN's VID/PCP based on input rte_flow_action.
 287  *
 288  * @param[in] action
 289  *   Pointer to struct rte_flow_action.
 290  * @param[out] vlan
 291  *   Pointer to struct rte_vlan_hdr.
 292  */
 293 static void
 294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 295                          struct rte_vlan_hdr *vlan)
 296 {
 297         uint16_t vlan_tci;
 298         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 299                 vlan_tci =
 300                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 301                                                action->conf)->vlan_pcp;
 302                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 303                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 304                 vlan->vlan_tci |= vlan_tci;
 305         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 306                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 307                 vlan->vlan_tci |= rte_be_to_cpu_16
 308                     (((const struct rte_flow_action_of_set_vlan_vid *)
 309                                              action->conf)->vlan_vid);
 310         }
 311 }
 312
 313 /**
 314  * Fetch 1, 2, 3 or 4 byte field from the byte array
 315  * and return as unsigned integer in host-endian format.
 316  *
 317  * @param[in] data
 318  *   Pointer to data array.
 319  * @param[in] size
 320  *   Size of field to extract.
 321  *
 322  * @return
 323  *   converted field in host endian format.
 324  */
 325 static inline uint32_t
 326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 327 {
 328         uint32_t ret;
 329
 330         switch (size) {
 331         case 1:
 332                 ret = *data;
 333                 break;
 334         case 2:
 335                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 336                 break;
 337         case 3:
 338                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 339                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 340                 break;
 341         case 4:
 342                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 343                 break;
 344         default:
 345                 MLX5_ASSERT(false);
 346                 ret = 0;
 347                 break;
 348         }
 349         return ret;
 350 }
 351
 352 /**
 353  * Convert modify-header action to DV specification.
 354  *
 355  * Data length of each action is determined by provided field description
 356  * and the item mask. Data bit offset and width of each action is determined
 357  * by provided item mask.
 358  *
 359  * @param[in] item
 360  *   Pointer to item specification.
 361  * @param[in] field
 362  *   Pointer to field modification information.
 363  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 365  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 366  * @param[in] dcopy
 367  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 368  *   Negative offset value sets the same offset as source offset.
 369  *   size field is ignored, value is taken from source field.
 370  * @param[in,out] resource
 371  *   Pointer to the modify-header resource.
 372  * @param[in] type
 373  *   Type of modification.
 374  * @param[out] error
 375  *   Pointer to the error structure.
 376  *
 377  * @return
 378  *   0 on success, a negative errno value otherwise and rte_errno is set.
 379  */
 380 static int
 381 flow_dv_convert_modify_action(struct rte_flow_item *item,
 382                               struct field_modify_info *field,
 383                               struct field_modify_info *dcopy,
 384                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 385                               uint32_t type, struct rte_flow_error *error)
 386 {
 387         uint32_t i = resource->actions_num;
 388         struct mlx5_modification_cmd *actions = resource->actions;
 389
 390         /*
 391          * The item and mask are provided in big-endian format.
 392          * The fields should be presented as in big-endian format either.
 393          * Mask must be always present, it defines the actual field width.
 394          */
 395         MLX5_ASSERT(item->mask);
 396         MLX5_ASSERT(field->size);
 397         do {
 398                 unsigned int size_b;
 399                 unsigned int off_b;
 400                 uint32_t mask;
 401                 uint32_t data;
 402
 403                 if (i >= MLX5_MAX_MODIFY_NUM)
 404                         return rte_flow_error_set(error, EINVAL,
 405                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 406                                  "too many items to modify");
 407                 /* Fetch variable byte size mask from the array. */
 408                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 409                                            field->offset, field->size);
 410                 if (!mask) {
 411                         ++field;
 412                         continue;
 413                 }
 414                 /* Deduce actual data width in bits from mask value. */
 415                 off_b = rte_bsf32(mask);
 416                 size_b = sizeof(uint32_t) * CHAR_BIT -
 417                          off_b - __builtin_clz(mask);
 418                 MLX5_ASSERT(size_b);
 419                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 420                 actions[i] = (struct mlx5_modification_cmd) {
 421                         .action_type = type,
 422                         .field = field->id,
 423                         .offset = off_b,
 424                         .length = size_b,
 425                 };
 426                 /* Convert entire record to expected big-endian format. */
 427                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 428                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 429                         MLX5_ASSERT(dcopy);
 430                         actions[i].dst_field = dcopy->id;
 431                         actions[i].dst_offset =
 432                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 433                         /* Convert entire record to big-endian format. */
 434                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 435                         ++dcopy;
 436                 } else {
 437                         MLX5_ASSERT(item->spec);
 438                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 439                                                    field->offset, field->size);
 440                         /* Shift out the trailing masked bits from data. */
 441                         data = (data & mask) >> off_b;
 442                         actions[i].data1 = rte_cpu_to_be_32(data);
 443                 }
 444                 ++i;
 445                 ++field;
 446         } while (field->size);
 447         if (resource->actions_num == i)
 448                 return rte_flow_error_set(error, EINVAL,
 449                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 450                                           "invalid modification flow item");
 451         resource->actions_num = i;
 452         return 0;
 453 }
 454
 455 /**
 456  * Convert modify-header set IPv4 address action to DV specification.
 457  *
 458  * @param[in,out] resource
 459  *   Pointer to the modify-header resource.
 460  * @param[in] action
 461  *   Pointer to action specification.
 462  * @param[out] error
 463  *   Pointer to the error structure.
 464  *
 465  * @return
 466  *   0 on success, a negative errno value otherwise and rte_errno is set.
 467  */
 468 static int
 469 flow_dv_convert_action_modify_ipv4
 470                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 471                          const struct rte_flow_action *action,
 472                          struct rte_flow_error *error)
 473 {
 474         const struct rte_flow_action_set_ipv4 *conf =
 475                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 476         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 477         struct rte_flow_item_ipv4 ipv4;
 478         struct rte_flow_item_ipv4 ipv4_mask;
 479
 480         memset(&ipv4, 0, sizeof(ipv4));
 481         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 482         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 483                 ipv4.hdr.src_addr = conf->ipv4_addr;
 484                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 485         } else {
 486                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 487                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 488         }
 489         item.spec = &ipv4;
 490         item.mask = &ipv4_mask;
 491         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 492                                              MLX5_MODIFICATION_TYPE_SET, error);
 493 }
 494
 495 /**
 496  * Convert modify-header set IPv6 address action to DV specification.
 497  *
 498  * @param[in,out] resource
 499  *   Pointer to the modify-header resource.
 500  * @param[in] action
 501  *   Pointer to action specification.
 502  * @param[out] error
 503  *   Pointer to the error structure.
 504  *
 505  * @return
 506  *   0 on success, a negative errno value otherwise and rte_errno is set.
 507  */
 508 static int
 509 flow_dv_convert_action_modify_ipv6
 510                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 511                          const struct rte_flow_action *action,
 512                          struct rte_flow_error *error)
 513 {
 514         const struct rte_flow_action_set_ipv6 *conf =
 515                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 516         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 517         struct rte_flow_item_ipv6 ipv6;
 518         struct rte_flow_item_ipv6 ipv6_mask;
 519
 520         memset(&ipv6, 0, sizeof(ipv6));
 521         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 522         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 523                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.src_addr));
 525                 memcpy(&ipv6_mask.hdr.src_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 527                        sizeof(ipv6.hdr.src_addr));
 528         } else {
 529                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 530                        sizeof(ipv6.hdr.dst_addr));
 531                 memcpy(&ipv6_mask.hdr.dst_addr,
 532                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 533                        sizeof(ipv6.hdr.dst_addr));
 534         }
 535         item.spec = &ipv6;
 536         item.mask = &ipv6_mask;
 537         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 538                                              MLX5_MODIFICATION_TYPE_SET, error);
 539 }
 540
 541 /**
 542  * Convert modify-header set MAC address action to DV specification.
 543  *
 544  * @param[in,out] resource
 545  *   Pointer to the modify-header resource.
 546  * @param[in] action
 547  *   Pointer to action specification.
 548  * @param[out] error
 549  *   Pointer to the error structure.
 550  *
 551  * @return
 552  *   0 on success, a negative errno value otherwise and rte_errno is set.
 553  */
 554 static int
 555 flow_dv_convert_action_modify_mac
 556                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 557                          const struct rte_flow_action *action,
 558                          struct rte_flow_error *error)
 559 {
 560         const struct rte_flow_action_set_mac *conf =
 561                 (const struct rte_flow_action_set_mac *)(action->conf);
 562         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 563         struct rte_flow_item_eth eth;
 564         struct rte_flow_item_eth eth_mask;
 565
 566         memset(&eth, 0, sizeof(eth));
 567         memset(&eth_mask, 0, sizeof(eth_mask));
 568         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 569                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.src.addr_bytes));
 571                 memcpy(&eth_mask.src.addr_bytes,
 572                        &rte_flow_item_eth_mask.src.addr_bytes,
 573                        sizeof(eth_mask.src.addr_bytes));
 574         } else {
 575                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 576                        sizeof(eth.dst.addr_bytes));
 577                 memcpy(&eth_mask.dst.addr_bytes,
 578                        &rte_flow_item_eth_mask.dst.addr_bytes,
 579                        sizeof(eth_mask.dst.addr_bytes));
 580         }
 581         item.spec = &eth;
 582         item.mask = &eth_mask;
 583         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 584                                              MLX5_MODIFICATION_TYPE_SET, error);
 585 }
 586
 587 /**
 588  * Convert modify-header set VLAN VID action to DV specification.
 589  *
 590  * @param[in,out] resource
 591  *   Pointer to the modify-header resource.
 592  * @param[in] action
 593  *   Pointer to action specification.
 594  * @param[out] error
 595  *   Pointer to the error structure.
 596  *
 597  * @return
 598  *   0 on success, a negative errno value otherwise and rte_errno is set.
 599  */
 600 static int
 601 flow_dv_convert_action_modify_vlan_vid
 602                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 603                          const struct rte_flow_action *action,
 604                          struct rte_flow_error *error)
 605 {
 606         const struct rte_flow_action_of_set_vlan_vid *conf =
 607                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 608         int i = resource->actions_num;
 609         struct mlx5_modification_cmd *actions = resource->actions;
 610         struct field_modify_info *field = modify_vlan_out_first_vid;
 611
 612         if (i >= MLX5_MAX_MODIFY_NUM)
 613                 return rte_flow_error_set(error, EINVAL,
 614                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 615                          "too many items to modify");
 616         actions[i] = (struct mlx5_modification_cmd) {
 617                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 618                 .field = field->id,
 619                 .length = field->size,
 620                 .offset = field->offset,
 621         };
 622         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 623         actions[i].data1 = conf->vlan_vid;
 624         actions[i].data1 = actions[i].data1 << 16;
 625         resource->actions_num = ++i;
 626         return 0;
 627 }
 628
 629 /**
 630  * Convert modify-header set TP action to DV specification.
 631  *
 632  * @param[in,out] resource
 633  *   Pointer to the modify-header resource.
 634  * @param[in] action
 635  *   Pointer to action specification.
 636  * @param[in] items
 637  *   Pointer to rte_flow_item objects list.
 638  * @param[in] attr
 639  *   Pointer to flow attributes structure.
 640  * @param[in] dev_flow
 641  *   Pointer to the sub flow.
 642  * @param[in] tunnel_decap
 643  *   Whether action is after tunnel decapsulation.
 644  * @param[out] error
 645  *   Pointer to the error structure.
 646  *
 647  * @return
 648  *   0 on success, a negative errno value otherwise and rte_errno is set.
 649  */
 650 static int
 651 flow_dv_convert_action_modify_tp
 652                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 653                          const struct rte_flow_action *action,
 654                          const struct rte_flow_item *items,
 655                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 656                          bool tunnel_decap, struct rte_flow_error *error)
 657 {
 658         const struct rte_flow_action_set_tp *conf =
 659                 (const struct rte_flow_action_set_tp *)(action->conf);
 660         struct rte_flow_item item;
 661         struct rte_flow_item_udp udp;
 662         struct rte_flow_item_udp udp_mask;
 663         struct rte_flow_item_tcp tcp;
 664         struct rte_flow_item_tcp tcp_mask;
 665         struct field_modify_info *field;
 666
 667         if (!attr->valid)
 668                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 669         if (attr->udp) {
 670                 memset(&udp, 0, sizeof(udp));
 671                 memset(&udp_mask, 0, sizeof(udp_mask));
 672                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 673                         udp.hdr.src_port = conf->port;
 674                         udp_mask.hdr.src_port =
 675                                         rte_flow_item_udp_mask.hdr.src_port;
 676                 } else {
 677                         udp.hdr.dst_port = conf->port;
 678                         udp_mask.hdr.dst_port =
 679                                         rte_flow_item_udp_mask.hdr.dst_port;
 680                 }
 681                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 682                 item.spec = &udp;
 683                 item.mask = &udp_mask;
 684                 field = modify_udp;
 685         } else {
 686                 MLX5_ASSERT(attr->tcp);
 687                 memset(&tcp, 0, sizeof(tcp));
 688                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 689                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 690                         tcp.hdr.src_port = conf->port;
 691                         tcp_mask.hdr.src_port =
 692                                         rte_flow_item_tcp_mask.hdr.src_port;
 693                 } else {
 694                         tcp.hdr.dst_port = conf->port;
 695                         tcp_mask.hdr.dst_port =
 696                                         rte_flow_item_tcp_mask.hdr.dst_port;
 697                 }
 698                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 699                 item.spec = &tcp;
 700                 item.mask = &tcp_mask;
 701                 field = modify_tcp;
 702         }
 703         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 704                                              MLX5_MODIFICATION_TYPE_SET, error);
 705 }
 706
 707 /**
 708  * Convert modify-header set TTL action to DV specification.
 709  *
 710  * @param[in,out] resource
 711  *   Pointer to the modify-header resource.
 712  * @param[in] action
 713  *   Pointer to action specification.
 714  * @param[in] items
 715  *   Pointer to rte_flow_item objects list.
 716  * @param[in] attr
 717  *   Pointer to flow attributes structure.
 718  * @param[in] dev_flow
 719  *   Pointer to the sub flow.
 720  * @param[in] tunnel_decap
 721  *   Whether action is after tunnel decapsulation.
 722  * @param[out] error
 723  *   Pointer to the error structure.
 724  *
 725  * @return
 726  *   0 on success, a negative errno value otherwise and rte_errno is set.
 727  */
 728 static int
 729 flow_dv_convert_action_modify_ttl
 730                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 731                          const struct rte_flow_action *action,
 732                          const struct rte_flow_item *items,
 733                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 734                          bool tunnel_decap, struct rte_flow_error *error)
 735 {
 736         const struct rte_flow_action_set_ttl *conf =
 737                 (const struct rte_flow_action_set_ttl *)(action->conf);
 738         struct rte_flow_item item;
 739         struct rte_flow_item_ipv4 ipv4;
 740         struct rte_flow_item_ipv4 ipv4_mask;
 741         struct rte_flow_item_ipv6 ipv6;
 742         struct rte_flow_item_ipv6 ipv6_mask;
 743         struct field_modify_info *field;
 744
 745         if (!attr->valid)
 746                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 747         if (attr->ipv4) {
 748                 memset(&ipv4, 0, sizeof(ipv4));
 749                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 750                 ipv4.hdr.time_to_live = conf->ttl_value;
 751                 ipv4_mask.hdr.time_to_live = 0xFF;
 752                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 753                 item.spec = &ipv4;
 754                 item.mask = &ipv4_mask;
 755                 field = modify_ipv4;
 756         } else {
 757                 MLX5_ASSERT(attr->ipv6);
 758                 memset(&ipv6, 0, sizeof(ipv6));
 759                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 760                 ipv6.hdr.hop_limits = conf->ttl_value;
 761                 ipv6_mask.hdr.hop_limits = 0xFF;
 762                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 763                 item.spec = &ipv6;
 764                 item.mask = &ipv6_mask;
 765                 field = modify_ipv6;
 766         }
 767         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 768                                              MLX5_MODIFICATION_TYPE_SET, error);
 769 }
 770
 771 /**
 772  * Convert modify-header decrement TTL action to DV specification.
 773  *
 774  * @param[in,out] resource
 775  *   Pointer to the modify-header resource.
 776  * @param[in] action
 777  *   Pointer to action specification.
 778  * @param[in] items
 779  *   Pointer to rte_flow_item objects list.
 780  * @param[in] attr
 781  *   Pointer to flow attributes structure.
 782  * @param[in] dev_flow
 783  *   Pointer to the sub flow.
 784  * @param[in] tunnel_decap
 785  *   Whether action is after tunnel decapsulation.
 786  * @param[out] error
 787  *   Pointer to the error structure.
 788  *
 789  * @return
 790  *   0 on success, a negative errno value otherwise and rte_errno is set.
 791  */
 792 static int
 793 flow_dv_convert_action_modify_dec_ttl
 794                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 795                          const struct rte_flow_item *items,
 796                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 797                          bool tunnel_decap, struct rte_flow_error *error)
 798 {
 799         struct rte_flow_item item;
 800         struct rte_flow_item_ipv4 ipv4;
 801         struct rte_flow_item_ipv4 ipv4_mask;
 802         struct rte_flow_item_ipv6 ipv6;
 803         struct rte_flow_item_ipv6 ipv6_mask;
 804         struct field_modify_info *field;
 805
 806         if (!attr->valid)
 807                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 808         if (attr->ipv4) {
 809                 memset(&ipv4, 0, sizeof(ipv4));
 810                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 811                 ipv4.hdr.time_to_live = 0xFF;
 812                 ipv4_mask.hdr.time_to_live = 0xFF;
 813                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 814                 item.spec = &ipv4;
 815                 item.mask = &ipv4_mask;
 816                 field = modify_ipv4;
 817         } else {
 818                 MLX5_ASSERT(attr->ipv6);
 819                 memset(&ipv6, 0, sizeof(ipv6));
 820                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 821                 ipv6.hdr.hop_limits = 0xFF;
 822                 ipv6_mask.hdr.hop_limits = 0xFF;
 823                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 824                 item.spec = &ipv6;
 825                 item.mask = &ipv6_mask;
 826                 field = modify_ipv6;
 827         }
 828         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 829                                              MLX5_MODIFICATION_TYPE_ADD, error);
 830 }
 831
 832 /**
 833  * Convert modify-header increment/decrement TCP Sequence number
 834  * to DV specification.
 835  *
 836  * @param[in,out] resource
 837  *   Pointer to the modify-header resource.
 838  * @param[in] action
 839  *   Pointer to action specification.
 840  * @param[out] error
 841  *   Pointer to the error structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 static int
 847 flow_dv_convert_action_modify_tcp_seq
 848                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 849                          const struct rte_flow_action *action,
 850                          struct rte_flow_error *error)
 851 {
 852         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 853         uint64_t value = rte_be_to_cpu_32(*conf);
 854         struct rte_flow_item item;
 855         struct rte_flow_item_tcp tcp;
 856         struct rte_flow_item_tcp tcp_mask;
 857
 858         memset(&tcp, 0, sizeof(tcp));
 859         memset(&tcp_mask, 0, sizeof(tcp_mask));
 860         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 861                 /*
 862                  * The HW has no decrement operation, only increment operation.
 863                  * To simulate decrement X from Y using increment operation
 864                  * we need to add UINT32_MAX X times to Y.
 865                  * Each adding of UINT32_MAX decrements Y by 1.
 866                  */
 867                 value *= UINT32_MAX;
 868         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 869         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 870         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 871         item.spec = &tcp;
 872         item.mask = &tcp_mask;
 873         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 874                                              MLX5_MODIFICATION_TYPE_ADD, error);
 875 }
 876
 877 /**
 878  * Convert modify-header increment/decrement TCP Acknowledgment number
 879  * to DV specification.
 880  *
 881  * @param[in,out] resource
 882  *   Pointer to the modify-header resource.
 883  * @param[in] action
 884  *   Pointer to action specification.
 885  * @param[out] error
 886  *   Pointer to the error structure.
 887  *
 888  * @return
 889  *   0 on success, a negative errno value otherwise and rte_errno is set.
 890  */
 891 static int
 892 flow_dv_convert_action_modify_tcp_ack
 893                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 894                          const struct rte_flow_action *action,
 895                          struct rte_flow_error *error)
 896 {
 897         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 898         uint64_t value = rte_be_to_cpu_32(*conf);
 899         struct rte_flow_item item;
 900         struct rte_flow_item_tcp tcp;
 901         struct rte_flow_item_tcp tcp_mask;
 902
 903         memset(&tcp, 0, sizeof(tcp));
 904         memset(&tcp_mask, 0, sizeof(tcp_mask));
 905         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 906                 /*
 907                  * The HW has no decrement operation, only increment operation.
 908                  * To simulate decrement X from Y using increment operation
 909                  * we need to add UINT32_MAX X times to Y.
 910                  * Each adding of UINT32_MAX decrements Y by 1.
 911                  */
 912                 value *= UINT32_MAX;
 913         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 914         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 915         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 916         item.spec = &tcp;
 917         item.mask = &tcp_mask;
 918         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 919                                              MLX5_MODIFICATION_TYPE_ADD, error);
 920 }
 921
 922 static enum mlx5_modification_field reg_to_field[] = {
 923         [REG_NON] = MLX5_MODI_OUT_NONE,
 924         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 925         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 926         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 927         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 928         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 929         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 930         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 931         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 932         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 933         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 934 };
 935
 936 /**
 937  * Convert register set to DV specification.
 938  *
 939  * @param[in,out] resource
 940  *   Pointer to the modify-header resource.
 941  * @param[in] action
 942  *   Pointer to action specification.
 943  * @param[out] error
 944  *   Pointer to the error structure.
 945  *
 946  * @return
 947  *   0 on success, a negative errno value otherwise and rte_errno is set.
 948  */
 949 static int
 950 flow_dv_convert_action_set_reg
 951                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 952                          const struct rte_flow_action *action,
 953                          struct rte_flow_error *error)
 954 {
 955         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 956         struct mlx5_modification_cmd *actions = resource->actions;
 957         uint32_t i = resource->actions_num;
 958
 959         if (i >= MLX5_MAX_MODIFY_NUM)
 960                 return rte_flow_error_set(error, EINVAL,
 961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 962                                           "too many items to modify");
 963         MLX5_ASSERT(conf->id != REG_NON);
 964         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 965         actions[i] = (struct mlx5_modification_cmd) {
 966                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 967                 .field = reg_to_field[conf->id],
 968         };
 969         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 970         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 971         ++i;
 972         resource->actions_num = i;
 973         return 0;
 974 }
 975
 976 /**
 977  * Convert SET_TAG action to DV specification.
 978  *
 979  * @param[in] dev
 980  *   Pointer to the rte_eth_dev structure.
 981  * @param[in,out] resource
 982  *   Pointer to the modify-header resource.
 983  * @param[in] conf
 984  *   Pointer to action specification.
 985  * @param[out] error
 986  *   Pointer to the error structure.
 987  *
 988  * @return
 989  *   0 on success, a negative errno value otherwise and rte_errno is set.
 990  */
 991 static int
 992 flow_dv_convert_action_set_tag
 993                         (struct rte_eth_dev *dev,
 994                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 995                          const struct rte_flow_action_set_tag *conf,
 996                          struct rte_flow_error *error)
 997 {
 998         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 999         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1000         struct rte_flow_item item = {
1001                 .spec = &data,
1002                 .mask = &mask,
1003         };
1004         struct field_modify_info reg_c_x[] = {
1005                 [1] = {0, 0, 0},
1006         };
1007         enum mlx5_modification_field reg_type;
1008         int ret;
1009
1010         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1011         if (ret < 0)
1012                 return ret;
1013         MLX5_ASSERT(ret != REG_NON);
1014         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1015         reg_type = reg_to_field[ret];
1016         MLX5_ASSERT(reg_type > 0);
1017         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1018         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1019                                              MLX5_MODIFICATION_TYPE_SET, error);
1020 }
1021
1022 /**
1023  * Convert internal COPY_REG action to DV specification.
1024  *
1025  * @param[in] dev
1026  *   Pointer to the rte_eth_dev structure.
1027  * @param[in,out] res
1028  *   Pointer to the modify-header resource.
1029  * @param[in] action
1030  *   Pointer to action specification.
1031  * @param[out] error
1032  *   Pointer to the error structure.
1033  *
1034  * @return
1035  *   0 on success, a negative errno value otherwise and rte_errno is set.
1036  */
1037 static int
1038 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1039                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1040                                  const struct rte_flow_action *action,
1041                                  struct rte_flow_error *error)
1042 {
1043         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1044         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1045         struct rte_flow_item item = {
1046                 .spec = NULL,
1047                 .mask = &mask,
1048         };
1049         struct field_modify_info reg_src[] = {
1050                 {4, 0, reg_to_field[conf->src]},
1051                 {0, 0, 0},
1052         };
1053         struct field_modify_info reg_dst = {
1054                 .offset = 0,
1055                 .id = reg_to_field[conf->dst],
1056         };
1057         /* Adjust reg_c[0] usage according to reported mask. */
1058         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1059                 struct mlx5_priv *priv = dev->data->dev_private;
1060                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1061
1062                 MLX5_ASSERT(reg_c0);
1063                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1064                 if (conf->dst == REG_C_0) {
1065                         /* Copy to reg_c[0], within mask only. */
1066                         reg_dst.offset = rte_bsf32(reg_c0);
1067                         /*
1068                          * Mask is ignoring the enianness, because
1069                          * there is no conversion in datapath.
1070                          */
1071 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1072                         /* Copy from destination lower bits to reg_c[0]. */
1073                         mask = reg_c0 >> reg_dst.offset;
1074 #else
1075                         /* Copy from destination upper bits to reg_c[0]. */
1076                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1077                                           rte_fls_u32(reg_c0));
1078 #endif
1079                 } else {
1080                         mask = rte_cpu_to_be_32(reg_c0);
1081 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1082                         /* Copy from reg_c[0] to destination lower bits. */
1083                         reg_dst.offset = 0;
1084 #else
1085                         /* Copy from reg_c[0] to destination upper bits. */
1086                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1087                                          (rte_fls_u32(reg_c0) -
1088                                           rte_bsf32(reg_c0));
1089 #endif
1090                 }
1091         }
1092         return flow_dv_convert_modify_action(&item,
1093                                              reg_src, &reg_dst, res,
1094                                              MLX5_MODIFICATION_TYPE_COPY,
1095                                              error);
1096 }
1097
1098 /**
1099  * Convert MARK action to DV specification. This routine is used
1100  * in extensive metadata only and requires metadata register to be
1101  * handled. In legacy mode hardware tag resource is engaged.
1102  *
1103  * @param[in] dev
1104  *   Pointer to the rte_eth_dev structure.
1105  * @param[in] conf
1106  *   Pointer to MARK action specification.
1107  * @param[in,out] resource
1108  *   Pointer to the modify-header resource.
1109  * @param[out] error
1110  *   Pointer to the error structure.
1111  *
1112  * @return
1113  *   0 on success, a negative errno value otherwise and rte_errno is set.
1114  */
1115 static int
1116 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1117                             const struct rte_flow_action_mark *conf,
1118                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1119                             struct rte_flow_error *error)
1120 {
1121         struct mlx5_priv *priv = dev->data->dev_private;
1122         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1123                                            priv->sh->dv_mark_mask);
1124         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1125         struct rte_flow_item item = {
1126                 .spec = &data,
1127                 .mask = &mask,
1128         };
1129         struct field_modify_info reg_c_x[] = {
1130                 [1] = {0, 0, 0},
1131         };
1132         int reg;
1133
1134         if (!mask)
1135                 return rte_flow_error_set(error, EINVAL,
1136                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1137                                           NULL, "zero mark action mask");
1138         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1139         if (reg < 0)
1140                 return reg;
1141         MLX5_ASSERT(reg > 0);
1142         if (reg == REG_C_0) {
1143                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1144                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1145
1146                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1147                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1148                 mask = rte_cpu_to_be_32(mask << shl_c0);
1149         }
1150         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1151         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1152                                              MLX5_MODIFICATION_TYPE_SET, error);
1153 }
1154
1155 /**
1156  * Get metadata register index for specified steering domain.
1157  *
1158  * @param[in] dev
1159  *   Pointer to the rte_eth_dev structure.
1160  * @param[in] attr
1161  *   Attributes of flow to determine steering domain.
1162  * @param[out] error
1163  *   Pointer to the error structure.
1164  *
1165  * @return
1166  *   positive index on success, a negative errno value otherwise
1167  *   and rte_errno is set.
1168  */
1169 static enum modify_reg
1170 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1171                          const struct rte_flow_attr *attr,
1172                          struct rte_flow_error *error)
1173 {
1174         int reg =
1175                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1176                                           MLX5_METADATA_FDB :
1177                                             attr->egress ?
1178                                             MLX5_METADATA_TX :
1179                                             MLX5_METADATA_RX, 0, error);
1180         if (reg < 0)
1181                 return rte_flow_error_set(error,
1182                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1183                                           NULL, "unavailable "
1184                                           "metadata register");
1185         return reg;
1186 }
1187
1188 /**
1189  * Convert SET_META action to DV specification.
1190  *
1191  * @param[in] dev
1192  *   Pointer to the rte_eth_dev structure.
1193  * @param[in,out] resource
1194  *   Pointer to the modify-header resource.
1195  * @param[in] attr
1196  *   Attributes of flow that includes this item.
1197  * @param[in] conf
1198  *   Pointer to action specification.
1199  * @param[out] error
1200  *   Pointer to the error structure.
1201  *
1202  * @return
1203  *   0 on success, a negative errno value otherwise and rte_errno is set.
1204  */
1205 static int
1206 flow_dv_convert_action_set_meta
1207                         (struct rte_eth_dev *dev,
1208                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1209                          const struct rte_flow_attr *attr,
1210                          const struct rte_flow_action_set_meta *conf,
1211                          struct rte_flow_error *error)
1212 {
1213         uint32_t data = conf->data;
1214         uint32_t mask = conf->mask;
1215         struct rte_flow_item item = {
1216                 .spec = &data,
1217                 .mask = &mask,
1218         };
1219         struct field_modify_info reg_c_x[] = {
1220                 [1] = {0, 0, 0},
1221         };
1222         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1223
1224         if (reg < 0)
1225                 return reg;
1226         MLX5_ASSERT(reg != REG_NON);
1227         /*
1228          * In datapath code there is no endianness
1229          * coversions for perfromance reasons, all
1230          * pattern conversions are done in rte_flow.
1231          */
1232         if (reg == REG_C_0) {
1233                 struct mlx5_priv *priv = dev->data->dev_private;
1234                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1235                 uint32_t shl_c0;
1236
1237                 MLX5_ASSERT(msk_c0);
1238 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1239                 shl_c0 = rte_bsf32(msk_c0);
1240 #else
1241                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1242 #endif
1243                 mask <<= shl_c0;
1244                 data <<= shl_c0;
1245                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1246         }
1247         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1248         /* The routine expects parameters in memory as big-endian ones. */
1249         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1250                                              MLX5_MODIFICATION_TYPE_SET, error);
1251 }
1252
1253 /**
1254  * Convert modify-header set IPv4 DSCP action to DV specification.
1255  *
1256  * @param[in,out] resource
1257  *   Pointer to the modify-header resource.
1258  * @param[in] action
1259  *   Pointer to action specification.
1260  * @param[out] error
1261  *   Pointer to the error structure.
1262  *
1263  * @return
1264  *   0 on success, a negative errno value otherwise and rte_errno is set.
1265  */
1266 static int
1267 flow_dv_convert_action_modify_ipv4_dscp
1268                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1269                          const struct rte_flow_action *action,
1270                          struct rte_flow_error *error)
1271 {
1272         const struct rte_flow_action_set_dscp *conf =
1273                 (const struct rte_flow_action_set_dscp *)(action->conf);
1274         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1275         struct rte_flow_item_ipv4 ipv4;
1276         struct rte_flow_item_ipv4 ipv4_mask;
1277
1278         memset(&ipv4, 0, sizeof(ipv4));
1279         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1280         ipv4.hdr.type_of_service = conf->dscp;
1281         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1282         item.spec = &ipv4;
1283         item.mask = &ipv4_mask;
1284         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1285                                              MLX5_MODIFICATION_TYPE_SET, error);
1286 }
1287
1288 /**
1289  * Convert modify-header set IPv6 DSCP action to DV specification.
1290  *
1291  * @param[in,out] resource
1292  *   Pointer to the modify-header resource.
1293  * @param[in] action
1294  *   Pointer to action specification.
1295  * @param[out] error
1296  *   Pointer to the error structure.
1297  *
1298  * @return
1299  *   0 on success, a negative errno value otherwise and rte_errno is set.
1300  */
1301 static int
1302 flow_dv_convert_action_modify_ipv6_dscp
1303                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1304                          const struct rte_flow_action *action,
1305                          struct rte_flow_error *error)
1306 {
1307         const struct rte_flow_action_set_dscp *conf =
1308                 (const struct rte_flow_action_set_dscp *)(action->conf);
1309         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1310         struct rte_flow_item_ipv6 ipv6;
1311         struct rte_flow_item_ipv6 ipv6_mask;
1312
1313         memset(&ipv6, 0, sizeof(ipv6));
1314         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1315         /*
1316          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1317          * rdma-core only accept the DSCP bits byte aligned start from
1318          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1319          * bits in IPv6 case as rdma-core requires byte aligned value.
1320          */
1321         ipv6.hdr.vtc_flow = conf->dscp;
1322         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1323         item.spec = &ipv6;
1324         item.mask = &ipv6_mask;
1325         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1326                                              MLX5_MODIFICATION_TYPE_SET, error);
1327 }
1328
1329 static int
1330 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1331 {
1332         switch (field) {
1333         case RTE_FLOW_FIELD_START:
1334                 return 32;
1335         case RTE_FLOW_FIELD_MAC_DST:
1336         case RTE_FLOW_FIELD_MAC_SRC:
1337                 return 48;
1338         case RTE_FLOW_FIELD_VLAN_TYPE:
1339                 return 16;
1340         case RTE_FLOW_FIELD_VLAN_ID:
1341                 return 12;
1342         case RTE_FLOW_FIELD_MAC_TYPE:
1343                 return 16;
1344         case RTE_FLOW_FIELD_IPV4_DSCP:
1345                 return 6;
1346         case RTE_FLOW_FIELD_IPV4_TTL:
1347                 return 8;
1348         case RTE_FLOW_FIELD_IPV4_SRC:
1349         case RTE_FLOW_FIELD_IPV4_DST:
1350                 return 32;
1351         case RTE_FLOW_FIELD_IPV6_DSCP:
1352                 return 6;
1353         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1354                 return 8;
1355         case RTE_FLOW_FIELD_IPV6_SRC:
1356         case RTE_FLOW_FIELD_IPV6_DST:
1357                 return 128;
1358         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1359         case RTE_FLOW_FIELD_TCP_PORT_DST:
1360                 return 16;
1361         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1362         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1363                 return 32;
1364         case RTE_FLOW_FIELD_TCP_FLAGS:
1365                 return 6;
1366         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1367         case RTE_FLOW_FIELD_UDP_PORT_DST:
1368                 return 16;
1369         case RTE_FLOW_FIELD_VXLAN_VNI:
1370         case RTE_FLOW_FIELD_GENEVE_VNI:
1371                 return 24;
1372         case RTE_FLOW_FIELD_GTP_TEID:
1373         case RTE_FLOW_FIELD_TAG:
1374                 return 32;
1375         case RTE_FLOW_FIELD_MARK:
1376                 return 24;
1377         case RTE_FLOW_FIELD_META:
1378                 return 32;
1379         case RTE_FLOW_FIELD_POINTER:
1380         case RTE_FLOW_FIELD_VALUE:
1381                 return 64;
1382         default:
1383                 MLX5_ASSERT(false);
1384         }
1385         return 0;
1386 }
1387
1388 static void
1389 mlx5_flow_field_id_to_modify_info
1390                 (const struct rte_flow_action_modify_data *data,
1391                  struct field_modify_info *info,
1392                  uint32_t *mask, uint32_t *value,
1393                  uint32_t width, uint32_t dst_width,
1394                  struct rte_eth_dev *dev,
1395                  const struct rte_flow_attr *attr,
1396                  struct rte_flow_error *error)
1397 {
1398         uint32_t idx = 0;
1399         uint64_t val = 0;
1400         switch (data->field) {
1401         case RTE_FLOW_FIELD_START:
1402                 /* not supported yet */
1403                 MLX5_ASSERT(false);
1404                 break;
1405         case RTE_FLOW_FIELD_MAC_DST:
1406                 if (mask) {
1407                         if (data->offset < 32) {
1408                                 info[idx] = (struct field_modify_info){4, 0,
1409                                                 MLX5_MODI_OUT_DMAC_47_16};
1410                                 if (width < 32) {
1411                                         mask[idx] =
1412                                                 rte_cpu_to_be_32(0xffffffff >>
1413                                                                  (32 - width));
1414                                         width = 0;
1415                                 } else {
1416                                         mask[idx] = RTE_BE32(0xffffffff);
1417                                         width -= 32;
1418                                 }
1419                                 if (!width)
1420                                         break;
1421                                 ++idx;
1422                         }
1423                         info[idx] = (struct field_modify_info){2, 4 * idx,
1424                                                 MLX5_MODI_OUT_DMAC_15_0};
1425                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1426                 } else {
1427                         if (data->offset < 32)
1428                                 info[idx++] = (struct field_modify_info){4, 0,
1429                                                 MLX5_MODI_OUT_DMAC_47_16};
1430                         info[idx] = (struct field_modify_info){2, 0,
1431                                                 MLX5_MODI_OUT_DMAC_15_0};
1432                 }
1433                 break;
1434         case RTE_FLOW_FIELD_MAC_SRC:
1435                 if (mask) {
1436                         if (data->offset < 32) {
1437                                 info[idx] = (struct field_modify_info){4, 0,
1438                                                 MLX5_MODI_OUT_SMAC_47_16};
1439                                 if (width < 32) {
1440                                         mask[idx] =
1441                                                 rte_cpu_to_be_32(0xffffffff >>
1442                                                                 (32 - width));
1443                                         width = 0;
1444                                 } else {
1445                                         mask[idx] = RTE_BE32(0xffffffff);
1446                                         width -= 32;
1447                                 }
1448                                 if (!width)
1449                                         break;
1450                                 ++idx;
1451                         }
1452                         info[idx] = (struct field_modify_info){2, 4 * idx,
1453                                                 MLX5_MODI_OUT_SMAC_15_0};
1454                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1455                 } else {
1456                         if (data->offset < 32)
1457                                 info[idx++] = (struct field_modify_info){4, 0,
1458                                                 MLX5_MODI_OUT_SMAC_47_16};
1459                         info[idx] = (struct field_modify_info){2, 0,
1460                                                 MLX5_MODI_OUT_SMAC_15_0};
1461                 }
1462                 break;
1463         case RTE_FLOW_FIELD_VLAN_TYPE:
1464                 /* not supported yet */
1465                 break;
1466         case RTE_FLOW_FIELD_VLAN_ID:
1467                 info[idx] = (struct field_modify_info){2, 0,
1468                                         MLX5_MODI_OUT_FIRST_VID};
1469                 if (mask)
1470                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1471                 break;
1472         case RTE_FLOW_FIELD_MAC_TYPE:
1473                 info[idx] = (struct field_modify_info){2, 0,
1474                                         MLX5_MODI_OUT_ETHERTYPE};
1475                 if (mask)
1476                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1477                 break;
1478         case RTE_FLOW_FIELD_IPV4_DSCP:
1479                 info[idx] = (struct field_modify_info){1, 0,
1480                                         MLX5_MODI_OUT_IP_DSCP};
1481                 if (mask)
1482                         mask[idx] = 0x3f >> (6 - width);
1483                 break;
1484         case RTE_FLOW_FIELD_IPV4_TTL:
1485                 info[idx] = (struct field_modify_info){1, 0,
1486                                         MLX5_MODI_OUT_IPV4_TTL};
1487                 if (mask)
1488                         mask[idx] = 0xff >> (8 - width);
1489                 break;
1490         case RTE_FLOW_FIELD_IPV4_SRC:
1491                 info[idx] = (struct field_modify_info){4, 0,
1492                                         MLX5_MODI_OUT_SIPV4};
1493                 if (mask)
1494                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1495                                                      (32 - width));
1496                 break;
1497         case RTE_FLOW_FIELD_IPV4_DST:
1498                 info[idx] = (struct field_modify_info){4, 0,
1499                                         MLX5_MODI_OUT_DIPV4};
1500                 if (mask)
1501                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1502                                                      (32 - width));
1503                 break;
1504         case RTE_FLOW_FIELD_IPV6_DSCP:
1505                 info[idx] = (struct field_modify_info){1, 0,
1506                                         MLX5_MODI_OUT_IP_DSCP};
1507                 if (mask)
1508                         mask[idx] = 0x3f >> (6 - width);
1509                 break;
1510         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1511                 info[idx] = (struct field_modify_info){1, 0,
1512                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1513                 if (mask)
1514                         mask[idx] = 0xff >> (8 - width);
1515                 break;
1516         case RTE_FLOW_FIELD_IPV6_SRC:
1517                 if (mask) {
1518                         if (data->offset < 32) {
1519                                 info[idx] = (struct field_modify_info){4,
1520                                                 4 * idx,
1521                                                 MLX5_MODI_OUT_SIPV6_31_0};
1522                                 if (width < 32) {
1523                                         mask[idx] =
1524                                                 rte_cpu_to_be_32(0xffffffff >>
1525                                                                  (32 - width));
1526                                         width = 0;
1527                                 } else {
1528                                         mask[idx] = RTE_BE32(0xffffffff);
1529                                         width -= 32;
1530                                 }
1531                                 if (!width)
1532                                         break;
1533                                 ++idx;
1534                         }
1535                         if (data->offset < 64) {
1536                                 info[idx] = (struct field_modify_info){4,
1537                                                 4 * idx,
1538                                                 MLX5_MODI_OUT_SIPV6_63_32};
1539                                 if (width < 32) {
1540                                         mask[idx] =
1541                                                 rte_cpu_to_be_32(0xffffffff >>
1542                                                                  (32 - width));
1543                                         width = 0;
1544                                 } else {
1545                                         mask[idx] = RTE_BE32(0xffffffff);
1546                                         width -= 32;
1547                                 }
1548                                 if (!width)
1549                                         break;
1550                                 ++idx;
1551                         }
1552                         if (data->offset < 96) {
1553                                 info[idx] = (struct field_modify_info){4,
1554                                                 4 * idx,
1555                                                 MLX5_MODI_OUT_SIPV6_95_64};
1556                                 if (width < 32) {
1557                                         mask[idx] =
1558                                                 rte_cpu_to_be_32(0xffffffff >>
1559                                                                  (32 - width));
1560                                         width = 0;
1561                                 } else {
1562                                         mask[idx] = RTE_BE32(0xffffffff);
1563                                         width -= 32;
1564                                 }
1565                                 if (!width)
1566                                         break;
1567                                 ++idx;
1568                         }
1569                         info[idx] = (struct field_modify_info){4, 4 * idx,
1570                                                 MLX5_MODI_OUT_SIPV6_127_96};
1571                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1572                                                      (32 - width));
1573                 } else {
1574                         if (data->offset < 32)
1575                                 info[idx++] = (struct field_modify_info){4, 0,
1576                                                 MLX5_MODI_OUT_SIPV6_31_0};
1577                         if (data->offset < 64)
1578                                 info[idx++] = (struct field_modify_info){4, 0,
1579                                                 MLX5_MODI_OUT_SIPV6_63_32};
1580                         if (data->offset < 96)
1581                                 info[idx++] = (struct field_modify_info){4, 0,
1582                                                 MLX5_MODI_OUT_SIPV6_95_64};
1583                         if (data->offset < 128)
1584                                 info[idx++] = (struct field_modify_info){4, 0,
1585                                                 MLX5_MODI_OUT_SIPV6_127_96};
1586                 }
1587                 break;
1588         case RTE_FLOW_FIELD_IPV6_DST:
1589                 if (mask) {
1590                         if (data->offset < 32) {
1591                                 info[idx] = (struct field_modify_info){4,
1592                                                 4 * idx,
1593                                                 MLX5_MODI_OUT_DIPV6_31_0};
1594                                 if (width < 32) {
1595                                         mask[idx] =
1596                                                 rte_cpu_to_be_32(0xffffffff >>
1597                                                                  (32 - width));
1598                                         width = 0;
1599                                 } else {
1600                                         mask[idx] = RTE_BE32(0xffffffff);
1601                                         width -= 32;
1602                                 }
1603                                 if (!width)
1604                                         break;
1605                                 ++idx;
1606                         }
1607                         if (data->offset < 64) {
1608                                 info[idx] = (struct field_modify_info){4,
1609                                                 4 * idx,
1610                                                 MLX5_MODI_OUT_DIPV6_63_32};
1611                                 if (width < 32) {
1612                                         mask[idx] =
1613                                                 rte_cpu_to_be_32(0xffffffff >>
1614                                                                  (32 - width));
1615                                         width = 0;
1616                                 } else {
1617                                         mask[idx] = RTE_BE32(0xffffffff);
1618                                         width -= 32;
1619                                 }
1620                                 if (!width)
1621                                         break;
1622                                 ++idx;
1623                         }
1624                         if (data->offset < 96) {
1625                                 info[idx] = (struct field_modify_info){4,
1626                                                 4 * idx,
1627                                                 MLX5_MODI_OUT_DIPV6_95_64};
1628                                 if (width < 32) {
1629                                         mask[idx] =
1630                                                 rte_cpu_to_be_32(0xffffffff >>
1631                                                                  (32 - width));
1632                                         width = 0;
1633                                 } else {
1634                                         mask[idx] = RTE_BE32(0xffffffff);
1635                                         width -= 32;
1636                                 }
1637                                 if (!width)
1638                                         break;
1639                                 ++idx;
1640                         }
1641                         info[idx] = (struct field_modify_info){4, 4 * idx,
1642                                                 MLX5_MODI_OUT_DIPV6_127_96};
1643                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1644                                                      (32 - width));
1645                 } else {
1646                         if (data->offset < 32)
1647                                 info[idx++] = (struct field_modify_info){4, 0,
1648                                                 MLX5_MODI_OUT_DIPV6_31_0};
1649                         if (data->offset < 64)
1650                                 info[idx++] = (struct field_modify_info){4, 0,
1651                                                 MLX5_MODI_OUT_DIPV6_63_32};
1652                         if (data->offset < 96)
1653                                 info[idx++] = (struct field_modify_info){4, 0,
1654                                                 MLX5_MODI_OUT_DIPV6_95_64};
1655                         if (data->offset < 128)
1656                                 info[idx++] = (struct field_modify_info){4, 0,
1657                                                 MLX5_MODI_OUT_DIPV6_127_96};
1658                 }
1659                 break;
1660         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1661                 info[idx] = (struct field_modify_info){2, 0,
1662                                         MLX5_MODI_OUT_TCP_SPORT};
1663                 if (mask)
1664                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1665                 break;
1666         case RTE_FLOW_FIELD_TCP_PORT_DST:
1667                 info[idx] = (struct field_modify_info){2, 0,
1668                                         MLX5_MODI_OUT_TCP_DPORT};
1669                 if (mask)
1670                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1671                 break;
1672         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1673                 info[idx] = (struct field_modify_info){4, 0,
1674                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1675                 if (mask)
1676                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1677                                                      (32 - width));
1678                 break;
1679         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1680                 info[idx] = (struct field_modify_info){4, 0,
1681                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1682                 if (mask)
1683                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1684                                                      (32 - width));
1685                 break;
1686         case RTE_FLOW_FIELD_TCP_FLAGS:
1687                 info[idx] = (struct field_modify_info){1, 0,
1688                                         MLX5_MODI_OUT_TCP_FLAGS};
1689                 if (mask)
1690                         mask[idx] = 0x3f >> (6 - width);
1691                 break;
1692         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1693                 info[idx] = (struct field_modify_info){2, 0,
1694                                         MLX5_MODI_OUT_UDP_SPORT};
1695                 if (mask)
1696                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1697                 break;
1698         case RTE_FLOW_FIELD_UDP_PORT_DST:
1699                 info[idx] = (struct field_modify_info){2, 0,
1700                                         MLX5_MODI_OUT_UDP_DPORT};
1701                 if (mask)
1702                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1703                 break;
1704         case RTE_FLOW_FIELD_VXLAN_VNI:
1705                 /* not supported yet */
1706                 break;
1707         case RTE_FLOW_FIELD_GENEVE_VNI:
1708                 /* not supported yet*/
1709                 break;
1710         case RTE_FLOW_FIELD_GTP_TEID:
1711                 info[idx] = (struct field_modify_info){4, 0,
1712                                         MLX5_MODI_GTP_TEID};
1713                 if (mask)
1714                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1715                                                      (32 - width));
1716                 break;
1717         case RTE_FLOW_FIELD_TAG:
1718                 {
1719                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1720                                                    data->level, error);
1721                         if (reg < 0)
1722                                 return;
1723                         MLX5_ASSERT(reg != REG_NON);
1724                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1725                         info[idx] = (struct field_modify_info){4, 0,
1726                                                 reg_to_field[reg]};
1727                         if (mask)
1728                                 mask[idx] =
1729                                         rte_cpu_to_be_32(0xffffffff >>
1730                                                          (32 - width));
1731                 }
1732                 break;
1733         case RTE_FLOW_FIELD_MARK:
1734                 {
1735                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1736                                                        0, error);
1737                         if (reg < 0)
1738                                 return;
1739                         MLX5_ASSERT(reg != REG_NON);
1740                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1741                         info[idx] = (struct field_modify_info){4, 0,
1742                                                 reg_to_field[reg]};
1743                         if (mask)
1744                                 mask[idx] =
1745                                         rte_cpu_to_be_32(0xffffffff >>
1746                                                          (32 - width));
1747                 }
1748                 break;
1749         case RTE_FLOW_FIELD_META:
1750                 {
1751                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1752                         if (reg < 0)
1753                                 return;
1754                         MLX5_ASSERT(reg != REG_NON);
1755                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1756                         info[idx] = (struct field_modify_info){4, 0,
1757                                                 reg_to_field[reg]};
1758                         if (mask)
1759                                 mask[idx] =
1760                                         rte_cpu_to_be_32(0xffffffff >>
1761                                                          (32 - width));
1762                 }
1763                 break;
1764         case RTE_FLOW_FIELD_POINTER:
1765         case RTE_FLOW_FIELD_VALUE:
1766                 if (data->field == RTE_FLOW_FIELD_POINTER)
1767                         memcpy(&val, (void *)(uintptr_t)data->value,
1768                                sizeof(uint64_t));
1769                 else
1770                         val = data->value;
1771                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1772                         if (mask[idx]) {
1773                                 if (dst_width > 16) {
1774                                         value[idx] = rte_cpu_to_be_32(val);
1775                                         val >>= 32;
1776                                 } else if (dst_width > 8) {
1777                                         value[idx] = rte_cpu_to_be_16(val);
1778                                         val >>= 16;
1779                                 } else {
1780                                         value[idx] = (uint8_t)val;
1781                                         val >>= 8;
1782                                 }
1783                                 if (!val)
1784                                         break;
1785                         }
1786                 }
1787                 break;
1788         default:
1789                 MLX5_ASSERT(false);
1790                 break;
1791         }
1792 }
1793
1794 /**
1795  * Convert modify_field action to DV specification.
1796  *
1797  * @param[in] dev
1798  *   Pointer to the rte_eth_dev structure.
1799  * @param[in,out] resource
1800  *   Pointer to the modify-header resource.
1801  * @param[in] action
1802  *   Pointer to action specification.
1803  * @param[in] attr
1804  *   Attributes of flow that includes this item.
1805  * @param[out] error
1806  *   Pointer to the error structure.
1807  *
1808  * @return
1809  *   0 on success, a negative errno value otherwise and rte_errno is set.
1810  */
1811 static int
1812 flow_dv_convert_action_modify_field
1813                         (struct rte_eth_dev *dev,
1814                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1815                          const struct rte_flow_action *action,
1816                          const struct rte_flow_attr *attr,
1817                          struct rte_flow_error *error)
1818 {
1819         const struct rte_flow_action_modify_field *conf =
1820                 (const struct rte_flow_action_modify_field *)(action->conf);
1821         struct rte_flow_item item;
1822         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1823                                                                 {0, 0, 0} };
1824         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1825                                                                 {0, 0, 0} };
1826         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1827         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1828         uint32_t type;
1829         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1830
1831         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1832                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1833                 type = MLX5_MODIFICATION_TYPE_SET;
1834                 /** For SET fill the destination field (field) first. */
1835                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1836                         value, conf->width, dst_width, dev, attr, error);
1837                 /** Then copy immediate value from source as per mask. */
1838                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1839                         value, conf->width, dst_width, dev, attr, error);
1840                 item.spec = &value;
1841         } else {
1842                 type = MLX5_MODIFICATION_TYPE_COPY;
1843                 /** For COPY fill the destination field (dcopy) without mask. */
1844                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1845                         value, conf->width, dst_width, dev, attr, error);
1846                 /** Then construct the source field (field) with mask. */
1847                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1848                         value, conf->width, dst_width, dev, attr, error);
1849         }
1850         item.mask = &mask;
1851         return flow_dv_convert_modify_action(&item,
1852                         field, dcopy, resource, type, error);
1853 }
1854
1855 /**
1856  * Validate MARK item.
1857  *
1858  * @param[in] dev
1859  *   Pointer to the rte_eth_dev structure.
1860  * @param[in] item
1861  *   Item specification.
1862  * @param[in] attr
1863  *   Attributes of flow that includes this item.
1864  * @param[out] error
1865  *   Pointer to error structure.
1866  *
1867  * @return
1868  *   0 on success, a negative errno value otherwise and rte_errno is set.
1869  */
1870 static int
1871 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1872                            const struct rte_flow_item *item,
1873                            const struct rte_flow_attr *attr __rte_unused,
1874                            struct rte_flow_error *error)
1875 {
1876         struct mlx5_priv *priv = dev->data->dev_private;
1877         struct mlx5_dev_config *config = &priv->config;
1878         const struct rte_flow_item_mark *spec = item->spec;
1879         const struct rte_flow_item_mark *mask = item->mask;
1880         const struct rte_flow_item_mark nic_mask = {
1881                 .id = priv->sh->dv_mark_mask,
1882         };
1883         int ret;
1884
1885         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1886                 return rte_flow_error_set(error, ENOTSUP,
1887                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1888                                           "extended metadata feature"
1889                                           " isn't enabled");
1890         if (!mlx5_flow_ext_mreg_supported(dev))
1891                 return rte_flow_error_set(error, ENOTSUP,
1892                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1893                                           "extended metadata register"
1894                                           " isn't supported");
1895         if (!nic_mask.id)
1896                 return rte_flow_error_set(error, ENOTSUP,
1897                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1898                                           "extended metadata register"
1899                                           " isn't available");
1900         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1901         if (ret < 0)
1902                 return ret;
1903         if (!spec)
1904                 return rte_flow_error_set(error, EINVAL,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1906                                           item->spec,
1907                                           "data cannot be empty");
1908         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1909                 return rte_flow_error_set(error, EINVAL,
1910                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1911                                           &spec->id,
1912                                           "mark id exceeds the limit");
1913         if (!mask)
1914                 mask = &nic_mask;
1915         if (!mask->id)
1916                 return rte_flow_error_set(error, EINVAL,
1917                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1918                                         "mask cannot be zero");
1919
1920         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1921                                         (const uint8_t *)&nic_mask,
1922                                         sizeof(struct rte_flow_item_mark),
1923                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1924         if (ret < 0)
1925                 return ret;
1926         return 0;
1927 }
1928
1929 /**
1930  * Validate META item.
1931  *
1932  * @param[in] dev
1933  *   Pointer to the rte_eth_dev structure.
1934  * @param[in] item
1935  *   Item specification.
1936  * @param[in] attr
1937  *   Attributes of flow that includes this item.
1938  * @param[out] error
1939  *   Pointer to error structure.
1940  *
1941  * @return
1942  *   0 on success, a negative errno value otherwise and rte_errno is set.
1943  */
1944 static int
1945 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1946                            const struct rte_flow_item *item,
1947                            const struct rte_flow_attr *attr,
1948                            struct rte_flow_error *error)
1949 {
1950         struct mlx5_priv *priv = dev->data->dev_private;
1951         struct mlx5_dev_config *config = &priv->config;
1952         const struct rte_flow_item_meta *spec = item->spec;
1953         const struct rte_flow_item_meta *mask = item->mask;
1954         struct rte_flow_item_meta nic_mask = {
1955                 .data = UINT32_MAX
1956         };
1957         int reg;
1958         int ret;
1959
1960         if (!spec)
1961                 return rte_flow_error_set(error, EINVAL,
1962                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1963                                           item->spec,
1964                                           "data cannot be empty");
1965         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1966                 if (!mlx5_flow_ext_mreg_supported(dev))
1967                         return rte_flow_error_set(error, ENOTSUP,
1968                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1969                                           "extended metadata register"
1970                                           " isn't supported");
1971                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1972                 if (reg < 0)
1973                         return reg;
1974                 if (reg == REG_NON)
1975                         return rte_flow_error_set(error, ENOTSUP,
1976                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1977                                         "unavalable extended metadata register");
1978                 if (reg == REG_B)
1979                         return rte_flow_error_set(error, ENOTSUP,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "match on reg_b "
1982                                           "isn't supported");
1983                 if (reg != REG_A)
1984                         nic_mask.data = priv->sh->dv_meta_mask;
1985         } else {
1986                 if (attr->transfer)
1987                         return rte_flow_error_set(error, ENOTSUP,
1988                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1989                                         "extended metadata feature "
1990                                         "should be enabled when "
1991                                         "meta item is requested "
1992                                         "with e-switch mode ");
1993                 if (attr->ingress)
1994                         return rte_flow_error_set(error, ENOTSUP,
1995                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1996                                         "match on metadata for ingress "
1997                                         "is not supported in legacy "
1998                                         "metadata mode");
1999         }
2000         if (!mask)
2001                 mask = &rte_flow_item_meta_mask;
2002         if (!mask->data)
2003                 return rte_flow_error_set(error, EINVAL,
2004                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2005                                         "mask cannot be zero");
2006
2007         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2008                                         (const uint8_t *)&nic_mask,
2009                                         sizeof(struct rte_flow_item_meta),
2010                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2011         return ret;
2012 }
2013
2014 /**
2015  * Validate TAG item.
2016  *
2017  * @param[in] dev
2018  *   Pointer to the rte_eth_dev structure.
2019  * @param[in] item
2020  *   Item specification.
2021  * @param[in] attr
2022  *   Attributes of flow that includes this item.
2023  * @param[out] error
2024  *   Pointer to error structure.
2025  *
2026  * @return
2027  *   0 on success, a negative errno value otherwise and rte_errno is set.
2028  */
2029 static int
2030 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2031                           const struct rte_flow_item *item,
2032                           const struct rte_flow_attr *attr __rte_unused,
2033                           struct rte_flow_error *error)
2034 {
2035         const struct rte_flow_item_tag *spec = item->spec;
2036         const struct rte_flow_item_tag *mask = item->mask;
2037         const struct rte_flow_item_tag nic_mask = {
2038                 .data = RTE_BE32(UINT32_MAX),
2039                 .index = 0xff,
2040         };
2041         int ret;
2042
2043         if (!mlx5_flow_ext_mreg_supported(dev))
2044                 return rte_flow_error_set(error, ENOTSUP,
2045                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2046                                           "extensive metadata register"
2047                                           " isn't supported");
2048         if (!spec)
2049                 return rte_flow_error_set(error, EINVAL,
2050                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2051                                           item->spec,
2052                                           "data cannot be empty");
2053         if (!mask)
2054                 mask = &rte_flow_item_tag_mask;
2055         if (!mask->data)
2056                 return rte_flow_error_set(error, EINVAL,
2057                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2058                                         "mask cannot be zero");
2059
2060         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2061                                         (const uint8_t *)&nic_mask,
2062                                         sizeof(struct rte_flow_item_tag),
2063                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2064         if (ret < 0)
2065                 return ret;
2066         if (mask->index != 0xff)
2067                 return rte_flow_error_set(error, EINVAL,
2068                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2069                                           "partial mask for tag index"
2070                                           " is not supported");
2071         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2072         if (ret < 0)
2073                 return ret;
2074         MLX5_ASSERT(ret != REG_NON);
2075         return 0;
2076 }
2077
2078 /**
2079  * Validate vport item.
2080  *
2081  * @param[in] dev
2082  *   Pointer to the rte_eth_dev structure.
2083  * @param[in] item
2084  *   Item specification.
2085  * @param[in] attr
2086  *   Attributes of flow that includes this item.
2087  * @param[in] item_flags
2088  *   Bit-fields that holds the items detected until now.
2089  * @param[out] error
2090  *   Pointer to error structure.
2091  *
2092  * @return
2093  *   0 on success, a negative errno value otherwise and rte_errno is set.
2094  */
2095 static int
2096 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2097                               const struct rte_flow_item *item,
2098                               const struct rte_flow_attr *attr,
2099                               uint64_t item_flags,
2100                               struct rte_flow_error *error)
2101 {
2102         const struct rte_flow_item_port_id *spec = item->spec;
2103         const struct rte_flow_item_port_id *mask = item->mask;
2104         const struct rte_flow_item_port_id switch_mask = {
2105                         .id = 0xffffffff,
2106         };
2107         struct mlx5_priv *esw_priv;
2108         struct mlx5_priv *dev_priv;
2109         int ret;
2110
2111         if (!attr->transfer)
2112                 return rte_flow_error_set(error, EINVAL,
2113                                           RTE_FLOW_ERROR_TYPE_ITEM,
2114                                           NULL,
2115                                           "match on port id is valid only"
2116                                           " when transfer flag is enabled");
2117         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2118                 return rte_flow_error_set(error, ENOTSUP,
2119                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2120                                           "multiple source ports are not"
2121                                           " supported");
2122         if (!mask)
2123                 mask = &switch_mask;
2124         if (mask->id != 0xffffffff)
2125                 return rte_flow_error_set(error, ENOTSUP,
2126                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2127                                            mask,
2128                                            "no support for partial mask on"
2129                                            " \"id\" field");
2130         ret = mlx5_flow_item_acceptable
2131                                 (item, (const uint8_t *)mask,
2132                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2133                                  sizeof(struct rte_flow_item_port_id),
2134                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2135         if (ret)
2136                 return ret;
2137         if (!spec)
2138                 return 0;
2139         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2140         if (!esw_priv)
2141                 return rte_flow_error_set(error, rte_errno,
2142                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2143                                           "failed to obtain E-Switch info for"
2144                                           " port");
2145         dev_priv = mlx5_dev_to_eswitch_info(dev);
2146         if (!dev_priv)
2147                 return rte_flow_error_set(error, rte_errno,
2148                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2149                                           NULL,
2150                                           "failed to obtain E-Switch info");
2151         if (esw_priv->domain_id != dev_priv->domain_id)
2152                 return rte_flow_error_set(error, EINVAL,
2153                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2154                                           "cannot match on a port from a"
2155                                           " different E-Switch");
2156         return 0;
2157 }
2158
2159 /**
2160  * Validate VLAN item.
2161  *
2162  * @param[in] item
2163  *   Item specification.
2164  * @param[in] item_flags
2165  *   Bit-fields that holds the items detected until now.
2166  * @param[in] dev
2167  *   Ethernet device flow is being created on.
2168  * @param[out] error
2169  *   Pointer to error structure.
2170  *
2171  * @return
2172  *   0 on success, a negative errno value otherwise and rte_errno is set.
2173  */
2174 static int
2175 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2176                            uint64_t item_flags,
2177                            struct rte_eth_dev *dev,
2178                            struct rte_flow_error *error)
2179 {
2180         const struct rte_flow_item_vlan *mask = item->mask;
2181         const struct rte_flow_item_vlan nic_mask = {
2182                 .tci = RTE_BE16(UINT16_MAX),
2183                 .inner_type = RTE_BE16(UINT16_MAX),
2184                 .has_more_vlan = 1,
2185         };
2186         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2187         int ret;
2188         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2189                                         MLX5_FLOW_LAYER_INNER_L4) :
2190                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2191                                         MLX5_FLOW_LAYER_OUTER_L4);
2192         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2193                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2194
2195         if (item_flags & vlanm)
2196                 return rte_flow_error_set(error, EINVAL,
2197                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2198                                           "multiple VLAN layers not supported");
2199         else if ((item_flags & l34m) != 0)
2200                 return rte_flow_error_set(error, EINVAL,
2201                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2202                                           "VLAN cannot follow L3/L4 layer");
2203         if (!mask)
2204                 mask = &rte_flow_item_vlan_mask;
2205         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2206                                         (const uint8_t *)&nic_mask,
2207                                         sizeof(struct rte_flow_item_vlan),
2208                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2209         if (ret)
2210                 return ret;
2211         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2212                 struct mlx5_priv *priv = dev->data->dev_private;
2213
2214                 if (priv->vmwa_context) {
2215                         /*
2216                          * Non-NULL context means we have a virtual machine
2217                          * and SR-IOV enabled, we have to create VLAN interface
2218                          * to make hypervisor to setup E-Switch vport
2219                          * context correctly. We avoid creating the multiple
2220                          * VLAN interfaces, so we cannot support VLAN tag mask.
2221                          */
2222                         return rte_flow_error_set(error, EINVAL,
2223                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2224                                                   item,
2225                                                   "VLAN tag mask is not"
2226                                                   " supported in virtual"
2227                                                   " environment");
2228                 }
2229         }
2230         return 0;
2231 }
2232
2233 /*
2234  * GTP flags are contained in 1 byte of the format:
2235  * -------------------------------------------
2236  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2237  * |-----------------------------------------|
2238  * | value | Version | PT | Res | E | S | PN |
2239  * -------------------------------------------
2240  *
2241  * Matching is supported only for GTP flags E, S, PN.
2242  */
2243 #define MLX5_GTP_FLAGS_MASK     0x07
2244
2245 /**
2246  * Validate GTP item.
2247  *
2248  * @param[in] dev
2249  *   Pointer to the rte_eth_dev structure.
2250  * @param[in] item
2251  *   Item specification.
2252  * @param[in] item_flags
2253  *   Bit-fields that holds the items detected until now.
2254  * @param[out] error
2255  *   Pointer to error structure.
2256  *
2257  * @return
2258  *   0 on success, a negative errno value otherwise and rte_errno is set.
2259  */
2260 static int
2261 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2262                           const struct rte_flow_item *item,
2263                           uint64_t item_flags,
2264                           struct rte_flow_error *error)
2265 {
2266         struct mlx5_priv *priv = dev->data->dev_private;
2267         const struct rte_flow_item_gtp *spec = item->spec;
2268         const struct rte_flow_item_gtp *mask = item->mask;
2269         const struct rte_flow_item_gtp nic_mask = {
2270                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2271                 .msg_type = 0xff,
2272                 .teid = RTE_BE32(0xffffffff),
2273         };
2274
2275         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2276                 return rte_flow_error_set(error, ENOTSUP,
2277                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2278                                           "GTP support is not enabled");
2279         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2280                 return rte_flow_error_set(error, ENOTSUP,
2281                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2282                                           "multiple tunnel layers not"
2283                                           " supported");
2284         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2285                 return rte_flow_error_set(error, EINVAL,
2286                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2287                                           "no outer UDP layer found");
2288         if (!mask)
2289                 mask = &rte_flow_item_gtp_mask;
2290         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2291                 return rte_flow_error_set(error, ENOTSUP,
2292                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2293                                           "Match is supported for GTP"
2294                                           " flags only");
2295         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2296                                          (const uint8_t *)&nic_mask,
2297                                          sizeof(struct rte_flow_item_gtp),
2298                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2299 }
2300
2301 /**
2302  * Validate GTP PSC item.
2303  *
2304  * @param[in] item
2305  *   Item specification.
2306  * @param[in] last_item
2307  *   Previous validated item in the pattern items.
2308  * @param[in] gtp_item
2309  *   Previous GTP item specification.
2310  * @param[in] attr
2311  *   Pointer to flow attributes.
2312  * @param[out] error
2313  *   Pointer to error structure.
2314  *
2315  * @return
2316  *   0 on success, a negative errno value otherwise and rte_errno is set.
2317  */
2318 static int
2319 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2320                               uint64_t last_item,
2321                               const struct rte_flow_item *gtp_item,
2322                               const struct rte_flow_attr *attr,
2323                               struct rte_flow_error *error)
2324 {
2325         const struct rte_flow_item_gtp *gtp_spec;
2326         const struct rte_flow_item_gtp *gtp_mask;
2327         const struct rte_flow_item_gtp_psc *spec;
2328         const struct rte_flow_item_gtp_psc *mask;
2329         const struct rte_flow_item_gtp_psc nic_mask = {
2330                 .pdu_type = 0xFF,
2331                 .qfi = 0xFF,
2332         };
2333
2334         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2335                 return rte_flow_error_set
2336                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2337                          "GTP PSC item must be preceded with GTP item");
2338         gtp_spec = gtp_item->spec;
2339         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2340         /* GTP spec and E flag is requested to match zero. */
2341         if (gtp_spec &&
2342                 (gtp_mask->v_pt_rsv_flags &
2343                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2344                 return rte_flow_error_set
2345                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2346                          "GTP E flag must be 1 to match GTP PSC");
2347         /* Check the flow is not created in group zero. */
2348         if (!attr->transfer && !attr->group)
2349                 return rte_flow_error_set
2350                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2351                          "GTP PSC is not supported for group 0");
2352         /* GTP spec is here and E flag is requested to match zero. */
2353         if (!item->spec)
2354                 return 0;
2355         spec = item->spec;
2356         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2357         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2358                 return rte_flow_error_set
2359                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2360                          "PDU type should be smaller than 16");
2361         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2362                                          (const uint8_t *)&nic_mask,
2363                                          sizeof(struct rte_flow_item_gtp_psc),
2364                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2365 }
2366
2367 /**
2368  * Validate IPV4 item.
2369  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2370  * add specific validation of fragment_offset field,
2371  *
2372  * @param[in] item
2373  *   Item specification.
2374  * @param[in] item_flags
2375  *   Bit-fields that holds the items detected until now.
2376  * @param[out] error
2377  *   Pointer to error structure.
2378  *
2379  * @return
2380  *   0 on success, a negative errno value otherwise and rte_errno is set.
2381  */
2382 static int
2383 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2384                            uint64_t item_flags,
2385                            uint64_t last_item,
2386                            uint16_t ether_type,
2387                            struct rte_flow_error *error)
2388 {
2389         int ret;
2390         const struct rte_flow_item_ipv4 *spec = item->spec;
2391         const struct rte_flow_item_ipv4 *last = item->last;
2392         const struct rte_flow_item_ipv4 *mask = item->mask;
2393         rte_be16_t fragment_offset_spec = 0;
2394         rte_be16_t fragment_offset_last = 0;
2395         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2396                 .hdr = {
2397                         .src_addr = RTE_BE32(0xffffffff),
2398                         .dst_addr = RTE_BE32(0xffffffff),
2399                         .type_of_service = 0xff,
2400                         .fragment_offset = RTE_BE16(0xffff),
2401                         .next_proto_id = 0xff,
2402                         .time_to_live = 0xff,
2403                 },
2404         };
2405
2406         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2407                                            ether_type, &nic_ipv4_mask,
2408                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2409         if (ret < 0)
2410                 return ret;
2411         if (spec && mask)
2412                 fragment_offset_spec = spec->hdr.fragment_offset &
2413                                        mask->hdr.fragment_offset;
2414         if (!fragment_offset_spec)
2415                 return 0;
2416         /*
2417          * spec and mask are valid, enforce using full mask to make sure the
2418          * complete value is used correctly.
2419          */
2420         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2421                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2422                 return rte_flow_error_set(error, EINVAL,
2423                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2424                                           item, "must use full mask for"
2425                                           " fragment_offset");
2426         /*
2427          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2428          * indicating this is 1st fragment of fragmented packet.
2429          * This is not yet supported in MLX5, return appropriate error message.
2430          */
2431         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2432                 return rte_flow_error_set(error, ENOTSUP,
2433                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2434                                           "match on first fragment not "
2435                                           "supported");
2436         if (fragment_offset_spec && !last)
2437                 return rte_flow_error_set(error, ENOTSUP,
2438                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2439                                           "specified value not supported");
2440         /* spec and last are valid, validate the specified range. */
2441         fragment_offset_last = last->hdr.fragment_offset &
2442                                mask->hdr.fragment_offset;
2443         /*
2444          * Match on fragment_offset spec 0x2001 and last 0x3fff
2445          * means MF is 1 and frag-offset is > 0.
2446          * This packet is fragment 2nd and onward, excluding last.
2447          * This is not yet supported in MLX5, return appropriate
2448          * error message.
2449          */
2450         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2451             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2452                 return rte_flow_error_set(error, ENOTSUP,
2453                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2454                                           last, "match on following "
2455                                           "fragments not supported");
2456         /*
2457          * Match on fragment_offset spec 0x0001 and last 0x1fff
2458          * means MF is 0 and frag-offset is > 0.
2459          * This packet is last fragment of fragmented packet.
2460          * This is not yet supported in MLX5, return appropriate
2461          * error message.
2462          */
2463         if (fragment_offset_spec == RTE_BE16(1) &&
2464             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2465                 return rte_flow_error_set(error, ENOTSUP,
2466                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2467                                           last, "match on last "
2468                                           "fragment not supported");
2469         /*
2470          * Match on fragment_offset spec 0x0001 and last 0x3fff
2471          * means MF and/or frag-offset is not 0.
2472          * This is a fragmented packet.
2473          * Other range values are invalid and rejected.
2474          */
2475         if (!(fragment_offset_spec == RTE_BE16(1) &&
2476               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2477                 return rte_flow_error_set(error, ENOTSUP,
2478                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2479                                           "specified range not supported");
2480         return 0;
2481 }
2482
2483 /**
2484  * Validate IPV6 fragment extension item.
2485  *
2486  * @param[in] item
2487  *   Item specification.
2488  * @param[in] item_flags
2489  *   Bit-fields that holds the items detected until now.
2490  * @param[out] error
2491  *   Pointer to error structure.
2492  *
2493  * @return
2494  *   0 on success, a negative errno value otherwise and rte_errno is set.
2495  */
2496 static int
2497 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2498                                     uint64_t item_flags,
2499                                     struct rte_flow_error *error)
2500 {
2501         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2502         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2503         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2504         rte_be16_t frag_data_spec = 0;
2505         rte_be16_t frag_data_last = 0;
2506         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2507         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2508                                       MLX5_FLOW_LAYER_OUTER_L4;
2509         int ret = 0;
2510         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2511                 .hdr = {
2512                         .next_header = 0xff,
2513                         .frag_data = RTE_BE16(0xffff),
2514                 },
2515         };
2516
2517         if (item_flags & l4m)
2518                 return rte_flow_error_set(error, EINVAL,
2519                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2520                                           "ipv6 fragment extension item cannot "
2521                                           "follow L4 item.");
2522         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2523             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2524                 return rte_flow_error_set(error, EINVAL,
2525                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2526                                           "ipv6 fragment extension item must "
2527                                           "follow ipv6 item");
2528         if (spec && mask)
2529                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2530         if (!frag_data_spec)
2531                 return 0;
2532         /*
2533          * spec and mask are valid, enforce using full mask to make sure the
2534          * complete value is used correctly.
2535          */
2536         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2537                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2538                 return rte_flow_error_set(error, EINVAL,
2539                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2540                                           item, "must use full mask for"
2541                                           " frag_data");
2542         /*
2543          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2544          * This is 1st fragment of fragmented packet.
2545          */
2546         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2547                 return rte_flow_error_set(error, ENOTSUP,
2548                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2549                                           "match on first fragment not "
2550                                           "supported");
2551         if (frag_data_spec && !last)
2552                 return rte_flow_error_set(error, EINVAL,
2553                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2554                                           "specified value not supported");
2555         ret = mlx5_flow_item_acceptable
2556                                 (item, (const uint8_t *)mask,
2557                                  (const uint8_t *)&nic_mask,
2558                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2559                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2560         if (ret)
2561                 return ret;
2562         /* spec and last are valid, validate the specified range. */
2563         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2564         /*
2565          * Match on frag_data spec 0x0009 and last 0xfff9
2566          * means M is 1 and frag-offset is > 0.
2567          * This packet is fragment 2nd and onward, excluding last.
2568          * This is not yet supported in MLX5, return appropriate
2569          * error message.
2570          */
2571         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2572                                        RTE_IPV6_EHDR_MF_MASK) &&
2573             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2574                 return rte_flow_error_set(error, ENOTSUP,
2575                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2576                                           last, "match on following "
2577                                           "fragments not supported");
2578         /*
2579          * Match on frag_data spec 0x0008 and last 0xfff8
2580          * means M is 0 and frag-offset is > 0.
2581          * This packet is last fragment of fragmented packet.
2582          * This is not yet supported in MLX5, return appropriate
2583          * error message.
2584          */
2585         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2586             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2587                 return rte_flow_error_set(error, ENOTSUP,
2588                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2589                                           last, "match on last "
2590                                           "fragment not supported");
2591         /* Other range values are invalid and rejected. */
2592         return rte_flow_error_set(error, EINVAL,
2593                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2594                                   "specified range not supported");
2595 }
2596
2597 /**
2598  * Validate the pop VLAN action.
2599  *
2600  * @param[in] dev
2601  *   Pointer to the rte_eth_dev structure.
2602  * @param[in] action_flags
2603  *   Holds the actions detected until now.
2604  * @param[in] action
2605  *   Pointer to the pop vlan action.
2606  * @param[in] item_flags
2607  *   The items found in this flow rule.
2608  * @param[in] attr
2609  *   Pointer to flow attributes.
2610  * @param[out] error
2611  *   Pointer to error structure.
2612  *
2613  * @return
2614  *   0 on success, a negative errno value otherwise and rte_errno is set.
2615  */
2616 static int
2617 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2618                                  uint64_t action_flags,
2619                                  const struct rte_flow_action *action,
2620                                  uint64_t item_flags,
2621                                  const struct rte_flow_attr *attr,
2622                                  struct rte_flow_error *error)
2623 {
2624         const struct mlx5_priv *priv = dev->data->dev_private;
2625
2626         (void)action;
2627         (void)attr;
2628         if (!priv->sh->pop_vlan_action)
2629                 return rte_flow_error_set(error, ENOTSUP,
2630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2631                                           NULL,
2632                                           "pop vlan action is not supported");
2633         if (attr->egress)
2634                 return rte_flow_error_set(error, ENOTSUP,
2635                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2636                                           NULL,
2637                                           "pop vlan action not supported for "
2638                                           "egress");
2639         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2640                 return rte_flow_error_set(error, ENOTSUP,
2641                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2642                                           "no support for multiple VLAN "
2643                                           "actions");
2644         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2645         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2646             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2647                 return rte_flow_error_set(error, ENOTSUP,
2648                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2649                                           NULL,
2650                                           "cannot pop vlan after decap without "
2651                                           "match on inner vlan in the flow");
2652         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2653         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2654             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2655                 return rte_flow_error_set(error, ENOTSUP,
2656                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2657                                           NULL,
2658                                           "cannot pop vlan without a "
2659                                           "match on (outer) vlan in the flow");
2660         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2661                 return rte_flow_error_set(error, EINVAL,
2662                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2663                                           "wrong action order, port_id should "
2664                                           "be after pop VLAN action");
2665         if (!attr->transfer && priv->representor)
2666                 return rte_flow_error_set(error, ENOTSUP,
2667                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2668                                           "pop vlan action for VF representor "
2669                                           "not supported on NIC table");
2670         return 0;
2671 }
2672
2673 /**
2674  * Get VLAN default info from vlan match info.
2675  *
2676  * @param[in] items
2677  *   the list of item specifications.
2678  * @param[out] vlan
2679  *   pointer VLAN info to fill to.
2680  *
2681  * @return
2682  *   0 on success, a negative errno value otherwise and rte_errno is set.
2683  */
2684 static void
2685 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2686                                   struct rte_vlan_hdr *vlan)
2687 {
2688         const struct rte_flow_item_vlan nic_mask = {
2689                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2690                                 MLX5DV_FLOW_VLAN_VID_MASK),
2691                 .inner_type = RTE_BE16(0xffff),
2692         };
2693
2694         if (items == NULL)
2695                 return;
2696         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2697                 int type = items->type;
2698
2699                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2700                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2701                         break;
2702         }
2703         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2704                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2705                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2706
2707                 /* If VLAN item in pattern doesn't contain data, return here. */
2708                 if (!vlan_v)
2709                         return;
2710                 if (!vlan_m)
2711                         vlan_m = &nic_mask;
2712                 /* Only full match values are accepted */
2713                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2714                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2715                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2716                         vlan->vlan_tci |=
2717                                 rte_be_to_cpu_16(vlan_v->tci &
2718                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2719                 }
2720                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2721                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2722                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2723                         vlan->vlan_tci |=
2724                                 rte_be_to_cpu_16(vlan_v->tci &
2725                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2726                 }
2727                 if (vlan_m->inner_type == nic_mask.inner_type)
2728                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2729                                                            vlan_m->inner_type);
2730         }
2731 }
2732
2733 /**
2734  * Validate the push VLAN action.
2735  *
2736  * @param[in] dev
2737  *   Pointer to the rte_eth_dev structure.
2738  * @param[in] action_flags
2739  *   Holds the actions detected until now.
2740  * @param[in] item_flags
2741  *   The items found in this flow rule.
2742  * @param[in] action
2743  *   Pointer to the action structure.
2744  * @param[in] attr
2745  *   Pointer to flow attributes
2746  * @param[out] error
2747  *   Pointer to error structure.
2748  *
2749  * @return
2750  *   0 on success, a negative errno value otherwise and rte_errno is set.
2751  */
2752 static int
2753 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2754                                   uint64_t action_flags,
2755                                   const struct rte_flow_item_vlan *vlan_m,
2756                                   const struct rte_flow_action *action,
2757                                   const struct rte_flow_attr *attr,
2758                                   struct rte_flow_error *error)
2759 {
2760         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2761         const struct mlx5_priv *priv = dev->data->dev_private;
2762
2763         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2764             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2765                 return rte_flow_error_set(error, EINVAL,
2766                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2767                                           "invalid vlan ethertype");
2768         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2769                 return rte_flow_error_set(error, EINVAL,
2770                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2771                                           "wrong action order, port_id should "
2772                                           "be after push VLAN");
2773         if (!attr->transfer && priv->representor)
2774                 return rte_flow_error_set(error, ENOTSUP,
2775                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776                                           "push vlan action for VF representor "
2777                                           "not supported on NIC table");
2778         if (vlan_m &&
2779             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2780             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2781                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2782             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2783             !(mlx5_flow_find_action
2784                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2785                 return rte_flow_error_set(error, EINVAL,
2786                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2787                                           "not full match mask on VLAN PCP and "
2788                                           "there is no of_set_vlan_pcp action, "
2789                                           "push VLAN action cannot figure out "
2790                                           "PCP value");
2791         if (vlan_m &&
2792             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2793             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2794                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2795             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2796             !(mlx5_flow_find_action
2797                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2798                 return rte_flow_error_set(error, EINVAL,
2799                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2800                                           "not full match mask on VLAN VID and "
2801                                           "there is no of_set_vlan_vid action, "
2802                                           "push VLAN action cannot figure out "
2803                                           "VID value");
2804         (void)attr;
2805         return 0;
2806 }
2807
2808 /**
2809  * Validate the set VLAN PCP.
2810  *
2811  * @param[in] action_flags
2812  *   Holds the actions detected until now.
2813  * @param[in] actions
2814  *   Pointer to the list of actions remaining in the flow rule.
2815  * @param[out] error
2816  *   Pointer to error structure.
2817  *
2818  * @return
2819  *   0 on success, a negative errno value otherwise and rte_errno is set.
2820  */
2821 static int
2822 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2823                                      const struct rte_flow_action actions[],
2824                                      struct rte_flow_error *error)
2825 {
2826         const struct rte_flow_action *action = actions;
2827         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2828
2829         if (conf->vlan_pcp > 7)
2830                 return rte_flow_error_set(error, EINVAL,
2831                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2832                                           "VLAN PCP value is too big");
2833         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2834                 return rte_flow_error_set(error, ENOTSUP,
2835                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2836                                           "set VLAN PCP action must follow "
2837                                           "the push VLAN action");
2838         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2839                 return rte_flow_error_set(error, ENOTSUP,
2840                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2841                                           "Multiple VLAN PCP modification are "
2842                                           "not supported");
2843         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2844                 return rte_flow_error_set(error, EINVAL,
2845                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2846                                           "wrong action order, port_id should "
2847                                           "be after set VLAN PCP");
2848         return 0;
2849 }
2850
2851 /**
2852  * Validate the set VLAN VID.
2853  *
2854  * @param[in] item_flags
2855  *   Holds the items detected in this rule.
2856  * @param[in] action_flags
2857  *   Holds the actions detected until now.
2858  * @param[in] actions
2859  *   Pointer to the list of actions remaining in the flow rule.
2860  * @param[out] error
2861  *   Pointer to error structure.
2862  *
2863  * @return
2864  *   0 on success, a negative errno value otherwise and rte_errno is set.
2865  */
2866 static int
2867 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2868                                      uint64_t action_flags,
2869                                      const struct rte_flow_action actions[],
2870                                      struct rte_flow_error *error)
2871 {
2872         const struct rte_flow_action *action = actions;
2873         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2874
2875         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2876                 return rte_flow_error_set(error, EINVAL,
2877                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2878                                           "VLAN VID value is too big");
2879         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2880             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2881                 return rte_flow_error_set(error, ENOTSUP,
2882                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2883                                           "set VLAN VID action must follow push"
2884                                           " VLAN action or match on VLAN item");
2885         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2886                 return rte_flow_error_set(error, ENOTSUP,
2887                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2888                                           "Multiple VLAN VID modifications are "
2889                                           "not supported");
2890         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891                 return rte_flow_error_set(error, EINVAL,
2892                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2893                                           "wrong action order, port_id should "
2894                                           "be after set VLAN VID");
2895         return 0;
2896 }
2897
2898 /*
2899  * Validate the FLAG action.
2900  *
2901  * @param[in] dev
2902  *   Pointer to the rte_eth_dev structure.
2903  * @param[in] action_flags
2904  *   Holds the actions detected until now.
2905  * @param[in] attr
2906  *   Pointer to flow attributes
2907  * @param[out] error
2908  *   Pointer to error structure.
2909  *
2910  * @return
2911  *   0 on success, a negative errno value otherwise and rte_errno is set.
2912  */
2913 static int
2914 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2915                              uint64_t action_flags,
2916                              const struct rte_flow_attr *attr,
2917                              struct rte_flow_error *error)
2918 {
2919         struct mlx5_priv *priv = dev->data->dev_private;
2920         struct mlx5_dev_config *config = &priv->config;
2921         int ret;
2922
2923         /* Fall back if no extended metadata register support. */
2924         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2925                 return mlx5_flow_validate_action_flag(action_flags, attr,
2926                                                       error);
2927         /* Extensive metadata mode requires registers. */
2928         if (!mlx5_flow_ext_mreg_supported(dev))
2929                 return rte_flow_error_set(error, ENOTSUP,
2930                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2931                                           "no metadata registers "
2932                                           "to support flag action");
2933         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2934                 return rte_flow_error_set(error, ENOTSUP,
2935                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2936                                           "extended metadata register"
2937                                           " isn't available");
2938         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2939         if (ret < 0)
2940                 return ret;
2941         MLX5_ASSERT(ret > 0);
2942         if (action_flags & MLX5_FLOW_ACTION_MARK)
2943                 return rte_flow_error_set(error, EINVAL,
2944                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2945                                           "can't mark and flag in same flow");
2946         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2947                 return rte_flow_error_set(error, EINVAL,
2948                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2949                                           "can't have 2 flag"
2950                                           " actions in same flow");
2951         return 0;
2952 }
2953
2954 /**
2955  * Validate MARK action.
2956  *
2957  * @param[in] dev
2958  *   Pointer to the rte_eth_dev structure.
2959  * @param[in] action
2960  *   Pointer to action.
2961  * @param[in] action_flags
2962  *   Holds the actions detected until now.
2963  * @param[in] attr
2964  *   Pointer to flow attributes
2965  * @param[out] error
2966  *   Pointer to error structure.
2967  *
2968  * @return
2969  *   0 on success, a negative errno value otherwise and rte_errno is set.
2970  */
2971 static int
2972 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2973                              const struct rte_flow_action *action,
2974                              uint64_t action_flags,
2975                              const struct rte_flow_attr *attr,
2976                              struct rte_flow_error *error)
2977 {
2978         struct mlx5_priv *priv = dev->data->dev_private;
2979         struct mlx5_dev_config *config = &priv->config;
2980         const struct rte_flow_action_mark *mark = action->conf;
2981         int ret;
2982
2983         if (is_tunnel_offload_active(dev))
2984                 return rte_flow_error_set(error, ENOTSUP,
2985                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2986                                           "no mark action "
2987                                           "if tunnel offload active");
2988         /* Fall back if no extended metadata register support. */
2989         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2990                 return mlx5_flow_validate_action_mark(action, action_flags,
2991                                                       attr, error);
2992         /* Extensive metadata mode requires registers. */
2993         if (!mlx5_flow_ext_mreg_supported(dev))
2994                 return rte_flow_error_set(error, ENOTSUP,
2995                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2996                                           "no metadata registers "
2997                                           "to support mark action");
2998         if (!priv->sh->dv_mark_mask)
2999                 return rte_flow_error_set(error, ENOTSUP,
3000                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3001                                           "extended metadata register"
3002                                           " isn't available");
3003         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3004         if (ret < 0)
3005                 return ret;
3006         MLX5_ASSERT(ret > 0);
3007         if (!mark)
3008                 return rte_flow_error_set(error, EINVAL,
3009                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3010                                           "configuration cannot be null");
3011         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3012                 return rte_flow_error_set(error, EINVAL,
3013                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3014                                           &mark->id,
3015                                           "mark id exceeds the limit");
3016         if (action_flags & MLX5_FLOW_ACTION_FLAG)
3017                 return rte_flow_error_set(error, EINVAL,
3018                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3019                                           "can't flag and mark in same flow");
3020         if (action_flags & MLX5_FLOW_ACTION_MARK)
3021                 return rte_flow_error_set(error, EINVAL,
3022                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3023                                           "can't have 2 mark actions in same"
3024                                           " flow");
3025         return 0;
3026 }
3027
3028 /**
3029  * Validate SET_META action.
3030  *
3031  * @param[in] dev
3032  *   Pointer to the rte_eth_dev structure.
3033  * @param[in] action
3034  *   Pointer to the action structure.
3035  * @param[in] action_flags
3036  *   Holds the actions detected until now.
3037  * @param[in] attr
3038  *   Pointer to flow attributes
3039  * @param[out] error
3040  *   Pointer to error structure.
3041  *
3042  * @return
3043  *   0 on success, a negative errno value otherwise and rte_errno is set.
3044  */
3045 static int
3046 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3047                                  const struct rte_flow_action *action,
3048                                  uint64_t action_flags __rte_unused,
3049                                  const struct rte_flow_attr *attr,
3050                                  struct rte_flow_error *error)
3051 {
3052         const struct rte_flow_action_set_meta *conf;
3053         uint32_t nic_mask = UINT32_MAX;
3054         int reg;
3055
3056         if (!mlx5_flow_ext_mreg_supported(dev))
3057                 return rte_flow_error_set(error, ENOTSUP,
3058                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3059                                           "extended metadata register"
3060                                           " isn't supported");
3061         reg = flow_dv_get_metadata_reg(dev, attr, error);
3062         if (reg < 0)
3063                 return reg;
3064         if (reg == REG_NON)
3065                 return rte_flow_error_set(error, ENOTSUP,
3066                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3067                                           "unavalable extended metadata register");
3068         if (reg != REG_A && reg != REG_B) {
3069                 struct mlx5_priv *priv = dev->data->dev_private;
3070
3071                 nic_mask = priv->sh->dv_meta_mask;
3072         }
3073         if (!(action->conf))
3074                 return rte_flow_error_set(error, EINVAL,
3075                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3076                                           "configuration cannot be null");
3077         conf = (const struct rte_flow_action_set_meta *)action->conf;
3078         if (!conf->mask)
3079                 return rte_flow_error_set(error, EINVAL,
3080                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3081                                           "zero mask doesn't have any effect");
3082         if (conf->mask & ~nic_mask)
3083                 return rte_flow_error_set(error, EINVAL,
3084                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3085                                           "meta data must be within reg C0");
3086         return 0;
3087 }
3088
3089 /**
3090  * Validate SET_TAG action.
3091  *
3092  * @param[in] dev
3093  *   Pointer to the rte_eth_dev structure.
3094  * @param[in] action
3095  *   Pointer to the action structure.
3096  * @param[in] action_flags
3097  *   Holds the actions detected until now.
3098  * @param[in] attr
3099  *   Pointer to flow attributes
3100  * @param[out] error
3101  *   Pointer to error structure.
3102  *
3103  * @return
3104  *   0 on success, a negative errno value otherwise and rte_errno is set.
3105  */
3106 static int
3107 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3108                                 const struct rte_flow_action *action,
3109                                 uint64_t action_flags,
3110                                 const struct rte_flow_attr *attr,
3111                                 struct rte_flow_error *error)
3112 {
3113         const struct rte_flow_action_set_tag *conf;
3114         const uint64_t terminal_action_flags =
3115                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3116                 MLX5_FLOW_ACTION_RSS;
3117         int ret;
3118
3119         if (!mlx5_flow_ext_mreg_supported(dev))
3120                 return rte_flow_error_set(error, ENOTSUP,
3121                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3122                                           "extensive metadata register"
3123                                           " isn't supported");
3124         if (!(action->conf))
3125                 return rte_flow_error_set(error, EINVAL,
3126                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3127                                           "configuration cannot be null");
3128         conf = (const struct rte_flow_action_set_tag *)action->conf;
3129         if (!conf->mask)
3130                 return rte_flow_error_set(error, EINVAL,
3131                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3132                                           "zero mask doesn't have any effect");
3133         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3134         if (ret < 0)
3135                 return ret;
3136         if (!attr->transfer && attr->ingress &&
3137             (action_flags & terminal_action_flags))
3138                 return rte_flow_error_set(error, EINVAL,
3139                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3140                                           "set_tag has no effect"
3141                                           " with terminal actions");
3142         return 0;
3143 }
3144
3145 /**
3146  * Validate count action.
3147  *
3148  * @param[in] dev
3149  *   Pointer to rte_eth_dev structure.
3150  * @param[in] action
3151  *   Pointer to the action structure.
3152  * @param[in] action_flags
3153  *   Holds the actions detected until now.
3154  * @param[out] error
3155  *   Pointer to error structure.
3156  *
3157  * @return
3158  *   0 on success, a negative errno value otherwise and rte_errno is set.
3159  */
3160 static int
3161 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3162                               const struct rte_flow_action *action,
3163                               uint64_t action_flags,
3164                               struct rte_flow_error *error)
3165 {
3166         struct mlx5_priv *priv = dev->data->dev_private;
3167         const struct rte_flow_action_count *count;
3168
3169         if (!priv->config.devx)
3170                 goto notsup_err;
3171         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3172                 return rte_flow_error_set(error, EINVAL,
3173                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3174                                           "duplicate count actions set");
3175         count = (const struct rte_flow_action_count *)action->conf;
3176         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3177             !priv->sh->flow_hit_aso_en)
3178                 return rte_flow_error_set(error, EINVAL,
3179                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3180                                           "old age and shared count combination is not supported");
3181 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3182         return 0;
3183 #endif
3184 notsup_err:
3185         return rte_flow_error_set
3186                       (error, ENOTSUP,
3187                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3188                        NULL,
3189                        "count action not supported");
3190 }
3191
3192 /**
3193  * Validate the L2 encap action.
3194  *
3195  * @param[in] dev
3196  *   Pointer to the rte_eth_dev structure.
3197  * @param[in] action_flags
3198  *   Holds the actions detected until now.
3199  * @param[in] action
3200  *   Pointer to the action structure.
3201  * @param[in] attr
3202  *   Pointer to flow attributes.
3203  * @param[out] error
3204  *   Pointer to error structure.
3205  *
3206  * @return
3207  *   0 on success, a negative errno value otherwise and rte_errno is set.
3208  */
3209 static int
3210 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3211                                  uint64_t action_flags,
3212                                  const struct rte_flow_action *action,
3213                                  const struct rte_flow_attr *attr,
3214                                  struct rte_flow_error *error)
3215 {
3216         const struct mlx5_priv *priv = dev->data->dev_private;
3217
3218         if (!(action->conf))
3219                 return rte_flow_error_set(error, EINVAL,
3220                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3221                                           "configuration cannot be null");
3222         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3223                 return rte_flow_error_set(error, EINVAL,
3224                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3225                                           "can only have a single encap action "
3226                                           "in a flow");
3227         if (!attr->transfer && priv->representor)
3228                 return rte_flow_error_set(error, ENOTSUP,
3229                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3230                                           "encap action for VF representor "
3231                                           "not supported on NIC table");
3232         return 0;
3233 }
3234
3235 /**
3236  * Validate a decap action.
3237  *
3238  * @param[in] dev
3239  *   Pointer to the rte_eth_dev structure.
3240  * @param[in] action_flags
3241  *   Holds the actions detected until now.
3242  * @param[in] action
3243  *   Pointer to the action structure.
3244  * @param[in] item_flags
3245  *   Holds the items detected.
3246  * @param[in] attr
3247  *   Pointer to flow attributes
3248  * @param[out] error
3249  *   Pointer to error structure.
3250  *
3251  * @return
3252  *   0 on success, a negative errno value otherwise and rte_errno is set.
3253  */
3254 static int
3255 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3256                               uint64_t action_flags,
3257                               const struct rte_flow_action *action,
3258                               const uint64_t item_flags,
3259                               const struct rte_flow_attr *attr,
3260                               struct rte_flow_error *error)
3261 {
3262         const struct mlx5_priv *priv = dev->data->dev_private;
3263
3264         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3265             !priv->config.decap_en)
3266                 return rte_flow_error_set(error, ENOTSUP,
3267                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3268                                           "decap is not enabled");
3269         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3270                 return rte_flow_error_set(error, ENOTSUP,
3271                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3272                                           action_flags &
3273                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3274                                           "have a single decap action" : "decap "
3275                                           "after encap is not supported");
3276         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3277                 return rte_flow_error_set(error, EINVAL,
3278                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3279                                           "can't have decap action after"
3280                                           " modify action");
3281         if (attr->egress)
3282                 return rte_flow_error_set(error, ENOTSUP,
3283                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3284                                           NULL,
3285                                           "decap action not supported for "
3286                                           "egress");
3287         if (!attr->transfer && priv->representor)
3288                 return rte_flow_error_set(error, ENOTSUP,
3289                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3290                                           "decap action for VF representor "
3291                                           "not supported on NIC table");
3292         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3293             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3294                 return rte_flow_error_set(error, ENOTSUP,
3295                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3296                                 "VXLAN item should be present for VXLAN decap");
3297         return 0;
3298 }
3299
3300 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3301
3302 /**
3303  * Validate the raw encap and decap actions.
3304  *
3305  * @param[in] dev
3306  *   Pointer to the rte_eth_dev structure.
3307  * @param[in] decap
3308  *   Pointer to the decap action.
3309  * @param[in] encap
3310  *   Pointer to the encap action.
3311  * @param[in] attr
3312  *   Pointer to flow attributes
3313  * @param[in/out] action_flags
3314  *   Holds the actions detected until now.
3315  * @param[out] actions_n
3316  *   pointer to the number of actions counter.
3317  * @param[in] action
3318  *   Pointer to the action structure.
3319  * @param[in] item_flags
3320  *   Holds the items detected.
3321  * @param[out] error
3322  *   Pointer to error structure.
3323  *
3324  * @return
3325  *   0 on success, a negative errno value otherwise and rte_errno is set.
3326  */
3327 static int
3328 flow_dv_validate_action_raw_encap_decap
3329         (struct rte_eth_dev *dev,
3330          const struct rte_flow_action_raw_decap *decap,
3331          const struct rte_flow_action_raw_encap *encap,
3332          const struct rte_flow_attr *attr, uint64_t *action_flags,
3333          int *actions_n, const struct rte_flow_action *action,
3334          uint64_t item_flags, struct rte_flow_error *error)
3335 {
3336         const struct mlx5_priv *priv = dev->data->dev_private;
3337         int ret;
3338
3339         if (encap && (!encap->size || !encap->data))
3340                 return rte_flow_error_set(error, EINVAL,
3341                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3342                                           "raw encap data cannot be empty");
3343         if (decap && encap) {
3344                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3345                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3346                         /* L3 encap. */
3347                         decap = NULL;
3348                 else if (encap->size <=
3349                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3350                            decap->size >
3351                            MLX5_ENCAPSULATION_DECISION_SIZE)
3352                         /* L3 decap. */
3353                         encap = NULL;
3354                 else if (encap->size >
3355                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3356                            decap->size >
3357                            MLX5_ENCAPSULATION_DECISION_SIZE)
3358                         /* 2 L2 actions: encap and decap. */
3359                         ;
3360                 else
3361                         return rte_flow_error_set(error,
3362                                 ENOTSUP,
3363                                 RTE_FLOW_ERROR_TYPE_ACTION,
3364                                 NULL, "unsupported too small "
3365                                 "raw decap and too small raw "
3366                                 "encap combination");
3367         }
3368         if (decap) {
3369                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3370                                                     item_flags, attr, error);
3371                 if (ret < 0)
3372                         return ret;
3373                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3374                 ++(*actions_n);
3375         }
3376         if (encap) {
3377                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3378                         return rte_flow_error_set(error, ENOTSUP,
3379                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3380                                                   NULL,
3381                                                   "small raw encap size");
3382                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3383                         return rte_flow_error_set(error, EINVAL,
3384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3385                                                   NULL,
3386                                                   "more than one encap action");
3387                 if (!attr->transfer && priv->representor)
3388                         return rte_flow_error_set
3389                                         (error, ENOTSUP,
3390                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3391                                          "encap action for VF representor "
3392                                          "not supported on NIC table");
3393                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3394                 ++(*actions_n);
3395         }
3396         return 0;
3397 }
3398
3399 /**
3400  * Match encap_decap resource.
3401  *
3402  * @param list
3403  *   Pointer to the hash list.
3404  * @param entry
3405  *   Pointer to exist resource entry object.
3406  * @param key
3407  *   Key of the new entry.
3408  * @param ctx_cb
3409  *   Pointer to new encap_decap resource.
3410  *
3411  * @return
3412  *   0 on matching, none-zero otherwise.
3413  */
3414 int
3415 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3416                              struct mlx5_hlist_entry *entry,
3417                              uint64_t key __rte_unused, void *cb_ctx)
3418 {
3419         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3420         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3421         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3422
3423         cache_resource = container_of(entry,
3424                                       struct mlx5_flow_dv_encap_decap_resource,
3425                                       entry);
3426         if (resource->reformat_type == cache_resource->reformat_type &&
3427             resource->ft_type == cache_resource->ft_type &&
3428             resource->flags == cache_resource->flags &&
3429             resource->size == cache_resource->size &&
3430             !memcmp((const void *)resource->buf,
3431                     (const void *)cache_resource->buf,
3432                     resource->size))
3433                 return 0;
3434         return -1;
3435 }
3436
3437 /**
3438  * Allocate encap_decap resource.
3439  *
3440  * @param list
3441  *   Pointer to the hash list.
3442  * @param entry
3443  *   Pointer to exist resource entry object.
3444  * @param ctx_cb
3445  *   Pointer to new encap_decap resource.
3446  *
3447  * @return
3448  *   0 on matching, none-zero otherwise.
3449  */
3450 struct mlx5_hlist_entry *
3451 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3452                               uint64_t key __rte_unused,
3453                               void *cb_ctx)
3454 {
3455         struct mlx5_dev_ctx_shared *sh = list->ctx;
3456         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3457         struct mlx5dv_dr_domain *domain;
3458         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3459         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3460         uint32_t idx;
3461         int ret;
3462
3463         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3464                 domain = sh->fdb_domain;
3465         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3466                 domain = sh->rx_domain;
3467         else
3468                 domain = sh->tx_domain;
3469         /* Register new encap/decap resource. */
3470         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3471                                        &idx);
3472         if (!cache_resource) {
3473                 rte_flow_error_set(ctx->error, ENOMEM,
3474                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3475                                    "cannot allocate resource memory");
3476                 return NULL;
3477         }
3478         *cache_resource = *resource;
3479         cache_resource->idx = idx;
3480         ret = mlx5_flow_os_create_flow_action_packet_reformat
3481                                         (sh->ctx, domain, cache_resource,
3482                                          &cache_resource->action);
3483         if (ret) {
3484                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3485                 rte_flow_error_set(ctx->error, ENOMEM,
3486                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3487                                    NULL, "cannot create action");
3488                 return NULL;
3489         }
3490
3491         return &cache_resource->entry;
3492 }
3493
3494 /**
3495  * Find existing encap/decap resource or create and register a new one.
3496  *
3497  * @param[in, out] dev
3498  *   Pointer to rte_eth_dev structure.
3499  * @param[in, out] resource
3500  *   Pointer to encap/decap resource.
3501  * @parm[in, out] dev_flow
3502  *   Pointer to the dev_flow.
3503  * @param[out] error
3504  *   pointer to error structure.
3505  *
3506  * @return
3507  *   0 on success otherwise -errno and errno is set.
3508  */
3509 static int
3510 flow_dv_encap_decap_resource_register
3511                         (struct rte_eth_dev *dev,
3512                          struct mlx5_flow_dv_encap_decap_resource *resource,
3513                          struct mlx5_flow *dev_flow,
3514                          struct rte_flow_error *error)
3515 {
3516         struct mlx5_priv *priv = dev->data->dev_private;
3517         struct mlx5_dev_ctx_shared *sh = priv->sh;
3518         struct mlx5_hlist_entry *entry;
3519         union {
3520                 struct {
3521                         uint32_t ft_type:8;
3522                         uint32_t refmt_type:8;
3523                         /*
3524                          * Header reformat actions can be shared between
3525                          * non-root tables. One bit to indicate non-root
3526                          * table or not.
3527                          */
3528                         uint32_t is_root:1;
3529                         uint32_t reserve:15;
3530                 };
3531                 uint32_t v32;
3532         } encap_decap_key = {
3533                 {
3534                         .ft_type = resource->ft_type,
3535                         .refmt_type = resource->reformat_type,
3536                         .is_root = !!dev_flow->dv.group,
3537                         .reserve = 0,
3538                 }
3539         };
3540         struct mlx5_flow_cb_ctx ctx = {
3541                 .error = error,
3542                 .data = resource,
3543         };
3544         uint64_t key64;
3545
3546         resource->flags = dev_flow->dv.group ? 0 : 1;
3547         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3548                                  sizeof(encap_decap_key.v32), 0);
3549         if (resource->reformat_type !=
3550             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3551             resource->size)
3552                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3553         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3554         if (!entry)
3555                 return -rte_errno;
3556         resource = container_of(entry, typeof(*resource), entry);
3557         dev_flow->dv.encap_decap = resource;
3558         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3559         return 0;
3560 }
3561
3562 /**
3563  * Find existing table jump resource or create and register a new one.
3564  *
3565  * @param[in, out] dev
3566  *   Pointer to rte_eth_dev structure.
3567  * @param[in, out] tbl
3568  *   Pointer to flow table resource.
3569  * @parm[in, out] dev_flow
3570  *   Pointer to the dev_flow.
3571  * @param[out] error
3572  *   pointer to error structure.
3573  *
3574  * @return
3575  *   0 on success otherwise -errno and errno is set.
3576  */
3577 static int
3578 flow_dv_jump_tbl_resource_register
3579                         (struct rte_eth_dev *dev __rte_unused,
3580                          struct mlx5_flow_tbl_resource *tbl,
3581                          struct mlx5_flow *dev_flow,
3582                          struct rte_flow_error *error __rte_unused)
3583 {
3584         struct mlx5_flow_tbl_data_entry *tbl_data =
3585                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3586
3587         MLX5_ASSERT(tbl);
3588         MLX5_ASSERT(tbl_data->jump.action);
3589         dev_flow->handle->rix_jump = tbl_data->idx;
3590         dev_flow->dv.jump = &tbl_data->jump;
3591         return 0;
3592 }
3593
3594 int
3595 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3596                          struct mlx5_cache_entry *entry, void *cb_ctx)
3597 {
3598         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3599         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3600         struct mlx5_flow_dv_port_id_action_resource *res =
3601                         container_of(entry, typeof(*res), entry);
3602
3603         return ref->port_id != res->port_id;
3604 }
3605
3606 struct mlx5_cache_entry *
3607 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3608                           struct mlx5_cache_entry *entry __rte_unused,
3609                           void *cb_ctx)
3610 {
3611         struct mlx5_dev_ctx_shared *sh = list->ctx;
3612         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3613         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3614         struct mlx5_flow_dv_port_id_action_resource *cache;
3615         uint32_t idx;
3616         int ret;
3617
3618         /* Register new port id action resource. */
3619         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3620         if (!cache) {
3621                 rte_flow_error_set(ctx->error, ENOMEM,
3622                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3623                                    "cannot allocate port_id action cache memory");
3624                 return NULL;
3625         }
3626         *cache = *ref;
3627         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3628                                                         ref->port_id,
3629                                                         &cache->action);
3630         if (ret) {
3631                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3632                 rte_flow_error_set(ctx->error, ENOMEM,
3633                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3634                                    "cannot create action");
3635                 return NULL;
3636         }
3637         cache->idx = idx;
3638         return &cache->entry;
3639 }
3640
3641 /**
3642  * Find existing table port ID resource or create and register a new one.
3643  *
3644  * @param[in, out] dev
3645  *   Pointer to rte_eth_dev structure.
3646  * @param[in, out] resource
3647  *   Pointer to port ID action resource.
3648  * @parm[in, out] dev_flow
3649  *   Pointer to the dev_flow.
3650  * @param[out] error
3651  *   pointer to error structure.
3652  *
3653  * @return
3654  *   0 on success otherwise -errno and errno is set.
3655  */
3656 static int
3657 flow_dv_port_id_action_resource_register
3658                         (struct rte_eth_dev *dev,
3659                          struct mlx5_flow_dv_port_id_action_resource *resource,
3660                          struct mlx5_flow *dev_flow,
3661                          struct rte_flow_error *error)
3662 {
3663         struct mlx5_priv *priv = dev->data->dev_private;
3664         struct mlx5_cache_entry *entry;
3665         struct mlx5_flow_dv_port_id_action_resource *cache;
3666         struct mlx5_flow_cb_ctx ctx = {
3667                 .error = error,
3668                 .data = resource,
3669         };
3670
3671         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3672         if (!entry)
3673                 return -rte_errno;
3674         cache = container_of(entry, typeof(*cache), entry);
3675         dev_flow->dv.port_id_action = cache;
3676         dev_flow->handle->rix_port_id_action = cache->idx;
3677         return 0;
3678 }
3679
3680 int
3681 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3682                          struct mlx5_cache_entry *entry, void *cb_ctx)
3683 {
3684         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3685         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3686         struct mlx5_flow_dv_push_vlan_action_resource *res =
3687                         container_of(entry, typeof(*res), entry);
3688
3689         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3690 }
3691
3692 struct mlx5_cache_entry *
3693 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3694                           struct mlx5_cache_entry *entry __rte_unused,
3695                           void *cb_ctx)
3696 {
3697         struct mlx5_dev_ctx_shared *sh = list->ctx;
3698         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3699         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3700         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3701         struct mlx5dv_dr_domain *domain;
3702         uint32_t idx;
3703         int ret;
3704
3705         /* Register new port id action resource. */
3706         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3707         if (!cache) {
3708                 rte_flow_error_set(ctx->error, ENOMEM,
3709                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3710                                    "cannot allocate push_vlan action cache memory");
3711                 return NULL;
3712         }
3713         *cache = *ref;
3714         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3715                 domain = sh->fdb_domain;
3716         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3717                 domain = sh->rx_domain;
3718         else
3719                 domain = sh->tx_domain;
3720         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3721                                                         &cache->action);
3722         if (ret) {
3723                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3724                 rte_flow_error_set(ctx->error, ENOMEM,
3725                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3726                                    "cannot create push vlan action");
3727                 return NULL;
3728         }
3729         cache->idx = idx;
3730         return &cache->entry;
3731 }
3732
3733 /**
3734  * Find existing push vlan resource or create and register a new one.
3735  *
3736  * @param [in, out] dev
3737  *   Pointer to rte_eth_dev structure.
3738  * @param[in, out] resource
3739  *   Pointer to port ID action resource.
3740  * @parm[in, out] dev_flow
3741  *   Pointer to the dev_flow.
3742  * @param[out] error
3743  *   pointer to error structure.
3744  *
3745  * @return
3746  *   0 on success otherwise -errno and errno is set.
3747  */
3748 static int
3749 flow_dv_push_vlan_action_resource_register
3750                        (struct rte_eth_dev *dev,
3751                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3752                         struct mlx5_flow *dev_flow,
3753                         struct rte_flow_error *error)
3754 {
3755         struct mlx5_priv *priv = dev->data->dev_private;
3756         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3757         struct mlx5_cache_entry *entry;
3758         struct mlx5_flow_cb_ctx ctx = {
3759                 .error = error,
3760                 .data = resource,
3761         };
3762
3763         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3764         if (!entry)
3765                 return -rte_errno;
3766         cache = container_of(entry, typeof(*cache), entry);
3767
3768         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3769         dev_flow->dv.push_vlan_res = cache;
3770         return 0;
3771 }
3772
3773 /**
3774  * Get the size of specific rte_flow_item_type hdr size
3775  *
3776  * @param[in] item_type
3777  *   Tested rte_flow_item_type.
3778  *
3779  * @return
3780  *   sizeof struct item_type, 0 if void or irrelevant.
3781  */
3782 static size_t
3783 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3784 {
3785         size_t retval;
3786
3787         switch (item_type) {
3788         case RTE_FLOW_ITEM_TYPE_ETH:
3789                 retval = sizeof(struct rte_ether_hdr);
3790                 break;
3791         case RTE_FLOW_ITEM_TYPE_VLAN:
3792                 retval = sizeof(struct rte_vlan_hdr);
3793                 break;
3794         case RTE_FLOW_ITEM_TYPE_IPV4:
3795                 retval = sizeof(struct rte_ipv4_hdr);
3796                 break;
3797         case RTE_FLOW_ITEM_TYPE_IPV6:
3798                 retval = sizeof(struct rte_ipv6_hdr);
3799                 break;
3800         case RTE_FLOW_ITEM_TYPE_UDP:
3801                 retval = sizeof(struct rte_udp_hdr);
3802                 break;
3803         case RTE_FLOW_ITEM_TYPE_TCP:
3804                 retval = sizeof(struct rte_tcp_hdr);
3805                 break;
3806         case RTE_FLOW_ITEM_TYPE_VXLAN:
3807         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3808                 retval = sizeof(struct rte_vxlan_hdr);
3809                 break;
3810         case RTE_FLOW_ITEM_TYPE_GRE:
3811         case RTE_FLOW_ITEM_TYPE_NVGRE:
3812                 retval = sizeof(struct rte_gre_hdr);
3813                 break;
3814         case RTE_FLOW_ITEM_TYPE_MPLS:
3815                 retval = sizeof(struct rte_mpls_hdr);
3816                 break;
3817         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3818         default:
3819                 retval = 0;
3820                 break;
3821         }
3822         return retval;
3823 }
3824
3825 #define MLX5_ENCAP_IPV4_VERSION         0x40
3826 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3827 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3828 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3829 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3830 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3831 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3832
3833 /**
3834  * Convert the encap action data from list of rte_flow_item to raw buffer
3835  *
3836  * @param[in] items
3837  *   Pointer to rte_flow_item objects list.
3838  * @param[out] buf
3839  *   Pointer to the output buffer.
3840  * @param[out] size
3841  *   Pointer to the output buffer size.
3842  * @param[out] error
3843  *   Pointer to the error structure.
3844  *
3845  * @return
3846  *   0 on success, a negative errno value otherwise and rte_errno is set.
3847  */
3848 static int
3849 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3850                            size_t *size, struct rte_flow_error *error)
3851 {
3852         struct rte_ether_hdr *eth = NULL;
3853         struct rte_vlan_hdr *vlan = NULL;
3854         struct rte_ipv4_hdr *ipv4 = NULL;
3855         struct rte_ipv6_hdr *ipv6 = NULL;
3856         struct rte_udp_hdr *udp = NULL;
3857         struct rte_vxlan_hdr *vxlan = NULL;
3858         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3859         struct rte_gre_hdr *gre = NULL;
3860         size_t len;
3861         size_t temp_size = 0;
3862
3863         if (!items)
3864                 return rte_flow_error_set(error, EINVAL,
3865                                           RTE_FLOW_ERROR_TYPE_ACTION,
3866                                           NULL, "invalid empty data");
3867         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3868                 len = flow_dv_get_item_hdr_len(items->type);
3869                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3870                         return rte_flow_error_set(error, EINVAL,
3871                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3872                                                   (void *)items->type,
3873                                                   "items total size is too big"
3874                                                   " for encap action");
3875                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3876                 switch (items->type) {
3877                 case RTE_FLOW_ITEM_TYPE_ETH:
3878                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3879                         break;
3880                 case RTE_FLOW_ITEM_TYPE_VLAN:
3881                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3882                         if (!eth)
3883                                 return rte_flow_error_set(error, EINVAL,
3884                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3885                                                 (void *)items->type,
3886                                                 "eth header not found");
3887                         if (!eth->ether_type)
3888                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3889                         break;
3890                 case RTE_FLOW_ITEM_TYPE_IPV4:
3891                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3892                         if (!vlan && !eth)
3893                                 return rte_flow_error_set(error, EINVAL,
3894                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3895                                                 (void *)items->type,
3896                                                 "neither eth nor vlan"
3897                                                 " header found");
3898                         if (vlan && !vlan->eth_proto)
3899                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3900                         else if (eth && !eth->ether_type)
3901                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902                         if (!ipv4->version_ihl)
3903                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3904                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3905                         if (!ipv4->time_to_live)
3906                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3907                         break;
3908                 case RTE_FLOW_ITEM_TYPE_IPV6:
3909                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3910                         if (!vlan && !eth)
3911                                 return rte_flow_error_set(error, EINVAL,
3912                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3913                                                 (void *)items->type,
3914                                                 "neither eth nor vlan"
3915                                                 " header found");
3916                         if (vlan && !vlan->eth_proto)
3917                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3918                         else if (eth && !eth->ether_type)
3919                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920                         if (!ipv6->vtc_flow)
3921                                 ipv6->vtc_flow =
3922                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3923                         if (!ipv6->hop_limits)
3924                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3925                         break;
3926                 case RTE_FLOW_ITEM_TYPE_UDP:
3927                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3928                         if (!ipv4 && !ipv6)
3929                                 return rte_flow_error_set(error, EINVAL,
3930                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3931                                                 (void *)items->type,
3932                                                 "ip header not found");
3933                         if (ipv4 && !ipv4->next_proto_id)
3934                                 ipv4->next_proto_id = IPPROTO_UDP;
3935                         else if (ipv6 && !ipv6->proto)
3936                                 ipv6->proto = IPPROTO_UDP;
3937                         break;
3938                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3939                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3940                         if (!udp)
3941                                 return rte_flow_error_set(error, EINVAL,
3942                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3943                                                 (void *)items->type,
3944                                                 "udp header not found");
3945                         if (!udp->dst_port)
3946                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3947                         if (!vxlan->vx_flags)
3948                                 vxlan->vx_flags =
3949                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3950                         break;
3951                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3952                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3953                         if (!udp)
3954                                 return rte_flow_error_set(error, EINVAL,
3955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3956                                                 (void *)items->type,
3957                                                 "udp header not found");
3958                         if (!vxlan_gpe->proto)
3959                                 return rte_flow_error_set(error, EINVAL,
3960                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3961                                                 (void *)items->type,
3962                                                 "next protocol not found");
3963                         if (!udp->dst_port)
3964                                 udp->dst_port =
3965                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3966                         if (!vxlan_gpe->vx_flags)
3967                                 vxlan_gpe->vx_flags =
3968                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3969                         break;
3970                 case RTE_FLOW_ITEM_TYPE_GRE:
3971                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3972                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3973                         if (!gre->proto)
3974                                 return rte_flow_error_set(error, EINVAL,
3975                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3976                                                 (void *)items->type,
3977                                                 "next protocol not found");
3978                         if (!ipv4 && !ipv6)
3979                                 return rte_flow_error_set(error, EINVAL,
3980                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3981                                                 (void *)items->type,
3982                                                 "ip header not found");
3983                         if (ipv4 && !ipv4->next_proto_id)
3984                                 ipv4->next_proto_id = IPPROTO_GRE;
3985                         else if (ipv6 && !ipv6->proto)
3986                                 ipv6->proto = IPPROTO_GRE;
3987                         break;
3988                 case RTE_FLOW_ITEM_TYPE_VOID:
3989                         break;
3990                 default:
3991                         return rte_flow_error_set(error, EINVAL,
3992                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3993                                                   (void *)items->type,
3994                                                   "unsupported item type");
3995                         break;
3996                 }
3997                 temp_size += len;
3998         }
3999         *size = temp_size;
4000         return 0;
4001 }
4002
4003 static int
4004 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4005 {
4006         struct rte_ether_hdr *eth = NULL;
4007         struct rte_vlan_hdr *vlan = NULL;
4008         struct rte_ipv6_hdr *ipv6 = NULL;
4009         struct rte_udp_hdr *udp = NULL;
4010         char *next_hdr;
4011         uint16_t proto;
4012
4013         eth = (struct rte_ether_hdr *)data;
4014         next_hdr = (char *)(eth + 1);
4015         proto = RTE_BE16(eth->ether_type);
4016
4017         /* VLAN skipping */
4018         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4019                 vlan = (struct rte_vlan_hdr *)next_hdr;
4020                 proto = RTE_BE16(vlan->eth_proto);
4021                 next_hdr += sizeof(struct rte_vlan_hdr);
4022         }
4023
4024         /* HW calculates IPv4 csum. no need to proceed */
4025         if (proto == RTE_ETHER_TYPE_IPV4)
4026                 return 0;
4027
4028         /* non IPv4/IPv6 header. not supported */
4029         if (proto != RTE_ETHER_TYPE_IPV6) {
4030                 return rte_flow_error_set(error, ENOTSUP,
4031                                           RTE_FLOW_ERROR_TYPE_ACTION,
4032                                           NULL, "Cannot offload non IPv4/IPv6");
4033         }
4034
4035         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4036
4037         /* ignore non UDP */
4038         if (ipv6->proto != IPPROTO_UDP)
4039                 return 0;
4040
4041         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4042         udp->dgram_cksum = 0;
4043
4044         return 0;
4045 }
4046
4047 /**
4048  * Convert L2 encap action to DV specification.
4049  *
4050  * @param[in] dev
4051  *   Pointer to rte_eth_dev structure.
4052  * @param[in] action
4053  *   Pointer to action structure.
4054  * @param[in, out] dev_flow
4055  *   Pointer to the mlx5_flow.
4056  * @param[in] transfer
4057  *   Mark if the flow is E-Switch flow.
4058  * @param[out] error
4059  *   Pointer to the error structure.
4060  *
4061  * @return
4062  *   0 on success, a negative errno value otherwise and rte_errno is set.
4063  */
4064 static int
4065 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4066                                const struct rte_flow_action *action,
4067                                struct mlx5_flow *dev_flow,
4068                                uint8_t transfer,
4069                                struct rte_flow_error *error)
4070 {
4071         const struct rte_flow_item *encap_data;
4072         const struct rte_flow_action_raw_encap *raw_encap_data;
4073         struct mlx5_flow_dv_encap_decap_resource res = {
4074                 .reformat_type =
4075                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4076                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4077                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4078         };
4079
4080         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4081                 raw_encap_data =
4082                         (const struct rte_flow_action_raw_encap *)action->conf;
4083                 res.size = raw_encap_data->size;
4084                 memcpy(res.buf, raw_encap_data->data, res.size);
4085         } else {
4086                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4087                         encap_data =
4088                                 ((const struct rte_flow_action_vxlan_encap *)
4089                                                 action->conf)->definition;
4090                 else
4091                         encap_data =
4092                                 ((const struct rte_flow_action_nvgre_encap *)
4093                                                 action->conf)->definition;
4094                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4095                                                &res.size, error))
4096                         return -rte_errno;
4097         }
4098         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4099                 return -rte_errno;
4100         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4101                 return rte_flow_error_set(error, EINVAL,
4102                                           RTE_FLOW_ERROR_TYPE_ACTION,
4103                                           NULL, "can't create L2 encap action");
4104         return 0;
4105 }
4106
4107 /**
4108  * Convert L2 decap action to DV specification.
4109  *
4110  * @param[in] dev
4111  *   Pointer to rte_eth_dev structure.
4112  * @param[in, out] dev_flow
4113  *   Pointer to the mlx5_flow.
4114  * @param[in] transfer
4115  *   Mark if the flow is E-Switch flow.
4116  * @param[out] error
4117  *   Pointer to the error structure.
4118  *
4119  * @return
4120  *   0 on success, a negative errno value otherwise and rte_errno is set.
4121  */
4122 static int
4123 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4124                                struct mlx5_flow *dev_flow,
4125                                uint8_t transfer,
4126                                struct rte_flow_error *error)
4127 {
4128         struct mlx5_flow_dv_encap_decap_resource res = {
4129                 .size = 0,
4130                 .reformat_type =
4131                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4132                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4133                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4134         };
4135
4136         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4137                 return rte_flow_error_set(error, EINVAL,
4138                                           RTE_FLOW_ERROR_TYPE_ACTION,
4139                                           NULL, "can't create L2 decap action");
4140         return 0;
4141 }
4142
4143 /**
4144  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4145  *
4146  * @param[in] dev
4147  *   Pointer to rte_eth_dev structure.
4148  * @param[in] action
4149  *   Pointer to action structure.
4150  * @param[in, out] dev_flow
4151  *   Pointer to the mlx5_flow.
4152  * @param[in] attr
4153  *   Pointer to the flow attributes.
4154  * @param[out] error
4155  *   Pointer to the error structure.
4156  *
4157  * @return
4158  *   0 on success, a negative errno value otherwise and rte_errno is set.
4159  */
4160 static int
4161 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4162                                 const struct rte_flow_action *action,
4163                                 struct mlx5_flow *dev_flow,
4164                                 const struct rte_flow_attr *attr,
4165                                 struct rte_flow_error *error)
4166 {
4167         const struct rte_flow_action_raw_encap *encap_data;
4168         struct mlx5_flow_dv_encap_decap_resource res;
4169
4170         memset(&res, 0, sizeof(res));
4171         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4172         res.size = encap_data->size;
4173         memcpy(res.buf, encap_data->data, res.size);
4174         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4175                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4176                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4177         if (attr->transfer)
4178                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4179         else
4180                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4181                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4182         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4183                 return rte_flow_error_set(error, EINVAL,
4184                                           RTE_FLOW_ERROR_TYPE_ACTION,
4185                                           NULL, "can't create encap action");
4186         return 0;
4187 }
4188
4189 /**
4190  * Create action push VLAN.
4191  *
4192  * @param[in] dev
4193  *   Pointer to rte_eth_dev structure.
4194  * @param[in] attr
4195  *   Pointer to the flow attributes.
4196  * @param[in] vlan
4197  *   Pointer to the vlan to push to the Ethernet header.
4198  * @param[in, out] dev_flow
4199  *   Pointer to the mlx5_flow.
4200  * @param[out] error
4201  *   Pointer to the error structure.
4202  *
4203  * @return
4204  *   0 on success, a negative errno value otherwise and rte_errno is set.
4205  */
4206 static int
4207 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4208                                 const struct rte_flow_attr *attr,
4209                                 const struct rte_vlan_hdr *vlan,
4210                                 struct mlx5_flow *dev_flow,
4211                                 struct rte_flow_error *error)
4212 {
4213         struct mlx5_flow_dv_push_vlan_action_resource res;
4214
4215         memset(&res, 0, sizeof(res));
4216         res.vlan_tag =
4217                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4218                                  vlan->vlan_tci);
4219         if (attr->transfer)
4220                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4221         else
4222                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4223                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4224         return flow_dv_push_vlan_action_resource_register
4225                                             (dev, &res, dev_flow, error);
4226 }
4227
4228 /**
4229  * Validate the modify-header actions.
4230  *
4231  * @param[in] action_flags
4232  *   Holds the actions detected until now.
4233  * @param[in] action
4234  *   Pointer to the modify action.
4235  * @param[out] error
4236  *   Pointer to error structure.
4237  *
4238  * @return
4239  *   0 on success, a negative errno value otherwise and rte_errno is set.
4240  */
4241 static int
4242 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4243                                    const struct rte_flow_action *action,
4244                                    struct rte_flow_error *error)
4245 {
4246         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4247                 return rte_flow_error_set(error, EINVAL,
4248                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4249                                           NULL, "action configuration not set");
4250         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4251                 return rte_flow_error_set(error, EINVAL,
4252                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4253                                           "can't have encap action before"
4254                                           " modify action");
4255         return 0;
4256 }
4257
4258 /**
4259  * Validate the modify-header MAC address actions.
4260  *
4261  * @param[in] action_flags
4262  *   Holds the actions detected until now.
4263  * @param[in] action
4264  *   Pointer to the modify action.
4265  * @param[in] item_flags
4266  *   Holds the items detected.
4267  * @param[out] error
4268  *   Pointer to error structure.
4269  *
4270  * @return
4271  *   0 on success, a negative errno value otherwise and rte_errno is set.
4272  */
4273 static int
4274 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4275                                    const struct rte_flow_action *action,
4276                                    const uint64_t item_flags,
4277                                    struct rte_flow_error *error)
4278 {
4279         int ret = 0;
4280
4281         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4282         if (!ret) {
4283                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4284                         return rte_flow_error_set(error, EINVAL,
4285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4286                                                   NULL,
4287                                                   "no L2 item in pattern");
4288         }
4289         return ret;
4290 }
4291
4292 /**
4293  * Validate the modify-header IPv4 address actions.
4294  *
4295  * @param[in] action_flags
4296  *   Holds the actions detected until now.
4297  * @param[in] action
4298  *   Pointer to the modify action.
4299  * @param[in] item_flags
4300  *   Holds the items detected.
4301  * @param[out] error
4302  *   Pointer to error structure.
4303  *
4304  * @return
4305  *   0 on success, a negative errno value otherwise and rte_errno is set.
4306  */
4307 static int
4308 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4309                                     const struct rte_flow_action *action,
4310                                     const uint64_t item_flags,
4311                                     struct rte_flow_error *error)
4312 {
4313         int ret = 0;
4314         uint64_t layer;
4315
4316         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4317         if (!ret) {
4318                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4319                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4320                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4321                 if (!(item_flags & layer))
4322                         return rte_flow_error_set(error, EINVAL,
4323                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4324                                                   NULL,
4325                                                   "no ipv4 item in pattern");
4326         }
4327         return ret;
4328 }
4329
4330 /**
4331  * Validate the modify-header IPv6 address actions.
4332  *
4333  * @param[in] action_flags
4334  *   Holds the actions detected until now.
4335  * @param[in] action
4336  *   Pointer to the modify action.
4337  * @param[in] item_flags
4338  *   Holds the items detected.
4339  * @param[out] error
4340  *   Pointer to error structure.
4341  *
4342  * @return
4343  *   0 on success, a negative errno value otherwise and rte_errno is set.
4344  */
4345 static int
4346 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4347                                     const struct rte_flow_action *action,
4348                                     const uint64_t item_flags,
4349                                     struct rte_flow_error *error)
4350 {
4351         int ret = 0;
4352         uint64_t layer;
4353
4354         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4355         if (!ret) {
4356                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4357                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4358                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4359                 if (!(item_flags & layer))
4360                         return rte_flow_error_set(error, EINVAL,
4361                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4362                                                   NULL,
4363                                                   "no ipv6 item in pattern");
4364         }
4365         return ret;
4366 }
4367
4368 /**
4369  * Validate the modify-header TP actions.
4370  *
4371  * @param[in] action_flags
4372  *   Holds the actions detected until now.
4373  * @param[in] action
4374  *   Pointer to the modify action.
4375  * @param[in] item_flags
4376  *   Holds the items detected.
4377  * @param[out] error
4378  *   Pointer to error structure.
4379  *
4380  * @return
4381  *   0 on success, a negative errno value otherwise and rte_errno is set.
4382  */
4383 static int
4384 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4385                                   const struct rte_flow_action *action,
4386                                   const uint64_t item_flags,
4387                                   struct rte_flow_error *error)
4388 {
4389         int ret = 0;
4390         uint64_t layer;
4391
4392         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4393         if (!ret) {
4394                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4395                                  MLX5_FLOW_LAYER_INNER_L4 :
4396                                  MLX5_FLOW_LAYER_OUTER_L4;
4397                 if (!(item_flags & layer))
4398                         return rte_flow_error_set(error, EINVAL,
4399                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4400                                                   NULL, "no transport layer "
4401                                                   "in pattern");
4402         }
4403         return ret;
4404 }
4405
4406 /**
4407  * Validate the modify-header actions of increment/decrement
4408  * TCP Sequence-number.
4409  *
4410  * @param[in] action_flags
4411  *   Holds the actions detected until now.
4412  * @param[in] action
4413  *   Pointer to the modify action.
4414  * @param[in] item_flags
4415  *   Holds the items detected.
4416  * @param[out] error
4417  *   Pointer to error structure.
4418  *
4419  * @return
4420  *   0 on success, a negative errno value otherwise and rte_errno is set.
4421  */
4422 static int
4423 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4424                                        const struct rte_flow_action *action,
4425                                        const uint64_t item_flags,
4426                                        struct rte_flow_error *error)
4427 {
4428         int ret = 0;
4429         uint64_t layer;
4430
4431         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4432         if (!ret) {
4433                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4434                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4435                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4436                 if (!(item_flags & layer))
4437                         return rte_flow_error_set(error, EINVAL,
4438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4439                                                   NULL, "no TCP item in"
4440                                                   " pattern");
4441                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4442                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4443                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4444                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4445                         return rte_flow_error_set(error, EINVAL,
4446                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4447                                                   NULL,
4448                                                   "cannot decrease and increase"
4449                                                   " TCP sequence number"
4450                                                   " at the same time");
4451         }
4452         return ret;
4453 }
4454
4455 /**
4456  * Validate the modify-header actions of increment/decrement
4457  * TCP Acknowledgment number.
4458  *
4459  * @param[in] action_flags
4460  *   Holds the actions detected until now.
4461  * @param[in] action
4462  *   Pointer to the modify action.
4463  * @param[in] item_flags
4464  *   Holds the items detected.
4465  * @param[out] error
4466  *   Pointer to error structure.
4467  *
4468  * @return
4469  *   0 on success, a negative errno value otherwise and rte_errno is set.
4470  */
4471 static int
4472 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4473                                        const struct rte_flow_action *action,
4474                                        const uint64_t item_flags,
4475                                        struct rte_flow_error *error)
4476 {
4477         int ret = 0;
4478         uint64_t layer;
4479
4480         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4481         if (!ret) {
4482                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4483                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4484                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4485                 if (!(item_flags & layer))
4486                         return rte_flow_error_set(error, EINVAL,
4487                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4488                                                   NULL, "no TCP item in"
4489                                                   " pattern");
4490                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4491                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4492                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4493                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4494                         return rte_flow_error_set(error, EINVAL,
4495                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4496                                                   NULL,
4497                                                   "cannot decrease and increase"
4498                                                   " TCP acknowledgment number"
4499                                                   " at the same time");
4500         }
4501         return ret;
4502 }
4503
4504 /**
4505  * Validate the modify-header TTL actions.
4506  *
4507  * @param[in] action_flags
4508  *   Holds the actions detected until now.
4509  * @param[in] action
4510  *   Pointer to the modify action.
4511  * @param[in] item_flags
4512  *   Holds the items detected.
4513  * @param[out] error
4514  *   Pointer to error structure.
4515  *
4516  * @return
4517  *   0 on success, a negative errno value otherwise and rte_errno is set.
4518  */
4519 static int
4520 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4521                                    const struct rte_flow_action *action,
4522                                    const uint64_t item_flags,
4523                                    struct rte_flow_error *error)
4524 {
4525         int ret = 0;
4526         uint64_t layer;
4527
4528         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4529         if (!ret) {
4530                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4531                                  MLX5_FLOW_LAYER_INNER_L3 :
4532                                  MLX5_FLOW_LAYER_OUTER_L3;
4533                 if (!(item_flags & layer))
4534                         return rte_flow_error_set(error, EINVAL,
4535                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4536                                                   NULL,
4537                                                   "no IP protocol in pattern");
4538         }
4539         return ret;
4540 }
4541
4542 /**
4543  * Validate the generic modify field actions.
4544  * @param[in] dev
4545  *   Pointer to the rte_eth_dev structure.
4546  * @param[in] action_flags
4547  *   Holds the actions detected until now.
4548  * @param[in] action
4549  *   Pointer to the modify action.
4550  * @param[in] attr
4551  *   Pointer to the flow attributes.
4552  * @param[out] error
4553  *   Pointer to error structure.
4554  *
4555  * @return
4556  *   Number of header fields to modify (0 or more) on success,
4557  *   a negative errno value otherwise and rte_errno is set.
4558  */
4559 static int
4560 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4561                                    const uint64_t action_flags,
4562                                    const struct rte_flow_action *action,
4563                                    const struct rte_flow_attr *attr,
4564                                    struct rte_flow_error *error)
4565 {
4566         int ret = 0;
4567         struct mlx5_priv *priv = dev->data->dev_private;
4568         struct mlx5_dev_config *config = &priv->config;
4569         const struct rte_flow_action_modify_field *action_modify_field =
4570                 action->conf;
4571         uint32_t dst_width =
4572                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4573         uint32_t src_width =
4574                 mlx5_flow_item_field_width(action_modify_field->src.field);
4575
4576         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4577         if (ret)
4578                 return ret;
4579
4580         if (action_modify_field->width == 0)
4581                 return rte_flow_error_set(error, EINVAL,
4582                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4583                                 "no bits are requested to be modified");
4584         else if (action_modify_field->width > dst_width ||
4585                  action_modify_field->width > src_width)
4586                 return rte_flow_error_set(error, EINVAL,
4587                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4588                                 "cannot modify more bits than"
4589                                 " the width of a field");
4590         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4591             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4592                 if ((action_modify_field->dst.offset +
4593                      action_modify_field->width > dst_width) ||
4594                     (action_modify_field->dst.offset % 32))
4595                         return rte_flow_error_set(error, EINVAL,
4596                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4597                                         "destination offset is too big"
4598                                         " or not aligned to 4 bytes");
4599                 if (action_modify_field->dst.level &&
4600                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4601                         return rte_flow_error_set(error, ENOTSUP,
4602                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4603                                         "inner header fields modification"
4604                                         " is not supported");
4605         }
4606         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4607             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4608                 if (!attr->transfer && !attr->group)
4609                         return rte_flow_error_set(error, ENOTSUP,
4610                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4611                                         "modify field action is not"
4612                                         " supported for group 0");
4613                 if ((action_modify_field->src.offset +
4614                      action_modify_field->width > src_width) ||
4615                     (action_modify_field->src.offset % 32))
4616                         return rte_flow_error_set(error, EINVAL,
4617                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4618                                         "source offset is too big"
4619                                         " or not aligned to 4 bytes");
4620                 if (action_modify_field->src.level &&
4621                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4622                         return rte_flow_error_set(error, ENOTSUP,
4623                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4624                                         "inner header fields modification"
4625                                         " is not supported");
4626         }
4627         if (action_modify_field->dst.field ==
4628             action_modify_field->src.field)
4629                 return rte_flow_error_set(error, EINVAL,
4630                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4631                                 "source and destination fields"
4632                                 " cannot be the same");
4633         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4634             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4635                 return rte_flow_error_set(error, EINVAL,
4636                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4637                                 "immediate value or a pointer to it"
4638                                 " cannot be used as a destination");
4639         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4640             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4641                 return rte_flow_error_set(error, ENOTSUP,
4642                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4643                                 "modifications of an arbitrary"
4644                                 " place in a packet is not supported");
4645         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4646             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4647                 return rte_flow_error_set(error, ENOTSUP,
4648                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4649                                 "modifications of the 802.1Q Tag"
4650                                 " Identifier is not supported");
4651         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4652             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4653                 return rte_flow_error_set(error, ENOTSUP,
4654                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4655                                 "modifications of the VXLAN Network"
4656                                 " Identifier is not supported");
4657         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4658             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4659                 return rte_flow_error_set(error, ENOTSUP,
4660                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4661                                 "modifications of the GENEVE Network"
4662                                 " Identifier is not supported");
4663         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4664             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4665             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4666             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4667                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4668                     !mlx5_flow_ext_mreg_supported(dev))
4669                         return rte_flow_error_set(error, ENOTSUP,
4670                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4671                                         "cannot modify mark or metadata without"
4672                                         " extended metadata register support");
4673         }
4674         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4675                 return rte_flow_error_set(error, ENOTSUP,
4676                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4677                                 "add and sub operations"
4678                                 " are not supported");
4679         return (action_modify_field->width / 32) +
4680                !!(action_modify_field->width % 32);
4681 }
4682
4683 /**
4684  * Validate jump action.
4685  *
4686  * @param[in] action
4687  *   Pointer to the jump action.
4688  * @param[in] action_flags
4689  *   Holds the actions detected until now.
4690  * @param[in] attributes
4691  *   Pointer to flow attributes
4692  * @param[in] external
4693  *   Action belongs to flow rule created by request external to PMD.
4694  * @param[out] error
4695  *   Pointer to error structure.
4696  *
4697  * @return
4698  *   0 on success, a negative errno value otherwise and rte_errno is set.
4699  */
4700 static int
4701 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4702                              const struct mlx5_flow_tunnel *tunnel,
4703                              const struct rte_flow_action *action,
4704                              uint64_t action_flags,
4705                              const struct rte_flow_attr *attributes,
4706                              bool external, struct rte_flow_error *error)
4707 {
4708         uint32_t target_group, table;
4709         int ret = 0;
4710         struct flow_grp_info grp_info = {
4711                 .external = !!external,
4712                 .transfer = !!attributes->transfer,
4713                 .fdb_def_rule = 1,
4714                 .std_tbl_fix = 0
4715         };
4716         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4717                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4718                 return rte_flow_error_set(error, EINVAL,
4719                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4720                                           "can't have 2 fate actions in"
4721                                           " same flow");
4722         if (action_flags & MLX5_FLOW_ACTION_METER)
4723                 return rte_flow_error_set(error, ENOTSUP,
4724                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4725                                           "jump with meter not support");
4726         if (!action->conf)
4727                 return rte_flow_error_set(error, EINVAL,
4728                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4729                                           NULL, "action configuration not set");
4730         target_group =
4731                 ((const struct rte_flow_action_jump *)action->conf)->group;
4732         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4733                                        &grp_info, error);
4734         if (ret)
4735                 return ret;
4736         if (attributes->group == target_group &&
4737             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4738                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4739                 return rte_flow_error_set(error, EINVAL,
4740                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4741                                           "target group must be other than"
4742                                           " the current flow group");
4743         return 0;
4744 }
4745
4746 /*
4747  * Validate the port_id action.
4748  *
4749  * @param[in] dev
4750  *   Pointer to rte_eth_dev structure.
4751  * @param[in] action_flags
4752  *   Bit-fields that holds the actions detected until now.
4753  * @param[in] action
4754  *   Port_id RTE action structure.
4755  * @param[in] attr
4756  *   Attributes of flow that includes this action.
4757  * @param[out] error
4758  *   Pointer to error structure.
4759  *
4760  * @return
4761  *   0 on success, a negative errno value otherwise and rte_errno is set.
4762  */
4763 static int
4764 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4765                                 uint64_t action_flags,
4766                                 const struct rte_flow_action *action,
4767                                 const struct rte_flow_attr *attr,
4768                                 struct rte_flow_error *error)
4769 {
4770         const struct rte_flow_action_port_id *port_id;
4771         struct mlx5_priv *act_priv;
4772         struct mlx5_priv *dev_priv;
4773         uint16_t port;
4774
4775         if (!attr->transfer)
4776                 return rte_flow_error_set(error, ENOTSUP,
4777                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4778                                           NULL,
4779                                           "port id action is valid in transfer"
4780                                           " mode only");
4781         if (!action || !action->conf)
4782                 return rte_flow_error_set(error, ENOTSUP,
4783                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4784                                           NULL,
4785                                           "port id action parameters must be"
4786                                           " specified");
4787         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4788                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4789                 return rte_flow_error_set(error, EINVAL,
4790                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4791                                           "can have only one fate actions in"
4792                                           " a flow");
4793         dev_priv = mlx5_dev_to_eswitch_info(dev);
4794         if (!dev_priv)
4795                 return rte_flow_error_set(error, rte_errno,
4796                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4797                                           NULL,
4798                                           "failed to obtain E-Switch info");
4799         port_id = action->conf;
4800         port = port_id->original ? dev->data->port_id : port_id->id;
4801         act_priv = mlx5_port_to_eswitch_info(port, false);
4802         if (!act_priv)
4803                 return rte_flow_error_set
4804                                 (error, rte_errno,
4805                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4806                                  "failed to obtain E-Switch port id for port");
4807         if (act_priv->domain_id != dev_priv->domain_id)
4808                 return rte_flow_error_set
4809                                 (error, EINVAL,
4810                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4811                                  "port does not belong to"
4812                                  " E-Switch being configured");
4813         return 0;
4814 }
4815
4816 /**
4817  * Get the maximum number of modify header actions.
4818  *
4819  * @param dev
4820  *   Pointer to rte_eth_dev structure.
4821  * @param flags
4822  *   Flags bits to check if root level.
4823  *
4824  * @return
4825  *   Max number of modify header actions device can support.
4826  */
4827 static inline unsigned int
4828 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4829                               uint64_t flags)
4830 {
4831         /*
4832          * There's no way to directly query the max capacity from FW.
4833          * The maximal value on root table should be assumed to be supported.
4834          */
4835         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4836                 return MLX5_MAX_MODIFY_NUM;
4837         else
4838                 return MLX5_ROOT_TBL_MODIFY_NUM;
4839 }
4840
4841 /**
4842  * Validate the meter action.
4843  *
4844  * @param[in] dev
4845  *   Pointer to rte_eth_dev structure.
4846  * @param[in] action_flags
4847  *   Bit-fields that holds the actions detected until now.
4848  * @param[in] action
4849  *   Pointer to the meter action.
4850  * @param[in] attr
4851  *   Attributes of flow that includes this action.
4852  * @param[out] error
4853  *   Pointer to error structure.
4854  *
4855  * @return
4856  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4857  */
4858 static int
4859 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4860                                 uint64_t action_flags,
4861                                 const struct rte_flow_action *action,
4862                                 const struct rte_flow_attr *attr,
4863                                 struct rte_flow_error *error)
4864 {
4865         struct mlx5_priv *priv = dev->data->dev_private;
4866         const struct rte_flow_action_meter *am = action->conf;
4867         struct mlx5_flow_meter *fm;
4868
4869         if (!am)
4870                 return rte_flow_error_set(error, EINVAL,
4871                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4872                                           "meter action conf is NULL");
4873
4874         if (action_flags & MLX5_FLOW_ACTION_METER)
4875                 return rte_flow_error_set(error, ENOTSUP,
4876                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4877                                           "meter chaining not support");
4878         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4879                 return rte_flow_error_set(error, ENOTSUP,
4880                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4881                                           "meter with jump not support");
4882         if (!priv->mtr_en)
4883                 return rte_flow_error_set(error, ENOTSUP,
4884                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4885                                           NULL,
4886                                           "meter action not supported");
4887         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4888         if (!fm)
4889                 return rte_flow_error_set(error, EINVAL,
4890                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4891                                           "Meter not found");
4892         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4893               (!fm->ingress && !attr->ingress && attr->egress) ||
4894               (!fm->egress && !attr->egress && attr->ingress))))
4895                 return rte_flow_error_set(error, EINVAL,
4896                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4897                                           "Flow attributes are either invalid "
4898                                           "or have a conflict with current "
4899                                           "meter attributes");
4900         return 0;
4901 }
4902
4903 /**
4904  * Validate the age action.
4905  *
4906  * @param[in] action_flags
4907  *   Holds the actions detected until now.
4908  * @param[in] action
4909  *   Pointer to the age action.
4910  * @param[in] dev
4911  *   Pointer to the Ethernet device structure.
4912  * @param[out] error
4913  *   Pointer to error structure.
4914  *
4915  * @return
4916  *   0 on success, a negative errno value otherwise and rte_errno is set.
4917  */
4918 static int
4919 flow_dv_validate_action_age(uint64_t action_flags,
4920                             const struct rte_flow_action *action,
4921                             struct rte_eth_dev *dev,
4922                             struct rte_flow_error *error)
4923 {
4924         struct mlx5_priv *priv = dev->data->dev_private;
4925         const struct rte_flow_action_age *age = action->conf;
4926
4927         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4928             !priv->sh->aso_age_mng))
4929                 return rte_flow_error_set(error, ENOTSUP,
4930                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4931                                           NULL,
4932                                           "age action not supported");
4933         if (!(action->conf))
4934                 return rte_flow_error_set(error, EINVAL,
4935                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4936                                           "configuration cannot be null");
4937         if (!(age->timeout))
4938                 return rte_flow_error_set(error, EINVAL,
4939                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4940                                           "invalid timeout value 0");
4941         if (action_flags & MLX5_FLOW_ACTION_AGE)
4942                 return rte_flow_error_set(error, EINVAL,
4943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4944                                           "duplicate age actions set");
4945         return 0;
4946 }
4947
4948 /**
4949  * Validate the modify-header IPv4 DSCP actions.
4950  *
4951  * @param[in] action_flags
4952  *   Holds the actions detected until now.
4953  * @param[in] action
4954  *   Pointer to the modify action.
4955  * @param[in] item_flags
4956  *   Holds the items detected.
4957  * @param[out] error
4958  *   Pointer to error structure.
4959  *
4960  * @return
4961  *   0 on success, a negative errno value otherwise and rte_errno is set.
4962  */
4963 static int
4964 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4965                                          const struct rte_flow_action *action,
4966                                          const uint64_t item_flags,
4967                                          struct rte_flow_error *error)
4968 {
4969         int ret = 0;
4970
4971         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4972         if (!ret) {
4973                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4974                         return rte_flow_error_set(error, EINVAL,
4975                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4976                                                   NULL,
4977                                                   "no ipv4 item in pattern");
4978         }
4979         return ret;
4980 }
4981
4982 /**
4983  * Validate the modify-header IPv6 DSCP actions.
4984  *
4985  * @param[in] action_flags
4986  *   Holds the actions detected until now.
4987  * @param[in] action
4988  *   Pointer to the modify action.
4989  * @param[in] item_flags
4990  *   Holds the items detected.
4991  * @param[out] error
4992  *   Pointer to error structure.
4993  *
4994  * @return
4995  *   0 on success, a negative errno value otherwise and rte_errno is set.
4996  */
4997 static int
4998 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4999                                          const struct rte_flow_action *action,
5000                                          const uint64_t item_flags,
5001                                          struct rte_flow_error *error)
5002 {
5003         int ret = 0;
5004
5005         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5006         if (!ret) {
5007                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5008                         return rte_flow_error_set(error, EINVAL,
5009                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5010                                                   NULL,
5011                                                   "no ipv6 item in pattern");
5012         }
5013         return ret;
5014 }
5015
5016 /**
5017  * Match modify-header resource.
5018  *
5019  * @param list
5020  *   Pointer to the hash list.
5021  * @param entry
5022  *   Pointer to exist resource entry object.
5023  * @param key
5024  *   Key of the new entry.
5025  * @param ctx
5026  *   Pointer to new modify-header resource.
5027  *
5028  * @return
5029  *   0 on matching, non-zero otherwise.
5030  */
5031 int
5032 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5033                         struct mlx5_hlist_entry *entry,
5034                         uint64_t key __rte_unused, void *cb_ctx)
5035 {
5036         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5037         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5038         struct mlx5_flow_dv_modify_hdr_resource *resource =
5039                         container_of(entry, typeof(*resource), entry);
5040         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5041
5042         key_len += ref->actions_num * sizeof(ref->actions[0]);
5043         return ref->actions_num != resource->actions_num ||
5044                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5045 }
5046
5047 struct mlx5_hlist_entry *
5048 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5049                          void *cb_ctx)
5050 {
5051         struct mlx5_dev_ctx_shared *sh = list->ctx;
5052         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5053         struct mlx5dv_dr_domain *ns;
5054         struct mlx5_flow_dv_modify_hdr_resource *entry;
5055         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5056         int ret;
5057         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5058         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5059
5060         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5061                             SOCKET_ID_ANY);
5062         if (!entry) {
5063                 rte_flow_error_set(ctx->error, ENOMEM,
5064                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5065                                    "cannot allocate resource memory");
5066                 return NULL;
5067         }
5068         rte_memcpy(&entry->ft_type,
5069                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5070                    key_len + data_len);
5071         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5072                 ns = sh->fdb_domain;
5073         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5074                 ns = sh->tx_domain;
5075         else
5076                 ns = sh->rx_domain;
5077         ret = mlx5_flow_os_create_flow_action_modify_header
5078                                         (sh->ctx, ns, entry,
5079                                          data_len, &entry->action);
5080         if (ret) {
5081                 mlx5_free(entry);
5082                 rte_flow_error_set(ctx->error, ENOMEM,
5083                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5084                                    NULL, "cannot create modification action");
5085                 return NULL;
5086         }
5087         return &entry->entry;
5088 }
5089
5090 /**
5091  * Validate the sample action.
5092  *
5093  * @param[in, out] action_flags
5094  *   Holds the actions detected until now.
5095  * @param[in] action
5096  *   Pointer to the sample action.
5097  * @param[in] dev
5098  *   Pointer to the Ethernet device structure.
5099  * @param[in] attr
5100  *   Attributes of flow that includes this action.
5101  * @param[in] item_flags
5102  *   Holds the items detected.
5103  * @param[in] rss
5104  *   Pointer to the RSS action.
5105  * @param[out] sample_rss
5106  *   Pointer to the RSS action in sample action list.
5107  * @param[out] count
5108  *   Pointer to the COUNT action in sample action list.
5109  * @param[out] fdb_mirror_limit
5110  *   Pointer to the FDB mirror limitation flag.
5111  * @param[out] error
5112  *   Pointer to error structure.
5113  *
5114  * @return
5115  *   0 on success, a negative errno value otherwise and rte_errno is set.
5116  */
5117 static int
5118 flow_dv_validate_action_sample(uint64_t *action_flags,
5119                                const struct rte_flow_action *action,
5120                                struct rte_eth_dev *dev,
5121                                const struct rte_flow_attr *attr,
5122                                uint64_t item_flags,
5123                                const struct rte_flow_action_rss *rss,
5124                                const struct rte_flow_action_rss **sample_rss,
5125                                const struct rte_flow_action_count **count,
5126                                int *fdb_mirror_limit,
5127                                struct rte_flow_error *error)
5128 {
5129         struct mlx5_priv *priv = dev->data->dev_private;
5130         struct mlx5_dev_config *dev_conf = &priv->config;
5131         const struct rte_flow_action_sample *sample = action->conf;
5132         const struct rte_flow_action *act;
5133         uint64_t sub_action_flags = 0;
5134         uint16_t queue_index = 0xFFFF;
5135         int actions_n = 0;
5136         int ret;
5137
5138         if (!sample)
5139                 return rte_flow_error_set(error, EINVAL,
5140                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5141                                           "configuration cannot be NULL");
5142         if (sample->ratio == 0)
5143                 return rte_flow_error_set(error, EINVAL,
5144                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5145                                           "ratio value starts from 1");
5146         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5147                 return rte_flow_error_set(error, ENOTSUP,
5148                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5149                                           NULL,
5150                                           "sample action not supported");
5151         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5152                 return rte_flow_error_set(error, EINVAL,
5153                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5154                                           "Multiple sample actions not "
5155                                           "supported");
5156         if (*action_flags & MLX5_FLOW_ACTION_METER)
5157                 return rte_flow_error_set(error, EINVAL,
5158                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5159                                           "wrong action order, meter should "
5160                                           "be after sample action");
5161         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5162                 return rte_flow_error_set(error, EINVAL,
5163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5164                                           "wrong action order, jump should "
5165                                           "be after sample action");
5166         act = sample->actions;
5167         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5168                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5169                         return rte_flow_error_set(error, ENOTSUP,
5170                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5171                                                   act, "too many actions");
5172                 switch (act->type) {
5173                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5174                         ret = mlx5_flow_validate_action_queue(act,
5175                                                               sub_action_flags,
5176                                                               dev,
5177                                                               attr, error);
5178                         if (ret < 0)
5179                                 return ret;
5180                         queue_index = ((const struct rte_flow_action_queue *)
5181                                                         (act->conf))->index;
5182                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5183                         ++actions_n;
5184                         break;
5185                 case RTE_FLOW_ACTION_TYPE_RSS:
5186                         *sample_rss = act->conf;
5187                         ret = mlx5_flow_validate_action_rss(act,
5188                                                             sub_action_flags,
5189                                                             dev, attr,
5190                                                             item_flags,
5191                                                             error);
5192                         if (ret < 0)
5193                                 return ret;
5194                         if (rss && *sample_rss &&
5195                             ((*sample_rss)->level != rss->level ||
5196                             (*sample_rss)->types != rss->types))
5197                                 return rte_flow_error_set(error, ENOTSUP,
5198                                         RTE_FLOW_ERROR_TYPE_ACTION,
5199                                         NULL,
5200                                         "Can't use the different RSS types "
5201                                         "or level in the same flow");
5202                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5203                                 queue_index = (*sample_rss)->queue[0];
5204                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5205                         ++actions_n;
5206                         break;
5207                 case RTE_FLOW_ACTION_TYPE_MARK:
5208                         ret = flow_dv_validate_action_mark(dev, act,
5209                                                            sub_action_flags,
5210                                                            attr, error);
5211                         if (ret < 0)
5212                                 return ret;
5213                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5214                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5215                                                 MLX5_FLOW_ACTION_MARK_EXT;
5216                         else
5217                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5218                         ++actions_n;
5219                         break;
5220                 case RTE_FLOW_ACTION_TYPE_COUNT:
5221                         ret = flow_dv_validate_action_count
5222                                 (dev, act,
5223                                  *action_flags | sub_action_flags,
5224                                  error);
5225                         if (ret < 0)
5226                                 return ret;
5227                         *count = act->conf;
5228                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5229                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5230                         ++actions_n;
5231                         break;
5232                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5233                         ret = flow_dv_validate_action_port_id(dev,
5234                                                               sub_action_flags,
5235                                                               act,
5236                                                               attr,
5237                                                               error);
5238                         if (ret)
5239                                 return ret;
5240                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5241                         ++actions_n;
5242                         break;
5243                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5244                         ret = flow_dv_validate_action_raw_encap_decap
5245                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5246                                  &actions_n, action, item_flags, error);
5247                         if (ret < 0)
5248                                 return ret;
5249                         ++actions_n;
5250                         break;
5251                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5252                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5253                         ret = flow_dv_validate_action_l2_encap(dev,
5254                                                                sub_action_flags,
5255                                                                act, attr,
5256                                                                error);
5257                         if (ret < 0)
5258                                 return ret;
5259                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5260                         ++actions_n;
5261                         break;
5262                 default:
5263                         return rte_flow_error_set(error, ENOTSUP,
5264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5265                                                   NULL,
5266                                                   "Doesn't support optional "
5267                                                   "action");
5268                 }
5269         }
5270         if (attr->ingress && !attr->transfer) {
5271                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5272                                           MLX5_FLOW_ACTION_RSS)))
5273                         return rte_flow_error_set(error, EINVAL,
5274                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5275                                                   NULL,
5276                                                   "Ingress must has a dest "
5277                                                   "QUEUE for Sample");
5278         } else if (attr->egress && !attr->transfer) {
5279                 return rte_flow_error_set(error, ENOTSUP,
5280                                           RTE_FLOW_ERROR_TYPE_ACTION,
5281                                           NULL,
5282                                           "Sample Only support Ingress "
5283                                           "or E-Switch");
5284         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5285                 MLX5_ASSERT(attr->transfer);
5286                 if (sample->ratio > 1)
5287                         return rte_flow_error_set(error, ENOTSUP,
5288                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5289                                                   NULL,
5290                                                   "E-Switch doesn't support "
5291                                                   "any optional action "
5292                                                   "for sampling");
5293                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5294                         return rte_flow_error_set(error, ENOTSUP,
5295                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5296                                                   NULL,
5297                                                   "unsupported action QUEUE");
5298                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5299                         return rte_flow_error_set(error, ENOTSUP,
5300                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5301                                                   NULL,
5302                                                   "unsupported action QUEUE");
5303                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5304                         return rte_flow_error_set(error, EINVAL,
5305                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5306                                                   NULL,
5307                                                   "E-Switch must has a dest "
5308                                                   "port for mirroring");
5309                 if (!priv->config.hca_attr.reg_c_preserve &&
5310                      priv->representor_id != -1)
5311                         *fdb_mirror_limit = 1;
5312         }
5313         /* Continue validation for Xcap actions.*/
5314         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5315             (queue_index == 0xFFFF ||
5316              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5317                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5318                      MLX5_FLOW_XCAP_ACTIONS)
5319                         return rte_flow_error_set(error, ENOTSUP,
5320                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5321                                                   NULL, "encap and decap "
5322                                                   "combination aren't "
5323                                                   "supported");
5324                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5325                                                         MLX5_FLOW_ACTION_ENCAP))
5326                         return rte_flow_error_set(error, ENOTSUP,
5327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5328                                                   NULL, "encap is not supported"
5329                                                   " for ingress traffic");
5330         }
5331         return 0;
5332 }
5333
5334 /**
5335  * Find existing modify-header resource or create and register a new one.
5336  *
5337  * @param dev[in, out]
5338  *   Pointer to rte_eth_dev structure.
5339  * @param[in, out] resource
5340  *   Pointer to modify-header resource.
5341  * @parm[in, out] dev_flow
5342  *   Pointer to the dev_flow.
5343  * @param[out] error
5344  *   pointer to error structure.
5345  *
5346  * @return
5347  *   0 on success otherwise -errno and errno is set.
5348  */
5349 static int
5350 flow_dv_modify_hdr_resource_register
5351                         (struct rte_eth_dev *dev,
5352                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5353                          struct mlx5_flow *dev_flow,
5354                          struct rte_flow_error *error)
5355 {
5356         struct mlx5_priv *priv = dev->data->dev_private;
5357         struct mlx5_dev_ctx_shared *sh = priv->sh;
5358         uint32_t key_len = sizeof(*resource) -
5359                            offsetof(typeof(*resource), ft_type) +
5360                            resource->actions_num * sizeof(resource->actions[0]);
5361         struct mlx5_hlist_entry *entry;
5362         struct mlx5_flow_cb_ctx ctx = {
5363                 .error = error,
5364                 .data = resource,
5365         };
5366         uint64_t key64;
5367
5368         resource->flags = dev_flow->dv.group ? 0 :
5369                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5370         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5371                                     resource->flags))
5372                 return rte_flow_error_set(error, EOVERFLOW,
5373                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5374                                           "too many modify header items");
5375         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5376         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5377         if (!entry)
5378                 return -rte_errno;
5379         resource = container_of(entry, typeof(*resource), entry);
5380         dev_flow->handle->dvh.modify_hdr = resource;
5381         return 0;
5382 }
5383
5384 /**
5385  * Get DV flow counter by index.
5386  *
5387  * @param[in] dev
5388  *   Pointer to the Ethernet device structure.
5389  * @param[in] idx
5390  *   mlx5 flow counter index in the container.
5391  * @param[out] ppool
5392  *   mlx5 flow counter pool in the container,
5393  *
5394  * @return
5395  *   Pointer to the counter, NULL otherwise.
5396  */
5397 static struct mlx5_flow_counter *
5398 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5399                            uint32_t idx,
5400                            struct mlx5_flow_counter_pool **ppool)
5401 {
5402         struct mlx5_priv *priv = dev->data->dev_private;
5403         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5404         struct mlx5_flow_counter_pool *pool;
5405
5406         /* Decrease to original index and clear shared bit. */
5407         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5408         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5409         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5410         MLX5_ASSERT(pool);
5411         if (ppool)
5412                 *ppool = pool;
5413         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5414 }
5415
5416 /**
5417  * Check the devx counter belongs to the pool.
5418  *
5419  * @param[in] pool
5420  *   Pointer to the counter pool.
5421  * @param[in] id
5422  *   The counter devx ID.
5423  *
5424  * @return
5425  *   True if counter belongs to the pool, false otherwise.
5426  */
5427 static bool
5428 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5429 {
5430         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5431                    MLX5_COUNTERS_PER_POOL;
5432
5433         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5434                 return true;
5435         return false;
5436 }
5437
5438 /**
5439  * Get a pool by devx counter ID.
5440  *
5441  * @param[in] cmng
5442  *   Pointer to the counter management.
5443  * @param[in] id
5444  *   The counter devx ID.
5445  *
5446  * @return
5447  *   The counter pool pointer if exists, NULL otherwise,
5448  */
5449 static struct mlx5_flow_counter_pool *
5450 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5451 {
5452         uint32_t i;
5453         struct mlx5_flow_counter_pool *pool = NULL;
5454
5455         rte_spinlock_lock(&cmng->pool_update_sl);
5456         /* Check last used pool. */
5457         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5458             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5459                 pool = cmng->pools[cmng->last_pool_idx];
5460                 goto out;
5461         }
5462         /* ID out of range means no suitable pool in the container. */
5463         if (id > cmng->max_id || id < cmng->min_id)
5464                 goto out;
5465         /*
5466          * Find the pool from the end of the container, since mostly counter
5467          * ID is sequence increasing, and the last pool should be the needed
5468          * one.
5469          */
5470         i = cmng->n_valid;
5471         while (i--) {
5472                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5473
5474                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5475                         pool = pool_tmp;
5476                         break;
5477                 }
5478         }
5479 out:
5480         rte_spinlock_unlock(&cmng->pool_update_sl);
5481         return pool;
5482 }
5483
5484 /**
5485  * Resize a counter container.
5486  *
5487  * @param[in] dev
5488  *   Pointer to the Ethernet device structure.
5489  *
5490  * @return
5491  *   0 on success, otherwise negative errno value and rte_errno is set.
5492  */
5493 static int
5494 flow_dv_container_resize(struct rte_eth_dev *dev)
5495 {
5496         struct mlx5_priv *priv = dev->data->dev_private;
5497         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5498         void *old_pools = cmng->pools;
5499         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5500         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5501         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5502
5503         if (!pools) {
5504                 rte_errno = ENOMEM;
5505                 return -ENOMEM;
5506         }
5507         if (old_pools)
5508                 memcpy(pools, old_pools, cmng->n *
5509                                        sizeof(struct mlx5_flow_counter_pool *));
5510         cmng->n = resize;
5511         cmng->pools = pools;
5512         if (old_pools)
5513                 mlx5_free(old_pools);
5514         return 0;
5515 }
5516
5517 /**
5518  * Query a devx flow counter.
5519  *
5520  * @param[in] dev
5521  *   Pointer to the Ethernet device structure.
5522  * @param[in] cnt
5523  *   Index to the flow counter.
5524  * @param[out] pkts
5525  *   The statistics value of packets.
5526  * @param[out] bytes
5527  *   The statistics value of bytes.
5528  *
5529  * @return
5530  *   0 on success, otherwise a negative errno value and rte_errno is set.
5531  */
5532 static inline int
5533 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5534                      uint64_t *bytes)
5535 {
5536         struct mlx5_priv *priv = dev->data->dev_private;
5537         struct mlx5_flow_counter_pool *pool = NULL;
5538         struct mlx5_flow_counter *cnt;
5539         int offset;
5540
5541         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5542         MLX5_ASSERT(pool);
5543         if (priv->sh->cmng.counter_fallback)
5544                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5545                                         0, pkts, bytes, 0, NULL, NULL, 0);
5546         rte_spinlock_lock(&pool->sl);
5547         if (!pool->raw) {
5548                 *pkts = 0;
5549                 *bytes = 0;
5550         } else {
5551                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5552                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5553                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5554         }
5555         rte_spinlock_unlock(&pool->sl);
5556         return 0;
5557 }
5558
5559 /**
5560  * Create and initialize a new counter pool.
5561  *
5562  * @param[in] dev
5563  *   Pointer to the Ethernet device structure.
5564  * @param[out] dcs
5565  *   The devX counter handle.
5566  * @param[in] age
5567  *   Whether the pool is for counter that was allocated for aging.
5568  * @param[in/out] cont_cur
5569  *   Pointer to the container pointer, it will be update in pool resize.
5570  *
5571  * @return
5572  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5573  */
5574 static struct mlx5_flow_counter_pool *
5575 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5576                     uint32_t age)
5577 {
5578         struct mlx5_priv *priv = dev->data->dev_private;
5579         struct mlx5_flow_counter_pool *pool;
5580         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5581         bool fallback = priv->sh->cmng.counter_fallback;
5582         uint32_t size = sizeof(*pool);
5583
5584         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5585         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5586         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5587         if (!pool) {
5588                 rte_errno = ENOMEM;
5589                 return NULL;
5590         }
5591         pool->raw = NULL;
5592         pool->is_aged = !!age;
5593         pool->query_gen = 0;
5594         pool->min_dcs = dcs;
5595         rte_spinlock_init(&pool->sl);
5596         rte_spinlock_init(&pool->csl);
5597         TAILQ_INIT(&pool->counters[0]);
5598         TAILQ_INIT(&pool->counters[1]);
5599         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5600         rte_spinlock_lock(&cmng->pool_update_sl);
5601         pool->index = cmng->n_valid;
5602         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5603                 mlx5_free(pool);
5604                 rte_spinlock_unlock(&cmng->pool_update_sl);
5605                 return NULL;
5606         }
5607         cmng->pools[pool->index] = pool;
5608         cmng->n_valid++;
5609         if (unlikely(fallback)) {
5610                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5611
5612                 if (base < cmng->min_id)
5613                         cmng->min_id = base;
5614                 if (base > cmng->max_id)
5615                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5616                 cmng->last_pool_idx = pool->index;
5617         }
5618         rte_spinlock_unlock(&cmng->pool_update_sl);
5619         return pool;
5620 }
5621
5622 /**
5623  * Prepare a new counter and/or a new counter pool.
5624  *
5625  * @param[in] dev
5626  *   Pointer to the Ethernet device structure.
5627  * @param[out] cnt_free
5628  *   Where to put the pointer of a new counter.
5629  * @param[in] age
5630  *   Whether the pool is for counter that was allocated for aging.
5631  *
5632  * @return
5633  *   The counter pool pointer and @p cnt_free is set on success,
5634  *   NULL otherwise and rte_errno is set.
5635  */
5636 static struct mlx5_flow_counter_pool *
5637 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5638                              struct mlx5_flow_counter **cnt_free,
5639                              uint32_t age)
5640 {
5641         struct mlx5_priv *priv = dev->data->dev_private;
5642         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5643         struct mlx5_flow_counter_pool *pool;
5644         struct mlx5_counters tmp_tq;
5645         struct mlx5_devx_obj *dcs = NULL;
5646         struct mlx5_flow_counter *cnt;
5647         enum mlx5_counter_type cnt_type =
5648                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5649         bool fallback = priv->sh->cmng.counter_fallback;
5650         uint32_t i;
5651
5652         if (fallback) {
5653                 /* bulk_bitmap must be 0 for single counter allocation. */
5654                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5655                 if (!dcs)
5656                         return NULL;
5657                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5658                 if (!pool) {
5659                         pool = flow_dv_pool_create(dev, dcs, age);
5660                         if (!pool) {
5661                                 mlx5_devx_cmd_destroy(dcs);
5662                                 return NULL;
5663                         }
5664                 }
5665                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5666                 cnt = MLX5_POOL_GET_CNT(pool, i);
5667                 cnt->pool = pool;
5668                 cnt->dcs_when_free = dcs;
5669                 *cnt_free = cnt;
5670                 return pool;
5671         }
5672         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5673         if (!dcs) {
5674                 rte_errno = ENODATA;
5675                 return NULL;
5676         }
5677         pool = flow_dv_pool_create(dev, dcs, age);
5678         if (!pool) {
5679                 mlx5_devx_cmd_destroy(dcs);
5680                 return NULL;
5681         }
5682         TAILQ_INIT(&tmp_tq);
5683         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5684                 cnt = MLX5_POOL_GET_CNT(pool, i);
5685                 cnt->pool = pool;
5686                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5687         }
5688         rte_spinlock_lock(&cmng->csl[cnt_type]);
5689         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5690         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5691         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5692         (*cnt_free)->pool = pool;
5693         return pool;
5694 }
5695
5696 /**
5697  * Allocate a flow counter.
5698  *
5699  * @param[in] dev
5700  *   Pointer to the Ethernet device structure.
5701  * @param[in] age
5702  *   Whether the counter was allocated for aging.
5703  *
5704  * @return
5705  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5706  */
5707 static uint32_t
5708 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5709 {
5710         struct mlx5_priv *priv = dev->data->dev_private;
5711         struct mlx5_flow_counter_pool *pool = NULL;
5712         struct mlx5_flow_counter *cnt_free = NULL;
5713         bool fallback = priv->sh->cmng.counter_fallback;
5714         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5715         enum mlx5_counter_type cnt_type =
5716                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5717         uint32_t cnt_idx;
5718
5719         if (!priv->config.devx) {
5720                 rte_errno = ENOTSUP;
5721                 return 0;
5722         }
5723         /* Get free counters from container. */
5724         rte_spinlock_lock(&cmng->csl[cnt_type]);
5725         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5726         if (cnt_free)
5727                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5728         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5729         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5730                 goto err;
5731         pool = cnt_free->pool;
5732         if (fallback)
5733                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5734         /* Create a DV counter action only in the first time usage. */
5735         if (!cnt_free->action) {
5736                 uint16_t offset;
5737                 struct mlx5_devx_obj *dcs;
5738                 int ret;
5739
5740                 if (!fallback) {
5741                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5742                         dcs = pool->min_dcs;
5743                 } else {
5744                         offset = 0;
5745                         dcs = cnt_free->dcs_when_free;
5746                 }
5747                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5748                                                             &cnt_free->action);
5749                 if (ret) {
5750                         rte_errno = errno;
5751                         goto err;
5752                 }
5753         }
5754         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5755                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5756         /* Update the counter reset values. */
5757         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5758                                  &cnt_free->bytes))
5759                 goto err;
5760         if (!fallback && !priv->sh->cmng.query_thread_on)
5761                 /* Start the asynchronous batch query by the host thread. */
5762                 mlx5_set_query_alarm(priv->sh);
5763         return cnt_idx;
5764 err:
5765         if (cnt_free) {
5766                 cnt_free->pool = pool;
5767                 if (fallback)
5768                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5769                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5770                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5771                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5772         }
5773         return 0;
5774 }
5775
5776 /**
5777  * Allocate a shared flow counter.
5778  *
5779  * @param[in] ctx
5780  *   Pointer to the shared counter configuration.
5781  * @param[in] data
5782  *   Pointer to save the allocated counter index.
5783  *
5784  * @return
5785  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5786  */
5787
5788 static int32_t
5789 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5790 {
5791         struct mlx5_shared_counter_conf *conf = ctx;
5792         struct rte_eth_dev *dev = conf->dev;
5793         struct mlx5_flow_counter *cnt;
5794
5795         data->dword = flow_dv_counter_alloc(dev, 0);
5796         data->dword |= MLX5_CNT_SHARED_OFFSET;
5797         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5798         cnt->shared_info.id = conf->id;
5799         return 0;
5800 }
5801
5802 /**
5803  * Get a shared flow counter.
5804  *
5805  * @param[in] dev
5806  *   Pointer to the Ethernet device structure.
5807  * @param[in] id
5808  *   Counter identifier.
5809  *
5810  * @return
5811  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5812  */
5813 static uint32_t
5814 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5815 {
5816         struct mlx5_priv *priv = dev->data->dev_private;
5817         struct mlx5_shared_counter_conf conf = {
5818                 .dev = dev,
5819                 .id = id,
5820         };
5821         union mlx5_l3t_data data = {
5822                 .dword = 0,
5823         };
5824
5825         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5826                                flow_dv_counter_alloc_shared_cb, &conf);
5827         return data.dword;
5828 }
5829
5830 /**
5831  * Get age param from counter index.
5832  *
5833  * @param[in] dev
5834  *   Pointer to the Ethernet device structure.
5835  * @param[in] counter
5836  *   Index to the counter handler.
5837  *
5838  * @return
5839  *   The aging parameter specified for the counter index.
5840  */
5841 static struct mlx5_age_param*
5842 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5843                                 uint32_t counter)
5844 {
5845         struct mlx5_flow_counter *cnt;
5846         struct mlx5_flow_counter_pool *pool = NULL;
5847
5848         flow_dv_counter_get_by_idx(dev, counter, &pool);
5849         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5850         cnt = MLX5_POOL_GET_CNT(pool, counter);
5851         return MLX5_CNT_TO_AGE(cnt);
5852 }
5853
5854 /**
5855  * Remove a flow counter from aged counter list.
5856  *
5857  * @param[in] dev
5858  *   Pointer to the Ethernet device structure.
5859  * @param[in] counter
5860  *   Index to the counter handler.
5861  * @param[in] cnt
5862  *   Pointer to the counter handler.
5863  */
5864 static void
5865 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5866                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5867 {
5868         struct mlx5_age_info *age_info;
5869         struct mlx5_age_param *age_param;
5870         struct mlx5_priv *priv = dev->data->dev_private;
5871         uint16_t expected = AGE_CANDIDATE;
5872
5873         age_info = GET_PORT_AGE_INFO(priv);
5874         age_param = flow_dv_counter_idx_get_age(dev, counter);
5875         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5876                                          AGE_FREE, false, __ATOMIC_RELAXED,
5877                                          __ATOMIC_RELAXED)) {
5878                 /**
5879                  * We need the lock even it is age timeout,
5880                  * since counter may still in process.
5881                  */
5882                 rte_spinlock_lock(&age_info->aged_sl);
5883                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5884                 rte_spinlock_unlock(&age_info->aged_sl);
5885                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5886         }
5887 }
5888
5889 /**
5890  * Release a flow counter.
5891  *
5892  * @param[in] dev
5893  *   Pointer to the Ethernet device structure.
5894  * @param[in] counter
5895  *   Index to the counter handler.
5896  */
5897 static void
5898 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5899 {
5900         struct mlx5_priv *priv = dev->data->dev_private;
5901         struct mlx5_flow_counter_pool *pool = NULL;
5902         struct mlx5_flow_counter *cnt;
5903         enum mlx5_counter_type cnt_type;
5904
5905         if (!counter)
5906                 return;
5907         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5908         MLX5_ASSERT(pool);
5909         if (IS_SHARED_CNT(counter) &&
5910             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5911                 return;
5912         if (pool->is_aged)
5913                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5914         cnt->pool = pool;
5915         /*
5916          * Put the counter back to list to be updated in none fallback mode.
5917          * Currently, we are using two list alternately, while one is in query,
5918          * add the freed counter to the other list based on the pool query_gen
5919          * value. After query finishes, add counter the list to the global
5920          * container counter list. The list changes while query starts. In
5921          * this case, lock will not be needed as query callback and release
5922          * function both operate with the different list.
5923          *
5924          */
5925         if (!priv->sh->cmng.counter_fallback) {
5926                 rte_spinlock_lock(&pool->csl);
5927                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5928                 rte_spinlock_unlock(&pool->csl);
5929         } else {
5930                 cnt->dcs_when_free = cnt->dcs_when_active;
5931                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5932                                            MLX5_COUNTER_TYPE_ORIGIN;
5933                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5934                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5935                                   cnt, next);
5936                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5937         }
5938 }
5939
5940 /**
5941  * Verify the @p attributes will be correctly understood by the NIC and store
5942  * them in the @p flow if everything is correct.
5943  *
5944  * @param[in] dev
5945  *   Pointer to dev struct.
5946  * @param[in] attributes
5947  *   Pointer to flow attributes
5948  * @param[in] external
5949  *   This flow rule is created by request external to PMD.
5950  * @param[out] error
5951  *   Pointer to error structure.
5952  *
5953  * @return
5954  *   - 0 on success and non root table.
5955  *   - 1 on success and root table.
5956  *   - a negative errno value otherwise and rte_errno is set.
5957  */
5958 static int
5959 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5960                             const struct mlx5_flow_tunnel *tunnel,
5961                             const struct rte_flow_attr *attributes,
5962                             const struct flow_grp_info *grp_info,
5963                             struct rte_flow_error *error)
5964 {
5965         struct mlx5_priv *priv = dev->data->dev_private;
5966         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5967         int ret = 0;
5968
5969 #ifndef HAVE_MLX5DV_DR
5970         RTE_SET_USED(tunnel);
5971         RTE_SET_USED(grp_info);
5972         if (attributes->group)
5973                 return rte_flow_error_set(error, ENOTSUP,
5974                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5975                                           NULL,
5976                                           "groups are not supported");
5977 #else
5978         uint32_t table = 0;
5979
5980         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5981                                        grp_info, error);
5982         if (ret)
5983                 return ret;
5984         if (!table)
5985                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5986 #endif
5987         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5988             attributes->priority > lowest_priority)
5989                 return rte_flow_error_set(error, ENOTSUP,
5990                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5991                                           NULL,
5992                                           "priority out of range");
5993         if (attributes->transfer) {
5994                 if (!priv->config.dv_esw_en)
5995                         return rte_flow_error_set
5996                                 (error, ENOTSUP,
5997                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5998                                  "E-Switch dr is not supported");
5999                 if (!(priv->representor || priv->master))
6000                         return rte_flow_error_set
6001                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6002                                  NULL, "E-Switch configuration can only be"
6003                                  " done by a master or a representor device");
6004                 if (attributes->egress)
6005                         return rte_flow_error_set
6006                                 (error, ENOTSUP,
6007                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6008                                  "egress is not supported");
6009         }
6010         if (!(attributes->egress ^ attributes->ingress))
6011                 return rte_flow_error_set(error, ENOTSUP,
6012                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6013                                           "must specify exactly one of "
6014                                           "ingress or egress");
6015         return ret;
6016 }
6017
6018 /**
6019  * Internal validation function. For validating both actions and items.
6020  *
6021  * @param[in] dev
6022  *   Pointer to the rte_eth_dev structure.
6023  * @param[in] attr
6024  *   Pointer to the flow attributes.
6025  * @param[in] items
6026  *   Pointer to the list of items.
6027  * @param[in] actions
6028  *   Pointer to the list of actions.
6029  * @param[in] external
6030  *   This flow rule is created by request external to PMD.
6031  * @param[in] hairpin
6032  *   Number of hairpin TX actions, 0 means classic flow.
6033  * @param[out] error
6034  *   Pointer to the error structure.
6035  *
6036  * @return
6037  *   0 on success, a negative errno value otherwise and rte_errno is set.
6038  */
6039 static int
6040 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6041                  const struct rte_flow_item items[],
6042                  const struct rte_flow_action actions[],
6043                  bool external, int hairpin, struct rte_flow_error *error)
6044 {
6045         int ret;
6046         uint64_t action_flags = 0;
6047         uint64_t item_flags = 0;
6048         uint64_t last_item = 0;
6049         uint8_t next_protocol = 0xff;
6050         uint16_t ether_type = 0;
6051         int actions_n = 0;
6052         uint8_t item_ipv6_proto = 0;
6053         int fdb_mirror_limit = 0;
6054         int modify_after_mirror = 0;
6055         const struct rte_flow_item *geneve_item = NULL;
6056         const struct rte_flow_item *gre_item = NULL;
6057         const struct rte_flow_item *gtp_item = NULL;
6058         const struct rte_flow_action_raw_decap *decap;
6059         const struct rte_flow_action_raw_encap *encap;
6060         const struct rte_flow_action_rss *rss = NULL;
6061         const struct rte_flow_action_rss *sample_rss = NULL;
6062         const struct rte_flow_action_count *count = NULL;
6063         const struct rte_flow_action_count *sample_count = NULL;
6064         const struct rte_flow_item_tcp nic_tcp_mask = {
6065                 .hdr = {
6066                         .tcp_flags = 0xFF,
6067                         .src_port = RTE_BE16(UINT16_MAX),
6068                         .dst_port = RTE_BE16(UINT16_MAX),
6069                 }
6070         };
6071         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6072                 .hdr = {
6073                         .src_addr =
6074                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6075                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6076                         .dst_addr =
6077                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6078                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6079                         .vtc_flow = RTE_BE32(0xffffffff),
6080                         .proto = 0xff,
6081                         .hop_limits = 0xff,
6082                 },
6083                 .has_frag_ext = 1,
6084         };
6085         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6086                 .hdr = {
6087                         .common = {
6088                                 .u32 =
6089                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6090                                         .type = 0xFF,
6091                                         }).u32),
6092                         },
6093                         .dummy[0] = 0xffffffff,
6094                 },
6095         };
6096         struct mlx5_priv *priv = dev->data->dev_private;
6097         struct mlx5_dev_config *dev_conf = &priv->config;
6098         uint16_t queue_index = 0xFFFF;
6099         const struct rte_flow_item_vlan *vlan_m = NULL;
6100         uint32_t rw_act_num = 0;
6101         uint64_t is_root;
6102         const struct mlx5_flow_tunnel *tunnel;
6103         struct flow_grp_info grp_info = {
6104                 .external = !!external,
6105                 .transfer = !!attr->transfer,
6106                 .fdb_def_rule = !!priv->fdb_def_rule,
6107         };
6108         const struct rte_eth_hairpin_conf *conf;
6109
6110         if (items == NULL)
6111                 return -1;
6112         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6113                 tunnel = flow_items_to_tunnel(items);
6114                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6115                                 MLX5_FLOW_ACTION_DECAP;
6116         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6117                 tunnel = flow_actions_to_tunnel(actions);
6118                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6119         } else {
6120                 tunnel = NULL;
6121         }
6122         if (tunnel && priv->representor)
6123                 return rte_flow_error_set(error, ENOTSUP,
6124                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6125                                           "decap not supported "
6126                                           "for VF representor");
6127         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6128                                 (dev, tunnel, attr, items, actions);
6129         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6130         if (ret < 0)
6131                 return ret;
6132         is_root = (uint64_t)ret;
6133         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6134                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6135                 int type = items->type;
6136
6137                 if (!mlx5_flow_os_item_supported(type))
6138                         return rte_flow_error_set(error, ENOTSUP,
6139                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6140                                                   NULL, "item not supported");
6141                 switch (type) {
6142                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6143                         if (items[0].type != (typeof(items[0].type))
6144                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6145                                 return rte_flow_error_set
6146                                                 (error, EINVAL,
6147                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6148                                                 NULL, "MLX5 private items "
6149                                                 "must be the first");
6150                         break;
6151                 case RTE_FLOW_ITEM_TYPE_VOID:
6152                         break;
6153                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6154                         ret = flow_dv_validate_item_port_id
6155                                         (dev, items, attr, item_flags, error);
6156                         if (ret < 0)
6157                                 return ret;
6158                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6159                         break;
6160                 case RTE_FLOW_ITEM_TYPE_ETH:
6161                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6162                                                           true, error);
6163                         if (ret < 0)
6164                                 return ret;
6165                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6166                                              MLX5_FLOW_LAYER_OUTER_L2;
6167                         if (items->mask != NULL && items->spec != NULL) {
6168                                 ether_type =
6169                                         ((const struct rte_flow_item_eth *)
6170                                          items->spec)->type;
6171                                 ether_type &=
6172                                         ((const struct rte_flow_item_eth *)
6173                                          items->mask)->type;
6174                                 ether_type = rte_be_to_cpu_16(ether_type);
6175                         } else {
6176                                 ether_type = 0;
6177                         }
6178                         break;
6179                 case RTE_FLOW_ITEM_TYPE_VLAN:
6180                         ret = flow_dv_validate_item_vlan(items, item_flags,
6181                                                          dev, error);
6182                         if (ret < 0)
6183                                 return ret;
6184                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6185                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6186                         if (items->mask != NULL && items->spec != NULL) {
6187                                 ether_type =
6188                                         ((const struct rte_flow_item_vlan *)
6189                                          items->spec)->inner_type;
6190                                 ether_type &=
6191                                         ((const struct rte_flow_item_vlan *)
6192                                          items->mask)->inner_type;
6193                                 ether_type = rte_be_to_cpu_16(ether_type);
6194                         } else {
6195                                 ether_type = 0;
6196                         }
6197                         /* Store outer VLAN mask for of_push_vlan action. */
6198                         if (!tunnel)
6199                                 vlan_m = items->mask;
6200                         break;
6201                 case RTE_FLOW_ITEM_TYPE_IPV4:
6202                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6203                                                   &item_flags, &tunnel);
6204                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6205                                                          last_item, ether_type,
6206                                                          error);
6207                         if (ret < 0)
6208                                 return ret;
6209                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6210                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6211                         if (items->mask != NULL &&
6212                             ((const struct rte_flow_item_ipv4 *)
6213                              items->mask)->hdr.next_proto_id) {
6214                                 next_protocol =
6215                                         ((const struct rte_flow_item_ipv4 *)
6216                                          (items->spec))->hdr.next_proto_id;
6217                                 next_protocol &=
6218                                         ((const struct rte_flow_item_ipv4 *)
6219                                          (items->mask))->hdr.next_proto_id;
6220                         } else {
6221                                 /* Reset for inner layer. */
6222                                 next_protocol = 0xff;
6223                         }
6224                         break;
6225                 case RTE_FLOW_ITEM_TYPE_IPV6:
6226                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6227                                                   &item_flags, &tunnel);
6228                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6229                                                            last_item,
6230                                                            ether_type,
6231                                                            &nic_ipv6_mask,
6232                                                            error);
6233                         if (ret < 0)
6234                                 return ret;
6235                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6236                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6237                         if (items->mask != NULL &&
6238                             ((const struct rte_flow_item_ipv6 *)
6239                              items->mask)->hdr.proto) {
6240                                 item_ipv6_proto =
6241                                         ((const struct rte_flow_item_ipv6 *)
6242                                          items->spec)->hdr.proto;
6243                                 next_protocol =
6244                                         ((const struct rte_flow_item_ipv6 *)
6245                                          items->spec)->hdr.proto;
6246                                 next_protocol &=
6247                                         ((const struct rte_flow_item_ipv6 *)
6248                                          items->mask)->hdr.proto;
6249                         } else {
6250                                 /* Reset for inner layer. */
6251                                 next_protocol = 0xff;
6252                         }
6253                         break;
6254                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6255                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6256                                                                   item_flags,
6257                                                                   error);
6258                         if (ret < 0)
6259                                 return ret;
6260                         last_item = tunnel ?
6261                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6262                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6263                         if (items->mask != NULL &&
6264                             ((const struct rte_flow_item_ipv6_frag_ext *)
6265                              items->mask)->hdr.next_header) {
6266                                 next_protocol =
6267                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6268                                  items->spec)->hdr.next_header;
6269                                 next_protocol &=
6270                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6271                                  items->mask)->hdr.next_header;
6272                         } else {
6273                                 /* Reset for inner layer. */
6274                                 next_protocol = 0xff;
6275                         }
6276                         break;
6277                 case RTE_FLOW_ITEM_TYPE_TCP:
6278                         ret = mlx5_flow_validate_item_tcp
6279                                                 (items, item_flags,
6280                                                  next_protocol,
6281                                                  &nic_tcp_mask,
6282                                                  error);
6283                         if (ret < 0)
6284                                 return ret;
6285                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6286                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6287                         break;
6288                 case RTE_FLOW_ITEM_TYPE_UDP:
6289                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6290                                                           next_protocol,
6291                                                           error);
6292                         if (ret < 0)
6293                                 return ret;
6294                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6295                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6296                         break;
6297                 case RTE_FLOW_ITEM_TYPE_GRE:
6298                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6299                                                           next_protocol, error);
6300                         if (ret < 0)
6301                                 return ret;
6302                         gre_item = items;
6303                         last_item = MLX5_FLOW_LAYER_GRE;
6304                         break;
6305                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6306                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6307                                                             next_protocol,
6308                                                             error);
6309                         if (ret < 0)
6310                                 return ret;
6311                         last_item = MLX5_FLOW_LAYER_NVGRE;
6312                         break;
6313                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6314                         ret = mlx5_flow_validate_item_gre_key
6315                                 (items, item_flags, gre_item, error);
6316                         if (ret < 0)
6317                                 return ret;
6318                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6319                         break;
6320                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6321                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6322                                                             error);
6323                         if (ret < 0)
6324                                 return ret;
6325                         last_item = MLX5_FLOW_LAYER_VXLAN;
6326                         break;
6327                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6328                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6329                                                                 item_flags, dev,
6330                                                                 error);
6331                         if (ret < 0)
6332                                 return ret;
6333                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6334                         break;
6335                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6336                         ret = mlx5_flow_validate_item_geneve(items,
6337                                                              item_flags, dev,
6338                                                              error);
6339                         if (ret < 0)
6340                                 return ret;
6341                         geneve_item = items;
6342                         last_item = MLX5_FLOW_LAYER_GENEVE;
6343                         break;
6344                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6345                         ret = mlx5_flow_validate_item_geneve_opt(items,
6346                                                                  last_item,
6347                                                                  geneve_item,
6348                                                                  dev,
6349                                                                  error);
6350                         if (ret < 0)
6351                                 return ret;
6352                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6353                         break;
6354                 case RTE_FLOW_ITEM_TYPE_MPLS:
6355                         ret = mlx5_flow_validate_item_mpls(dev, items,
6356                                                            item_flags,
6357                                                            last_item, error);
6358                         if (ret < 0)
6359                                 return ret;
6360                         last_item = MLX5_FLOW_LAYER_MPLS;
6361                         break;
6362
6363                 case RTE_FLOW_ITEM_TYPE_MARK:
6364                         ret = flow_dv_validate_item_mark(dev, items, attr,
6365                                                          error);
6366                         if (ret < 0)
6367                                 return ret;
6368                         last_item = MLX5_FLOW_ITEM_MARK;
6369                         break;
6370                 case RTE_FLOW_ITEM_TYPE_META:
6371                         ret = flow_dv_validate_item_meta(dev, items, attr,
6372                                                          error);
6373                         if (ret < 0)
6374                                 return ret;
6375                         last_item = MLX5_FLOW_ITEM_METADATA;
6376                         break;
6377                 case RTE_FLOW_ITEM_TYPE_ICMP:
6378                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6379                                                            next_protocol,
6380                                                            error);
6381                         if (ret < 0)
6382                                 return ret;
6383                         last_item = MLX5_FLOW_LAYER_ICMP;
6384                         break;
6385                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6386                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6387                                                             next_protocol,
6388                                                             error);
6389                         if (ret < 0)
6390                                 return ret;
6391                         item_ipv6_proto = IPPROTO_ICMPV6;
6392                         last_item = MLX5_FLOW_LAYER_ICMP6;
6393                         break;
6394                 case RTE_FLOW_ITEM_TYPE_TAG:
6395                         ret = flow_dv_validate_item_tag(dev, items,
6396                                                         attr, error);
6397                         if (ret < 0)
6398                                 return ret;
6399                         last_item = MLX5_FLOW_ITEM_TAG;
6400                         break;
6401                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6402                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6403                         break;
6404                 case RTE_FLOW_ITEM_TYPE_GTP:
6405                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6406                                                         error);
6407                         if (ret < 0)
6408                                 return ret;
6409                         gtp_item = items;
6410                         last_item = MLX5_FLOW_LAYER_GTP;
6411                         break;
6412                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6413                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6414                                                             gtp_item, attr,
6415                                                             error);
6416                         if (ret < 0)
6417                                 return ret;
6418                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6419                         break;
6420                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6421                         /* Capacity will be checked in the translate stage. */
6422                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6423                                                             last_item,
6424                                                             ether_type,
6425                                                             &nic_ecpri_mask,
6426                                                             error);
6427                         if (ret < 0)
6428                                 return ret;
6429                         last_item = MLX5_FLOW_LAYER_ECPRI;
6430                         break;
6431                 default:
6432                         return rte_flow_error_set(error, ENOTSUP,
6433                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6434                                                   NULL, "item not supported");
6435                 }
6436                 item_flags |= last_item;
6437         }
6438         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6439                 int type = actions->type;
6440
6441                 if (!mlx5_flow_os_action_supported(type))
6442                         return rte_flow_error_set(error, ENOTSUP,
6443                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6444                                                   actions,
6445                                                   "action not supported");
6446                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6447                         return rte_flow_error_set(error, ENOTSUP,
6448                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6449                                                   actions, "too many actions");
6450                 switch (type) {
6451                 case RTE_FLOW_ACTION_TYPE_VOID:
6452                         break;
6453                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6454                         ret = flow_dv_validate_action_port_id(dev,
6455                                                               action_flags,
6456                                                               actions,
6457                                                               attr,
6458                                                               error);
6459                         if (ret)
6460                                 return ret;
6461                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6462                         ++actions_n;
6463                         break;
6464                 case RTE_FLOW_ACTION_TYPE_FLAG:
6465                         ret = flow_dv_validate_action_flag(dev, action_flags,
6466                                                            attr, error);
6467                         if (ret < 0)
6468                                 return ret;
6469                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6470                                 /* Count all modify-header actions as one. */
6471                                 if (!(action_flags &
6472                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6473                                         ++actions_n;
6474                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6475                                                 MLX5_FLOW_ACTION_MARK_EXT;
6476                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6477                                         modify_after_mirror = 1;
6478
6479                         } else {
6480                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6481                                 ++actions_n;
6482                         }
6483                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6484                         break;
6485                 case RTE_FLOW_ACTION_TYPE_MARK:
6486                         ret = flow_dv_validate_action_mark(dev, actions,
6487                                                            action_flags,
6488                                                            attr, error);
6489                         if (ret < 0)
6490                                 return ret;
6491                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6492                                 /* Count all modify-header actions as one. */
6493                                 if (!(action_flags &
6494                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6495                                         ++actions_n;
6496                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6497                                                 MLX5_FLOW_ACTION_MARK_EXT;
6498                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6499                                         modify_after_mirror = 1;
6500                         } else {
6501                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6502                                 ++actions_n;
6503                         }
6504                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6505                         break;
6506                 case RTE_FLOW_ACTION_TYPE_SET_META:
6507                         ret = flow_dv_validate_action_set_meta(dev, actions,
6508                                                                action_flags,
6509                                                                attr, error);
6510                         if (ret < 0)
6511                                 return ret;
6512                         /* Count all modify-header actions as one action. */
6513                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6514                                 ++actions_n;
6515                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6516                                 modify_after_mirror = 1;
6517                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6518                         rw_act_num += MLX5_ACT_NUM_SET_META;
6519                         break;
6520                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6521                         ret = flow_dv_validate_action_set_tag(dev, actions,
6522                                                               action_flags,
6523                                                               attr, error);
6524                         if (ret < 0)
6525                                 return ret;
6526                         /* Count all modify-header actions as one action. */
6527                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6528                                 ++actions_n;
6529                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6530                                 modify_after_mirror = 1;
6531                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6532                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6533                         break;
6534                 case RTE_FLOW_ACTION_TYPE_DROP:
6535                         ret = mlx5_flow_validate_action_drop(action_flags,
6536                                                              attr, error);
6537                         if (ret < 0)
6538                                 return ret;
6539                         action_flags |= MLX5_FLOW_ACTION_DROP;
6540                         ++actions_n;
6541                         break;
6542                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6543                         ret = mlx5_flow_validate_action_queue(actions,
6544                                                               action_flags, dev,
6545                                                               attr, error);
6546                         if (ret < 0)
6547                                 return ret;
6548                         queue_index = ((const struct rte_flow_action_queue *)
6549                                                         (actions->conf))->index;
6550                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6551                         ++actions_n;
6552                         break;
6553                 case RTE_FLOW_ACTION_TYPE_RSS:
6554                         rss = actions->conf;
6555                         ret = mlx5_flow_validate_action_rss(actions,
6556                                                             action_flags, dev,
6557                                                             attr, item_flags,
6558                                                             error);
6559                         if (ret < 0)
6560                                 return ret;
6561                         if (rss && sample_rss &&
6562                             (sample_rss->level != rss->level ||
6563                             sample_rss->types != rss->types))
6564                                 return rte_flow_error_set(error, ENOTSUP,
6565                                         RTE_FLOW_ERROR_TYPE_ACTION,
6566                                         NULL,
6567                                         "Can't use the different RSS types "
6568                                         "or level in the same flow");
6569                         if (rss != NULL && rss->queue_num)
6570                                 queue_index = rss->queue[0];
6571                         action_flags |= MLX5_FLOW_ACTION_RSS;
6572                         ++actions_n;
6573                         break;
6574                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6575                         ret =
6576                         mlx5_flow_validate_action_default_miss(action_flags,
6577                                         attr, error);
6578                         if (ret < 0)
6579                                 return ret;
6580                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6581                         ++actions_n;
6582                         break;
6583                 case RTE_FLOW_ACTION_TYPE_COUNT:
6584                         ret = flow_dv_validate_action_count(dev, actions,
6585                                                             action_flags,
6586                                                             error);
6587                         if (ret < 0)
6588                                 return ret;
6589                         count = actions->conf;
6590                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6591                         ++actions_n;
6592                         break;
6593                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6594                         if (flow_dv_validate_action_pop_vlan(dev,
6595                                                              action_flags,
6596                                                              actions,
6597                                                              item_flags, attr,
6598                                                              error))
6599                                 return -rte_errno;
6600                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6601                                 modify_after_mirror = 1;
6602                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6603                         ++actions_n;
6604                         break;
6605                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6606                         ret = flow_dv_validate_action_push_vlan(dev,
6607                                                                 action_flags,
6608                                                                 vlan_m,
6609                                                                 actions, attr,
6610                                                                 error);
6611                         if (ret < 0)
6612                                 return ret;
6613                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6614                                 modify_after_mirror = 1;
6615                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6616                         ++actions_n;
6617                         break;
6618                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6619                         ret = flow_dv_validate_action_set_vlan_pcp
6620                                                 (action_flags, actions, error);
6621                         if (ret < 0)
6622                                 return ret;
6623                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6624                                 modify_after_mirror = 1;
6625                         /* Count PCP with push_vlan command. */
6626                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6627                         break;
6628                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6629                         ret = flow_dv_validate_action_set_vlan_vid
6630                                                 (item_flags, action_flags,
6631                                                  actions, error);
6632                         if (ret < 0)
6633                                 return ret;
6634                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6635                                 modify_after_mirror = 1;
6636                         /* Count VID with push_vlan command. */
6637                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6638                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6639                         break;
6640                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6641                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6642                         ret = flow_dv_validate_action_l2_encap(dev,
6643                                                                action_flags,
6644                                                                actions, attr,
6645                                                                error);
6646                         if (ret < 0)
6647                                 return ret;
6648                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6649                         ++actions_n;
6650                         break;
6651                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6652                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6653                         ret = flow_dv_validate_action_decap(dev, action_flags,
6654                                                             actions, item_flags,
6655                                                             attr, error);
6656                         if (ret < 0)
6657                                 return ret;
6658                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6659                                 modify_after_mirror = 1;
6660                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6661                         ++actions_n;
6662                         break;
6663                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6664                         ret = flow_dv_validate_action_raw_encap_decap
6665                                 (dev, NULL, actions->conf, attr, &action_flags,
6666                                  &actions_n, actions, item_flags, error);
6667                         if (ret < 0)
6668                                 return ret;
6669                         break;
6670                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6671                         decap = actions->conf;
6672                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6673                                 ;
6674                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6675                                 encap = NULL;
6676                                 actions--;
6677                         } else {
6678                                 encap = actions->conf;
6679                         }
6680                         ret = flow_dv_validate_action_raw_encap_decap
6681                                            (dev,
6682                                             decap ? decap : &empty_decap, encap,
6683                                             attr, &action_flags, &actions_n,
6684                                             actions, item_flags, error);
6685                         if (ret < 0)
6686                                 return ret;
6687                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6688                             (action_flags & MLX5_FLOW_ACTION_DECAP))
6689                                 modify_after_mirror = 1;
6690                         break;
6691                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6692                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6693                         ret = flow_dv_validate_action_modify_mac(action_flags,
6694                                                                  actions,
6695                                                                  item_flags,
6696                                                                  error);
6697                         if (ret < 0)
6698                                 return ret;
6699                         /* Count all modify-header actions as one action. */
6700                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6701                                 ++actions_n;
6702                         action_flags |= actions->type ==
6703                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6704                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6705                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6706                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6707                                 modify_after_mirror = 1;
6708                         /*
6709                          * Even if the source and destination MAC addresses have
6710                          * overlap in the header with 4B alignment, the convert
6711                          * function will handle them separately and 4 SW actions
6712                          * will be created. And 2 actions will be added each
6713                          * time no matter how many bytes of address will be set.
6714                          */
6715                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6716                         break;
6717                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6718                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6719                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6720                                                                   actions,
6721                                                                   item_flags,
6722                                                                   error);
6723                         if (ret < 0)
6724                                 return ret;
6725                         /* Count all modify-header actions as one action. */
6726                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6727                                 ++actions_n;
6728                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6729                                 modify_after_mirror = 1;
6730                         action_flags |= actions->type ==
6731                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6732                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6733                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6734                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6735                         break;
6736                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6737                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6738                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6739                                                                   actions,
6740                                                                   item_flags,
6741                                                                   error);
6742                         if (ret < 0)
6743                                 return ret;
6744                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6745                                 return rte_flow_error_set(error, ENOTSUP,
6746                                         RTE_FLOW_ERROR_TYPE_ACTION,
6747                                         actions,
6748                                         "Can't change header "
6749                                         "with ICMPv6 proto");
6750                         /* Count all modify-header actions as one action. */
6751                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6752                                 ++actions_n;
6753                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6754                                 modify_after_mirror = 1;
6755                         action_flags |= actions->type ==
6756                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6757                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6758                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6759                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6760                         break;
6761                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6762                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6763                         ret = flow_dv_validate_action_modify_tp(action_flags,
6764                                                                 actions,
6765                                                                 item_flags,
6766                                                                 error);
6767                         if (ret < 0)
6768                                 return ret;
6769                         /* Count all modify-header actions as one action. */
6770                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6771                                 ++actions_n;
6772                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6773                                 modify_after_mirror = 1;
6774                         action_flags |= actions->type ==
6775                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6776                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6777                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6778                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6779                         break;
6780                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6781                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6782                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6783                                                                  actions,
6784                                                                  item_flags,
6785                                                                  error);
6786                         if (ret < 0)
6787                                 return ret;
6788                         /* Count all modify-header actions as one action. */
6789                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6790                                 ++actions_n;
6791                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6792                                 modify_after_mirror = 1;
6793                         action_flags |= actions->type ==
6794                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6795                                                 MLX5_FLOW_ACTION_SET_TTL :
6796                                                 MLX5_FLOW_ACTION_DEC_TTL;
6797                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6798                         break;
6799                 case RTE_FLOW_ACTION_TYPE_JUMP:
6800                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6801                                                            action_flags,
6802                                                            attr, external,
6803                                                            error);
6804                         if (ret)
6805                                 return ret;
6806                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6807                             fdb_mirror_limit)
6808                                 return rte_flow_error_set(error, EINVAL,
6809                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6810                                                   NULL,
6811                                                   "sample and jump action combination is not supported");
6812                         ++actions_n;
6813                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6814                         break;
6815                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6816                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6817                         ret = flow_dv_validate_action_modify_tcp_seq
6818                                                                 (action_flags,
6819                                                                  actions,
6820                                                                  item_flags,
6821                                                                  error);
6822                         if (ret < 0)
6823                                 return ret;
6824                         /* Count all modify-header actions as one action. */
6825                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6826                                 ++actions_n;
6827                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6828                                 modify_after_mirror = 1;
6829                         action_flags |= actions->type ==
6830                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6831                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6832                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6833                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6834                         break;
6835                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6836                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6837                         ret = flow_dv_validate_action_modify_tcp_ack
6838                                                                 (action_flags,
6839                                                                  actions,
6840                                                                  item_flags,
6841                                                                  error);
6842                         if (ret < 0)
6843                                 return ret;
6844                         /* Count all modify-header actions as one action. */
6845                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6846                                 ++actions_n;
6847                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6848                                 modify_after_mirror = 1;
6849                         action_flags |= actions->type ==
6850                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6851                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6852                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6853                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6854                         break;
6855                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6856                         break;
6857                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6858                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6859                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6860                         break;
6861                 case RTE_FLOW_ACTION_TYPE_METER:
6862                         ret = mlx5_flow_validate_action_meter(dev,
6863                                                               action_flags,
6864                                                               actions, attr,
6865                                                               error);
6866                         if (ret < 0)
6867                                 return ret;
6868                         action_flags |= MLX5_FLOW_ACTION_METER;
6869                         ++actions_n;
6870                         /* Meter action will add one more TAG action. */
6871                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6872                         break;
6873                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6874                         if (!attr->transfer && !attr->group)
6875                                 return rte_flow_error_set(error, ENOTSUP,
6876                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6877                                                                            NULL,
6878                           "Shared ASO age action is not supported for group 0");
6879                         action_flags |= MLX5_FLOW_ACTION_AGE;
6880                         ++actions_n;
6881                         break;
6882                 case RTE_FLOW_ACTION_TYPE_AGE:
6883                         ret = flow_dv_validate_action_age(action_flags,
6884                                                           actions, dev,
6885                                                           error);
6886                         if (ret < 0)
6887                                 return ret;
6888                         /*
6889                          * Validate the regular AGE action (using counter)
6890                          * mutual exclusion with share counter actions.
6891                          */
6892                         if (!priv->sh->flow_hit_aso_en) {
6893                                 if (count && count->shared)
6894                                         return rte_flow_error_set
6895                                                 (error, EINVAL,
6896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6897                                                 NULL,
6898                                                 "old age and shared count combination is not supported");
6899                                 if (sample_count)
6900                                         return rte_flow_error_set
6901                                                 (error, EINVAL,
6902                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6903                                                 NULL,
6904                                                 "old age action and count must be in the same sub flow");
6905                         }
6906                         action_flags |= MLX5_FLOW_ACTION_AGE;
6907                         ++actions_n;
6908                         break;
6909                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6910                         ret = flow_dv_validate_action_modify_ipv4_dscp
6911                                                          (action_flags,
6912                                                           actions,
6913                                                           item_flags,
6914                                                           error);
6915                         if (ret < 0)
6916                                 return ret;
6917                         /* Count all modify-header actions as one action. */
6918                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6919                                 ++actions_n;
6920                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6921                                 modify_after_mirror = 1;
6922                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6923                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6924                         break;
6925                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6926                         ret = flow_dv_validate_action_modify_ipv6_dscp
6927                                                                 (action_flags,
6928                                                                  actions,
6929                                                                  item_flags,
6930                                                                  error);
6931                         if (ret < 0)
6932                                 return ret;
6933                         /* Count all modify-header actions as one action. */
6934                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6935                                 ++actions_n;
6936                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6937                                 modify_after_mirror = 1;
6938                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6939                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6940                         break;
6941                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6942                         ret = flow_dv_validate_action_sample(&action_flags,
6943                                                              actions, dev,
6944                                                              attr, item_flags,
6945                                                              rss, &sample_rss,
6946                                                              &sample_count,
6947                                                              &fdb_mirror_limit,
6948                                                              error);
6949                         if (ret < 0)
6950                                 return ret;
6951                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6952                         ++actions_n;
6953                         break;
6954                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6955                         if (actions[0].type != (typeof(actions[0].type))
6956                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6957                                 return rte_flow_error_set
6958                                                 (error, EINVAL,
6959                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6960                                                 NULL, "MLX5 private action "
6961                                                 "must be the first");
6962
6963                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6964                         break;
6965                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6966                         ret = flow_dv_validate_action_modify_field(dev,
6967                                                                    action_flags,
6968                                                                    actions,
6969                                                                    attr,
6970                                                                    error);
6971                         if (ret < 0)
6972                                 return ret;
6973                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6974                                 modify_after_mirror = 1;
6975                         /* Count all modify-header actions as one action. */
6976                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6977                                 ++actions_n;
6978                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6979                         rw_act_num += ret;
6980                         break;
6981                 default:
6982                         return rte_flow_error_set(error, ENOTSUP,
6983                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6984                                                   actions,
6985                                                   "action not supported");
6986                 }
6987         }
6988         /*
6989          * Validate actions in flow rules
6990          * - Explicit decap action is prohibited by the tunnel offload API.
6991          * - Drop action in tunnel steer rule is prohibited by the API.
6992          * - Application cannot use MARK action because it's value can mask
6993          *   tunnel default miss nitification.
6994          * - JUMP in tunnel match rule has no support in current PMD
6995          *   implementation.
6996          * - TAG & META are reserved for future uses.
6997          */
6998         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6999                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
7000                                             MLX5_FLOW_ACTION_MARK     |
7001                                             MLX5_FLOW_ACTION_SET_TAG  |
7002                                             MLX5_FLOW_ACTION_SET_META |
7003                                             MLX5_FLOW_ACTION_DROP;
7004
7005                 if (action_flags & bad_actions_mask)
7006                         return rte_flow_error_set
7007                                         (error, EINVAL,
7008                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7009                                         "Invalid RTE action in tunnel "
7010                                         "set decap rule");
7011                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7012                         return rte_flow_error_set
7013                                         (error, EINVAL,
7014                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7015                                         "tunnel set decap rule must terminate "
7016                                         "with JUMP");
7017                 if (!attr->ingress)
7018                         return rte_flow_error_set
7019                                         (error, EINVAL,
7020                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7021                                         "tunnel flows for ingress traffic only");
7022         }
7023         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7024                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7025                                             MLX5_FLOW_ACTION_MARK    |
7026                                             MLX5_FLOW_ACTION_SET_TAG |
7027                                             MLX5_FLOW_ACTION_SET_META;
7028
7029                 if (action_flags & bad_actions_mask)
7030                         return rte_flow_error_set
7031                                         (error, EINVAL,
7032                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7033                                         "Invalid RTE action in tunnel "
7034                                         "set match rule");
7035         }
7036         /*
7037          * Validate the drop action mutual exclusion with other actions.
7038          * Drop action is mutually-exclusive with any other action, except for
7039          * Count action.
7040          * Drop action compatibility with tunnel offload was already validated.
7041          */
7042         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7043                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7044         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7045             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7046                 return rte_flow_error_set(error, EINVAL,
7047                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7048                                           "Drop action is mutually-exclusive "
7049                                           "with any other action, except for "
7050                                           "Count action");
7051         /* Eswitch has few restrictions on using items and actions */
7052         if (attr->transfer) {
7053                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7054                     action_flags & MLX5_FLOW_ACTION_FLAG)
7055                         return rte_flow_error_set(error, ENOTSUP,
7056                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7057                                                   NULL,
7058                                                   "unsupported action FLAG");
7059                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7060                     action_flags & MLX5_FLOW_ACTION_MARK)
7061                         return rte_flow_error_set(error, ENOTSUP,
7062                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7063                                                   NULL,
7064                                                   "unsupported action MARK");
7065                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7066                         return rte_flow_error_set(error, ENOTSUP,
7067                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7068                                                   NULL,
7069                                                   "unsupported action QUEUE");
7070                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7071                         return rte_flow_error_set(error, ENOTSUP,
7072                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7073                                                   NULL,
7074                                                   "unsupported action RSS");
7075                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7076                         return rte_flow_error_set(error, EINVAL,
7077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7078                                                   actions,
7079                                                   "no fate action is found");
7080         } else {
7081                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7082                         return rte_flow_error_set(error, EINVAL,
7083                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7084                                                   actions,
7085                                                   "no fate action is found");
7086         }
7087         /*
7088          * Continue validation for Xcap and VLAN actions.
7089          * If hairpin is working in explicit TX rule mode, there is no actions
7090          * splitting and the validation of hairpin ingress flow should be the
7091          * same as other standard flows.
7092          */
7093         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7094                              MLX5_FLOW_VLAN_ACTIONS)) &&
7095             (queue_index == 0xFFFF ||
7096              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7097              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7098              conf->tx_explicit != 0))) {
7099                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7100                     MLX5_FLOW_XCAP_ACTIONS)
7101                         return rte_flow_error_set(error, ENOTSUP,
7102                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7103                                                   NULL, "encap and decap "
7104                                                   "combination aren't supported");
7105                 if (!attr->transfer && attr->ingress) {
7106                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7107                                 return rte_flow_error_set
7108                                                 (error, ENOTSUP,
7109                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7110                                                  NULL, "encap is not supported"
7111                                                  " for ingress traffic");
7112                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7113                                 return rte_flow_error_set
7114                                                 (error, ENOTSUP,
7115                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7116                                                  NULL, "push VLAN action not "
7117                                                  "supported for ingress");
7118                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7119                                         MLX5_FLOW_VLAN_ACTIONS)
7120                                 return rte_flow_error_set
7121                                                 (error, ENOTSUP,
7122                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7123                                                  NULL, "no support for "
7124                                                  "multiple VLAN actions");
7125                 }
7126         }
7127         /*
7128          * Hairpin flow will add one more TAG action in TX implicit mode.
7129          * In TX explicit mode, there will be no hairpin flow ID.
7130          */
7131         if (hairpin > 0)
7132                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7133         /* extra metadata enabled: one more TAG action will be add. */
7134         if (dev_conf->dv_flow_en &&
7135             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7136             mlx5_flow_ext_mreg_supported(dev))
7137                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7138         if (rw_act_num >
7139                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7140                 return rte_flow_error_set(error, ENOTSUP,
7141                                           RTE_FLOW_ERROR_TYPE_ACTION,
7142                                           NULL, "too many header modify"
7143                                           " actions to support");
7144         }
7145         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7146         if (fdb_mirror_limit && modify_after_mirror)
7147                 return rte_flow_error_set(error, EINVAL,
7148                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7149                                 "sample before modify action is not supported");
7150         return 0;
7151 }
7152
7153 /**
7154  * Internal preparation function. Allocates the DV flow size,
7155  * this size is constant.
7156  *
7157  * @param[in] dev
7158  *   Pointer to the rte_eth_dev structure.
7159  * @param[in] attr
7160  *   Pointer to the flow attributes.
7161  * @param[in] items
7162  *   Pointer to the list of items.
7163  * @param[in] actions
7164  *   Pointer to the list of actions.
7165  * @param[out] error
7166  *   Pointer to the error structure.
7167  *
7168  * @return
7169  *   Pointer to mlx5_flow object on success,
7170  *   otherwise NULL and rte_errno is set.
7171  */
7172 static struct mlx5_flow *
7173 flow_dv_prepare(struct rte_eth_dev *dev,
7174                 const struct rte_flow_attr *attr __rte_unused,
7175                 const struct rte_flow_item items[] __rte_unused,
7176                 const struct rte_flow_action actions[] __rte_unused,
7177                 struct rte_flow_error *error)
7178 {
7179         uint32_t handle_idx = 0;
7180         struct mlx5_flow *dev_flow;
7181         struct mlx5_flow_handle *dev_handle;
7182         struct mlx5_priv *priv = dev->data->dev_private;
7183         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7184
7185         MLX5_ASSERT(wks);
7186         /* In case of corrupting the memory. */
7187         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7188                 rte_flow_error_set(error, ENOSPC,
7189                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7190                                    "not free temporary device flow");
7191                 return NULL;
7192         }
7193         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7194                                    &handle_idx);
7195         if (!dev_handle) {
7196                 rte_flow_error_set(error, ENOMEM,
7197                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7198                                    "not enough memory to create flow handle");
7199                 return NULL;
7200         }
7201         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7202         dev_flow = &wks->flows[wks->flow_idx++];
7203         memset(dev_flow, 0, sizeof(*dev_flow));
7204         dev_flow->handle = dev_handle;
7205         dev_flow->handle_idx = handle_idx;
7206         /*
7207          * In some old rdma-core releases, before continuing, a check of the
7208          * length of matching parameter will be done at first. It needs to use
7209          * the length without misc4 param. If the flow has misc4 support, then
7210          * the length needs to be adjusted accordingly. Each param member is
7211          * aligned with a 64B boundary naturally.
7212          */
7213         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7214                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7215         dev_flow->ingress = attr->ingress;
7216         dev_flow->dv.transfer = attr->transfer;
7217         return dev_flow;
7218 }
7219
7220 #ifdef RTE_LIBRTE_MLX5_DEBUG
7221 /**
7222  * Sanity check for match mask and value. Similar to check_valid_spec() in
7223  * kernel driver. If unmasked bit is present in value, it returns failure.
7224  *
7225  * @param match_mask
7226  *   pointer to match mask buffer.
7227  * @param match_value
7228  *   pointer to match value buffer.
7229  *
7230  * @return
7231  *   0 if valid, -EINVAL otherwise.
7232  */
7233 static int
7234 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7235 {
7236         uint8_t *m = match_mask;
7237         uint8_t *v = match_value;
7238         unsigned int i;
7239
7240         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7241                 if (v[i] & ~m[i]) {
7242                         DRV_LOG(ERR,
7243                                 "match_value differs from match_criteria"
7244                                 " %p[%u] != %p[%u]",
7245                                 match_value, i, match_mask, i);
7246                         return -EINVAL;
7247                 }
7248         }
7249         return 0;
7250 }
7251 #endif
7252
7253 /**
7254  * Add match of ip_version.
7255  *
7256  * @param[in] group
7257  *   Flow group.
7258  * @param[in] headers_v
7259  *   Values header pointer.
7260  * @param[in] headers_m
7261  *   Masks header pointer.
7262  * @param[in] ip_version
7263  *   The IP version to set.
7264  */
7265 static inline void
7266 flow_dv_set_match_ip_version(uint32_t group,
7267                              void *headers_v,
7268                              void *headers_m,
7269                              uint8_t ip_version)
7270 {
7271         if (group == 0)
7272                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7273         else
7274                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7275                          ip_version);
7276         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7277         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7278         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7279 }
7280
7281 /**
7282  * Add Ethernet item to matcher and to the value.
7283  *
7284  * @param[in, out] matcher
7285  *   Flow matcher.
7286  * @param[in, out] key
7287  *   Flow matcher value.
7288  * @param[in] item
7289  *   Flow pattern to translate.
7290  * @param[in] inner
7291  *   Item is inner pattern.
7292  */
7293 static void
7294 flow_dv_translate_item_eth(void *matcher, void *key,
7295                            const struct rte_flow_item *item, int inner,
7296                            uint32_t group)
7297 {
7298         const struct rte_flow_item_eth *eth_m = item->mask;
7299         const struct rte_flow_item_eth *eth_v = item->spec;
7300         const struct rte_flow_item_eth nic_mask = {
7301                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7302                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7303                 .type = RTE_BE16(0xffff),
7304                 .has_vlan = 0,
7305         };
7306         void *hdrs_m;
7307         void *hdrs_v;
7308         char *l24_v;
7309         unsigned int i;
7310
7311         if (!eth_v)
7312                 return;
7313         if (!eth_m)
7314                 eth_m = &nic_mask;
7315         if (inner) {
7316                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7317                                          inner_headers);
7318                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7319         } else {
7320                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7321                                          outer_headers);
7322                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7323         }
7324         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7325                &eth_m->dst, sizeof(eth_m->dst));
7326         /* The value must be in the range of the mask. */
7327         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7328         for (i = 0; i < sizeof(eth_m->dst); ++i)
7329                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7330         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7331                &eth_m->src, sizeof(eth_m->src));
7332         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7333         /* The value must be in the range of the mask. */
7334         for (i = 0; i < sizeof(eth_m->dst); ++i)
7335                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7336         /*
7337          * HW supports match on one Ethertype, the Ethertype following the last
7338          * VLAN tag of the packet (see PRM).
7339          * Set match on ethertype only if ETH header is not followed by VLAN.
7340          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7341          * ethertype, and use ip_version field instead.
7342          * eCPRI over Ether layer will use type value 0xAEFE.
7343          */
7344         if (eth_m->type == 0xFFFF) {
7345                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7346                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7347                 switch (eth_v->type) {
7348                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7349                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7350                         return;
7351                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7352                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7353                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7354                         return;
7355                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7356                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7357                         return;
7358                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7359                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7360                         return;
7361                 default:
7362                         break;
7363                 }
7364         }
7365         if (eth_m->has_vlan) {
7366                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7367                 if (eth_v->has_vlan) {
7368                         /*
7369                          * Here, when also has_more_vlan field in VLAN item is
7370                          * not set, only single-tagged packets will be matched.
7371                          */
7372                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7373                         return;
7374                 }
7375         }
7376         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7377                  rte_be_to_cpu_16(eth_m->type));
7378         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7379         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7380 }
7381
7382 /**
7383  * Add VLAN item to matcher and to the value.
7384  *
7385  * @param[in, out] dev_flow
7386  *   Flow descriptor.
7387  * @param[in, out] matcher
7388  *   Flow matcher.
7389  * @param[in, out] key
7390  *   Flow matcher value.
7391  * @param[in] item
7392  *   Flow pattern to translate.
7393  * @param[in] inner
7394  *   Item is inner pattern.
7395  */
7396 static void
7397 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7398                             void *matcher, void *key,
7399                             const struct rte_flow_item *item,
7400                             int inner, uint32_t group)
7401 {
7402         const struct rte_flow_item_vlan *vlan_m = item->mask;
7403         const struct rte_flow_item_vlan *vlan_v = item->spec;
7404         void *hdrs_m;
7405         void *hdrs_v;
7406         uint16_t tci_m;
7407         uint16_t tci_v;
7408
7409         if (inner) {
7410                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7411                                          inner_headers);
7412                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7413         } else {
7414                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7415                                          outer_headers);
7416                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7417                 /*
7418                  * This is workaround, masks are not supported,
7419                  * and pre-validated.
7420                  */
7421                 if (vlan_v)
7422                         dev_flow->handle->vf_vlan.tag =
7423                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7424         }
7425         /*
7426          * When VLAN item exists in flow, mark packet as tagged,
7427          * even if TCI is not specified.
7428          */
7429         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7430                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7431                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7432         }
7433         if (!vlan_v)
7434                 return;
7435         if (!vlan_m)
7436                 vlan_m = &rte_flow_item_vlan_mask;
7437         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7438         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7439         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7440         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7441         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7442         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7443         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7444         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7445         /*
7446          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7447          * ethertype, and use ip_version field instead.
7448          */
7449         if (vlan_m->inner_type == 0xFFFF) {
7450                 switch (vlan_v->inner_type) {
7451                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7452                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7453                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7454                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7455                         return;
7456                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7457                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7458                         return;
7459                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7460                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7461                         return;
7462                 default:
7463                         break;
7464                 }
7465         }
7466         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7467                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7468                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7469                 /* Only one vlan_tag bit can be set. */
7470                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7471                 return;
7472         }
7473         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7474                  rte_be_to_cpu_16(vlan_m->inner_type));
7475         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7476                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7477 }
7478
7479 /**
7480  * Add IPV4 item to matcher and to the value.
7481  *
7482  * @param[in, out] matcher
7483  *   Flow matcher.
7484  * @param[in, out] key
7485  *   Flow matcher value.
7486  * @param[in] item
7487  *   Flow pattern to translate.
7488  * @param[in] inner
7489  *   Item is inner pattern.
7490  * @param[in] group
7491  *   The group to insert the rule.
7492  */
7493 static void
7494 flow_dv_translate_item_ipv4(void *matcher, void *key,
7495                             const struct rte_flow_item *item,
7496                             int inner, uint32_t group)
7497 {
7498         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7499         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7500         const struct rte_flow_item_ipv4 nic_mask = {
7501                 .hdr = {
7502                         .src_addr = RTE_BE32(0xffffffff),
7503                         .dst_addr = RTE_BE32(0xffffffff),
7504                         .type_of_service = 0xff,
7505                         .next_proto_id = 0xff,
7506                         .time_to_live = 0xff,
7507                 },
7508         };
7509         void *headers_m;
7510         void *headers_v;
7511         char *l24_m;
7512         char *l24_v;
7513         uint8_t tos;
7514
7515         if (inner) {
7516                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7517                                          inner_headers);
7518                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7519         } else {
7520                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7521                                          outer_headers);
7522                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7523         }
7524         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7525         if (!ipv4_v)
7526                 return;
7527         if (!ipv4_m)
7528                 ipv4_m = &nic_mask;
7529         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7530                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7531         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7532                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7533         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7534         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7535         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7536                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7537         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7538                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7539         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7540         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7541         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7542         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7543                  ipv4_m->hdr.type_of_service);
7544         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7545         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7546                  ipv4_m->hdr.type_of_service >> 2);
7547         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7548         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7549                  ipv4_m->hdr.next_proto_id);
7550         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7551                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7552         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7553                  ipv4_m->hdr.time_to_live);
7554         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7555                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7556         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7557                  !!(ipv4_m->hdr.fragment_offset));
7558         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7559                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7560 }
7561
7562 /**
7563  * Add IPV6 item to matcher and to the value.
7564  *
7565  * @param[in, out] matcher
7566  *   Flow matcher.
7567  * @param[in, out] key
7568  *   Flow matcher value.
7569  * @param[in] item
7570  *   Flow pattern to translate.
7571  * @param[in] inner
7572  *   Item is inner pattern.
7573  * @param[in] group
7574  *   The group to insert the rule.
7575  */
7576 static void
7577 flow_dv_translate_item_ipv6(void *matcher, void *key,
7578                             const struct rte_flow_item *item,
7579                             int inner, uint32_t group)
7580 {
7581         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7582         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7583         const struct rte_flow_item_ipv6 nic_mask = {
7584                 .hdr = {
7585                         .src_addr =
7586                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7587                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7588                         .dst_addr =
7589                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7590                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7591                         .vtc_flow = RTE_BE32(0xffffffff),
7592                         .proto = 0xff,
7593                         .hop_limits = 0xff,
7594                 },
7595         };
7596         void *headers_m;
7597         void *headers_v;
7598         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7599         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7600         char *l24_m;
7601         char *l24_v;
7602         uint32_t vtc_m;
7603         uint32_t vtc_v;
7604         int i;
7605         int size;
7606
7607         if (inner) {
7608                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7609                                          inner_headers);
7610                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7611         } else {
7612                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7613                                          outer_headers);
7614                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7615         }
7616         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7617         if (!ipv6_v)
7618                 return;
7619         if (!ipv6_m)
7620                 ipv6_m = &nic_mask;
7621         size = sizeof(ipv6_m->hdr.dst_addr);
7622         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7623                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7624         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7625                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7626         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7627         for (i = 0; i < size; ++i)
7628                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7629         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7630                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7631         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7632                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7633         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7634         for (i = 0; i < size; ++i)
7635                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7636         /* TOS. */
7637         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7638         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7639         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7640         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7641         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7642         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7643         /* Label. */
7644         if (inner) {
7645                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7646                          vtc_m);
7647                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7648                          vtc_v);
7649         } else {
7650                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7651                          vtc_m);
7652                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7653                          vtc_v);
7654         }
7655         /* Protocol. */
7656         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7657                  ipv6_m->hdr.proto);
7658         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7659                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7660         /* Hop limit. */
7661         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7662                  ipv6_m->hdr.hop_limits);
7663         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7664                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7665         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7666                  !!(ipv6_m->has_frag_ext));
7667         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7668                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7669 }
7670
7671 /**
7672  * Add IPV6 fragment extension item to matcher and to the value.
7673  *
7674  * @param[in, out] matcher
7675  *   Flow matcher.
7676  * @param[in, out] key
7677  *   Flow matcher value.
7678  * @param[in] item
7679  *   Flow pattern to translate.
7680  * @param[in] inner
7681  *   Item is inner pattern.
7682  */
7683 static void
7684 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7685                                      const struct rte_flow_item *item,
7686                                      int inner)
7687 {
7688         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7689         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7690         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7691                 .hdr = {
7692                         .next_header = 0xff,
7693                         .frag_data = RTE_BE16(0xffff),
7694                 },
7695         };
7696         void *headers_m;
7697         void *headers_v;
7698
7699         if (inner) {
7700                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7701                                          inner_headers);
7702                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7703         } else {
7704                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7705                                          outer_headers);
7706                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7707         }
7708         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7709         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7710         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7711         if (!ipv6_frag_ext_v)
7712                 return;
7713         if (!ipv6_frag_ext_m)
7714                 ipv6_frag_ext_m = &nic_mask;
7715         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7716                  ipv6_frag_ext_m->hdr.next_header);
7717         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7718                  ipv6_frag_ext_v->hdr.next_header &
7719                  ipv6_frag_ext_m->hdr.next_header);
7720 }
7721
7722 /**
7723  * Add TCP item to matcher and to the value.
7724  *
7725  * @param[in, out] matcher
7726  *   Flow matcher.
7727  * @param[in, out] key
7728  *   Flow matcher value.
7729  * @param[in] item
7730  *   Flow pattern to translate.
7731  * @param[in] inner
7732  *   Item is inner pattern.
7733  */
7734 static void
7735 flow_dv_translate_item_tcp(void *matcher, void *key,
7736                            const struct rte_flow_item *item,
7737                            int inner)
7738 {
7739         const struct rte_flow_item_tcp *tcp_m = item->mask;
7740         const struct rte_flow_item_tcp *tcp_v = item->spec;
7741         void *headers_m;
7742         void *headers_v;
7743
7744         if (inner) {
7745                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7746                                          inner_headers);
7747                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7748         } else {
7749                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7750                                          outer_headers);
7751                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7752         }
7753         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7754         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7755         if (!tcp_v)
7756                 return;
7757         if (!tcp_m)
7758                 tcp_m = &rte_flow_item_tcp_mask;
7759         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7760                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7761         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7762                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7763         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7764                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7765         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7766                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7767         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7768                  tcp_m->hdr.tcp_flags);
7769         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7770                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7771 }
7772
7773 /**
7774  * Add UDP item to matcher and to the value.
7775  *
7776  * @param[in, out] matcher
7777  *   Flow matcher.
7778  * @param[in, out] key
7779  *   Flow matcher value.
7780  * @param[in] item
7781  *   Flow pattern to translate.
7782  * @param[in] inner
7783  *   Item is inner pattern.
7784  */
7785 static void
7786 flow_dv_translate_item_udp(void *matcher, void *key,
7787                            const struct rte_flow_item *item,
7788                            int inner)
7789 {
7790         const struct rte_flow_item_udp *udp_m = item->mask;
7791         const struct rte_flow_item_udp *udp_v = item->spec;
7792         void *headers_m;
7793         void *headers_v;
7794
7795         if (inner) {
7796                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7797                                          inner_headers);
7798                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7799         } else {
7800                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7801                                          outer_headers);
7802                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7803         }
7804         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7805         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7806         if (!udp_v)
7807                 return;
7808         if (!udp_m)
7809                 udp_m = &rte_flow_item_udp_mask;
7810         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7811                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7812         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7813                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7814         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7815                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7816         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7817                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7818 }
7819
7820 /**
7821  * Add GRE optional Key item to matcher and to the value.
7822  *
7823  * @param[in, out] matcher
7824  *   Flow matcher.
7825  * @param[in, out] key
7826  *   Flow matcher value.
7827  * @param[in] item
7828  *   Flow pattern to translate.
7829  * @param[in] inner
7830  *   Item is inner pattern.
7831  */
7832 static void
7833 flow_dv_translate_item_gre_key(void *matcher, void *key,
7834                                    const struct rte_flow_item *item)
7835 {
7836         const rte_be32_t *key_m = item->mask;
7837         const rte_be32_t *key_v = item->spec;
7838         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7839         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7840         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7841
7842         /* GRE K bit must be on and should already be validated */
7843         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7844         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7845         if (!key_v)
7846                 return;
7847         if (!key_m)
7848                 key_m = &gre_key_default_mask;
7849         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7850                  rte_be_to_cpu_32(*key_m) >> 8);
7851         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7852                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7853         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7854                  rte_be_to_cpu_32(*key_m) & 0xFF);
7855         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7856                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7857 }
7858
7859 /**
7860  * Add GRE item to matcher and to the value.
7861  *
7862  * @param[in, out] matcher
7863  *   Flow matcher.
7864  * @param[in, out] key
7865  *   Flow matcher value.
7866  * @param[in] item
7867  *   Flow pattern to translate.
7868  * @param[in] inner
7869  *   Item is inner pattern.
7870  */
7871 static void
7872 flow_dv_translate_item_gre(void *matcher, void *key,
7873                            const struct rte_flow_item *item,
7874                            int inner)
7875 {
7876         const struct rte_flow_item_gre *gre_m = item->mask;
7877         const struct rte_flow_item_gre *gre_v = item->spec;
7878         void *headers_m;
7879         void *headers_v;
7880         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7881         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7882         struct {
7883                 union {
7884                         __extension__
7885                         struct {
7886                                 uint16_t version:3;
7887                                 uint16_t rsvd0:9;
7888                                 uint16_t s_present:1;
7889                                 uint16_t k_present:1;
7890                                 uint16_t rsvd_bit1:1;
7891                                 uint16_t c_present:1;
7892                         };
7893                         uint16_t value;
7894                 };
7895         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7896
7897         if (inner) {
7898                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7899                                          inner_headers);
7900                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7901         } else {
7902                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7903                                          outer_headers);
7904                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7905         }
7906         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7907         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7908         if (!gre_v)
7909                 return;
7910         if (!gre_m)
7911                 gre_m = &rte_flow_item_gre_mask;
7912         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7913                  rte_be_to_cpu_16(gre_m->protocol));
7914         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7915                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7916         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7917         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7918         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7919                  gre_crks_rsvd0_ver_m.c_present);
7920         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7921                  gre_crks_rsvd0_ver_v.c_present &
7922                  gre_crks_rsvd0_ver_m.c_present);
7923         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7924                  gre_crks_rsvd0_ver_m.k_present);
7925         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7926                  gre_crks_rsvd0_ver_v.k_present &
7927                  gre_crks_rsvd0_ver_m.k_present);
7928         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7929                  gre_crks_rsvd0_ver_m.s_present);
7930         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7931                  gre_crks_rsvd0_ver_v.s_present &
7932                  gre_crks_rsvd0_ver_m.s_present);
7933 }
7934
7935 /**
7936  * Add NVGRE item to matcher and to the value.
7937  *
7938  * @param[in, out] matcher
7939  *   Flow matcher.
7940  * @param[in, out] key
7941  *   Flow matcher value.
7942  * @param[in] item
7943  *   Flow pattern to translate.
7944  * @param[in] inner
7945  *   Item is inner pattern.
7946  */
7947 static void
7948 flow_dv_translate_item_nvgre(void *matcher, void *key,
7949                              const struct rte_flow_item *item,
7950                              int inner)
7951 {
7952         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7953         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7954         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7955         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7956         const char *tni_flow_id_m;
7957         const char *tni_flow_id_v;
7958         char *gre_key_m;
7959         char *gre_key_v;
7960         int size;
7961         int i;
7962
7963         /* For NVGRE, GRE header fields must be set with defined values. */
7964         const struct rte_flow_item_gre gre_spec = {
7965                 .c_rsvd0_ver = RTE_BE16(0x2000),
7966                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7967         };
7968         const struct rte_flow_item_gre gre_mask = {
7969                 .c_rsvd0_ver = RTE_BE16(0xB000),
7970                 .protocol = RTE_BE16(UINT16_MAX),
7971         };
7972         const struct rte_flow_item gre_item = {
7973                 .spec = &gre_spec,
7974                 .mask = &gre_mask,
7975                 .last = NULL,
7976         };
7977         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7978         if (!nvgre_v)
7979                 return;
7980         if (!nvgre_m)
7981                 nvgre_m = &rte_flow_item_nvgre_mask;
7982         tni_flow_id_m = (const char *)nvgre_m->tni;
7983         tni_flow_id_v = (const char *)nvgre_v->tni;
7984         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7985         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7986         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7987         memcpy(gre_key_m, tni_flow_id_m, size);
7988         for (i = 0; i < size; ++i)
7989                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7990 }
7991
7992 /**
7993  * Add VXLAN item to matcher and to the value.
7994  *
7995  * @param[in, out] matcher
7996  *   Flow matcher.
7997  * @param[in, out] key
7998  *   Flow matcher value.
7999  * @param[in] item
8000  *   Flow pattern to translate.
8001  * @param[in] inner
8002  *   Item is inner pattern.
8003  */
8004 static void
8005 flow_dv_translate_item_vxlan(void *matcher, void *key,
8006                              const struct rte_flow_item *item,
8007                              int inner)
8008 {
8009         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8010         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8011         void *headers_m;
8012         void *headers_v;
8013         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8014         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8015         char *vni_m;
8016         char *vni_v;
8017         uint16_t dport;
8018         int size;
8019         int i;
8020
8021         if (inner) {
8022                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8023                                          inner_headers);
8024                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8025         } else {
8026                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8027                                          outer_headers);
8028                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8029         }
8030         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8031                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8032         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8033                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8034                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8035         }
8036         if (!vxlan_v)
8037                 return;
8038         if (!vxlan_m)
8039                 vxlan_m = &rte_flow_item_vxlan_mask;
8040         size = sizeof(vxlan_m->vni);
8041         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8042         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8043         memcpy(vni_m, vxlan_m->vni, size);
8044         for (i = 0; i < size; ++i)
8045                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8046 }
8047
8048 /**
8049  * Add VXLAN-GPE item to matcher and to the value.
8050  *
8051  * @param[in, out] matcher
8052  *   Flow matcher.
8053  * @param[in, out] key
8054  *   Flow matcher value.
8055  * @param[in] item
8056  *   Flow pattern to translate.
8057  * @param[in] inner
8058  *   Item is inner pattern.
8059  */
8060
8061 static void
8062 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8063                                  const struct rte_flow_item *item, int inner)
8064 {
8065         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8066         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8067         void *headers_m;
8068         void *headers_v;
8069         void *misc_m =
8070                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8071         void *misc_v =
8072                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8073         char *vni_m;
8074         char *vni_v;
8075         uint16_t dport;
8076         int size;
8077         int i;
8078         uint8_t flags_m = 0xff;
8079         uint8_t flags_v = 0xc;
8080
8081         if (inner) {
8082                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8083                                          inner_headers);
8084                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8085         } else {
8086                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8087                                          outer_headers);
8088                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8089         }
8090         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8091                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8092         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8093                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8094                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8095         }
8096         if (!vxlan_v)
8097                 return;
8098         if (!vxlan_m)
8099                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8100         size = sizeof(vxlan_m->vni);
8101         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8102         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8103         memcpy(vni_m, vxlan_m->vni, size);
8104         for (i = 0; i < size; ++i)
8105                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8106         if (vxlan_m->flags) {
8107                 flags_m = vxlan_m->flags;
8108                 flags_v = vxlan_v->flags;
8109         }
8110         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8111         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8112         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8113                  vxlan_m->protocol);
8114         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8115                  vxlan_v->protocol);
8116 }
8117
8118 /**
8119  * Add Geneve item to matcher and to the value.
8120  *
8121  * @param[in, out] matcher
8122  *   Flow matcher.
8123  * @param[in, out] key
8124  *   Flow matcher value.
8125  * @param[in] item
8126  *   Flow pattern to translate.
8127  * @param[in] inner
8128  *   Item is inner pattern.
8129  */
8130
8131 static void
8132 flow_dv_translate_item_geneve(void *matcher, void *key,
8133                               const struct rte_flow_item *item, int inner)
8134 {
8135         const struct rte_flow_item_geneve *geneve_m = item->mask;
8136         const struct rte_flow_item_geneve *geneve_v = item->spec;
8137         void *headers_m;
8138         void *headers_v;
8139         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8140         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8141         uint16_t dport;
8142         uint16_t gbhdr_m;
8143         uint16_t gbhdr_v;
8144         char *vni_m;
8145         char *vni_v;
8146         size_t size, i;
8147
8148         if (inner) {
8149                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8150                                          inner_headers);
8151                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8152         } else {
8153                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8154                                          outer_headers);
8155                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8156         }
8157         dport = MLX5_UDP_PORT_GENEVE;
8158         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8159                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8160                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8161         }
8162         if (!geneve_v)
8163                 return;
8164         if (!geneve_m)
8165                 geneve_m = &rte_flow_item_geneve_mask;
8166         size = sizeof(geneve_m->vni);
8167         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8168         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8169         memcpy(vni_m, geneve_m->vni, size);
8170         for (i = 0; i < size; ++i)
8171                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8172         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8173                  rte_be_to_cpu_16(geneve_m->protocol));
8174         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8175                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8176         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8177         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8178         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8179                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8180         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8181                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8182         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8183                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8184         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8185                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8186                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8187 }
8188
8189 /**
8190  * Create Geneve TLV option resource.
8191  *
8192  * @param dev[in, out]
8193  *   Pointer to rte_eth_dev structure.
8194  * @param[in, out] tag_be24
8195  *   Tag value in big endian then R-shift 8.
8196  * @parm[in, out] dev_flow
8197  *   Pointer to the dev_flow.
8198  * @param[out] error
8199  *   pointer to error structure.
8200  *
8201  * @return
8202  *   0 on success otherwise -errno and errno is set.
8203  */
8204
8205 int
8206 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8207                                              const struct rte_flow_item *item,
8208                                              struct rte_flow_error *error)
8209 {
8210         struct mlx5_priv *priv = dev->data->dev_private;
8211         struct mlx5_dev_ctx_shared *sh = priv->sh;
8212         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8213                         sh->geneve_tlv_option_resource;
8214         struct mlx5_devx_obj *obj;
8215         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8216         int ret = 0;
8217
8218         if (!geneve_opt_v)
8219                 return -1;
8220         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8221         if (geneve_opt_resource != NULL) {
8222                 if (geneve_opt_resource->option_class ==
8223                         geneve_opt_v->option_class &&
8224                         geneve_opt_resource->option_type ==
8225                         geneve_opt_v->option_type &&
8226                         geneve_opt_resource->length ==
8227                         geneve_opt_v->option_len) {
8228                         /* We already have GENVE TLV option obj allocated. */
8229                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8230                                            __ATOMIC_RELAXED);
8231                 } else {
8232                         ret = rte_flow_error_set(error, ENOMEM,
8233                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8234                                 "Only one GENEVE TLV option supported");
8235                         goto exit;
8236                 }
8237         } else {
8238                 /* Create a GENEVE TLV object and resource. */
8239                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8240                                 geneve_opt_v->option_class,
8241                                 geneve_opt_v->option_type,
8242                                 geneve_opt_v->option_len);
8243                 if (!obj) {
8244                         ret = rte_flow_error_set(error, ENODATA,
8245                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8246                                 "Failed to create GENEVE TLV Devx object");
8247                         goto exit;
8248                 }
8249                 sh->geneve_tlv_option_resource =
8250                                 mlx5_malloc(MLX5_MEM_ZERO,
8251                                                 sizeof(*geneve_opt_resource),
8252                                                 0, SOCKET_ID_ANY);
8253                 if (!sh->geneve_tlv_option_resource) {
8254                         claim_zero(mlx5_devx_cmd_destroy(obj));
8255                         ret = rte_flow_error_set(error, ENOMEM,
8256                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8257                                 "GENEVE TLV object memory allocation failed");
8258                         goto exit;
8259                 }
8260                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8261                 geneve_opt_resource->obj = obj;
8262                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8263                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8264                 geneve_opt_resource->length = geneve_opt_v->option_len;
8265                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8266                                 __ATOMIC_RELAXED);
8267         }
8268 exit:
8269         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8270         return ret;
8271 }
8272
8273 /**
8274  * Add Geneve TLV option item to matcher.
8275  *
8276  * @param[in, out] dev
8277  *   Pointer to rte_eth_dev structure.
8278  * @param[in, out] matcher
8279  *   Flow matcher.
8280  * @param[in, out] key
8281  *   Flow matcher value.
8282  * @param[in] item
8283  *   Flow pattern to translate.
8284  * @param[out] error
8285  *   Pointer to error structure.
8286  */
8287 static int
8288 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8289                                   void *key, const struct rte_flow_item *item,
8290                                   struct rte_flow_error *error)
8291 {
8292         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8293         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8294         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8295         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8296         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8297                         misc_parameters_3);
8298         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8299         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8300         int ret = 0;
8301
8302         if (!geneve_opt_v)
8303                 return -1;
8304         if (!geneve_opt_m)
8305                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8306         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8307                                                            error);
8308         if (ret) {
8309                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8310                 return ret;
8311         }
8312         /*
8313          * Set the option length in GENEVE header if not requested.
8314          * The GENEVE TLV option length is expressed by the option length field
8315          * in the GENEVE header.
8316          * If the option length was not requested but the GENEVE TLV option item
8317          * is present we set the option length field implicitly.
8318          */
8319         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8320                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8321                          MLX5_GENEVE_OPTLEN_MASK);
8322                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8323                          geneve_opt_v->option_len + 1);
8324         }
8325         /* Set the data. */
8326         if (geneve_opt_v->data) {
8327                 memcpy(&opt_data_key, geneve_opt_v->data,
8328                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8329                                 sizeof(opt_data_key)));
8330                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8331                                 sizeof(opt_data_key));
8332                 memcpy(&opt_data_mask, geneve_opt_m->data,
8333                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8334                                 sizeof(opt_data_mask)));
8335                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8336                                 sizeof(opt_data_mask));
8337                 MLX5_SET(fte_match_set_misc3, misc3_m,
8338                                 geneve_tlv_option_0_data,
8339                                 rte_be_to_cpu_32(opt_data_mask));
8340                 MLX5_SET(fte_match_set_misc3, misc3_v,
8341                                 geneve_tlv_option_0_data,
8342                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8343         }
8344         return ret;
8345 }
8346
8347 /**
8348  * Add MPLS item to matcher and to the value.
8349  *
8350  * @param[in, out] matcher
8351  *   Flow matcher.
8352  * @param[in, out] key
8353  *   Flow matcher value.
8354  * @param[in] item
8355  *   Flow pattern to translate.
8356  * @param[in] prev_layer
8357  *   The protocol layer indicated in previous item.
8358  * @param[in] inner
8359  *   Item is inner pattern.
8360  */
8361 static void
8362 flow_dv_translate_item_mpls(void *matcher, void *key,
8363                             const struct rte_flow_item *item,
8364                             uint64_t prev_layer,
8365                             int inner)
8366 {
8367         const uint32_t *in_mpls_m = item->mask;
8368         const uint32_t *in_mpls_v = item->spec;
8369         uint32_t *out_mpls_m = 0;
8370         uint32_t *out_mpls_v = 0;
8371         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8372         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8373         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8374                                      misc_parameters_2);
8375         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8376         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8377         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8378
8379         switch (prev_layer) {
8380         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8381                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8382                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8383                          MLX5_UDP_PORT_MPLS);
8384                 break;
8385         case MLX5_FLOW_LAYER_GRE:
8386                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8387                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8388                          RTE_ETHER_TYPE_MPLS);
8389                 break;
8390         default:
8391                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8392                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8393                          IPPROTO_MPLS);
8394                 break;
8395         }
8396         if (!in_mpls_v)
8397                 return;
8398         if (!in_mpls_m)
8399                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8400         switch (prev_layer) {
8401         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8402                 out_mpls_m =
8403                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8404                                                  outer_first_mpls_over_udp);
8405                 out_mpls_v =
8406                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8407                                                  outer_first_mpls_over_udp);
8408                 break;
8409         case MLX5_FLOW_LAYER_GRE:
8410                 out_mpls_m =
8411                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8412                                                  outer_first_mpls_over_gre);
8413                 out_mpls_v =
8414                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8415                                                  outer_first_mpls_over_gre);
8416                 break;
8417         default:
8418                 /* Inner MPLS not over GRE is not supported. */
8419                 if (!inner) {
8420                         out_mpls_m =
8421                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8422                                                          misc2_m,
8423                                                          outer_first_mpls);
8424                         out_mpls_v =
8425                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8426                                                          misc2_v,
8427                                                          outer_first_mpls);
8428                 }
8429                 break;
8430         }
8431         if (out_mpls_m && out_mpls_v) {
8432                 *out_mpls_m = *in_mpls_m;
8433                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8434         }
8435 }
8436
8437 /**
8438  * Add metadata register item to matcher
8439  *
8440  * @param[in, out] matcher
8441  *   Flow matcher.
8442  * @param[in, out] key
8443  *   Flow matcher value.
8444  * @param[in] reg_type
8445  *   Type of device metadata register
8446  * @param[in] value
8447  *   Register value
8448  * @param[in] mask
8449  *   Register mask
8450  */
8451 static void
8452 flow_dv_match_meta_reg(void *matcher, void *key,
8453                        enum modify_reg reg_type,
8454                        uint32_t data, uint32_t mask)
8455 {
8456         void *misc2_m =
8457                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8458         void *misc2_v =
8459                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8460         uint32_t temp;
8461
8462         data &= mask;
8463         switch (reg_type) {
8464         case REG_A:
8465                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8466                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8467                 break;
8468         case REG_B:
8469                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8470                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8471                 break;
8472         case REG_C_0:
8473                 /*
8474                  * The metadata register C0 field might be divided into
8475                  * source vport index and META item value, we should set
8476                  * this field according to specified mask, not as whole one.
8477                  */
8478                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8479                 temp |= mask;
8480                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8481                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8482                 temp &= ~mask;
8483                 temp |= data;
8484                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8485                 break;
8486         case REG_C_1:
8487                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8488                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8489                 break;
8490         case REG_C_2:
8491                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8492                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8493                 break;
8494         case REG_C_3:
8495                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8496                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8497                 break;
8498         case REG_C_4:
8499                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8500                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8501                 break;
8502         case REG_C_5:
8503                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8504                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8505                 break;
8506         case REG_C_6:
8507                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8508                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8509                 break;
8510         case REG_C_7:
8511                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8512                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8513                 break;
8514         default:
8515                 MLX5_ASSERT(false);
8516                 break;
8517         }
8518 }
8519
8520 /**
8521  * Add MARK item to matcher
8522  *
8523  * @param[in] dev
8524  *   The device to configure through.
8525  * @param[in, out] matcher
8526  *   Flow matcher.
8527  * @param[in, out] key
8528  *   Flow matcher value.
8529  * @param[in] item
8530  *   Flow pattern to translate.
8531  */
8532 static void
8533 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8534                             void *matcher, void *key,
8535                             const struct rte_flow_item *item)
8536 {
8537         struct mlx5_priv *priv = dev->data->dev_private;
8538         const struct rte_flow_item_mark *mark;
8539         uint32_t value;
8540         uint32_t mask;
8541
8542         mark = item->mask ? (const void *)item->mask :
8543                             &rte_flow_item_mark_mask;
8544         mask = mark->id & priv->sh->dv_mark_mask;
8545         mark = (const void *)item->spec;
8546         MLX5_ASSERT(mark);
8547         value = mark->id & priv->sh->dv_mark_mask & mask;
8548         if (mask) {
8549                 enum modify_reg reg;
8550
8551                 /* Get the metadata register index for the mark. */
8552                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8553                 MLX5_ASSERT(reg > 0);
8554                 if (reg == REG_C_0) {
8555                         struct mlx5_priv *priv = dev->data->dev_private;
8556                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8557                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8558
8559                         mask &= msk_c0;
8560                         mask <<= shl_c0;
8561                         value <<= shl_c0;
8562                 }
8563                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8564         }
8565 }
8566
8567 /**
8568  * Add META item to matcher
8569  *
8570  * @param[in] dev
8571  *   The devich to configure through.
8572  * @param[in, out] matcher
8573  *   Flow matcher.
8574  * @param[in, out] key
8575  *   Flow matcher value.
8576  * @param[in] attr
8577  *   Attributes of flow that includes this item.
8578  * @param[in] item
8579  *   Flow pattern to translate.
8580  */
8581 static void
8582 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8583                             void *matcher, void *key,
8584                             const struct rte_flow_attr *attr,
8585                             const struct rte_flow_item *item)
8586 {
8587         const struct rte_flow_item_meta *meta_m;
8588         const struct rte_flow_item_meta *meta_v;
8589
8590         meta_m = (const void *)item->mask;
8591         if (!meta_m)
8592                 meta_m = &rte_flow_item_meta_mask;
8593         meta_v = (const void *)item->spec;
8594         if (meta_v) {
8595                 int reg;
8596                 uint32_t value = meta_v->data;
8597                 uint32_t mask = meta_m->data;
8598
8599                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8600                 if (reg < 0)
8601                         return;
8602                 MLX5_ASSERT(reg != REG_NON);
8603                 /*
8604                  * In datapath code there is no endianness
8605                  * coversions for perfromance reasons, all
8606                  * pattern conversions are done in rte_flow.
8607                  */
8608                 value = rte_cpu_to_be_32(value);
8609                 mask = rte_cpu_to_be_32(mask);
8610                 if (reg == REG_C_0) {
8611                         struct mlx5_priv *priv = dev->data->dev_private;
8612                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8613                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8614 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8615                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8616
8617                         value >>= shr_c0;
8618                         mask >>= shr_c0;
8619 #endif
8620                         value <<= shl_c0;
8621                         mask <<= shl_c0;
8622                         MLX5_ASSERT(msk_c0);
8623                         MLX5_ASSERT(!(~msk_c0 & mask));
8624                 }
8625                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8626         }
8627 }
8628
8629 /**
8630  * Add vport metadata Reg C0 item to matcher
8631  *
8632  * @param[in, out] matcher
8633  *   Flow matcher.
8634  * @param[in, out] key
8635  *   Flow matcher value.
8636  * @param[in] reg
8637  *   Flow pattern to translate.
8638  */
8639 static void
8640 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8641                                   uint32_t value, uint32_t mask)
8642 {
8643         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8644 }
8645
8646 /**
8647  * Add tag item to matcher
8648  *
8649  * @param[in] dev
8650  *   The devich to configure through.
8651  * @param[in, out] matcher
8652  *   Flow matcher.
8653  * @param[in, out] key
8654  *   Flow matcher value.
8655  * @param[in] item
8656  *   Flow pattern to translate.
8657  */
8658 static void
8659 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8660                                 void *matcher, void *key,
8661                                 const struct rte_flow_item *item)
8662 {
8663         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8664         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8665         uint32_t mask, value;
8666
8667         MLX5_ASSERT(tag_v);
8668         value = tag_v->data;
8669         mask = tag_m ? tag_m->data : UINT32_MAX;
8670         if (tag_v->id == REG_C_0) {
8671                 struct mlx5_priv *priv = dev->data->dev_private;
8672                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8673                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8674
8675                 mask &= msk_c0;
8676                 mask <<= shl_c0;
8677                 value <<= shl_c0;
8678         }
8679         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8680 }
8681
8682 /**
8683  * Add TAG item to matcher
8684  *
8685  * @param[in] dev
8686  *   The devich to configure through.
8687  * @param[in, out] matcher
8688  *   Flow matcher.
8689  * @param[in, out] key
8690  *   Flow matcher value.
8691  * @param[in] item
8692  *   Flow pattern to translate.
8693  */
8694 static void
8695 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8696                            void *matcher, void *key,
8697                            const struct rte_flow_item *item)
8698 {
8699         const struct rte_flow_item_tag *tag_v = item->spec;
8700         const struct rte_flow_item_tag *tag_m = item->mask;
8701         enum modify_reg reg;
8702
8703         MLX5_ASSERT(tag_v);
8704         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8705         /* Get the metadata register index for the tag. */
8706         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8707         MLX5_ASSERT(reg > 0);
8708         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8709 }
8710
8711 /**
8712  * Add source vport match to the specified matcher.
8713  *
8714  * @param[in, out] matcher
8715  *   Flow matcher.
8716  * @param[in, out] key
8717  *   Flow matcher value.
8718  * @param[in] port
8719  *   Source vport value to match
8720  * @param[in] mask
8721  *   Mask
8722  */
8723 static void
8724 flow_dv_translate_item_source_vport(void *matcher, void *key,
8725                                     int16_t port, uint16_t mask)
8726 {
8727         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8728         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8729
8730         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8731         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8732 }
8733
8734 /**
8735  * Translate port-id item to eswitch match on  port-id.
8736  *
8737  * @param[in] dev
8738  *   The devich to configure through.
8739  * @param[in, out] matcher
8740  *   Flow matcher.
8741  * @param[in, out] key
8742  *   Flow matcher value.
8743  * @param[in] item
8744  *   Flow pattern to translate.
8745  * @param[in]
8746  *   Flow attributes.
8747  *
8748  * @return
8749  *   0 on success, a negative errno value otherwise.
8750  */
8751 static int
8752 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8753                                void *key, const struct rte_flow_item *item,
8754                                const struct rte_flow_attr *attr)
8755 {
8756         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8757         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8758         struct mlx5_priv *priv;
8759         uint16_t mask, id;
8760
8761         mask = pid_m ? pid_m->id : 0xffff;
8762         id = pid_v ? pid_v->id : dev->data->port_id;
8763         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8764         if (!priv)
8765                 return -rte_errno;
8766         /*
8767          * Translate to vport field or to metadata, depending on mode.
8768          * Kernel can use either misc.source_port or half of C0 metadata
8769          * register.
8770          */
8771         if (priv->vport_meta_mask) {
8772                 /*
8773                  * Provide the hint for SW steering library
8774                  * to insert the flow into ingress domain and
8775                  * save the extra vport match.
8776                  */
8777                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8778                     priv->pf_bond < 0 && attr->transfer)
8779                         flow_dv_translate_item_source_vport
8780                                 (matcher, key, priv->vport_id, mask);
8781                 /*
8782                  * We should always set the vport metadata register,
8783                  * otherwise the SW steering library can drop
8784                  * the rule if wire vport metadata value is not zero,
8785                  * it depends on kernel configuration.
8786                  */
8787                 flow_dv_translate_item_meta_vport(matcher, key,
8788                                                   priv->vport_meta_tag,
8789                                                   priv->vport_meta_mask);
8790         } else {
8791                 flow_dv_translate_item_source_vport(matcher, key,
8792                                                     priv->vport_id, mask);
8793         }
8794         return 0;
8795 }
8796
8797 /**
8798  * Add ICMP6 item to matcher and to the value.
8799  *
8800  * @param[in, out] matcher
8801  *   Flow matcher.
8802  * @param[in, out] key
8803  *   Flow matcher value.
8804  * @param[in] item
8805  *   Flow pattern to translate.
8806  * @param[in] inner
8807  *   Item is inner pattern.
8808  */
8809 static void
8810 flow_dv_translate_item_icmp6(void *matcher, void *key,
8811                               const struct rte_flow_item *item,
8812                               int inner)
8813 {
8814         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8815         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8816         void *headers_m;
8817         void *headers_v;
8818         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8819                                      misc_parameters_3);
8820         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8821         if (inner) {
8822                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8823                                          inner_headers);
8824                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8825         } else {
8826                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8827                                          outer_headers);
8828                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8829         }
8830         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8831         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8832         if (!icmp6_v)
8833                 return;
8834         if (!icmp6_m)
8835                 icmp6_m = &rte_flow_item_icmp6_mask;
8836         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8837         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8838                  icmp6_v->type & icmp6_m->type);
8839         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8840         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8841                  icmp6_v->code & icmp6_m->code);
8842 }
8843
8844 /**
8845  * Add ICMP item to matcher and to the value.
8846  *
8847  * @param[in, out] matcher
8848  *   Flow matcher.
8849  * @param[in, out] key
8850  *   Flow matcher value.
8851  * @param[in] item
8852  *   Flow pattern to translate.
8853  * @param[in] inner
8854  *   Item is inner pattern.
8855  */
8856 static void
8857 flow_dv_translate_item_icmp(void *matcher, void *key,
8858                             const struct rte_flow_item *item,
8859                             int inner)
8860 {
8861         const struct rte_flow_item_icmp *icmp_m = item->mask;
8862         const struct rte_flow_item_icmp *icmp_v = item->spec;
8863         uint32_t icmp_header_data_m = 0;
8864         uint32_t icmp_header_data_v = 0;
8865         void *headers_m;
8866         void *headers_v;
8867         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8868                                      misc_parameters_3);
8869         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8870         if (inner) {
8871                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8872                                          inner_headers);
8873                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8874         } else {
8875                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8876                                          outer_headers);
8877                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8878         }
8879         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8880         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8881         if (!icmp_v)
8882                 return;
8883         if (!icmp_m)
8884                 icmp_m = &rte_flow_item_icmp_mask;
8885         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8886                  icmp_m->hdr.icmp_type);
8887         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8888                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8889         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8890                  icmp_m->hdr.icmp_code);
8891         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8892                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8893         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8894         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8895         if (icmp_header_data_m) {
8896                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8897                 icmp_header_data_v |=
8898                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8899                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8900                          icmp_header_data_m);
8901                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8902                          icmp_header_data_v & icmp_header_data_m);
8903         }
8904 }
8905
8906 /**
8907  * Add GTP item to matcher and to the value.
8908  *
8909  * @param[in, out] matcher
8910  *   Flow matcher.
8911  * @param[in, out] key
8912  *   Flow matcher value.
8913  * @param[in] item
8914  *   Flow pattern to translate.
8915  * @param[in] inner
8916  *   Item is inner pattern.
8917  */
8918 static void
8919 flow_dv_translate_item_gtp(void *matcher, void *key,
8920                            const struct rte_flow_item *item, int inner)
8921 {
8922         const struct rte_flow_item_gtp *gtp_m = item->mask;
8923         const struct rte_flow_item_gtp *gtp_v = item->spec;
8924         void *headers_m;
8925         void *headers_v;
8926         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8927                                      misc_parameters_3);
8928         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8929         uint16_t dport = RTE_GTPU_UDP_PORT;
8930
8931         if (inner) {
8932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8933                                          inner_headers);
8934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8935         } else {
8936                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8937                                          outer_headers);
8938                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8939         }
8940         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8941                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8942                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8943         }
8944         if (!gtp_v)
8945                 return;
8946         if (!gtp_m)
8947                 gtp_m = &rte_flow_item_gtp_mask;
8948         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8949                  gtp_m->v_pt_rsv_flags);
8950         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8951                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8952         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8953         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8954                  gtp_v->msg_type & gtp_m->msg_type);
8955         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8956                  rte_be_to_cpu_32(gtp_m->teid));
8957         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8958                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8959 }
8960
8961 /**
8962  * Add GTP PSC item to matcher.
8963  *
8964  * @param[in, out] matcher
8965  *   Flow matcher.
8966  * @param[in, out] key
8967  *   Flow matcher value.
8968  * @param[in] item
8969  *   Flow pattern to translate.
8970  */
8971 static int
8972 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8973                                const struct rte_flow_item *item)
8974 {
8975         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8976         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8977         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8978                         misc_parameters_3);
8979         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8980         union {
8981                 uint32_t w32;
8982                 struct {
8983                         uint16_t seq_num;
8984                         uint8_t npdu_num;
8985                         uint8_t next_ext_header_type;
8986                 };
8987         } dw_2;
8988         uint8_t gtp_flags;
8989
8990         /* Always set E-flag match on one, regardless of GTP item settings. */
8991         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8992         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8993         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8994         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8995         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8996         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8997         /*Set next extension header type. */
8998         dw_2.seq_num = 0;
8999         dw_2.npdu_num = 0;
9000         dw_2.next_ext_header_type = 0xff;
9001         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9002                  rte_cpu_to_be_32(dw_2.w32));
9003         dw_2.seq_num = 0;
9004         dw_2.npdu_num = 0;
9005         dw_2.next_ext_header_type = 0x85;
9006         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9007                  rte_cpu_to_be_32(dw_2.w32));
9008         if (gtp_psc_v) {
9009                 union {
9010                         uint32_t w32;
9011                         struct {
9012                                 uint8_t len;
9013                                 uint8_t type_flags;
9014                                 uint8_t qfi;
9015                                 uint8_t reserved;
9016                         };
9017                 } dw_0;
9018
9019                 /*Set extension header PDU type and Qos. */
9020                 if (!gtp_psc_m)
9021                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9022                 dw_0.w32 = 0;
9023                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9024                 dw_0.qfi = gtp_psc_m->qfi;
9025                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9026                          rte_cpu_to_be_32(dw_0.w32));
9027                 dw_0.w32 = 0;
9028                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9029                                                         gtp_psc_m->pdu_type);
9030                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9031                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9032                          rte_cpu_to_be_32(dw_0.w32));
9033         }
9034         return 0;
9035 }
9036
9037 /**
9038  * Add eCPRI item to matcher and to the value.
9039  *
9040  * @param[in] dev
9041  *   The devich to configure through.
9042  * @param[in, out] matcher
9043  *   Flow matcher.
9044  * @param[in, out] key
9045  *   Flow matcher value.
9046  * @param[in] item
9047  *   Flow pattern to translate.
9048  * @param[in] samples
9049  *   Sample IDs to be used in the matching.
9050  */
9051 static void
9052 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9053                              void *key, const struct rte_flow_item *item)
9054 {
9055         struct mlx5_priv *priv = dev->data->dev_private;
9056         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9057         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9058         struct rte_ecpri_common_hdr common;
9059         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9060                                      misc_parameters_4);
9061         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9062         uint32_t *samples;
9063         void *dw_m;
9064         void *dw_v;
9065
9066         if (!ecpri_v)
9067                 return;
9068         if (!ecpri_m)
9069                 ecpri_m = &rte_flow_item_ecpri_mask;
9070         /*
9071          * Maximal four DW samples are supported in a single matching now.
9072          * Two are used now for a eCPRI matching:
9073          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9074          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9075          *    if any.
9076          */
9077         if (!ecpri_m->hdr.common.u32)
9078                 return;
9079         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9080         /* Need to take the whole DW as the mask to fill the entry. */
9081         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9082                             prog_sample_field_value_0);
9083         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9084                             prog_sample_field_value_0);
9085         /* Already big endian (network order) in the header. */
9086         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9087         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9088         /* Sample#0, used for matching type, offset 0. */
9089         MLX5_SET(fte_match_set_misc4, misc4_m,
9090                  prog_sample_field_id_0, samples[0]);
9091         /* It makes no sense to set the sample ID in the mask field. */
9092         MLX5_SET(fte_match_set_misc4, misc4_v,
9093                  prog_sample_field_id_0, samples[0]);
9094         /*
9095          * Checking if message body part needs to be matched.
9096          * Some wildcard rules only matching type field should be supported.
9097          */
9098         if (ecpri_m->hdr.dummy[0]) {
9099                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9100                 switch (common.type) {
9101                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9102                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9103                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9104                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9105                                             prog_sample_field_value_1);
9106                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9107                                             prog_sample_field_value_1);
9108                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9109                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9110                                             ecpri_m->hdr.dummy[0];
9111                         /* Sample#1, to match message body, offset 4. */
9112                         MLX5_SET(fte_match_set_misc4, misc4_m,
9113                                  prog_sample_field_id_1, samples[1]);
9114                         MLX5_SET(fte_match_set_misc4, misc4_v,
9115                                  prog_sample_field_id_1, samples[1]);
9116                         break;
9117                 default:
9118                         /* Others, do not match any sample ID. */
9119                         break;
9120                 }
9121         }
9122 }
9123
9124 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9125
9126 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9127         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9128                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9129
9130 /**
9131  * Calculate flow matcher enable bitmap.
9132  *
9133  * @param match_criteria
9134  *   Pointer to flow matcher criteria.
9135  *
9136  * @return
9137  *   Bitmap of enabled fields.
9138  */
9139 static uint8_t
9140 flow_dv_matcher_enable(uint32_t *match_criteria)
9141 {
9142         uint8_t match_criteria_enable;
9143
9144         match_criteria_enable =
9145                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9146                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9147         match_criteria_enable |=
9148                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9149                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9150         match_criteria_enable |=
9151                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9152                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9153         match_criteria_enable |=
9154                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9155                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9156         match_criteria_enable |=
9157                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9158                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9159         match_criteria_enable |=
9160                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9161                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9162         return match_criteria_enable;
9163 }
9164
9165 struct mlx5_hlist_entry *
9166 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9167 {
9168         struct mlx5_dev_ctx_shared *sh = list->ctx;
9169         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9170         struct rte_eth_dev *dev = ctx->dev;
9171         struct mlx5_flow_tbl_data_entry *tbl_data;
9172         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9173         struct rte_flow_error *error = ctx->error;
9174         union mlx5_flow_tbl_key key = { .v64 = key64 };
9175         struct mlx5_flow_tbl_resource *tbl;
9176         void *domain;
9177         uint32_t idx = 0;
9178         int ret;
9179
9180         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9181         if (!tbl_data) {
9182                 rte_flow_error_set(error, ENOMEM,
9183                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9184                                    NULL,
9185                                    "cannot allocate flow table data entry");
9186                 return NULL;
9187         }
9188         tbl_data->idx = idx;
9189         tbl_data->tunnel = tt_prm->tunnel;
9190         tbl_data->group_id = tt_prm->group_id;
9191         tbl_data->external = !!tt_prm->external;
9192         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9193         tbl_data->is_egress = !!key.direction;
9194         tbl_data->is_transfer = !!key.domain;
9195         tbl_data->dummy = !!key.dummy;
9196         tbl_data->table_id = key.table_id;
9197         tbl = &tbl_data->tbl;
9198         if (key.dummy)
9199                 return &tbl_data->entry;
9200         if (key.domain)
9201                 domain = sh->fdb_domain;
9202         else if (key.direction)
9203                 domain = sh->tx_domain;
9204         else
9205                 domain = sh->rx_domain;
9206         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9207         if (ret) {
9208                 rte_flow_error_set(error, ENOMEM,
9209                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9210                                    NULL, "cannot create flow table object");
9211                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9212                 return NULL;
9213         }
9214         if (key.table_id) {
9215                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9216                                         (tbl->obj, &tbl_data->jump.action);
9217                 if (ret) {
9218                         rte_flow_error_set(error, ENOMEM,
9219                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9220                                            NULL,
9221                                            "cannot create flow jump action");
9222                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9223                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9224                         return NULL;
9225                 }
9226         }
9227         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9228               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9229               key.table_id);
9230         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9231                              flow_dv_matcher_create_cb,
9232                              flow_dv_matcher_match_cb,
9233                              flow_dv_matcher_remove_cb);
9234         return &tbl_data->entry;
9235 }
9236
9237 int
9238 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9239                      struct mlx5_hlist_entry *entry, uint64_t key64,
9240                      void *cb_ctx __rte_unused)
9241 {
9242         struct mlx5_flow_tbl_data_entry *tbl_data =
9243                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9244         union mlx5_flow_tbl_key key = { .v64 = key64 };
9245
9246         return tbl_data->table_id != key.table_id ||
9247                tbl_data->dummy != key.dummy ||
9248                tbl_data->is_transfer != key.domain ||
9249                tbl_data->is_egress != key.direction;
9250 }
9251
9252 /**
9253  * Get a flow table.
9254  *
9255  * @param[in, out] dev
9256  *   Pointer to rte_eth_dev structure.
9257  * @param[in] table_id
9258  *   Table id to use.
9259  * @param[in] egress
9260  *   Direction of the table.
9261  * @param[in] transfer
9262  *   E-Switch or NIC flow.
9263  * @param[in] dummy
9264  *   Dummy entry for dv API.
9265  * @param[out] error
9266  *   pointer to error structure.
9267  *
9268  * @return
9269  *   Returns tables resource based on the index, NULL in case of failed.
9270  */
9271 struct mlx5_flow_tbl_resource *
9272 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9273                          uint32_t table_id, uint8_t egress,
9274                          uint8_t transfer,
9275                          bool external,
9276                          const struct mlx5_flow_tunnel *tunnel,
9277                          uint32_t group_id, uint8_t dummy,
9278                          struct rte_flow_error *error)
9279 {
9280         struct mlx5_priv *priv = dev->data->dev_private;
9281         union mlx5_flow_tbl_key table_key = {
9282                 {
9283                         .table_id = table_id,
9284                         .dummy = dummy,
9285                         .domain = !!transfer,
9286                         .direction = !!egress,
9287                 }
9288         };
9289         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9290                 .tunnel = tunnel,
9291                 .group_id = group_id,
9292                 .external = external,
9293         };
9294         struct mlx5_flow_cb_ctx ctx = {
9295                 .dev = dev,
9296                 .error = error,
9297                 .data = &tt_prm,
9298         };
9299         struct mlx5_hlist_entry *entry;
9300         struct mlx5_flow_tbl_data_entry *tbl_data;
9301
9302         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9303         if (!entry) {
9304                 rte_flow_error_set(error, ENOMEM,
9305                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9306                                    "cannot get table");
9307                 return NULL;
9308         }
9309         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9310                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9311         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9312         return &tbl_data->tbl;
9313 }
9314
9315 void
9316 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9317                       struct mlx5_hlist_entry *entry)
9318 {
9319         struct mlx5_dev_ctx_shared *sh = list->ctx;
9320         struct mlx5_flow_tbl_data_entry *tbl_data =
9321                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9322
9323         MLX5_ASSERT(entry && sh);
9324         if (tbl_data->jump.action)
9325                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9326         if (tbl_data->tbl.obj)
9327                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9328         if (tbl_data->tunnel_offload && tbl_data->external) {
9329                 struct mlx5_hlist_entry *he;
9330                 struct mlx5_hlist *tunnel_grp_hash;
9331                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9332                 union tunnel_tbl_key tunnel_key = {
9333                         .tunnel_id = tbl_data->tunnel ?
9334                                         tbl_data->tunnel->tunnel_id : 0,
9335                         .group = tbl_data->group_id
9336                 };
9337                 uint32_t table_id = tbl_data->table_id;
9338
9339                 tunnel_grp_hash = tbl_data->tunnel ?
9340                                         tbl_data->tunnel->groups :
9341                                         thub->groups;
9342                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9343                 if (he)
9344                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9345                 DRV_LOG(DEBUG,
9346                         "Table_id %u tunnel %u group %u released.",
9347                         table_id,
9348                         tbl_data->tunnel ?
9349                         tbl_data->tunnel->tunnel_id : 0,
9350                         tbl_data->group_id);
9351         }
9352         mlx5_cache_list_destroy(&tbl_data->matchers);
9353         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9354 }
9355
9356 /**
9357  * Release a flow table.
9358  *
9359  * @param[in] sh
9360  *   Pointer to device shared structure.
9361  * @param[in] tbl
9362  *   Table resource to be released.
9363  *
9364  * @return
9365  *   Returns 0 if table was released, else return 1;
9366  */
9367 static int
9368 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9369                              struct mlx5_flow_tbl_resource *tbl)
9370 {
9371         struct mlx5_flow_tbl_data_entry *tbl_data =
9372                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9373
9374         if (!tbl)
9375                 return 0;
9376         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9377 }
9378
9379 int
9380 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9381                          struct mlx5_cache_entry *entry, void *cb_ctx)
9382 {
9383         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9384         struct mlx5_flow_dv_matcher *ref = ctx->data;
9385         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9386                                                         entry);
9387
9388         return cur->crc != ref->crc ||
9389                cur->priority != ref->priority ||
9390                memcmp((const void *)cur->mask.buf,
9391                       (const void *)ref->mask.buf, ref->mask.size);
9392 }
9393
9394 struct mlx5_cache_entry *
9395 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9396                           struct mlx5_cache_entry *entry __rte_unused,
9397                           void *cb_ctx)
9398 {
9399         struct mlx5_dev_ctx_shared *sh = list->ctx;
9400         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9401         struct mlx5_flow_dv_matcher *ref = ctx->data;
9402         struct mlx5_flow_dv_matcher *cache;
9403         struct mlx5dv_flow_matcher_attr dv_attr = {
9404                 .type = IBV_FLOW_ATTR_NORMAL,
9405                 .match_mask = (void *)&ref->mask,
9406         };
9407         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9408                                                             typeof(*tbl), tbl);
9409         int ret;
9410
9411         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9412         if (!cache) {
9413                 rte_flow_error_set(ctx->error, ENOMEM,
9414                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9415                                    "cannot create matcher");
9416                 return NULL;
9417         }
9418         *cache = *ref;
9419         dv_attr.match_criteria_enable =
9420                 flow_dv_matcher_enable(cache->mask.buf);
9421         dv_attr.priority = ref->priority;
9422         if (tbl->is_egress)
9423                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9424         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9425                                                &cache->matcher_object);
9426         if (ret) {
9427                 mlx5_free(cache);
9428                 rte_flow_error_set(ctx->error, ENOMEM,
9429                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9430                                    "cannot create matcher");
9431                 return NULL;
9432         }
9433         return &cache->entry;
9434 }
9435
9436 /**
9437  * Register the flow matcher.
9438  *
9439  * @param[in, out] dev
9440  *   Pointer to rte_eth_dev structure.
9441  * @param[in, out] matcher
9442  *   Pointer to flow matcher.
9443  * @param[in, out] key
9444  *   Pointer to flow table key.
9445  * @parm[in, out] dev_flow
9446  *   Pointer to the dev_flow.
9447  * @param[out] error
9448  *   pointer to error structure.
9449  *
9450  * @return
9451  *   0 on success otherwise -errno and errno is set.
9452  */
9453 static int
9454 flow_dv_matcher_register(struct rte_eth_dev *dev,
9455                          struct mlx5_flow_dv_matcher *ref,
9456                          union mlx5_flow_tbl_key *key,
9457                          struct mlx5_flow *dev_flow,
9458                          const struct mlx5_flow_tunnel *tunnel,
9459                          uint32_t group_id,
9460                          struct rte_flow_error *error)
9461 {
9462         struct mlx5_cache_entry *entry;
9463         struct mlx5_flow_dv_matcher *cache;
9464         struct mlx5_flow_tbl_resource *tbl;
9465         struct mlx5_flow_tbl_data_entry *tbl_data;
9466         struct mlx5_flow_cb_ctx ctx = {
9467                 .error = error,
9468                 .data = ref,
9469         };
9470
9471         /**
9472          * tunnel offload API requires this registration for cases when
9473          * tunnel match rule was inserted before tunnel set rule.
9474          */
9475         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9476                                        key->direction, key->domain,
9477                                        dev_flow->external, tunnel,
9478                                        group_id, 0, error);
9479         if (!tbl)
9480                 return -rte_errno;      /* No need to refill the error info */
9481         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9482         ref->tbl = tbl;
9483         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9484         if (!entry) {
9485                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9486                 return rte_flow_error_set(error, ENOMEM,
9487                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9488                                           "cannot allocate ref memory");
9489         }
9490         cache = container_of(entry, typeof(*cache), entry);
9491         dev_flow->handle->dvh.matcher = cache;
9492         return 0;
9493 }
9494
9495 struct mlx5_hlist_entry *
9496 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9497 {
9498         struct mlx5_dev_ctx_shared *sh = list->ctx;
9499         struct rte_flow_error *error = ctx;
9500         struct mlx5_flow_dv_tag_resource *entry;
9501         uint32_t idx = 0;
9502         int ret;
9503
9504         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9505         if (!entry) {
9506                 rte_flow_error_set(error, ENOMEM,
9507                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9508                                    "cannot allocate resource memory");
9509                 return NULL;
9510         }
9511         entry->idx = idx;
9512         entry->tag_id = key;
9513         ret = mlx5_flow_os_create_flow_action_tag(key,
9514                                                   &entry->action);
9515         if (ret) {
9516                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9517                 rte_flow_error_set(error, ENOMEM,
9518                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9519                                    NULL, "cannot create action");
9520                 return NULL;
9521         }
9522         return &entry->entry;
9523 }
9524
9525 int
9526 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9527                      struct mlx5_hlist_entry *entry, uint64_t key,
9528                      void *cb_ctx __rte_unused)
9529 {
9530         struct mlx5_flow_dv_tag_resource *tag =
9531                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9532
9533         return key != tag->tag_id;
9534 }
9535
9536 /**
9537  * Find existing tag resource or create and register a new one.
9538  *
9539  * @param dev[in, out]
9540  *   Pointer to rte_eth_dev structure.
9541  * @param[in, out] tag_be24
9542  *   Tag value in big endian then R-shift 8.
9543  * @parm[in, out] dev_flow
9544  *   Pointer to the dev_flow.
9545  * @param[out] error
9546  *   pointer to error structure.
9547  *
9548  * @return
9549  *   0 on success otherwise -errno and errno is set.
9550  */
9551 static int
9552 flow_dv_tag_resource_register
9553                         (struct rte_eth_dev *dev,
9554                          uint32_t tag_be24,
9555                          struct mlx5_flow *dev_flow,
9556                          struct rte_flow_error *error)
9557 {
9558         struct mlx5_priv *priv = dev->data->dev_private;
9559         struct mlx5_flow_dv_tag_resource *cache_resource;
9560         struct mlx5_hlist_entry *entry;
9561
9562         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9563         if (entry) {
9564                 cache_resource = container_of
9565                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9566                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9567                 dev_flow->dv.tag_resource = cache_resource;
9568                 return 0;
9569         }
9570         return -rte_errno;
9571 }
9572
9573 void
9574 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9575                       struct mlx5_hlist_entry *entry)
9576 {
9577         struct mlx5_dev_ctx_shared *sh = list->ctx;
9578         struct mlx5_flow_dv_tag_resource *tag =
9579                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9580
9581         MLX5_ASSERT(tag && sh && tag->action);
9582         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9583         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9584         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9585 }
9586
9587 /**
9588  * Release the tag.
9589  *
9590  * @param dev
9591  *   Pointer to Ethernet device.
9592  * @param tag_idx
9593  *   Tag index.
9594  *
9595  * @return
9596  *   1 while a reference on it exists, 0 when freed.
9597  */
9598 static int
9599 flow_dv_tag_release(struct rte_eth_dev *dev,
9600                     uint32_t tag_idx)
9601 {
9602         struct mlx5_priv *priv = dev->data->dev_private;
9603         struct mlx5_flow_dv_tag_resource *tag;
9604
9605         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9606         if (!tag)
9607                 return 0;
9608         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9609                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9610         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9611 }
9612
9613 /**
9614  * Translate port ID action to vport.
9615  *
9616  * @param[in] dev
9617  *   Pointer to rte_eth_dev structure.
9618  * @param[in] action
9619  *   Pointer to the port ID action.
9620  * @param[out] dst_port_id
9621  *   The target port ID.
9622  * @param[out] error
9623  *   Pointer to the error structure.
9624  *
9625  * @return
9626  *   0 on success, a negative errno value otherwise and rte_errno is set.
9627  */
9628 static int
9629 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9630                                  const struct rte_flow_action *action,
9631                                  uint32_t *dst_port_id,
9632                                  struct rte_flow_error *error)
9633 {
9634         uint32_t port;
9635         struct mlx5_priv *priv;
9636         const struct rte_flow_action_port_id *conf =
9637                         (const struct rte_flow_action_port_id *)action->conf;
9638
9639         port = conf->original ? dev->data->port_id : conf->id;
9640         priv = mlx5_port_to_eswitch_info(port, false);
9641         if (!priv)
9642                 return rte_flow_error_set(error, -rte_errno,
9643                                           RTE_FLOW_ERROR_TYPE_ACTION,
9644                                           NULL,
9645                                           "No eswitch info was found for port");
9646 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9647         /*
9648          * This parameter is transferred to
9649          * mlx5dv_dr_action_create_dest_ib_port().
9650          */
9651         *dst_port_id = priv->dev_port;
9652 #else
9653         /*
9654          * Legacy mode, no LAG configurations is supported.
9655          * This parameter is transferred to
9656          * mlx5dv_dr_action_create_dest_vport().
9657          */
9658         *dst_port_id = priv->vport_id;
9659 #endif
9660         return 0;
9661 }
9662
9663 /**
9664  * Create a counter with aging configuration.
9665  *
9666  * @param[in] dev
9667  *   Pointer to rte_eth_dev structure.
9668  * @param[out] count
9669  *   Pointer to the counter action configuration.
9670  * @param[in] age
9671  *   Pointer to the aging action configuration.
9672  *
9673  * @return
9674  *   Index to flow counter on success, 0 otherwise.
9675  */
9676 static uint32_t
9677 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9678                                 struct mlx5_flow *dev_flow,
9679                                 const struct rte_flow_action_count *count,
9680                                 const struct rte_flow_action_age *age)
9681 {
9682         uint32_t counter;
9683         struct mlx5_age_param *age_param;
9684
9685         if (count && count->shared)
9686                 counter = flow_dv_counter_get_shared(dev, count->id);
9687         else
9688                 counter = flow_dv_counter_alloc(dev, !!age);
9689         if (!counter || age == NULL)
9690                 return counter;
9691         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9692         age_param->context = age->context ? age->context :
9693                 (void *)(uintptr_t)(dev_flow->flow_idx);
9694         age_param->timeout = age->timeout;
9695         age_param->port_id = dev->data->port_id;
9696         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9697         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9698         return counter;
9699 }
9700
9701 /**
9702  * Add Tx queue matcher
9703  *
9704  * @param[in] dev
9705  *   Pointer to the dev struct.
9706  * @param[in, out] matcher
9707  *   Flow matcher.
9708  * @param[in, out] key
9709  *   Flow matcher value.
9710  * @param[in] item
9711  *   Flow pattern to translate.
9712  * @param[in] inner
9713  *   Item is inner pattern.
9714  */
9715 static void
9716 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9717                                 void *matcher, void *key,
9718                                 const struct rte_flow_item *item)
9719 {
9720         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9721         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9722         void *misc_m =
9723                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9724         void *misc_v =
9725                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9726         struct mlx5_txq_ctrl *txq;
9727         uint32_t queue;
9728
9729
9730         queue_m = (const void *)item->mask;
9731         if (!queue_m)
9732                 return;
9733         queue_v = (const void *)item->spec;
9734         if (!queue_v)
9735                 return;
9736         txq = mlx5_txq_get(dev, queue_v->queue);
9737         if (!txq)
9738                 return;
9739         queue = txq->obj->sq->id;
9740         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9741         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9742                  queue & queue_m->queue);
9743         mlx5_txq_release(dev, queue_v->queue);
9744 }
9745
9746 /**
9747  * Set the hash fields according to the @p flow information.
9748  *
9749  * @param[in] dev_flow
9750  *   Pointer to the mlx5_flow.
9751  * @param[in] rss_desc
9752  *   Pointer to the mlx5_flow_rss_desc.
9753  */
9754 static void
9755 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9756                        struct mlx5_flow_rss_desc *rss_desc)
9757 {
9758         uint64_t items = dev_flow->handle->layers;
9759         int rss_inner = 0;
9760         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9761
9762         dev_flow->hash_fields = 0;
9763 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9764         if (rss_desc->level >= 2) {
9765                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9766                 rss_inner = 1;
9767         }
9768 #endif
9769         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9770             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9771                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9772                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9773                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9774                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9775                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9776                         else
9777                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9778                 }
9779         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9780                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9781                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9782                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9783                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9784                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9785                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9786                         else
9787                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9788                 }
9789         }
9790         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9791             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9792                 if (rss_types & ETH_RSS_UDP) {
9793                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9794                                 dev_flow->hash_fields |=
9795                                                 IBV_RX_HASH_SRC_PORT_UDP;
9796                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9797                                 dev_flow->hash_fields |=
9798                                                 IBV_RX_HASH_DST_PORT_UDP;
9799                         else
9800                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9801                 }
9802         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9803                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9804                 if (rss_types & ETH_RSS_TCP) {
9805                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9806                                 dev_flow->hash_fields |=
9807                                                 IBV_RX_HASH_SRC_PORT_TCP;
9808                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9809                                 dev_flow->hash_fields |=
9810                                                 IBV_RX_HASH_DST_PORT_TCP;
9811                         else
9812                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9813                 }
9814         }
9815 }
9816
9817 /**
9818  * Prepare an Rx Hash queue.
9819  *
9820  * @param dev
9821  *   Pointer to Ethernet device.
9822  * @param[in] dev_flow
9823  *   Pointer to the mlx5_flow.
9824  * @param[in] rss_desc
9825  *   Pointer to the mlx5_flow_rss_desc.
9826  * @param[out] hrxq_idx
9827  *   Hash Rx queue index.
9828  *
9829  * @return
9830  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9831  */
9832 static struct mlx5_hrxq *
9833 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9834                      struct mlx5_flow *dev_flow,
9835                      struct mlx5_flow_rss_desc *rss_desc,
9836                      uint32_t *hrxq_idx)
9837 {
9838         struct mlx5_priv *priv = dev->data->dev_private;
9839         struct mlx5_flow_handle *dh = dev_flow->handle;
9840         struct mlx5_hrxq *hrxq;
9841
9842         MLX5_ASSERT(rss_desc->queue_num);
9843         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9844         rss_desc->hash_fields = dev_flow->hash_fields;
9845         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9846         rss_desc->shared_rss = 0;
9847         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9848         if (!*hrxq_idx)
9849                 return NULL;
9850         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9851                               *hrxq_idx);
9852         return hrxq;
9853 }
9854
9855 /**
9856  * Release sample sub action resource.
9857  *
9858  * @param[in, out] dev
9859  *   Pointer to rte_eth_dev structure.
9860  * @param[in] act_res
9861  *   Pointer to sample sub action resource.
9862  */
9863 static void
9864 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9865                                    struct mlx5_flow_sub_actions_idx *act_res)
9866 {
9867         if (act_res->rix_hrxq) {
9868                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9869                 act_res->rix_hrxq = 0;
9870         }
9871         if (act_res->rix_encap_decap) {
9872                 flow_dv_encap_decap_resource_release(dev,
9873                                                      act_res->rix_encap_decap);
9874                 act_res->rix_encap_decap = 0;
9875         }
9876         if (act_res->rix_port_id_action) {
9877                 flow_dv_port_id_action_resource_release(dev,
9878                                                 act_res->rix_port_id_action);
9879                 act_res->rix_port_id_action = 0;
9880         }
9881         if (act_res->rix_tag) {
9882                 flow_dv_tag_release(dev, act_res->rix_tag);
9883                 act_res->rix_tag = 0;
9884         }
9885         if (act_res->rix_jump) {
9886                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9887                 act_res->rix_jump = 0;
9888         }
9889 }
9890
9891 int
9892 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9893                         struct mlx5_cache_entry *entry, void *cb_ctx)
9894 {
9895         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9896         struct rte_eth_dev *dev = ctx->dev;
9897         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9898         struct mlx5_flow_dv_sample_resource *cache_resource =
9899                         container_of(entry, typeof(*cache_resource), entry);
9900
9901         if (resource->ratio == cache_resource->ratio &&
9902             resource->ft_type == cache_resource->ft_type &&
9903             resource->ft_id == cache_resource->ft_id &&
9904             resource->set_action == cache_resource->set_action &&
9905             !memcmp((void *)&resource->sample_act,
9906                     (void *)&cache_resource->sample_act,
9907                     sizeof(struct mlx5_flow_sub_actions_list))) {
9908                 /*
9909                  * Existing sample action should release the prepared
9910                  * sub-actions reference counter.
9911                  */
9912                 flow_dv_sample_sub_actions_release(dev,
9913                                                 &resource->sample_idx);
9914                 return 0;
9915         }
9916         return 1;
9917 }
9918
9919 struct mlx5_cache_entry *
9920 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9921                          struct mlx5_cache_entry *entry __rte_unused,
9922                          void *cb_ctx)
9923 {
9924         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9925         struct rte_eth_dev *dev = ctx->dev;
9926         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9927         void **sample_dv_actions = resource->sub_actions;
9928         struct mlx5_flow_dv_sample_resource *cache_resource;
9929         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9930         struct mlx5_priv *priv = dev->data->dev_private;
9931         struct mlx5_dev_ctx_shared *sh = priv->sh;
9932         struct mlx5_flow_tbl_resource *tbl;
9933         uint32_t idx = 0;
9934         const uint32_t next_ft_step = 1;
9935         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9936         uint8_t is_egress = 0;
9937         uint8_t is_transfer = 0;
9938         struct rte_flow_error *error = ctx->error;
9939
9940         /* Register new sample resource. */
9941         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9942         if (!cache_resource) {
9943                 rte_flow_error_set(error, ENOMEM,
9944                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9945                                           NULL,
9946                                           "cannot allocate resource memory");
9947                 return NULL;
9948         }
9949         *cache_resource = *resource;
9950         /* Create normal path table level */
9951         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9952                 is_transfer = 1;
9953         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9954                 is_egress = 1;
9955         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9956                                         is_egress, is_transfer,
9957                                         true, NULL, 0, 0, error);
9958         if (!tbl) {
9959                 rte_flow_error_set(error, ENOMEM,
9960                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9961                                           NULL,
9962                                           "fail to create normal path table "
9963                                           "for sample");
9964                 goto error;
9965         }
9966         cache_resource->normal_path_tbl = tbl;
9967         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9968                 if (!sh->default_miss_action) {
9969                         rte_flow_error_set(error, ENOMEM,
9970                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9971                                                 NULL,
9972                                                 "default miss action was not "
9973                                                 "created");
9974                         goto error;
9975                 }
9976                 sample_dv_actions[resource->sample_act.actions_num++] =
9977                                                 sh->default_miss_action;
9978         }
9979         /* Create a DR sample action */
9980         sampler_attr.sample_ratio = cache_resource->ratio;
9981         sampler_attr.default_next_table = tbl->obj;
9982         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9983         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9984                                                         &sample_dv_actions[0];
9985         sampler_attr.action = cache_resource->set_action;
9986         if (mlx5_os_flow_dr_create_flow_action_sampler
9987                         (&sampler_attr, &cache_resource->verbs_action)) {
9988                 rte_flow_error_set(error, ENOMEM,
9989                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9990                                         NULL, "cannot create sample action");
9991                 goto error;
9992         }
9993         cache_resource->idx = idx;
9994         cache_resource->dev = dev;
9995         return &cache_resource->entry;
9996 error:
9997         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9998                 flow_dv_sample_sub_actions_release(dev,
9999                                                    &cache_resource->sample_idx);
10000         if (cache_resource->normal_path_tbl)
10001                 flow_dv_tbl_resource_release(MLX5_SH(dev),
10002                                 cache_resource->normal_path_tbl);
10003         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10004         return NULL;
10005
10006 }
10007
10008 /**
10009  * Find existing sample resource or create and register a new one.
10010  *
10011  * @param[in, out] dev
10012  *   Pointer to rte_eth_dev structure.
10013  * @param[in] resource
10014  *   Pointer to sample resource.
10015  * @parm[in, out] dev_flow
10016  *   Pointer to the dev_flow.
10017  * @param[out] error
10018  *   pointer to error structure.
10019  *
10020  * @return
10021  *   0 on success otherwise -errno and errno is set.
10022  */
10023 static int
10024 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10025                          struct mlx5_flow_dv_sample_resource *resource,
10026                          struct mlx5_flow *dev_flow,
10027                          struct rte_flow_error *error)
10028 {
10029         struct mlx5_flow_dv_sample_resource *cache_resource;
10030         struct mlx5_cache_entry *entry;
10031         struct mlx5_priv *priv = dev->data->dev_private;
10032         struct mlx5_flow_cb_ctx ctx = {
10033                 .dev = dev,
10034                 .error = error,
10035                 .data = resource,
10036         };
10037
10038         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10039         if (!entry)
10040                 return -rte_errno;
10041         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10042         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10043         dev_flow->dv.sample_res = cache_resource;
10044         return 0;
10045 }
10046
10047 int
10048 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10049                             struct mlx5_cache_entry *entry, void *cb_ctx)
10050 {
10051         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10052         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10053         struct rte_eth_dev *dev = ctx->dev;
10054         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10055                         container_of(entry, typeof(*cache_resource), entry);
10056         uint32_t idx = 0;
10057
10058         if (resource->num_of_dest == cache_resource->num_of_dest &&
10059             resource->ft_type == cache_resource->ft_type &&
10060             !memcmp((void *)cache_resource->sample_act,
10061                     (void *)resource->sample_act,
10062                    (resource->num_of_dest *
10063                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10064                 /*
10065                  * Existing sample action should release the prepared
10066                  * sub-actions reference counter.
10067                  */
10068                 for (idx = 0; idx < resource->num_of_dest; idx++)
10069                         flow_dv_sample_sub_actions_release(dev,
10070                                         &resource->sample_idx[idx]);
10071                 return 0;
10072         }
10073         return 1;
10074 }
10075
10076 struct mlx5_cache_entry *
10077 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10078                          struct mlx5_cache_entry *entry __rte_unused,
10079                          void *cb_ctx)
10080 {
10081         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10082         struct rte_eth_dev *dev = ctx->dev;
10083         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10084         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10085         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10086         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10087         struct mlx5_priv *priv = dev->data->dev_private;
10088         struct mlx5_dev_ctx_shared *sh = priv->sh;
10089         struct mlx5_flow_sub_actions_list *sample_act;
10090         struct mlx5dv_dr_domain *domain;
10091         uint32_t idx = 0, res_idx = 0;
10092         struct rte_flow_error *error = ctx->error;
10093         uint64_t action_flags;
10094         int ret;
10095
10096         /* Register new destination array resource. */
10097         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10098                                             &res_idx);
10099         if (!cache_resource) {
10100                 rte_flow_error_set(error, ENOMEM,
10101                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10102                                           NULL,
10103                                           "cannot allocate resource memory");
10104                 return NULL;
10105         }
10106         *cache_resource = *resource;
10107         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10108                 domain = sh->fdb_domain;
10109         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10110                 domain = sh->rx_domain;
10111         else
10112                 domain = sh->tx_domain;
10113         for (idx = 0; idx < resource->num_of_dest; idx++) {
10114                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10115                                  mlx5_malloc(MLX5_MEM_ZERO,
10116                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10117                                  0, SOCKET_ID_ANY);
10118                 if (!dest_attr[idx]) {
10119                         rte_flow_error_set(error, ENOMEM,
10120                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10121                                            NULL,
10122                                            "cannot allocate resource memory");
10123                         goto error;
10124                 }
10125                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10126                 sample_act = &resource->sample_act[idx];
10127                 action_flags = sample_act->action_flags;
10128                 switch (action_flags) {
10129                 case MLX5_FLOW_ACTION_QUEUE:
10130                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10131                         break;
10132                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10133                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10134                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10135                         dest_attr[idx]->dest_reformat->reformat =
10136                                         sample_act->dr_encap_action;
10137                         dest_attr[idx]->dest_reformat->dest =
10138                                         sample_act->dr_port_id_action;
10139                         break;
10140                 case MLX5_FLOW_ACTION_PORT_ID:
10141                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10142                         break;
10143                 case MLX5_FLOW_ACTION_JUMP:
10144                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10145                         break;
10146                 default:
10147                         rte_flow_error_set(error, EINVAL,
10148                                            RTE_FLOW_ERROR_TYPE_ACTION,
10149                                            NULL,
10150                                            "unsupported actions type");
10151                         goto error;
10152                 }
10153         }
10154         /* create a dest array actioin */
10155         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10156                                                 (domain,
10157                                                  cache_resource->num_of_dest,
10158                                                  dest_attr,
10159                                                  &cache_resource->action);
10160         if (ret) {
10161                 rte_flow_error_set(error, ENOMEM,
10162                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10163                                    NULL,
10164                                    "cannot create destination array action");
10165                 goto error;
10166         }
10167         cache_resource->idx = res_idx;
10168         cache_resource->dev = dev;
10169         for (idx = 0; idx < resource->num_of_dest; idx++)
10170                 mlx5_free(dest_attr[idx]);
10171         return &cache_resource->entry;
10172 error:
10173         for (idx = 0; idx < resource->num_of_dest; idx++) {
10174                 flow_dv_sample_sub_actions_release(dev,
10175                                 &cache_resource->sample_idx[idx]);
10176                 if (dest_attr[idx])
10177                         mlx5_free(dest_attr[idx]);
10178         }
10179
10180         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10181         return NULL;
10182 }
10183
10184 /**
10185  * Find existing destination array resource or create and register a new one.
10186  *
10187  * @param[in, out] dev
10188  *   Pointer to rte_eth_dev structure.
10189  * @param[in] resource
10190  *   Pointer to destination array resource.
10191  * @parm[in, out] dev_flow
10192  *   Pointer to the dev_flow.
10193  * @param[out] error
10194  *   pointer to error structure.
10195  *
10196  * @return
10197  *   0 on success otherwise -errno and errno is set.
10198  */
10199 static int
10200 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10201                          struct mlx5_flow_dv_dest_array_resource *resource,
10202                          struct mlx5_flow *dev_flow,
10203                          struct rte_flow_error *error)
10204 {
10205         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10206         struct mlx5_priv *priv = dev->data->dev_private;
10207         struct mlx5_cache_entry *entry;
10208         struct mlx5_flow_cb_ctx ctx = {
10209                 .dev = dev,
10210                 .error = error,
10211                 .data = resource,
10212         };
10213
10214         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10215         if (!entry)
10216                 return -rte_errno;
10217         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10218         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10219         dev_flow->dv.dest_array_res = cache_resource;
10220         return 0;
10221 }
10222
10223 /**
10224  * Convert Sample action to DV specification.
10225  *
10226  * @param[in] dev
10227  *   Pointer to rte_eth_dev structure.
10228  * @param[in] action
10229  *   Pointer to sample action structure.
10230  * @param[in, out] dev_flow
10231  *   Pointer to the mlx5_flow.
10232  * @param[in] attr
10233  *   Pointer to the flow attributes.
10234  * @param[in, out] num_of_dest
10235  *   Pointer to the num of destination.
10236  * @param[in, out] sample_actions
10237  *   Pointer to sample actions list.
10238  * @param[in, out] res
10239  *   Pointer to sample resource.
10240  * @param[out] error
10241  *   Pointer to the error structure.
10242  *
10243  * @return
10244  *   0 on success, a negative errno value otherwise and rte_errno is set.
10245  */
10246 static int
10247 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10248                                 const struct rte_flow_action_sample *action,
10249                                 struct mlx5_flow *dev_flow,
10250                                 const struct rte_flow_attr *attr,
10251                                 uint32_t *num_of_dest,
10252                                 void **sample_actions,
10253                                 struct mlx5_flow_dv_sample_resource *res,
10254                                 struct rte_flow_error *error)
10255 {
10256         struct mlx5_priv *priv = dev->data->dev_private;
10257         const struct rte_flow_action *sub_actions;
10258         struct mlx5_flow_sub_actions_list *sample_act;
10259         struct mlx5_flow_sub_actions_idx *sample_idx;
10260         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10261         struct rte_flow *flow = dev_flow->flow;
10262         struct mlx5_flow_rss_desc *rss_desc;
10263         uint64_t action_flags = 0;
10264
10265         MLX5_ASSERT(wks);
10266         rss_desc = &wks->rss_desc;
10267         sample_act = &res->sample_act;
10268         sample_idx = &res->sample_idx;
10269         res->ratio = action->ratio;
10270         sub_actions = action->actions;
10271         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10272                 int type = sub_actions->type;
10273                 uint32_t pre_rix = 0;
10274                 void *pre_r;
10275                 switch (type) {
10276                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10277                 {
10278                         const struct rte_flow_action_queue *queue;
10279                         struct mlx5_hrxq *hrxq;
10280                         uint32_t hrxq_idx;
10281
10282                         queue = sub_actions->conf;
10283                         rss_desc->queue_num = 1;
10284                         rss_desc->queue[0] = queue->index;
10285                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10286                                                     rss_desc, &hrxq_idx);
10287                         if (!hrxq)
10288                                 return rte_flow_error_set
10289                                         (error, rte_errno,
10290                                          RTE_FLOW_ERROR_TYPE_ACTION,
10291                                          NULL,
10292                                          "cannot create fate queue");
10293                         sample_act->dr_queue_action = hrxq->action;
10294                         sample_idx->rix_hrxq = hrxq_idx;
10295                         sample_actions[sample_act->actions_num++] =
10296                                                 hrxq->action;
10297                         (*num_of_dest)++;
10298                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10299                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10300                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10301                         dev_flow->handle->fate_action =
10302                                         MLX5_FLOW_FATE_QUEUE;
10303                         break;
10304                 }
10305                 case RTE_FLOW_ACTION_TYPE_RSS:
10306                 {
10307                         struct mlx5_hrxq *hrxq;
10308                         uint32_t hrxq_idx;
10309                         const struct rte_flow_action_rss *rss;
10310                         const uint8_t *rss_key;
10311
10312                         rss = sub_actions->conf;
10313                         memcpy(rss_desc->queue, rss->queue,
10314                                rss->queue_num * sizeof(uint16_t));
10315                         rss_desc->queue_num = rss->queue_num;
10316                         /* NULL RSS key indicates default RSS key. */
10317                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10318                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10319                         /*
10320                          * rss->level and rss.types should be set in advance
10321                          * when expanding items for RSS.
10322                          */
10323                         flow_dv_hashfields_set(dev_flow, rss_desc);
10324                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10325                                                     rss_desc, &hrxq_idx);
10326                         if (!hrxq)
10327                                 return rte_flow_error_set
10328                                         (error, rte_errno,
10329                                          RTE_FLOW_ERROR_TYPE_ACTION,
10330                                          NULL,
10331                                          "cannot create fate queue");
10332                         sample_act->dr_queue_action = hrxq->action;
10333                         sample_idx->rix_hrxq = hrxq_idx;
10334                         sample_actions[sample_act->actions_num++] =
10335                                                 hrxq->action;
10336                         (*num_of_dest)++;
10337                         action_flags |= MLX5_FLOW_ACTION_RSS;
10338                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10339                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10340                         dev_flow->handle->fate_action =
10341                                         MLX5_FLOW_FATE_QUEUE;
10342                         break;
10343                 }
10344                 case RTE_FLOW_ACTION_TYPE_MARK:
10345                 {
10346                         uint32_t tag_be = mlx5_flow_mark_set
10347                                 (((const struct rte_flow_action_mark *)
10348                                 (sub_actions->conf))->id);
10349
10350                         dev_flow->handle->mark = 1;
10351                         pre_rix = dev_flow->handle->dvh.rix_tag;
10352                         /* Save the mark resource before sample */
10353                         pre_r = dev_flow->dv.tag_resource;
10354                         if (flow_dv_tag_resource_register(dev, tag_be,
10355                                                   dev_flow, error))
10356                                 return -rte_errno;
10357                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10358                         sample_act->dr_tag_action =
10359                                 dev_flow->dv.tag_resource->action;
10360                         sample_idx->rix_tag =
10361                                 dev_flow->handle->dvh.rix_tag;
10362                         sample_actions[sample_act->actions_num++] =
10363                                                 sample_act->dr_tag_action;
10364                         /* Recover the mark resource after sample */
10365                         dev_flow->dv.tag_resource = pre_r;
10366                         dev_flow->handle->dvh.rix_tag = pre_rix;
10367                         action_flags |= MLX5_FLOW_ACTION_MARK;
10368                         break;
10369                 }
10370                 case RTE_FLOW_ACTION_TYPE_COUNT:
10371                 {
10372                         if (!flow->counter) {
10373                                 flow->counter =
10374                                         flow_dv_translate_create_counter(dev,
10375                                                 dev_flow, sub_actions->conf,
10376                                                 0);
10377                                 if (!flow->counter)
10378                                         return rte_flow_error_set
10379                                                 (error, rte_errno,
10380                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10381                                                 NULL,
10382                                                 "cannot create counter"
10383                                                 " object.");
10384                         }
10385                         sample_act->dr_cnt_action =
10386                                   (flow_dv_counter_get_by_idx(dev,
10387                                   flow->counter, NULL))->action;
10388                         sample_actions[sample_act->actions_num++] =
10389                                                 sample_act->dr_cnt_action;
10390                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10391                         break;
10392                 }
10393                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10394                 {
10395                         struct mlx5_flow_dv_port_id_action_resource
10396                                         port_id_resource;
10397                         uint32_t port_id = 0;
10398
10399                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10400                         /* Save the port id resource before sample */
10401                         pre_rix = dev_flow->handle->rix_port_id_action;
10402                         pre_r = dev_flow->dv.port_id_action;
10403                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10404                                                              &port_id, error))
10405                                 return -rte_errno;
10406                         port_id_resource.port_id = port_id;
10407                         if (flow_dv_port_id_action_resource_register
10408                             (dev, &port_id_resource, dev_flow, error))
10409                                 return -rte_errno;
10410                         sample_act->dr_port_id_action =
10411                                 dev_flow->dv.port_id_action->action;
10412                         sample_idx->rix_port_id_action =
10413                                 dev_flow->handle->rix_port_id_action;
10414                         sample_actions[sample_act->actions_num++] =
10415                                                 sample_act->dr_port_id_action;
10416                         /* Recover the port id resource after sample */
10417                         dev_flow->dv.port_id_action = pre_r;
10418                         dev_flow->handle->rix_port_id_action = pre_rix;
10419                         (*num_of_dest)++;
10420                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10421                         break;
10422                 }
10423                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10424                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10425                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10426                         /* Save the encap resource before sample */
10427                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10428                         pre_r = dev_flow->dv.encap_decap;
10429                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10430                                                            dev_flow,
10431                                                            attr->transfer,
10432                                                            error))
10433                                 return -rte_errno;
10434                         sample_act->dr_encap_action =
10435                                 dev_flow->dv.encap_decap->action;
10436                         sample_idx->rix_encap_decap =
10437                                 dev_flow->handle->dvh.rix_encap_decap;
10438                         sample_actions[sample_act->actions_num++] =
10439                                                 sample_act->dr_encap_action;
10440                         /* Recover the encap resource after sample */
10441                         dev_flow->dv.encap_decap = pre_r;
10442                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10443                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10444                         break;
10445                 default:
10446                         return rte_flow_error_set(error, EINVAL,
10447                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10448                                 NULL,
10449                                 "Not support for sampler action");
10450                 }
10451         }
10452         sample_act->action_flags = action_flags;
10453         res->ft_id = dev_flow->dv.group;
10454         if (attr->transfer) {
10455                 union {
10456                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10457                         uint64_t set_action;
10458                 } action_ctx = { .set_action = 0 };
10459
10460                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10461                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10462                          MLX5_MODIFICATION_TYPE_SET);
10463                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10464                          MLX5_MODI_META_REG_C_0);
10465                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10466                          priv->vport_meta_tag);
10467                 res->set_action = action_ctx.set_action;
10468         } else if (attr->ingress) {
10469                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10470         } else {
10471                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10472         }
10473         return 0;
10474 }
10475
10476 /**
10477  * Convert Sample action to DV specification.
10478  *
10479  * @param[in] dev
10480  *   Pointer to rte_eth_dev structure.
10481  * @param[in, out] dev_flow
10482  *   Pointer to the mlx5_flow.
10483  * @param[in] num_of_dest
10484  *   The num of destination.
10485  * @param[in, out] res
10486  *   Pointer to sample resource.
10487  * @param[in, out] mdest_res
10488  *   Pointer to destination array resource.
10489  * @param[in] sample_actions
10490  *   Pointer to sample path actions list.
10491  * @param[in] action_flags
10492  *   Holds the actions detected until now.
10493  * @param[out] error
10494  *   Pointer to the error structure.
10495  *
10496  * @return
10497  *   0 on success, a negative errno value otherwise and rte_errno is set.
10498  */
10499 static int
10500 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10501                              struct mlx5_flow *dev_flow,
10502                              uint32_t num_of_dest,
10503                              struct mlx5_flow_dv_sample_resource *res,
10504                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10505                              void **sample_actions,
10506                              uint64_t action_flags,
10507                              struct rte_flow_error *error)
10508 {
10509         /* update normal path action resource into last index of array */
10510         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10511         struct mlx5_flow_sub_actions_list *sample_act =
10512                                         &mdest_res->sample_act[dest_index];
10513         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10514         struct mlx5_flow_rss_desc *rss_desc;
10515         uint32_t normal_idx = 0;
10516         struct mlx5_hrxq *hrxq;
10517         uint32_t hrxq_idx;
10518
10519         MLX5_ASSERT(wks);
10520         rss_desc = &wks->rss_desc;
10521         if (num_of_dest > 1) {
10522                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10523                         /* Handle QP action for mirroring */
10524                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10525                                                     rss_desc, &hrxq_idx);
10526                         if (!hrxq)
10527                                 return rte_flow_error_set
10528                                      (error, rte_errno,
10529                                       RTE_FLOW_ERROR_TYPE_ACTION,
10530                                       NULL,
10531                                       "cannot create rx queue");
10532                         normal_idx++;
10533                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10534                         sample_act->dr_queue_action = hrxq->action;
10535                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10536                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10537                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10538                 }
10539                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10540                         normal_idx++;
10541                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10542                                 dev_flow->handle->dvh.rix_encap_decap;
10543                         sample_act->dr_encap_action =
10544                                 dev_flow->dv.encap_decap->action;
10545                         dev_flow->handle->dvh.rix_encap_decap = 0;
10546                 }
10547                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10548                         normal_idx++;
10549                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10550                                 dev_flow->handle->rix_port_id_action;
10551                         sample_act->dr_port_id_action =
10552                                 dev_flow->dv.port_id_action->action;
10553                         dev_flow->handle->rix_port_id_action = 0;
10554                 }
10555                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10556                         normal_idx++;
10557                         mdest_res->sample_idx[dest_index].rix_jump =
10558                                 dev_flow->handle->rix_jump;
10559                         sample_act->dr_jump_action =
10560                                 dev_flow->dv.jump->action;
10561                         dev_flow->handle->rix_jump = 0;
10562                 }
10563                 sample_act->actions_num = normal_idx;
10564                 /* update sample action resource into first index of array */
10565                 mdest_res->ft_type = res->ft_type;
10566                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10567                                 sizeof(struct mlx5_flow_sub_actions_idx));
10568                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10569                                 sizeof(struct mlx5_flow_sub_actions_list));
10570                 mdest_res->num_of_dest = num_of_dest;
10571                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10572                                                          dev_flow, error))
10573                         return rte_flow_error_set(error, EINVAL,
10574                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10575                                                   NULL, "can't create sample "
10576                                                   "action");
10577         } else {
10578                 res->sub_actions = sample_actions;
10579                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10580                         return rte_flow_error_set(error, EINVAL,
10581                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10582                                                   NULL,
10583                                                   "can't create sample action");
10584         }
10585         return 0;
10586 }
10587
10588 /**
10589  * Remove an ASO age action from age actions list.
10590  *
10591  * @param[in] dev
10592  *   Pointer to the Ethernet device structure.
10593  * @param[in] age
10594  *   Pointer to the aso age action handler.
10595  */
10596 static void
10597 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10598                                 struct mlx5_aso_age_action *age)
10599 {
10600         struct mlx5_age_info *age_info;
10601         struct mlx5_age_param *age_param = &age->age_params;
10602         struct mlx5_priv *priv = dev->data->dev_private;
10603         uint16_t expected = AGE_CANDIDATE;
10604
10605         age_info = GET_PORT_AGE_INFO(priv);
10606         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10607                                          AGE_FREE, false, __ATOMIC_RELAXED,
10608                                          __ATOMIC_RELAXED)) {
10609                 /**
10610                  * We need the lock even it is age timeout,
10611                  * since age action may still in process.
10612                  */
10613                 rte_spinlock_lock(&age_info->aged_sl);
10614                 LIST_REMOVE(age, next);
10615                 rte_spinlock_unlock(&age_info->aged_sl);
10616                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10617         }
10618 }
10619
10620 /**
10621  * Release an ASO age action.
10622  *
10623  * @param[in] dev
10624  *   Pointer to the Ethernet device structure.
10625  * @param[in] age_idx
10626  *   Index of ASO age action to release.
10627  * @param[in] flow
10628  *   True if the release operation is during flow destroy operation.
10629  *   False if the release operation is during action destroy operation.
10630  *
10631  * @return
10632  *   0 when age action was removed, otherwise the number of references.
10633  */
10634 static int
10635 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10636 {
10637         struct mlx5_priv *priv = dev->data->dev_private;
10638         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10639         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10640         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10641
10642         if (!ret) {
10643                 flow_dv_aso_age_remove_from_age(dev, age);
10644                 rte_spinlock_lock(&mng->free_sl);
10645                 LIST_INSERT_HEAD(&mng->free, age, next);
10646                 rte_spinlock_unlock(&mng->free_sl);
10647         }
10648         return ret;
10649 }
10650
10651 /**
10652  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10653  *
10654  * @param[in] dev
10655  *   Pointer to the Ethernet device structure.
10656  *
10657  * @return
10658  *   0 on success, otherwise negative errno value and rte_errno is set.
10659  */
10660 static int
10661 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10662 {
10663         struct mlx5_priv *priv = dev->data->dev_private;
10664         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10665         void *old_pools = mng->pools;
10666         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10667         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10668         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10669
10670         if (!pools) {
10671                 rte_errno = ENOMEM;
10672                 return -ENOMEM;
10673         }
10674         if (old_pools) {
10675                 memcpy(pools, old_pools,
10676                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10677                 mlx5_free(old_pools);
10678         } else {
10679                 /* First ASO flow hit allocation - starting ASO data-path. */
10680                 int ret = mlx5_aso_queue_start(priv->sh);
10681
10682                 if (ret) {
10683                         mlx5_free(pools);
10684                         return ret;
10685                 }
10686         }
10687         mng->n = resize;
10688         mng->pools = pools;
10689         return 0;
10690 }
10691
10692 /**
10693  * Create and initialize a new ASO aging pool.
10694  *
10695  * @param[in] dev
10696  *   Pointer to the Ethernet device structure.
10697  * @param[out] age_free
10698  *   Where to put the pointer of a new age action.
10699  *
10700  * @return
10701  *   The age actions pool pointer and @p age_free is set on success,
10702  *   NULL otherwise and rte_errno is set.
10703  */
10704 static struct mlx5_aso_age_pool *
10705 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10706                         struct mlx5_aso_age_action **age_free)
10707 {
10708         struct mlx5_priv *priv = dev->data->dev_private;
10709         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10710         struct mlx5_aso_age_pool *pool = NULL;
10711         struct mlx5_devx_obj *obj = NULL;
10712         uint32_t i;
10713
10714         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10715                                                     priv->sh->pdn);
10716         if (!obj) {
10717                 rte_errno = ENODATA;
10718                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10719                 return NULL;
10720         }
10721         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10722         if (!pool) {
10723                 claim_zero(mlx5_devx_cmd_destroy(obj));
10724                 rte_errno = ENOMEM;
10725                 return NULL;
10726         }
10727         pool->flow_hit_aso_obj = obj;
10728         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10729         rte_spinlock_lock(&mng->resize_sl);
10730         pool->index = mng->next;
10731         /* Resize pools array if there is no room for the new pool in it. */
10732         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10733                 claim_zero(mlx5_devx_cmd_destroy(obj));
10734                 mlx5_free(pool);
10735                 rte_spinlock_unlock(&mng->resize_sl);
10736                 return NULL;
10737         }
10738         mng->pools[pool->index] = pool;
10739         mng->next++;
10740         rte_spinlock_unlock(&mng->resize_sl);
10741         /* Assign the first action in the new pool, the rest go to free list. */
10742         *age_free = &pool->actions[0];
10743         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10744                 pool->actions[i].offset = i;
10745                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10746         }
10747         return pool;
10748 }
10749
10750 /**
10751  * Allocate a ASO aging bit.
10752  *
10753  * @param[in] dev
10754  *   Pointer to the Ethernet device structure.
10755  * @param[out] error
10756  *   Pointer to the error structure.
10757  *
10758  * @return
10759  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10760  */
10761 static uint32_t
10762 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10763 {
10764         struct mlx5_priv *priv = dev->data->dev_private;
10765         const struct mlx5_aso_age_pool *pool;
10766         struct mlx5_aso_age_action *age_free = NULL;
10767         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10768
10769         MLX5_ASSERT(mng);
10770         /* Try to get the next free age action bit. */
10771         rte_spinlock_lock(&mng->free_sl);
10772         age_free = LIST_FIRST(&mng->free);
10773         if (age_free) {
10774                 LIST_REMOVE(age_free, next);
10775         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10776                 rte_spinlock_unlock(&mng->free_sl);
10777                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10778                                    NULL, "failed to create ASO age pool");
10779                 return 0; /* 0 is an error. */
10780         }
10781         rte_spinlock_unlock(&mng->free_sl);
10782         pool = container_of
10783           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10784                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10785                                                                        actions);
10786         if (!age_free->dr_action) {
10787                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10788                                                  error);
10789
10790                 if (reg_c < 0) {
10791                         rte_flow_error_set(error, rte_errno,
10792                                            RTE_FLOW_ERROR_TYPE_ACTION,
10793                                            NULL, "failed to get reg_c "
10794                                            "for ASO flow hit");
10795                         return 0; /* 0 is an error. */
10796                 }
10797 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10798                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10799                                 (priv->sh->rx_domain,
10800                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10801                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10802                                  (reg_c - REG_C_0));
10803 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10804                 if (!age_free->dr_action) {
10805                         rte_errno = errno;
10806                         rte_spinlock_lock(&mng->free_sl);
10807                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10808                         rte_spinlock_unlock(&mng->free_sl);
10809                         rte_flow_error_set(error, rte_errno,
10810                                            RTE_FLOW_ERROR_TYPE_ACTION,
10811                                            NULL, "failed to create ASO "
10812                                            "flow hit action");
10813                         return 0; /* 0 is an error. */
10814                 }
10815         }
10816         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10817         return pool->index | ((age_free->offset + 1) << 16);
10818 }
10819
10820 /**
10821  * Create a age action using ASO mechanism.
10822  *
10823  * @param[in] dev
10824  *   Pointer to rte_eth_dev structure.
10825  * @param[in] age
10826  *   Pointer to the aging action configuration.
10827  * @param[out] error
10828  *   Pointer to the error structure.
10829  *
10830  * @return
10831  *   Index to flow counter on success, 0 otherwise.
10832  */
10833 static uint32_t
10834 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10835                                  const struct rte_flow_action_age *age,
10836                                  struct rte_flow_error *error)
10837 {
10838         uint32_t age_idx = 0;
10839         struct mlx5_aso_age_action *aso_age;
10840
10841         age_idx = flow_dv_aso_age_alloc(dev, error);
10842         if (!age_idx)
10843                 return 0;
10844         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10845         aso_age->age_params.context = age->context;
10846         aso_age->age_params.timeout = age->timeout;
10847         aso_age->age_params.port_id = dev->data->port_id;
10848         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10849                          __ATOMIC_RELAXED);
10850         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10851                          __ATOMIC_RELAXED);
10852         return age_idx;
10853 }
10854
10855 /**
10856  * Fill the flow with DV spec, lock free
10857  * (mutex should be acquired by caller).
10858  *
10859  * @param[in] dev
10860  *   Pointer to rte_eth_dev structure.
10861  * @param[in, out] dev_flow
10862  *   Pointer to the sub flow.
10863  * @param[in] attr
10864  *   Pointer to the flow attributes.
10865  * @param[in] items
10866  *   Pointer to the list of items.
10867  * @param[in] actions
10868  *   Pointer to the list of actions.
10869  * @param[out] error
10870  *   Pointer to the error structure.
10871  *
10872  * @return
10873  *   0 on success, a negative errno value otherwise and rte_errno is set.
10874  */
10875 static int
10876 flow_dv_translate(struct rte_eth_dev *dev,
10877                   struct mlx5_flow *dev_flow,
10878                   const struct rte_flow_attr *attr,
10879                   const struct rte_flow_item items[],
10880                   const struct rte_flow_action actions[],
10881                   struct rte_flow_error *error)
10882 {
10883         struct mlx5_priv *priv = dev->data->dev_private;
10884         struct mlx5_dev_config *dev_conf = &priv->config;
10885         struct rte_flow *flow = dev_flow->flow;
10886         struct mlx5_flow_handle *handle = dev_flow->handle;
10887         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10888         struct mlx5_flow_rss_desc *rss_desc;
10889         uint64_t item_flags = 0;
10890         uint64_t last_item = 0;
10891         uint64_t action_flags = 0;
10892         struct mlx5_flow_dv_matcher matcher = {
10893                 .mask = {
10894                         .size = sizeof(matcher.mask.buf) -
10895                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10896                 },
10897         };
10898         int actions_n = 0;
10899         bool actions_end = false;
10900         union {
10901                 struct mlx5_flow_dv_modify_hdr_resource res;
10902                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10903                             sizeof(struct mlx5_modification_cmd) *
10904                             (MLX5_MAX_MODIFY_NUM + 1)];
10905         } mhdr_dummy;
10906         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10907         const struct rte_flow_action_count *count = NULL;
10908         const struct rte_flow_action_age *age = NULL;
10909         union flow_dv_attr flow_attr = { .attr = 0 };
10910         uint32_t tag_be;
10911         union mlx5_flow_tbl_key tbl_key;
10912         uint32_t modify_action_position = UINT32_MAX;
10913         void *match_mask = matcher.mask.buf;
10914         void *match_value = dev_flow->dv.value.buf;
10915         uint8_t next_protocol = 0xff;
10916         struct rte_vlan_hdr vlan = { 0 };
10917         struct mlx5_flow_dv_dest_array_resource mdest_res;
10918         struct mlx5_flow_dv_sample_resource sample_res;
10919         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10920         const struct rte_flow_action_sample *sample = NULL;
10921         struct mlx5_flow_sub_actions_list *sample_act;
10922         uint32_t sample_act_pos = UINT32_MAX;
10923         uint32_t num_of_dest = 0;
10924         int tmp_actions_n = 0;
10925         uint32_t table;
10926         int ret = 0;
10927         const struct mlx5_flow_tunnel *tunnel;
10928         struct flow_grp_info grp_info = {
10929                 .external = !!dev_flow->external,
10930                 .transfer = !!attr->transfer,
10931                 .fdb_def_rule = !!priv->fdb_def_rule,
10932                 .skip_scale = dev_flow->skip_scale &
10933                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10934         };
10935
10936         if (!wks)
10937                 return rte_flow_error_set(error, ENOMEM,
10938                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10939                                           NULL,
10940                                           "failed to push flow workspace");
10941         rss_desc = &wks->rss_desc;
10942         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10943         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10944         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10945                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10946         /* update normal path action resource into last index of array */
10947         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10948         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10949                  flow_items_to_tunnel(items) :
10950                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10951                  flow_actions_to_tunnel(actions) :
10952                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10953         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10954                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10955         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10956                                 (dev, tunnel, attr, items, actions);
10957         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10958                                        &grp_info, error);
10959         if (ret)
10960                 return ret;
10961         dev_flow->dv.group = table;
10962         if (attr->transfer)
10963                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10964         /* number of actions must be set to 0 in case of dirty stack. */
10965         mhdr_res->actions_num = 0;
10966         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10967                 /*
10968                  * do not add decap action if match rule drops packet
10969                  * HW rejects rules with decap & drop
10970                  *
10971                  * if tunnel match rule was inserted before matching tunnel set
10972                  * rule flow table used in the match rule must be registered.
10973                  * current implementation handles that in the
10974                  * flow_dv_match_register() at the function end.
10975                  */
10976                 bool add_decap = true;
10977                 const struct rte_flow_action *ptr = actions;
10978
10979                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10980                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10981                                 add_decap = false;
10982                                 break;
10983                         }
10984                 }
10985                 if (add_decap) {
10986                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10987                                                            attr->transfer,
10988                                                            error))
10989                                 return -rte_errno;
10990                         dev_flow->dv.actions[actions_n++] =
10991                                         dev_flow->dv.encap_decap->action;
10992                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10993                 }
10994         }
10995         for (; !actions_end ; actions++) {
10996                 const struct rte_flow_action_queue *queue;
10997                 const struct rte_flow_action_rss *rss;
10998                 const struct rte_flow_action *action = actions;
10999                 const uint8_t *rss_key;
11000                 struct mlx5_flow_tbl_resource *tbl;
11001                 struct mlx5_aso_age_action *age_act;
11002                 uint32_t port_id = 0;
11003                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11004                 int action_type = actions->type;
11005                 const struct rte_flow_action *found_action = NULL;
11006                 uint32_t jump_group = 0;
11007
11008                 if (!mlx5_flow_os_action_supported(action_type))
11009                         return rte_flow_error_set(error, ENOTSUP,
11010                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11011                                                   actions,
11012                                                   "action not supported");
11013                 switch (action_type) {
11014                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11015                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11016                         break;
11017                 case RTE_FLOW_ACTION_TYPE_VOID:
11018                         break;
11019                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11020                         if (flow_dv_translate_action_port_id(dev, action,
11021                                                              &port_id, error))
11022                                 return -rte_errno;
11023                         port_id_resource.port_id = port_id;
11024                         MLX5_ASSERT(!handle->rix_port_id_action);
11025                         if (flow_dv_port_id_action_resource_register
11026                             (dev, &port_id_resource, dev_flow, error))
11027                                 return -rte_errno;
11028                         dev_flow->dv.actions[actions_n++] =
11029                                         dev_flow->dv.port_id_action->action;
11030                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11031                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11032                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11033                         num_of_dest++;
11034                         break;
11035                 case RTE_FLOW_ACTION_TYPE_FLAG:
11036                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11037                         dev_flow->handle->mark = 1;
11038                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11039                                 struct rte_flow_action_mark mark = {
11040                                         .id = MLX5_FLOW_MARK_DEFAULT,
11041                                 };
11042
11043                                 if (flow_dv_convert_action_mark(dev, &mark,
11044                                                                 mhdr_res,
11045                                                                 error))
11046                                         return -rte_errno;
11047                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11048                                 break;
11049                         }
11050                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11051                         /*
11052                          * Only one FLAG or MARK is supported per device flow
11053                          * right now. So the pointer to the tag resource must be
11054                          * zero before the register process.
11055                          */
11056                         MLX5_ASSERT(!handle->dvh.rix_tag);
11057                         if (flow_dv_tag_resource_register(dev, tag_be,
11058                                                           dev_flow, error))
11059                                 return -rte_errno;
11060                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11061                         dev_flow->dv.actions[actions_n++] =
11062                                         dev_flow->dv.tag_resource->action;
11063                         break;
11064                 case RTE_FLOW_ACTION_TYPE_MARK:
11065                         action_flags |= MLX5_FLOW_ACTION_MARK;
11066                         dev_flow->handle->mark = 1;
11067                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11068                                 const struct rte_flow_action_mark *mark =
11069                                         (const struct rte_flow_action_mark *)
11070                                                 actions->conf;
11071
11072                                 if (flow_dv_convert_action_mark(dev, mark,
11073                                                                 mhdr_res,
11074                                                                 error))
11075                                         return -rte_errno;
11076                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11077                                 break;
11078                         }
11079                         /* Fall-through */
11080                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11081                         /* Legacy (non-extensive) MARK action. */
11082                         tag_be = mlx5_flow_mark_set
11083                               (((const struct rte_flow_action_mark *)
11084                                (actions->conf))->id);
11085                         MLX5_ASSERT(!handle->dvh.rix_tag);
11086                         if (flow_dv_tag_resource_register(dev, tag_be,
11087                                                           dev_flow, error))
11088                                 return -rte_errno;
11089                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11090                         dev_flow->dv.actions[actions_n++] =
11091                                         dev_flow->dv.tag_resource->action;
11092                         break;
11093                 case RTE_FLOW_ACTION_TYPE_SET_META:
11094                         if (flow_dv_convert_action_set_meta
11095                                 (dev, mhdr_res, attr,
11096                                  (const struct rte_flow_action_set_meta *)
11097                                   actions->conf, error))
11098                                 return -rte_errno;
11099                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11100                         break;
11101                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11102                         if (flow_dv_convert_action_set_tag
11103                                 (dev, mhdr_res,
11104                                  (const struct rte_flow_action_set_tag *)
11105                                   actions->conf, error))
11106                                 return -rte_errno;
11107                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11108                         break;
11109                 case RTE_FLOW_ACTION_TYPE_DROP:
11110                         action_flags |= MLX5_FLOW_ACTION_DROP;
11111                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11112                         break;
11113                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11114                         queue = actions->conf;
11115                         rss_desc->queue_num = 1;
11116                         rss_desc->queue[0] = queue->index;
11117                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11118                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11119                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11120                         num_of_dest++;
11121                         break;
11122                 case RTE_FLOW_ACTION_TYPE_RSS:
11123                         rss = actions->conf;
11124                         memcpy(rss_desc->queue, rss->queue,
11125                                rss->queue_num * sizeof(uint16_t));
11126                         rss_desc->queue_num = rss->queue_num;
11127                         /* NULL RSS key indicates default RSS key. */
11128                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11129                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11130                         /*
11131                          * rss->level and rss.types should be set in advance
11132                          * when expanding items for RSS.
11133                          */
11134                         action_flags |= MLX5_FLOW_ACTION_RSS;
11135                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11136                                 MLX5_FLOW_FATE_SHARED_RSS :
11137                                 MLX5_FLOW_FATE_QUEUE;
11138                         break;
11139                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11140                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11141                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11142                         __atomic_fetch_add(&age_act->refcnt, 1,
11143                                            __ATOMIC_RELAXED);
11144                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11145                         action_flags |= MLX5_FLOW_ACTION_AGE;
11146                         break;
11147                 case RTE_FLOW_ACTION_TYPE_AGE:
11148                         if (priv->sh->flow_hit_aso_en && attr->group) {
11149                                 /*
11150                                  * Create one shared age action, to be used
11151                                  * by all sub-flows.
11152                                  */
11153                                 if (!flow->age) {
11154                                         flow->age =
11155                                                 flow_dv_translate_create_aso_age
11156                                                         (dev, action->conf,
11157                                                          error);
11158                                         if (!flow->age)
11159                                                 return rte_flow_error_set
11160                                                 (error, rte_errno,
11161                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11162                                                  NULL,
11163                                                  "can't create ASO age action");
11164                                 }
11165                                 dev_flow->dv.actions[actions_n++] =
11166                                           (flow_aso_age_get_by_idx
11167                                                 (dev, flow->age))->dr_action;
11168                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11169                                 break;
11170                         }
11171                         /* Fall-through */
11172                 case RTE_FLOW_ACTION_TYPE_COUNT:
11173                         if (!dev_conf->devx) {
11174                                 return rte_flow_error_set
11175                                               (error, ENOTSUP,
11176                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11177                                                NULL,
11178                                                "count action not supported");
11179                         }
11180                         /* Save information first, will apply later. */
11181                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11182                                 count = action->conf;
11183                         else
11184                                 age = action->conf;
11185                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11186                         break;
11187                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11188                         dev_flow->dv.actions[actions_n++] =
11189                                                 priv->sh->pop_vlan_action;
11190                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11191                         break;
11192                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11193                         if (!(action_flags &
11194                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11195                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11196                         vlan.eth_proto = rte_be_to_cpu_16
11197                              ((((const struct rte_flow_action_of_push_vlan *)
11198                                                    actions->conf)->ethertype));
11199                         found_action = mlx5_flow_find_action
11200                                         (actions + 1,
11201                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11202                         if (found_action)
11203                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11204                         found_action = mlx5_flow_find_action
11205                                         (actions + 1,
11206                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11207                         if (found_action)
11208                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11209                         if (flow_dv_create_action_push_vlan
11210                                             (dev, attr, &vlan, dev_flow, error))
11211                                 return -rte_errno;
11212                         dev_flow->dv.actions[actions_n++] =
11213                                         dev_flow->dv.push_vlan_res->action;
11214                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11215                         break;
11216                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11217                         /* of_vlan_push action handled this action */
11218                         MLX5_ASSERT(action_flags &
11219                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11220                         break;
11221                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11222                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11223                                 break;
11224                         flow_dev_get_vlan_info_from_items(items, &vlan);
11225                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11226                         /* If no VLAN push - this is a modify header action */
11227                         if (flow_dv_convert_action_modify_vlan_vid
11228                                                 (mhdr_res, actions, error))
11229                                 return -rte_errno;
11230                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11231                         break;
11232                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11233                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11234                         if (flow_dv_create_action_l2_encap(dev, actions,
11235                                                            dev_flow,
11236                                                            attr->transfer,
11237                                                            error))
11238                                 return -rte_errno;
11239                         dev_flow->dv.actions[actions_n++] =
11240                                         dev_flow->dv.encap_decap->action;
11241                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11242                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11243                                 sample_act->action_flags |=
11244                                                         MLX5_FLOW_ACTION_ENCAP;
11245                         break;
11246                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11247                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11248                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11249                                                            attr->transfer,
11250                                                            error))
11251                                 return -rte_errno;
11252                         dev_flow->dv.actions[actions_n++] =
11253                                         dev_flow->dv.encap_decap->action;
11254                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11255                         break;
11256                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11257                         /* Handle encap with preceding decap. */
11258                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11259                                 if (flow_dv_create_action_raw_encap
11260                                         (dev, actions, dev_flow, attr, error))
11261                                         return -rte_errno;
11262                                 dev_flow->dv.actions[actions_n++] =
11263                                         dev_flow->dv.encap_decap->action;
11264                         } else {
11265                                 /* Handle encap without preceding decap. */
11266                                 if (flow_dv_create_action_l2_encap
11267                                     (dev, actions, dev_flow, attr->transfer,
11268                                      error))
11269                                         return -rte_errno;
11270                                 dev_flow->dv.actions[actions_n++] =
11271                                         dev_flow->dv.encap_decap->action;
11272                         }
11273                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11274                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11275                                 sample_act->action_flags |=
11276                                                         MLX5_FLOW_ACTION_ENCAP;
11277                         break;
11278                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11279                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11280                                 ;
11281                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11282                                 if (flow_dv_create_action_l2_decap
11283                                     (dev, dev_flow, attr->transfer, error))
11284                                         return -rte_errno;
11285                                 dev_flow->dv.actions[actions_n++] =
11286                                         dev_flow->dv.encap_decap->action;
11287                         }
11288                         /* If decap is followed by encap, handle it at encap. */
11289                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11290                         break;
11291                 case RTE_FLOW_ACTION_TYPE_JUMP:
11292                         jump_group = ((const struct rte_flow_action_jump *)
11293                                                         action->conf)->group;
11294                         grp_info.std_tbl_fix = 0;
11295                         if (dev_flow->skip_scale &
11296                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11297                                 grp_info.skip_scale = 1;
11298                         else
11299                                 grp_info.skip_scale = 0;
11300                         ret = mlx5_flow_group_to_table(dev, tunnel,
11301                                                        jump_group,
11302                                                        &table,
11303                                                        &grp_info, error);
11304                         if (ret)
11305                                 return ret;
11306                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11307                                                        attr->transfer,
11308                                                        !!dev_flow->external,
11309                                                        tunnel, jump_group, 0,
11310                                                        error);
11311                         if (!tbl)
11312                                 return rte_flow_error_set
11313                                                 (error, errno,
11314                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11315                                                  NULL,
11316                                                  "cannot create jump action.");
11317                         if (flow_dv_jump_tbl_resource_register
11318                             (dev, tbl, dev_flow, error)) {
11319                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11320                                 return rte_flow_error_set
11321                                                 (error, errno,
11322                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11323                                                  NULL,
11324                                                  "cannot create jump action.");
11325                         }
11326                         dev_flow->dv.actions[actions_n++] =
11327                                         dev_flow->dv.jump->action;
11328                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11329                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11330                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11331                         num_of_dest++;
11332                         break;
11333                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11334                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11335                         if (flow_dv_convert_action_modify_mac
11336                                         (mhdr_res, actions, error))
11337                                 return -rte_errno;
11338                         action_flags |= actions->type ==
11339                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11340                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11341                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11342                         break;
11343                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11344                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11345                         if (flow_dv_convert_action_modify_ipv4
11346                                         (mhdr_res, actions, error))
11347                                 return -rte_errno;
11348                         action_flags |= actions->type ==
11349                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11350                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11351                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11352                         break;
11353                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11354                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11355                         if (flow_dv_convert_action_modify_ipv6
11356                                         (mhdr_res, actions, error))
11357                                 return -rte_errno;
11358                         action_flags |= actions->type ==
11359                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11360                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11361                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11362                         break;
11363                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11364                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11365                         if (flow_dv_convert_action_modify_tp
11366                                         (mhdr_res, actions, items,
11367                                          &flow_attr, dev_flow, !!(action_flags &
11368                                          MLX5_FLOW_ACTION_DECAP), error))
11369                                 return -rte_errno;
11370                         action_flags |= actions->type ==
11371                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11372                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11373                                         MLX5_FLOW_ACTION_SET_TP_DST;
11374                         break;
11375                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11376                         if (flow_dv_convert_action_modify_dec_ttl
11377                                         (mhdr_res, items, &flow_attr, dev_flow,
11378                                          !!(action_flags &
11379                                          MLX5_FLOW_ACTION_DECAP), error))
11380                                 return -rte_errno;
11381                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11382                         break;
11383                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11384                         if (flow_dv_convert_action_modify_ttl
11385                                         (mhdr_res, actions, items, &flow_attr,
11386                                          dev_flow, !!(action_flags &
11387                                          MLX5_FLOW_ACTION_DECAP), error))
11388                                 return -rte_errno;
11389                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11390                         break;
11391                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11392                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11393                         if (flow_dv_convert_action_modify_tcp_seq
11394                                         (mhdr_res, actions, error))
11395                                 return -rte_errno;
11396                         action_flags |= actions->type ==
11397                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11398                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11399                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11400                         break;
11401
11402                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11403                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11404                         if (flow_dv_convert_action_modify_tcp_ack
11405                                         (mhdr_res, actions, error))
11406                                 return -rte_errno;
11407                         action_flags |= actions->type ==
11408                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11409                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11410                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11411                         break;
11412                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11413                         if (flow_dv_convert_action_set_reg
11414                                         (mhdr_res, actions, error))
11415                                 return -rte_errno;
11416                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11417                         break;
11418                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11419                         if (flow_dv_convert_action_copy_mreg
11420                                         (dev, mhdr_res, actions, error))
11421                                 return -rte_errno;
11422                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11423                         break;
11424                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11425                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11426                         dev_flow->handle->fate_action =
11427                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11428                         break;
11429                 case RTE_FLOW_ACTION_TYPE_METER:
11430                         if (!wks->fm)
11431                                 return rte_flow_error_set(error, rte_errno,
11432                                         RTE_FLOW_ERROR_TYPE_ACTION,
11433                                         NULL, "Failed to get meter in flow.");
11434                         /* Set the meter action. */
11435                         dev_flow->dv.actions[actions_n++] =
11436                                 wks->fm->mfts->meter_action;
11437                         action_flags |= MLX5_FLOW_ACTION_METER;
11438                         break;
11439                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11440                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11441                                                               actions, error))
11442                                 return -rte_errno;
11443                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11444                         break;
11445                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11446                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11447                                                               actions, error))
11448                                 return -rte_errno;
11449                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11450                         break;
11451                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11452                         sample_act_pos = actions_n;
11453                         sample = (const struct rte_flow_action_sample *)
11454                                  action->conf;
11455                         actions_n++;
11456                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11457                         /* put encap action into group if work with port id */
11458                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11459                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11460                                 sample_act->action_flags |=
11461                                                         MLX5_FLOW_ACTION_ENCAP;
11462                         break;
11463                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11464                         if (flow_dv_convert_action_modify_field
11465                                         (dev, mhdr_res, actions, attr, error))
11466                                 return -rte_errno;
11467                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11468                         break;
11469                 case RTE_FLOW_ACTION_TYPE_END:
11470                         actions_end = true;
11471                         if (mhdr_res->actions_num) {
11472                                 /* create modify action if needed. */
11473                                 if (flow_dv_modify_hdr_resource_register
11474                                         (dev, mhdr_res, dev_flow, error))
11475                                         return -rte_errno;
11476                                 dev_flow->dv.actions[modify_action_position] =
11477                                         handle->dvh.modify_hdr->action;
11478                         }
11479                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11480                                 /*
11481                                  * Create one count action, to be used
11482                                  * by all sub-flows.
11483                                  */
11484                                 if (!flow->counter) {
11485                                         flow->counter =
11486                                                 flow_dv_translate_create_counter
11487                                                         (dev, dev_flow, count,
11488                                                          age);
11489                                         if (!flow->counter)
11490                                                 return rte_flow_error_set
11491                                                 (error, rte_errno,
11492                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11493                                                  NULL, "cannot create counter"
11494                                                  " object.");
11495                                 }
11496                                 dev_flow->dv.actions[actions_n] =
11497                                           (flow_dv_counter_get_by_idx(dev,
11498                                           flow->counter, NULL))->action;
11499                                 actions_n++;
11500                         }
11501                 default:
11502                         break;
11503                 }
11504                 if (mhdr_res->actions_num &&
11505                     modify_action_position == UINT32_MAX)
11506                         modify_action_position = actions_n++;
11507         }
11508         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11509                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11510                 int item_type = items->type;
11511
11512                 if (!mlx5_flow_os_item_supported(item_type))
11513                         return rte_flow_error_set(error, ENOTSUP,
11514                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11515                                                   NULL, "item not supported");
11516                 switch (item_type) {
11517                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11518                         flow_dv_translate_item_port_id
11519                                 (dev, match_mask, match_value, items, attr);
11520                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11521                         break;
11522                 case RTE_FLOW_ITEM_TYPE_ETH:
11523                         flow_dv_translate_item_eth(match_mask, match_value,
11524                                                    items, tunnel,
11525                                                    dev_flow->dv.group);
11526                         matcher.priority = action_flags &
11527                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11528                                         !dev_flow->external ?
11529                                         MLX5_PRIORITY_MAP_L3 :
11530                                         MLX5_PRIORITY_MAP_L2;
11531                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11532                                              MLX5_FLOW_LAYER_OUTER_L2;
11533                         break;
11534                 case RTE_FLOW_ITEM_TYPE_VLAN:
11535                         flow_dv_translate_item_vlan(dev_flow,
11536                                                     match_mask, match_value,
11537                                                     items, tunnel,
11538                                                     dev_flow->dv.group);
11539                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11540                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11541                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11542                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11543                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11544                         break;
11545                 case RTE_FLOW_ITEM_TYPE_IPV4:
11546                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11547                                                   &item_flags, &tunnel);
11548                         flow_dv_translate_item_ipv4(match_mask, match_value,
11549                                                     items, tunnel,
11550                                                     dev_flow->dv.group);
11551                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11552                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11553                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11554                         if (items->mask != NULL &&
11555                             ((const struct rte_flow_item_ipv4 *)
11556                              items->mask)->hdr.next_proto_id) {
11557                                 next_protocol =
11558                                         ((const struct rte_flow_item_ipv4 *)
11559                                          (items->spec))->hdr.next_proto_id;
11560                                 next_protocol &=
11561                                         ((const struct rte_flow_item_ipv4 *)
11562                                          (items->mask))->hdr.next_proto_id;
11563                         } else {
11564                                 /* Reset for inner layer. */
11565                                 next_protocol = 0xff;
11566                         }
11567                         break;
11568                 case RTE_FLOW_ITEM_TYPE_IPV6:
11569                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11570                                                   &item_flags, &tunnel);
11571                         flow_dv_translate_item_ipv6(match_mask, match_value,
11572                                                     items, tunnel,
11573                                                     dev_flow->dv.group);
11574                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11575                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11576                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11577                         if (items->mask != NULL &&
11578                             ((const struct rte_flow_item_ipv6 *)
11579                              items->mask)->hdr.proto) {
11580                                 next_protocol =
11581                                         ((const struct rte_flow_item_ipv6 *)
11582                                          items->spec)->hdr.proto;
11583                                 next_protocol &=
11584                                         ((const struct rte_flow_item_ipv6 *)
11585                                          items->mask)->hdr.proto;
11586                         } else {
11587                                 /* Reset for inner layer. */
11588                                 next_protocol = 0xff;
11589                         }
11590                         break;
11591                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11592                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11593                                                              match_value,
11594                                                              items, tunnel);
11595                         last_item = tunnel ?
11596                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11597                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11598                         if (items->mask != NULL &&
11599                             ((const struct rte_flow_item_ipv6_frag_ext *)
11600                              items->mask)->hdr.next_header) {
11601                                 next_protocol =
11602                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11603                                  items->spec)->hdr.next_header;
11604                                 next_protocol &=
11605                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11606                                  items->mask)->hdr.next_header;
11607                         } else {
11608                                 /* Reset for inner layer. */
11609                                 next_protocol = 0xff;
11610                         }
11611                         break;
11612                 case RTE_FLOW_ITEM_TYPE_TCP:
11613                         flow_dv_translate_item_tcp(match_mask, match_value,
11614                                                    items, tunnel);
11615                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11616                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11617                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11618                         break;
11619                 case RTE_FLOW_ITEM_TYPE_UDP:
11620                         flow_dv_translate_item_udp(match_mask, match_value,
11621                                                    items, tunnel);
11622                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11623                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11624                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11625                         break;
11626                 case RTE_FLOW_ITEM_TYPE_GRE:
11627                         flow_dv_translate_item_gre(match_mask, match_value,
11628                                                    items, tunnel);
11629                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11630                         last_item = MLX5_FLOW_LAYER_GRE;
11631                         break;
11632                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11633                         flow_dv_translate_item_gre_key(match_mask,
11634                                                        match_value, items);
11635                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11636                         break;
11637                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11638                         flow_dv_translate_item_nvgre(match_mask, match_value,
11639                                                      items, tunnel);
11640                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11641                         last_item = MLX5_FLOW_LAYER_GRE;
11642                         break;
11643                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11644                         flow_dv_translate_item_vxlan(match_mask, match_value,
11645                                                      items, tunnel);
11646                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11647                         last_item = MLX5_FLOW_LAYER_VXLAN;
11648                         break;
11649                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11650                         flow_dv_translate_item_vxlan_gpe(match_mask,
11651                                                          match_value, items,
11652                                                          tunnel);
11653                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11654                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11655                         break;
11656                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11657                         flow_dv_translate_item_geneve(match_mask, match_value,
11658                                                       items, tunnel);
11659                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11660                         last_item = MLX5_FLOW_LAYER_GENEVE;
11661                         break;
11662                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11663                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11664                                                           match_value,
11665                                                           items, error);
11666                         if (ret)
11667                                 return rte_flow_error_set(error, -ret,
11668                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11669                                         "cannot create GENEVE TLV option");
11670                         flow->geneve_tlv_option = 1;
11671                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11672                         break;
11673                 case RTE_FLOW_ITEM_TYPE_MPLS:
11674                         flow_dv_translate_item_mpls(match_mask, match_value,
11675                                                     items, last_item, tunnel);
11676                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11677                         last_item = MLX5_FLOW_LAYER_MPLS;
11678                         break;
11679                 case RTE_FLOW_ITEM_TYPE_MARK:
11680                         flow_dv_translate_item_mark(dev, match_mask,
11681                                                     match_value, items);
11682                         last_item = MLX5_FLOW_ITEM_MARK;
11683                         break;
11684                 case RTE_FLOW_ITEM_TYPE_META:
11685                         flow_dv_translate_item_meta(dev, match_mask,
11686                                                     match_value, attr, items);
11687                         last_item = MLX5_FLOW_ITEM_METADATA;
11688                         break;
11689                 case RTE_FLOW_ITEM_TYPE_ICMP:
11690                         flow_dv_translate_item_icmp(match_mask, match_value,
11691                                                     items, tunnel);
11692                         last_item = MLX5_FLOW_LAYER_ICMP;
11693                         break;
11694                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11695                         flow_dv_translate_item_icmp6(match_mask, match_value,
11696                                                       items, tunnel);
11697                         last_item = MLX5_FLOW_LAYER_ICMP6;
11698                         break;
11699                 case RTE_FLOW_ITEM_TYPE_TAG:
11700                         flow_dv_translate_item_tag(dev, match_mask,
11701                                                    match_value, items);
11702                         last_item = MLX5_FLOW_ITEM_TAG;
11703                         break;
11704                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11705                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11706                                                         match_value, items);
11707                         last_item = MLX5_FLOW_ITEM_TAG;
11708                         break;
11709                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11710                         flow_dv_translate_item_tx_queue(dev, match_mask,
11711                                                         match_value,
11712                                                         items);
11713                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11714                         break;
11715                 case RTE_FLOW_ITEM_TYPE_GTP:
11716                         flow_dv_translate_item_gtp(match_mask, match_value,
11717                                                    items, tunnel);
11718                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11719                         last_item = MLX5_FLOW_LAYER_GTP;
11720                         break;
11721                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11722                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11723                                                           match_value,
11724                                                           items);
11725                         if (ret)
11726                                 return rte_flow_error_set(error, -ret,
11727                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11728                                         "cannot create GTP PSC item");
11729                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11730                         break;
11731                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11732                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11733                                 /* Create it only the first time to be used. */
11734                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11735                                 if (ret)
11736                                         return rte_flow_error_set
11737                                                 (error, -ret,
11738                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11739                                                 NULL,
11740                                                 "cannot create eCPRI parser");
11741                         }
11742                         /* Adjust the length matcher and device flow value. */
11743                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11744                         dev_flow->dv.value.size =
11745                                         MLX5_ST_SZ_BYTES(fte_match_param);
11746                         flow_dv_translate_item_ecpri(dev, match_mask,
11747                                                      match_value, items);
11748                         /* No other protocol should follow eCPRI layer. */
11749                         last_item = MLX5_FLOW_LAYER_ECPRI;
11750                         break;
11751                 default:
11752                         break;
11753                 }
11754                 item_flags |= last_item;
11755         }
11756         /*
11757          * When E-Switch mode is enabled, we have two cases where we need to
11758          * set the source port manually.
11759          * The first one, is in case of Nic steering rule, and the second is
11760          * E-Switch rule where no port_id item was found. In both cases
11761          * the source port is set according the current port in use.
11762          */
11763         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11764             (priv->representor || priv->master)) {
11765                 if (flow_dv_translate_item_port_id(dev, match_mask,
11766                                                    match_value, NULL, attr))
11767                         return -rte_errno;
11768         }
11769 #ifdef RTE_LIBRTE_MLX5_DEBUG
11770         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11771                                               dev_flow->dv.value.buf));
11772 #endif
11773         /*
11774          * Layers may be already initialized from prefix flow if this dev_flow
11775          * is the suffix flow.
11776          */
11777         handle->layers |= item_flags;
11778         if (action_flags & MLX5_FLOW_ACTION_RSS)
11779                 flow_dv_hashfields_set(dev_flow, rss_desc);
11780         /* If has RSS action in the sample action, the Sample/Mirror resource
11781          * should be registered after the hash filed be update.
11782          */
11783         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11784                 ret = flow_dv_translate_action_sample(dev,
11785                                                       sample,
11786                                                       dev_flow, attr,
11787                                                       &num_of_dest,
11788                                                       sample_actions,
11789                                                       &sample_res,
11790                                                       error);
11791                 if (ret < 0)
11792                         return ret;
11793                 ret = flow_dv_create_action_sample(dev,
11794                                                    dev_flow,
11795                                                    num_of_dest,
11796                                                    &sample_res,
11797                                                    &mdest_res,
11798                                                    sample_actions,
11799                                                    action_flags,
11800                                                    error);
11801                 if (ret < 0)
11802                         return rte_flow_error_set
11803                                                 (error, rte_errno,
11804                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11805                                                 NULL,
11806                                                 "cannot create sample action");
11807                 if (num_of_dest > 1) {
11808                         dev_flow->dv.actions[sample_act_pos] =
11809                         dev_flow->dv.dest_array_res->action;
11810                 } else {
11811                         dev_flow->dv.actions[sample_act_pos] =
11812                         dev_flow->dv.sample_res->verbs_action;
11813                 }
11814         }
11815         /*
11816          * For multiple destination (sample action with ratio=1), the encap
11817          * action and port id action will be combined into group action.
11818          * So need remove the original these actions in the flow and only
11819          * use the sample action instead of.
11820          */
11821         if (num_of_dest > 1 &&
11822             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11823                 int i;
11824                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11825
11826                 for (i = 0; i < actions_n; i++) {
11827                         if ((sample_act->dr_encap_action &&
11828                                 sample_act->dr_encap_action ==
11829                                 dev_flow->dv.actions[i]) ||
11830                                 (sample_act->dr_port_id_action &&
11831                                 sample_act->dr_port_id_action ==
11832                                 dev_flow->dv.actions[i]) ||
11833                                 (sample_act->dr_jump_action &&
11834                                 sample_act->dr_jump_action ==
11835                                 dev_flow->dv.actions[i]))
11836                                 continue;
11837                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11838                 }
11839                 memcpy((void *)dev_flow->dv.actions,
11840                                 (void *)temp_actions,
11841                                 tmp_actions_n * sizeof(void *));
11842                 actions_n = tmp_actions_n;
11843         }
11844         dev_flow->dv.actions_n = actions_n;
11845         dev_flow->act_flags = action_flags;
11846         /* Register matcher. */
11847         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11848                                     matcher.mask.size);
11849         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11850                                         matcher.priority);
11851         /* reserved field no needs to be set to 0 here. */
11852         tbl_key.domain = attr->transfer;
11853         tbl_key.direction = attr->egress;
11854         tbl_key.table_id = dev_flow->dv.group;
11855         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11856                                      tunnel, attr->group, error))
11857                 return -rte_errno;
11858         return 0;
11859 }
11860
11861 /**
11862  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11863  * and tunnel.
11864  *
11865  * @param[in, out] action
11866  *   Shred RSS action holding hash RX queue objects.
11867  * @param[in] hash_fields
11868  *   Defines combination of packet fields to participate in RX hash.
11869  * @param[in] tunnel
11870  *   Tunnel type
11871  * @param[in] hrxq_idx
11872  *   Hash RX queue index to set.
11873  *
11874  * @return
11875  *   0 on success, otherwise negative errno value.
11876  */
11877 static int
11878 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11879                               const uint64_t hash_fields,
11880                               uint32_t hrxq_idx)
11881 {
11882         uint32_t *hrxqs = action->hrxq;
11883
11884         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11885         case MLX5_RSS_HASH_IPV4:
11886                 /* fall-through. */
11887         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11888                 /* fall-through. */
11889         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11890                 hrxqs[0] = hrxq_idx;
11891                 return 0;
11892         case MLX5_RSS_HASH_IPV4_TCP:
11893                 /* fall-through. */
11894         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11895                 /* fall-through. */
11896         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11897                 hrxqs[1] = hrxq_idx;
11898                 return 0;
11899         case MLX5_RSS_HASH_IPV4_UDP:
11900                 /* fall-through. */
11901         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11902                 /* fall-through. */
11903         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11904                 hrxqs[2] = hrxq_idx;
11905                 return 0;
11906         case MLX5_RSS_HASH_IPV6:
11907                 /* fall-through. */
11908         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11909                 /* fall-through. */
11910         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11911                 hrxqs[3] = hrxq_idx;
11912                 return 0;
11913         case MLX5_RSS_HASH_IPV6_TCP:
11914                 /* fall-through. */
11915         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11916                 /* fall-through. */
11917         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11918                 hrxqs[4] = hrxq_idx;
11919                 return 0;
11920         case MLX5_RSS_HASH_IPV6_UDP:
11921                 /* fall-through. */
11922         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11923                 /* fall-through. */
11924         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11925                 hrxqs[5] = hrxq_idx;
11926                 return 0;
11927         case MLX5_RSS_HASH_NONE:
11928                 hrxqs[6] = hrxq_idx;
11929                 return 0;
11930         default:
11931                 return -1;
11932         }
11933 }
11934
11935 /**
11936  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11937  * and tunnel.
11938  *
11939  * @param[in] dev
11940  *   Pointer to the Ethernet device structure.
11941  * @param[in] idx
11942  *   Shared RSS action ID holding hash RX queue objects.
11943  * @param[in] hash_fields
11944  *   Defines combination of packet fields to participate in RX hash.
11945  * @param[in] tunnel
11946  *   Tunnel type
11947  *
11948  * @return
11949  *   Valid hash RX queue index, otherwise 0.
11950  */
11951 static uint32_t
11952 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11953                                  const uint64_t hash_fields)
11954 {
11955         struct mlx5_priv *priv = dev->data->dev_private;
11956         struct mlx5_shared_action_rss *shared_rss =
11957             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11958         const uint32_t *hrxqs = shared_rss->hrxq;
11959
11960         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11961         case MLX5_RSS_HASH_IPV4:
11962                 /* fall-through. */
11963         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11964                 /* fall-through. */
11965         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11966                 return hrxqs[0];
11967         case MLX5_RSS_HASH_IPV4_TCP:
11968                 /* fall-through. */
11969         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11970                 /* fall-through. */
11971         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11972                 return hrxqs[1];
11973         case MLX5_RSS_HASH_IPV4_UDP:
11974                 /* fall-through. */
11975         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11976                 /* fall-through. */
11977         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11978                 return hrxqs[2];
11979         case MLX5_RSS_HASH_IPV6:
11980                 /* fall-through. */
11981         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11982                 /* fall-through. */
11983         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11984                 return hrxqs[3];
11985         case MLX5_RSS_HASH_IPV6_TCP:
11986                 /* fall-through. */
11987         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11988                 /* fall-through. */
11989         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11990                 return hrxqs[4];
11991         case MLX5_RSS_HASH_IPV6_UDP:
11992                 /* fall-through. */
11993         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11994                 /* fall-through. */
11995         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11996                 return hrxqs[5];
11997         case MLX5_RSS_HASH_NONE:
11998                 return hrxqs[6];
11999         default:
12000                 return 0;
12001         }
12002
12003 }
12004
12005 /**
12006  * Apply the flow to the NIC, lock free,
12007  * (mutex should be acquired by caller).
12008  *
12009  * @param[in] dev
12010  *   Pointer to the Ethernet device structure.
12011  * @param[in, out] flow
12012  *   Pointer to flow structure.
12013  * @param[out] error
12014  *   Pointer to error structure.
12015  *
12016  * @return
12017  *   0 on success, a negative errno value otherwise and rte_errno is set.
12018  */
12019 static int
12020 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12021               struct rte_flow_error *error)
12022 {
12023         struct mlx5_flow_dv_workspace *dv;
12024         struct mlx5_flow_handle *dh;
12025         struct mlx5_flow_handle_dv *dv_h;
12026         struct mlx5_flow *dev_flow;
12027         struct mlx5_priv *priv = dev->data->dev_private;
12028         uint32_t handle_idx;
12029         int n;
12030         int err;
12031         int idx;
12032         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12033         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12034
12035         MLX5_ASSERT(wks);
12036         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12037                 dev_flow = &wks->flows[idx];
12038                 dv = &dev_flow->dv;
12039                 dh = dev_flow->handle;
12040                 dv_h = &dh->dvh;
12041                 n = dv->actions_n;
12042                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12043                         if (dv->transfer) {
12044                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12045                                 dv->actions[n++] = priv->sh->dr_drop_action;
12046                         } else {
12047 #ifdef HAVE_MLX5DV_DR
12048                                 /* DR supports drop action placeholder. */
12049                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12050                                 dv->actions[n++] = priv->sh->dr_drop_action;
12051 #else
12052                                 /* For DV we use the explicit drop queue. */
12053                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12054                                 dv->actions[n++] =
12055                                                 priv->drop_queue.hrxq->action;
12056 #endif
12057                         }
12058                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12059                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12060                         struct mlx5_hrxq *hrxq;
12061                         uint32_t hrxq_idx;
12062
12063                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12064                                                     &hrxq_idx);
12065                         if (!hrxq) {
12066                                 rte_flow_error_set
12067                                         (error, rte_errno,
12068                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12069                                          "cannot get hash queue");
12070                                 goto error;
12071                         }
12072                         dh->rix_hrxq = hrxq_idx;
12073                         dv->actions[n++] = hrxq->action;
12074                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12075                         struct mlx5_hrxq *hrxq = NULL;
12076                         uint32_t hrxq_idx;
12077
12078                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12079                                                 rss_desc->shared_rss,
12080                                                 dev_flow->hash_fields);
12081                         if (hrxq_idx)
12082                                 hrxq = mlx5_ipool_get
12083                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12084                                          hrxq_idx);
12085                         if (!hrxq) {
12086                                 rte_flow_error_set
12087                                         (error, rte_errno,
12088                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12089                                          "cannot get hash queue");
12090                                 goto error;
12091                         }
12092                         dh->rix_srss = rss_desc->shared_rss;
12093                         dv->actions[n++] = hrxq->action;
12094                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12095                         if (!priv->sh->default_miss_action) {
12096                                 rte_flow_error_set
12097                                         (error, rte_errno,
12098                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12099                                          "default miss action not be created.");
12100                                 goto error;
12101                         }
12102                         dv->actions[n++] = priv->sh->default_miss_action;
12103                 }
12104                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12105                                                (void *)&dv->value, n,
12106                                                dv->actions, &dh->drv_flow);
12107                 if (err) {
12108                         rte_flow_error_set(error, errno,
12109                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12110                                            NULL,
12111                                            "hardware refuses to create flow");
12112                         goto error;
12113                 }
12114                 if (priv->vmwa_context &&
12115                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12116                         /*
12117                          * The rule contains the VLAN pattern.
12118                          * For VF we are going to create VLAN
12119                          * interface to make hypervisor set correct
12120                          * e-Switch vport context.
12121                          */
12122                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12123                 }
12124         }
12125         return 0;
12126 error:
12127         err = rte_errno; /* Save rte_errno before cleanup. */
12128         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12129                        handle_idx, dh, next) {
12130                 /* hrxq is union, don't clear it if the flag is not set. */
12131                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12132                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12133                         dh->rix_hrxq = 0;
12134                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12135                         dh->rix_srss = 0;
12136                 }
12137                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12138                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12139         }
12140         rte_errno = err; /* Restore rte_errno. */
12141         return -rte_errno;
12142 }
12143
12144 void
12145 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12146                           struct mlx5_cache_entry *entry)
12147 {
12148         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12149                                                           entry);
12150
12151         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12152         mlx5_free(cache);
12153 }
12154
12155 /**
12156  * Release the flow matcher.
12157  *
12158  * @param dev
12159  *   Pointer to Ethernet device.
12160  * @param port_id
12161  *   Index to port ID action resource.
12162  *
12163  * @return
12164  *   1 while a reference on it exists, 0 when freed.
12165  */
12166 static int
12167 flow_dv_matcher_release(struct rte_eth_dev *dev,
12168                         struct mlx5_flow_handle *handle)
12169 {
12170         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12171         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12172                                                             typeof(*tbl), tbl);
12173         int ret;
12174
12175         MLX5_ASSERT(matcher->matcher_object);
12176         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12177         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12178         return ret;
12179 }
12180
12181 /**
12182  * Release encap_decap resource.
12183  *
12184  * @param list
12185  *   Pointer to the hash list.
12186  * @param entry
12187  *   Pointer to exist resource entry object.
12188  */
12189 void
12190 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12191                               struct mlx5_hlist_entry *entry)
12192 {
12193         struct mlx5_dev_ctx_shared *sh = list->ctx;
12194         struct mlx5_flow_dv_encap_decap_resource *res =
12195                 container_of(entry, typeof(*res), entry);
12196
12197         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12198         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12199 }
12200
12201 /**
12202  * Release an encap/decap resource.
12203  *
12204  * @param dev
12205  *   Pointer to Ethernet device.
12206  * @param encap_decap_idx
12207  *   Index of encap decap resource.
12208  *
12209  * @return
12210  *   1 while a reference on it exists, 0 when freed.
12211  */
12212 static int
12213 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12214                                      uint32_t encap_decap_idx)
12215 {
12216         struct mlx5_priv *priv = dev->data->dev_private;
12217         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12218
12219         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12220                                         encap_decap_idx);
12221         if (!cache_resource)
12222                 return 0;
12223         MLX5_ASSERT(cache_resource->action);
12224         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12225                                      &cache_resource->entry);
12226 }
12227
12228 /**
12229  * Release an jump to table action resource.
12230  *
12231  * @param dev
12232  *   Pointer to Ethernet device.
12233  * @param rix_jump
12234  *   Index to the jump action resource.
12235  *
12236  * @return
12237  *   1 while a reference on it exists, 0 when freed.
12238  */
12239 static int
12240 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12241                                   uint32_t rix_jump)
12242 {
12243         struct mlx5_priv *priv = dev->data->dev_private;
12244         struct mlx5_flow_tbl_data_entry *tbl_data;
12245
12246         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12247                                   rix_jump);
12248         if (!tbl_data)
12249                 return 0;
12250         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12251 }
12252
12253 void
12254 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12255                          struct mlx5_hlist_entry *entry)
12256 {
12257         struct mlx5_flow_dv_modify_hdr_resource *res =
12258                 container_of(entry, typeof(*res), entry);
12259
12260         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12261         mlx5_free(entry);
12262 }
12263
12264 /**
12265  * Release a modify-header resource.
12266  *
12267  * @param dev
12268  *   Pointer to Ethernet device.
12269  * @param handle
12270  *   Pointer to mlx5_flow_handle.
12271  *
12272  * @return
12273  *   1 while a reference on it exists, 0 when freed.
12274  */
12275 static int
12276 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12277                                     struct mlx5_flow_handle *handle)
12278 {
12279         struct mlx5_priv *priv = dev->data->dev_private;
12280         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12281
12282         MLX5_ASSERT(entry->action);
12283         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12284 }
12285
12286 void
12287 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12288                           struct mlx5_cache_entry *entry)
12289 {
12290         struct mlx5_dev_ctx_shared *sh = list->ctx;
12291         struct mlx5_flow_dv_port_id_action_resource *cache =
12292                         container_of(entry, typeof(*cache), entry);
12293
12294         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12295         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12296 }
12297
12298 /**
12299  * Release port ID action resource.
12300  *
12301  * @param dev
12302  *   Pointer to Ethernet device.
12303  * @param handle
12304  *   Pointer to mlx5_flow_handle.
12305  *
12306  * @return
12307  *   1 while a reference on it exists, 0 when freed.
12308  */
12309 static int
12310 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12311                                         uint32_t port_id)
12312 {
12313         struct mlx5_priv *priv = dev->data->dev_private;
12314         struct mlx5_flow_dv_port_id_action_resource *cache;
12315
12316         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12317         if (!cache)
12318                 return 0;
12319         MLX5_ASSERT(cache->action);
12320         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12321                                      &cache->entry);
12322 }
12323
12324 /**
12325  * Release shared RSS action resource.
12326  *
12327  * @param dev
12328  *   Pointer to Ethernet device.
12329  * @param srss
12330  *   Shared RSS action index.
12331  */
12332 static void
12333 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12334 {
12335         struct mlx5_priv *priv = dev->data->dev_private;
12336         struct mlx5_shared_action_rss *shared_rss;
12337
12338         shared_rss = mlx5_ipool_get
12339                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12340         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12341 }
12342
12343 void
12344 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12345                             struct mlx5_cache_entry *entry)
12346 {
12347         struct mlx5_dev_ctx_shared *sh = list->ctx;
12348         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12349                         container_of(entry, typeof(*cache), entry);
12350
12351         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12352         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12353 }
12354
12355 /**
12356  * Release push vlan action resource.
12357  *
12358  * @param dev
12359  *   Pointer to Ethernet device.
12360  * @param handle
12361  *   Pointer to mlx5_flow_handle.
12362  *
12363  * @return
12364  *   1 while a reference on it exists, 0 when freed.
12365  */
12366 static int
12367 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12368                                           struct mlx5_flow_handle *handle)
12369 {
12370         struct mlx5_priv *priv = dev->data->dev_private;
12371         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12372         uint32_t idx = handle->dvh.rix_push_vlan;
12373
12374         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12375         if (!cache)
12376                 return 0;
12377         MLX5_ASSERT(cache->action);
12378         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12379                                      &cache->entry);
12380 }
12381
12382 /**
12383  * Release the fate resource.
12384  *
12385  * @param dev
12386  *   Pointer to Ethernet device.
12387  * @param handle
12388  *   Pointer to mlx5_flow_handle.
12389  */
12390 static void
12391 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12392                                struct mlx5_flow_handle *handle)
12393 {
12394         if (!handle->rix_fate)
12395                 return;
12396         switch (handle->fate_action) {
12397         case MLX5_FLOW_FATE_QUEUE:
12398                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12399                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12400                 break;
12401         case MLX5_FLOW_FATE_JUMP:
12402                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12403                 break;
12404         case MLX5_FLOW_FATE_PORT_ID:
12405                 flow_dv_port_id_action_resource_release(dev,
12406                                 handle->rix_port_id_action);
12407                 break;
12408         default:
12409                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12410                 break;
12411         }
12412         handle->rix_fate = 0;
12413 }
12414
12415 void
12416 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12417                          struct mlx5_cache_entry *entry)
12418 {
12419         struct mlx5_flow_dv_sample_resource *cache_resource =
12420                         container_of(entry, typeof(*cache_resource), entry);
12421         struct rte_eth_dev *dev = cache_resource->dev;
12422         struct mlx5_priv *priv = dev->data->dev_private;
12423
12424         if (cache_resource->verbs_action)
12425                 claim_zero(mlx5_flow_os_destroy_flow_action
12426                                 (cache_resource->verbs_action));
12427         if (cache_resource->normal_path_tbl)
12428                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12429                         cache_resource->normal_path_tbl);
12430         flow_dv_sample_sub_actions_release(dev,
12431                                 &cache_resource->sample_idx);
12432         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12433                         cache_resource->idx);
12434         DRV_LOG(DEBUG, "sample resource %p: removed",
12435                 (void *)cache_resource);
12436 }
12437
12438 /**
12439  * Release an sample resource.
12440  *
12441  * @param dev
12442  *   Pointer to Ethernet device.
12443  * @param handle
12444  *   Pointer to mlx5_flow_handle.
12445  *
12446  * @return
12447  *   1 while a reference on it exists, 0 when freed.
12448  */
12449 static int
12450 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12451                                      struct mlx5_flow_handle *handle)
12452 {
12453         struct mlx5_priv *priv = dev->data->dev_private;
12454         struct mlx5_flow_dv_sample_resource *cache_resource;
12455
12456         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12457                          handle->dvh.rix_sample);
12458         if (!cache_resource)
12459                 return 0;
12460         MLX5_ASSERT(cache_resource->verbs_action);
12461         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12462                                      &cache_resource->entry);
12463 }
12464
12465 void
12466 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12467                              struct mlx5_cache_entry *entry)
12468 {
12469         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12470                         container_of(entry, typeof(*cache_resource), entry);
12471         struct rte_eth_dev *dev = cache_resource->dev;
12472         struct mlx5_priv *priv = dev->data->dev_private;
12473         uint32_t i = 0;
12474
12475         MLX5_ASSERT(cache_resource->action);
12476         if (cache_resource->action)
12477                 claim_zero(mlx5_flow_os_destroy_flow_action
12478                                         (cache_resource->action));
12479         for (; i < cache_resource->num_of_dest; i++)
12480                 flow_dv_sample_sub_actions_release(dev,
12481                                 &cache_resource->sample_idx[i]);
12482         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12483                         cache_resource->idx);
12484         DRV_LOG(DEBUG, "destination array resource %p: removed",
12485                 (void *)cache_resource);
12486 }
12487
12488 /**
12489  * Release an destination array resource.
12490  *
12491  * @param dev
12492  *   Pointer to Ethernet device.
12493  * @param handle
12494  *   Pointer to mlx5_flow_handle.
12495  *
12496  * @return
12497  *   1 while a reference on it exists, 0 when freed.
12498  */
12499 static int
12500 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12501                                     struct mlx5_flow_handle *handle)
12502 {
12503         struct mlx5_priv *priv = dev->data->dev_private;
12504         struct mlx5_flow_dv_dest_array_resource *cache;
12505
12506         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12507                                handle->dvh.rix_dest_array);
12508         if (!cache)
12509                 return 0;
12510         MLX5_ASSERT(cache->action);
12511         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12512                                      &cache->entry);
12513 }
12514
12515 static void
12516 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12517 {
12518         struct mlx5_priv *priv = dev->data->dev_private;
12519         struct mlx5_dev_ctx_shared *sh = priv->sh;
12520         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12521                                 sh->geneve_tlv_option_resource;
12522         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12523         if (geneve_opt_resource) {
12524                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12525                                          __ATOMIC_RELAXED))) {
12526                         claim_zero(mlx5_devx_cmd_destroy
12527                                         (geneve_opt_resource->obj));
12528                         mlx5_free(sh->geneve_tlv_option_resource);
12529                         sh->geneve_tlv_option_resource = NULL;
12530                 }
12531         }
12532         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12533 }
12534
12535 /**
12536  * Remove the flow from the NIC but keeps it in memory.
12537  * Lock free, (mutex should be acquired by caller).
12538  *
12539  * @param[in] dev
12540  *   Pointer to Ethernet device.
12541  * @param[in, out] flow
12542  *   Pointer to flow structure.
12543  */
12544 static void
12545 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12546 {
12547         struct mlx5_flow_handle *dh;
12548         uint32_t handle_idx;
12549         struct mlx5_priv *priv = dev->data->dev_private;
12550
12551         if (!flow)
12552                 return;
12553         handle_idx = flow->dev_handles;
12554         while (handle_idx) {
12555                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12556                                     handle_idx);
12557                 if (!dh)
12558                         return;
12559                 if (dh->drv_flow) {
12560                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12561                         dh->drv_flow = NULL;
12562                 }
12563                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12564                         flow_dv_fate_resource_release(dev, dh);
12565                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12566                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12567                 handle_idx = dh->next.next;
12568         }
12569 }
12570
12571 /**
12572  * Remove the flow from the NIC and the memory.
12573  * Lock free, (mutex should be acquired by caller).
12574  *
12575  * @param[in] dev
12576  *   Pointer to the Ethernet device structure.
12577  * @param[in, out] flow
12578  *   Pointer to flow structure.
12579  */
12580 static void
12581 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12582 {
12583         struct mlx5_flow_handle *dev_handle;
12584         struct mlx5_priv *priv = dev->data->dev_private;
12585         struct mlx5_flow_meter *fm = NULL;
12586         uint32_t srss = 0;
12587
12588         if (!flow)
12589                 return;
12590         flow_dv_remove(dev, flow);
12591         if (flow->counter) {
12592                 flow_dv_counter_free(dev, flow->counter);
12593                 flow->counter = 0;
12594         }
12595         if (flow->meter) {
12596                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12597                                     flow->meter);
12598                 if (fm)
12599                         mlx5_flow_meter_detach(fm);
12600                 flow->meter = 0;
12601         }
12602         if (flow->age)
12603                 flow_dv_aso_age_release(dev, flow->age);
12604         if (flow->geneve_tlv_option) {
12605                 flow_dv_geneve_tlv_option_resource_release(dev);
12606                 flow->geneve_tlv_option = 0;
12607         }
12608         while (flow->dev_handles) {
12609                 uint32_t tmp_idx = flow->dev_handles;
12610
12611                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12612                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12613                 if (!dev_handle)
12614                         return;
12615                 flow->dev_handles = dev_handle->next.next;
12616                 if (dev_handle->dvh.matcher)
12617                         flow_dv_matcher_release(dev, dev_handle);
12618                 if (dev_handle->dvh.rix_sample)
12619                         flow_dv_sample_resource_release(dev, dev_handle);
12620                 if (dev_handle->dvh.rix_dest_array)
12621                         flow_dv_dest_array_resource_release(dev, dev_handle);
12622                 if (dev_handle->dvh.rix_encap_decap)
12623                         flow_dv_encap_decap_resource_release(dev,
12624                                 dev_handle->dvh.rix_encap_decap);
12625                 if (dev_handle->dvh.modify_hdr)
12626                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12627                 if (dev_handle->dvh.rix_push_vlan)
12628                         flow_dv_push_vlan_action_resource_release(dev,
12629                                                                   dev_handle);
12630                 if (dev_handle->dvh.rix_tag)
12631                         flow_dv_tag_release(dev,
12632                                             dev_handle->dvh.rix_tag);
12633                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12634                         flow_dv_fate_resource_release(dev, dev_handle);
12635                 else if (!srss)
12636                         srss = dev_handle->rix_srss;
12637                 if (fm && dev_handle->is_meter_flow_id &&
12638                     dev_handle->split_flow_id)
12639                         mlx5_ipool_free(fm->flow_ipool,
12640                                         dev_handle->split_flow_id);
12641                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12642                            tmp_idx);
12643         }
12644         if (srss)
12645                 flow_dv_shared_rss_action_release(dev, srss);
12646 }
12647
12648 /**
12649  * Release array of hash RX queue objects.
12650  * Helper function.
12651  *
12652  * @param[in] dev
12653  *   Pointer to the Ethernet device structure.
12654  * @param[in, out] hrxqs
12655  *   Array of hash RX queue objects.
12656  *
12657  * @return
12658  *   Total number of references to hash RX queue objects in *hrxqs* array
12659  *   after this operation.
12660  */
12661 static int
12662 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12663                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12664 {
12665         size_t i;
12666         int remaining = 0;
12667
12668         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12669                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12670
12671                 if (!ret)
12672                         (*hrxqs)[i] = 0;
12673                 remaining += ret;
12674         }
12675         return remaining;
12676 }
12677
12678 /**
12679  * Release all hash RX queue objects representing shared RSS action.
12680  *
12681  * @param[in] dev
12682  *   Pointer to the Ethernet device structure.
12683  * @param[in, out] action
12684  *   Shared RSS action to remove hash RX queue objects from.
12685  *
12686  * @return
12687  *   Total number of references to hash RX queue objects stored in *action*
12688  *   after this operation.
12689  *   Expected to be 0 if no external references held.
12690  */
12691 static int
12692 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12693                                  struct mlx5_shared_action_rss *shared_rss)
12694 {
12695         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12696 }
12697
12698 /**
12699  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12700  * user input.
12701  *
12702  * Only one hash value is available for one L3+L4 combination:
12703  * for example:
12704  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12705  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12706  * same slot in mlx5_rss_hash_fields.
12707  *
12708  * @param[in] rss
12709  *   Pointer to the shared action RSS conf.
12710  * @param[in, out] hash_field
12711  *   hash_field variable needed to be adjusted.
12712  *
12713  * @return
12714  *   void
12715  */
12716 static void
12717 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12718                                      uint64_t *hash_field)
12719 {
12720         uint64_t rss_types = rss->origin.types;
12721
12722         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12723         case MLX5_RSS_HASH_IPV4:
12724                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12725                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12726                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12727                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12728                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12729                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12730                         else
12731                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12732                 }
12733                 return;
12734         case MLX5_RSS_HASH_IPV6:
12735                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12736                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12737                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12738                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12739                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12740                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12741                         else
12742                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12743                 }
12744                 return;
12745         case MLX5_RSS_HASH_IPV4_UDP:
12746                 /* fall-through. */
12747         case MLX5_RSS_HASH_IPV6_UDP:
12748                 if (rss_types & ETH_RSS_UDP) {
12749                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12750                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12751                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12752                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12753                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12754                         else
12755                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12756                 }
12757                 return;
12758         case MLX5_RSS_HASH_IPV4_TCP:
12759                 /* fall-through. */
12760         case MLX5_RSS_HASH_IPV6_TCP:
12761                 if (rss_types & ETH_RSS_TCP) {
12762                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12763                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12764                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12765                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12766                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12767                         else
12768                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12769                 }
12770                 return;
12771         default:
12772                 return;
12773         }
12774 }
12775
12776 /**
12777  * Setup shared RSS action.
12778  * Prepare set of hash RX queue objects sufficient to handle all valid
12779  * hash_fields combinations (see enum ibv_rx_hash_fields).
12780  *
12781  * @param[in] dev
12782  *   Pointer to the Ethernet device structure.
12783  * @param[in] action_idx
12784  *   Shared RSS action ipool index.
12785  * @param[in, out] action
12786  *   Partially initialized shared RSS action.
12787  * @param[out] error
12788  *   Perform verbose error reporting if not NULL. Initialized in case of
12789  *   error only.
12790  *
12791  * @return
12792  *   0 on success, otherwise negative errno value.
12793  */
12794 static int
12795 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12796                            uint32_t action_idx,
12797                            struct mlx5_shared_action_rss *shared_rss,
12798                            struct rte_flow_error *error)
12799 {
12800         struct mlx5_flow_rss_desc rss_desc = { 0 };
12801         size_t i;
12802         int err;
12803
12804         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12805                 return rte_flow_error_set(error, rte_errno,
12806                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12807                                           "cannot setup indirection table");
12808         }
12809         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12810         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12811         rss_desc.const_q = shared_rss->origin.queue;
12812         rss_desc.queue_num = shared_rss->origin.queue_num;
12813         /* Set non-zero value to indicate a shared RSS. */
12814         rss_desc.shared_rss = action_idx;
12815         rss_desc.ind_tbl = shared_rss->ind_tbl;
12816         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12817                 uint32_t hrxq_idx;
12818                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12819                 int tunnel = 0;
12820
12821                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12822                 if (shared_rss->origin.level > 1) {
12823                         hash_fields |= IBV_RX_HASH_INNER;
12824                         tunnel = 1;
12825                 }
12826                 rss_desc.tunnel = tunnel;
12827                 rss_desc.hash_fields = hash_fields;
12828                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12829                 if (!hrxq_idx) {
12830                         rte_flow_error_set
12831                                 (error, rte_errno,
12832                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12833                                  "cannot get hash queue");
12834                         goto error_hrxq_new;
12835                 }
12836                 err = __flow_dv_action_rss_hrxq_set
12837                         (shared_rss, hash_fields, hrxq_idx);
12838                 MLX5_ASSERT(!err);
12839         }
12840         return 0;
12841 error_hrxq_new:
12842         err = rte_errno;
12843         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12844         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12845                 shared_rss->ind_tbl = NULL;
12846         rte_errno = err;
12847         return -rte_errno;
12848 }
12849
12850 /**
12851  * Create shared RSS action.
12852  *
12853  * @param[in] dev
12854  *   Pointer to the Ethernet device structure.
12855  * @param[in] conf
12856  *   Shared action configuration.
12857  * @param[in] rss
12858  *   RSS action specification used to create shared action.
12859  * @param[out] error
12860  *   Perform verbose error reporting if not NULL. Initialized in case of
12861  *   error only.
12862  *
12863  * @return
12864  *   A valid shared action ID in case of success, 0 otherwise and
12865  *   rte_errno is set.
12866  */
12867 static uint32_t
12868 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12869                             const struct rte_flow_indir_action_conf *conf,
12870                             const struct rte_flow_action_rss *rss,
12871                             struct rte_flow_error *error)
12872 {
12873         struct mlx5_priv *priv = dev->data->dev_private;
12874         struct mlx5_shared_action_rss *shared_rss = NULL;
12875         void *queue = NULL;
12876         struct rte_flow_action_rss *origin;
12877         const uint8_t *rss_key;
12878         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12879         uint32_t idx;
12880
12881         RTE_SET_USED(conf);
12882         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12883                             0, SOCKET_ID_ANY);
12884         shared_rss = mlx5_ipool_zmalloc
12885                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12886         if (!shared_rss || !queue) {
12887                 rte_flow_error_set(error, ENOMEM,
12888                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12889                                    "cannot allocate resource memory");
12890                 goto error_rss_init;
12891         }
12892         if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
12893                 rte_flow_error_set(error, E2BIG,
12894                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12895                                    "rss action number out of range");
12896                 goto error_rss_init;
12897         }
12898         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12899                                           sizeof(*shared_rss->ind_tbl),
12900                                           0, SOCKET_ID_ANY);
12901         if (!shared_rss->ind_tbl) {
12902                 rte_flow_error_set(error, ENOMEM,
12903                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12904                                    "cannot allocate resource memory");
12905                 goto error_rss_init;
12906         }
12907         memcpy(queue, rss->queue, queue_size);
12908         shared_rss->ind_tbl->queues = queue;
12909         shared_rss->ind_tbl->queues_n = rss->queue_num;
12910         origin = &shared_rss->origin;
12911         origin->func = rss->func;
12912         origin->level = rss->level;
12913         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12914         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12915         /* NULL RSS key indicates default RSS key. */
12916         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12917         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12918         origin->key = &shared_rss->key[0];
12919         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12920         origin->queue = queue;
12921         origin->queue_num = rss->queue_num;
12922         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12923                 goto error_rss_init;
12924         rte_spinlock_init(&shared_rss->action_rss_sl);
12925         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12926         rte_spinlock_lock(&priv->shared_act_sl);
12927         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12928                      &priv->rss_shared_actions, idx, shared_rss, next);
12929         rte_spinlock_unlock(&priv->shared_act_sl);
12930         return idx;
12931 error_rss_init:
12932         if (shared_rss) {
12933                 if (shared_rss->ind_tbl)
12934                         mlx5_free(shared_rss->ind_tbl);
12935                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12936                                 idx);
12937         }
12938         if (queue)
12939                 mlx5_free(queue);
12940         return 0;
12941 }
12942
12943 /**
12944  * Destroy the shared RSS action.
12945  * Release related hash RX queue objects.
12946  *
12947  * @param[in] dev
12948  *   Pointer to the Ethernet device structure.
12949  * @param[in] idx
12950  *   The shared RSS action object ID to be removed.
12951  * @param[out] error
12952  *   Perform verbose error reporting if not NULL. Initialized in case of
12953  *   error only.
12954  *
12955  * @return
12956  *   0 on success, otherwise negative errno value.
12957  */
12958 static int
12959 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12960                              struct rte_flow_error *error)
12961 {
12962         struct mlx5_priv *priv = dev->data->dev_private;
12963         struct mlx5_shared_action_rss *shared_rss =
12964             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12965         uint32_t old_refcnt = 1;
12966         int remaining;
12967         uint16_t *queue = NULL;
12968
12969         if (!shared_rss)
12970                 return rte_flow_error_set(error, EINVAL,
12971                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12972                                           "invalid shared action");
12973         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12974         if (remaining)
12975                 return rte_flow_error_set(error, EBUSY,
12976                                           RTE_FLOW_ERROR_TYPE_ACTION,
12977                                           NULL,
12978                                           "shared rss hrxq has references");
12979         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12980                                          0, 0, __ATOMIC_ACQUIRE,
12981                                          __ATOMIC_RELAXED))
12982                 return rte_flow_error_set(error, EBUSY,
12983                                           RTE_FLOW_ERROR_TYPE_ACTION,
12984                                           NULL,
12985                                           "shared rss has references");
12986         queue = shared_rss->ind_tbl->queues;
12987         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12988         if (remaining)
12989                 return rte_flow_error_set(error, EBUSY,
12990                                           RTE_FLOW_ERROR_TYPE_ACTION,
12991                                           NULL,
12992                                           "shared rss indirection table has"
12993                                           " references");
12994         mlx5_free(queue);
12995         rte_spinlock_lock(&priv->shared_act_sl);
12996         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12997                      &priv->rss_shared_actions, idx, shared_rss, next);
12998         rte_spinlock_unlock(&priv->shared_act_sl);
12999         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13000                         idx);
13001         return 0;
13002 }
13003
13004 /**
13005  * Create indirect action, lock free,
13006  * (mutex should be acquired by caller).
13007  * Dispatcher for action type specific call.
13008  *
13009  * @param[in] dev
13010  *   Pointer to the Ethernet device structure.
13011  * @param[in] conf
13012  *   Shared action configuration.
13013  * @param[in] action
13014  *   Action specification used to create indirect action.
13015  * @param[out] error
13016  *   Perform verbose error reporting if not NULL. Initialized in case of
13017  *   error only.
13018  *
13019  * @return
13020  *   A valid shared action handle in case of success, NULL otherwise and
13021  *   rte_errno is set.
13022  */
13023 static struct rte_flow_action_handle *
13024 flow_dv_action_create(struct rte_eth_dev *dev,
13025                       const struct rte_flow_indir_action_conf *conf,
13026                       const struct rte_flow_action *action,
13027                       struct rte_flow_error *err)
13028 {
13029         uint32_t idx = 0;
13030         uint32_t ret = 0;
13031
13032         switch (action->type) {
13033         case RTE_FLOW_ACTION_TYPE_RSS:
13034                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13035                 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13036                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13037                 break;
13038         case RTE_FLOW_ACTION_TYPE_AGE:
13039                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13040                 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13041                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13042                 if (ret) {
13043                         struct mlx5_aso_age_action *aso_age =
13044                                               flow_aso_age_get_by_idx(dev, ret);
13045
13046                         if (!aso_age->age_params.context)
13047                                 aso_age->age_params.context =
13048                                                          (void *)(uintptr_t)idx;
13049                 }
13050                 break;
13051         default:
13052                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13053                                    NULL, "action type not supported");
13054                 break;
13055         }
13056         return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13057 }
13058
13059 /**
13060  * Destroy the indirect action.
13061  * Release action related resources on the NIC and the memory.
13062  * Lock free, (mutex should be acquired by caller).
13063  * Dispatcher for action type specific call.
13064  *
13065  * @param[in] dev
13066  *   Pointer to the Ethernet device structure.
13067  * @param[in] handle
13068  *   The indirect action object handle to be removed.
13069  * @param[out] error
13070  *   Perform verbose error reporting if not NULL. Initialized in case of
13071  *   error only.
13072  *
13073  * @return
13074  *   0 on success, otherwise negative errno value.
13075  */
13076 static int
13077 flow_dv_action_destroy(struct rte_eth_dev *dev,
13078                        struct rte_flow_action_handle *handle,
13079                        struct rte_flow_error *error)
13080 {
13081         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13082         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13083         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13084         int ret;
13085
13086         switch (type) {
13087         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13088                 return __flow_dv_action_rss_release(dev, idx, error);
13089         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13090                 ret = flow_dv_aso_age_release(dev, idx);
13091                 if (ret)
13092                         /*
13093                          * In this case, the last flow has a reference will
13094                          * actually release the age action.
13095                          */
13096                         DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13097                                 " released with references %d.", idx, ret);
13098                 return 0;
13099         default:
13100                 return rte_flow_error_set(error, ENOTSUP,
13101                                           RTE_FLOW_ERROR_TYPE_ACTION,
13102                                           NULL,
13103                                           "action type not supported");
13104         }
13105 }
13106
13107 /**
13108  * Updates in place shared RSS action configuration.
13109  *
13110  * @param[in] dev
13111  *   Pointer to the Ethernet device structure.
13112  * @param[in] idx
13113  *   The shared RSS action object ID to be updated.
13114  * @param[in] action_conf
13115  *   RSS action specification used to modify *shared_rss*.
13116  * @param[out] error
13117  *   Perform verbose error reporting if not NULL. Initialized in case of
13118  *   error only.
13119  *
13120  * @return
13121  *   0 on success, otherwise negative errno value.
13122  * @note: currently only support update of RSS queues.
13123  */
13124 static int
13125 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13126                             const struct rte_flow_action_rss *action_conf,
13127                             struct rte_flow_error *error)
13128 {
13129         struct mlx5_priv *priv = dev->data->dev_private;
13130         struct mlx5_shared_action_rss *shared_rss =
13131             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13132         int ret = 0;
13133         void *queue = NULL;
13134         uint16_t *queue_old = NULL;
13135         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13136
13137         if (!shared_rss)
13138                 return rte_flow_error_set(error, EINVAL,
13139                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13140                                           "invalid shared action to update");
13141         if (priv->obj_ops.ind_table_modify == NULL)
13142                 return rte_flow_error_set(error, ENOTSUP,
13143                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13144                                           "cannot modify indirection table");
13145         queue = mlx5_malloc(MLX5_MEM_ZERO,
13146                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13147                             0, SOCKET_ID_ANY);
13148         if (!queue)
13149                 return rte_flow_error_set(error, ENOMEM,
13150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13151                                           NULL,
13152                                           "cannot allocate resource memory");
13153         memcpy(queue, action_conf->queue, queue_size);
13154         MLX5_ASSERT(shared_rss->ind_tbl);
13155         rte_spinlock_lock(&shared_rss->action_rss_sl);
13156         queue_old = shared_rss->ind_tbl->queues;
13157         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13158                                         queue, action_conf->queue_num, true);
13159         if (ret) {
13160                 mlx5_free(queue);
13161                 ret = rte_flow_error_set(error, rte_errno,
13162                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13163                                           "cannot update indirection table");
13164         } else {
13165                 mlx5_free(queue_old);
13166                 shared_rss->origin.queue = queue;
13167                 shared_rss->origin.queue_num = action_conf->queue_num;
13168         }
13169         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13170         return ret;
13171 }
13172
13173 /**
13174  * Updates in place shared action configuration, lock free,
13175  * (mutex should be acquired by caller).
13176  *
13177  * @param[in] dev
13178  *   Pointer to the Ethernet device structure.
13179  * @param[in] handle
13180  *   The indirect action object handle to be updated.
13181  * @param[in] update
13182  *   Action specification used to modify the action pointed by *handle*.
13183  *   *update* could be of same type with the action pointed by the *handle*
13184  *   handle argument, or some other structures like a wrapper, depending on
13185  *   the indirect action type.
13186  * @param[out] error
13187  *   Perform verbose error reporting if not NULL. Initialized in case of
13188  *   error only.
13189  *
13190  * @return
13191  *   0 on success, otherwise negative errno value.
13192  */
13193 static int
13194 flow_dv_action_update(struct rte_eth_dev *dev,
13195                         struct rte_flow_action_handle *handle,
13196                         const void *update,
13197                         struct rte_flow_error *err)
13198 {
13199         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13200         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13201         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13202         const void *action_conf;
13203
13204         switch (type) {
13205         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13206                 action_conf = ((const struct rte_flow_action *)update)->conf;
13207                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13208         default:
13209                 return rte_flow_error_set(err, ENOTSUP,
13210                                           RTE_FLOW_ERROR_TYPE_ACTION,
13211                                           NULL,
13212                                           "action type update not supported");
13213         }
13214 }
13215
13216 static int
13217 flow_dv_action_query(struct rte_eth_dev *dev,
13218                      const struct rte_flow_action_handle *handle, void *data,
13219                      struct rte_flow_error *error)
13220 {
13221         struct mlx5_age_param *age_param;
13222         struct rte_flow_query_age *resp;
13223         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13224         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13225         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13226
13227         switch (type) {
13228         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13229                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13230                 resp = data;
13231                 resp->aged = __atomic_load_n(&age_param->state,
13232                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13233                                                                           1 : 0;
13234                 resp->sec_since_last_hit_valid = !resp->aged;
13235                 if (resp->sec_since_last_hit_valid)
13236                         resp->sec_since_last_hit = __atomic_load_n
13237                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13238                 return 0;
13239         default:
13240                 return rte_flow_error_set(error, ENOTSUP,
13241                                           RTE_FLOW_ERROR_TYPE_ACTION,
13242                                           NULL,
13243                                           "action type query not supported");
13244         }
13245 }
13246
13247 /**
13248  * Query a dv flow  rule for its statistics via devx.
13249  *
13250  * @param[in] dev
13251  *   Pointer to Ethernet device.
13252  * @param[in] flow
13253  *   Pointer to the sub flow.
13254  * @param[out] data
13255  *   data retrieved by the query.
13256  * @param[out] error
13257  *   Perform verbose error reporting if not NULL.
13258  *
13259  * @return
13260  *   0 on success, a negative errno value otherwise and rte_errno is set.
13261  */
13262 static int
13263 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13264                     void *data, struct rte_flow_error *error)
13265 {
13266         struct mlx5_priv *priv = dev->data->dev_private;
13267         struct rte_flow_query_count *qc = data;
13268
13269         if (!priv->config.devx)
13270                 return rte_flow_error_set(error, ENOTSUP,
13271                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13272                                           NULL,
13273                                           "counters are not supported");
13274         if (flow->counter) {
13275                 uint64_t pkts, bytes;
13276                 struct mlx5_flow_counter *cnt;
13277
13278                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13279                                                  NULL);
13280                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13281                                                &bytes);
13282
13283                 if (err)
13284                         return rte_flow_error_set(error, -err,
13285                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13286                                         NULL, "cannot read counters");
13287                 qc->hits_set = 1;
13288                 qc->bytes_set = 1;
13289                 qc->hits = pkts - cnt->hits;
13290                 qc->bytes = bytes - cnt->bytes;
13291                 if (qc->reset) {
13292                         cnt->hits = pkts;
13293                         cnt->bytes = bytes;
13294                 }
13295                 return 0;
13296         }
13297         return rte_flow_error_set(error, EINVAL,
13298                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13299                                   NULL,
13300                                   "counters are not available");
13301 }
13302
13303 /**
13304  * Query a flow rule AGE action for aging information.
13305  *
13306  * @param[in] dev
13307  *   Pointer to Ethernet device.
13308  * @param[in] flow
13309  *   Pointer to the sub flow.
13310  * @param[out] data
13311  *   data retrieved by the query.
13312  * @param[out] error
13313  *   Perform verbose error reporting if not NULL.
13314  *
13315  * @return
13316  *   0 on success, a negative errno value otherwise and rte_errno is set.
13317  */
13318 static int
13319 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13320                   void *data, struct rte_flow_error *error)
13321 {
13322         struct rte_flow_query_age *resp = data;
13323         struct mlx5_age_param *age_param;
13324
13325         if (flow->age) {
13326                 struct mlx5_aso_age_action *act =
13327                                      flow_aso_age_get_by_idx(dev, flow->age);
13328
13329                 age_param = &act->age_params;
13330         } else if (flow->counter) {
13331                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13332
13333                 if (!age_param || !age_param->timeout)
13334                         return rte_flow_error_set
13335                                         (error, EINVAL,
13336                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13337                                          NULL, "cannot read age data");
13338         } else {
13339                 return rte_flow_error_set(error, EINVAL,
13340                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13341                                           NULL, "age data not available");
13342         }
13343         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13344                                      AGE_TMOUT ? 1 : 0;
13345         resp->sec_since_last_hit_valid = !resp->aged;
13346         if (resp->sec_since_last_hit_valid)
13347                 resp->sec_since_last_hit = __atomic_load_n
13348                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13349         return 0;
13350 }
13351
13352 /**
13353  * Query a flow.
13354  *
13355  * @see rte_flow_query()
13356  * @see rte_flow_ops
13357  */
13358 static int
13359 flow_dv_query(struct rte_eth_dev *dev,
13360               struct rte_flow *flow __rte_unused,
13361               const struct rte_flow_action *actions __rte_unused,
13362               void *data __rte_unused,
13363               struct rte_flow_error *error __rte_unused)
13364 {
13365         int ret = -EINVAL;
13366
13367         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13368                 switch (actions->type) {
13369                 case RTE_FLOW_ACTION_TYPE_VOID:
13370                         break;
13371                 case RTE_FLOW_ACTION_TYPE_COUNT:
13372                         ret = flow_dv_query_count(dev, flow, data, error);
13373                         break;
13374                 case RTE_FLOW_ACTION_TYPE_AGE:
13375                         ret = flow_dv_query_age(dev, flow, data, error);
13376                         break;
13377                 default:
13378                         return rte_flow_error_set(error, ENOTSUP,
13379                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13380                                                   actions,
13381                                                   "action not supported");
13382                 }
13383         }
13384         return ret;
13385 }
13386
13387 /**
13388  * Destroy the meter table set.
13389  * Lock free, (mutex should be acquired by caller).
13390  *
13391  * @param[in] dev
13392  *   Pointer to Ethernet device.
13393  * @param[in] tbl
13394  *   Pointer to the meter table set.
13395  *
13396  * @return
13397  *   Always 0.
13398  */
13399 static int
13400 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13401                         struct mlx5_meter_domains_infos *tbl)
13402 {
13403         struct mlx5_priv *priv = dev->data->dev_private;
13404         struct mlx5_meter_domains_infos *mtd =
13405                                 (struct mlx5_meter_domains_infos *)tbl;
13406
13407         if (!mtd || !priv->config.dv_flow_en)
13408                 return 0;
13409         if (mtd->egress.tbl)
13410                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13411         if (mtd->egress.sfx_tbl)
13412                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13413         if (mtd->ingress.tbl)
13414                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13415         if (mtd->ingress.sfx_tbl)
13416                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13417                                              mtd->ingress.sfx_tbl);
13418         if (mtd->transfer.tbl)
13419                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13420         if (mtd->transfer.sfx_tbl)
13421                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13422                                              mtd->transfer.sfx_tbl);
13423         mlx5_free(mtd);
13424         return 0;
13425 }
13426
13427 /* Number of meter flow actions, count and jump or count and drop. */
13428 #define METER_ACTIONS 2
13429
13430 /**
13431  * Create specify domain meter table and suffix table.
13432  *
13433  * @param[in] dev
13434  *   Pointer to Ethernet device.
13435  * @param[in,out] mtb
13436  *   Pointer to DV meter table set.
13437  * @param[in] egress
13438  *   Table attribute.
13439  * @param[in] transfer
13440  *   Table attribute.
13441  *
13442  * @return
13443  *   0 on success, -1 otherwise.
13444  */
13445 static int
13446 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13447                            struct mlx5_meter_domains_infos *mtb,
13448                            uint8_t egress, uint8_t transfer)
13449 {
13450         struct rte_flow_error error;
13451         struct mlx5_meter_domain_info *dtb;
13452
13453         if (transfer)
13454                 dtb = &mtb->transfer;
13455         else if (egress)
13456                 dtb = &mtb->egress;
13457         else
13458                 dtb = &mtb->ingress;
13459         /* Create the meter table with METER level. */
13460         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13461                                             egress, transfer, false, NULL, 0,
13462                                             0, &error);
13463         if (!dtb->tbl) {
13464                 DRV_LOG(ERR, "Failed to create meter policer table.");
13465                 return -1;
13466         }
13467         /* Create the meter suffix table with SUFFIX level. */
13468         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13469                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13470                                             egress, transfer, false, NULL, 0,
13471                                             0, &error);
13472         if (!dtb->sfx_tbl) {
13473                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13474                 return -1;
13475         }
13476         return 0;
13477 }
13478
13479 /**
13480  * Create the needed meter and suffix tables.
13481  * Lock free, (mutex should be acquired by caller).
13482  *
13483  * @param[in] dev
13484  *   Pointer to Ethernet device.
13485  *
13486  * @return
13487  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13488  */
13489 static struct mlx5_meter_domains_infos *
13490 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13491 {
13492         struct mlx5_priv *priv = dev->data->dev_private;
13493         struct mlx5_meter_domains_infos *mtb;
13494         int ret;
13495
13496         if (!priv->mtr_en) {
13497                 rte_errno = ENOTSUP;
13498                 return NULL;
13499         }
13500         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13501         if (!mtb) {
13502                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13503                 return NULL;
13504         }
13505         /* Egress meter table. */
13506         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13507         if (ret) {
13508                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13509                 goto error_exit;
13510         }
13511         /* Ingress meter table. */
13512         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13513         if (ret) {
13514                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13515                 goto error_exit;
13516         }
13517         /* FDB meter table. */
13518         if (priv->config.dv_esw_en) {
13519                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13520                 if (ret) {
13521                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13522                         goto error_exit;
13523                 }
13524         }
13525         return mtb;
13526 error_exit:
13527         flow_dv_destroy_mtr_tbl(dev, mtb);
13528         return NULL;
13529 }
13530
13531 /**
13532  * Destroy the meter table matchers.
13533  * Lock free, (mutex should be acquired by caller).
13534  *
13535  * @param[in] dev
13536  *   Pointer to Ethernet device.
13537  * @param[in,out] dtb
13538  *   Pointer to DV meter table.
13539  *
13540  * @return
13541  *   Always 0.
13542  */
13543 static int
13544 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13545                              struct mlx5_meter_domain_info *dtb)
13546 {
13547         struct mlx5_priv *priv = dev->data->dev_private;
13548         struct mlx5_flow_tbl_data_entry *tbl;
13549
13550         if (!priv->config.dv_flow_en)
13551                 return 0;
13552         if (dtb->drop_matcher) {
13553                 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13554                 mlx5_cache_unregister(&tbl->matchers,
13555                                       &dtb->drop_matcher->entry);
13556                 dtb->drop_matcher = NULL;
13557         }
13558         if (dtb->color_matcher) {
13559                 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13560                 mlx5_cache_unregister(&tbl->matchers,
13561                                       &dtb->color_matcher->entry);
13562                 dtb->color_matcher = NULL;
13563         }
13564         return 0;
13565 }
13566
13567 /**
13568  * Create the matchers for meter table.
13569  *
13570  * @param[in] dev
13571  *   Pointer to Ethernet device.
13572  * @param[in] color_reg_c_idx
13573  *   Reg C index for color match.
13574  * @param[in] mtr_id_reg_c_idx
13575  *   Reg C index for meter_id match.
13576  * @param[in] mtr_id_mask
13577  *   Mask for meter_id match criteria.
13578  * @param[in,out] dtb
13579  *   Pointer to DV meter table.
13580  * @param[out] error
13581  *   Perform verbose error reporting if not NULL.
13582  *
13583  * @return
13584  *   0 on success, a negative errno value otherwise and rte_errno is set.
13585  */
13586 static int
13587 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13588                              uint32_t color_reg_c_idx,
13589                              uint32_t mtr_id_reg_c_idx,
13590                              uint32_t mtr_id_mask,
13591                              struct mlx5_meter_domain_info *dtb,
13592                              struct rte_flow_error *error)
13593 {
13594         struct mlx5_priv *priv = dev->data->dev_private;
13595         struct mlx5_flow_tbl_data_entry *tbl_data;
13596         struct mlx5_cache_entry *entry;
13597         struct mlx5_flow_dv_matcher matcher = {
13598                 .mask = {
13599                         .size = sizeof(matcher.mask.buf) -
13600                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13601                 },
13602                 .tbl = dtb->tbl,
13603         };
13604         struct mlx5_flow_dv_match_params value = {
13605                 .size = sizeof(value.buf) -
13606                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13607         };
13608         struct mlx5_flow_cb_ctx ctx = {
13609                 .error = error,
13610                 .data = &matcher,
13611         };
13612         uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13613
13614         tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13615         if (!dtb->drop_matcher) {
13616                 /* Create matchers for Drop. */
13617                 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13618                                        mtr_id_reg_c_idx, 0, mtr_id_mask);
13619                 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13620                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13621                                         matcher.mask.size);
13622                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13623                 if (!entry) {
13624                         DRV_LOG(ERR, "Failed to register meter drop matcher.");
13625                         return -1;
13626                 }
13627                 dtb->drop_matcher =
13628                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13629         }
13630         if (!dtb->color_matcher) {
13631                 /* Create matchers for Color + meter_id. */
13632                 if (priv->mtr_reg_share) {
13633                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13634                                         color_reg_c_idx, 0,
13635                                         (mtr_id_mask | color_mask));
13636                 } else {
13637                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13638                                         color_reg_c_idx, 0, color_mask);
13639                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13640                                         mtr_id_reg_c_idx, 0, mtr_id_mask);
13641                 }
13642                 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13643                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13644                                         matcher.mask.size);
13645                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13646                 if (!entry) {
13647                         DRV_LOG(ERR, "Failed to register meter color matcher.");
13648                         return -1;
13649                 }
13650                 dtb->color_matcher =
13651                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13652         }
13653         return 0;
13654 }
13655
13656 /**
13657  * Destroy domain policer rule.
13658  *
13659  * @param[in] dev
13660  *   Pointer to Ethernet device.
13661  * @param[in] dt
13662  *   Pointer to domain table.
13663  */
13664 static void
13665 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13666                                     struct mlx5_meter_domain_info *dt)
13667 {
13668         if (dt->drop_rule) {
13669                 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13670                 dt->drop_rule = NULL;
13671         }
13672         if (dt->green_rule) {
13673                 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13674                 dt->green_rule = NULL;
13675         }
13676         flow_dv_destroy_mtr_matchers(dev, dt);
13677         if (dt->jump_actn) {
13678                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13679                 dt->jump_actn = NULL;
13680         }
13681 }
13682
13683 /**
13684  * Destroy policer rules.
13685  *
13686  * @param[in] dev
13687  *   Pointer to Ethernet device.
13688  * @param[in] fm
13689  *   Pointer to flow meter structure.
13690  * @param[in] attr
13691  *   Pointer to flow attributes.
13692  *
13693  * @return
13694  *   Always 0.
13695  */
13696 static int
13697 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13698                               const struct mlx5_flow_meter *fm,
13699                               const struct rte_flow_attr *attr)
13700 {
13701         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13702
13703         if (!mtb)
13704                 return 0;
13705         if (attr->egress)
13706                 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13707         if (attr->ingress)
13708                 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13709         if (attr->transfer)
13710                 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13711         return 0;
13712 }
13713
13714 /**
13715  * Create specify domain meter policer rule.
13716  *
13717  * @param[in] dev
13718  *   Pointer to Ethernet device.
13719  * @param[in] fm
13720  *   Pointer to flow meter structure.
13721  * @param[in] mtb
13722  *   Pointer to DV meter table set.
13723  * @param[out] drop_rule
13724  *   The address of pointer saving drop rule.
13725  * @param[out] color_rule
13726  *   The address of pointer saving green rule.
13727  *
13728  * @return
13729  *   0 on success, -1 otherwise.
13730  */
13731 static int
13732 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13733                                     struct mlx5_flow_meter *fm,
13734                                     struct mlx5_meter_domain_info *dtb,
13735                                     void **drop_rule,
13736                                     void **green_rule)
13737 {
13738         struct mlx5_priv *priv = dev->data->dev_private;
13739         struct mlx5_flow_dv_match_params matcher = {
13740                 .size = sizeof(matcher.buf) -
13741                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13742         };
13743         struct mlx5_flow_dv_match_params value = {
13744                 .size = sizeof(value.buf) -
13745                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13746         };
13747         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13748         struct rte_flow_error error;
13749         uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13750                                                     0, &error);
13751         uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13752                                                      0, &error);
13753         uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13754         uint32_t mtr_id_mask =
13755                 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13756         void *actions[METER_ACTIONS];
13757         int i;
13758         int ret = 0;
13759
13760         /* Create jump action. */
13761         if (!dtb->jump_actn)
13762                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13763                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13764         if (ret) {
13765                 DRV_LOG(ERR, "Failed to create policer jump action.");
13766                 goto error;
13767         }
13768         /* Prepare matchers. */
13769         if (!dtb->drop_matcher || !dtb->color_matcher) {
13770                 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13771                                                    mtr_id_reg_c, mtr_id_mask,
13772                                                    dtb, &error);
13773                 if (ret) {
13774                         DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13775                         goto error;
13776                 }
13777         }
13778         /* Create Drop flow, matching meter_id only. */
13779         i = 0;
13780         flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13781                                (fm->idx << mtr_id_offset), UINT32_MAX);
13782         if (mtb->drop_count)
13783                 actions[i++] = mtb->drop_count;
13784         actions[i++] = priv->sh->dr_drop_action;
13785         ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13786                                        (void *)&value, i, actions, drop_rule);
13787         if (ret) {
13788                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13789                 goto error;
13790         }
13791         /* Create flow matching Green color + meter_id. */
13792         i = 0;
13793         if (priv->mtr_reg_share) {
13794                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13795                                        ((fm->idx << mtr_id_offset) |
13796                                         rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13797                                        UINT32_MAX);
13798         } else {
13799                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13800                                        rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13801                                        UINT32_MAX);
13802                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13803                                        fm->idx, UINT32_MAX);
13804         }
13805         if (mtb->green_count)
13806                 actions[i++] = mtb->green_count;
13807         actions[i++] = dtb->jump_actn;
13808         ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
13809                                        (void *)&value, i, actions, green_rule);
13810         if (ret) {
13811                 DRV_LOG(ERR, "Failed to create meter policer color rule.");
13812                 goto error;
13813         }
13814         return 0;
13815 error:
13816         rte_errno = errno;
13817         return -1;
13818 }
13819
13820 /**
13821  * Prepare policer rules for all domains.
13822  * If meter already initialized, this will replace all old rules with new ones.
13823  *
13824  * @param[in] dev
13825  *   Pointer to Ethernet device.
13826  * @param[in] fm
13827  *   Pointer to flow meter structure.
13828  * @param[in] attr
13829  *   Pointer to flow attributes.
13830  *
13831  * @return
13832  *   0 on success, -1 otherwise.
13833  */
13834 static int
13835 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
13836                               struct mlx5_flow_meter *fm,
13837                               const struct rte_flow_attr *attr)
13838 {
13839         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13840         bool initialized = false;
13841         struct mlx5_flow_counter *cnt;
13842         void *egress_drop_rule = NULL;
13843         void *egress_green_rule = NULL;
13844         void *ingress_drop_rule = NULL;
13845         void *ingress_green_rule = NULL;
13846         void *transfer_drop_rule = NULL;
13847         void *transfer_green_rule = NULL;
13848         int ret;
13849
13850         /* Get the statistics counters for green/drop. */
13851         if (fm->policer_stats.cnt[RTE_COLOR_GREEN]) {
13852                 cnt = flow_dv_counter_get_by_idx(dev,
13853                                         fm->policer_stats.cnt[RTE_COLOR_GREEN],
13854                                         NULL);
13855                 mtb->green_count = cnt->action;
13856         } else {
13857                 mtb->green_count = NULL;
13858         }
13859         if (fm->policer_stats.cnt[RTE_MTR_DROPPED]) {
13860                 cnt = flow_dv_counter_get_by_idx(dev,
13861                                         fm->policer_stats.cnt[RTE_MTR_DROPPED],
13862                                         NULL);
13863                 mtb->drop_count = cnt->action;
13864         } else {
13865                 mtb->drop_count = NULL;
13866         }
13867         /**
13868          * If flow meter has been initialized, all policer rules
13869          * are created. So can get if meter initialized by checking
13870          * any policer rule.
13871          */
13872         if (mtb->egress.drop_rule)
13873                 initialized = true;
13874         if (attr->egress) {
13875                 ret = flow_dv_create_policer_forward_rule(dev,
13876                                 fm, &mtb->egress,
13877                                 &egress_drop_rule, &egress_green_rule);
13878                 if (ret) {
13879                         DRV_LOG(ERR, "Failed to create egress policer.");
13880                         goto error;
13881                 }
13882         }
13883         if (attr->ingress) {
13884                 ret = flow_dv_create_policer_forward_rule(dev,
13885                                 fm, &mtb->ingress,
13886                                 &ingress_drop_rule, &ingress_green_rule);
13887                 if (ret) {
13888                         DRV_LOG(ERR, "Failed to create ingress policer.");
13889                         goto error;
13890                 }
13891         }
13892         if (attr->transfer) {
13893                 ret = flow_dv_create_policer_forward_rule(dev,
13894                                 fm, &mtb->transfer,
13895                                 &transfer_drop_rule, &transfer_green_rule);
13896                 if (ret) {
13897                         DRV_LOG(ERR, "Failed to create transfer policer.");
13898                         goto error;
13899                 }
13900         }
13901         /* Replace old flows if existing. */
13902         if (mtb->egress.drop_rule)
13903                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
13904         if (mtb->egress.green_rule)
13905                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
13906         if (mtb->ingress.drop_rule)
13907                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
13908         if (mtb->ingress.green_rule)
13909                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
13910         if (mtb->transfer.drop_rule)
13911                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
13912         if (mtb->transfer.green_rule)
13913                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
13914         mtb->egress.drop_rule = egress_drop_rule;
13915         mtb->egress.green_rule = egress_green_rule;
13916         mtb->ingress.drop_rule = ingress_drop_rule;
13917         mtb->ingress.green_rule = ingress_green_rule;
13918         mtb->transfer.drop_rule = transfer_drop_rule;
13919         mtb->transfer.green_rule = transfer_green_rule;
13920         return 0;
13921 error:
13922         if (egress_drop_rule)
13923                 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
13924         if (egress_green_rule)
13925                 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
13926         if (ingress_drop_rule)
13927                 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
13928         if (ingress_green_rule)
13929                 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
13930         if (transfer_drop_rule)
13931                 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
13932         if (transfer_green_rule)
13933                 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
13934         if (!initialized)
13935                 flow_dv_destroy_policer_rules(dev, fm, attr);
13936         return -1;
13937 }
13938
13939 /**
13940  * Validate the batch counter support in root table.
13941  *
13942  * Create a simple flow with invalid counter and drop action on root table to
13943  * validate if batch counter with offset on root table is supported or not.
13944  *
13945  * @param[in] dev
13946  *   Pointer to rte_eth_dev structure.
13947  *
13948  * @return
13949  *   0 on success, a negative errno value otherwise and rte_errno is set.
13950  */
13951 int
13952 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13953 {
13954         struct mlx5_priv *priv = dev->data->dev_private;
13955         struct mlx5_dev_ctx_shared *sh = priv->sh;
13956         struct mlx5_flow_dv_match_params mask = {
13957                 .size = sizeof(mask.buf),
13958         };
13959         struct mlx5_flow_dv_match_params value = {
13960                 .size = sizeof(value.buf),
13961         };
13962         struct mlx5dv_flow_matcher_attr dv_attr = {
13963                 .type = IBV_FLOW_ATTR_NORMAL,
13964                 .priority = 0,
13965                 .match_criteria_enable = 0,
13966                 .match_mask = (void *)&mask,
13967         };
13968         void *actions[2] = { 0 };
13969         struct mlx5_flow_tbl_resource *tbl = NULL;
13970         struct mlx5_devx_obj *dcs = NULL;
13971         void *matcher = NULL;
13972         void *flow = NULL;
13973         int ret = -1;
13974
13975         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13976         if (!tbl)
13977                 goto err;
13978         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13979         if (!dcs)
13980                 goto err;
13981         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13982                                                     &actions[0]);
13983         if (ret)
13984                 goto err;
13985         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13986                                           priv->drop_queue.hrxq->action;
13987         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13988         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13989                                                &matcher);
13990         if (ret)
13991                 goto err;
13992         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13993                                        actions, &flow);
13994 err:
13995         /*
13996          * If batch counter with offset is not supported, the driver will not
13997          * validate the invalid offset value, flow create should success.
13998          * In this case, it means batch counter is not supported in root table.
13999          *
14000          * Otherwise, if flow create is failed, counter offset is supported.
14001          */
14002         if (flow) {
14003                 DRV_LOG(INFO, "Batch counter is not supported in root "
14004                               "table. Switch to fallback mode.");
14005                 rte_errno = ENOTSUP;
14006                 ret = -rte_errno;
14007                 claim_zero(mlx5_flow_os_destroy_flow(flow));
14008         } else {
14009                 /* Check matcher to make sure validate fail at flow create. */
14010                 if (!matcher || (matcher && errno != EINVAL))
14011                         DRV_LOG(ERR, "Unexpected error in counter offset "
14012                                      "support detection");
14013                 ret = 0;
14014         }
14015         if (actions[0])
14016                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14017         if (matcher)
14018                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14019         if (tbl)
14020                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14021         if (dcs)
14022                 claim_zero(mlx5_devx_cmd_destroy(dcs));
14023         return ret;
14024 }
14025
14026 /**
14027  * Query a devx counter.
14028  *
14029  * @param[in] dev
14030  *   Pointer to the Ethernet device structure.
14031  * @param[in] cnt
14032  *   Index to the flow counter.
14033  * @param[in] clear
14034  *   Set to clear the counter statistics.
14035  * @param[out] pkts
14036  *   The statistics value of packets.
14037  * @param[out] bytes
14038  *   The statistics value of bytes.
14039  *
14040  * @return
14041  *   0 on success, otherwise return -1.
14042  */
14043 static int
14044 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14045                       uint64_t *pkts, uint64_t *bytes)
14046 {
14047         struct mlx5_priv *priv = dev->data->dev_private;
14048         struct mlx5_flow_counter *cnt;
14049         uint64_t inn_pkts, inn_bytes;
14050         int ret;
14051
14052         if (!priv->config.devx)
14053                 return -1;
14054
14055         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14056         if (ret)
14057                 return -1;
14058         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14059         *pkts = inn_pkts - cnt->hits;
14060         *bytes = inn_bytes - cnt->bytes;
14061         if (clear) {
14062                 cnt->hits = inn_pkts;
14063                 cnt->bytes = inn_bytes;
14064         }
14065         return 0;
14066 }
14067
14068 /**
14069  * Get aged-out flows.
14070  *
14071  * @param[in] dev
14072  *   Pointer to the Ethernet device structure.
14073  * @param[in] context
14074  *   The address of an array of pointers to the aged-out flows contexts.
14075  * @param[in] nb_contexts
14076  *   The length of context array pointers.
14077  * @param[out] error
14078  *   Perform verbose error reporting if not NULL. Initialized in case of
14079  *   error only.
14080  *
14081  * @return
14082  *   how many contexts get in success, otherwise negative errno value.
14083  *   if nb_contexts is 0, return the amount of all aged contexts.
14084  *   if nb_contexts is not 0 , return the amount of aged flows reported
14085  *   in the context array.
14086  * @note: only stub for now
14087  */
14088 static int
14089 flow_get_aged_flows(struct rte_eth_dev *dev,
14090                     void **context,
14091                     uint32_t nb_contexts,
14092                     struct rte_flow_error *error)
14093 {
14094         struct mlx5_priv *priv = dev->data->dev_private;
14095         struct mlx5_age_info *age_info;
14096         struct mlx5_age_param *age_param;
14097         struct mlx5_flow_counter *counter;
14098         struct mlx5_aso_age_action *act;
14099         int nb_flows = 0;
14100
14101         if (nb_contexts && !context)
14102                 return rte_flow_error_set(error, EINVAL,
14103                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14104                                           NULL, "empty context");
14105         age_info = GET_PORT_AGE_INFO(priv);
14106         rte_spinlock_lock(&age_info->aged_sl);
14107         LIST_FOREACH(act, &age_info->aged_aso, next) {
14108                 nb_flows++;
14109                 if (nb_contexts) {
14110                         context[nb_flows - 1] =
14111                                                 act->age_params.context;
14112                         if (!(--nb_contexts))
14113                                 break;
14114                 }
14115         }
14116         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14117                 nb_flows++;
14118                 if (nb_contexts) {
14119                         age_param = MLX5_CNT_TO_AGE(counter);
14120                         context[nb_flows - 1] = age_param->context;
14121                         if (!(--nb_contexts))
14122                                 break;
14123                 }
14124         }
14125         rte_spinlock_unlock(&age_info->aged_sl);
14126         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14127         return nb_flows;
14128 }
14129
14130 /*
14131  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14132  */
14133 static uint32_t
14134 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14135 {
14136         return flow_dv_counter_alloc(dev, 0);
14137 }
14138
14139 /**
14140  * Validate indirect action.
14141  * Dispatcher for action type specific validation.
14142  *
14143  * @param[in] dev
14144  *   Pointer to the Ethernet device structure.
14145  * @param[in] conf
14146  *   Shared action configuration.
14147  * @param[in] action
14148  *   The indirect action object to validate.
14149  * @param[out] error
14150  *   Perform verbose error reporting if not NULL. Initialized in case of
14151  *   error only.
14152  *
14153  * @return
14154  *   0 on success, otherwise negative errno value.
14155  */
14156 static int
14157 flow_dv_action_validate(struct rte_eth_dev *dev,
14158                         const struct rte_flow_indir_action_conf *conf,
14159                         const struct rte_flow_action *action,
14160                         struct rte_flow_error *err)
14161 {
14162         struct mlx5_priv *priv = dev->data->dev_private;
14163
14164         RTE_SET_USED(conf);
14165         switch (action->type) {
14166         case RTE_FLOW_ACTION_TYPE_RSS:
14167                 /*
14168                  * priv->obj_ops is set according to driver capabilities.
14169                  * When DevX capabilities are
14170                  * sufficient, it is set to devx_obj_ops.
14171                  * Otherwise, it is set to ibv_obj_ops.
14172                  * ibv_obj_ops doesn't support ind_table_modify operation.
14173                  * In this case the shared RSS action can't be used.
14174                  */
14175                 if (priv->obj_ops.ind_table_modify == NULL)
14176                         return rte_flow_error_set
14177                                         (err, ENOTSUP,
14178                                          RTE_FLOW_ERROR_TYPE_ACTION,
14179                                          NULL,
14180                                          "shared RSS action not supported");
14181                 return mlx5_validate_action_rss(dev, action, err);
14182         case RTE_FLOW_ACTION_TYPE_AGE:
14183                 if (!priv->sh->aso_age_mng)
14184                         return rte_flow_error_set(err, ENOTSUP,
14185                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14186                                                 NULL,
14187                                              "shared age action not supported");
14188                 return flow_dv_validate_action_age(0, action, dev, err);
14189         default:
14190                 return rte_flow_error_set(err, ENOTSUP,
14191                                           RTE_FLOW_ERROR_TYPE_ACTION,
14192                                           NULL,
14193                                           "action type not supported");
14194         }
14195 }
14196
14197 static int
14198 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14199 {
14200         struct mlx5_priv *priv = dev->data->dev_private;
14201         int ret = 0;
14202
14203         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14204                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14205                                                 flags);
14206                 if (ret != 0)
14207                         return ret;
14208         }
14209         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14210                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14211                 if (ret != 0)
14212                         return ret;
14213         }
14214         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14215                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14216                 if (ret != 0)
14217                         return ret;
14218         }
14219         return 0;
14220 }
14221
14222 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14223         .validate = flow_dv_validate,
14224         .prepare = flow_dv_prepare,
14225         .translate = flow_dv_translate,
14226         .apply = flow_dv_apply,
14227         .remove = flow_dv_remove,
14228         .destroy = flow_dv_destroy,
14229         .query = flow_dv_query,
14230         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14231         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14232         .prepare_policer_rules = flow_dv_prepare_policer_rules,
14233         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14234         .counter_alloc = flow_dv_counter_allocate,
14235         .counter_free = flow_dv_counter_free,
14236         .counter_query = flow_dv_counter_query,
14237         .get_aged_flows = flow_get_aged_flows,
14238         .action_validate = flow_dv_action_validate,
14239         .action_create = flow_dv_action_create,
14240         .action_destroy = flow_dv_action_destroy,
14241         .action_update = flow_dv_action_update,
14242         .action_query = flow_dv_action_query,
14243         .sync_domain = flow_dv_sync_domain,
14244 };
14245
14246 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14247