drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 /**
  88  * Initialize flow attributes structure according to flow items' types.
  89  *
  90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  91  * mode. For tunnel mode, the items to be modified are the outermost ones.
  92  *
  93  * @param[in] item
  94  *   Pointer to item specification.
  95  * @param[out] attr
  96  *   Pointer to flow attributes structure.
  97  * @param[in] dev_flow
  98  *   Pointer to the sub flow.
  99  * @param[in] tunnel_decap
 100  *   Whether action is after tunnel decapsulation.
 101  */
 102 static void
 103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 105 {
 106         uint64_t layers = dev_flow->handle->layers;
 107
 108         /*
 109          * If layers is already initialized, it means this dev_flow is the
 110          * suffix flow, the layers flags is set by the prefix flow. Need to
 111          * use the layer flags from prefix flow as the suffix flow may not
 112          * have the user defined items as the flow is split.
 113          */
 114         if (layers) {
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 116                         attr->ipv4 = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 118                         attr->ipv6 = 1;
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 120                         attr->tcp = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 122                         attr->udp = 1;
 123                 attr->valid = 1;
 124                 return;
 125         }
 126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 127                 uint8_t next_protocol = 0xff;
 128                 switch (item->type) {
 129                 case RTE_FLOW_ITEM_TYPE_GRE:
 130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 134                 case RTE_FLOW_ITEM_TYPE_MPLS:
 135                         if (tunnel_decap)
 136                                 attr->attr = 0;
 137                         break;
 138                 case RTE_FLOW_ITEM_TYPE_IPV4:
 139                         if (!attr->ipv6)
 140                                 attr->ipv4 = 1;
 141                         if (item->mask != NULL &&
 142                             ((const struct rte_flow_item_ipv4 *)
 143                             item->mask)->hdr.next_proto_id)
 144                                 next_protocol =
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->spec))->hdr.next_proto_id &
 147                                     ((const struct rte_flow_item_ipv4 *)
 148                                       (item->mask))->hdr.next_proto_id;
 149                         if ((next_protocol == IPPROTO_IPIP ||
 150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 151                                 attr->attr = 0;
 152                         break;
 153                 case RTE_FLOW_ITEM_TYPE_IPV6:
 154                         if (!attr->ipv4)
 155                                 attr->ipv6 = 1;
 156                         if (item->mask != NULL &&
 157                             ((const struct rte_flow_item_ipv6 *)
 158                             item->mask)->hdr.proto)
 159                                 next_protocol =
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->spec))->hdr.proto &
 162                                     ((const struct rte_flow_item_ipv6 *)
 163                                       (item->mask))->hdr.proto;
 164                         if ((next_protocol == IPPROTO_IPIP ||
 165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 166                                 attr->attr = 0;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_UDP:
 169                         if (!attr->tcp)
 170                                 attr->udp = 1;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_TCP:
 173                         if (!attr->udp)
 174                                 attr->tcp = 1;
 175                         break;
 176                 default:
 177                         break;
 178                 }
 179         }
 180         attr->valid = 1;
 181 }
 182
 183 /**
 184  * Convert rte_mtr_color to mlx5 color.
 185  *
 186  * @param[in] rcol
 187  *   rte_mtr_color.
 188  *
 189  * @return
 190  *   mlx5 color.
 191  */
 192 static int
 193 rte_col_2_mlx5_col(enum rte_color rcol)
 194 {
 195         switch (rcol) {
 196         case RTE_COLOR_GREEN:
 197                 return MLX5_FLOW_COLOR_GREEN;
 198         case RTE_COLOR_YELLOW:
 199                 return MLX5_FLOW_COLOR_YELLOW;
 200         case RTE_COLOR_RED:
 201                 return MLX5_FLOW_COLOR_RED;
 202         default:
 203                 break;
 204         }
 205         return MLX5_FLOW_COLOR_UNDEFINED;
 206 }
 207
 208 struct field_modify_info {
 209         uint32_t size; /* Size of field in protocol header, in bytes. */
 210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 211         enum mlx5_modification_field id;
 212 };
 213
 214 struct field_modify_info modify_eth[] = {
 215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_vlan_out_first_vid[] = {
 223         /* Size in bits !!! */
 224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 225         {0, 0, 0},
 226 };
 227
 228 struct field_modify_info modify_ipv4[] = {
 229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 231         {4, 12, MLX5_MODI_OUT_SIPV4},
 232         {4, 16, MLX5_MODI_OUT_DIPV4},
 233         {0, 0, 0},
 234 };
 235
 236 struct field_modify_info modify_ipv6[] = {
 237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_udp[] = {
 251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 253         {0, 0, 0},
 254 };
 255
 256 struct field_modify_info modify_tcp[] = {
 257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 261         {0, 0, 0},
 262 };
 263
 264 static void
 265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 266                           uint8_t next_protocol, uint64_t *item_flags,
 267                           int *tunnel)
 268 {
 269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 271         if (next_protocol == IPPROTO_IPIP) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 273                 *tunnel = 1;
 274         }
 275         if (next_protocol == IPPROTO_IPV6) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 277                 *tunnel = 1;
 278         }
 279 }
 280
 281 /* Update VLAN's VID/PCP based on input rte_flow_action.
 282  *
 283  * @param[in] action
 284  *   Pointer to struct rte_flow_action.
 285  * @param[out] vlan
 286  *   Pointer to struct rte_vlan_hdr.
 287  */
 288 static void
 289 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 290                          struct rte_vlan_hdr *vlan)
 291 {
 292         uint16_t vlan_tci;
 293         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 294                 vlan_tci =
 295                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 296                                                action->conf)->vlan_pcp;
 297                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 298                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 299                 vlan->vlan_tci |= vlan_tci;
 300         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 301                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 302                 vlan->vlan_tci |= rte_be_to_cpu_16
 303                     (((const struct rte_flow_action_of_set_vlan_vid *)
 304                                              action->conf)->vlan_vid);
 305         }
 306 }
 307
 308 /**
 309  * Fetch 1, 2, 3 or 4 byte field from the byte array
 310  * and return as unsigned integer in host-endian format.
 311  *
 312  * @param[in] data
 313  *   Pointer to data array.
 314  * @param[in] size
 315  *   Size of field to extract.
 316  *
 317  * @return
 318  *   converted field in host endian format.
 319  */
 320 static inline uint32_t
 321 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 322 {
 323         uint32_t ret;
 324
 325         switch (size) {
 326         case 1:
 327                 ret = *data;
 328                 break;
 329         case 2:
 330                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 331                 break;
 332         case 3:
 333                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 334                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 335                 break;
 336         case 4:
 337                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 338                 break;
 339         default:
 340                 MLX5_ASSERT(false);
 341                 ret = 0;
 342                 break;
 343         }
 344         return ret;
 345 }
 346
 347 /**
 348  * Convert modify-header action to DV specification.
 349  *
 350  * Data length of each action is determined by provided field description
 351  * and the item mask. Data bit offset and width of each action is determined
 352  * by provided item mask.
 353  *
 354  * @param[in] item
 355  *   Pointer to item specification.
 356  * @param[in] field
 357  *   Pointer to field modification information.
 358  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 359  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 360  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 361  * @param[in] dcopy
 362  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 363  *   Negative offset value sets the same offset as source offset.
 364  *   size field is ignored, value is taken from source field.
 365  * @param[in,out] resource
 366  *   Pointer to the modify-header resource.
 367  * @param[in] type
 368  *   Type of modification.
 369  * @param[out] error
 370  *   Pointer to the error structure.
 371  *
 372  * @return
 373  *   0 on success, a negative errno value otherwise and rte_errno is set.
 374  */
 375 static int
 376 flow_dv_convert_modify_action(struct rte_flow_item *item,
 377                               struct field_modify_info *field,
 378                               struct field_modify_info *dcopy,
 379                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 380                               uint32_t type, struct rte_flow_error *error)
 381 {
 382         uint32_t i = resource->actions_num;
 383         struct mlx5_modification_cmd *actions = resource->actions;
 384
 385         /*
 386          * The item and mask are provided in big-endian format.
 387          * The fields should be presented as in big-endian format either.
 388          * Mask must be always present, it defines the actual field width.
 389          */
 390         MLX5_ASSERT(item->mask);
 391         MLX5_ASSERT(field->size);
 392         do {
 393                 unsigned int size_b;
 394                 unsigned int off_b;
 395                 uint32_t mask;
 396                 uint32_t data;
 397
 398                 if (i >= MLX5_MAX_MODIFY_NUM)
 399                         return rte_flow_error_set(error, EINVAL,
 400                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 401                                  "too many items to modify");
 402                 /* Fetch variable byte size mask from the array. */
 403                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 404                                            field->offset, field->size);
 405                 if (!mask) {
 406                         ++field;
 407                         continue;
 408                 }
 409                 /* Deduce actual data width in bits from mask value. */
 410                 off_b = rte_bsf32(mask);
 411                 size_b = sizeof(uint32_t) * CHAR_BIT -
 412                          off_b - __builtin_clz(mask);
 413                 MLX5_ASSERT(size_b);
 414                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 415                 actions[i] = (struct mlx5_modification_cmd) {
 416                         .action_type = type,
 417                         .field = field->id,
 418                         .offset = off_b,
 419                         .length = size_b,
 420                 };
 421                 /* Convert entire record to expected big-endian format. */
 422                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 423                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 424                         MLX5_ASSERT(dcopy);
 425                         actions[i].dst_field = dcopy->id;
 426                         actions[i].dst_offset =
 427                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 428                         /* Convert entire record to big-endian format. */
 429                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 430                 } else {
 431                         MLX5_ASSERT(item->spec);
 432                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 433                                                    field->offset, field->size);
 434                         /* Shift out the trailing masked bits from data. */
 435                         data = (data & mask) >> off_b;
 436                         actions[i].data1 = rte_cpu_to_be_32(data);
 437                 }
 438                 ++i;
 439                 ++field;
 440         } while (field->size);
 441         if (resource->actions_num == i)
 442                 return rte_flow_error_set(error, EINVAL,
 443                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 444                                           "invalid modification flow item");
 445         resource->actions_num = i;
 446         return 0;
 447 }
 448
 449 /**
 450  * Convert modify-header set IPv4 address action to DV specification.
 451  *
 452  * @param[in,out] resource
 453  *   Pointer to the modify-header resource.
 454  * @param[in] action
 455  *   Pointer to action specification.
 456  * @param[out] error
 457  *   Pointer to the error structure.
 458  *
 459  * @return
 460  *   0 on success, a negative errno value otherwise and rte_errno is set.
 461  */
 462 static int
 463 flow_dv_convert_action_modify_ipv4
 464                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 465                          const struct rte_flow_action *action,
 466                          struct rte_flow_error *error)
 467 {
 468         const struct rte_flow_action_set_ipv4 *conf =
 469                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 470         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 471         struct rte_flow_item_ipv4 ipv4;
 472         struct rte_flow_item_ipv4 ipv4_mask;
 473
 474         memset(&ipv4, 0, sizeof(ipv4));
 475         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 476         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 477                 ipv4.hdr.src_addr = conf->ipv4_addr;
 478                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 479         } else {
 480                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 481                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 482         }
 483         item.spec = &ipv4;
 484         item.mask = &ipv4_mask;
 485         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 486                                              MLX5_MODIFICATION_TYPE_SET, error);
 487 }
 488
 489 /**
 490  * Convert modify-header set IPv6 address action to DV specification.
 491  *
 492  * @param[in,out] resource
 493  *   Pointer to the modify-header resource.
 494  * @param[in] action
 495  *   Pointer to action specification.
 496  * @param[out] error
 497  *   Pointer to the error structure.
 498  *
 499  * @return
 500  *   0 on success, a negative errno value otherwise and rte_errno is set.
 501  */
 502 static int
 503 flow_dv_convert_action_modify_ipv6
 504                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 505                          const struct rte_flow_action *action,
 506                          struct rte_flow_error *error)
 507 {
 508         const struct rte_flow_action_set_ipv6 *conf =
 509                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 510         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 511         struct rte_flow_item_ipv6 ipv6;
 512         struct rte_flow_item_ipv6 ipv6_mask;
 513
 514         memset(&ipv6, 0, sizeof(ipv6));
 515         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 516         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 517                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 518                        sizeof(ipv6.hdr.src_addr));
 519                 memcpy(&ipv6_mask.hdr.src_addr,
 520                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 521                        sizeof(ipv6.hdr.src_addr));
 522         } else {
 523                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.dst_addr));
 525                 memcpy(&ipv6_mask.hdr.dst_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 527                        sizeof(ipv6.hdr.dst_addr));
 528         }
 529         item.spec = &ipv6;
 530         item.mask = &ipv6_mask;
 531         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 532                                              MLX5_MODIFICATION_TYPE_SET, error);
 533 }
 534
 535 /**
 536  * Convert modify-header set MAC address action to DV specification.
 537  *
 538  * @param[in,out] resource
 539  *   Pointer to the modify-header resource.
 540  * @param[in] action
 541  *   Pointer to action specification.
 542  * @param[out] error
 543  *   Pointer to the error structure.
 544  *
 545  * @return
 546  *   0 on success, a negative errno value otherwise and rte_errno is set.
 547  */
 548 static int
 549 flow_dv_convert_action_modify_mac
 550                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 551                          const struct rte_flow_action *action,
 552                          struct rte_flow_error *error)
 553 {
 554         const struct rte_flow_action_set_mac *conf =
 555                 (const struct rte_flow_action_set_mac *)(action->conf);
 556         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 557         struct rte_flow_item_eth eth;
 558         struct rte_flow_item_eth eth_mask;
 559
 560         memset(&eth, 0, sizeof(eth));
 561         memset(&eth_mask, 0, sizeof(eth_mask));
 562         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 563                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 564                        sizeof(eth.src.addr_bytes));
 565                 memcpy(&eth_mask.src.addr_bytes,
 566                        &rte_flow_item_eth_mask.src.addr_bytes,
 567                        sizeof(eth_mask.src.addr_bytes));
 568         } else {
 569                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.dst.addr_bytes));
 571                 memcpy(&eth_mask.dst.addr_bytes,
 572                        &rte_flow_item_eth_mask.dst.addr_bytes,
 573                        sizeof(eth_mask.dst.addr_bytes));
 574         }
 575         item.spec = &eth;
 576         item.mask = &eth_mask;
 577         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 578                                              MLX5_MODIFICATION_TYPE_SET, error);
 579 }
 580
 581 /**
 582  * Convert modify-header set VLAN VID action to DV specification.
 583  *
 584  * @param[in,out] resource
 585  *   Pointer to the modify-header resource.
 586  * @param[in] action
 587  *   Pointer to action specification.
 588  * @param[out] error
 589  *   Pointer to the error structure.
 590  *
 591  * @return
 592  *   0 on success, a negative errno value otherwise and rte_errno is set.
 593  */
 594 static int
 595 flow_dv_convert_action_modify_vlan_vid
 596                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 597                          const struct rte_flow_action *action,
 598                          struct rte_flow_error *error)
 599 {
 600         const struct rte_flow_action_of_set_vlan_vid *conf =
 601                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 602         int i = resource->actions_num;
 603         struct mlx5_modification_cmd *actions = resource->actions;
 604         struct field_modify_info *field = modify_vlan_out_first_vid;
 605
 606         if (i >= MLX5_MAX_MODIFY_NUM)
 607                 return rte_flow_error_set(error, EINVAL,
 608                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 609                          "too many items to modify");
 610         actions[i] = (struct mlx5_modification_cmd) {
 611                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 612                 .field = field->id,
 613                 .length = field->size,
 614                 .offset = field->offset,
 615         };
 616         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 617         actions[i].data1 = conf->vlan_vid;
 618         actions[i].data1 = actions[i].data1 << 16;
 619         resource->actions_num = ++i;
 620         return 0;
 621 }
 622
 623 /**
 624  * Convert modify-header set TP action to DV specification.
 625  *
 626  * @param[in,out] resource
 627  *   Pointer to the modify-header resource.
 628  * @param[in] action
 629  *   Pointer to action specification.
 630  * @param[in] items
 631  *   Pointer to rte_flow_item objects list.
 632  * @param[in] attr
 633  *   Pointer to flow attributes structure.
 634  * @param[in] dev_flow
 635  *   Pointer to the sub flow.
 636  * @param[in] tunnel_decap
 637  *   Whether action is after tunnel decapsulation.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_tp
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 650                          bool tunnel_decap, struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_tp *conf =
 653                 (const struct rte_flow_action_set_tp *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_udp udp;
 656         struct rte_flow_item_udp udp_mask;
 657         struct rte_flow_item_tcp tcp;
 658         struct rte_flow_item_tcp tcp_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 663         if (attr->udp) {
 664                 memset(&udp, 0, sizeof(udp));
 665                 memset(&udp_mask, 0, sizeof(udp_mask));
 666                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 667                         udp.hdr.src_port = conf->port;
 668                         udp_mask.hdr.src_port =
 669                                         rte_flow_item_udp_mask.hdr.src_port;
 670                 } else {
 671                         udp.hdr.dst_port = conf->port;
 672                         udp_mask.hdr.dst_port =
 673                                         rte_flow_item_udp_mask.hdr.dst_port;
 674                 }
 675                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 676                 item.spec = &udp;
 677                 item.mask = &udp_mask;
 678                 field = modify_udp;
 679         } else {
 680                 MLX5_ASSERT(attr->tcp);
 681                 memset(&tcp, 0, sizeof(tcp));
 682                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 683                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 684                         tcp.hdr.src_port = conf->port;
 685                         tcp_mask.hdr.src_port =
 686                                         rte_flow_item_tcp_mask.hdr.src_port;
 687                 } else {
 688                         tcp.hdr.dst_port = conf->port;
 689                         tcp_mask.hdr.dst_port =
 690                                         rte_flow_item_tcp_mask.hdr.dst_port;
 691                 }
 692                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 693                 item.spec = &tcp;
 694                 item.mask = &tcp_mask;
 695                 field = modify_tcp;
 696         }
 697         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 698                                              MLX5_MODIFICATION_TYPE_SET, error);
 699 }
 700
 701 /**
 702  * Convert modify-header set TTL action to DV specification.
 703  *
 704  * @param[in,out] resource
 705  *   Pointer to the modify-header resource.
 706  * @param[in] action
 707  *   Pointer to action specification.
 708  * @param[in] items
 709  *   Pointer to rte_flow_item objects list.
 710  * @param[in] attr
 711  *   Pointer to flow attributes structure.
 712  * @param[in] dev_flow
 713  *   Pointer to the sub flow.
 714  * @param[in] tunnel_decap
 715  *   Whether action is after tunnel decapsulation.
 716  * @param[out] error
 717  *   Pointer to the error structure.
 718  *
 719  * @return
 720  *   0 on success, a negative errno value otherwise and rte_errno is set.
 721  */
 722 static int
 723 flow_dv_convert_action_modify_ttl
 724                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 725                          const struct rte_flow_action *action,
 726                          const struct rte_flow_item *items,
 727                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 728                          bool tunnel_decap, struct rte_flow_error *error)
 729 {
 730         const struct rte_flow_action_set_ttl *conf =
 731                 (const struct rte_flow_action_set_ttl *)(action->conf);
 732         struct rte_flow_item item;
 733         struct rte_flow_item_ipv4 ipv4;
 734         struct rte_flow_item_ipv4 ipv4_mask;
 735         struct rte_flow_item_ipv6 ipv6;
 736         struct rte_flow_item_ipv6 ipv6_mask;
 737         struct field_modify_info *field;
 738
 739         if (!attr->valid)
 740                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 741         if (attr->ipv4) {
 742                 memset(&ipv4, 0, sizeof(ipv4));
 743                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 744                 ipv4.hdr.time_to_live = conf->ttl_value;
 745                 ipv4_mask.hdr.time_to_live = 0xFF;
 746                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 747                 item.spec = &ipv4;
 748                 item.mask = &ipv4_mask;
 749                 field = modify_ipv4;
 750         } else {
 751                 MLX5_ASSERT(attr->ipv6);
 752                 memset(&ipv6, 0, sizeof(ipv6));
 753                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 754                 ipv6.hdr.hop_limits = conf->ttl_value;
 755                 ipv6_mask.hdr.hop_limits = 0xFF;
 756                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 757                 item.spec = &ipv6;
 758                 item.mask = &ipv6_mask;
 759                 field = modify_ipv6;
 760         }
 761         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 762                                              MLX5_MODIFICATION_TYPE_SET, error);
 763 }
 764
 765 /**
 766  * Convert modify-header decrement TTL action to DV specification.
 767  *
 768  * @param[in,out] resource
 769  *   Pointer to the modify-header resource.
 770  * @param[in] action
 771  *   Pointer to action specification.
 772  * @param[in] items
 773  *   Pointer to rte_flow_item objects list.
 774  * @param[in] attr
 775  *   Pointer to flow attributes structure.
 776  * @param[in] dev_flow
 777  *   Pointer to the sub flow.
 778  * @param[in] tunnel_decap
 779  *   Whether action is after tunnel decapsulation.
 780  * @param[out] error
 781  *   Pointer to the error structure.
 782  *
 783  * @return
 784  *   0 on success, a negative errno value otherwise and rte_errno is set.
 785  */
 786 static int
 787 flow_dv_convert_action_modify_dec_ttl
 788                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 789                          const struct rte_flow_item *items,
 790                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 791                          bool tunnel_decap, struct rte_flow_error *error)
 792 {
 793         struct rte_flow_item item;
 794         struct rte_flow_item_ipv4 ipv4;
 795         struct rte_flow_item_ipv4 ipv4_mask;
 796         struct rte_flow_item_ipv6 ipv6;
 797         struct rte_flow_item_ipv6 ipv6_mask;
 798         struct field_modify_info *field;
 799
 800         if (!attr->valid)
 801                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 802         if (attr->ipv4) {
 803                 memset(&ipv4, 0, sizeof(ipv4));
 804                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 805                 ipv4.hdr.time_to_live = 0xFF;
 806                 ipv4_mask.hdr.time_to_live = 0xFF;
 807                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 808                 item.spec = &ipv4;
 809                 item.mask = &ipv4_mask;
 810                 field = modify_ipv4;
 811         } else {
 812                 MLX5_ASSERT(attr->ipv6);
 813                 memset(&ipv6, 0, sizeof(ipv6));
 814                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 815                 ipv6.hdr.hop_limits = 0xFF;
 816                 ipv6_mask.hdr.hop_limits = 0xFF;
 817                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 818                 item.spec = &ipv6;
 819                 item.mask = &ipv6_mask;
 820                 field = modify_ipv6;
 821         }
 822         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 823                                              MLX5_MODIFICATION_TYPE_ADD, error);
 824 }
 825
 826 /**
 827  * Convert modify-header increment/decrement TCP Sequence number
 828  * to DV specification.
 829  *
 830  * @param[in,out] resource
 831  *   Pointer to the modify-header resource.
 832  * @param[in] action
 833  *   Pointer to action specification.
 834  * @param[out] error
 835  *   Pointer to the error structure.
 836  *
 837  * @return
 838  *   0 on success, a negative errno value otherwise and rte_errno is set.
 839  */
 840 static int
 841 flow_dv_convert_action_modify_tcp_seq
 842                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 843                          const struct rte_flow_action *action,
 844                          struct rte_flow_error *error)
 845 {
 846         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 847         uint64_t value = rte_be_to_cpu_32(*conf);
 848         struct rte_flow_item item;
 849         struct rte_flow_item_tcp tcp;
 850         struct rte_flow_item_tcp tcp_mask;
 851
 852         memset(&tcp, 0, sizeof(tcp));
 853         memset(&tcp_mask, 0, sizeof(tcp_mask));
 854         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 855                 /*
 856                  * The HW has no decrement operation, only increment operation.
 857                  * To simulate decrement X from Y using increment operation
 858                  * we need to add UINT32_MAX X times to Y.
 859                  * Each adding of UINT32_MAX decrements Y by 1.
 860                  */
 861                 value *= UINT32_MAX;
 862         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 863         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 864         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 865         item.spec = &tcp;
 866         item.mask = &tcp_mask;
 867         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 868                                              MLX5_MODIFICATION_TYPE_ADD, error);
 869 }
 870
 871 /**
 872  * Convert modify-header increment/decrement TCP Acknowledgment number
 873  * to DV specification.
 874  *
 875  * @param[in,out] resource
 876  *   Pointer to the modify-header resource.
 877  * @param[in] action
 878  *   Pointer to action specification.
 879  * @param[out] error
 880  *   Pointer to the error structure.
 881  *
 882  * @return
 883  *   0 on success, a negative errno value otherwise and rte_errno is set.
 884  */
 885 static int
 886 flow_dv_convert_action_modify_tcp_ack
 887                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 888                          const struct rte_flow_action *action,
 889                          struct rte_flow_error *error)
 890 {
 891         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 892         uint64_t value = rte_be_to_cpu_32(*conf);
 893         struct rte_flow_item item;
 894         struct rte_flow_item_tcp tcp;
 895         struct rte_flow_item_tcp tcp_mask;
 896
 897         memset(&tcp, 0, sizeof(tcp));
 898         memset(&tcp_mask, 0, sizeof(tcp_mask));
 899         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 900                 /*
 901                  * The HW has no decrement operation, only increment operation.
 902                  * To simulate decrement X from Y using increment operation
 903                  * we need to add UINT32_MAX X times to Y.
 904                  * Each adding of UINT32_MAX decrements Y by 1.
 905                  */
 906                 value *= UINT32_MAX;
 907         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 908         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 909         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 910         item.spec = &tcp;
 911         item.mask = &tcp_mask;
 912         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 913                                              MLX5_MODIFICATION_TYPE_ADD, error);
 914 }
 915
 916 static enum mlx5_modification_field reg_to_field[] = {
 917         [REG_NON] = MLX5_MODI_OUT_NONE,
 918         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 919         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 920         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 921         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 922         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 923         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 924         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 925         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 926         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 927         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 928 };
 929
 930 /**
 931  * Convert register set to DV specification.
 932  *
 933  * @param[in,out] resource
 934  *   Pointer to the modify-header resource.
 935  * @param[in] action
 936  *   Pointer to action specification.
 937  * @param[out] error
 938  *   Pointer to the error structure.
 939  *
 940  * @return
 941  *   0 on success, a negative errno value otherwise and rte_errno is set.
 942  */
 943 static int
 944 flow_dv_convert_action_set_reg
 945                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 946                          const struct rte_flow_action *action,
 947                          struct rte_flow_error *error)
 948 {
 949         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 950         struct mlx5_modification_cmd *actions = resource->actions;
 951         uint32_t i = resource->actions_num;
 952
 953         if (i >= MLX5_MAX_MODIFY_NUM)
 954                 return rte_flow_error_set(error, EINVAL,
 955                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 956                                           "too many items to modify");
 957         MLX5_ASSERT(conf->id != REG_NON);
 958         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 959         actions[i] = (struct mlx5_modification_cmd) {
 960                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 961                 .field = reg_to_field[conf->id],
 962         };
 963         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 964         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 965         ++i;
 966         resource->actions_num = i;
 967         return 0;
 968 }
 969
 970 /**
 971  * Convert SET_TAG action to DV specification.
 972  *
 973  * @param[in] dev
 974  *   Pointer to the rte_eth_dev structure.
 975  * @param[in,out] resource
 976  *   Pointer to the modify-header resource.
 977  * @param[in] conf
 978  *   Pointer to action specification.
 979  * @param[out] error
 980  *   Pointer to the error structure.
 981  *
 982  * @return
 983  *   0 on success, a negative errno value otherwise and rte_errno is set.
 984  */
 985 static int
 986 flow_dv_convert_action_set_tag
 987                         (struct rte_eth_dev *dev,
 988                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 989                          const struct rte_flow_action_set_tag *conf,
 990                          struct rte_flow_error *error)
 991 {
 992         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 993         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 994         struct rte_flow_item item = {
 995                 .spec = &data,
 996                 .mask = &mask,
 997         };
 998         struct field_modify_info reg_c_x[] = {
 999                 [1] = {0, 0, 0},
1000         };
1001         enum mlx5_modification_field reg_type;
1002         int ret;
1003
1004         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1005         if (ret < 0)
1006                 return ret;
1007         MLX5_ASSERT(ret != REG_NON);
1008         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1009         reg_type = reg_to_field[ret];
1010         MLX5_ASSERT(reg_type > 0);
1011         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1012         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1013                                              MLX5_MODIFICATION_TYPE_SET, error);
1014 }
1015
1016 /**
1017  * Convert internal COPY_REG action to DV specification.
1018  *
1019  * @param[in] dev
1020  *   Pointer to the rte_eth_dev structure.
1021  * @param[in,out] res
1022  *   Pointer to the modify-header resource.
1023  * @param[in] action
1024  *   Pointer to action specification.
1025  * @param[out] error
1026  *   Pointer to the error structure.
1027  *
1028  * @return
1029  *   0 on success, a negative errno value otherwise and rte_errno is set.
1030  */
1031 static int
1032 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1033                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1034                                  const struct rte_flow_action *action,
1035                                  struct rte_flow_error *error)
1036 {
1037         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1038         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1039         struct rte_flow_item item = {
1040                 .spec = NULL,
1041                 .mask = &mask,
1042         };
1043         struct field_modify_info reg_src[] = {
1044                 {4, 0, reg_to_field[conf->src]},
1045                 {0, 0, 0},
1046         };
1047         struct field_modify_info reg_dst = {
1048                 .offset = 0,
1049                 .id = reg_to_field[conf->dst],
1050         };
1051         /* Adjust reg_c[0] usage according to reported mask. */
1052         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1053                 struct mlx5_priv *priv = dev->data->dev_private;
1054                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1055
1056                 MLX5_ASSERT(reg_c0);
1057                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1058                 if (conf->dst == REG_C_0) {
1059                         /* Copy to reg_c[0], within mask only. */
1060                         reg_dst.offset = rte_bsf32(reg_c0);
1061                         /*
1062                          * Mask is ignoring the enianness, because
1063                          * there is no conversion in datapath.
1064                          */
1065 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1066                         /* Copy from destination lower bits to reg_c[0]. */
1067                         mask = reg_c0 >> reg_dst.offset;
1068 #else
1069                         /* Copy from destination upper bits to reg_c[0]. */
1070                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1071                                           rte_fls_u32(reg_c0));
1072 #endif
1073                 } else {
1074                         mask = rte_cpu_to_be_32(reg_c0);
1075 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1076                         /* Copy from reg_c[0] to destination lower bits. */
1077                         reg_dst.offset = 0;
1078 #else
1079                         /* Copy from reg_c[0] to destination upper bits. */
1080                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1081                                          (rte_fls_u32(reg_c0) -
1082                                           rte_bsf32(reg_c0));
1083 #endif
1084                 }
1085         }
1086         return flow_dv_convert_modify_action(&item,
1087                                              reg_src, &reg_dst, res,
1088                                              MLX5_MODIFICATION_TYPE_COPY,
1089                                              error);
1090 }
1091
1092 /**
1093  * Convert MARK action to DV specification. This routine is used
1094  * in extensive metadata only and requires metadata register to be
1095  * handled. In legacy mode hardware tag resource is engaged.
1096  *
1097  * @param[in] dev
1098  *   Pointer to the rte_eth_dev structure.
1099  * @param[in] conf
1100  *   Pointer to MARK action specification.
1101  * @param[in,out] resource
1102  *   Pointer to the modify-header resource.
1103  * @param[out] error
1104  *   Pointer to the error structure.
1105  *
1106  * @return
1107  *   0 on success, a negative errno value otherwise and rte_errno is set.
1108  */
1109 static int
1110 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1111                             const struct rte_flow_action_mark *conf,
1112                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1113                             struct rte_flow_error *error)
1114 {
1115         struct mlx5_priv *priv = dev->data->dev_private;
1116         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1117                                            priv->sh->dv_mark_mask);
1118         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1119         struct rte_flow_item item = {
1120                 .spec = &data,
1121                 .mask = &mask,
1122         };
1123         struct field_modify_info reg_c_x[] = {
1124                 [1] = {0, 0, 0},
1125         };
1126         int reg;
1127
1128         if (!mask)
1129                 return rte_flow_error_set(error, EINVAL,
1130                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1131                                           NULL, "zero mark action mask");
1132         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1133         if (reg < 0)
1134                 return reg;
1135         MLX5_ASSERT(reg > 0);
1136         if (reg == REG_C_0) {
1137                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1138                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1139
1140                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1141                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1142                 mask = rte_cpu_to_be_32(mask << shl_c0);
1143         }
1144         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1145         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1146                                              MLX5_MODIFICATION_TYPE_SET, error);
1147 }
1148
1149 /**
1150  * Get metadata register index for specified steering domain.
1151  *
1152  * @param[in] dev
1153  *   Pointer to the rte_eth_dev structure.
1154  * @param[in] attr
1155  *   Attributes of flow to determine steering domain.
1156  * @param[out] error
1157  *   Pointer to the error structure.
1158  *
1159  * @return
1160  *   positive index on success, a negative errno value otherwise
1161  *   and rte_errno is set.
1162  */
1163 static enum modify_reg
1164 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1165                          const struct rte_flow_attr *attr,
1166                          struct rte_flow_error *error)
1167 {
1168         int reg =
1169                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1170                                           MLX5_METADATA_FDB :
1171                                             attr->egress ?
1172                                             MLX5_METADATA_TX :
1173                                             MLX5_METADATA_RX, 0, error);
1174         if (reg < 0)
1175                 return rte_flow_error_set(error,
1176                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1177                                           NULL, "unavailable "
1178                                           "metadata register");
1179         return reg;
1180 }
1181
1182 /**
1183  * Convert SET_META action to DV specification.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in,out] resource
1188  *   Pointer to the modify-header resource.
1189  * @param[in] attr
1190  *   Attributes of flow that includes this item.
1191  * @param[in] conf
1192  *   Pointer to action specification.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   0 on success, a negative errno value otherwise and rte_errno is set.
1198  */
1199 static int
1200 flow_dv_convert_action_set_meta
1201                         (struct rte_eth_dev *dev,
1202                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1203                          const struct rte_flow_attr *attr,
1204                          const struct rte_flow_action_set_meta *conf,
1205                          struct rte_flow_error *error)
1206 {
1207         uint32_t data = conf->data;
1208         uint32_t mask = conf->mask;
1209         struct rte_flow_item item = {
1210                 .spec = &data,
1211                 .mask = &mask,
1212         };
1213         struct field_modify_info reg_c_x[] = {
1214                 [1] = {0, 0, 0},
1215         };
1216         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1217
1218         if (reg < 0)
1219                 return reg;
1220         MLX5_ASSERT(reg != REG_NON);
1221         /*
1222          * In datapath code there is no endianness
1223          * coversions for perfromance reasons, all
1224          * pattern conversions are done in rte_flow.
1225          */
1226         if (reg == REG_C_0) {
1227                 struct mlx5_priv *priv = dev->data->dev_private;
1228                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1229                 uint32_t shl_c0;
1230
1231                 MLX5_ASSERT(msk_c0);
1232 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1233                 shl_c0 = rte_bsf32(msk_c0);
1234 #else
1235                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1236 #endif
1237                 mask <<= shl_c0;
1238                 data <<= shl_c0;
1239                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1240         }
1241         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1242         /* The routine expects parameters in memory as big-endian ones. */
1243         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1244                                              MLX5_MODIFICATION_TYPE_SET, error);
1245 }
1246
1247 /**
1248  * Convert modify-header set IPv4 DSCP action to DV specification.
1249  *
1250  * @param[in,out] resource
1251  *   Pointer to the modify-header resource.
1252  * @param[in] action
1253  *   Pointer to action specification.
1254  * @param[out] error
1255  *   Pointer to the error structure.
1256  *
1257  * @return
1258  *   0 on success, a negative errno value otherwise and rte_errno is set.
1259  */
1260 static int
1261 flow_dv_convert_action_modify_ipv4_dscp
1262                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1263                          const struct rte_flow_action *action,
1264                          struct rte_flow_error *error)
1265 {
1266         const struct rte_flow_action_set_dscp *conf =
1267                 (const struct rte_flow_action_set_dscp *)(action->conf);
1268         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1269         struct rte_flow_item_ipv4 ipv4;
1270         struct rte_flow_item_ipv4 ipv4_mask;
1271
1272         memset(&ipv4, 0, sizeof(ipv4));
1273         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1274         ipv4.hdr.type_of_service = conf->dscp;
1275         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1276         item.spec = &ipv4;
1277         item.mask = &ipv4_mask;
1278         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv6 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv6_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1304         struct rte_flow_item_ipv6 ipv6;
1305         struct rte_flow_item_ipv6 ipv6_mask;
1306
1307         memset(&ipv6, 0, sizeof(ipv6));
1308         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1309         /*
1310          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1311          * rdma-core only accept the DSCP bits byte aligned start from
1312          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1313          * bits in IPv6 case as rdma-core requires byte aligned value.
1314          */
1315         ipv6.hdr.vtc_flow = conf->dscp;
1316         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1317         item.spec = &ipv6;
1318         item.mask = &ipv6_mask;
1319         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1320                                              MLX5_MODIFICATION_TYPE_SET, error);
1321 }
1322
1323 /**
1324  * Validate MARK item.
1325  *
1326  * @param[in] dev
1327  *   Pointer to the rte_eth_dev structure.
1328  * @param[in] item
1329  *   Item specification.
1330  * @param[in] attr
1331  *   Attributes of flow that includes this item.
1332  * @param[out] error
1333  *   Pointer to error structure.
1334  *
1335  * @return
1336  *   0 on success, a negative errno value otherwise and rte_errno is set.
1337  */
1338 static int
1339 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1340                            const struct rte_flow_item *item,
1341                            const struct rte_flow_attr *attr __rte_unused,
1342                            struct rte_flow_error *error)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_dev_config *config = &priv->config;
1346         const struct rte_flow_item_mark *spec = item->spec;
1347         const struct rte_flow_item_mark *mask = item->mask;
1348         const struct rte_flow_item_mark nic_mask = {
1349                 .id = priv->sh->dv_mark_mask,
1350         };
1351         int ret;
1352
1353         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1354                 return rte_flow_error_set(error, ENOTSUP,
1355                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1356                                           "extended metadata feature"
1357                                           " isn't enabled");
1358         if (!mlx5_flow_ext_mreg_supported(dev))
1359                 return rte_flow_error_set(error, ENOTSUP,
1360                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1361                                           "extended metadata register"
1362                                           " isn't supported");
1363         if (!nic_mask.id)
1364                 return rte_flow_error_set(error, ENOTSUP,
1365                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1366                                           "extended metadata register"
1367                                           " isn't available");
1368         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1369         if (ret < 0)
1370                 return ret;
1371         if (!spec)
1372                 return rte_flow_error_set(error, EINVAL,
1373                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1374                                           item->spec,
1375                                           "data cannot be empty");
1376         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1377                 return rte_flow_error_set(error, EINVAL,
1378                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1379                                           &spec->id,
1380                                           "mark id exceeds the limit");
1381         if (!mask)
1382                 mask = &nic_mask;
1383         if (!mask->id)
1384                 return rte_flow_error_set(error, EINVAL,
1385                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386                                         "mask cannot be zero");
1387
1388         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1389                                         (const uint8_t *)&nic_mask,
1390                                         sizeof(struct rte_flow_item_mark),
1391                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1392         if (ret < 0)
1393                 return ret;
1394         return 0;
1395 }
1396
1397 /**
1398  * Validate META item.
1399  *
1400  * @param[in] dev
1401  *   Pointer to the rte_eth_dev structure.
1402  * @param[in] item
1403  *   Item specification.
1404  * @param[in] attr
1405  *   Attributes of flow that includes this item.
1406  * @param[out] error
1407  *   Pointer to error structure.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1414                            const struct rte_flow_item *item,
1415                            const struct rte_flow_attr *attr,
1416                            struct rte_flow_error *error)
1417 {
1418         struct mlx5_priv *priv = dev->data->dev_private;
1419         struct mlx5_dev_config *config = &priv->config;
1420         const struct rte_flow_item_meta *spec = item->spec;
1421         const struct rte_flow_item_meta *mask = item->mask;
1422         struct rte_flow_item_meta nic_mask = {
1423                 .data = UINT32_MAX
1424         };
1425         int reg;
1426         int ret;
1427
1428         if (!spec)
1429                 return rte_flow_error_set(error, EINVAL,
1430                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1431                                           item->spec,
1432                                           "data cannot be empty");
1433         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1434                 if (!mlx5_flow_ext_mreg_supported(dev))
1435                         return rte_flow_error_set(error, ENOTSUP,
1436                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1437                                           "extended metadata register"
1438                                           " isn't supported");
1439                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1440                 if (reg < 0)
1441                         return reg;
1442                 if (reg == REG_NON)
1443                         return rte_flow_error_set(error, ENOTSUP,
1444                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1445                                         "unavalable extended metadata register");
1446                 if (reg == REG_B)
1447                         return rte_flow_error_set(error, ENOTSUP,
1448                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1449                                           "match on reg_b "
1450                                           "isn't supported");
1451                 if (reg != REG_A)
1452                         nic_mask.data = priv->sh->dv_meta_mask;
1453         } else if (attr->transfer) {
1454                 return rte_flow_error_set(error, ENOTSUP,
1455                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1456                                         "extended metadata feature "
1457                                         "should be enabled when "
1458                                         "meta item is requested "
1459                                         "with e-switch mode ");
1460         }
1461         if (!mask)
1462                 mask = &rte_flow_item_meta_mask;
1463         if (!mask->data)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1466                                         "mask cannot be zero");
1467
1468         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1469                                         (const uint8_t *)&nic_mask,
1470                                         sizeof(struct rte_flow_item_meta),
1471                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1472         return ret;
1473 }
1474
1475 /**
1476  * Validate TAG item.
1477  *
1478  * @param[in] dev
1479  *   Pointer to the rte_eth_dev structure.
1480  * @param[in] item
1481  *   Item specification.
1482  * @param[in] attr
1483  *   Attributes of flow that includes this item.
1484  * @param[out] error
1485  *   Pointer to error structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 static int
1491 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1492                           const struct rte_flow_item *item,
1493                           const struct rte_flow_attr *attr __rte_unused,
1494                           struct rte_flow_error *error)
1495 {
1496         const struct rte_flow_item_tag *spec = item->spec;
1497         const struct rte_flow_item_tag *mask = item->mask;
1498         const struct rte_flow_item_tag nic_mask = {
1499                 .data = RTE_BE32(UINT32_MAX),
1500                 .index = 0xff,
1501         };
1502         int ret;
1503
1504         if (!mlx5_flow_ext_mreg_supported(dev))
1505                 return rte_flow_error_set(error, ENOTSUP,
1506                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1507                                           "extensive metadata register"
1508                                           " isn't supported");
1509         if (!spec)
1510                 return rte_flow_error_set(error, EINVAL,
1511                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1512                                           item->spec,
1513                                           "data cannot be empty");
1514         if (!mask)
1515                 mask = &rte_flow_item_tag_mask;
1516         if (!mask->data)
1517                 return rte_flow_error_set(error, EINVAL,
1518                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1519                                         "mask cannot be zero");
1520
1521         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1522                                         (const uint8_t *)&nic_mask,
1523                                         sizeof(struct rte_flow_item_tag),
1524                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1525         if (ret < 0)
1526                 return ret;
1527         if (mask->index != 0xff)
1528                 return rte_flow_error_set(error, EINVAL,
1529                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1530                                           "partial mask for tag index"
1531                                           " is not supported");
1532         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1533         if (ret < 0)
1534                 return ret;
1535         MLX5_ASSERT(ret != REG_NON);
1536         return 0;
1537 }
1538
1539 /**
1540  * Validate vport item.
1541  *
1542  * @param[in] dev
1543  *   Pointer to the rte_eth_dev structure.
1544  * @param[in] item
1545  *   Item specification.
1546  * @param[in] attr
1547  *   Attributes of flow that includes this item.
1548  * @param[in] item_flags
1549  *   Bit-fields that holds the items detected until now.
1550  * @param[out] error
1551  *   Pointer to error structure.
1552  *
1553  * @return
1554  *   0 on success, a negative errno value otherwise and rte_errno is set.
1555  */
1556 static int
1557 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1558                               const struct rte_flow_item *item,
1559                               const struct rte_flow_attr *attr,
1560                               uint64_t item_flags,
1561                               struct rte_flow_error *error)
1562 {
1563         const struct rte_flow_item_port_id *spec = item->spec;
1564         const struct rte_flow_item_port_id *mask = item->mask;
1565         const struct rte_flow_item_port_id switch_mask = {
1566                         .id = 0xffffffff,
1567         };
1568         struct mlx5_priv *esw_priv;
1569         struct mlx5_priv *dev_priv;
1570         int ret;
1571
1572         if (!attr->transfer)
1573                 return rte_flow_error_set(error, EINVAL,
1574                                           RTE_FLOW_ERROR_TYPE_ITEM,
1575                                           NULL,
1576                                           "match on port id is valid only"
1577                                           " when transfer flag is enabled");
1578         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1579                 return rte_flow_error_set(error, ENOTSUP,
1580                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1581                                           "multiple source ports are not"
1582                                           " supported");
1583         if (!mask)
1584                 mask = &switch_mask;
1585         if (mask->id != 0xffffffff)
1586                 return rte_flow_error_set(error, ENOTSUP,
1587                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1588                                            mask,
1589                                            "no support for partial mask on"
1590                                            " \"id\" field");
1591         ret = mlx5_flow_item_acceptable
1592                                 (item, (const uint8_t *)mask,
1593                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1594                                  sizeof(struct rte_flow_item_port_id),
1595                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1596         if (ret)
1597                 return ret;
1598         if (!spec)
1599                 return 0;
1600         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1601         if (!esw_priv)
1602                 return rte_flow_error_set(error, rte_errno,
1603                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1604                                           "failed to obtain E-Switch info for"
1605                                           " port");
1606         dev_priv = mlx5_dev_to_eswitch_info(dev);
1607         if (!dev_priv)
1608                 return rte_flow_error_set(error, rte_errno,
1609                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1610                                           NULL,
1611                                           "failed to obtain E-Switch info");
1612         if (esw_priv->domain_id != dev_priv->domain_id)
1613                 return rte_flow_error_set(error, EINVAL,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1615                                           "cannot match on a port from a"
1616                                           " different E-Switch");
1617         return 0;
1618 }
1619
1620 /**
1621  * Validate VLAN item.
1622  *
1623  * @param[in] item
1624  *   Item specification.
1625  * @param[in] item_flags
1626  *   Bit-fields that holds the items detected until now.
1627  * @param[in] dev
1628  *   Ethernet device flow is being created on.
1629  * @param[out] error
1630  *   Pointer to error structure.
1631  *
1632  * @return
1633  *   0 on success, a negative errno value otherwise and rte_errno is set.
1634  */
1635 static int
1636 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1637                            uint64_t item_flags,
1638                            struct rte_eth_dev *dev,
1639                            struct rte_flow_error *error)
1640 {
1641         const struct rte_flow_item_vlan *mask = item->mask;
1642         const struct rte_flow_item_vlan nic_mask = {
1643                 .tci = RTE_BE16(UINT16_MAX),
1644                 .inner_type = RTE_BE16(UINT16_MAX),
1645                 .has_more_vlan = 1,
1646         };
1647         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1648         int ret;
1649         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1650                                         MLX5_FLOW_LAYER_INNER_L4) :
1651                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1652                                         MLX5_FLOW_LAYER_OUTER_L4);
1653         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1654                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1655
1656         if (item_flags & vlanm)
1657                 return rte_flow_error_set(error, EINVAL,
1658                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1659                                           "multiple VLAN layers not supported");
1660         else if ((item_flags & l34m) != 0)
1661                 return rte_flow_error_set(error, EINVAL,
1662                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1663                                           "VLAN cannot follow L3/L4 layer");
1664         if (!mask)
1665                 mask = &rte_flow_item_vlan_mask;
1666         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1667                                         (const uint8_t *)&nic_mask,
1668                                         sizeof(struct rte_flow_item_vlan),
1669                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1670         if (ret)
1671                 return ret;
1672         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1673                 struct mlx5_priv *priv = dev->data->dev_private;
1674
1675                 if (priv->vmwa_context) {
1676                         /*
1677                          * Non-NULL context means we have a virtual machine
1678                          * and SR-IOV enabled, we have to create VLAN interface
1679                          * to make hypervisor to setup E-Switch vport
1680                          * context correctly. We avoid creating the multiple
1681                          * VLAN interfaces, so we cannot support VLAN tag mask.
1682                          */
1683                         return rte_flow_error_set(error, EINVAL,
1684                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1685                                                   item,
1686                                                   "VLAN tag mask is not"
1687                                                   " supported in virtual"
1688                                                   " environment");
1689                 }
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * GTP flags are contained in 1 byte of the format:
1696  * -------------------------------------------
1697  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1698  * |-----------------------------------------|
1699  * | value | Version | PT | Res | E | S | PN |
1700  * -------------------------------------------
1701  *
1702  * Matching is supported only for GTP flags E, S, PN.
1703  */
1704 #define MLX5_GTP_FLAGS_MASK     0x07
1705
1706 /**
1707  * Validate GTP item.
1708  *
1709  * @param[in] dev
1710  *   Pointer to the rte_eth_dev structure.
1711  * @param[in] item
1712  *   Item specification.
1713  * @param[in] item_flags
1714  *   Bit-fields that holds the items detected until now.
1715  * @param[out] error
1716  *   Pointer to error structure.
1717  *
1718  * @return
1719  *   0 on success, a negative errno value otherwise and rte_errno is set.
1720  */
1721 static int
1722 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1723                           const struct rte_flow_item *item,
1724                           uint64_t item_flags,
1725                           struct rte_flow_error *error)
1726 {
1727         struct mlx5_priv *priv = dev->data->dev_private;
1728         const struct rte_flow_item_gtp *spec = item->spec;
1729         const struct rte_flow_item_gtp *mask = item->mask;
1730         const struct rte_flow_item_gtp nic_mask = {
1731                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1732                 .msg_type = 0xff,
1733                 .teid = RTE_BE32(0xffffffff),
1734         };
1735
1736         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1739                                           "GTP support is not enabled");
1740         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1741                 return rte_flow_error_set(error, ENOTSUP,
1742                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1743                                           "multiple tunnel layers not"
1744                                           " supported");
1745         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1748                                           "no outer UDP layer found");
1749         if (!mask)
1750                 mask = &rte_flow_item_gtp_mask;
1751         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1752                 return rte_flow_error_set(error, ENOTSUP,
1753                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1754                                           "Match is supported for GTP"
1755                                           " flags only");
1756         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1757                                          (const uint8_t *)&nic_mask,
1758                                          sizeof(struct rte_flow_item_gtp),
1759                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1760 }
1761
1762 /**
1763  * Validate IPV4 item.
1764  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1765  * add specific validation of fragment_offset field,
1766  *
1767  * @param[in] item
1768  *   Item specification.
1769  * @param[in] item_flags
1770  *   Bit-fields that holds the items detected until now.
1771  * @param[out] error
1772  *   Pointer to error structure.
1773  *
1774  * @return
1775  *   0 on success, a negative errno value otherwise and rte_errno is set.
1776  */
1777 static int
1778 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1779                            uint64_t item_flags,
1780                            uint64_t last_item,
1781                            uint16_t ether_type,
1782                            struct rte_flow_error *error)
1783 {
1784         int ret;
1785         const struct rte_flow_item_ipv4 *spec = item->spec;
1786         const struct rte_flow_item_ipv4 *last = item->last;
1787         const struct rte_flow_item_ipv4 *mask = item->mask;
1788         rte_be16_t fragment_offset_spec = 0;
1789         rte_be16_t fragment_offset_last = 0;
1790         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1791                 .hdr = {
1792                         .src_addr = RTE_BE32(0xffffffff),
1793                         .dst_addr = RTE_BE32(0xffffffff),
1794                         .type_of_service = 0xff,
1795                         .fragment_offset = RTE_BE16(0xffff),
1796                         .next_proto_id = 0xff,
1797                         .time_to_live = 0xff,
1798                 },
1799         };
1800
1801         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1802                                            ether_type, &nic_ipv4_mask,
1803                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1804         if (ret < 0)
1805                 return ret;
1806         if (spec && mask)
1807                 fragment_offset_spec = spec->hdr.fragment_offset &
1808                                        mask->hdr.fragment_offset;
1809         if (!fragment_offset_spec)
1810                 return 0;
1811         /*
1812          * spec and mask are valid, enforce using full mask to make sure the
1813          * complete value is used correctly.
1814          */
1815         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1816                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1817                 return rte_flow_error_set(error, EINVAL,
1818                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1819                                           item, "must use full mask for"
1820                                           " fragment_offset");
1821         /*
1822          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1823          * indicating this is 1st fragment of fragmented packet.
1824          * This is not yet supported in MLX5, return appropriate error message.
1825          */
1826         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1829                                           "match on first fragment not "
1830                                           "supported");
1831         if (fragment_offset_spec && !last)
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1834                                           "specified value not supported");
1835         /* spec and last are valid, validate the specified range. */
1836         fragment_offset_last = last->hdr.fragment_offset &
1837                                mask->hdr.fragment_offset;
1838         /*
1839          * Match on fragment_offset spec 0x2001 and last 0x3fff
1840          * means MF is 1 and frag-offset is > 0.
1841          * This packet is fragment 2nd and onward, excluding last.
1842          * This is not yet supported in MLX5, return appropriate
1843          * error message.
1844          */
1845         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1846             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1847                 return rte_flow_error_set(error, ENOTSUP,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1849                                           last, "match on following "
1850                                           "fragments not supported");
1851         /*
1852          * Match on fragment_offset spec 0x0001 and last 0x1fff
1853          * means MF is 0 and frag-offset is > 0.
1854          * This packet is last fragment of fragmented packet.
1855          * This is not yet supported in MLX5, return appropriate
1856          * error message.
1857          */
1858         if (fragment_offset_spec == RTE_BE16(1) &&
1859             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1860                 return rte_flow_error_set(error, ENOTSUP,
1861                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1862                                           last, "match on last "
1863                                           "fragment not supported");
1864         /*
1865          * Match on fragment_offset spec 0x0001 and last 0x3fff
1866          * means MF and/or frag-offset is not 0.
1867          * This is a fragmented packet.
1868          * Other range values are invalid and rejected.
1869          */
1870         if (!(fragment_offset_spec == RTE_BE16(1) &&
1871               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1872                 return rte_flow_error_set(error, ENOTSUP,
1873                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1874                                           "specified range not supported");
1875         return 0;
1876 }
1877
1878 /**
1879  * Validate IPV6 fragment extension item.
1880  *
1881  * @param[in] item
1882  *   Item specification.
1883  * @param[in] item_flags
1884  *   Bit-fields that holds the items detected until now.
1885  * @param[out] error
1886  *   Pointer to error structure.
1887  *
1888  * @return
1889  *   0 on success, a negative errno value otherwise and rte_errno is set.
1890  */
1891 static int
1892 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1893                                     uint64_t item_flags,
1894                                     struct rte_flow_error *error)
1895 {
1896         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1897         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1898         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1899         rte_be16_t frag_data_spec = 0;
1900         rte_be16_t frag_data_last = 0;
1901         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1902         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1903                                       MLX5_FLOW_LAYER_OUTER_L4;
1904         int ret = 0;
1905         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1906                 .hdr = {
1907                         .next_header = 0xff,
1908                         .frag_data = RTE_BE16(0xffff),
1909                 },
1910         };
1911
1912         if (item_flags & l4m)
1913                 return rte_flow_error_set(error, EINVAL,
1914                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1915                                           "ipv6 fragment extension item cannot "
1916                                           "follow L4 item.");
1917         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1918             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1919                 return rte_flow_error_set(error, EINVAL,
1920                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1921                                           "ipv6 fragment extension item must "
1922                                           "follow ipv6 item");
1923         if (spec && mask)
1924                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1925         if (!frag_data_spec)
1926                 return 0;
1927         /*
1928          * spec and mask are valid, enforce using full mask to make sure the
1929          * complete value is used correctly.
1930          */
1931         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1932                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1933                 return rte_flow_error_set(error, EINVAL,
1934                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1935                                           item, "must use full mask for"
1936                                           " frag_data");
1937         /*
1938          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1939          * This is 1st fragment of fragmented packet.
1940          */
1941         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1942                 return rte_flow_error_set(error, ENOTSUP,
1943                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1944                                           "match on first fragment not "
1945                                           "supported");
1946         if (frag_data_spec && !last)
1947                 return rte_flow_error_set(error, EINVAL,
1948                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1949                                           "specified value not supported");
1950         ret = mlx5_flow_item_acceptable
1951                                 (item, (const uint8_t *)mask,
1952                                  (const uint8_t *)&nic_mask,
1953                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1954                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1955         if (ret)
1956                 return ret;
1957         /* spec and last are valid, validate the specified range. */
1958         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1959         /*
1960          * Match on frag_data spec 0x0009 and last 0xfff9
1961          * means M is 1 and frag-offset is > 0.
1962          * This packet is fragment 2nd and onward, excluding last.
1963          * This is not yet supported in MLX5, return appropriate
1964          * error message.
1965          */
1966         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1967                                        RTE_IPV6_EHDR_MF_MASK) &&
1968             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1969                 return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1971                                           last, "match on following "
1972                                           "fragments not supported");
1973         /*
1974          * Match on frag_data spec 0x0008 and last 0xfff8
1975          * means M is 0 and frag-offset is > 0.
1976          * This packet is last fragment of fragmented packet.
1977          * This is not yet supported in MLX5, return appropriate
1978          * error message.
1979          */
1980         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
1981             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
1982                 return rte_flow_error_set(error, ENOTSUP,
1983                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1984                                           last, "match on last "
1985                                           "fragment not supported");
1986         /* Other range values are invalid and rejected. */
1987         return rte_flow_error_set(error, EINVAL,
1988                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1989                                   "specified range not supported");
1990 }
1991
1992 /**
1993  * Validate the pop VLAN action.
1994  *
1995  * @param[in] dev
1996  *   Pointer to the rte_eth_dev structure.
1997  * @param[in] action_flags
1998  *   Holds the actions detected until now.
1999  * @param[in] action
2000  *   Pointer to the pop vlan action.
2001  * @param[in] item_flags
2002  *   The items found in this flow rule.
2003  * @param[in] attr
2004  *   Pointer to flow attributes.
2005  * @param[out] error
2006  *   Pointer to error structure.
2007  *
2008  * @return
2009  *   0 on success, a negative errno value otherwise and rte_errno is set.
2010  */
2011 static int
2012 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2013                                  uint64_t action_flags,
2014                                  const struct rte_flow_action *action,
2015                                  uint64_t item_flags,
2016                                  const struct rte_flow_attr *attr,
2017                                  struct rte_flow_error *error)
2018 {
2019         const struct mlx5_priv *priv = dev->data->dev_private;
2020
2021         (void)action;
2022         (void)attr;
2023         if (!priv->sh->pop_vlan_action)
2024                 return rte_flow_error_set(error, ENOTSUP,
2025                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2026                                           NULL,
2027                                           "pop vlan action is not supported");
2028         if (attr->egress)
2029                 return rte_flow_error_set(error, ENOTSUP,
2030                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2031                                           NULL,
2032                                           "pop vlan action not supported for "
2033                                           "egress");
2034         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2035                 return rte_flow_error_set(error, ENOTSUP,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2037                                           "no support for multiple VLAN "
2038                                           "actions");
2039         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2040         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2041             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2042                 return rte_flow_error_set(error, ENOTSUP,
2043                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2044                                           NULL,
2045                                           "cannot pop vlan after decap without "
2046                                           "match on inner vlan in the flow");
2047         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2048         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2049             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2050                 return rte_flow_error_set(error, ENOTSUP,
2051                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2052                                           NULL,
2053                                           "cannot pop vlan without a "
2054                                           "match on (outer) vlan in the flow");
2055         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2056                 return rte_flow_error_set(error, EINVAL,
2057                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2058                                           "wrong action order, port_id should "
2059                                           "be after pop VLAN action");
2060         if (!attr->transfer && priv->representor)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2063                                           "pop vlan action for VF representor "
2064                                           "not supported on NIC table");
2065         return 0;
2066 }
2067
2068 /**
2069  * Get VLAN default info from vlan match info.
2070  *
2071  * @param[in] items
2072  *   the list of item specifications.
2073  * @param[out] vlan
2074  *   pointer VLAN info to fill to.
2075  *
2076  * @return
2077  *   0 on success, a negative errno value otherwise and rte_errno is set.
2078  */
2079 static void
2080 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2081                                   struct rte_vlan_hdr *vlan)
2082 {
2083         const struct rte_flow_item_vlan nic_mask = {
2084                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2085                                 MLX5DV_FLOW_VLAN_VID_MASK),
2086                 .inner_type = RTE_BE16(0xffff),
2087         };
2088
2089         if (items == NULL)
2090                 return;
2091         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2092                 int type = items->type;
2093
2094                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2095                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2096                         break;
2097         }
2098         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2099                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2100                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2101
2102                 /* If VLAN item in pattern doesn't contain data, return here. */
2103                 if (!vlan_v)
2104                         return;
2105                 if (!vlan_m)
2106                         vlan_m = &nic_mask;
2107                 /* Only full match values are accepted */
2108                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2109                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2110                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2111                         vlan->vlan_tci |=
2112                                 rte_be_to_cpu_16(vlan_v->tci &
2113                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2114                 }
2115                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2116                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2117                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2118                         vlan->vlan_tci |=
2119                                 rte_be_to_cpu_16(vlan_v->tci &
2120                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2121                 }
2122                 if (vlan_m->inner_type == nic_mask.inner_type)
2123                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2124                                                            vlan_m->inner_type);
2125         }
2126 }
2127
2128 /**
2129  * Validate the push VLAN action.
2130  *
2131  * @param[in] dev
2132  *   Pointer to the rte_eth_dev structure.
2133  * @param[in] action_flags
2134  *   Holds the actions detected until now.
2135  * @param[in] item_flags
2136  *   The items found in this flow rule.
2137  * @param[in] action
2138  *   Pointer to the action structure.
2139  * @param[in] attr
2140  *   Pointer to flow attributes
2141  * @param[out] error
2142  *   Pointer to error structure.
2143  *
2144  * @return
2145  *   0 on success, a negative errno value otherwise and rte_errno is set.
2146  */
2147 static int
2148 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2149                                   uint64_t action_flags,
2150                                   const struct rte_flow_item_vlan *vlan_m,
2151                                   const struct rte_flow_action *action,
2152                                   const struct rte_flow_attr *attr,
2153                                   struct rte_flow_error *error)
2154 {
2155         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2156         const struct mlx5_priv *priv = dev->data->dev_private;
2157
2158         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2159             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2160                 return rte_flow_error_set(error, EINVAL,
2161                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2162                                           "invalid vlan ethertype");
2163         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2164                 return rte_flow_error_set(error, EINVAL,
2165                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2166                                           "wrong action order, port_id should "
2167                                           "be after push VLAN");
2168         if (!attr->transfer && priv->representor)
2169                 return rte_flow_error_set(error, ENOTSUP,
2170                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2171                                           "push vlan action for VF representor "
2172                                           "not supported on NIC table");
2173         if (vlan_m &&
2174             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2175             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2176                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2177             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2178             !(mlx5_flow_find_action
2179                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2180                 return rte_flow_error_set(error, EINVAL,
2181                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2182                                           "not full match mask on VLAN PCP and "
2183                                           "there is no of_set_vlan_pcp action, "
2184                                           "push VLAN action cannot figure out "
2185                                           "PCP value");
2186         if (vlan_m &&
2187             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2188             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2189                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2190             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2191             !(mlx5_flow_find_action
2192                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2193                 return rte_flow_error_set(error, EINVAL,
2194                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2195                                           "not full match mask on VLAN VID and "
2196                                           "there is no of_set_vlan_vid action, "
2197                                           "push VLAN action cannot figure out "
2198                                           "VID value");
2199         (void)attr;
2200         return 0;
2201 }
2202
2203 /**
2204  * Validate the set VLAN PCP.
2205  *
2206  * @param[in] action_flags
2207  *   Holds the actions detected until now.
2208  * @param[in] actions
2209  *   Pointer to the list of actions remaining in the flow rule.
2210  * @param[out] error
2211  *   Pointer to error structure.
2212  *
2213  * @return
2214  *   0 on success, a negative errno value otherwise and rte_errno is set.
2215  */
2216 static int
2217 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2218                                      const struct rte_flow_action actions[],
2219                                      struct rte_flow_error *error)
2220 {
2221         const struct rte_flow_action *action = actions;
2222         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2223
2224         if (conf->vlan_pcp > 7)
2225                 return rte_flow_error_set(error, EINVAL,
2226                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2227                                           "VLAN PCP value is too big");
2228         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2229                 return rte_flow_error_set(error, ENOTSUP,
2230                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2231                                           "set VLAN PCP action must follow "
2232                                           "the push VLAN action");
2233         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2236                                           "Multiple VLAN PCP modification are "
2237                                           "not supported");
2238         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2239                 return rte_flow_error_set(error, EINVAL,
2240                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2241                                           "wrong action order, port_id should "
2242                                           "be after set VLAN PCP");
2243         return 0;
2244 }
2245
2246 /**
2247  * Validate the set VLAN VID.
2248  *
2249  * @param[in] item_flags
2250  *   Holds the items detected in this rule.
2251  * @param[in] action_flags
2252  *   Holds the actions detected until now.
2253  * @param[in] actions
2254  *   Pointer to the list of actions remaining in the flow rule.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2263                                      uint64_t action_flags,
2264                                      const struct rte_flow_action actions[],
2265                                      struct rte_flow_error *error)
2266 {
2267         const struct rte_flow_action *action = actions;
2268         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2269
2270         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2271                 return rte_flow_error_set(error, EINVAL,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "VLAN VID value is too big");
2274         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2275             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2276                 return rte_flow_error_set(error, ENOTSUP,
2277                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2278                                           "set VLAN VID action must follow push"
2279                                           " VLAN action or match on VLAN item");
2280         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2281                 return rte_flow_error_set(error, ENOTSUP,
2282                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2283                                           "Multiple VLAN VID modifications are "
2284                                           "not supported");
2285         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2286                 return rte_flow_error_set(error, EINVAL,
2287                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2288                                           "wrong action order, port_id should "
2289                                           "be after set VLAN VID");
2290         return 0;
2291 }
2292
2293 /*
2294  * Validate the FLAG action.
2295  *
2296  * @param[in] dev
2297  *   Pointer to the rte_eth_dev structure.
2298  * @param[in] action_flags
2299  *   Holds the actions detected until now.
2300  * @param[in] attr
2301  *   Pointer to flow attributes
2302  * @param[out] error
2303  *   Pointer to error structure.
2304  *
2305  * @return
2306  *   0 on success, a negative errno value otherwise and rte_errno is set.
2307  */
2308 static int
2309 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2310                              uint64_t action_flags,
2311                              const struct rte_flow_attr *attr,
2312                              struct rte_flow_error *error)
2313 {
2314         struct mlx5_priv *priv = dev->data->dev_private;
2315         struct mlx5_dev_config *config = &priv->config;
2316         int ret;
2317
2318         /* Fall back if no extended metadata register support. */
2319         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2320                 return mlx5_flow_validate_action_flag(action_flags, attr,
2321                                                       error);
2322         /* Extensive metadata mode requires registers. */
2323         if (!mlx5_flow_ext_mreg_supported(dev))
2324                 return rte_flow_error_set(error, ENOTSUP,
2325                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2326                                           "no metadata registers "
2327                                           "to support flag action");
2328         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2329                 return rte_flow_error_set(error, ENOTSUP,
2330                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2331                                           "extended metadata register"
2332                                           " isn't available");
2333         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2334         if (ret < 0)
2335                 return ret;
2336         MLX5_ASSERT(ret > 0);
2337         if (action_flags & MLX5_FLOW_ACTION_MARK)
2338                 return rte_flow_error_set(error, EINVAL,
2339                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2340                                           "can't mark and flag in same flow");
2341         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2342                 return rte_flow_error_set(error, EINVAL,
2343                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2344                                           "can't have 2 flag"
2345                                           " actions in same flow");
2346         return 0;
2347 }
2348
2349 /**
2350  * Validate MARK action.
2351  *
2352  * @param[in] dev
2353  *   Pointer to the rte_eth_dev structure.
2354  * @param[in] action
2355  *   Pointer to action.
2356  * @param[in] action_flags
2357  *   Holds the actions detected until now.
2358  * @param[in] attr
2359  *   Pointer to flow attributes
2360  * @param[out] error
2361  *   Pointer to error structure.
2362  *
2363  * @return
2364  *   0 on success, a negative errno value otherwise and rte_errno is set.
2365  */
2366 static int
2367 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2368                              const struct rte_flow_action *action,
2369                              uint64_t action_flags,
2370                              const struct rte_flow_attr *attr,
2371                              struct rte_flow_error *error)
2372 {
2373         struct mlx5_priv *priv = dev->data->dev_private;
2374         struct mlx5_dev_config *config = &priv->config;
2375         const struct rte_flow_action_mark *mark = action->conf;
2376         int ret;
2377
2378         /* Fall back if no extended metadata register support. */
2379         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2380                 return mlx5_flow_validate_action_mark(action, action_flags,
2381                                                       attr, error);
2382         /* Extensive metadata mode requires registers. */
2383         if (!mlx5_flow_ext_mreg_supported(dev))
2384                 return rte_flow_error_set(error, ENOTSUP,
2385                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2386                                           "no metadata registers "
2387                                           "to support mark action");
2388         if (!priv->sh->dv_mark_mask)
2389                 return rte_flow_error_set(error, ENOTSUP,
2390                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391                                           "extended metadata register"
2392                                           " isn't available");
2393         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2394         if (ret < 0)
2395                 return ret;
2396         MLX5_ASSERT(ret > 0);
2397         if (!mark)
2398                 return rte_flow_error_set(error, EINVAL,
2399                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2400                                           "configuration cannot be null");
2401         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2402                 return rte_flow_error_set(error, EINVAL,
2403                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2404                                           &mark->id,
2405                                           "mark id exceeds the limit");
2406         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2407                 return rte_flow_error_set(error, EINVAL,
2408                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2409                                           "can't flag and mark in same flow");
2410         if (action_flags & MLX5_FLOW_ACTION_MARK)
2411                 return rte_flow_error_set(error, EINVAL,
2412                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2413                                           "can't have 2 mark actions in same"
2414                                           " flow");
2415         return 0;
2416 }
2417
2418 /**
2419  * Validate SET_META action.
2420  *
2421  * @param[in] dev
2422  *   Pointer to the rte_eth_dev structure.
2423  * @param[in] action
2424  *   Pointer to the action structure.
2425  * @param[in] action_flags
2426  *   Holds the actions detected until now.
2427  * @param[in] attr
2428  *   Pointer to flow attributes
2429  * @param[out] error
2430  *   Pointer to error structure.
2431  *
2432  * @return
2433  *   0 on success, a negative errno value otherwise and rte_errno is set.
2434  */
2435 static int
2436 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2437                                  const struct rte_flow_action *action,
2438                                  uint64_t action_flags __rte_unused,
2439                                  const struct rte_flow_attr *attr,
2440                                  struct rte_flow_error *error)
2441 {
2442         const struct rte_flow_action_set_meta *conf;
2443         uint32_t nic_mask = UINT32_MAX;
2444         int reg;
2445
2446         if (!mlx5_flow_ext_mreg_supported(dev))
2447                 return rte_flow_error_set(error, ENOTSUP,
2448                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2449                                           "extended metadata register"
2450                                           " isn't supported");
2451         reg = flow_dv_get_metadata_reg(dev, attr, error);
2452         if (reg < 0)
2453                 return reg;
2454         if (reg == REG_NON)
2455                 return rte_flow_error_set(error, ENOTSUP,
2456                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2457                                           "unavalable extended metadata register");
2458         if (reg != REG_A && reg != REG_B) {
2459                 struct mlx5_priv *priv = dev->data->dev_private;
2460
2461                 nic_mask = priv->sh->dv_meta_mask;
2462         }
2463         if (!(action->conf))
2464                 return rte_flow_error_set(error, EINVAL,
2465                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2466                                           "configuration cannot be null");
2467         conf = (const struct rte_flow_action_set_meta *)action->conf;
2468         if (!conf->mask)
2469                 return rte_flow_error_set(error, EINVAL,
2470                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2471                                           "zero mask doesn't have any effect");
2472         if (conf->mask & ~nic_mask)
2473                 return rte_flow_error_set(error, EINVAL,
2474                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2475                                           "meta data must be within reg C0");
2476         return 0;
2477 }
2478
2479 /**
2480  * Validate SET_TAG action.
2481  *
2482  * @param[in] dev
2483  *   Pointer to the rte_eth_dev structure.
2484  * @param[in] action
2485  *   Pointer to the action structure.
2486  * @param[in] action_flags
2487  *   Holds the actions detected until now.
2488  * @param[in] attr
2489  *   Pointer to flow attributes
2490  * @param[out] error
2491  *   Pointer to error structure.
2492  *
2493  * @return
2494  *   0 on success, a negative errno value otherwise and rte_errno is set.
2495  */
2496 static int
2497 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2498                                 const struct rte_flow_action *action,
2499                                 uint64_t action_flags,
2500                                 const struct rte_flow_attr *attr,
2501                                 struct rte_flow_error *error)
2502 {
2503         const struct rte_flow_action_set_tag *conf;
2504         const uint64_t terminal_action_flags =
2505                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2506                 MLX5_FLOW_ACTION_RSS;
2507         int ret;
2508
2509         if (!mlx5_flow_ext_mreg_supported(dev))
2510                 return rte_flow_error_set(error, ENOTSUP,
2511                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2512                                           "extensive metadata register"
2513                                           " isn't supported");
2514         if (!(action->conf))
2515                 return rte_flow_error_set(error, EINVAL,
2516                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2517                                           "configuration cannot be null");
2518         conf = (const struct rte_flow_action_set_tag *)action->conf;
2519         if (!conf->mask)
2520                 return rte_flow_error_set(error, EINVAL,
2521                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2522                                           "zero mask doesn't have any effect");
2523         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2524         if (ret < 0)
2525                 return ret;
2526         if (!attr->transfer && attr->ingress &&
2527             (action_flags & terminal_action_flags))
2528                 return rte_flow_error_set(error, EINVAL,
2529                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2530                                           "set_tag has no effect"
2531                                           " with terminal actions");
2532         return 0;
2533 }
2534
2535 /**
2536  * Validate count action.
2537  *
2538  * @param[in] dev
2539  *   Pointer to rte_eth_dev structure.
2540  * @param[out] error
2541  *   Pointer to error structure.
2542  *
2543  * @return
2544  *   0 on success, a negative errno value otherwise and rte_errno is set.
2545  */
2546 static int
2547 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2548                               struct rte_flow_error *error)
2549 {
2550         struct mlx5_priv *priv = dev->data->dev_private;
2551
2552         if (!priv->config.devx)
2553                 goto notsup_err;
2554 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2555         return 0;
2556 #endif
2557 notsup_err:
2558         return rte_flow_error_set
2559                       (error, ENOTSUP,
2560                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2561                        NULL,
2562                        "count action not supported");
2563 }
2564
2565 /**
2566  * Validate the L2 encap action.
2567  *
2568  * @param[in] dev
2569  *   Pointer to the rte_eth_dev structure.
2570  * @param[in] action_flags
2571  *   Holds the actions detected until now.
2572  * @param[in] action
2573  *   Pointer to the action structure.
2574  * @param[in] attr
2575  *   Pointer to flow attributes.
2576  * @param[out] error
2577  *   Pointer to error structure.
2578  *
2579  * @return
2580  *   0 on success, a negative errno value otherwise and rte_errno is set.
2581  */
2582 static int
2583 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2584                                  uint64_t action_flags,
2585                                  const struct rte_flow_action *action,
2586                                  const struct rte_flow_attr *attr,
2587                                  struct rte_flow_error *error)
2588 {
2589         const struct mlx5_priv *priv = dev->data->dev_private;
2590
2591         if (!(action->conf))
2592                 return rte_flow_error_set(error, EINVAL,
2593                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2594                                           "configuration cannot be null");
2595         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2596                 return rte_flow_error_set(error, EINVAL,
2597                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2598                                           "can only have a single encap action "
2599                                           "in a flow");
2600         if (!attr->transfer && priv->representor)
2601                 return rte_flow_error_set(error, ENOTSUP,
2602                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2603                                           "encap action for VF representor "
2604                                           "not supported on NIC table");
2605         return 0;
2606 }
2607
2608 /**
2609  * Validate a decap action.
2610  *
2611  * @param[in] dev
2612  *   Pointer to the rte_eth_dev structure.
2613  * @param[in] action_flags
2614  *   Holds the actions detected until now.
2615  * @param[in] action
2616  *   Pointer to the action structure.
2617  * @param[in] item_flags
2618  *   Holds the items detected.
2619  * @param[in] attr
2620  *   Pointer to flow attributes
2621  * @param[out] error
2622  *   Pointer to error structure.
2623  *
2624  * @return
2625  *   0 on success, a negative errno value otherwise and rte_errno is set.
2626  */
2627 static int
2628 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2629                               uint64_t action_flags,
2630                               const struct rte_flow_action *action,
2631                               const uint64_t item_flags,
2632                               const struct rte_flow_attr *attr,
2633                               struct rte_flow_error *error)
2634 {
2635         const struct mlx5_priv *priv = dev->data->dev_private;
2636
2637         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2638             !priv->config.decap_en)
2639                 return rte_flow_error_set(error, ENOTSUP,
2640                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2641                                           "decap is not enabled");
2642         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2643                 return rte_flow_error_set(error, ENOTSUP,
2644                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2645                                           action_flags &
2646                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2647                                           "have a single decap action" : "decap "
2648                                           "after encap is not supported");
2649         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2650                 return rte_flow_error_set(error, EINVAL,
2651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2652                                           "can't have decap action after"
2653                                           " modify action");
2654         if (attr->egress)
2655                 return rte_flow_error_set(error, ENOTSUP,
2656                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2657                                           NULL,
2658                                           "decap action not supported for "
2659                                           "egress");
2660         if (!attr->transfer && priv->representor)
2661                 return rte_flow_error_set(error, ENOTSUP,
2662                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2663                                           "decap action for VF representor "
2664                                           "not supported on NIC table");
2665         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
2666             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
2667                 return rte_flow_error_set(error, ENOTSUP,
2668                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2669                                 "VXLAN item should be present for VXLAN decap");
2670         return 0;
2671 }
2672
2673 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2674
2675 /**
2676  * Validate the raw encap and decap actions.
2677  *
2678  * @param[in] dev
2679  *   Pointer to the rte_eth_dev structure.
2680  * @param[in] decap
2681  *   Pointer to the decap action.
2682  * @param[in] encap
2683  *   Pointer to the encap action.
2684  * @param[in] attr
2685  *   Pointer to flow attributes
2686  * @param[in/out] action_flags
2687  *   Holds the actions detected until now.
2688  * @param[out] actions_n
2689  *   pointer to the number of actions counter.
2690  * @param[in] action
2691  *   Pointer to the action structure.
2692  * @param[in] item_flags
2693  *   Holds the items detected.
2694  * @param[out] error
2695  *   Pointer to error structure.
2696  *
2697  * @return
2698  *   0 on success, a negative errno value otherwise and rte_errno is set.
2699  */
2700 static int
2701 flow_dv_validate_action_raw_encap_decap
2702         (struct rte_eth_dev *dev,
2703          const struct rte_flow_action_raw_decap *decap,
2704          const struct rte_flow_action_raw_encap *encap,
2705          const struct rte_flow_attr *attr, uint64_t *action_flags,
2706          int *actions_n, const struct rte_flow_action *action,
2707          uint64_t item_flags, struct rte_flow_error *error)
2708 {
2709         const struct mlx5_priv *priv = dev->data->dev_private;
2710         int ret;
2711
2712         if (encap && (!encap->size || !encap->data))
2713                 return rte_flow_error_set(error, EINVAL,
2714                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2715                                           "raw encap data cannot be empty");
2716         if (decap && encap) {
2717                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2718                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2719                         /* L3 encap. */
2720                         decap = NULL;
2721                 else if (encap->size <=
2722                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2723                            decap->size >
2724                            MLX5_ENCAPSULATION_DECISION_SIZE)
2725                         /* L3 decap. */
2726                         encap = NULL;
2727                 else if (encap->size >
2728                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2729                            decap->size >
2730                            MLX5_ENCAPSULATION_DECISION_SIZE)
2731                         /* 2 L2 actions: encap and decap. */
2732                         ;
2733                 else
2734                         return rte_flow_error_set(error,
2735                                 ENOTSUP,
2736                                 RTE_FLOW_ERROR_TYPE_ACTION,
2737                                 NULL, "unsupported too small "
2738                                 "raw decap and too small raw "
2739                                 "encap combination");
2740         }
2741         if (decap) {
2742                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
2743                                                     item_flags, attr, error);
2744                 if (ret < 0)
2745                         return ret;
2746                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2747                 ++(*actions_n);
2748         }
2749         if (encap) {
2750                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2751                         return rte_flow_error_set(error, ENOTSUP,
2752                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2753                                                   NULL,
2754                                                   "small raw encap size");
2755                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2756                         return rte_flow_error_set(error, EINVAL,
2757                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2758                                                   NULL,
2759                                                   "more than one encap action");
2760                 if (!attr->transfer && priv->representor)
2761                         return rte_flow_error_set
2762                                         (error, ENOTSUP,
2763                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2764                                          "encap action for VF representor "
2765                                          "not supported on NIC table");
2766                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2767                 ++(*actions_n);
2768         }
2769         return 0;
2770 }
2771
2772 /**
2773  * Match encap_decap resource.
2774  *
2775  * @param list
2776  *   Pointer to the hash list.
2777  * @param entry
2778  *   Pointer to exist resource entry object.
2779  * @param key
2780  *   Key of the new entry.
2781  * @param ctx_cb
2782  *   Pointer to new encap_decap resource.
2783  *
2784  * @return
2785  *   0 on matching, none-zero otherwise.
2786  */
2787 int
2788 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2789                              struct mlx5_hlist_entry *entry,
2790                              uint64_t key __rte_unused, void *cb_ctx)
2791 {
2792         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2793         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2794         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2795
2796         cache_resource = container_of(entry,
2797                                       struct mlx5_flow_dv_encap_decap_resource,
2798                                       entry);
2799         if (resource->reformat_type == cache_resource->reformat_type &&
2800             resource->ft_type == cache_resource->ft_type &&
2801             resource->flags == cache_resource->flags &&
2802             resource->size == cache_resource->size &&
2803             !memcmp((const void *)resource->buf,
2804                     (const void *)cache_resource->buf,
2805                     resource->size))
2806                 return 0;
2807         return -1;
2808 }
2809
2810 /**
2811  * Allocate encap_decap resource.
2812  *
2813  * @param list
2814  *   Pointer to the hash list.
2815  * @param entry
2816  *   Pointer to exist resource entry object.
2817  * @param ctx_cb
2818  *   Pointer to new encap_decap resource.
2819  *
2820  * @return
2821  *   0 on matching, none-zero otherwise.
2822  */
2823 struct mlx5_hlist_entry *
2824 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2825                               uint64_t key __rte_unused,
2826                               void *cb_ctx)
2827 {
2828         struct mlx5_dev_ctx_shared *sh = list->ctx;
2829         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2830         struct mlx5dv_dr_domain *domain;
2831         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2832         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2833         uint32_t idx;
2834         int ret;
2835
2836         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2837                 domain = sh->fdb_domain;
2838         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2839                 domain = sh->rx_domain;
2840         else
2841                 domain = sh->tx_domain;
2842         /* Register new encap/decap resource. */
2843         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2844                                        &idx);
2845         if (!cache_resource) {
2846                 rte_flow_error_set(ctx->error, ENOMEM,
2847                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2848                                    "cannot allocate resource memory");
2849                 return NULL;
2850         }
2851         *cache_resource = *resource;
2852         cache_resource->idx = idx;
2853         ret = mlx5_flow_os_create_flow_action_packet_reformat
2854                                         (sh->ctx, domain, cache_resource,
2855                                          &cache_resource->action);
2856         if (ret) {
2857                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2858                 rte_flow_error_set(ctx->error, ENOMEM,
2859                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2860                                    NULL, "cannot create action");
2861                 return NULL;
2862         }
2863
2864         return &cache_resource->entry;
2865 }
2866
2867 /**
2868  * Find existing encap/decap resource or create and register a new one.
2869  *
2870  * @param[in, out] dev
2871  *   Pointer to rte_eth_dev structure.
2872  * @param[in, out] resource
2873  *   Pointer to encap/decap resource.
2874  * @parm[in, out] dev_flow
2875  *   Pointer to the dev_flow.
2876  * @param[out] error
2877  *   pointer to error structure.
2878  *
2879  * @return
2880  *   0 on success otherwise -errno and errno is set.
2881  */
2882 static int
2883 flow_dv_encap_decap_resource_register
2884                         (struct rte_eth_dev *dev,
2885                          struct mlx5_flow_dv_encap_decap_resource *resource,
2886                          struct mlx5_flow *dev_flow,
2887                          struct rte_flow_error *error)
2888 {
2889         struct mlx5_priv *priv = dev->data->dev_private;
2890         struct mlx5_dev_ctx_shared *sh = priv->sh;
2891         struct mlx5_hlist_entry *entry;
2892         union {
2893                 struct {
2894                         uint32_t ft_type:8;
2895                         uint32_t refmt_type:8;
2896                         /*
2897                          * Header reformat actions can be shared between
2898                          * non-root tables. One bit to indicate non-root
2899                          * table or not.
2900                          */
2901                         uint32_t is_root:1;
2902                         uint32_t reserve:15;
2903                 };
2904                 uint32_t v32;
2905         } encap_decap_key = {
2906                 {
2907                         .ft_type = resource->ft_type,
2908                         .refmt_type = resource->reformat_type,
2909                         .is_root = !!dev_flow->dv.group,
2910                         .reserve = 0,
2911                 }
2912         };
2913         struct mlx5_flow_cb_ctx ctx = {
2914                 .error = error,
2915                 .data = resource,
2916         };
2917         uint64_t key64;
2918
2919         resource->flags = dev_flow->dv.group ? 0 : 1;
2920         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
2921                                  sizeof(encap_decap_key.v32), 0);
2922         if (resource->reformat_type !=
2923             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
2924             resource->size)
2925                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
2926         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
2927         if (!entry)
2928                 return -rte_errno;
2929         resource = container_of(entry, typeof(*resource), entry);
2930         dev_flow->dv.encap_decap = resource;
2931         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2932         return 0;
2933 }
2934
2935 /**
2936  * Find existing table jump resource or create and register a new one.
2937  *
2938  * @param[in, out] dev
2939  *   Pointer to rte_eth_dev structure.
2940  * @param[in, out] tbl
2941  *   Pointer to flow table resource.
2942  * @parm[in, out] dev_flow
2943  *   Pointer to the dev_flow.
2944  * @param[out] error
2945  *   pointer to error structure.
2946  *
2947  * @return
2948  *   0 on success otherwise -errno and errno is set.
2949  */
2950 static int
2951 flow_dv_jump_tbl_resource_register
2952                         (struct rte_eth_dev *dev __rte_unused,
2953                          struct mlx5_flow_tbl_resource *tbl,
2954                          struct mlx5_flow *dev_flow,
2955                          struct rte_flow_error *error __rte_unused)
2956 {
2957         struct mlx5_flow_tbl_data_entry *tbl_data =
2958                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2959
2960         MLX5_ASSERT(tbl);
2961         MLX5_ASSERT(tbl_data->jump.action);
2962         dev_flow->handle->rix_jump = tbl_data->idx;
2963         dev_flow->dv.jump = &tbl_data->jump;
2964         return 0;
2965 }
2966
2967 int
2968 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
2969                          struct mlx5_cache_entry *entry, void *cb_ctx)
2970 {
2971         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2972         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2973         struct mlx5_flow_dv_port_id_action_resource *res =
2974                         container_of(entry, typeof(*res), entry);
2975
2976         return ref->port_id != res->port_id;
2977 }
2978
2979 struct mlx5_cache_entry *
2980 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
2981                           struct mlx5_cache_entry *entry __rte_unused,
2982                           void *cb_ctx)
2983 {
2984         struct mlx5_dev_ctx_shared *sh = list->ctx;
2985         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2986         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
2987         struct mlx5_flow_dv_port_id_action_resource *cache;
2988         uint32_t idx;
2989         int ret;
2990
2991         /* Register new port id action resource. */
2992         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
2993         if (!cache) {
2994                 rte_flow_error_set(ctx->error, ENOMEM,
2995                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2996                                    "cannot allocate port_id action cache memory");
2997                 return NULL;
2998         }
2999         *cache = *ref;
3000         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3001                                                         ref->port_id,
3002                                                         &cache->action);
3003         if (ret) {
3004                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3005                 rte_flow_error_set(ctx->error, ENOMEM,
3006                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3007                                    "cannot create action");
3008                 return NULL;
3009         }
3010         return &cache->entry;
3011 }
3012
3013 /**
3014  * Find existing table port ID resource or create and register a new one.
3015  *
3016  * @param[in, out] dev
3017  *   Pointer to rte_eth_dev structure.
3018  * @param[in, out] resource
3019  *   Pointer to port ID action resource.
3020  * @parm[in, out] dev_flow
3021  *   Pointer to the dev_flow.
3022  * @param[out] error
3023  *   pointer to error structure.
3024  *
3025  * @return
3026  *   0 on success otherwise -errno and errno is set.
3027  */
3028 static int
3029 flow_dv_port_id_action_resource_register
3030                         (struct rte_eth_dev *dev,
3031                          struct mlx5_flow_dv_port_id_action_resource *resource,
3032                          struct mlx5_flow *dev_flow,
3033                          struct rte_flow_error *error)
3034 {
3035         struct mlx5_priv *priv = dev->data->dev_private;
3036         struct mlx5_cache_entry *entry;
3037         struct mlx5_flow_dv_port_id_action_resource *cache;
3038         struct mlx5_flow_cb_ctx ctx = {
3039                 .error = error,
3040                 .data = resource,
3041         };
3042
3043         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3044         if (!entry)
3045                 return -rte_errno;
3046         cache = container_of(entry, typeof(*cache), entry);
3047         dev_flow->dv.port_id_action = cache;
3048         dev_flow->handle->rix_port_id_action = cache->idx;
3049         return 0;
3050 }
3051
3052 int
3053 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3054                          struct mlx5_cache_entry *entry, void *cb_ctx)
3055 {
3056         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3057         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3058         struct mlx5_flow_dv_push_vlan_action_resource *res =
3059                         container_of(entry, typeof(*res), entry);
3060
3061         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3062 }
3063
3064 struct mlx5_cache_entry *
3065 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3066                           struct mlx5_cache_entry *entry __rte_unused,
3067                           void *cb_ctx)
3068 {
3069         struct mlx5_dev_ctx_shared *sh = list->ctx;
3070         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3071         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3072         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3073         struct mlx5dv_dr_domain *domain;
3074         uint32_t idx;
3075         int ret;
3076
3077         /* Register new port id action resource. */
3078         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3079         if (!cache) {
3080                 rte_flow_error_set(ctx->error, ENOMEM,
3081                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3082                                    "cannot allocate push_vlan action cache memory");
3083                 return NULL;
3084         }
3085         *cache = *ref;
3086         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3087                 domain = sh->fdb_domain;
3088         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3089                 domain = sh->rx_domain;
3090         else
3091                 domain = sh->tx_domain;
3092         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3093                                                         &cache->action);
3094         if (ret) {
3095                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3096                 rte_flow_error_set(ctx->error, ENOMEM,
3097                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3098                                    "cannot create push vlan action");
3099                 return NULL;
3100         }
3101         return &cache->entry;
3102 }
3103
3104 /**
3105  * Find existing push vlan resource or create and register a new one.
3106  *
3107  * @param [in, out] dev
3108  *   Pointer to rte_eth_dev structure.
3109  * @param[in, out] resource
3110  *   Pointer to port ID action resource.
3111  * @parm[in, out] dev_flow
3112  *   Pointer to the dev_flow.
3113  * @param[out] error
3114  *   pointer to error structure.
3115  *
3116  * @return
3117  *   0 on success otherwise -errno and errno is set.
3118  */
3119 static int
3120 flow_dv_push_vlan_action_resource_register
3121                        (struct rte_eth_dev *dev,
3122                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3123                         struct mlx5_flow *dev_flow,
3124                         struct rte_flow_error *error)
3125 {
3126         struct mlx5_priv *priv = dev->data->dev_private;
3127         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3128         struct mlx5_cache_entry *entry;
3129         struct mlx5_flow_cb_ctx ctx = {
3130                 .error = error,
3131                 .data = resource,
3132         };
3133
3134         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3135         if (!entry)
3136                 return -rte_errno;
3137         cache = container_of(entry, typeof(*cache), entry);
3138
3139         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3140         dev_flow->dv.push_vlan_res = cache;
3141         return 0;
3142 }
3143
3144 /**
3145  * Get the size of specific rte_flow_item_type hdr size
3146  *
3147  * @param[in] item_type
3148  *   Tested rte_flow_item_type.
3149  *
3150  * @return
3151  *   sizeof struct item_type, 0 if void or irrelevant.
3152  */
3153 static size_t
3154 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3155 {
3156         size_t retval;
3157
3158         switch (item_type) {
3159         case RTE_FLOW_ITEM_TYPE_ETH:
3160                 retval = sizeof(struct rte_ether_hdr);
3161                 break;
3162         case RTE_FLOW_ITEM_TYPE_VLAN:
3163                 retval = sizeof(struct rte_vlan_hdr);
3164                 break;
3165         case RTE_FLOW_ITEM_TYPE_IPV4:
3166                 retval = sizeof(struct rte_ipv4_hdr);
3167                 break;
3168         case RTE_FLOW_ITEM_TYPE_IPV6:
3169                 retval = sizeof(struct rte_ipv6_hdr);
3170                 break;
3171         case RTE_FLOW_ITEM_TYPE_UDP:
3172                 retval = sizeof(struct rte_udp_hdr);
3173                 break;
3174         case RTE_FLOW_ITEM_TYPE_TCP:
3175                 retval = sizeof(struct rte_tcp_hdr);
3176                 break;
3177         case RTE_FLOW_ITEM_TYPE_VXLAN:
3178         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3179                 retval = sizeof(struct rte_vxlan_hdr);
3180                 break;
3181         case RTE_FLOW_ITEM_TYPE_GRE:
3182         case RTE_FLOW_ITEM_TYPE_NVGRE:
3183                 retval = sizeof(struct rte_gre_hdr);
3184                 break;
3185         case RTE_FLOW_ITEM_TYPE_MPLS:
3186                 retval = sizeof(struct rte_mpls_hdr);
3187                 break;
3188         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3189         default:
3190                 retval = 0;
3191                 break;
3192         }
3193         return retval;
3194 }
3195
3196 #define MLX5_ENCAP_IPV4_VERSION         0x40
3197 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3198 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3199 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3200 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3201 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3202 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3203
3204 /**
3205  * Convert the encap action data from list of rte_flow_item to raw buffer
3206  *
3207  * @param[in] items
3208  *   Pointer to rte_flow_item objects list.
3209  * @param[out] buf
3210  *   Pointer to the output buffer.
3211  * @param[out] size
3212  *   Pointer to the output buffer size.
3213  * @param[out] error
3214  *   Pointer to the error structure.
3215  *
3216  * @return
3217  *   0 on success, a negative errno value otherwise and rte_errno is set.
3218  */
3219 static int
3220 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3221                            size_t *size, struct rte_flow_error *error)
3222 {
3223         struct rte_ether_hdr *eth = NULL;
3224         struct rte_vlan_hdr *vlan = NULL;
3225         struct rte_ipv4_hdr *ipv4 = NULL;
3226         struct rte_ipv6_hdr *ipv6 = NULL;
3227         struct rte_udp_hdr *udp = NULL;
3228         struct rte_vxlan_hdr *vxlan = NULL;
3229         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3230         struct rte_gre_hdr *gre = NULL;
3231         size_t len;
3232         size_t temp_size = 0;
3233
3234         if (!items)
3235                 return rte_flow_error_set(error, EINVAL,
3236                                           RTE_FLOW_ERROR_TYPE_ACTION,
3237                                           NULL, "invalid empty data");
3238         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3239                 len = flow_dv_get_item_hdr_len(items->type);
3240                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3241                         return rte_flow_error_set(error, EINVAL,
3242                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3243                                                   (void *)items->type,
3244                                                   "items total size is too big"
3245                                                   " for encap action");
3246                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3247                 switch (items->type) {
3248                 case RTE_FLOW_ITEM_TYPE_ETH:
3249                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3250                         break;
3251                 case RTE_FLOW_ITEM_TYPE_VLAN:
3252                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3253                         if (!eth)
3254                                 return rte_flow_error_set(error, EINVAL,
3255                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3256                                                 (void *)items->type,
3257                                                 "eth header not found");
3258                         if (!eth->ether_type)
3259                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3260                         break;
3261                 case RTE_FLOW_ITEM_TYPE_IPV4:
3262                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3263                         if (!vlan && !eth)
3264                                 return rte_flow_error_set(error, EINVAL,
3265                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3266                                                 (void *)items->type,
3267                                                 "neither eth nor vlan"
3268                                                 " header found");
3269                         if (vlan && !vlan->eth_proto)
3270                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3271                         else if (eth && !eth->ether_type)
3272                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3273                         if (!ipv4->version_ihl)
3274                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3275                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3276                         if (!ipv4->time_to_live)
3277                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3278                         break;
3279                 case RTE_FLOW_ITEM_TYPE_IPV6:
3280                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3281                         if (!vlan && !eth)
3282                                 return rte_flow_error_set(error, EINVAL,
3283                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3284                                                 (void *)items->type,
3285                                                 "neither eth nor vlan"
3286                                                 " header found");
3287                         if (vlan && !vlan->eth_proto)
3288                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3289                         else if (eth && !eth->ether_type)
3290                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3291                         if (!ipv6->vtc_flow)
3292                                 ipv6->vtc_flow =
3293                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3294                         if (!ipv6->hop_limits)
3295                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3296                         break;
3297                 case RTE_FLOW_ITEM_TYPE_UDP:
3298                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3299                         if (!ipv4 && !ipv6)
3300                                 return rte_flow_error_set(error, EINVAL,
3301                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3302                                                 (void *)items->type,
3303                                                 "ip header not found");
3304                         if (ipv4 && !ipv4->next_proto_id)
3305                                 ipv4->next_proto_id = IPPROTO_UDP;
3306                         else if (ipv6 && !ipv6->proto)
3307                                 ipv6->proto = IPPROTO_UDP;
3308                         break;
3309                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3310                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3311                         if (!udp)
3312                                 return rte_flow_error_set(error, EINVAL,
3313                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3314                                                 (void *)items->type,
3315                                                 "udp header not found");
3316                         if (!udp->dst_port)
3317                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3318                         if (!vxlan->vx_flags)
3319                                 vxlan->vx_flags =
3320                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3321                         break;
3322                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3323                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3324                         if (!udp)
3325                                 return rte_flow_error_set(error, EINVAL,
3326                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3327                                                 (void *)items->type,
3328                                                 "udp header not found");
3329                         if (!vxlan_gpe->proto)
3330                                 return rte_flow_error_set(error, EINVAL,
3331                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3332                                                 (void *)items->type,
3333                                                 "next protocol not found");
3334                         if (!udp->dst_port)
3335                                 udp->dst_port =
3336                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3337                         if (!vxlan_gpe->vx_flags)
3338                                 vxlan_gpe->vx_flags =
3339                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3340                         break;
3341                 case RTE_FLOW_ITEM_TYPE_GRE:
3342                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3343                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3344                         if (!gre->proto)
3345                                 return rte_flow_error_set(error, EINVAL,
3346                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3347                                                 (void *)items->type,
3348                                                 "next protocol not found");
3349                         if (!ipv4 && !ipv6)
3350                                 return rte_flow_error_set(error, EINVAL,
3351                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3352                                                 (void *)items->type,
3353                                                 "ip header not found");
3354                         if (ipv4 && !ipv4->next_proto_id)
3355                                 ipv4->next_proto_id = IPPROTO_GRE;
3356                         else if (ipv6 && !ipv6->proto)
3357                                 ipv6->proto = IPPROTO_GRE;
3358                         break;
3359                 case RTE_FLOW_ITEM_TYPE_VOID:
3360                         break;
3361                 default:
3362                         return rte_flow_error_set(error, EINVAL,
3363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3364                                                   (void *)items->type,
3365                                                   "unsupported item type");
3366                         break;
3367                 }
3368                 temp_size += len;
3369         }
3370         *size = temp_size;
3371         return 0;
3372 }
3373
3374 static int
3375 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3376 {
3377         struct rte_ether_hdr *eth = NULL;
3378         struct rte_vlan_hdr *vlan = NULL;
3379         struct rte_ipv6_hdr *ipv6 = NULL;
3380         struct rte_udp_hdr *udp = NULL;
3381         char *next_hdr;
3382         uint16_t proto;
3383
3384         eth = (struct rte_ether_hdr *)data;
3385         next_hdr = (char *)(eth + 1);
3386         proto = RTE_BE16(eth->ether_type);
3387
3388         /* VLAN skipping */
3389         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3390                 vlan = (struct rte_vlan_hdr *)next_hdr;
3391                 proto = RTE_BE16(vlan->eth_proto);
3392                 next_hdr += sizeof(struct rte_vlan_hdr);
3393         }
3394
3395         /* HW calculates IPv4 csum. no need to proceed */
3396         if (proto == RTE_ETHER_TYPE_IPV4)
3397                 return 0;
3398
3399         /* non IPv4/IPv6 header. not supported */
3400         if (proto != RTE_ETHER_TYPE_IPV6) {
3401                 return rte_flow_error_set(error, ENOTSUP,
3402                                           RTE_FLOW_ERROR_TYPE_ACTION,
3403                                           NULL, "Cannot offload non IPv4/IPv6");
3404         }
3405
3406         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3407
3408         /* ignore non UDP */
3409         if (ipv6->proto != IPPROTO_UDP)
3410                 return 0;
3411
3412         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3413         udp->dgram_cksum = 0;
3414
3415         return 0;
3416 }
3417
3418 /**
3419  * Convert L2 encap action to DV specification.
3420  *
3421  * @param[in] dev
3422  *   Pointer to rte_eth_dev structure.
3423  * @param[in] action
3424  *   Pointer to action structure.
3425  * @param[in, out] dev_flow
3426  *   Pointer to the mlx5_flow.
3427  * @param[in] transfer
3428  *   Mark if the flow is E-Switch flow.
3429  * @param[out] error
3430  *   Pointer to the error structure.
3431  *
3432  * @return
3433  *   0 on success, a negative errno value otherwise and rte_errno is set.
3434  */
3435 static int
3436 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3437                                const struct rte_flow_action *action,
3438                                struct mlx5_flow *dev_flow,
3439                                uint8_t transfer,
3440                                struct rte_flow_error *error)
3441 {
3442         const struct rte_flow_item *encap_data;
3443         const struct rte_flow_action_raw_encap *raw_encap_data;
3444         struct mlx5_flow_dv_encap_decap_resource res = {
3445                 .reformat_type =
3446                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3447                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3448                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3449         };
3450
3451         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3452                 raw_encap_data =
3453                         (const struct rte_flow_action_raw_encap *)action->conf;
3454                 res.size = raw_encap_data->size;
3455                 memcpy(res.buf, raw_encap_data->data, res.size);
3456         } else {
3457                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3458                         encap_data =
3459                                 ((const struct rte_flow_action_vxlan_encap *)
3460                                                 action->conf)->definition;
3461                 else
3462                         encap_data =
3463                                 ((const struct rte_flow_action_nvgre_encap *)
3464                                                 action->conf)->definition;
3465                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3466                                                &res.size, error))
3467                         return -rte_errno;
3468         }
3469         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3470                 return -rte_errno;
3471         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3472                 return rte_flow_error_set(error, EINVAL,
3473                                           RTE_FLOW_ERROR_TYPE_ACTION,
3474                                           NULL, "can't create L2 encap action");
3475         return 0;
3476 }
3477
3478 /**
3479  * Convert L2 decap action to DV specification.
3480  *
3481  * @param[in] dev
3482  *   Pointer to rte_eth_dev structure.
3483  * @param[in, out] dev_flow
3484  *   Pointer to the mlx5_flow.
3485  * @param[in] transfer
3486  *   Mark if the flow is E-Switch flow.
3487  * @param[out] error
3488  *   Pointer to the error structure.
3489  *
3490  * @return
3491  *   0 on success, a negative errno value otherwise and rte_errno is set.
3492  */
3493 static int
3494 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3495                                struct mlx5_flow *dev_flow,
3496                                uint8_t transfer,
3497                                struct rte_flow_error *error)
3498 {
3499         struct mlx5_flow_dv_encap_decap_resource res = {
3500                 .size = 0,
3501                 .reformat_type =
3502                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3503                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3504                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3505         };
3506
3507         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3508                 return rte_flow_error_set(error, EINVAL,
3509                                           RTE_FLOW_ERROR_TYPE_ACTION,
3510                                           NULL, "can't create L2 decap action");
3511         return 0;
3512 }
3513
3514 /**
3515  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3516  *
3517  * @param[in] dev
3518  *   Pointer to rte_eth_dev structure.
3519  * @param[in] action
3520  *   Pointer to action structure.
3521  * @param[in, out] dev_flow
3522  *   Pointer to the mlx5_flow.
3523  * @param[in] attr
3524  *   Pointer to the flow attributes.
3525  * @param[out] error
3526  *   Pointer to the error structure.
3527  *
3528  * @return
3529  *   0 on success, a negative errno value otherwise and rte_errno is set.
3530  */
3531 static int
3532 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3533                                 const struct rte_flow_action *action,
3534                                 struct mlx5_flow *dev_flow,
3535                                 const struct rte_flow_attr *attr,
3536                                 struct rte_flow_error *error)
3537 {
3538         const struct rte_flow_action_raw_encap *encap_data;
3539         struct mlx5_flow_dv_encap_decap_resource res;
3540
3541         memset(&res, 0, sizeof(res));
3542         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3543         res.size = encap_data->size;
3544         memcpy(res.buf, encap_data->data, res.size);
3545         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3546                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3547                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3548         if (attr->transfer)
3549                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3550         else
3551                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3552                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3553         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3554                 return rte_flow_error_set(error, EINVAL,
3555                                           RTE_FLOW_ERROR_TYPE_ACTION,
3556                                           NULL, "can't create encap action");
3557         return 0;
3558 }
3559
3560 /**
3561  * Create action push VLAN.
3562  *
3563  * @param[in] dev
3564  *   Pointer to rte_eth_dev structure.
3565  * @param[in] attr
3566  *   Pointer to the flow attributes.
3567  * @param[in] vlan
3568  *   Pointer to the vlan to push to the Ethernet header.
3569  * @param[in, out] dev_flow
3570  *   Pointer to the mlx5_flow.
3571  * @param[out] error
3572  *   Pointer to the error structure.
3573  *
3574  * @return
3575  *   0 on success, a negative errno value otherwise and rte_errno is set.
3576  */
3577 static int
3578 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3579                                 const struct rte_flow_attr *attr,
3580                                 const struct rte_vlan_hdr *vlan,
3581                                 struct mlx5_flow *dev_flow,
3582                                 struct rte_flow_error *error)
3583 {
3584         struct mlx5_flow_dv_push_vlan_action_resource res;
3585
3586         memset(&res, 0, sizeof(res));
3587         res.vlan_tag =
3588                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3589                                  vlan->vlan_tci);
3590         if (attr->transfer)
3591                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3592         else
3593                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3594                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3595         return flow_dv_push_vlan_action_resource_register
3596                                             (dev, &res, dev_flow, error);
3597 }
3598
3599 static int fdb_mirror;
3600
3601 /**
3602  * Validate the modify-header actions.
3603  *
3604  * @param[in] action_flags
3605  *   Holds the actions detected until now.
3606  * @param[in] action
3607  *   Pointer to the modify action.
3608  * @param[out] error
3609  *   Pointer to error structure.
3610  *
3611  * @return
3612  *   0 on success, a negative errno value otherwise and rte_errno is set.
3613  */
3614 static int
3615 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3616                                    const struct rte_flow_action *action,
3617                                    struct rte_flow_error *error)
3618 {
3619         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3620                 return rte_flow_error_set(error, EINVAL,
3621                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3622                                           NULL, "action configuration not set");
3623         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3624                 return rte_flow_error_set(error, EINVAL,
3625                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3626                                           "can't have encap action before"
3627                                           " modify action");
3628         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3629                 return rte_flow_error_set(error, EINVAL,
3630                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3631                                           "can't support sample action before"
3632                                           " modify action for E-Switch"
3633                                           " mirroring");
3634         return 0;
3635 }
3636
3637 /**
3638  * Validate the modify-header MAC address actions.
3639  *
3640  * @param[in] action_flags
3641  *   Holds the actions detected until now.
3642  * @param[in] action
3643  *   Pointer to the modify action.
3644  * @param[in] item_flags
3645  *   Holds the items detected.
3646  * @param[out] error
3647  *   Pointer to error structure.
3648  *
3649  * @return
3650  *   0 on success, a negative errno value otherwise and rte_errno is set.
3651  */
3652 static int
3653 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3654                                    const struct rte_flow_action *action,
3655                                    const uint64_t item_flags,
3656                                    struct rte_flow_error *error)
3657 {
3658         int ret = 0;
3659
3660         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3661         if (!ret) {
3662                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3663                         return rte_flow_error_set(error, EINVAL,
3664                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3665                                                   NULL,
3666                                                   "no L2 item in pattern");
3667         }
3668         return ret;
3669 }
3670
3671 /**
3672  * Validate the modify-header IPv4 address actions.
3673  *
3674  * @param[in] action_flags
3675  *   Holds the actions detected until now.
3676  * @param[in] action
3677  *   Pointer to the modify action.
3678  * @param[in] item_flags
3679  *   Holds the items detected.
3680  * @param[out] error
3681  *   Pointer to error structure.
3682  *
3683  * @return
3684  *   0 on success, a negative errno value otherwise and rte_errno is set.
3685  */
3686 static int
3687 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3688                                     const struct rte_flow_action *action,
3689                                     const uint64_t item_flags,
3690                                     struct rte_flow_error *error)
3691 {
3692         int ret = 0;
3693         uint64_t layer;
3694
3695         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3696         if (!ret) {
3697                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3698                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3699                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3700                 if (!(item_flags & layer))
3701                         return rte_flow_error_set(error, EINVAL,
3702                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3703                                                   NULL,
3704                                                   "no ipv4 item in pattern");
3705         }
3706         return ret;
3707 }
3708
3709 /**
3710  * Validate the modify-header IPv6 address actions.
3711  *
3712  * @param[in] action_flags
3713  *   Holds the actions detected until now.
3714  * @param[in] action
3715  *   Pointer to the modify action.
3716  * @param[in] item_flags
3717  *   Holds the items detected.
3718  * @param[out] error
3719  *   Pointer to error structure.
3720  *
3721  * @return
3722  *   0 on success, a negative errno value otherwise and rte_errno is set.
3723  */
3724 static int
3725 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3726                                     const struct rte_flow_action *action,
3727                                     const uint64_t item_flags,
3728                                     struct rte_flow_error *error)
3729 {
3730         int ret = 0;
3731         uint64_t layer;
3732
3733         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3734         if (!ret) {
3735                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3736                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3737                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3738                 if (!(item_flags & layer))
3739                         return rte_flow_error_set(error, EINVAL,
3740                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3741                                                   NULL,
3742                                                   "no ipv6 item in pattern");
3743         }
3744         return ret;
3745 }
3746
3747 /**
3748  * Validate the modify-header TP actions.
3749  *
3750  * @param[in] action_flags
3751  *   Holds the actions detected until now.
3752  * @param[in] action
3753  *   Pointer to the modify action.
3754  * @param[in] item_flags
3755  *   Holds the items detected.
3756  * @param[out] error
3757  *   Pointer to error structure.
3758  *
3759  * @return
3760  *   0 on success, a negative errno value otherwise and rte_errno is set.
3761  */
3762 static int
3763 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3764                                   const struct rte_flow_action *action,
3765                                   const uint64_t item_flags,
3766                                   struct rte_flow_error *error)
3767 {
3768         int ret = 0;
3769         uint64_t layer;
3770
3771         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3772         if (!ret) {
3773                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3774                                  MLX5_FLOW_LAYER_INNER_L4 :
3775                                  MLX5_FLOW_LAYER_OUTER_L4;
3776                 if (!(item_flags & layer))
3777                         return rte_flow_error_set(error, EINVAL,
3778                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3779                                                   NULL, "no transport layer "
3780                                                   "in pattern");
3781         }
3782         return ret;
3783 }
3784
3785 /**
3786  * Validate the modify-header actions of increment/decrement
3787  * TCP Sequence-number.
3788  *
3789  * @param[in] action_flags
3790  *   Holds the actions detected until now.
3791  * @param[in] action
3792  *   Pointer to the modify action.
3793  * @param[in] item_flags
3794  *   Holds the items detected.
3795  * @param[out] error
3796  *   Pointer to error structure.
3797  *
3798  * @return
3799  *   0 on success, a negative errno value otherwise and rte_errno is set.
3800  */
3801 static int
3802 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3803                                        const struct rte_flow_action *action,
3804                                        const uint64_t item_flags,
3805                                        struct rte_flow_error *error)
3806 {
3807         int ret = 0;
3808         uint64_t layer;
3809
3810         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3811         if (!ret) {
3812                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3813                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3814                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3815                 if (!(item_flags & layer))
3816                         return rte_flow_error_set(error, EINVAL,
3817                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3818                                                   NULL, "no TCP item in"
3819                                                   " pattern");
3820                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3821                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3822                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3823                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3824                         return rte_flow_error_set(error, EINVAL,
3825                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3826                                                   NULL,
3827                                                   "cannot decrease and increase"
3828                                                   " TCP sequence number"
3829                                                   " at the same time");
3830         }
3831         return ret;
3832 }
3833
3834 /**
3835  * Validate the modify-header actions of increment/decrement
3836  * TCP Acknowledgment number.
3837  *
3838  * @param[in] action_flags
3839  *   Holds the actions detected until now.
3840  * @param[in] action
3841  *   Pointer to the modify action.
3842  * @param[in] item_flags
3843  *   Holds the items detected.
3844  * @param[out] error
3845  *   Pointer to error structure.
3846  *
3847  * @return
3848  *   0 on success, a negative errno value otherwise and rte_errno is set.
3849  */
3850 static int
3851 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3852                                        const struct rte_flow_action *action,
3853                                        const uint64_t item_flags,
3854                                        struct rte_flow_error *error)
3855 {
3856         int ret = 0;
3857         uint64_t layer;
3858
3859         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3860         if (!ret) {
3861                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3862                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3863                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3864                 if (!(item_flags & layer))
3865                         return rte_flow_error_set(error, EINVAL,
3866                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3867                                                   NULL, "no TCP item in"
3868                                                   " pattern");
3869                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3870                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3871                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3872                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3873                         return rte_flow_error_set(error, EINVAL,
3874                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3875                                                   NULL,
3876                                                   "cannot decrease and increase"
3877                                                   " TCP acknowledgment number"
3878                                                   " at the same time");
3879         }
3880         return ret;
3881 }
3882
3883 /**
3884  * Validate the modify-header TTL actions.
3885  *
3886  * @param[in] action_flags
3887  *   Holds the actions detected until now.
3888  * @param[in] action
3889  *   Pointer to the modify action.
3890  * @param[in] item_flags
3891  *   Holds the items detected.
3892  * @param[out] error
3893  *   Pointer to error structure.
3894  *
3895  * @return
3896  *   0 on success, a negative errno value otherwise and rte_errno is set.
3897  */
3898 static int
3899 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3900                                    const struct rte_flow_action *action,
3901                                    const uint64_t item_flags,
3902                                    struct rte_flow_error *error)
3903 {
3904         int ret = 0;
3905         uint64_t layer;
3906
3907         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3908         if (!ret) {
3909                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3910                                  MLX5_FLOW_LAYER_INNER_L3 :
3911                                  MLX5_FLOW_LAYER_OUTER_L3;
3912                 if (!(item_flags & layer))
3913                         return rte_flow_error_set(error, EINVAL,
3914                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3915                                                   NULL,
3916                                                   "no IP protocol in pattern");
3917         }
3918         return ret;
3919 }
3920
3921 /**
3922  * Validate jump action.
3923  *
3924  * @param[in] action
3925  *   Pointer to the jump action.
3926  * @param[in] action_flags
3927  *   Holds the actions detected until now.
3928  * @param[in] attributes
3929  *   Pointer to flow attributes
3930  * @param[in] external
3931  *   Action belongs to flow rule created by request external to PMD.
3932  * @param[out] error
3933  *   Pointer to error structure.
3934  *
3935  * @return
3936  *   0 on success, a negative errno value otherwise and rte_errno is set.
3937  */
3938 static int
3939 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3940                              const struct mlx5_flow_tunnel *tunnel,
3941                              const struct rte_flow_action *action,
3942                              uint64_t action_flags,
3943                              const struct rte_flow_attr *attributes,
3944                              bool external, struct rte_flow_error *error)
3945 {
3946         uint32_t target_group, table;
3947         int ret = 0;
3948         struct flow_grp_info grp_info = {
3949                 .external = !!external,
3950                 .transfer = !!attributes->transfer,
3951                 .fdb_def_rule = 1,
3952                 .std_tbl_fix = 0
3953         };
3954         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3955                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3956                 return rte_flow_error_set(error, EINVAL,
3957                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3958                                           "can't have 2 fate actions in"
3959                                           " same flow");
3960         if (action_flags & MLX5_FLOW_ACTION_METER)
3961                 return rte_flow_error_set(error, ENOTSUP,
3962                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3963                                           "jump with meter not support");
3964         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3965                 return rte_flow_error_set(error, EINVAL,
3966                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3967                                           "E-Switch mirroring can't support"
3968                                           " Sample action and jump action in"
3969                                           " same flow now");
3970         if (!action->conf)
3971                 return rte_flow_error_set(error, EINVAL,
3972                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3973                                           NULL, "action configuration not set");
3974         target_group =
3975                 ((const struct rte_flow_action_jump *)action->conf)->group;
3976         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3977                                        &grp_info, error);
3978         if (ret)
3979                 return ret;
3980         if (attributes->group == target_group &&
3981             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3982                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3983                 return rte_flow_error_set(error, EINVAL,
3984                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3985                                           "target group must be other than"
3986                                           " the current flow group");
3987         return 0;
3988 }
3989
3990 /*
3991  * Validate the port_id action.
3992  *
3993  * @param[in] dev
3994  *   Pointer to rte_eth_dev structure.
3995  * @param[in] action_flags
3996  *   Bit-fields that holds the actions detected until now.
3997  * @param[in] action
3998  *   Port_id RTE action structure.
3999  * @param[in] attr
4000  *   Attributes of flow that includes this action.
4001  * @param[out] error
4002  *   Pointer to error structure.
4003  *
4004  * @return
4005  *   0 on success, a negative errno value otherwise and rte_errno is set.
4006  */
4007 static int
4008 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4009                                 uint64_t action_flags,
4010                                 const struct rte_flow_action *action,
4011                                 const struct rte_flow_attr *attr,
4012                                 struct rte_flow_error *error)
4013 {
4014         const struct rte_flow_action_port_id *port_id;
4015         struct mlx5_priv *act_priv;
4016         struct mlx5_priv *dev_priv;
4017         uint16_t port;
4018
4019         if (!attr->transfer)
4020                 return rte_flow_error_set(error, ENOTSUP,
4021                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4022                                           NULL,
4023                                           "port id action is valid in transfer"
4024                                           " mode only");
4025         if (!action || !action->conf)
4026                 return rte_flow_error_set(error, ENOTSUP,
4027                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4028                                           NULL,
4029                                           "port id action parameters must be"
4030                                           " specified");
4031         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4032                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4033                 return rte_flow_error_set(error, EINVAL,
4034                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4035                                           "can have only one fate actions in"
4036                                           " a flow");
4037         dev_priv = mlx5_dev_to_eswitch_info(dev);
4038         if (!dev_priv)
4039                 return rte_flow_error_set(error, rte_errno,
4040                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4041                                           NULL,
4042                                           "failed to obtain E-Switch info");
4043         port_id = action->conf;
4044         port = port_id->original ? dev->data->port_id : port_id->id;
4045         act_priv = mlx5_port_to_eswitch_info(port, false);
4046         if (!act_priv)
4047                 return rte_flow_error_set
4048                                 (error, rte_errno,
4049                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4050                                  "failed to obtain E-Switch port id for port");
4051         if (act_priv->domain_id != dev_priv->domain_id)
4052                 return rte_flow_error_set
4053                                 (error, EINVAL,
4054                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4055                                  "port does not belong to"
4056                                  " E-Switch being configured");
4057         return 0;
4058 }
4059
4060 /**
4061  * Get the maximum number of modify header actions.
4062  *
4063  * @param dev
4064  *   Pointer to rte_eth_dev structure.
4065  * @param flags
4066  *   Flags bits to check if root level.
4067  *
4068  * @return
4069  *   Max number of modify header actions device can support.
4070  */
4071 static inline unsigned int
4072 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4073                               uint64_t flags)
4074 {
4075         /*
4076          * There's no way to directly query the max capacity from FW.
4077          * The maximal value on root table should be assumed to be supported.
4078          */
4079         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4080                 return MLX5_MAX_MODIFY_NUM;
4081         else
4082                 return MLX5_ROOT_TBL_MODIFY_NUM;
4083 }
4084
4085 /**
4086  * Validate the meter action.
4087  *
4088  * @param[in] dev
4089  *   Pointer to rte_eth_dev structure.
4090  * @param[in] action_flags
4091  *   Bit-fields that holds the actions detected until now.
4092  * @param[in] action
4093  *   Pointer to the meter action.
4094  * @param[in] attr
4095  *   Attributes of flow that includes this action.
4096  * @param[out] error
4097  *   Pointer to error structure.
4098  *
4099  * @return
4100  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4101  */
4102 static int
4103 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4104                                 uint64_t action_flags,
4105                                 const struct rte_flow_action *action,
4106                                 const struct rte_flow_attr *attr,
4107                                 struct rte_flow_error *error)
4108 {
4109         struct mlx5_priv *priv = dev->data->dev_private;
4110         const struct rte_flow_action_meter *am = action->conf;
4111         struct mlx5_flow_meter *fm;
4112
4113         if (!am)
4114                 return rte_flow_error_set(error, EINVAL,
4115                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4116                                           "meter action conf is NULL");
4117
4118         if (action_flags & MLX5_FLOW_ACTION_METER)
4119                 return rte_flow_error_set(error, ENOTSUP,
4120                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4121                                           "meter chaining not support");
4122         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4123                 return rte_flow_error_set(error, ENOTSUP,
4124                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4125                                           "meter with jump not support");
4126         if (!priv->mtr_en)
4127                 return rte_flow_error_set(error, ENOTSUP,
4128                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4129                                           NULL,
4130                                           "meter action not supported");
4131         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4132         if (!fm)
4133                 return rte_flow_error_set(error, EINVAL,
4134                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4135                                           "Meter not found");
4136         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4137               (!fm->ingress && !attr->ingress && attr->egress) ||
4138               (!fm->egress && !attr->egress && attr->ingress))))
4139                 return rte_flow_error_set(error, EINVAL,
4140                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4141                                           "Flow attributes are either invalid "
4142                                           "or have a conflict with current "
4143                                           "meter attributes");
4144         return 0;
4145 }
4146
4147 /**
4148  * Validate the age action.
4149  *
4150  * @param[in] action_flags
4151  *   Holds the actions detected until now.
4152  * @param[in] action
4153  *   Pointer to the age action.
4154  * @param[in] dev
4155  *   Pointer to the Ethernet device structure.
4156  * @param[out] error
4157  *   Pointer to error structure.
4158  *
4159  * @return
4160  *   0 on success, a negative errno value otherwise and rte_errno is set.
4161  */
4162 static int
4163 flow_dv_validate_action_age(uint64_t action_flags,
4164                             const struct rte_flow_action *action,
4165                             struct rte_eth_dev *dev,
4166                             struct rte_flow_error *error)
4167 {
4168         struct mlx5_priv *priv = dev->data->dev_private;
4169         const struct rte_flow_action_age *age = action->conf;
4170
4171         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4172             !priv->sh->aso_age_mng))
4173                 return rte_flow_error_set(error, ENOTSUP,
4174                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4175                                           NULL,
4176                                           "age action not supported");
4177         if (!(action->conf))
4178                 return rte_flow_error_set(error, EINVAL,
4179                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4180                                           "configuration cannot be null");
4181         if (!(age->timeout))
4182                 return rte_flow_error_set(error, EINVAL,
4183                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4184                                           "invalid timeout value 0");
4185         if (action_flags & MLX5_FLOW_ACTION_AGE)
4186                 return rte_flow_error_set(error, EINVAL,
4187                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4188                                           "duplicate age actions set");
4189         return 0;
4190 }
4191
4192 /**
4193  * Validate the modify-header IPv4 DSCP actions.
4194  *
4195  * @param[in] action_flags
4196  *   Holds the actions detected until now.
4197  * @param[in] action
4198  *   Pointer to the modify action.
4199  * @param[in] item_flags
4200  *   Holds the items detected.
4201  * @param[out] error
4202  *   Pointer to error structure.
4203  *
4204  * @return
4205  *   0 on success, a negative errno value otherwise and rte_errno is set.
4206  */
4207 static int
4208 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4209                                          const struct rte_flow_action *action,
4210                                          const uint64_t item_flags,
4211                                          struct rte_flow_error *error)
4212 {
4213         int ret = 0;
4214
4215         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4216         if (!ret) {
4217                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4218                         return rte_flow_error_set(error, EINVAL,
4219                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4220                                                   NULL,
4221                                                   "no ipv4 item in pattern");
4222         }
4223         return ret;
4224 }
4225
4226 /**
4227  * Validate the modify-header IPv6 DSCP actions.
4228  *
4229  * @param[in] action_flags
4230  *   Holds the actions detected until now.
4231  * @param[in] action
4232  *   Pointer to the modify action.
4233  * @param[in] item_flags
4234  *   Holds the items detected.
4235  * @param[out] error
4236  *   Pointer to error structure.
4237  *
4238  * @return
4239  *   0 on success, a negative errno value otherwise and rte_errno is set.
4240  */
4241 static int
4242 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4243                                          const struct rte_flow_action *action,
4244                                          const uint64_t item_flags,
4245                                          struct rte_flow_error *error)
4246 {
4247         int ret = 0;
4248
4249         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4250         if (!ret) {
4251                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4252                         return rte_flow_error_set(error, EINVAL,
4253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4254                                                   NULL,
4255                                                   "no ipv6 item in pattern");
4256         }
4257         return ret;
4258 }
4259
4260 /**
4261  * Match modify-header resource.
4262  *
4263  * @param list
4264  *   Pointer to the hash list.
4265  * @param entry
4266  *   Pointer to exist resource entry object.
4267  * @param key
4268  *   Key of the new entry.
4269  * @param ctx
4270  *   Pointer to new modify-header resource.
4271  *
4272  * @return
4273  *   0 on matching, non-zero otherwise.
4274  */
4275 int
4276 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4277                         struct mlx5_hlist_entry *entry,
4278                         uint64_t key __rte_unused, void *cb_ctx)
4279 {
4280         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4281         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4282         struct mlx5_flow_dv_modify_hdr_resource *resource =
4283                         container_of(entry, typeof(*resource), entry);
4284         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4285
4286         key_len += ref->actions_num * sizeof(ref->actions[0]);
4287         return ref->actions_num != resource->actions_num ||
4288                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4289 }
4290
4291 struct mlx5_hlist_entry *
4292 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4293                          void *cb_ctx)
4294 {
4295         struct mlx5_dev_ctx_shared *sh = list->ctx;
4296         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4297         struct mlx5dv_dr_domain *ns;
4298         struct mlx5_flow_dv_modify_hdr_resource *entry;
4299         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4300         int ret;
4301         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4302         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4303
4304         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4305                             SOCKET_ID_ANY);
4306         if (!entry) {
4307                 rte_flow_error_set(ctx->error, ENOMEM,
4308                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4309                                    "cannot allocate resource memory");
4310                 return NULL;
4311         }
4312         rte_memcpy(&entry->ft_type,
4313                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4314                    key_len + data_len);
4315         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4316                 ns = sh->fdb_domain;
4317         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4318                 ns = sh->tx_domain;
4319         else
4320                 ns = sh->rx_domain;
4321         ret = mlx5_flow_os_create_flow_action_modify_header
4322                                         (sh->ctx, ns, entry,
4323                                          data_len, &entry->action);
4324         if (ret) {
4325                 mlx5_free(entry);
4326                 rte_flow_error_set(ctx->error, ENOMEM,
4327                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4328                                    NULL, "cannot create modification action");
4329                 return NULL;
4330         }
4331         return &entry->entry;
4332 }
4333
4334 /**
4335  * Validate the sample action.
4336  *
4337  * @param[in] action_flags
4338  *   Holds the actions detected until now.
4339  * @param[in] action
4340  *   Pointer to the sample action.
4341  * @param[in] dev
4342  *   Pointer to the Ethernet device structure.
4343  * @param[in] attr
4344  *   Attributes of flow that includes this action.
4345  * @param[in] item_flags
4346  *   Holds the items detected.
4347  * @param[out] error
4348  *   Pointer to error structure.
4349  *
4350  * @return
4351  *   0 on success, a negative errno value otherwise and rte_errno is set.
4352  */
4353 static int
4354 flow_dv_validate_action_sample(uint64_t action_flags,
4355                                const struct rte_flow_action *action,
4356                                struct rte_eth_dev *dev,
4357                                const struct rte_flow_attr *attr,
4358                                const uint64_t item_flags,
4359                                struct rte_flow_error *error)
4360 {
4361         struct mlx5_priv *priv = dev->data->dev_private;
4362         struct mlx5_dev_config *dev_conf = &priv->config;
4363         const struct rte_flow_action_sample *sample = action->conf;
4364         const struct rte_flow_action *act;
4365         uint64_t sub_action_flags = 0;
4366         uint16_t queue_index = 0xFFFF;
4367         int actions_n = 0;
4368         int ret;
4369         fdb_mirror = 0;
4370
4371         if (!sample)
4372                 return rte_flow_error_set(error, EINVAL,
4373                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4374                                           "configuration cannot be NULL");
4375         if (sample->ratio == 0)
4376                 return rte_flow_error_set(error, EINVAL,
4377                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4378                                           "ratio value starts from 1");
4379         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4380                 return rte_flow_error_set(error, ENOTSUP,
4381                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4382                                           NULL,
4383                                           "sample action not supported");
4384         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4385                 return rte_flow_error_set(error, EINVAL,
4386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4387                                           "Multiple sample actions not "
4388                                           "supported");
4389         if (action_flags & MLX5_FLOW_ACTION_METER)
4390                 return rte_flow_error_set(error, EINVAL,
4391                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4392                                           "wrong action order, meter should "
4393                                           "be after sample action");
4394         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4395                 return rte_flow_error_set(error, EINVAL,
4396                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4397                                           "wrong action order, jump should "
4398                                           "be after sample action");
4399         act = sample->actions;
4400         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4401                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4402                         return rte_flow_error_set(error, ENOTSUP,
4403                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4404                                                   act, "too many actions");
4405                 switch (act->type) {
4406                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4407                         ret = mlx5_flow_validate_action_queue(act,
4408                                                               sub_action_flags,
4409                                                               dev,
4410                                                               attr, error);
4411                         if (ret < 0)
4412                                 return ret;
4413                         queue_index = ((const struct rte_flow_action_queue *)
4414                                                         (act->conf))->index;
4415                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4416                         ++actions_n;
4417                         break;
4418                 case RTE_FLOW_ACTION_TYPE_MARK:
4419                         ret = flow_dv_validate_action_mark(dev, act,
4420                                                            sub_action_flags,
4421                                                            attr, error);
4422                         if (ret < 0)
4423                                 return ret;
4424                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4425                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4426                                                 MLX5_FLOW_ACTION_MARK_EXT;
4427                         else
4428                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4429                         ++actions_n;
4430                         break;
4431                 case RTE_FLOW_ACTION_TYPE_COUNT:
4432                         ret = flow_dv_validate_action_count(dev, error);
4433                         if (ret < 0)
4434                                 return ret;
4435                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4436                         ++actions_n;
4437                         break;
4438                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4439                         ret = flow_dv_validate_action_port_id(dev,
4440                                                               sub_action_flags,
4441                                                               act,
4442                                                               attr,
4443                                                               error);
4444                         if (ret)
4445                                 return ret;
4446                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4447                         ++actions_n;
4448                         break;
4449                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4450                         ret = flow_dv_validate_action_raw_encap_decap
4451                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4452                                  &actions_n, action, item_flags, error);
4453                         if (ret < 0)
4454                                 return ret;
4455                         ++actions_n;
4456                         break;
4457                 default:
4458                         return rte_flow_error_set(error, ENOTSUP,
4459                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4460                                                   NULL,
4461                                                   "Doesn't support optional "
4462                                                   "action");
4463                 }
4464         }
4465         if (attr->ingress && !attr->transfer) {
4466                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4467                         return rte_flow_error_set(error, EINVAL,
4468                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4469                                                   NULL,
4470                                                   "Ingress must has a dest "
4471                                                   "QUEUE for Sample");
4472         } else if (attr->egress && !attr->transfer) {
4473                 return rte_flow_error_set(error, ENOTSUP,
4474                                           RTE_FLOW_ERROR_TYPE_ACTION,
4475                                           NULL,
4476                                           "Sample Only support Ingress "
4477                                           "or E-Switch");
4478         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4479                 MLX5_ASSERT(attr->transfer);
4480                 if (sample->ratio > 1)
4481                         return rte_flow_error_set(error, ENOTSUP,
4482                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4483                                                   NULL,
4484                                                   "E-Switch doesn't support "
4485                                                   "any optional action "
4486                                                   "for sampling");
4487                 fdb_mirror = 1;
4488                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4489                         return rte_flow_error_set(error, ENOTSUP,
4490                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4491                                                   NULL,
4492                                                   "unsupported action QUEUE");
4493                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4494                         return rte_flow_error_set(error, EINVAL,
4495                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4496                                                   NULL,
4497                                                   "E-Switch must has a dest "
4498                                                   "port for mirroring");
4499         }
4500         /* Continue validation for Xcap actions.*/
4501         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4502             (queue_index == 0xFFFF ||
4503              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4504                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4505                      MLX5_FLOW_XCAP_ACTIONS)
4506                         return rte_flow_error_set(error, ENOTSUP,
4507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4508                                                   NULL, "encap and decap "
4509                                                   "combination aren't "
4510                                                   "supported");
4511                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4512                                                         MLX5_FLOW_ACTION_ENCAP))
4513                         return rte_flow_error_set(error, ENOTSUP,
4514                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4515                                                   NULL, "encap is not supported"
4516                                                   " for ingress traffic");
4517         }
4518         return 0;
4519 }
4520
4521 /**
4522  * Find existing modify-header resource or create and register a new one.
4523  *
4524  * @param dev[in, out]
4525  *   Pointer to rte_eth_dev structure.
4526  * @param[in, out] resource
4527  *   Pointer to modify-header resource.
4528  * @parm[in, out] dev_flow
4529  *   Pointer to the dev_flow.
4530  * @param[out] error
4531  *   pointer to error structure.
4532  *
4533  * @return
4534  *   0 on success otherwise -errno and errno is set.
4535  */
4536 static int
4537 flow_dv_modify_hdr_resource_register
4538                         (struct rte_eth_dev *dev,
4539                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4540                          struct mlx5_flow *dev_flow,
4541                          struct rte_flow_error *error)
4542 {
4543         struct mlx5_priv *priv = dev->data->dev_private;
4544         struct mlx5_dev_ctx_shared *sh = priv->sh;
4545         uint32_t key_len = sizeof(*resource) -
4546                            offsetof(typeof(*resource), ft_type) +
4547                            resource->actions_num * sizeof(resource->actions[0]);
4548         struct mlx5_hlist_entry *entry;
4549         struct mlx5_flow_cb_ctx ctx = {
4550                 .error = error,
4551                 .data = resource,
4552         };
4553         uint64_t key64;
4554
4555         resource->flags = dev_flow->dv.group ? 0 :
4556                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4557         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4558                                     resource->flags))
4559                 return rte_flow_error_set(error, EOVERFLOW,
4560                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4561                                           "too many modify header items");
4562         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4563         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
4564         if (!entry)
4565                 return -rte_errno;
4566         resource = container_of(entry, typeof(*resource), entry);
4567         dev_flow->handle->dvh.modify_hdr = resource;
4568         return 0;
4569 }
4570
4571 /**
4572  * Get DV flow counter by index.
4573  *
4574  * @param[in] dev
4575  *   Pointer to the Ethernet device structure.
4576  * @param[in] idx
4577  *   mlx5 flow counter index in the container.
4578  * @param[out] ppool
4579  *   mlx5 flow counter pool in the container,
4580  *
4581  * @return
4582  *   Pointer to the counter, NULL otherwise.
4583  */
4584 static struct mlx5_flow_counter *
4585 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4586                            uint32_t idx,
4587                            struct mlx5_flow_counter_pool **ppool)
4588 {
4589         struct mlx5_priv *priv = dev->data->dev_private;
4590         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4591         struct mlx5_flow_counter_pool *pool;
4592
4593         /* Decrease to original index and clear shared bit. */
4594         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4595         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4596         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4597         MLX5_ASSERT(pool);
4598         if (ppool)
4599                 *ppool = pool;
4600         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4601 }
4602
4603 /**
4604  * Check the devx counter belongs to the pool.
4605  *
4606  * @param[in] pool
4607  *   Pointer to the counter pool.
4608  * @param[in] id
4609  *   The counter devx ID.
4610  *
4611  * @return
4612  *   True if counter belongs to the pool, false otherwise.
4613  */
4614 static bool
4615 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4616 {
4617         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4618                    MLX5_COUNTERS_PER_POOL;
4619
4620         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4621                 return true;
4622         return false;
4623 }
4624
4625 /**
4626  * Get a pool by devx counter ID.
4627  *
4628  * @param[in] cmng
4629  *   Pointer to the counter management.
4630  * @param[in] id
4631  *   The counter devx ID.
4632  *
4633  * @return
4634  *   The counter pool pointer if exists, NULL otherwise,
4635  */
4636 static struct mlx5_flow_counter_pool *
4637 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4638 {
4639         uint32_t i;
4640         struct mlx5_flow_counter_pool *pool = NULL;
4641
4642         rte_spinlock_lock(&cmng->pool_update_sl);
4643         /* Check last used pool. */
4644         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4645             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4646                 pool = cmng->pools[cmng->last_pool_idx];
4647                 goto out;
4648         }
4649         /* ID out of range means no suitable pool in the container. */
4650         if (id > cmng->max_id || id < cmng->min_id)
4651                 goto out;
4652         /*
4653          * Find the pool from the end of the container, since mostly counter
4654          * ID is sequence increasing, and the last pool should be the needed
4655          * one.
4656          */
4657         i = cmng->n_valid;
4658         while (i--) {
4659                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4660
4661                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4662                         pool = pool_tmp;
4663                         break;
4664                 }
4665         }
4666 out:
4667         rte_spinlock_unlock(&cmng->pool_update_sl);
4668         return pool;
4669 }
4670
4671 /**
4672  * Resize a counter container.
4673  *
4674  * @param[in] dev
4675  *   Pointer to the Ethernet device structure.
4676  *
4677  * @return
4678  *   0 on success, otherwise negative errno value and rte_errno is set.
4679  */
4680 static int
4681 flow_dv_container_resize(struct rte_eth_dev *dev)
4682 {
4683         struct mlx5_priv *priv = dev->data->dev_private;
4684         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4685         void *old_pools = cmng->pools;
4686         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4687         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4688         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4689
4690         if (!pools) {
4691                 rte_errno = ENOMEM;
4692                 return -ENOMEM;
4693         }
4694         if (old_pools)
4695                 memcpy(pools, old_pools, cmng->n *
4696                                        sizeof(struct mlx5_flow_counter_pool *));
4697         cmng->n = resize;
4698         cmng->pools = pools;
4699         if (old_pools)
4700                 mlx5_free(old_pools);
4701         return 0;
4702 }
4703
4704 /**
4705  * Query a devx flow counter.
4706  *
4707  * @param[in] dev
4708  *   Pointer to the Ethernet device structure.
4709  * @param[in] cnt
4710  *   Index to the flow counter.
4711  * @param[out] pkts
4712  *   The statistics value of packets.
4713  * @param[out] bytes
4714  *   The statistics value of bytes.
4715  *
4716  * @return
4717  *   0 on success, otherwise a negative errno value and rte_errno is set.
4718  */
4719 static inline int
4720 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4721                      uint64_t *bytes)
4722 {
4723         struct mlx5_priv *priv = dev->data->dev_private;
4724         struct mlx5_flow_counter_pool *pool = NULL;
4725         struct mlx5_flow_counter *cnt;
4726         int offset;
4727
4728         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4729         MLX5_ASSERT(pool);
4730         if (priv->sh->cmng.counter_fallback)
4731                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4732                                         0, pkts, bytes, 0, NULL, NULL, 0);
4733         rte_spinlock_lock(&pool->sl);
4734         if (!pool->raw) {
4735                 *pkts = 0;
4736                 *bytes = 0;
4737         } else {
4738                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4739                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4740                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4741         }
4742         rte_spinlock_unlock(&pool->sl);
4743         return 0;
4744 }
4745
4746 /**
4747  * Create and initialize a new counter pool.
4748  *
4749  * @param[in] dev
4750  *   Pointer to the Ethernet device structure.
4751  * @param[out] dcs
4752  *   The devX counter handle.
4753  * @param[in] age
4754  *   Whether the pool is for counter that was allocated for aging.
4755  * @param[in/out] cont_cur
4756  *   Pointer to the container pointer, it will be update in pool resize.
4757  *
4758  * @return
4759  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4760  */
4761 static struct mlx5_flow_counter_pool *
4762 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4763                     uint32_t age)
4764 {
4765         struct mlx5_priv *priv = dev->data->dev_private;
4766         struct mlx5_flow_counter_pool *pool;
4767         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4768         bool fallback = priv->sh->cmng.counter_fallback;
4769         uint32_t size = sizeof(*pool);
4770
4771         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4772         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4773         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4774         if (!pool) {
4775                 rte_errno = ENOMEM;
4776                 return NULL;
4777         }
4778         pool->raw = NULL;
4779         pool->is_aged = !!age;
4780         pool->query_gen = 0;
4781         pool->min_dcs = dcs;
4782         rte_spinlock_init(&pool->sl);
4783         rte_spinlock_init(&pool->csl);
4784         TAILQ_INIT(&pool->counters[0]);
4785         TAILQ_INIT(&pool->counters[1]);
4786         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4787         rte_spinlock_lock(&cmng->pool_update_sl);
4788         pool->index = cmng->n_valid;
4789         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4790                 mlx5_free(pool);
4791                 rte_spinlock_unlock(&cmng->pool_update_sl);
4792                 return NULL;
4793         }
4794         cmng->pools[pool->index] = pool;
4795         cmng->n_valid++;
4796         if (unlikely(fallback)) {
4797                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4798
4799                 if (base < cmng->min_id)
4800                         cmng->min_id = base;
4801                 if (base > cmng->max_id)
4802                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4803                 cmng->last_pool_idx = pool->index;
4804         }
4805         rte_spinlock_unlock(&cmng->pool_update_sl);
4806         return pool;
4807 }
4808
4809 /**
4810  * Prepare a new counter and/or a new counter pool.
4811  *
4812  * @param[in] dev
4813  *   Pointer to the Ethernet device structure.
4814  * @param[out] cnt_free
4815  *   Where to put the pointer of a new counter.
4816  * @param[in] age
4817  *   Whether the pool is for counter that was allocated for aging.
4818  *
4819  * @return
4820  *   The counter pool pointer and @p cnt_free is set on success,
4821  *   NULL otherwise and rte_errno is set.
4822  */
4823 static struct mlx5_flow_counter_pool *
4824 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4825                              struct mlx5_flow_counter **cnt_free,
4826                              uint32_t age)
4827 {
4828         struct mlx5_priv *priv = dev->data->dev_private;
4829         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4830         struct mlx5_flow_counter_pool *pool;
4831         struct mlx5_counters tmp_tq;
4832         struct mlx5_devx_obj *dcs = NULL;
4833         struct mlx5_flow_counter *cnt;
4834         enum mlx5_counter_type cnt_type =
4835                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4836         bool fallback = priv->sh->cmng.counter_fallback;
4837         uint32_t i;
4838
4839         if (fallback) {
4840                 /* bulk_bitmap must be 0 for single counter allocation. */
4841                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4842                 if (!dcs)
4843                         return NULL;
4844                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4845                 if (!pool) {
4846                         pool = flow_dv_pool_create(dev, dcs, age);
4847                         if (!pool) {
4848                                 mlx5_devx_cmd_destroy(dcs);
4849                                 return NULL;
4850                         }
4851                 }
4852                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4853                 cnt = MLX5_POOL_GET_CNT(pool, i);
4854                 cnt->pool = pool;
4855                 cnt->dcs_when_free = dcs;
4856                 *cnt_free = cnt;
4857                 return pool;
4858         }
4859         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4860         if (!dcs) {
4861                 rte_errno = ENODATA;
4862                 return NULL;
4863         }
4864         pool = flow_dv_pool_create(dev, dcs, age);
4865         if (!pool) {
4866                 mlx5_devx_cmd_destroy(dcs);
4867                 return NULL;
4868         }
4869         TAILQ_INIT(&tmp_tq);
4870         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4871                 cnt = MLX5_POOL_GET_CNT(pool, i);
4872                 cnt->pool = pool;
4873                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4874         }
4875         rte_spinlock_lock(&cmng->csl[cnt_type]);
4876         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4877         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4878         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4879         (*cnt_free)->pool = pool;
4880         return pool;
4881 }
4882
4883 /**
4884  * Allocate a flow counter.
4885  *
4886  * @param[in] dev
4887  *   Pointer to the Ethernet device structure.
4888  * @param[in] age
4889  *   Whether the counter was allocated for aging.
4890  *
4891  * @return
4892  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4893  */
4894 static uint32_t
4895 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4896 {
4897         struct mlx5_priv *priv = dev->data->dev_private;
4898         struct mlx5_flow_counter_pool *pool = NULL;
4899         struct mlx5_flow_counter *cnt_free = NULL;
4900         bool fallback = priv->sh->cmng.counter_fallback;
4901         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4902         enum mlx5_counter_type cnt_type =
4903                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4904         uint32_t cnt_idx;
4905
4906         if (!priv->config.devx) {
4907                 rte_errno = ENOTSUP;
4908                 return 0;
4909         }
4910         /* Get free counters from container. */
4911         rte_spinlock_lock(&cmng->csl[cnt_type]);
4912         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4913         if (cnt_free)
4914                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4915         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4916         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4917                 goto err;
4918         pool = cnt_free->pool;
4919         if (fallback)
4920                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4921         /* Create a DV counter action only in the first time usage. */
4922         if (!cnt_free->action) {
4923                 uint16_t offset;
4924                 struct mlx5_devx_obj *dcs;
4925                 int ret;
4926
4927                 if (!fallback) {
4928                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4929                         dcs = pool->min_dcs;
4930                 } else {
4931                         offset = 0;
4932                         dcs = cnt_free->dcs_when_free;
4933                 }
4934                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4935                                                             &cnt_free->action);
4936                 if (ret) {
4937                         rte_errno = errno;
4938                         goto err;
4939                 }
4940         }
4941         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4942                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4943         /* Update the counter reset values. */
4944         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4945                                  &cnt_free->bytes))
4946                 goto err;
4947         if (!fallback && !priv->sh->cmng.query_thread_on)
4948                 /* Start the asynchronous batch query by the host thread. */
4949                 mlx5_set_query_alarm(priv->sh);
4950         return cnt_idx;
4951 err:
4952         if (cnt_free) {
4953                 cnt_free->pool = pool;
4954                 if (fallback)
4955                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4956                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4957                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4958                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4959         }
4960         return 0;
4961 }
4962
4963 /**
4964  * Allocate a shared flow counter.
4965  *
4966  * @param[in] ctx
4967  *   Pointer to the shared counter configuration.
4968  * @param[in] data
4969  *   Pointer to save the allocated counter index.
4970  *
4971  * @return
4972  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4973  */
4974
4975 static int32_t
4976 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4977 {
4978         struct mlx5_shared_counter_conf *conf = ctx;
4979         struct rte_eth_dev *dev = conf->dev;
4980         struct mlx5_flow_counter *cnt;
4981
4982         data->dword = flow_dv_counter_alloc(dev, 0);
4983         data->dword |= MLX5_CNT_SHARED_OFFSET;
4984         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4985         cnt->shared_info.id = conf->id;
4986         return 0;
4987 }
4988
4989 /**
4990  * Get a shared flow counter.
4991  *
4992  * @param[in] dev
4993  *   Pointer to the Ethernet device structure.
4994  * @param[in] id
4995  *   Counter identifier.
4996  *
4997  * @return
4998  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4999  */
5000 static uint32_t
5001 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5002 {
5003         struct mlx5_priv *priv = dev->data->dev_private;
5004         struct mlx5_shared_counter_conf conf = {
5005                 .dev = dev,
5006                 .id = id,
5007         };
5008         union mlx5_l3t_data data = {
5009                 .dword = 0,
5010         };
5011
5012         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5013                                flow_dv_counter_alloc_shared_cb, &conf);
5014         return data.dword;
5015 }
5016
5017 /**
5018  * Get age param from counter index.
5019  *
5020  * @param[in] dev
5021  *   Pointer to the Ethernet device structure.
5022  * @param[in] counter
5023  *   Index to the counter handler.
5024  *
5025  * @return
5026  *   The aging parameter specified for the counter index.
5027  */
5028 static struct mlx5_age_param*
5029 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5030                                 uint32_t counter)
5031 {
5032         struct mlx5_flow_counter *cnt;
5033         struct mlx5_flow_counter_pool *pool = NULL;
5034
5035         flow_dv_counter_get_by_idx(dev, counter, &pool);
5036         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5037         cnt = MLX5_POOL_GET_CNT(pool, counter);
5038         return MLX5_CNT_TO_AGE(cnt);
5039 }
5040
5041 /**
5042  * Remove a flow counter from aged counter list.
5043  *
5044  * @param[in] dev
5045  *   Pointer to the Ethernet device structure.
5046  * @param[in] counter
5047  *   Index to the counter handler.
5048  * @param[in] cnt
5049  *   Pointer to the counter handler.
5050  */
5051 static void
5052 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5053                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5054 {
5055         struct mlx5_age_info *age_info;
5056         struct mlx5_age_param *age_param;
5057         struct mlx5_priv *priv = dev->data->dev_private;
5058         uint16_t expected = AGE_CANDIDATE;
5059
5060         age_info = GET_PORT_AGE_INFO(priv);
5061         age_param = flow_dv_counter_idx_get_age(dev, counter);
5062         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5063                                          AGE_FREE, false, __ATOMIC_RELAXED,
5064                                          __ATOMIC_RELAXED)) {
5065                 /**
5066                  * We need the lock even it is age timeout,
5067                  * since counter may still in process.
5068                  */
5069                 rte_spinlock_lock(&age_info->aged_sl);
5070                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5071                 rte_spinlock_unlock(&age_info->aged_sl);
5072                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5073         }
5074 }
5075
5076 /**
5077  * Release a flow counter.
5078  *
5079  * @param[in] dev
5080  *   Pointer to the Ethernet device structure.
5081  * @param[in] counter
5082  *   Index to the counter handler.
5083  */
5084 static void
5085 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5086 {
5087         struct mlx5_priv *priv = dev->data->dev_private;
5088         struct mlx5_flow_counter_pool *pool = NULL;
5089         struct mlx5_flow_counter *cnt;
5090         enum mlx5_counter_type cnt_type;
5091
5092         if (!counter)
5093                 return;
5094         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5095         MLX5_ASSERT(pool);
5096         if (IS_SHARED_CNT(counter) &&
5097             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5098                 return;
5099         if (pool->is_aged)
5100                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5101         cnt->pool = pool;
5102         /*
5103          * Put the counter back to list to be updated in none fallback mode.
5104          * Currently, we are using two list alternately, while one is in query,
5105          * add the freed counter to the other list based on the pool query_gen
5106          * value. After query finishes, add counter the list to the global
5107          * container counter list. The list changes while query starts. In
5108          * this case, lock will not be needed as query callback and release
5109          * function both operate with the different list.
5110          *
5111          */
5112         if (!priv->sh->cmng.counter_fallback) {
5113                 rte_spinlock_lock(&pool->csl);
5114                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5115                 rte_spinlock_unlock(&pool->csl);
5116         } else {
5117                 cnt->dcs_when_free = cnt->dcs_when_active;
5118                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5119                                            MLX5_COUNTER_TYPE_ORIGIN;
5120                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5121                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5122                                   cnt, next);
5123                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5124         }
5125 }
5126
5127 /**
5128  * Verify the @p attributes will be correctly understood by the NIC and store
5129  * them in the @p flow if everything is correct.
5130  *
5131  * @param[in] dev
5132  *   Pointer to dev struct.
5133  * @param[in] attributes
5134  *   Pointer to flow attributes
5135  * @param[in] external
5136  *   This flow rule is created by request external to PMD.
5137  * @param[out] error
5138  *   Pointer to error structure.
5139  *
5140  * @return
5141  *   - 0 on success and non root table.
5142  *   - 1 on success and root table.
5143  *   - a negative errno value otherwise and rte_errno is set.
5144  */
5145 static int
5146 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5147                             const struct mlx5_flow_tunnel *tunnel,
5148                             const struct rte_flow_attr *attributes,
5149                             const struct flow_grp_info *grp_info,
5150                             struct rte_flow_error *error)
5151 {
5152         struct mlx5_priv *priv = dev->data->dev_private;
5153         uint32_t priority_max = priv->config.flow_prio - 1;
5154         int ret = 0;
5155
5156 #ifndef HAVE_MLX5DV_DR
5157         RTE_SET_USED(tunnel);
5158         RTE_SET_USED(grp_info);
5159         if (attributes->group)
5160                 return rte_flow_error_set(error, ENOTSUP,
5161                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5162                                           NULL,
5163                                           "groups are not supported");
5164 #else
5165         uint32_t table = 0;
5166
5167         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5168                                        grp_info, error);
5169         if (ret)
5170                 return ret;
5171         if (!table)
5172                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5173 #endif
5174         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5175             attributes->priority >= priority_max)
5176                 return rte_flow_error_set(error, ENOTSUP,
5177                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5178                                           NULL,
5179                                           "priority out of range");
5180         if (attributes->transfer) {
5181                 if (!priv->config.dv_esw_en)
5182                         return rte_flow_error_set
5183                                 (error, ENOTSUP,
5184                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5185                                  "E-Switch dr is not supported");
5186                 if (!(priv->representor || priv->master))
5187                         return rte_flow_error_set
5188                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5189                                  NULL, "E-Switch configuration can only be"
5190                                  " done by a master or a representor device");
5191                 if (attributes->egress)
5192                         return rte_flow_error_set
5193                                 (error, ENOTSUP,
5194                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5195                                  "egress is not supported");
5196         }
5197         if (!(attributes->egress ^ attributes->ingress))
5198                 return rte_flow_error_set(error, ENOTSUP,
5199                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5200                                           "must specify exactly one of "
5201                                           "ingress or egress");
5202         return ret;
5203 }
5204
5205 /**
5206  * Internal validation function. For validating both actions and items.
5207  *
5208  * @param[in] dev
5209  *   Pointer to the rte_eth_dev structure.
5210  * @param[in] attr
5211  *   Pointer to the flow attributes.
5212  * @param[in] items
5213  *   Pointer to the list of items.
5214  * @param[in] actions
5215  *   Pointer to the list of actions.
5216  * @param[in] external
5217  *   This flow rule is created by request external to PMD.
5218  * @param[in] hairpin
5219  *   Number of hairpin TX actions, 0 means classic flow.
5220  * @param[out] error
5221  *   Pointer to the error structure.
5222  *
5223  * @return
5224  *   0 on success, a negative errno value otherwise and rte_errno is set.
5225  */
5226 static int
5227 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5228                  const struct rte_flow_item items[],
5229                  const struct rte_flow_action actions[],
5230                  bool external, int hairpin, struct rte_flow_error *error)
5231 {
5232         int ret;
5233         uint64_t action_flags = 0;
5234         uint64_t item_flags = 0;
5235         uint64_t last_item = 0;
5236         uint8_t next_protocol = 0xff;
5237         uint16_t ether_type = 0;
5238         int actions_n = 0;
5239         uint8_t item_ipv6_proto = 0;
5240         const struct rte_flow_item *gre_item = NULL;
5241         const struct rte_flow_action_raw_decap *decap;
5242         const struct rte_flow_action_raw_encap *encap;
5243         const struct rte_flow_action_rss *rss;
5244         const struct rte_flow_item_tcp nic_tcp_mask = {
5245                 .hdr = {
5246                         .tcp_flags = 0xFF,
5247                         .src_port = RTE_BE16(UINT16_MAX),
5248                         .dst_port = RTE_BE16(UINT16_MAX),
5249                 }
5250         };
5251         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5252                 .hdr = {
5253                         .src_addr =
5254                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5255                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5256                         .dst_addr =
5257                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5258                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5259                         .vtc_flow = RTE_BE32(0xffffffff),
5260                         .proto = 0xff,
5261                         .hop_limits = 0xff,
5262                 },
5263                 .has_frag_ext = 1,
5264         };
5265         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5266                 .hdr = {
5267                         .common = {
5268                                 .u32 =
5269                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5270                                         .type = 0xFF,
5271                                         }).u32),
5272                         },
5273                         .dummy[0] = 0xffffffff,
5274                 },
5275         };
5276         struct mlx5_priv *priv = dev->data->dev_private;
5277         struct mlx5_dev_config *dev_conf = &priv->config;
5278         uint16_t queue_index = 0xFFFF;
5279         const struct rte_flow_item_vlan *vlan_m = NULL;
5280         int16_t rw_act_num = 0;
5281         uint64_t is_root;
5282         const struct mlx5_flow_tunnel *tunnel;
5283         struct flow_grp_info grp_info = {
5284                 .external = !!external,
5285                 .transfer = !!attr->transfer,
5286                 .fdb_def_rule = !!priv->fdb_def_rule,
5287         };
5288         const struct rte_eth_hairpin_conf *conf;
5289
5290         if (items == NULL)
5291                 return -1;
5292         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5293                 tunnel = flow_items_to_tunnel(items);
5294                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5295                                 MLX5_FLOW_ACTION_DECAP;
5296         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5297                 tunnel = flow_actions_to_tunnel(actions);
5298                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5299         } else {
5300                 tunnel = NULL;
5301         }
5302         if (tunnel && priv->representor)
5303                 return rte_flow_error_set(error, ENOTSUP,
5304                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5305                                           "decap not supported "
5306                                           "for VF representor");
5307         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5308                                 (dev, tunnel, attr, items, actions);
5309         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
5310         if (ret < 0)
5311                 return ret;
5312         is_root = (uint64_t)ret;
5313         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5314                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5315                 int type = items->type;
5316
5317                 if (!mlx5_flow_os_item_supported(type))
5318                         return rte_flow_error_set(error, ENOTSUP,
5319                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5320                                                   NULL, "item not supported");
5321                 switch (type) {
5322                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5323                         if (items[0].type != (typeof(items[0].type))
5324                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5325                                 return rte_flow_error_set
5326                                                 (error, EINVAL,
5327                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5328                                                 NULL, "MLX5 private items "
5329                                                 "must be the first");
5330                         break;
5331                 case RTE_FLOW_ITEM_TYPE_VOID:
5332                         break;
5333                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5334                         ret = flow_dv_validate_item_port_id
5335                                         (dev, items, attr, item_flags, error);
5336                         if (ret < 0)
5337                                 return ret;
5338                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5339                         break;
5340                 case RTE_FLOW_ITEM_TYPE_ETH:
5341                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5342                                                           true, error);
5343                         if (ret < 0)
5344                                 return ret;
5345                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5346                                              MLX5_FLOW_LAYER_OUTER_L2;
5347                         if (items->mask != NULL && items->spec != NULL) {
5348                                 ether_type =
5349                                         ((const struct rte_flow_item_eth *)
5350                                          items->spec)->type;
5351                                 ether_type &=
5352                                         ((const struct rte_flow_item_eth *)
5353                                          items->mask)->type;
5354                                 ether_type = rte_be_to_cpu_16(ether_type);
5355                         } else {
5356                                 ether_type = 0;
5357                         }
5358                         break;
5359                 case RTE_FLOW_ITEM_TYPE_VLAN:
5360                         ret = flow_dv_validate_item_vlan(items, item_flags,
5361                                                          dev, error);
5362                         if (ret < 0)
5363                                 return ret;
5364                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5365                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5366                         if (items->mask != NULL && items->spec != NULL) {
5367                                 ether_type =
5368                                         ((const struct rte_flow_item_vlan *)
5369                                          items->spec)->inner_type;
5370                                 ether_type &=
5371                                         ((const struct rte_flow_item_vlan *)
5372                                          items->mask)->inner_type;
5373                                 ether_type = rte_be_to_cpu_16(ether_type);
5374                         } else {
5375                                 ether_type = 0;
5376                         }
5377                         /* Store outer VLAN mask for of_push_vlan action. */
5378                         if (!tunnel)
5379                                 vlan_m = items->mask;
5380                         break;
5381                 case RTE_FLOW_ITEM_TYPE_IPV4:
5382                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5383                                                   &item_flags, &tunnel);
5384                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5385                                                          last_item, ether_type,
5386                                                          error);
5387                         if (ret < 0)
5388                                 return ret;
5389                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5390                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5391                         if (items->mask != NULL &&
5392                             ((const struct rte_flow_item_ipv4 *)
5393                              items->mask)->hdr.next_proto_id) {
5394                                 next_protocol =
5395                                         ((const struct rte_flow_item_ipv4 *)
5396                                          (items->spec))->hdr.next_proto_id;
5397                                 next_protocol &=
5398                                         ((const struct rte_flow_item_ipv4 *)
5399                                          (items->mask))->hdr.next_proto_id;
5400                         } else {
5401                                 /* Reset for inner layer. */
5402                                 next_protocol = 0xff;
5403                         }
5404                         break;
5405                 case RTE_FLOW_ITEM_TYPE_IPV6:
5406                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5407                                                   &item_flags, &tunnel);
5408                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5409                                                            last_item,
5410                                                            ether_type,
5411                                                            &nic_ipv6_mask,
5412                                                            error);
5413                         if (ret < 0)
5414                                 return ret;
5415                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5416                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5417                         if (items->mask != NULL &&
5418                             ((const struct rte_flow_item_ipv6 *)
5419                              items->mask)->hdr.proto) {
5420                                 item_ipv6_proto =
5421                                         ((const struct rte_flow_item_ipv6 *)
5422                                          items->spec)->hdr.proto;
5423                                 next_protocol =
5424                                         ((const struct rte_flow_item_ipv6 *)
5425                                          items->spec)->hdr.proto;
5426                                 next_protocol &=
5427                                         ((const struct rte_flow_item_ipv6 *)
5428                                          items->mask)->hdr.proto;
5429                         } else {
5430                                 /* Reset for inner layer. */
5431                                 next_protocol = 0xff;
5432                         }
5433                         break;
5434                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5435                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5436                                                                   item_flags,
5437                                                                   error);
5438                         if (ret < 0)
5439                                 return ret;
5440                         last_item = tunnel ?
5441                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5442                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5443                         if (items->mask != NULL &&
5444                             ((const struct rte_flow_item_ipv6_frag_ext *)
5445                              items->mask)->hdr.next_header) {
5446                                 next_protocol =
5447                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5448                                  items->spec)->hdr.next_header;
5449                                 next_protocol &=
5450                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5451                                  items->mask)->hdr.next_header;
5452                         } else {
5453                                 /* Reset for inner layer. */
5454                                 next_protocol = 0xff;
5455                         }
5456                         break;
5457                 case RTE_FLOW_ITEM_TYPE_TCP:
5458                         ret = mlx5_flow_validate_item_tcp
5459                                                 (items, item_flags,
5460                                                  next_protocol,
5461                                                  &nic_tcp_mask,
5462                                                  error);
5463                         if (ret < 0)
5464                                 return ret;
5465                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5466                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5467                         break;
5468                 case RTE_FLOW_ITEM_TYPE_UDP:
5469                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5470                                                           next_protocol,
5471                                                           error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5475                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5476                         break;
5477                 case RTE_FLOW_ITEM_TYPE_GRE:
5478                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5479                                                           next_protocol, error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         gre_item = items;
5483                         last_item = MLX5_FLOW_LAYER_GRE;
5484                         break;
5485                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5486                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5487                                                             next_protocol,
5488                                                             error);
5489                         if (ret < 0)
5490                                 return ret;
5491                         last_item = MLX5_FLOW_LAYER_NVGRE;
5492                         break;
5493                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5494                         ret = mlx5_flow_validate_item_gre_key
5495                                 (items, item_flags, gre_item, error);
5496                         if (ret < 0)
5497                                 return ret;
5498                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5499                         break;
5500                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5501                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5502                                                             error);
5503                         if (ret < 0)
5504                                 return ret;
5505                         last_item = MLX5_FLOW_LAYER_VXLAN;
5506                         break;
5507                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5508                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5509                                                                 item_flags, dev,
5510                                                                 error);
5511                         if (ret < 0)
5512                                 return ret;
5513                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5514                         break;
5515                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5516                         ret = mlx5_flow_validate_item_geneve(items,
5517                                                              item_flags, dev,
5518                                                              error);
5519                         if (ret < 0)
5520                                 return ret;
5521                         last_item = MLX5_FLOW_LAYER_GENEVE;
5522                         break;
5523                 case RTE_FLOW_ITEM_TYPE_MPLS:
5524                         ret = mlx5_flow_validate_item_mpls(dev, items,
5525                                                            item_flags,
5526                                                            last_item, error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         last_item = MLX5_FLOW_LAYER_MPLS;
5530                         break;
5531
5532                 case RTE_FLOW_ITEM_TYPE_MARK:
5533                         ret = flow_dv_validate_item_mark(dev, items, attr,
5534                                                          error);
5535                         if (ret < 0)
5536                                 return ret;
5537                         last_item = MLX5_FLOW_ITEM_MARK;
5538                         break;
5539                 case RTE_FLOW_ITEM_TYPE_META:
5540                         ret = flow_dv_validate_item_meta(dev, items, attr,
5541                                                          error);
5542                         if (ret < 0)
5543                                 return ret;
5544                         last_item = MLX5_FLOW_ITEM_METADATA;
5545                         break;
5546                 case RTE_FLOW_ITEM_TYPE_ICMP:
5547                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5548                                                            next_protocol,
5549                                                            error);
5550                         if (ret < 0)
5551                                 return ret;
5552                         last_item = MLX5_FLOW_LAYER_ICMP;
5553                         break;
5554                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5555                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5556                                                             next_protocol,
5557                                                             error);
5558                         if (ret < 0)
5559                                 return ret;
5560                         item_ipv6_proto = IPPROTO_ICMPV6;
5561                         last_item = MLX5_FLOW_LAYER_ICMP6;
5562                         break;
5563                 case RTE_FLOW_ITEM_TYPE_TAG:
5564                         ret = flow_dv_validate_item_tag(dev, items,
5565                                                         attr, error);
5566                         if (ret < 0)
5567                                 return ret;
5568                         last_item = MLX5_FLOW_ITEM_TAG;
5569                         break;
5570                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5571                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5572                         break;
5573                 case RTE_FLOW_ITEM_TYPE_GTP:
5574                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5575                                                         error);
5576                         if (ret < 0)
5577                                 return ret;
5578                         last_item = MLX5_FLOW_LAYER_GTP;
5579                         break;
5580                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5581                         /* Capacity will be checked in the translate stage. */
5582                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5583                                                             last_item,
5584                                                             ether_type,
5585                                                             &nic_ecpri_mask,
5586                                                             error);
5587                         if (ret < 0)
5588                                 return ret;
5589                         last_item = MLX5_FLOW_LAYER_ECPRI;
5590                         break;
5591                 default:
5592                         return rte_flow_error_set(error, ENOTSUP,
5593                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5594                                                   NULL, "item not supported");
5595                 }
5596                 item_flags |= last_item;
5597         }
5598         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5599                 int type = actions->type;
5600
5601                 if (!mlx5_flow_os_action_supported(type))
5602                         return rte_flow_error_set(error, ENOTSUP,
5603                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5604                                                   actions,
5605                                                   "action not supported");
5606                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5607                         return rte_flow_error_set(error, ENOTSUP,
5608                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5609                                                   actions, "too many actions");
5610                 switch (type) {
5611                 case RTE_FLOW_ACTION_TYPE_VOID:
5612                         break;
5613                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5614                         ret = flow_dv_validate_action_port_id(dev,
5615                                                               action_flags,
5616                                                               actions,
5617                                                               attr,
5618                                                               error);
5619                         if (ret)
5620                                 return ret;
5621                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5622                         ++actions_n;
5623                         break;
5624                 case RTE_FLOW_ACTION_TYPE_FLAG:
5625                         ret = flow_dv_validate_action_flag(dev, action_flags,
5626                                                            attr, error);
5627                         if (ret < 0)
5628                                 return ret;
5629                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5630                                 /* Count all modify-header actions as one. */
5631                                 if (!(action_flags &
5632                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5633                                         ++actions_n;
5634                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5635                                                 MLX5_FLOW_ACTION_MARK_EXT;
5636                         } else {
5637                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5638                                 ++actions_n;
5639                         }
5640                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5641                         break;
5642                 case RTE_FLOW_ACTION_TYPE_MARK:
5643                         ret = flow_dv_validate_action_mark(dev, actions,
5644                                                            action_flags,
5645                                                            attr, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5649                                 /* Count all modify-header actions as one. */
5650                                 if (!(action_flags &
5651                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5652                                         ++actions_n;
5653                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5654                                                 MLX5_FLOW_ACTION_MARK_EXT;
5655                         } else {
5656                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5657                                 ++actions_n;
5658                         }
5659                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5660                         break;
5661                 case RTE_FLOW_ACTION_TYPE_SET_META:
5662                         ret = flow_dv_validate_action_set_meta(dev, actions,
5663                                                                action_flags,
5664                                                                attr, error);
5665                         if (ret < 0)
5666                                 return ret;
5667                         /* Count all modify-header actions as one action. */
5668                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5669                                 ++actions_n;
5670                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5671                         rw_act_num += MLX5_ACT_NUM_SET_META;
5672                         break;
5673                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5674                         ret = flow_dv_validate_action_set_tag(dev, actions,
5675                                                               action_flags,
5676                                                               attr, error);
5677                         if (ret < 0)
5678                                 return ret;
5679                         /* Count all modify-header actions as one action. */
5680                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5681                                 ++actions_n;
5682                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5683                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5684                         break;
5685                 case RTE_FLOW_ACTION_TYPE_DROP:
5686                         ret = mlx5_flow_validate_action_drop(action_flags,
5687                                                              attr, error);
5688                         if (ret < 0)
5689                                 return ret;
5690                         action_flags |= MLX5_FLOW_ACTION_DROP;
5691                         ++actions_n;
5692                         break;
5693                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5694                         ret = mlx5_flow_validate_action_queue(actions,
5695                                                               action_flags, dev,
5696                                                               attr, error);
5697                         if (ret < 0)
5698                                 return ret;
5699                         queue_index = ((const struct rte_flow_action_queue *)
5700                                                         (actions->conf))->index;
5701                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5702                         ++actions_n;
5703                         break;
5704                 case RTE_FLOW_ACTION_TYPE_RSS:
5705                         rss = actions->conf;
5706                         ret = mlx5_flow_validate_action_rss(actions,
5707                                                             action_flags, dev,
5708                                                             attr, item_flags,
5709                                                             error);
5710                         if (ret < 0)
5711                                 return ret;
5712                         if (rss != NULL && rss->queue_num)
5713                                 queue_index = rss->queue[0];
5714                         action_flags |= MLX5_FLOW_ACTION_RSS;
5715                         ++actions_n;
5716                         break;
5717                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5718                         ret =
5719                         mlx5_flow_validate_action_default_miss(action_flags,
5720                                         attr, error);
5721                         if (ret < 0)
5722                                 return ret;
5723                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5724                         ++actions_n;
5725                         break;
5726                 case RTE_FLOW_ACTION_TYPE_COUNT:
5727                         ret = flow_dv_validate_action_count(dev, error);
5728                         if (ret < 0)
5729                                 return ret;
5730                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5731                         ++actions_n;
5732                         break;
5733                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5734                         if (flow_dv_validate_action_pop_vlan(dev,
5735                                                              action_flags,
5736                                                              actions,
5737                                                              item_flags, attr,
5738                                                              error))
5739                                 return -rte_errno;
5740                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5741                         ++actions_n;
5742                         break;
5743                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5744                         ret = flow_dv_validate_action_push_vlan(dev,
5745                                                                 action_flags,
5746                                                                 vlan_m,
5747                                                                 actions, attr,
5748                                                                 error);
5749                         if (ret < 0)
5750                                 return ret;
5751                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5752                         ++actions_n;
5753                         break;
5754                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5755                         ret = flow_dv_validate_action_set_vlan_pcp
5756                                                 (action_flags, actions, error);
5757                         if (ret < 0)
5758                                 return ret;
5759                         /* Count PCP with push_vlan command. */
5760                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5761                         break;
5762                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5763                         ret = flow_dv_validate_action_set_vlan_vid
5764                                                 (item_flags, action_flags,
5765                                                  actions, error);
5766                         if (ret < 0)
5767                                 return ret;
5768                         /* Count VID with push_vlan command. */
5769                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5770                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5771                         break;
5772                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5773                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5774                         ret = flow_dv_validate_action_l2_encap(dev,
5775                                                                action_flags,
5776                                                                actions, attr,
5777                                                                error);
5778                         if (ret < 0)
5779                                 return ret;
5780                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5781                         ++actions_n;
5782                         break;
5783                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5784                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5785                         ret = flow_dv_validate_action_decap(dev, action_flags,
5786                                                             actions, item_flags,
5787                                                             attr, error);
5788                         if (ret < 0)
5789                                 return ret;
5790                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5791                         ++actions_n;
5792                         break;
5793                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5794                         ret = flow_dv_validate_action_raw_encap_decap
5795                                 (dev, NULL, actions->conf, attr, &action_flags,
5796                                  &actions_n, actions, item_flags, error);
5797                         if (ret < 0)
5798                                 return ret;
5799                         break;
5800                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5801                         decap = actions->conf;
5802                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5803                                 ;
5804                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5805                                 encap = NULL;
5806                                 actions--;
5807                         } else {
5808                                 encap = actions->conf;
5809                         }
5810                         ret = flow_dv_validate_action_raw_encap_decap
5811                                            (dev,
5812                                             decap ? decap : &empty_decap, encap,
5813                                             attr, &action_flags, &actions_n,
5814                                             actions, item_flags, error);
5815                         if (ret < 0)
5816                                 return ret;
5817                         break;
5818                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5819                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5820                         ret = flow_dv_validate_action_modify_mac(action_flags,
5821                                                                  actions,
5822                                                                  item_flags,
5823                                                                  error);
5824                         if (ret < 0)
5825                                 return ret;
5826                         /* Count all modify-header actions as one action. */
5827                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5828                                 ++actions_n;
5829                         action_flags |= actions->type ==
5830                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5831                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5832                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5833                         /*
5834                          * Even if the source and destination MAC addresses have
5835                          * overlap in the header with 4B alignment, the convert
5836                          * function will handle them separately and 4 SW actions
5837                          * will be created. And 2 actions will be added each
5838                          * time no matter how many bytes of address will be set.
5839                          */
5840                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5841                         break;
5842                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5843                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5844                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5845                                                                   actions,
5846                                                                   item_flags,
5847                                                                   error);
5848                         if (ret < 0)
5849                                 return ret;
5850                         /* Count all modify-header actions as one action. */
5851                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5852                                 ++actions_n;
5853                         action_flags |= actions->type ==
5854                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5855                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5856                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5857                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5858                         break;
5859                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5860                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5861                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5862                                                                   actions,
5863                                                                   item_flags,
5864                                                                   error);
5865                         if (ret < 0)
5866                                 return ret;
5867                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5868                                 return rte_flow_error_set(error, ENOTSUP,
5869                                         RTE_FLOW_ERROR_TYPE_ACTION,
5870                                         actions,
5871                                         "Can't change header "
5872                                         "with ICMPv6 proto");
5873                         /* Count all modify-header actions as one action. */
5874                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5875                                 ++actions_n;
5876                         action_flags |= actions->type ==
5877                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5878                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5879                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5880                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5881                         break;
5882                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5883                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5884                         ret = flow_dv_validate_action_modify_tp(action_flags,
5885                                                                 actions,
5886                                                                 item_flags,
5887                                                                 error);
5888                         if (ret < 0)
5889                                 return ret;
5890                         /* Count all modify-header actions as one action. */
5891                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5892                                 ++actions_n;
5893                         action_flags |= actions->type ==
5894                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5895                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5896                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5897                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5898                         break;
5899                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5900                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5901                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5902                                                                  actions,
5903                                                                  item_flags,
5904                                                                  error);
5905                         if (ret < 0)
5906                                 return ret;
5907                         /* Count all modify-header actions as one action. */
5908                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5909                                 ++actions_n;
5910                         action_flags |= actions->type ==
5911                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5912                                                 MLX5_FLOW_ACTION_SET_TTL :
5913                                                 MLX5_FLOW_ACTION_DEC_TTL;
5914                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5915                         break;
5916                 case RTE_FLOW_ACTION_TYPE_JUMP:
5917                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5918                                                            action_flags,
5919                                                            attr, external,
5920                                                            error);
5921                         if (ret)
5922                                 return ret;
5923                         ++actions_n;
5924                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5925                         break;
5926                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5927                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5928                         ret = flow_dv_validate_action_modify_tcp_seq
5929                                                                 (action_flags,
5930                                                                  actions,
5931                                                                  item_flags,
5932                                                                  error);
5933                         if (ret < 0)
5934                                 return ret;
5935                         /* Count all modify-header actions as one action. */
5936                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5937                                 ++actions_n;
5938                         action_flags |= actions->type ==
5939                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5940                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5941                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5942                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5943                         break;
5944                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5945                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5946                         ret = flow_dv_validate_action_modify_tcp_ack
5947                                                                 (action_flags,
5948                                                                  actions,
5949                                                                  item_flags,
5950                                                                  error);
5951                         if (ret < 0)
5952                                 return ret;
5953                         /* Count all modify-header actions as one action. */
5954                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5955                                 ++actions_n;
5956                         action_flags |= actions->type ==
5957                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5958                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5959                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5960                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5961                         break;
5962                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5963                         break;
5964                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5965                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5966                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5967                         break;
5968                 case RTE_FLOW_ACTION_TYPE_METER:
5969                         ret = mlx5_flow_validate_action_meter(dev,
5970                                                               action_flags,
5971                                                               actions, attr,
5972                                                               error);
5973                         if (ret < 0)
5974                                 return ret;
5975                         action_flags |= MLX5_FLOW_ACTION_METER;
5976                         ++actions_n;
5977                         /* Meter action will add one more TAG action. */
5978                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5979                         break;
5980                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
5981                         if (!attr->transfer && !attr->group)
5982                                 return rte_flow_error_set(error, ENOTSUP,
5983                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5984                                                                            NULL,
5985                           "Shared ASO age action is not supported for group 0");
5986                         action_flags |= MLX5_FLOW_ACTION_AGE;
5987                         ++actions_n;
5988                         break;
5989                 case RTE_FLOW_ACTION_TYPE_AGE:
5990                         ret = flow_dv_validate_action_age(action_flags,
5991                                                           actions, dev,
5992                                                           error);
5993                         if (ret < 0)
5994                                 return ret;
5995                         action_flags |= MLX5_FLOW_ACTION_AGE;
5996                         ++actions_n;
5997                         break;
5998                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5999                         ret = flow_dv_validate_action_modify_ipv4_dscp
6000                                                          (action_flags,
6001                                                           actions,
6002                                                           item_flags,
6003                                                           error);
6004                         if (ret < 0)
6005                                 return ret;
6006                         /* Count all modify-header actions as one action. */
6007                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6008                                 ++actions_n;
6009                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6010                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6011                         break;
6012                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6013                         ret = flow_dv_validate_action_modify_ipv6_dscp
6014                                                                 (action_flags,
6015                                                                  actions,
6016                                                                  item_flags,
6017                                                                  error);
6018                         if (ret < 0)
6019                                 return ret;
6020                         /* Count all modify-header actions as one action. */
6021                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6022                                 ++actions_n;
6023                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6024                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6025                         break;
6026                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6027                         ret = flow_dv_validate_action_sample(action_flags,
6028                                                              actions, dev,
6029                                                              attr, item_flags,
6030                                                              error);
6031                         if (ret < 0)
6032                                 return ret;
6033                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6034                         ++actions_n;
6035                         break;
6036                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6037                         if (actions[0].type != (typeof(actions[0].type))
6038                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6039                                 return rte_flow_error_set
6040                                                 (error, EINVAL,
6041                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6042                                                 NULL, "MLX5 private action "
6043                                                 "must be the first");
6044
6045                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6046                         break;
6047                 default:
6048                         return rte_flow_error_set(error, ENOTSUP,
6049                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6050                                                   actions,
6051                                                   "action not supported");
6052                 }
6053         }
6054         /*
6055          * Validate actions in flow rules
6056          * - Explicit decap action is prohibited by the tunnel offload API.
6057          * - Drop action in tunnel steer rule is prohibited by the API.
6058          * - Application cannot use MARK action because it's value can mask
6059          *   tunnel default miss nitification.
6060          * - JUMP in tunnel match rule has no support in current PMD
6061          *   implementation.
6062          * - TAG & META are reserved for future uses.
6063          */
6064         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6065                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6066                                             MLX5_FLOW_ACTION_MARK     |
6067                                             MLX5_FLOW_ACTION_SET_TAG  |
6068                                             MLX5_FLOW_ACTION_SET_META |
6069                                             MLX5_FLOW_ACTION_DROP;
6070
6071                 if (action_flags & bad_actions_mask)
6072                         return rte_flow_error_set
6073                                         (error, EINVAL,
6074                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6075                                         "Invalid RTE action in tunnel "
6076                                         "set decap rule");
6077                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6078                         return rte_flow_error_set
6079                                         (error, EINVAL,
6080                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6081                                         "tunnel set decap rule must terminate "
6082                                         "with JUMP");
6083                 if (!attr->ingress)
6084                         return rte_flow_error_set
6085                                         (error, EINVAL,
6086                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6087                                         "tunnel flows for ingress traffic only");
6088         }
6089         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6090                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6091                                             MLX5_FLOW_ACTION_MARK    |
6092                                             MLX5_FLOW_ACTION_SET_TAG |
6093                                             MLX5_FLOW_ACTION_SET_META;
6094
6095                 if (action_flags & bad_actions_mask)
6096                         return rte_flow_error_set
6097                                         (error, EINVAL,
6098                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6099                                         "Invalid RTE action in tunnel "
6100                                         "set match rule");
6101         }
6102         /*
6103          * Validate the drop action mutual exclusion with other actions.
6104          * Drop action is mutually-exclusive with any other action, except for
6105          * Count action.
6106          */
6107         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6108             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6109                 return rte_flow_error_set(error, EINVAL,
6110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6111                                           "Drop action is mutually-exclusive "
6112                                           "with any other action, except for "
6113                                           "Count action");
6114         /* Eswitch has few restrictions on using items and actions */
6115         if (attr->transfer) {
6116                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6117                     action_flags & MLX5_FLOW_ACTION_FLAG)
6118                         return rte_flow_error_set(error, ENOTSUP,
6119                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6120                                                   NULL,
6121                                                   "unsupported action FLAG");
6122                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6123                     action_flags & MLX5_FLOW_ACTION_MARK)
6124                         return rte_flow_error_set(error, ENOTSUP,
6125                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6126                                                   NULL,
6127                                                   "unsupported action MARK");
6128                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6129                         return rte_flow_error_set(error, ENOTSUP,
6130                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6131                                                   NULL,
6132                                                   "unsupported action QUEUE");
6133                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6134                         return rte_flow_error_set(error, ENOTSUP,
6135                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6136                                                   NULL,
6137                                                   "unsupported action RSS");
6138                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6139                         return rte_flow_error_set(error, EINVAL,
6140                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6141                                                   actions,
6142                                                   "no fate action is found");
6143         } else {
6144                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6145                         return rte_flow_error_set(error, EINVAL,
6146                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6147                                                   actions,
6148                                                   "no fate action is found");
6149         }
6150         /*
6151          * Continue validation for Xcap and VLAN actions.
6152          * If hairpin is working in explicit TX rule mode, there is no actions
6153          * splitting and the validation of hairpin ingress flow should be the
6154          * same as other standard flows.
6155          */
6156         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6157                              MLX5_FLOW_VLAN_ACTIONS)) &&
6158             (queue_index == 0xFFFF ||
6159              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6160              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6161              conf->tx_explicit != 0))) {
6162                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6163                     MLX5_FLOW_XCAP_ACTIONS)
6164                         return rte_flow_error_set(error, ENOTSUP,
6165                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6166                                                   NULL, "encap and decap "
6167                                                   "combination aren't supported");
6168                 if (!attr->transfer && attr->ingress) {
6169                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6170                                 return rte_flow_error_set
6171                                                 (error, ENOTSUP,
6172                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6173                                                  NULL, "encap is not supported"
6174                                                  " for ingress traffic");
6175                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6176                                 return rte_flow_error_set
6177                                                 (error, ENOTSUP,
6178                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6179                                                  NULL, "push VLAN action not "
6180                                                  "supported for ingress");
6181                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6182                                         MLX5_FLOW_VLAN_ACTIONS)
6183                                 return rte_flow_error_set
6184                                                 (error, ENOTSUP,
6185                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6186                                                  NULL, "no support for "
6187                                                  "multiple VLAN actions");
6188                 }
6189         }
6190         /*
6191          * Hairpin flow will add one more TAG action in TX implicit mode.
6192          * In TX explicit mode, there will be no hairpin flow ID.
6193          */
6194         if (hairpin > 0)
6195                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6196         /* extra metadata enabled: one more TAG action will be add. */
6197         if (dev_conf->dv_flow_en &&
6198             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6199             mlx5_flow_ext_mreg_supported(dev))
6200                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6201         if ((uint32_t)rw_act_num >
6202                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6203                 return rte_flow_error_set(error, ENOTSUP,
6204                                           RTE_FLOW_ERROR_TYPE_ACTION,
6205                                           NULL, "too many header modify"
6206                                           " actions to support");
6207         }
6208         return 0;
6209 }
6210
6211 /**
6212  * Internal preparation function. Allocates the DV flow size,
6213  * this size is constant.
6214  *
6215  * @param[in] dev
6216  *   Pointer to the rte_eth_dev structure.
6217  * @param[in] attr
6218  *   Pointer to the flow attributes.
6219  * @param[in] items
6220  *   Pointer to the list of items.
6221  * @param[in] actions
6222  *   Pointer to the list of actions.
6223  * @param[out] error
6224  *   Pointer to the error structure.
6225  *
6226  * @return
6227  *   Pointer to mlx5_flow object on success,
6228  *   otherwise NULL and rte_errno is set.
6229  */
6230 static struct mlx5_flow *
6231 flow_dv_prepare(struct rte_eth_dev *dev,
6232                 const struct rte_flow_attr *attr __rte_unused,
6233                 const struct rte_flow_item items[] __rte_unused,
6234                 const struct rte_flow_action actions[] __rte_unused,
6235                 struct rte_flow_error *error)
6236 {
6237         uint32_t handle_idx = 0;
6238         struct mlx5_flow *dev_flow;
6239         struct mlx5_flow_handle *dev_handle;
6240         struct mlx5_priv *priv = dev->data->dev_private;
6241         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6242
6243         MLX5_ASSERT(wks);
6244         /* In case of corrupting the memory. */
6245         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6246                 rte_flow_error_set(error, ENOSPC,
6247                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6248                                    "not free temporary device flow");
6249                 return NULL;
6250         }
6251         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6252                                    &handle_idx);
6253         if (!dev_handle) {
6254                 rte_flow_error_set(error, ENOMEM,
6255                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6256                                    "not enough memory to create flow handle");
6257                 return NULL;
6258         }
6259         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
6260         dev_flow = &wks->flows[wks->flow_idx++];
6261         memset(dev_flow, 0, sizeof(*dev_flow));
6262         dev_flow->handle = dev_handle;
6263         dev_flow->handle_idx = handle_idx;
6264         /*
6265          * In some old rdma-core releases, before continuing, a check of the
6266          * length of matching parameter will be done at first. It needs to use
6267          * the length without misc4 param. If the flow has misc4 support, then
6268          * the length needs to be adjusted accordingly. Each param member is
6269          * aligned with a 64B boundary naturally.
6270          */
6271         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6272                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6273         dev_flow->ingress = attr->ingress;
6274         dev_flow->dv.transfer = attr->transfer;
6275         return dev_flow;
6276 }
6277
6278 #ifdef RTE_LIBRTE_MLX5_DEBUG
6279 /**
6280  * Sanity check for match mask and value. Similar to check_valid_spec() in
6281  * kernel driver. If unmasked bit is present in value, it returns failure.
6282  *
6283  * @param match_mask
6284  *   pointer to match mask buffer.
6285  * @param match_value
6286  *   pointer to match value buffer.
6287  *
6288  * @return
6289  *   0 if valid, -EINVAL otherwise.
6290  */
6291 static int
6292 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6293 {
6294         uint8_t *m = match_mask;
6295         uint8_t *v = match_value;
6296         unsigned int i;
6297
6298         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6299                 if (v[i] & ~m[i]) {
6300                         DRV_LOG(ERR,
6301                                 "match_value differs from match_criteria"
6302                                 " %p[%u] != %p[%u]",
6303                                 match_value, i, match_mask, i);
6304                         return -EINVAL;
6305                 }
6306         }
6307         return 0;
6308 }
6309 #endif
6310
6311 /**
6312  * Add match of ip_version.
6313  *
6314  * @param[in] group
6315  *   Flow group.
6316  * @param[in] headers_v
6317  *   Values header pointer.
6318  * @param[in] headers_m
6319  *   Masks header pointer.
6320  * @param[in] ip_version
6321  *   The IP version to set.
6322  */
6323 static inline void
6324 flow_dv_set_match_ip_version(uint32_t group,
6325                              void *headers_v,
6326                              void *headers_m,
6327                              uint8_t ip_version)
6328 {
6329         if (group == 0)
6330                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6331         else
6332                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6333                          ip_version);
6334         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6335         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6336         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6337 }
6338
6339 /**
6340  * Add Ethernet item to matcher and to the value.
6341  *
6342  * @param[in, out] matcher
6343  *   Flow matcher.
6344  * @param[in, out] key
6345  *   Flow matcher value.
6346  * @param[in] item
6347  *   Flow pattern to translate.
6348  * @param[in] inner
6349  *   Item is inner pattern.
6350  */
6351 static void
6352 flow_dv_translate_item_eth(void *matcher, void *key,
6353                            const struct rte_flow_item *item, int inner,
6354                            uint32_t group)
6355 {
6356         const struct rte_flow_item_eth *eth_m = item->mask;
6357         const struct rte_flow_item_eth *eth_v = item->spec;
6358         const struct rte_flow_item_eth nic_mask = {
6359                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6360                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6361                 .type = RTE_BE16(0xffff),
6362                 .has_vlan = 0,
6363         };
6364         void *hdrs_m;
6365         void *hdrs_v;
6366         char *l24_v;
6367         unsigned int i;
6368
6369         if (!eth_v)
6370                 return;
6371         if (!eth_m)
6372                 eth_m = &nic_mask;
6373         if (inner) {
6374                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6375                                          inner_headers);
6376                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6377         } else {
6378                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6379                                          outer_headers);
6380                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6381         }
6382         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6383                &eth_m->dst, sizeof(eth_m->dst));
6384         /* The value must be in the range of the mask. */
6385         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6386         for (i = 0; i < sizeof(eth_m->dst); ++i)
6387                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6388         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6389                &eth_m->src, sizeof(eth_m->src));
6390         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6391         /* The value must be in the range of the mask. */
6392         for (i = 0; i < sizeof(eth_m->dst); ++i)
6393                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6394         /*
6395          * HW supports match on one Ethertype, the Ethertype following the last
6396          * VLAN tag of the packet (see PRM).
6397          * Set match on ethertype only if ETH header is not followed by VLAN.
6398          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6399          * ethertype, and use ip_version field instead.
6400          * eCPRI over Ether layer will use type value 0xAEFE.
6401          */
6402         if (eth_m->type == 0xFFFF) {
6403                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6404                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6405                 switch (eth_v->type) {
6406                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6407                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6408                         return;
6409                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6410                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6411                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6412                         return;
6413                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6414                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6415                         return;
6416                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6417                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6418                         return;
6419                 default:
6420                         break;
6421                 }
6422         }
6423         if (eth_m->has_vlan) {
6424                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6425                 if (eth_v->has_vlan) {
6426                         /*
6427                          * Here, when also has_more_vlan field in VLAN item is
6428                          * not set, only single-tagged packets will be matched.
6429                          */
6430                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6431                         return;
6432                 }
6433         }
6434         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6435                  rte_be_to_cpu_16(eth_m->type));
6436         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6437         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6438 }
6439
6440 /**
6441  * Add VLAN item to matcher and to the value.
6442  *
6443  * @param[in, out] dev_flow
6444  *   Flow descriptor.
6445  * @param[in, out] matcher
6446  *   Flow matcher.
6447  * @param[in, out] key
6448  *   Flow matcher value.
6449  * @param[in] item
6450  *   Flow pattern to translate.
6451  * @param[in] inner
6452  *   Item is inner pattern.
6453  */
6454 static void
6455 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6456                             void *matcher, void *key,
6457                             const struct rte_flow_item *item,
6458                             int inner, uint32_t group)
6459 {
6460         const struct rte_flow_item_vlan *vlan_m = item->mask;
6461         const struct rte_flow_item_vlan *vlan_v = item->spec;
6462         void *hdrs_m;
6463         void *hdrs_v;
6464         uint16_t tci_m;
6465         uint16_t tci_v;
6466
6467         if (inner) {
6468                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6469                                          inner_headers);
6470                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6471         } else {
6472                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6473                                          outer_headers);
6474                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6475                 /*
6476                  * This is workaround, masks are not supported,
6477                  * and pre-validated.
6478                  */
6479                 if (vlan_v)
6480                         dev_flow->handle->vf_vlan.tag =
6481                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6482         }
6483         /*
6484          * When VLAN item exists in flow, mark packet as tagged,
6485          * even if TCI is not specified.
6486          */
6487         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6488                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6489                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6490         }
6491         if (!vlan_v)
6492                 return;
6493         if (!vlan_m)
6494                 vlan_m = &rte_flow_item_vlan_mask;
6495         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6496         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6497         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6498         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6499         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6500         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6501         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6502         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6503         /*
6504          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6505          * ethertype, and use ip_version field instead.
6506          */
6507         if (vlan_m->inner_type == 0xFFFF) {
6508                 switch (vlan_v->inner_type) {
6509                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6510                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6511                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6512                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6513                         return;
6514                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6515                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6516                         return;
6517                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6518                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6519                         return;
6520                 default:
6521                         break;
6522                 }
6523         }
6524         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6525                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6526                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6527                 /* Only one vlan_tag bit can be set. */
6528                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6529                 return;
6530         }
6531         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6532                  rte_be_to_cpu_16(vlan_m->inner_type));
6533         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6534                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6535 }
6536
6537 /**
6538  * Add IPV4 item to matcher and to the value.
6539  *
6540  * @param[in, out] matcher
6541  *   Flow matcher.
6542  * @param[in, out] key
6543  *   Flow matcher value.
6544  * @param[in] item
6545  *   Flow pattern to translate.
6546  * @param[in] inner
6547  *   Item is inner pattern.
6548  * @param[in] group
6549  *   The group to insert the rule.
6550  */
6551 static void
6552 flow_dv_translate_item_ipv4(void *matcher, void *key,
6553                             const struct rte_flow_item *item,
6554                             int inner, uint32_t group)
6555 {
6556         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6557         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6558         const struct rte_flow_item_ipv4 nic_mask = {
6559                 .hdr = {
6560                         .src_addr = RTE_BE32(0xffffffff),
6561                         .dst_addr = RTE_BE32(0xffffffff),
6562                         .type_of_service = 0xff,
6563                         .next_proto_id = 0xff,
6564                         .time_to_live = 0xff,
6565                 },
6566         };
6567         void *headers_m;
6568         void *headers_v;
6569         char *l24_m;
6570         char *l24_v;
6571         uint8_t tos;
6572
6573         if (inner) {
6574                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6575                                          inner_headers);
6576                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6577         } else {
6578                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6579                                          outer_headers);
6580                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6581         }
6582         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6583         if (!ipv4_v)
6584                 return;
6585         if (!ipv4_m)
6586                 ipv4_m = &nic_mask;
6587         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6588                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6589         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6590                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6591         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6592         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6593         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6594                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6595         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6596                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6597         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6598         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6599         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6600         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6601                  ipv4_m->hdr.type_of_service);
6602         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6603         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6604                  ipv4_m->hdr.type_of_service >> 2);
6605         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6606         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6607                  ipv4_m->hdr.next_proto_id);
6608         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6609                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6610         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6611                  ipv4_m->hdr.time_to_live);
6612         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6613                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6614         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6615                  !!(ipv4_m->hdr.fragment_offset));
6616         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6617                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6618 }
6619
6620 /**
6621  * Add IPV6 item to matcher and to the value.
6622  *
6623  * @param[in, out] matcher
6624  *   Flow matcher.
6625  * @param[in, out] key
6626  *   Flow matcher value.
6627  * @param[in] item
6628  *   Flow pattern to translate.
6629  * @param[in] inner
6630  *   Item is inner pattern.
6631  * @param[in] group
6632  *   The group to insert the rule.
6633  */
6634 static void
6635 flow_dv_translate_item_ipv6(void *matcher, void *key,
6636                             const struct rte_flow_item *item,
6637                             int inner, uint32_t group)
6638 {
6639         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6640         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6641         const struct rte_flow_item_ipv6 nic_mask = {
6642                 .hdr = {
6643                         .src_addr =
6644                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6645                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6646                         .dst_addr =
6647                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6648                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6649                         .vtc_flow = RTE_BE32(0xffffffff),
6650                         .proto = 0xff,
6651                         .hop_limits = 0xff,
6652                 },
6653         };
6654         void *headers_m;
6655         void *headers_v;
6656         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6657         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6658         char *l24_m;
6659         char *l24_v;
6660         uint32_t vtc_m;
6661         uint32_t vtc_v;
6662         int i;
6663         int size;
6664
6665         if (inner) {
6666                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667                                          inner_headers);
6668                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6669         } else {
6670                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6671                                          outer_headers);
6672                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6673         }
6674         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6675         if (!ipv6_v)
6676                 return;
6677         if (!ipv6_m)
6678                 ipv6_m = &nic_mask;
6679         size = sizeof(ipv6_m->hdr.dst_addr);
6680         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6681                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6682         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6683                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6684         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6685         for (i = 0; i < size; ++i)
6686                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6687         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6688                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6689         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6690                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6691         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6692         for (i = 0; i < size; ++i)
6693                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6694         /* TOS. */
6695         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6696         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6697         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6698         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6699         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6700         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6701         /* Label. */
6702         if (inner) {
6703                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6704                          vtc_m);
6705                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6706                          vtc_v);
6707         } else {
6708                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6709                          vtc_m);
6710                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6711                          vtc_v);
6712         }
6713         /* Protocol. */
6714         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6715                  ipv6_m->hdr.proto);
6716         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6717                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6718         /* Hop limit. */
6719         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6720                  ipv6_m->hdr.hop_limits);
6721         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6722                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6723         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6724                  !!(ipv6_m->has_frag_ext));
6725         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6726                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6727 }
6728
6729 /**
6730  * Add IPV6 fragment extension item to matcher and to the value.
6731  *
6732  * @param[in, out] matcher
6733  *   Flow matcher.
6734  * @param[in, out] key
6735  *   Flow matcher value.
6736  * @param[in] item
6737  *   Flow pattern to translate.
6738  * @param[in] inner
6739  *   Item is inner pattern.
6740  */
6741 static void
6742 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6743                                      const struct rte_flow_item *item,
6744                                      int inner)
6745 {
6746         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6747         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6748         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6749                 .hdr = {
6750                         .next_header = 0xff,
6751                         .frag_data = RTE_BE16(0xffff),
6752                 },
6753         };
6754         void *headers_m;
6755         void *headers_v;
6756
6757         if (inner) {
6758                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6759                                          inner_headers);
6760                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6761         } else {
6762                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6763                                          outer_headers);
6764                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6765         }
6766         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6767         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6768         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6769         if (!ipv6_frag_ext_v)
6770                 return;
6771         if (!ipv6_frag_ext_m)
6772                 ipv6_frag_ext_m = &nic_mask;
6773         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6774                  ipv6_frag_ext_m->hdr.next_header);
6775         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6776                  ipv6_frag_ext_v->hdr.next_header &
6777                  ipv6_frag_ext_m->hdr.next_header);
6778 }
6779
6780 /**
6781  * Add TCP item to matcher and to the value.
6782  *
6783  * @param[in, out] matcher
6784  *   Flow matcher.
6785  * @param[in, out] key
6786  *   Flow matcher value.
6787  * @param[in] item
6788  *   Flow pattern to translate.
6789  * @param[in] inner
6790  *   Item is inner pattern.
6791  */
6792 static void
6793 flow_dv_translate_item_tcp(void *matcher, void *key,
6794                            const struct rte_flow_item *item,
6795                            int inner)
6796 {
6797         const struct rte_flow_item_tcp *tcp_m = item->mask;
6798         const struct rte_flow_item_tcp *tcp_v = item->spec;
6799         void *headers_m;
6800         void *headers_v;
6801
6802         if (inner) {
6803                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6804                                          inner_headers);
6805                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6806         } else {
6807                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6808                                          outer_headers);
6809                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6810         }
6811         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6812         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6813         if (!tcp_v)
6814                 return;
6815         if (!tcp_m)
6816                 tcp_m = &rte_flow_item_tcp_mask;
6817         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6818                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6819         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6820                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6821         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6822                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6823         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6824                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6826                  tcp_m->hdr.tcp_flags);
6827         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6828                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6829 }
6830
6831 /**
6832  * Add UDP item to matcher and to the value.
6833  *
6834  * @param[in, out] matcher
6835  *   Flow matcher.
6836  * @param[in, out] key
6837  *   Flow matcher value.
6838  * @param[in] item
6839  *   Flow pattern to translate.
6840  * @param[in] inner
6841  *   Item is inner pattern.
6842  */
6843 static void
6844 flow_dv_translate_item_udp(void *matcher, void *key,
6845                            const struct rte_flow_item *item,
6846                            int inner)
6847 {
6848         const struct rte_flow_item_udp *udp_m = item->mask;
6849         const struct rte_flow_item_udp *udp_v = item->spec;
6850         void *headers_m;
6851         void *headers_v;
6852
6853         if (inner) {
6854                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6855                                          inner_headers);
6856                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6857         } else {
6858                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6859                                          outer_headers);
6860                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6861         }
6862         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6863         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6864         if (!udp_v)
6865                 return;
6866         if (!udp_m)
6867                 udp_m = &rte_flow_item_udp_mask;
6868         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6869                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6870         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6871                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6872         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6873                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6874         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6875                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6876 }
6877
6878 /**
6879  * Add GRE optional Key item to matcher and to the value.
6880  *
6881  * @param[in, out] matcher
6882  *   Flow matcher.
6883  * @param[in, out] key
6884  *   Flow matcher value.
6885  * @param[in] item
6886  *   Flow pattern to translate.
6887  * @param[in] inner
6888  *   Item is inner pattern.
6889  */
6890 static void
6891 flow_dv_translate_item_gre_key(void *matcher, void *key,
6892                                    const struct rte_flow_item *item)
6893 {
6894         const rte_be32_t *key_m = item->mask;
6895         const rte_be32_t *key_v = item->spec;
6896         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6897         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6898         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6899
6900         /* GRE K bit must be on and should already be validated */
6901         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6902         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6903         if (!key_v)
6904                 return;
6905         if (!key_m)
6906                 key_m = &gre_key_default_mask;
6907         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6908                  rte_be_to_cpu_32(*key_m) >> 8);
6909         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6910                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6911         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6912                  rte_be_to_cpu_32(*key_m) & 0xFF);
6913         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6914                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6915 }
6916
6917 /**
6918  * Add GRE item to matcher and to the value.
6919  *
6920  * @param[in, out] matcher
6921  *   Flow matcher.
6922  * @param[in, out] key
6923  *   Flow matcher value.
6924  * @param[in] item
6925  *   Flow pattern to translate.
6926  * @param[in] inner
6927  *   Item is inner pattern.
6928  */
6929 static void
6930 flow_dv_translate_item_gre(void *matcher, void *key,
6931                            const struct rte_flow_item *item,
6932                            int inner)
6933 {
6934         const struct rte_flow_item_gre *gre_m = item->mask;
6935         const struct rte_flow_item_gre *gre_v = item->spec;
6936         void *headers_m;
6937         void *headers_v;
6938         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6939         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6940         struct {
6941                 union {
6942                         __extension__
6943                         struct {
6944                                 uint16_t version:3;
6945                                 uint16_t rsvd0:9;
6946                                 uint16_t s_present:1;
6947                                 uint16_t k_present:1;
6948                                 uint16_t rsvd_bit1:1;
6949                                 uint16_t c_present:1;
6950                         };
6951                         uint16_t value;
6952                 };
6953         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6954
6955         if (inner) {
6956                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6957                                          inner_headers);
6958                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6959         } else {
6960                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6961                                          outer_headers);
6962                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6963         }
6964         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6965         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6966         if (!gre_v)
6967                 return;
6968         if (!gre_m)
6969                 gre_m = &rte_flow_item_gre_mask;
6970         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6971                  rte_be_to_cpu_16(gre_m->protocol));
6972         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6973                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6974         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6975         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6976         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6977                  gre_crks_rsvd0_ver_m.c_present);
6978         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6979                  gre_crks_rsvd0_ver_v.c_present &
6980                  gre_crks_rsvd0_ver_m.c_present);
6981         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6982                  gre_crks_rsvd0_ver_m.k_present);
6983         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6984                  gre_crks_rsvd0_ver_v.k_present &
6985                  gre_crks_rsvd0_ver_m.k_present);
6986         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6987                  gre_crks_rsvd0_ver_m.s_present);
6988         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6989                  gre_crks_rsvd0_ver_v.s_present &
6990                  gre_crks_rsvd0_ver_m.s_present);
6991 }
6992
6993 /**
6994  * Add NVGRE item to matcher and to the value.
6995  *
6996  * @param[in, out] matcher
6997  *   Flow matcher.
6998  * @param[in, out] key
6999  *   Flow matcher value.
7000  * @param[in] item
7001  *   Flow pattern to translate.
7002  * @param[in] inner
7003  *   Item is inner pattern.
7004  */
7005 static void
7006 flow_dv_translate_item_nvgre(void *matcher, void *key,
7007                              const struct rte_flow_item *item,
7008                              int inner)
7009 {
7010         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7011         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7012         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7013         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7014         const char *tni_flow_id_m;
7015         const char *tni_flow_id_v;
7016         char *gre_key_m;
7017         char *gre_key_v;
7018         int size;
7019         int i;
7020
7021         /* For NVGRE, GRE header fields must be set with defined values. */
7022         const struct rte_flow_item_gre gre_spec = {
7023                 .c_rsvd0_ver = RTE_BE16(0x2000),
7024                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7025         };
7026         const struct rte_flow_item_gre gre_mask = {
7027                 .c_rsvd0_ver = RTE_BE16(0xB000),
7028                 .protocol = RTE_BE16(UINT16_MAX),
7029         };
7030         const struct rte_flow_item gre_item = {
7031                 .spec = &gre_spec,
7032                 .mask = &gre_mask,
7033                 .last = NULL,
7034         };
7035         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7036         if (!nvgre_v)
7037                 return;
7038         if (!nvgre_m)
7039                 nvgre_m = &rte_flow_item_nvgre_mask;
7040         tni_flow_id_m = (const char *)nvgre_m->tni;
7041         tni_flow_id_v = (const char *)nvgre_v->tni;
7042         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7043         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7044         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7045         memcpy(gre_key_m, tni_flow_id_m, size);
7046         for (i = 0; i < size; ++i)
7047                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7048 }
7049
7050 /**
7051  * Add VXLAN item to matcher and to the value.
7052  *
7053  * @param[in, out] matcher
7054  *   Flow matcher.
7055  * @param[in, out] key
7056  *   Flow matcher value.
7057  * @param[in] item
7058  *   Flow pattern to translate.
7059  * @param[in] inner
7060  *   Item is inner pattern.
7061  */
7062 static void
7063 flow_dv_translate_item_vxlan(void *matcher, void *key,
7064                              const struct rte_flow_item *item,
7065                              int inner)
7066 {
7067         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7068         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7069         void *headers_m;
7070         void *headers_v;
7071         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7072         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7073         char *vni_m;
7074         char *vni_v;
7075         uint16_t dport;
7076         int size;
7077         int i;
7078
7079         if (inner) {
7080                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7081                                          inner_headers);
7082                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7083         } else {
7084                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7085                                          outer_headers);
7086                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7087         }
7088         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7089                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7090         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7091                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7092                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7093         }
7094         if (!vxlan_v)
7095                 return;
7096         if (!vxlan_m)
7097                 vxlan_m = &rte_flow_item_vxlan_mask;
7098         size = sizeof(vxlan_m->vni);
7099         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7100         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7101         memcpy(vni_m, vxlan_m->vni, size);
7102         for (i = 0; i < size; ++i)
7103                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7104 }
7105
7106 /**
7107  * Add VXLAN-GPE item to matcher and to the value.
7108  *
7109  * @param[in, out] matcher
7110  *   Flow matcher.
7111  * @param[in, out] key
7112  *   Flow matcher value.
7113  * @param[in] item
7114  *   Flow pattern to translate.
7115  * @param[in] inner
7116  *   Item is inner pattern.
7117  */
7118
7119 static void
7120 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7121                                  const struct rte_flow_item *item, int inner)
7122 {
7123         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7124         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7125         void *headers_m;
7126         void *headers_v;
7127         void *misc_m =
7128                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7129         void *misc_v =
7130                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7131         char *vni_m;
7132         char *vni_v;
7133         uint16_t dport;
7134         int size;
7135         int i;
7136         uint8_t flags_m = 0xff;
7137         uint8_t flags_v = 0xc;
7138
7139         if (inner) {
7140                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7141                                          inner_headers);
7142                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7143         } else {
7144                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7145                                          outer_headers);
7146                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7147         }
7148         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7149                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7150         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7151                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7152                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7153         }
7154         if (!vxlan_v)
7155                 return;
7156         if (!vxlan_m)
7157                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7158         size = sizeof(vxlan_m->vni);
7159         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7160         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7161         memcpy(vni_m, vxlan_m->vni, size);
7162         for (i = 0; i < size; ++i)
7163                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7164         if (vxlan_m->flags) {
7165                 flags_m = vxlan_m->flags;
7166                 flags_v = vxlan_v->flags;
7167         }
7168         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7169         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7170         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7171                  vxlan_m->protocol);
7172         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7173                  vxlan_v->protocol);
7174 }
7175
7176 /**
7177  * Add Geneve item to matcher and to the value.
7178  *
7179  * @param[in, out] matcher
7180  *   Flow matcher.
7181  * @param[in, out] key
7182  *   Flow matcher value.
7183  * @param[in] item
7184  *   Flow pattern to translate.
7185  * @param[in] inner
7186  *   Item is inner pattern.
7187  */
7188
7189 static void
7190 flow_dv_translate_item_geneve(void *matcher, void *key,
7191                               const struct rte_flow_item *item, int inner)
7192 {
7193         const struct rte_flow_item_geneve *geneve_m = item->mask;
7194         const struct rte_flow_item_geneve *geneve_v = item->spec;
7195         void *headers_m;
7196         void *headers_v;
7197         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7198         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7199         uint16_t dport;
7200         uint16_t gbhdr_m;
7201         uint16_t gbhdr_v;
7202         char *vni_m;
7203         char *vni_v;
7204         size_t size, i;
7205
7206         if (inner) {
7207                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7208                                          inner_headers);
7209                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7210         } else {
7211                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7212                                          outer_headers);
7213                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7214         }
7215         dport = MLX5_UDP_PORT_GENEVE;
7216         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7217                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7218                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7219         }
7220         if (!geneve_v)
7221                 return;
7222         if (!geneve_m)
7223                 geneve_m = &rte_flow_item_geneve_mask;
7224         size = sizeof(geneve_m->vni);
7225         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7226         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7227         memcpy(vni_m, geneve_m->vni, size);
7228         for (i = 0; i < size; ++i)
7229                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7230         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7231                  rte_be_to_cpu_16(geneve_m->protocol));
7232         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7233                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7234         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7235         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7236         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7237                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7238         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7239                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7240         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7241                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7242         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7243                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7244                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7245 }
7246
7247 /**
7248  * Add MPLS item to matcher and to the value.
7249  *
7250  * @param[in, out] matcher
7251  *   Flow matcher.
7252  * @param[in, out] key
7253  *   Flow matcher value.
7254  * @param[in] item
7255  *   Flow pattern to translate.
7256  * @param[in] prev_layer
7257  *   The protocol layer indicated in previous item.
7258  * @param[in] inner
7259  *   Item is inner pattern.
7260  */
7261 static void
7262 flow_dv_translate_item_mpls(void *matcher, void *key,
7263                             const struct rte_flow_item *item,
7264                             uint64_t prev_layer,
7265                             int inner)
7266 {
7267         const uint32_t *in_mpls_m = item->mask;
7268         const uint32_t *in_mpls_v = item->spec;
7269         uint32_t *out_mpls_m = 0;
7270         uint32_t *out_mpls_v = 0;
7271         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7272         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7273         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7274                                      misc_parameters_2);
7275         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7276         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7277         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7278
7279         switch (prev_layer) {
7280         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7281                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7282                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7283                          MLX5_UDP_PORT_MPLS);
7284                 break;
7285         case MLX5_FLOW_LAYER_GRE:
7286                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7287                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7288                          RTE_ETHER_TYPE_MPLS);
7289                 break;
7290         default:
7291                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7292                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7293                          IPPROTO_MPLS);
7294                 break;
7295         }
7296         if (!in_mpls_v)
7297                 return;
7298         if (!in_mpls_m)
7299                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7300         switch (prev_layer) {
7301         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7302                 out_mpls_m =
7303                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7304                                                  outer_first_mpls_over_udp);
7305                 out_mpls_v =
7306                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7307                                                  outer_first_mpls_over_udp);
7308                 break;
7309         case MLX5_FLOW_LAYER_GRE:
7310                 out_mpls_m =
7311                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7312                                                  outer_first_mpls_over_gre);
7313                 out_mpls_v =
7314                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7315                                                  outer_first_mpls_over_gre);
7316                 break;
7317         default:
7318                 /* Inner MPLS not over GRE is not supported. */
7319                 if (!inner) {
7320                         out_mpls_m =
7321                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7322                                                          misc2_m,
7323                                                          outer_first_mpls);
7324                         out_mpls_v =
7325                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7326                                                          misc2_v,
7327                                                          outer_first_mpls);
7328                 }
7329                 break;
7330         }
7331         if (out_mpls_m && out_mpls_v) {
7332                 *out_mpls_m = *in_mpls_m;
7333                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7334         }
7335 }
7336
7337 /**
7338  * Add metadata register item to matcher
7339  *
7340  * @param[in, out] matcher
7341  *   Flow matcher.
7342  * @param[in, out] key
7343  *   Flow matcher value.
7344  * @param[in] reg_type
7345  *   Type of device metadata register
7346  * @param[in] value
7347  *   Register value
7348  * @param[in] mask
7349  *   Register mask
7350  */
7351 static void
7352 flow_dv_match_meta_reg(void *matcher, void *key,
7353                        enum modify_reg reg_type,
7354                        uint32_t data, uint32_t mask)
7355 {
7356         void *misc2_m =
7357                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7358         void *misc2_v =
7359                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7360         uint32_t temp;
7361
7362         data &= mask;
7363         switch (reg_type) {
7364         case REG_A:
7365                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7366                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7367                 break;
7368         case REG_B:
7369                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7370                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7371                 break;
7372         case REG_C_0:
7373                 /*
7374                  * The metadata register C0 field might be divided into
7375                  * source vport index and META item value, we should set
7376                  * this field according to specified mask, not as whole one.
7377                  */
7378                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7379                 temp |= mask;
7380                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7381                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7382                 temp &= ~mask;
7383                 temp |= data;
7384                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7385                 break;
7386         case REG_C_1:
7387                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7388                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7389                 break;
7390         case REG_C_2:
7391                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7392                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7393                 break;
7394         case REG_C_3:
7395                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7396                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7397                 break;
7398         case REG_C_4:
7399                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7400                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7401                 break;
7402         case REG_C_5:
7403                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7404                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7405                 break;
7406         case REG_C_6:
7407                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7408                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7409                 break;
7410         case REG_C_7:
7411                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7412                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7413                 break;
7414         default:
7415                 MLX5_ASSERT(false);
7416                 break;
7417         }
7418 }
7419
7420 /**
7421  * Add MARK item to matcher
7422  *
7423  * @param[in] dev
7424  *   The device to configure through.
7425  * @param[in, out] matcher
7426  *   Flow matcher.
7427  * @param[in, out] key
7428  *   Flow matcher value.
7429  * @param[in] item
7430  *   Flow pattern to translate.
7431  */
7432 static void
7433 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7434                             void *matcher, void *key,
7435                             const struct rte_flow_item *item)
7436 {
7437         struct mlx5_priv *priv = dev->data->dev_private;
7438         const struct rte_flow_item_mark *mark;
7439         uint32_t value;
7440         uint32_t mask;
7441
7442         mark = item->mask ? (const void *)item->mask :
7443                             &rte_flow_item_mark_mask;
7444         mask = mark->id & priv->sh->dv_mark_mask;
7445         mark = (const void *)item->spec;
7446         MLX5_ASSERT(mark);
7447         value = mark->id & priv->sh->dv_mark_mask & mask;
7448         if (mask) {
7449                 enum modify_reg reg;
7450
7451                 /* Get the metadata register index for the mark. */
7452                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7453                 MLX5_ASSERT(reg > 0);
7454                 if (reg == REG_C_0) {
7455                         struct mlx5_priv *priv = dev->data->dev_private;
7456                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7457                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7458
7459                         mask &= msk_c0;
7460                         mask <<= shl_c0;
7461                         value <<= shl_c0;
7462                 }
7463                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7464         }
7465 }
7466
7467 /**
7468  * Add META item to matcher
7469  *
7470  * @param[in] dev
7471  *   The devich to configure through.
7472  * @param[in, out] matcher
7473  *   Flow matcher.
7474  * @param[in, out] key
7475  *   Flow matcher value.
7476  * @param[in] attr
7477  *   Attributes of flow that includes this item.
7478  * @param[in] item
7479  *   Flow pattern to translate.
7480  */
7481 static void
7482 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7483                             void *matcher, void *key,
7484                             const struct rte_flow_attr *attr,
7485                             const struct rte_flow_item *item)
7486 {
7487         const struct rte_flow_item_meta *meta_m;
7488         const struct rte_flow_item_meta *meta_v;
7489
7490         meta_m = (const void *)item->mask;
7491         if (!meta_m)
7492                 meta_m = &rte_flow_item_meta_mask;
7493         meta_v = (const void *)item->spec;
7494         if (meta_v) {
7495                 int reg;
7496                 uint32_t value = meta_v->data;
7497                 uint32_t mask = meta_m->data;
7498
7499                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7500                 if (reg < 0)
7501                         return;
7502                 MLX5_ASSERT(reg != REG_NON);
7503                 /*
7504                  * In datapath code there is no endianness
7505                  * coversions for perfromance reasons, all
7506                  * pattern conversions are done in rte_flow.
7507                  */
7508                 value = rte_cpu_to_be_32(value);
7509                 mask = rte_cpu_to_be_32(mask);
7510                 if (reg == REG_C_0) {
7511                         struct mlx5_priv *priv = dev->data->dev_private;
7512                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7513                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7514 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7515                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7516
7517                         value >>= shr_c0;
7518                         mask >>= shr_c0;
7519 #endif
7520                         value <<= shl_c0;
7521                         mask <<= shl_c0;
7522                         MLX5_ASSERT(msk_c0);
7523                         MLX5_ASSERT(!(~msk_c0 & mask));
7524                 }
7525                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7526         }
7527 }
7528
7529 /**
7530  * Add vport metadata Reg C0 item to matcher
7531  *
7532  * @param[in, out] matcher
7533  *   Flow matcher.
7534  * @param[in, out] key
7535  *   Flow matcher value.
7536  * @param[in] reg
7537  *   Flow pattern to translate.
7538  */
7539 static void
7540 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7541                                   uint32_t value, uint32_t mask)
7542 {
7543         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7544 }
7545
7546 /**
7547  * Add tag item to matcher
7548  *
7549  * @param[in] dev
7550  *   The devich to configure through.
7551  * @param[in, out] matcher
7552  *   Flow matcher.
7553  * @param[in, out] key
7554  *   Flow matcher value.
7555  * @param[in] item
7556  *   Flow pattern to translate.
7557  */
7558 static void
7559 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7560                                 void *matcher, void *key,
7561                                 const struct rte_flow_item *item)
7562 {
7563         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7564         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7565         uint32_t mask, value;
7566
7567         MLX5_ASSERT(tag_v);
7568         value = tag_v->data;
7569         mask = tag_m ? tag_m->data : UINT32_MAX;
7570         if (tag_v->id == REG_C_0) {
7571                 struct mlx5_priv *priv = dev->data->dev_private;
7572                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7573                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7574
7575                 mask &= msk_c0;
7576                 mask <<= shl_c0;
7577                 value <<= shl_c0;
7578         }
7579         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7580 }
7581
7582 /**
7583  * Add TAG item to matcher
7584  *
7585  * @param[in] dev
7586  *   The devich to configure through.
7587  * @param[in, out] matcher
7588  *   Flow matcher.
7589  * @param[in, out] key
7590  *   Flow matcher value.
7591  * @param[in] item
7592  *   Flow pattern to translate.
7593  */
7594 static void
7595 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7596                            void *matcher, void *key,
7597                            const struct rte_flow_item *item)
7598 {
7599         const struct rte_flow_item_tag *tag_v = item->spec;
7600         const struct rte_flow_item_tag *tag_m = item->mask;
7601         enum modify_reg reg;
7602
7603         MLX5_ASSERT(tag_v);
7604         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7605         /* Get the metadata register index for the tag. */
7606         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7607         MLX5_ASSERT(reg > 0);
7608         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7609 }
7610
7611 /**
7612  * Add source vport match to the specified matcher.
7613  *
7614  * @param[in, out] matcher
7615  *   Flow matcher.
7616  * @param[in, out] key
7617  *   Flow matcher value.
7618  * @param[in] port
7619  *   Source vport value to match
7620  * @param[in] mask
7621  *   Mask
7622  */
7623 static void
7624 flow_dv_translate_item_source_vport(void *matcher, void *key,
7625                                     int16_t port, uint16_t mask)
7626 {
7627         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7628         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7629
7630         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7631         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7632 }
7633
7634 /**
7635  * Translate port-id item to eswitch match on  port-id.
7636  *
7637  * @param[in] dev
7638  *   The devich to configure through.
7639  * @param[in, out] matcher
7640  *   Flow matcher.
7641  * @param[in, out] key
7642  *   Flow matcher value.
7643  * @param[in] item
7644  *   Flow pattern to translate.
7645  * @param[in]
7646  *   Flow attributes.
7647  *
7648  * @return
7649  *   0 on success, a negative errno value otherwise.
7650  */
7651 static int
7652 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7653                                void *key, const struct rte_flow_item *item,
7654                                const struct rte_flow_attr *attr)
7655 {
7656         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7657         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7658         struct mlx5_priv *priv;
7659         uint16_t mask, id;
7660
7661         mask = pid_m ? pid_m->id : 0xffff;
7662         id = pid_v ? pid_v->id : dev->data->port_id;
7663         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7664         if (!priv)
7665                 return -rte_errno;
7666         /*
7667          * Translate to vport field or to metadata, depending on mode.
7668          * Kernel can use either misc.source_port or half of C0 metadata
7669          * register.
7670          */
7671         if (priv->vport_meta_mask) {
7672                 /*
7673                  * Provide the hint for SW steering library
7674                  * to insert the flow into ingress domain and
7675                  * save the extra vport match.
7676                  */
7677                 if (mask == 0xffff && priv->vport_id == 0xffff &&
7678                     priv->pf_bond < 0 && attr->transfer)
7679                         flow_dv_translate_item_source_vport
7680                                 (matcher, key, priv->vport_id, mask);
7681                 else
7682                         flow_dv_translate_item_meta_vport
7683                                 (matcher, key,
7684                                  priv->vport_meta_tag,
7685                                  priv->vport_meta_mask);
7686         } else {
7687                 flow_dv_translate_item_source_vport(matcher, key,
7688                                                     priv->vport_id, mask);
7689         }
7690         return 0;
7691 }
7692
7693 /**
7694  * Add ICMP6 item to matcher and to the value.
7695  *
7696  * @param[in, out] matcher
7697  *   Flow matcher.
7698  * @param[in, out] key
7699  *   Flow matcher value.
7700  * @param[in] item
7701  *   Flow pattern to translate.
7702  * @param[in] inner
7703  *   Item is inner pattern.
7704  */
7705 static void
7706 flow_dv_translate_item_icmp6(void *matcher, void *key,
7707                               const struct rte_flow_item *item,
7708                               int inner)
7709 {
7710         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7711         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7712         void *headers_m;
7713         void *headers_v;
7714         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7715                                      misc_parameters_3);
7716         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7717         if (inner) {
7718                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7719                                          inner_headers);
7720                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7721         } else {
7722                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7723                                          outer_headers);
7724                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7725         }
7726         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7727         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7728         if (!icmp6_v)
7729                 return;
7730         if (!icmp6_m)
7731                 icmp6_m = &rte_flow_item_icmp6_mask;
7732         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7733         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7734                  icmp6_v->type & icmp6_m->type);
7735         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7736         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7737                  icmp6_v->code & icmp6_m->code);
7738 }
7739
7740 /**
7741  * Add ICMP item to matcher and to the value.
7742  *
7743  * @param[in, out] matcher
7744  *   Flow matcher.
7745  * @param[in, out] key
7746  *   Flow matcher value.
7747  * @param[in] item
7748  *   Flow pattern to translate.
7749  * @param[in] inner
7750  *   Item is inner pattern.
7751  */
7752 static void
7753 flow_dv_translate_item_icmp(void *matcher, void *key,
7754                             const struct rte_flow_item *item,
7755                             int inner)
7756 {
7757         const struct rte_flow_item_icmp *icmp_m = item->mask;
7758         const struct rte_flow_item_icmp *icmp_v = item->spec;
7759         uint32_t icmp_header_data_m = 0;
7760         uint32_t icmp_header_data_v = 0;
7761         void *headers_m;
7762         void *headers_v;
7763         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7764                                      misc_parameters_3);
7765         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7766         if (inner) {
7767                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7768                                          inner_headers);
7769                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7770         } else {
7771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7772                                          outer_headers);
7773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7774         }
7775         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7777         if (!icmp_v)
7778                 return;
7779         if (!icmp_m)
7780                 icmp_m = &rte_flow_item_icmp_mask;
7781         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7782                  icmp_m->hdr.icmp_type);
7783         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7784                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7785         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7786                  icmp_m->hdr.icmp_code);
7787         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7788                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7789         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7790         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7791         if (icmp_header_data_m) {
7792                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7793                 icmp_header_data_v |=
7794                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7795                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7796                          icmp_header_data_m);
7797                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7798                          icmp_header_data_v & icmp_header_data_m);
7799         }
7800 }
7801
7802 /**
7803  * Add GTP item to matcher and to the value.
7804  *
7805  * @param[in, out] matcher
7806  *   Flow matcher.
7807  * @param[in, out] key
7808  *   Flow matcher value.
7809  * @param[in] item
7810  *   Flow pattern to translate.
7811  * @param[in] inner
7812  *   Item is inner pattern.
7813  */
7814 static void
7815 flow_dv_translate_item_gtp(void *matcher, void *key,
7816                            const struct rte_flow_item *item, int inner)
7817 {
7818         const struct rte_flow_item_gtp *gtp_m = item->mask;
7819         const struct rte_flow_item_gtp *gtp_v = item->spec;
7820         void *headers_m;
7821         void *headers_v;
7822         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7823                                      misc_parameters_3);
7824         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7825         uint16_t dport = RTE_GTPU_UDP_PORT;
7826
7827         if (inner) {
7828                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7829                                          inner_headers);
7830                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7831         } else {
7832                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7833                                          outer_headers);
7834                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7835         }
7836         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7837                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7838                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7839         }
7840         if (!gtp_v)
7841                 return;
7842         if (!gtp_m)
7843                 gtp_m = &rte_flow_item_gtp_mask;
7844         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7845                  gtp_m->v_pt_rsv_flags);
7846         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7847                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7848         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7849         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7850                  gtp_v->msg_type & gtp_m->msg_type);
7851         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7852                  rte_be_to_cpu_32(gtp_m->teid));
7853         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7854                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7855 }
7856
7857 /**
7858  * Add eCPRI item to matcher and to the value.
7859  *
7860  * @param[in] dev
7861  *   The devich to configure through.
7862  * @param[in, out] matcher
7863  *   Flow matcher.
7864  * @param[in, out] key
7865  *   Flow matcher value.
7866  * @param[in] item
7867  *   Flow pattern to translate.
7868  * @param[in] samples
7869  *   Sample IDs to be used in the matching.
7870  */
7871 static void
7872 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7873                              void *key, const struct rte_flow_item *item)
7874 {
7875         struct mlx5_priv *priv = dev->data->dev_private;
7876         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7877         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7878         struct rte_ecpri_common_hdr common;
7879         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7880                                      misc_parameters_4);
7881         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7882         uint32_t *samples;
7883         void *dw_m;
7884         void *dw_v;
7885
7886         if (!ecpri_v)
7887                 return;
7888         if (!ecpri_m)
7889                 ecpri_m = &rte_flow_item_ecpri_mask;
7890         /*
7891          * Maximal four DW samples are supported in a single matching now.
7892          * Two are used now for a eCPRI matching:
7893          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7894          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7895          *    if any.
7896          */
7897         if (!ecpri_m->hdr.common.u32)
7898                 return;
7899         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7900         /* Need to take the whole DW as the mask to fill the entry. */
7901         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7902                             prog_sample_field_value_0);
7903         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7904                             prog_sample_field_value_0);
7905         /* Already big endian (network order) in the header. */
7906         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7907         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
7908         /* Sample#0, used for matching type, offset 0. */
7909         MLX5_SET(fte_match_set_misc4, misc4_m,
7910                  prog_sample_field_id_0, samples[0]);
7911         /* It makes no sense to set the sample ID in the mask field. */
7912         MLX5_SET(fte_match_set_misc4, misc4_v,
7913                  prog_sample_field_id_0, samples[0]);
7914         /*
7915          * Checking if message body part needs to be matched.
7916          * Some wildcard rules only matching type field should be supported.
7917          */
7918         if (ecpri_m->hdr.dummy[0]) {
7919                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
7920                 switch (common.type) {
7921                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7922                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7923                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7924                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7925                                             prog_sample_field_value_1);
7926                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7927                                             prog_sample_field_value_1);
7928                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7929                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
7930                                             ecpri_m->hdr.dummy[0];
7931                         /* Sample#1, to match message body, offset 4. */
7932                         MLX5_SET(fte_match_set_misc4, misc4_m,
7933                                  prog_sample_field_id_1, samples[1]);
7934                         MLX5_SET(fte_match_set_misc4, misc4_v,
7935                                  prog_sample_field_id_1, samples[1]);
7936                         break;
7937                 default:
7938                         /* Others, do not match any sample ID. */
7939                         break;
7940                 }
7941         }
7942 }
7943
7944 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7945
7946 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7947         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7948                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7949
7950 /**
7951  * Calculate flow matcher enable bitmap.
7952  *
7953  * @param match_criteria
7954  *   Pointer to flow matcher criteria.
7955  *
7956  * @return
7957  *   Bitmap of enabled fields.
7958  */
7959 static uint8_t
7960 flow_dv_matcher_enable(uint32_t *match_criteria)
7961 {
7962         uint8_t match_criteria_enable;
7963
7964         match_criteria_enable =
7965                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7966                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7967         match_criteria_enable |=
7968                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7969                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7970         match_criteria_enable |=
7971                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7972                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7973         match_criteria_enable |=
7974                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7975                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7976         match_criteria_enable |=
7977                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7978                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7979         match_criteria_enable |=
7980                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7981                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7982         return match_criteria_enable;
7983 }
7984
7985 struct mlx5_hlist_entry *
7986 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
7987 {
7988         struct mlx5_dev_ctx_shared *sh = list->ctx;
7989         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
7990         struct rte_eth_dev *dev = ctx->dev;
7991         struct mlx5_flow_tbl_data_entry *tbl_data;
7992         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
7993         struct rte_flow_error *error = ctx->error;
7994         union mlx5_flow_tbl_key key = { .v64 = key64 };
7995         struct mlx5_flow_tbl_resource *tbl;
7996         void *domain;
7997         uint32_t idx = 0;
7998         int ret;
7999
8000         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8001         if (!tbl_data) {
8002                 rte_flow_error_set(error, ENOMEM,
8003                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8004                                    NULL,
8005                                    "cannot allocate flow table data entry");
8006                 return NULL;
8007         }
8008         tbl_data->idx = idx;
8009         tbl_data->tunnel = tt_prm->tunnel;
8010         tbl_data->group_id = tt_prm->group_id;
8011         tbl_data->external = !!tt_prm->external;
8012         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
8013         tbl_data->is_egress = !!key.direction;
8014         tbl_data->is_transfer = !!key.domain;
8015         tbl_data->dummy = !!key.dummy;
8016         tbl_data->table_id = key.table_id;
8017         tbl = &tbl_data->tbl;
8018         if (key.dummy)
8019                 return &tbl_data->entry;
8020         if (key.domain)
8021                 domain = sh->fdb_domain;
8022         else if (key.direction)
8023                 domain = sh->tx_domain;
8024         else
8025                 domain = sh->rx_domain;
8026         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
8027         if (ret) {
8028                 rte_flow_error_set(error, ENOMEM,
8029                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8030                                    NULL, "cannot create flow table object");
8031                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8032                 return NULL;
8033         }
8034         if (key.table_id) {
8035                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8036                                         (tbl->obj, &tbl_data->jump.action);
8037                 if (ret) {
8038                         rte_flow_error_set(error, ENOMEM,
8039                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8040                                            NULL,
8041                                            "cannot create flow jump action");
8042                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8043                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8044                         return NULL;
8045                 }
8046         }
8047         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
8048               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
8049               key.table_id);
8050         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
8051                              flow_dv_matcher_create_cb,
8052                              flow_dv_matcher_match_cb,
8053                              flow_dv_matcher_remove_cb);
8054         return &tbl_data->entry;
8055 }
8056
8057 int
8058 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
8059                      struct mlx5_hlist_entry *entry, uint64_t key64,
8060                      void *cb_ctx __rte_unused)
8061 {
8062         struct mlx5_flow_tbl_data_entry *tbl_data =
8063                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8064         union mlx5_flow_tbl_key key = { .v64 = key64 };
8065
8066         return tbl_data->table_id != key.table_id ||
8067                tbl_data->dummy != key.dummy ||
8068                tbl_data->is_transfer != key.domain ||
8069                tbl_data->is_egress != key.direction;
8070 }
8071
8072 /**
8073  * Get a flow table.
8074  *
8075  * @param[in, out] dev
8076  *   Pointer to rte_eth_dev structure.
8077  * @param[in] table_id
8078  *   Table id to use.
8079  * @param[in] egress
8080  *   Direction of the table.
8081  * @param[in] transfer
8082  *   E-Switch or NIC flow.
8083  * @param[in] dummy
8084  *   Dummy entry for dv API.
8085  * @param[out] error
8086  *   pointer to error structure.
8087  *
8088  * @return
8089  *   Returns tables resource based on the index, NULL in case of failed.
8090  */
8091 struct mlx5_flow_tbl_resource *
8092 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8093                          uint32_t table_id, uint8_t egress,
8094                          uint8_t transfer,
8095                          bool external,
8096                          const struct mlx5_flow_tunnel *tunnel,
8097                          uint32_t group_id, uint8_t dummy,
8098                          struct rte_flow_error *error)
8099 {
8100         struct mlx5_priv *priv = dev->data->dev_private;
8101         union mlx5_flow_tbl_key table_key = {
8102                 {
8103                         .table_id = table_id,
8104                         .dummy = dummy,
8105                         .domain = !!transfer,
8106                         .direction = !!egress,
8107                 }
8108         };
8109         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8110                 .tunnel = tunnel,
8111                 .group_id = group_id,
8112                 .external = external,
8113         };
8114         struct mlx5_flow_cb_ctx ctx = {
8115                 .dev = dev,
8116                 .error = error,
8117                 .data = &tt_prm,
8118         };
8119         struct mlx5_hlist_entry *entry;
8120         struct mlx5_flow_tbl_data_entry *tbl_data;
8121
8122         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8123         if (!entry) {
8124                 rte_flow_error_set(error, ENOMEM,
8125                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8126                                    "cannot get table");
8127                 return NULL;
8128         }
8129         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
8130                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
8131         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8132         return &tbl_data->tbl;
8133 }
8134
8135 void
8136 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8137                       struct mlx5_hlist_entry *entry)
8138 {
8139         struct mlx5_dev_ctx_shared *sh = list->ctx;
8140         struct mlx5_flow_tbl_data_entry *tbl_data =
8141                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8142
8143         MLX5_ASSERT(entry && sh);
8144         if (tbl_data->jump.action)
8145                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8146         if (tbl_data->tbl.obj)
8147                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8148         if (tbl_data->tunnel_offload && tbl_data->external) {
8149                 struct mlx5_hlist_entry *he;
8150                 struct mlx5_hlist *tunnel_grp_hash;
8151                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8152                 union tunnel_tbl_key tunnel_key = {
8153                         .tunnel_id = tbl_data->tunnel ?
8154                                         tbl_data->tunnel->tunnel_id : 0,
8155                         .group = tbl_data->group_id
8156                 };
8157                 uint32_t table_id = tbl_data->table_id;
8158
8159                 tunnel_grp_hash = tbl_data->tunnel ?
8160                                         tbl_data->tunnel->groups :
8161                                         thub->groups;
8162                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8163                 if (he)
8164                         mlx5_hlist_unregister(tunnel_grp_hash, he);
8165                 DRV_LOG(DEBUG,
8166                         "Table_id %u tunnel %u group %u released.",
8167                         table_id,
8168                         tbl_data->tunnel ?
8169                         tbl_data->tunnel->tunnel_id : 0,
8170                         tbl_data->group_id);
8171         }
8172         mlx5_cache_list_destroy(&tbl_data->matchers);
8173         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8174 }
8175
8176 /**
8177  * Release a flow table.
8178  *
8179  * @param[in] sh
8180  *   Pointer to device shared structure.
8181  * @param[in] tbl
8182  *   Table resource to be released.
8183  *
8184  * @return
8185  *   Returns 0 if table was released, else return 1;
8186  */
8187 static int
8188 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
8189                              struct mlx5_flow_tbl_resource *tbl)
8190 {
8191         struct mlx5_flow_tbl_data_entry *tbl_data =
8192                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8193
8194         if (!tbl)
8195                 return 0;
8196         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8197 }
8198
8199 int
8200 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
8201                          struct mlx5_cache_entry *entry, void *cb_ctx)
8202 {
8203         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8204         struct mlx5_flow_dv_matcher *ref = ctx->data;
8205         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
8206                                                         entry);
8207
8208         return cur->crc != ref->crc ||
8209                cur->priority != ref->priority ||
8210                memcmp((const void *)cur->mask.buf,
8211                       (const void *)ref->mask.buf, ref->mask.size);
8212 }
8213
8214 struct mlx5_cache_entry *
8215 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
8216                           struct mlx5_cache_entry *entry __rte_unused,
8217                           void *cb_ctx)
8218 {
8219         struct mlx5_dev_ctx_shared *sh = list->ctx;
8220         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8221         struct mlx5_flow_dv_matcher *ref = ctx->data;
8222         struct mlx5_flow_dv_matcher *cache;
8223         struct mlx5dv_flow_matcher_attr dv_attr = {
8224                 .type = IBV_FLOW_ATTR_NORMAL,
8225                 .match_mask = (void *)&ref->mask,
8226         };
8227         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
8228                                                             typeof(*tbl), tbl);
8229         int ret;
8230
8231         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
8232         if (!cache) {
8233                 rte_flow_error_set(ctx->error, ENOMEM,
8234                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8235                                    "cannot create matcher");
8236                 return NULL;
8237         }
8238         *cache = *ref;
8239         dv_attr.match_criteria_enable =
8240                 flow_dv_matcher_enable(cache->mask.buf);
8241         dv_attr.priority = ref->priority;
8242         if (tbl->is_egress)
8243                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8244         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
8245                                                &cache->matcher_object);
8246         if (ret) {
8247                 mlx5_free(cache);
8248                 rte_flow_error_set(ctx->error, ENOMEM,
8249                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8250                                    "cannot create matcher");
8251                 return NULL;
8252         }
8253         return &cache->entry;
8254 }
8255
8256 /**
8257  * Register the flow matcher.
8258  *
8259  * @param[in, out] dev
8260  *   Pointer to rte_eth_dev structure.
8261  * @param[in, out] matcher
8262  *   Pointer to flow matcher.
8263  * @param[in, out] key
8264  *   Pointer to flow table key.
8265  * @parm[in, out] dev_flow
8266  *   Pointer to the dev_flow.
8267  * @param[out] error
8268  *   pointer to error structure.
8269  *
8270  * @return
8271  *   0 on success otherwise -errno and errno is set.
8272  */
8273 static int
8274 flow_dv_matcher_register(struct rte_eth_dev *dev,
8275                          struct mlx5_flow_dv_matcher *ref,
8276                          union mlx5_flow_tbl_key *key,
8277                          struct mlx5_flow *dev_flow,
8278                          const struct mlx5_flow_tunnel *tunnel,
8279                          uint32_t group_id,
8280                          struct rte_flow_error *error)
8281 {
8282         struct mlx5_cache_entry *entry;
8283         struct mlx5_flow_dv_matcher *cache;
8284         struct mlx5_flow_tbl_resource *tbl;
8285         struct mlx5_flow_tbl_data_entry *tbl_data;
8286         struct mlx5_flow_cb_ctx ctx = {
8287                 .error = error,
8288                 .data = ref,
8289         };
8290
8291         /**
8292          * tunnel offload API requires this registration for cases when
8293          * tunnel match rule was inserted before tunnel set rule.
8294          */
8295         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
8296                                        key->direction, key->domain,
8297                                        dev_flow->external, tunnel,
8298                                        group_id, 0, error);
8299         if (!tbl)
8300                 return -rte_errno;      /* No need to refill the error info */
8301         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8302         ref->tbl = tbl;
8303         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
8304         if (!entry) {
8305                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
8306                 return rte_flow_error_set(error, ENOMEM,
8307                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8308                                           "cannot allocate ref memory");
8309         }
8310         cache = container_of(entry, typeof(*cache), entry);
8311         dev_flow->handle->dvh.matcher = cache;
8312         return 0;
8313 }
8314
8315 struct mlx5_hlist_entry *
8316 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8317 {
8318         struct mlx5_dev_ctx_shared *sh = list->ctx;
8319         struct rte_flow_error *error = ctx;
8320         struct mlx5_flow_dv_tag_resource *entry;
8321         uint32_t idx = 0;
8322         int ret;
8323
8324         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8325         if (!entry) {
8326                 rte_flow_error_set(error, ENOMEM,
8327                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8328                                    "cannot allocate resource memory");
8329                 return NULL;
8330         }
8331         entry->idx = idx;
8332         entry->tag_id = key;
8333         ret = mlx5_flow_os_create_flow_action_tag(key,
8334                                                   &entry->action);
8335         if (ret) {
8336                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8337                 rte_flow_error_set(error, ENOMEM,
8338                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8339                                    NULL, "cannot create action");
8340                 return NULL;
8341         }
8342         return &entry->entry;
8343 }
8344
8345 int
8346 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
8347                      struct mlx5_hlist_entry *entry, uint64_t key,
8348                      void *cb_ctx __rte_unused)
8349 {
8350         struct mlx5_flow_dv_tag_resource *tag =
8351                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8352
8353         return key != tag->tag_id;
8354 }
8355
8356 /**
8357  * Find existing tag resource or create and register a new one.
8358  *
8359  * @param dev[in, out]
8360  *   Pointer to rte_eth_dev structure.
8361  * @param[in, out] tag_be24
8362  *   Tag value in big endian then R-shift 8.
8363  * @parm[in, out] dev_flow
8364  *   Pointer to the dev_flow.
8365  * @param[out] error
8366  *   pointer to error structure.
8367  *
8368  * @return
8369  *   0 on success otherwise -errno and errno is set.
8370  */
8371 static int
8372 flow_dv_tag_resource_register
8373                         (struct rte_eth_dev *dev,
8374                          uint32_t tag_be24,
8375                          struct mlx5_flow *dev_flow,
8376                          struct rte_flow_error *error)
8377 {
8378         struct mlx5_priv *priv = dev->data->dev_private;
8379         struct mlx5_flow_dv_tag_resource *cache_resource;
8380         struct mlx5_hlist_entry *entry;
8381
8382         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8383         if (entry) {
8384                 cache_resource = container_of
8385                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8386                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8387                 dev_flow->dv.tag_resource = cache_resource;
8388                 return 0;
8389         }
8390         return -rte_errno;
8391 }
8392
8393 void
8394 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8395                       struct mlx5_hlist_entry *entry)
8396 {
8397         struct mlx5_dev_ctx_shared *sh = list->ctx;
8398         struct mlx5_flow_dv_tag_resource *tag =
8399                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8400
8401         MLX5_ASSERT(tag && sh && tag->action);
8402         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8403         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8404         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8405 }
8406
8407 /**
8408  * Release the tag.
8409  *
8410  * @param dev
8411  *   Pointer to Ethernet device.
8412  * @param tag_idx
8413  *   Tag index.
8414  *
8415  * @return
8416  *   1 while a reference on it exists, 0 when freed.
8417  */
8418 static int
8419 flow_dv_tag_release(struct rte_eth_dev *dev,
8420                     uint32_t tag_idx)
8421 {
8422         struct mlx5_priv *priv = dev->data->dev_private;
8423         struct mlx5_flow_dv_tag_resource *tag;
8424
8425         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8426         if (!tag)
8427                 return 0;
8428         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8429                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8430         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8431 }
8432
8433 /**
8434  * Translate port ID action to vport.
8435  *
8436  * @param[in] dev
8437  *   Pointer to rte_eth_dev structure.
8438  * @param[in] action
8439  *   Pointer to the port ID action.
8440  * @param[out] dst_port_id
8441  *   The target port ID.
8442  * @param[out] error
8443  *   Pointer to the error structure.
8444  *
8445  * @return
8446  *   0 on success, a negative errno value otherwise and rte_errno is set.
8447  */
8448 static int
8449 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8450                                  const struct rte_flow_action *action,
8451                                  uint32_t *dst_port_id,
8452                                  struct rte_flow_error *error)
8453 {
8454         uint32_t port;
8455         struct mlx5_priv *priv;
8456         const struct rte_flow_action_port_id *conf =
8457                         (const struct rte_flow_action_port_id *)action->conf;
8458
8459         port = conf->original ? dev->data->port_id : conf->id;
8460         priv = mlx5_port_to_eswitch_info(port, false);
8461         if (!priv)
8462                 return rte_flow_error_set(error, -rte_errno,
8463                                           RTE_FLOW_ERROR_TYPE_ACTION,
8464                                           NULL,
8465                                           "No eswitch info was found for port");
8466 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8467         /*
8468          * This parameter is transferred to
8469          * mlx5dv_dr_action_create_dest_ib_port().
8470          */
8471         *dst_port_id = priv->dev_port;
8472 #else
8473         /*
8474          * Legacy mode, no LAG configurations is supported.
8475          * This parameter is transferred to
8476          * mlx5dv_dr_action_create_dest_vport().
8477          */
8478         *dst_port_id = priv->vport_id;
8479 #endif
8480         return 0;
8481 }
8482
8483 /**
8484  * Create a counter with aging configuration.
8485  *
8486  * @param[in] dev
8487  *   Pointer to rte_eth_dev structure.
8488  * @param[out] count
8489  *   Pointer to the counter action configuration.
8490  * @param[in] age
8491  *   Pointer to the aging action configuration.
8492  *
8493  * @return
8494  *   Index to flow counter on success, 0 otherwise.
8495  */
8496 static uint32_t
8497 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8498                                 struct mlx5_flow *dev_flow,
8499                                 const struct rte_flow_action_count *count,
8500                                 const struct rte_flow_action_age *age)
8501 {
8502         uint32_t counter;
8503         struct mlx5_age_param *age_param;
8504
8505         if (count && count->shared)
8506                 counter = flow_dv_counter_get_shared(dev, count->id);
8507         else
8508                 counter = flow_dv_counter_alloc(dev, !!age);
8509         if (!counter || age == NULL)
8510                 return counter;
8511         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8512         age_param->context = age->context ? age->context :
8513                 (void *)(uintptr_t)(dev_flow->flow_idx);
8514         age_param->timeout = age->timeout;
8515         age_param->port_id = dev->data->port_id;
8516         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8517         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8518         return counter;
8519 }
8520
8521 /**
8522  * Add Tx queue matcher
8523  *
8524  * @param[in] dev
8525  *   Pointer to the dev struct.
8526  * @param[in, out] matcher
8527  *   Flow matcher.
8528  * @param[in, out] key
8529  *   Flow matcher value.
8530  * @param[in] item
8531  *   Flow pattern to translate.
8532  * @param[in] inner
8533  *   Item is inner pattern.
8534  */
8535 static void
8536 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8537                                 void *matcher, void *key,
8538                                 const struct rte_flow_item *item)
8539 {
8540         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8541         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8542         void *misc_m =
8543                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8544         void *misc_v =
8545                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8546         struct mlx5_txq_ctrl *txq;
8547         uint32_t queue;
8548
8549
8550         queue_m = (const void *)item->mask;
8551         if (!queue_m)
8552                 return;
8553         queue_v = (const void *)item->spec;
8554         if (!queue_v)
8555                 return;
8556         txq = mlx5_txq_get(dev, queue_v->queue);
8557         if (!txq)
8558                 return;
8559         queue = txq->obj->sq->id;
8560         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8561         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8562                  queue & queue_m->queue);
8563         mlx5_txq_release(dev, queue_v->queue);
8564 }
8565
8566 /**
8567  * Set the hash fields according to the @p flow information.
8568  *
8569  * @param[in] dev_flow
8570  *   Pointer to the mlx5_flow.
8571  * @param[in] rss_desc
8572  *   Pointer to the mlx5_flow_rss_desc.
8573  */
8574 static void
8575 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8576                        struct mlx5_flow_rss_desc *rss_desc)
8577 {
8578         uint64_t items = dev_flow->handle->layers;
8579         int rss_inner = 0;
8580         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8581
8582         dev_flow->hash_fields = 0;
8583 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8584         if (rss_desc->level >= 2) {
8585                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8586                 rss_inner = 1;
8587         }
8588 #endif
8589         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8590             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8591                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8592                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8593                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8594                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8595                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8596                         else
8597                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8598                 }
8599         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8600                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8601                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8602                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8603                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8604                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8605                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8606                         else
8607                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8608                 }
8609         }
8610         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8611             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8612                 if (rss_types & ETH_RSS_UDP) {
8613                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8614                                 dev_flow->hash_fields |=
8615                                                 IBV_RX_HASH_SRC_PORT_UDP;
8616                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8617                                 dev_flow->hash_fields |=
8618                                                 IBV_RX_HASH_DST_PORT_UDP;
8619                         else
8620                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8621                 }
8622         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8623                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8624                 if (rss_types & ETH_RSS_TCP) {
8625                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8626                                 dev_flow->hash_fields |=
8627                                                 IBV_RX_HASH_SRC_PORT_TCP;
8628                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8629                                 dev_flow->hash_fields |=
8630                                                 IBV_RX_HASH_DST_PORT_TCP;
8631                         else
8632                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8633                 }
8634         }
8635 }
8636
8637 /**
8638  * Prepare an Rx Hash queue.
8639  *
8640  * @param dev
8641  *   Pointer to Ethernet device.
8642  * @param[in] dev_flow
8643  *   Pointer to the mlx5_flow.
8644  * @param[in] rss_desc
8645  *   Pointer to the mlx5_flow_rss_desc.
8646  * @param[out] hrxq_idx
8647  *   Hash Rx queue index.
8648  *
8649  * @return
8650  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8651  */
8652 static struct mlx5_hrxq *
8653 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8654                      struct mlx5_flow *dev_flow,
8655                      struct mlx5_flow_rss_desc *rss_desc,
8656                      uint32_t *hrxq_idx)
8657 {
8658         struct mlx5_priv *priv = dev->data->dev_private;
8659         struct mlx5_flow_handle *dh = dev_flow->handle;
8660         struct mlx5_hrxq *hrxq;
8661
8662         MLX5_ASSERT(rss_desc->queue_num);
8663         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8664         rss_desc->hash_fields = dev_flow->hash_fields;
8665         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8666         rss_desc->shared_rss = 0;
8667         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8668         if (!*hrxq_idx)
8669                 return NULL;
8670         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8671                               *hrxq_idx);
8672         return hrxq;
8673 }
8674
8675 /**
8676  * Release sample sub action resource.
8677  *
8678  * @param[in, out] dev
8679  *   Pointer to rte_eth_dev structure.
8680  * @param[in] act_res
8681  *   Pointer to sample sub action resource.
8682  */
8683 static void
8684 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
8685                                    struct mlx5_flow_sub_actions_idx *act_res)
8686 {
8687         if (act_res->rix_hrxq) {
8688                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
8689                 act_res->rix_hrxq = 0;
8690         }
8691         if (act_res->rix_encap_decap) {
8692                 flow_dv_encap_decap_resource_release(dev,
8693                                                      act_res->rix_encap_decap);
8694                 act_res->rix_encap_decap = 0;
8695         }
8696         if (act_res->rix_port_id_action) {
8697                 flow_dv_port_id_action_resource_release(dev,
8698                                                 act_res->rix_port_id_action);
8699                 act_res->rix_port_id_action = 0;
8700         }
8701         if (act_res->rix_tag) {
8702                 flow_dv_tag_release(dev, act_res->rix_tag);
8703                 act_res->rix_tag = 0;
8704         }
8705         if (act_res->cnt) {
8706                 flow_dv_counter_free(dev, act_res->cnt);
8707                 act_res->cnt = 0;
8708         }
8709 }
8710
8711 int
8712 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
8713                         struct mlx5_cache_entry *entry, void *cb_ctx)
8714 {
8715         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8716         struct rte_eth_dev *dev = ctx->dev;
8717         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8718         struct mlx5_flow_dv_sample_resource *cache_resource =
8719                         container_of(entry, typeof(*cache_resource), entry);
8720
8721         if (resource->ratio == cache_resource->ratio &&
8722             resource->ft_type == cache_resource->ft_type &&
8723             resource->ft_id == cache_resource->ft_id &&
8724             resource->set_action == cache_resource->set_action &&
8725             !memcmp((void *)&resource->sample_act,
8726                     (void *)&cache_resource->sample_act,
8727                     sizeof(struct mlx5_flow_sub_actions_list))) {
8728                 /*
8729                  * Existing sample action should release the prepared
8730                  * sub-actions reference counter.
8731                  */
8732                 flow_dv_sample_sub_actions_release(dev,
8733                                                 &resource->sample_idx);
8734                 return 0;
8735         }
8736         return 1;
8737 }
8738
8739 struct mlx5_cache_entry *
8740 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
8741                          struct mlx5_cache_entry *entry __rte_unused,
8742                          void *cb_ctx)
8743 {
8744         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8745         struct rte_eth_dev *dev = ctx->dev;
8746         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
8747         void **sample_dv_actions = resource->sub_actions;
8748         struct mlx5_flow_dv_sample_resource *cache_resource;
8749         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8750         struct mlx5_priv *priv = dev->data->dev_private;
8751         struct mlx5_dev_ctx_shared *sh = priv->sh;
8752         struct mlx5_flow_tbl_resource *tbl;
8753         uint32_t idx = 0;
8754         const uint32_t next_ft_step = 1;
8755         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8756         uint8_t is_egress = 0;
8757         uint8_t is_transfer = 0;
8758         struct rte_flow_error *error = ctx->error;
8759
8760         /* Register new sample resource. */
8761         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
8762         if (!cache_resource) {
8763                 rte_flow_error_set(error, ENOMEM,
8764                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8765                                           NULL,
8766                                           "cannot allocate resource memory");
8767                 return NULL;
8768         }
8769         *cache_resource = *resource;
8770         /* Create normal path table level */
8771         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8772                 is_transfer = 1;
8773         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
8774                 is_egress = 1;
8775         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8776                                         is_egress, is_transfer,
8777                                         true, NULL, 0, 0, error);
8778         if (!tbl) {
8779                 rte_flow_error_set(error, ENOMEM,
8780                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8781                                           NULL,
8782                                           "fail to create normal path table "
8783                                           "for sample");
8784                 goto error;
8785         }
8786         int ret;
8787
8788         cache_resource->normal_path_tbl = tbl;
8789         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8790                 ret = mlx5_flow_os_create_flow_action_default_miss
8791                         (&cache_resource->default_miss);
8792                 if (!ret) {
8793                         rte_flow_error_set(error, ENOMEM,
8794                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8795                                                 NULL,
8796                                                 "cannot create default miss "
8797                                                 "action");
8798                         goto error;
8799                 }
8800                 sample_dv_actions[resource->sample_act.actions_num++] =
8801                                                 cache_resource->default_miss;
8802         }
8803         /* Create a DR sample action */
8804         sampler_attr.sample_ratio = cache_resource->ratio;
8805         sampler_attr.default_next_table = tbl->obj;
8806         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8807         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8808                                                         &sample_dv_actions[0];
8809         sampler_attr.action = cache_resource->set_action;
8810         if (mlx5_os_flow_dr_create_flow_action_sampler
8811                         (&sampler_attr, &cache_resource->verbs_action)) {
8812                 rte_flow_error_set(error, ENOMEM,
8813                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8814                                         NULL, "cannot create sample action");
8815                 goto error;
8816         }
8817         cache_resource->idx = idx;
8818         cache_resource->dev = dev;
8819         return &cache_resource->entry;
8820 error:
8821         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB &&
8822             cache_resource->default_miss)
8823                 claim_zero(mlx5_flow_os_destroy_flow_action
8824                                 (cache_resource->default_miss));
8825         else
8826                 flow_dv_sample_sub_actions_release(dev,
8827                                                    &cache_resource->sample_idx);
8828         if (cache_resource->normal_path_tbl)
8829                 flow_dv_tbl_resource_release(MLX5_SH(dev),
8830                                 cache_resource->normal_path_tbl);
8831         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
8832         return NULL;
8833
8834 }
8835
8836 /**
8837  * Find existing sample resource or create and register a new one.
8838  *
8839  * @param[in, out] dev
8840  *   Pointer to rte_eth_dev structure.
8841  * @param[in] resource
8842  *   Pointer to sample resource.
8843  * @parm[in, out] dev_flow
8844  *   Pointer to the dev_flow.
8845  * @param[out] error
8846  *   pointer to error structure.
8847  *
8848  * @return
8849  *   0 on success otherwise -errno and errno is set.
8850  */
8851 static int
8852 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8853                          struct mlx5_flow_dv_sample_resource *resource,
8854                          struct mlx5_flow *dev_flow,
8855                          struct rte_flow_error *error)
8856 {
8857         struct mlx5_flow_dv_sample_resource *cache_resource;
8858         struct mlx5_cache_entry *entry;
8859         struct mlx5_priv *priv = dev->data->dev_private;
8860         struct mlx5_flow_cb_ctx ctx = {
8861                 .dev = dev,
8862                 .error = error,
8863                 .data = resource,
8864         };
8865
8866         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
8867         if (!entry)
8868                 return -rte_errno;
8869         cache_resource = container_of(entry, typeof(*cache_resource), entry);
8870         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
8871         dev_flow->dv.sample_res = cache_resource;
8872         return 0;
8873 }
8874
8875 int
8876 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
8877                             struct mlx5_cache_entry *entry, void *cb_ctx)
8878 {
8879         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8880         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8881         struct rte_eth_dev *dev = ctx->dev;
8882         struct mlx5_flow_dv_dest_array_resource *cache_resource =
8883                         container_of(entry, typeof(*cache_resource), entry);
8884         uint32_t idx = 0;
8885
8886         if (resource->num_of_dest == cache_resource->num_of_dest &&
8887             resource->ft_type == cache_resource->ft_type &&
8888             !memcmp((void *)cache_resource->sample_act,
8889                     (void *)resource->sample_act,
8890                    (resource->num_of_dest *
8891                    sizeof(struct mlx5_flow_sub_actions_list)))) {
8892                 /*
8893                  * Existing sample action should release the prepared
8894                  * sub-actions reference counter.
8895                  */
8896                 for (idx = 0; idx < resource->num_of_dest; idx++)
8897                         flow_dv_sample_sub_actions_release(dev,
8898                                         &resource->sample_idx[idx]);
8899                 return 0;
8900         }
8901         return 1;
8902 }
8903
8904 struct mlx5_cache_entry *
8905 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
8906                          struct mlx5_cache_entry *entry __rte_unused,
8907                          void *cb_ctx)
8908 {
8909         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
8910         struct rte_eth_dev *dev = ctx->dev;
8911         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8912         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
8913         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8914         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8915         struct mlx5_priv *priv = dev->data->dev_private;
8916         struct mlx5_dev_ctx_shared *sh = priv->sh;
8917         struct mlx5_flow_sub_actions_list *sample_act;
8918         struct mlx5dv_dr_domain *domain;
8919         uint32_t idx = 0, res_idx = 0;
8920         struct rte_flow_error *error = ctx->error;
8921         int ret;
8922
8923         /* Register new destination array resource. */
8924         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8925                                             &res_idx);
8926         if (!cache_resource) {
8927                 rte_flow_error_set(error, ENOMEM,
8928                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8929                                           NULL,
8930                                           "cannot allocate resource memory");
8931                 return NULL;
8932         }
8933         *cache_resource = *resource;
8934         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
8935                 domain = sh->fdb_domain;
8936         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
8937                 domain = sh->rx_domain;
8938         else
8939                 domain = sh->tx_domain;
8940         for (idx = 0; idx < resource->num_of_dest; idx++) {
8941                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8942                                  mlx5_malloc(MLX5_MEM_ZERO,
8943                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8944                                  0, SOCKET_ID_ANY);
8945                 if (!dest_attr[idx]) {
8946                         rte_flow_error_set(error, ENOMEM,
8947                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8948                                            NULL,
8949                                            "cannot allocate resource memory");
8950                         goto error;
8951                 }
8952                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8953                 sample_act = &resource->sample_act[idx];
8954                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8955                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8956                 } else if (sample_act->action_flags ==
8957                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8958                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8959                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8960                         dest_attr[idx]->dest_reformat->reformat =
8961                                         sample_act->dr_encap_action;
8962                         dest_attr[idx]->dest_reformat->dest =
8963                                         sample_act->dr_port_id_action;
8964                 } else if (sample_act->action_flags ==
8965                            MLX5_FLOW_ACTION_PORT_ID) {
8966                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8967                 }
8968         }
8969         /* create a dest array actioin */
8970         ret = mlx5_os_flow_dr_create_flow_action_dest_array
8971                                                 (domain,
8972                                                  cache_resource->num_of_dest,
8973                                                  dest_attr,
8974                                                  &cache_resource->action);
8975         if (ret) {
8976                 rte_flow_error_set(error, ENOMEM,
8977                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8978                                    NULL,
8979                                    "cannot create destination array action");
8980                 goto error;
8981         }
8982         cache_resource->idx = res_idx;
8983         cache_resource->dev = dev;
8984         for (idx = 0; idx < resource->num_of_dest; idx++)
8985                 mlx5_free(dest_attr[idx]);
8986         return &cache_resource->entry;
8987 error:
8988         for (idx = 0; idx < resource->num_of_dest; idx++) {
8989                 struct mlx5_flow_sub_actions_idx *act_res =
8990                                         &cache_resource->sample_idx[idx];
8991                 if (act_res->rix_hrxq &&
8992                     !mlx5_hrxq_release(dev,
8993                                 act_res->rix_hrxq))
8994                         act_res->rix_hrxq = 0;
8995                 if (act_res->rix_encap_decap &&
8996                         !flow_dv_encap_decap_resource_release(dev,
8997                                 act_res->rix_encap_decap))
8998                         act_res->rix_encap_decap = 0;
8999                 if (act_res->rix_port_id_action &&
9000                         !flow_dv_port_id_action_resource_release(dev,
9001                                 act_res->rix_port_id_action))
9002                         act_res->rix_port_id_action = 0;
9003                 if (dest_attr[idx])
9004                         mlx5_free(dest_attr[idx]);
9005         }
9006
9007         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
9008         return NULL;
9009 }
9010
9011 /**
9012  * Find existing destination array resource or create and register a new one.
9013  *
9014  * @param[in, out] dev
9015  *   Pointer to rte_eth_dev structure.
9016  * @param[in] resource
9017  *   Pointer to destination array resource.
9018  * @parm[in, out] dev_flow
9019  *   Pointer to the dev_flow.
9020  * @param[out] error
9021  *   pointer to error structure.
9022  *
9023  * @return
9024  *   0 on success otherwise -errno and errno is set.
9025  */
9026 static int
9027 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
9028                          struct mlx5_flow_dv_dest_array_resource *resource,
9029                          struct mlx5_flow *dev_flow,
9030                          struct rte_flow_error *error)
9031 {
9032         struct mlx5_flow_dv_dest_array_resource *cache_resource;
9033         struct mlx5_priv *priv = dev->data->dev_private;
9034         struct mlx5_cache_entry *entry;
9035         struct mlx5_flow_cb_ctx ctx = {
9036                 .dev = dev,
9037                 .error = error,
9038                 .data = resource,
9039         };
9040
9041         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
9042         if (!entry)
9043                 return -rte_errno;
9044         cache_resource = container_of(entry, typeof(*cache_resource), entry);
9045         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
9046         dev_flow->dv.dest_array_res = cache_resource;
9047         return 0;
9048 }
9049
9050 /**
9051  * Convert Sample action to DV specification.
9052  *
9053  * @param[in] dev
9054  *   Pointer to rte_eth_dev structure.
9055  * @param[in] action
9056  *   Pointer to action structure.
9057  * @param[in, out] dev_flow
9058  *   Pointer to the mlx5_flow.
9059  * @param[in] attr
9060  *   Pointer to the flow attributes.
9061  * @param[in, out] num_of_dest
9062  *   Pointer to the num of destination.
9063  * @param[in, out] sample_actions
9064  *   Pointer to sample actions list.
9065  * @param[in, out] res
9066  *   Pointer to sample resource.
9067  * @param[out] error
9068  *   Pointer to the error structure.
9069  *
9070  * @return
9071  *   0 on success, a negative errno value otherwise and rte_errno is set.
9072  */
9073 static int
9074 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
9075                                 const struct rte_flow_action *action,
9076                                 struct mlx5_flow *dev_flow,
9077                                 const struct rte_flow_attr *attr,
9078                                 uint32_t *num_of_dest,
9079                                 void **sample_actions,
9080                                 struct mlx5_flow_dv_sample_resource *res,
9081                                 struct rte_flow_error *error)
9082 {
9083         struct mlx5_priv *priv = dev->data->dev_private;
9084         const struct rte_flow_action_sample *sample_action;
9085         const struct rte_flow_action *sub_actions;
9086         const struct rte_flow_action_queue *queue;
9087         struct mlx5_flow_sub_actions_list *sample_act;
9088         struct mlx5_flow_sub_actions_idx *sample_idx;
9089         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9090         struct mlx5_flow_rss_desc *rss_desc;
9091         uint64_t action_flags = 0;
9092
9093         MLX5_ASSERT(wks);
9094         rss_desc = &wks->rss_desc;
9095         sample_act = &res->sample_act;
9096         sample_idx = &res->sample_idx;
9097         sample_action = (const struct rte_flow_action_sample *)action->conf;
9098         res->ratio = sample_action->ratio;
9099         sub_actions = sample_action->actions;
9100         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
9101                 int type = sub_actions->type;
9102                 uint32_t pre_rix = 0;
9103                 void *pre_r;
9104                 switch (type) {
9105                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9106                 {
9107                         struct mlx5_hrxq *hrxq;
9108                         uint32_t hrxq_idx;
9109
9110                         queue = sub_actions->conf;
9111                         rss_desc->queue_num = 1;
9112                         rss_desc->queue[0] = queue->index;
9113                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9114                                                     rss_desc, &hrxq_idx);
9115                         if (!hrxq)
9116                                 return rte_flow_error_set
9117                                         (error, rte_errno,
9118                                          RTE_FLOW_ERROR_TYPE_ACTION,
9119                                          NULL,
9120                                          "cannot create fate queue");
9121                         sample_act->dr_queue_action = hrxq->action;
9122                         sample_idx->rix_hrxq = hrxq_idx;
9123                         sample_actions[sample_act->actions_num++] =
9124                                                 hrxq->action;
9125                         (*num_of_dest)++;
9126                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9127                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9128                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9129                         dev_flow->handle->fate_action =
9130                                         MLX5_FLOW_FATE_QUEUE;
9131                         break;
9132                 }
9133                 case RTE_FLOW_ACTION_TYPE_MARK:
9134                 {
9135                         uint32_t tag_be = mlx5_flow_mark_set
9136                                 (((const struct rte_flow_action_mark *)
9137                                 (sub_actions->conf))->id);
9138
9139                         dev_flow->handle->mark = 1;
9140                         pre_rix = dev_flow->handle->dvh.rix_tag;
9141                         /* Save the mark resource before sample */
9142                         pre_r = dev_flow->dv.tag_resource;
9143                         if (flow_dv_tag_resource_register(dev, tag_be,
9144                                                   dev_flow, error))
9145                                 return -rte_errno;
9146                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9147                         sample_act->dr_tag_action =
9148                                 dev_flow->dv.tag_resource->action;
9149                         sample_idx->rix_tag =
9150                                 dev_flow->handle->dvh.rix_tag;
9151                         sample_actions[sample_act->actions_num++] =
9152                                                 sample_act->dr_tag_action;
9153                         /* Recover the mark resource after sample */
9154                         dev_flow->dv.tag_resource = pre_r;
9155                         dev_flow->handle->dvh.rix_tag = pre_rix;
9156                         action_flags |= MLX5_FLOW_ACTION_MARK;
9157                         break;
9158                 }
9159                 case RTE_FLOW_ACTION_TYPE_COUNT:
9160                 {
9161                         uint32_t counter;
9162
9163                         counter = flow_dv_translate_create_counter(dev,
9164                                         dev_flow, sub_actions->conf, 0);
9165                         if (!counter)
9166                                 return rte_flow_error_set
9167                                                 (error, rte_errno,
9168                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9169                                                  NULL,
9170                                                  "cannot create counter"
9171                                                  " object.");
9172                         sample_idx->cnt = counter;
9173                         sample_act->dr_cnt_action =
9174                                   (flow_dv_counter_get_by_idx(dev,
9175                                   counter, NULL))->action;
9176                         sample_actions[sample_act->actions_num++] =
9177                                                 sample_act->dr_cnt_action;
9178                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9179                         break;
9180                 }
9181                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9182                 {
9183                         struct mlx5_flow_dv_port_id_action_resource
9184                                         port_id_resource;
9185                         uint32_t port_id = 0;
9186
9187                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9188                         /* Save the port id resource before sample */
9189                         pre_rix = dev_flow->handle->rix_port_id_action;
9190                         pre_r = dev_flow->dv.port_id_action;
9191                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9192                                                              &port_id, error))
9193                                 return -rte_errno;
9194                         port_id_resource.port_id = port_id;
9195                         if (flow_dv_port_id_action_resource_register
9196                             (dev, &port_id_resource, dev_flow, error))
9197                                 return -rte_errno;
9198                         sample_act->dr_port_id_action =
9199                                 dev_flow->dv.port_id_action->action;
9200                         sample_idx->rix_port_id_action =
9201                                 dev_flow->handle->rix_port_id_action;
9202                         sample_actions[sample_act->actions_num++] =
9203                                                 sample_act->dr_port_id_action;
9204                         /* Recover the port id resource after sample */
9205                         dev_flow->dv.port_id_action = pre_r;
9206                         dev_flow->handle->rix_port_id_action = pre_rix;
9207                         (*num_of_dest)++;
9208                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9209                         break;
9210                 }
9211                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9212                         /* Save the encap resource before sample */
9213                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9214                         pre_r = dev_flow->dv.encap_decap;
9215                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9216                                                            dev_flow,
9217                                                            attr->transfer,
9218                                                            error))
9219                                 return -rte_errno;
9220                         sample_act->dr_encap_action =
9221                                 dev_flow->dv.encap_decap->action;
9222                         sample_idx->rix_encap_decap =
9223                                 dev_flow->handle->dvh.rix_encap_decap;
9224                         sample_actions[sample_act->actions_num++] =
9225                                                 sample_act->dr_encap_action;
9226                         /* Recover the encap resource after sample */
9227                         dev_flow->dv.encap_decap = pre_r;
9228                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9229                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9230                         break;
9231                 default:
9232                         return rte_flow_error_set(error, EINVAL,
9233                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9234                                 NULL,
9235                                 "Not support for sampler action");
9236                 }
9237         }
9238         sample_act->action_flags = action_flags;
9239         res->ft_id = dev_flow->dv.group;
9240         if (attr->transfer) {
9241                 union {
9242                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9243                         uint64_t set_action;
9244                 } action_ctx = { .set_action = 0 };
9245
9246                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9247                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9248                          MLX5_MODIFICATION_TYPE_SET);
9249                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9250                          MLX5_MODI_META_REG_C_0);
9251                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9252                          priv->vport_meta_tag);
9253                 res->set_action = action_ctx.set_action;
9254         } else if (attr->ingress) {
9255                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9256         } else {
9257                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
9258         }
9259         return 0;
9260 }
9261
9262 /**
9263  * Convert Sample action to DV specification.
9264  *
9265  * @param[in] dev
9266  *   Pointer to rte_eth_dev structure.
9267  * @param[in, out] dev_flow
9268  *   Pointer to the mlx5_flow.
9269  * @param[in] num_of_dest
9270  *   The num of destination.
9271  * @param[in, out] res
9272  *   Pointer to sample resource.
9273  * @param[in, out] mdest_res
9274  *   Pointer to destination array resource.
9275  * @param[in] sample_actions
9276  *   Pointer to sample path actions list.
9277  * @param[in] action_flags
9278  *   Holds the actions detected until now.
9279  * @param[out] error
9280  *   Pointer to the error structure.
9281  *
9282  * @return
9283  *   0 on success, a negative errno value otherwise and rte_errno is set.
9284  */
9285 static int
9286 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9287                              struct mlx5_flow *dev_flow,
9288                              uint32_t num_of_dest,
9289                              struct mlx5_flow_dv_sample_resource *res,
9290                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9291                              void **sample_actions,
9292                              uint64_t action_flags,
9293                              struct rte_flow_error *error)
9294 {
9295         /* update normal path action resource into last index of array */
9296         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9297         struct mlx5_flow_sub_actions_list *sample_act =
9298                                         &mdest_res->sample_act[dest_index];
9299         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9300         struct mlx5_flow_rss_desc *rss_desc;
9301         uint32_t normal_idx = 0;
9302         struct mlx5_hrxq *hrxq;
9303         uint32_t hrxq_idx;
9304
9305         MLX5_ASSERT(wks);
9306         rss_desc = &wks->rss_desc;
9307         if (num_of_dest > 1) {
9308                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9309                         /* Handle QP action for mirroring */
9310                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9311                                                     rss_desc, &hrxq_idx);
9312                         if (!hrxq)
9313                                 return rte_flow_error_set
9314                                      (error, rte_errno,
9315                                       RTE_FLOW_ERROR_TYPE_ACTION,
9316                                       NULL,
9317                                       "cannot create rx queue");
9318                         normal_idx++;
9319                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9320                         sample_act->dr_queue_action = hrxq->action;
9321                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9322                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9323                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9324                 }
9325                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9326                         normal_idx++;
9327                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9328                                 dev_flow->handle->dvh.rix_encap_decap;
9329                         sample_act->dr_encap_action =
9330                                 dev_flow->dv.encap_decap->action;
9331                 }
9332                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9333                         normal_idx++;
9334                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9335                                 dev_flow->handle->rix_port_id_action;
9336                         sample_act->dr_port_id_action =
9337                                 dev_flow->dv.port_id_action->action;
9338                 }
9339                 sample_act->actions_num = normal_idx;
9340                 /* update sample action resource into first index of array */
9341                 mdest_res->ft_type = res->ft_type;
9342                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9343                                 sizeof(struct mlx5_flow_sub_actions_idx));
9344                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9345                                 sizeof(struct mlx5_flow_sub_actions_list));
9346                 mdest_res->num_of_dest = num_of_dest;
9347                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
9348                                                          dev_flow, error))
9349                         return rte_flow_error_set(error, EINVAL,
9350                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9351                                                   NULL, "can't create sample "
9352                                                   "action");
9353         } else {
9354                 res->sub_actions = sample_actions;
9355                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
9356                         return rte_flow_error_set(error, EINVAL,
9357                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9358                                                   NULL,
9359                                                   "can't create sample action");
9360         }
9361         return 0;
9362 }
9363
9364 /**
9365  * Remove an ASO age action from age actions list.
9366  *
9367  * @param[in] dev
9368  *   Pointer to the Ethernet device structure.
9369  * @param[in] age
9370  *   Pointer to the aso age action handler.
9371  */
9372 static void
9373 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
9374                                 struct mlx5_aso_age_action *age)
9375 {
9376         struct mlx5_age_info *age_info;
9377         struct mlx5_age_param *age_param = &age->age_params;
9378         struct mlx5_priv *priv = dev->data->dev_private;
9379         uint16_t expected = AGE_CANDIDATE;
9380
9381         age_info = GET_PORT_AGE_INFO(priv);
9382         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
9383                                          AGE_FREE, false, __ATOMIC_RELAXED,
9384                                          __ATOMIC_RELAXED)) {
9385                 /**
9386                  * We need the lock even it is age timeout,
9387                  * since age action may still in process.
9388                  */
9389                 rte_spinlock_lock(&age_info->aged_sl);
9390                 LIST_REMOVE(age, next);
9391                 rte_spinlock_unlock(&age_info->aged_sl);
9392                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
9393         }
9394 }
9395
9396 /**
9397  * Release an ASO age action.
9398  *
9399  * @param[in] dev
9400  *   Pointer to the Ethernet device structure.
9401  * @param[in] age_idx
9402  *   Index of ASO age action to release.
9403  * @param[in] flow
9404  *   True if the release operation is during flow destroy operation.
9405  *   False if the release operation is during action destroy operation.
9406  *
9407  * @return
9408  *   0 when age action was removed, otherwise the number of references.
9409  */
9410 static int
9411 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
9412 {
9413         struct mlx5_priv *priv = dev->data->dev_private;
9414         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9415         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
9416         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
9417
9418         if (!ret) {
9419                 flow_dv_aso_age_remove_from_age(dev, age);
9420                 rte_spinlock_lock(&mng->free_sl);
9421                 LIST_INSERT_HEAD(&mng->free, age, next);
9422                 rte_spinlock_unlock(&mng->free_sl);
9423         }
9424         return ret;
9425 }
9426
9427 /**
9428  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
9429  *
9430  * @param[in] dev
9431  *   Pointer to the Ethernet device structure.
9432  *
9433  * @return
9434  *   0 on success, otherwise negative errno value and rte_errno is set.
9435  */
9436 static int
9437 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
9438 {
9439         struct mlx5_priv *priv = dev->data->dev_private;
9440         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9441         void *old_pools = mng->pools;
9442         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
9443         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
9444         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
9445
9446         if (!pools) {
9447                 rte_errno = ENOMEM;
9448                 return -ENOMEM;
9449         }
9450         if (old_pools) {
9451                 memcpy(pools, old_pools,
9452                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
9453                 mlx5_free(old_pools);
9454         } else {
9455                 /* First ASO flow hit allocation - starting ASO data-path. */
9456                 int ret = mlx5_aso_queue_start(priv->sh);
9457
9458                 if (ret) {
9459                         mlx5_free(pools);
9460                         return ret;
9461                 }
9462         }
9463         mng->n = resize;
9464         mng->pools = pools;
9465         return 0;
9466 }
9467
9468 /**
9469  * Create and initialize a new ASO aging pool.
9470  *
9471  * @param[in] dev
9472  *   Pointer to the Ethernet device structure.
9473  * @param[out] age_free
9474  *   Where to put the pointer of a new age action.
9475  *
9476  * @return
9477  *   The age actions pool pointer and @p age_free is set on success,
9478  *   NULL otherwise and rte_errno is set.
9479  */
9480 static struct mlx5_aso_age_pool *
9481 flow_dv_age_pool_create(struct rte_eth_dev *dev,
9482                         struct mlx5_aso_age_action **age_free)
9483 {
9484         struct mlx5_priv *priv = dev->data->dev_private;
9485         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9486         struct mlx5_aso_age_pool *pool = NULL;
9487         struct mlx5_devx_obj *obj = NULL;
9488         uint32_t i;
9489
9490         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
9491                                                     priv->sh->pdn);
9492         if (!obj) {
9493                 rte_errno = ENODATA;
9494                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
9495                 return NULL;
9496         }
9497         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
9498         if (!pool) {
9499                 claim_zero(mlx5_devx_cmd_destroy(obj));
9500                 rte_errno = ENOMEM;
9501                 return NULL;
9502         }
9503         pool->flow_hit_aso_obj = obj;
9504         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
9505         rte_spinlock_lock(&mng->resize_sl);
9506         pool->index = mng->next;
9507         /* Resize pools array if there is no room for the new pool in it. */
9508         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
9509                 claim_zero(mlx5_devx_cmd_destroy(obj));
9510                 mlx5_free(pool);
9511                 rte_spinlock_unlock(&mng->resize_sl);
9512                 return NULL;
9513         }
9514         mng->pools[pool->index] = pool;
9515         mng->next++;
9516         rte_spinlock_unlock(&mng->resize_sl);
9517         /* Assign the first action in the new pool, the rest go to free list. */
9518         *age_free = &pool->actions[0];
9519         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
9520                 pool->actions[i].offset = i;
9521                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
9522         }
9523         return pool;
9524 }
9525
9526 /**
9527  * Allocate a ASO aging bit.
9528  *
9529  * @param[in] dev
9530  *   Pointer to the Ethernet device structure.
9531  * @param[out] error
9532  *   Pointer to the error structure.
9533  *
9534  * @return
9535  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
9536  */
9537 static uint32_t
9538 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
9539 {
9540         struct mlx5_priv *priv = dev->data->dev_private;
9541         const struct mlx5_aso_age_pool *pool;
9542         struct mlx5_aso_age_action *age_free = NULL;
9543         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
9544
9545         MLX5_ASSERT(mng);
9546         /* Try to get the next free age action bit. */
9547         rte_spinlock_lock(&mng->free_sl);
9548         age_free = LIST_FIRST(&mng->free);
9549         if (age_free) {
9550                 LIST_REMOVE(age_free, next);
9551         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
9552                 rte_spinlock_unlock(&mng->free_sl);
9553                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
9554                                    NULL, "failed to create ASO age pool");
9555                 return 0; /* 0 is an error. */
9556         }
9557         rte_spinlock_unlock(&mng->free_sl);
9558         pool = container_of
9559           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
9560                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
9561                                                                        actions);
9562         if (!age_free->dr_action) {
9563                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
9564                                                  error);
9565
9566                 if (reg_c < 0) {
9567                         rte_flow_error_set(error, rte_errno,
9568                                            RTE_FLOW_ERROR_TYPE_ACTION,
9569                                            NULL, "failed to get reg_c "
9570                                            "for ASO flow hit");
9571                         return 0; /* 0 is an error. */
9572                 }
9573 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
9574                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
9575                                 (priv->sh->rx_domain,
9576                                  pool->flow_hit_aso_obj->obj, age_free->offset,
9577                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
9578                                  (reg_c - REG_C_0));
9579 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
9580                 if (!age_free->dr_action) {
9581                         rte_errno = errno;
9582                         rte_spinlock_lock(&mng->free_sl);
9583                         LIST_INSERT_HEAD(&mng->free, age_free, next);
9584                         rte_spinlock_unlock(&mng->free_sl);
9585                         rte_flow_error_set(error, rte_errno,
9586                                            RTE_FLOW_ERROR_TYPE_ACTION,
9587                                            NULL, "failed to create ASO "
9588                                            "flow hit action");
9589                         return 0; /* 0 is an error. */
9590                 }
9591         }
9592         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
9593         return pool->index | ((age_free->offset + 1) << 16);
9594 }
9595
9596 /**
9597  * Create a age action using ASO mechanism.
9598  *
9599  * @param[in] dev
9600  *   Pointer to rte_eth_dev structure.
9601  * @param[in] age
9602  *   Pointer to the aging action configuration.
9603  * @param[out] error
9604  *   Pointer to the error structure.
9605  *
9606  * @return
9607  *   Index to flow counter on success, 0 otherwise.
9608  */
9609 static uint32_t
9610 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
9611                                  const struct rte_flow_action_age *age,
9612                                  struct rte_flow_error *error)
9613 {
9614         uint32_t age_idx = 0;
9615         struct mlx5_aso_age_action *aso_age;
9616
9617         age_idx = flow_dv_aso_age_alloc(dev, error);
9618         if (!age_idx)
9619                 return 0;
9620         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
9621         aso_age->age_params.context = age->context;
9622         aso_age->age_params.timeout = age->timeout;
9623         aso_age->age_params.port_id = dev->data->port_id;
9624         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
9625                          __ATOMIC_RELAXED);
9626         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
9627                          __ATOMIC_RELAXED);
9628         return age_idx;
9629 }
9630
9631 /**
9632  * Fill the flow with DV spec, lock free
9633  * (mutex should be acquired by caller).
9634  *
9635  * @param[in] dev
9636  *   Pointer to rte_eth_dev structure.
9637  * @param[in, out] dev_flow
9638  *   Pointer to the sub flow.
9639  * @param[in] attr
9640  *   Pointer to the flow attributes.
9641  * @param[in] items
9642  *   Pointer to the list of items.
9643  * @param[in] actions
9644  *   Pointer to the list of actions.
9645  * @param[out] error
9646  *   Pointer to the error structure.
9647  *
9648  * @return
9649  *   0 on success, a negative errno value otherwise and rte_errno is set.
9650  */
9651 static int
9652 flow_dv_translate(struct rte_eth_dev *dev,
9653                   struct mlx5_flow *dev_flow,
9654                   const struct rte_flow_attr *attr,
9655                   const struct rte_flow_item items[],
9656                   const struct rte_flow_action actions[],
9657                   struct rte_flow_error *error)
9658 {
9659         struct mlx5_priv *priv = dev->data->dev_private;
9660         struct mlx5_dev_config *dev_conf = &priv->config;
9661         struct rte_flow *flow = dev_flow->flow;
9662         struct mlx5_flow_handle *handle = dev_flow->handle;
9663         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9664         struct mlx5_flow_rss_desc *rss_desc;
9665         uint64_t item_flags = 0;
9666         uint64_t last_item = 0;
9667         uint64_t action_flags = 0;
9668         uint64_t priority = attr->priority;
9669         struct mlx5_flow_dv_matcher matcher = {
9670                 .mask = {
9671                         .size = sizeof(matcher.mask.buf) -
9672                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9673                 },
9674         };
9675         int actions_n = 0;
9676         bool actions_end = false;
9677         union {
9678                 struct mlx5_flow_dv_modify_hdr_resource res;
9679                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9680                             sizeof(struct mlx5_modification_cmd) *
9681                             (MLX5_MAX_MODIFY_NUM + 1)];
9682         } mhdr_dummy;
9683         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9684         const struct rte_flow_action_count *count = NULL;
9685         const struct rte_flow_action_age *age = NULL;
9686         union flow_dv_attr flow_attr = { .attr = 0 };
9687         uint32_t tag_be;
9688         union mlx5_flow_tbl_key tbl_key;
9689         uint32_t modify_action_position = UINT32_MAX;
9690         void *match_mask = matcher.mask.buf;
9691         void *match_value = dev_flow->dv.value.buf;
9692         uint8_t next_protocol = 0xff;
9693         struct rte_vlan_hdr vlan = { 0 };
9694         struct mlx5_flow_dv_dest_array_resource mdest_res;
9695         struct mlx5_flow_dv_sample_resource sample_res;
9696         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9697         struct mlx5_flow_sub_actions_list *sample_act;
9698         uint32_t sample_act_pos = UINT32_MAX;
9699         uint32_t num_of_dest = 0;
9700         int tmp_actions_n = 0;
9701         uint32_t table;
9702         int ret = 0;
9703         const struct mlx5_flow_tunnel *tunnel;
9704         struct flow_grp_info grp_info = {
9705                 .external = !!dev_flow->external,
9706                 .transfer = !!attr->transfer,
9707                 .fdb_def_rule = !!priv->fdb_def_rule,
9708                 .skip_scale = !!dev_flow->skip_scale,
9709         };
9710
9711         if (!wks)
9712                 return rte_flow_error_set(error, ENOMEM,
9713                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9714                                           NULL,
9715                                           "failed to push flow workspace");
9716         rss_desc = &wks->rss_desc;
9717         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9718         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9719         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9720                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9721         /* update normal path action resource into last index of array */
9722         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9723         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9724                  flow_items_to_tunnel(items) :
9725                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9726                  flow_actions_to_tunnel(actions) :
9727                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9728         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9729                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9730         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9731                                 (dev, tunnel, attr, items, actions);
9732         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9733                                        &grp_info, error);
9734         if (ret)
9735                 return ret;
9736         dev_flow->dv.group = table;
9737         if (attr->transfer)
9738                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9739         if (priority == MLX5_FLOW_PRIO_RSVD)
9740                 priority = dev_conf->flow_prio - 1;
9741         /* number of actions must be set to 0 in case of dirty stack. */
9742         mhdr_res->actions_num = 0;
9743         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9744                 /*
9745                  * do not add decap action if match rule drops packet
9746                  * HW rejects rules with decap & drop
9747                  *
9748                  * if tunnel match rule was inserted before matching tunnel set
9749                  * rule flow table used in the match rule must be registered.
9750                  * current implementation handles that in the
9751                  * flow_dv_match_register() at the function end.
9752                  */
9753                 bool add_decap = true;
9754                 const struct rte_flow_action *ptr = actions;
9755
9756                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9757                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9758                                 add_decap = false;
9759                                 break;
9760                         }
9761                 }
9762                 if (add_decap) {
9763                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9764                                                            attr->transfer,
9765                                                            error))
9766                                 return -rte_errno;
9767                         dev_flow->dv.actions[actions_n++] =
9768                                         dev_flow->dv.encap_decap->action;
9769                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9770                 }
9771         }
9772         for (; !actions_end ; actions++) {
9773                 const struct rte_flow_action_queue *queue;
9774                 const struct rte_flow_action_rss *rss;
9775                 const struct rte_flow_action *action = actions;
9776                 const uint8_t *rss_key;
9777                 const struct rte_flow_action_meter *mtr;
9778                 struct mlx5_flow_tbl_resource *tbl;
9779                 struct mlx5_aso_age_action *age_act;
9780                 uint32_t port_id = 0;
9781                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9782                 int action_type = actions->type;
9783                 const struct rte_flow_action *found_action = NULL;
9784                 struct mlx5_flow_meter *fm = NULL;
9785                 uint32_t jump_group = 0;
9786
9787                 if (!mlx5_flow_os_action_supported(action_type))
9788                         return rte_flow_error_set(error, ENOTSUP,
9789                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9790                                                   actions,
9791                                                   "action not supported");
9792                 switch (action_type) {
9793                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9794                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9795                         break;
9796                 case RTE_FLOW_ACTION_TYPE_VOID:
9797                         break;
9798                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9799                         if (flow_dv_translate_action_port_id(dev, action,
9800                                                              &port_id, error))
9801                                 return -rte_errno;
9802                         port_id_resource.port_id = port_id;
9803                         MLX5_ASSERT(!handle->rix_port_id_action);
9804                         if (flow_dv_port_id_action_resource_register
9805                             (dev, &port_id_resource, dev_flow, error))
9806                                 return -rte_errno;
9807                         dev_flow->dv.actions[actions_n++] =
9808                                         dev_flow->dv.port_id_action->action;
9809                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9810                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9811                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9812                         num_of_dest++;
9813                         break;
9814                 case RTE_FLOW_ACTION_TYPE_FLAG:
9815                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9816                         dev_flow->handle->mark = 1;
9817                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9818                                 struct rte_flow_action_mark mark = {
9819                                         .id = MLX5_FLOW_MARK_DEFAULT,
9820                                 };
9821
9822                                 if (flow_dv_convert_action_mark(dev, &mark,
9823                                                                 mhdr_res,
9824                                                                 error))
9825                                         return -rte_errno;
9826                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9827                                 break;
9828                         }
9829                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9830                         /*
9831                          * Only one FLAG or MARK is supported per device flow
9832                          * right now. So the pointer to the tag resource must be
9833                          * zero before the register process.
9834                          */
9835                         MLX5_ASSERT(!handle->dvh.rix_tag);
9836                         if (flow_dv_tag_resource_register(dev, tag_be,
9837                                                           dev_flow, error))
9838                                 return -rte_errno;
9839                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9840                         dev_flow->dv.actions[actions_n++] =
9841                                         dev_flow->dv.tag_resource->action;
9842                         break;
9843                 case RTE_FLOW_ACTION_TYPE_MARK:
9844                         action_flags |= MLX5_FLOW_ACTION_MARK;
9845                         dev_flow->handle->mark = 1;
9846                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9847                                 const struct rte_flow_action_mark *mark =
9848                                         (const struct rte_flow_action_mark *)
9849                                                 actions->conf;
9850
9851                                 if (flow_dv_convert_action_mark(dev, mark,
9852                                                                 mhdr_res,
9853                                                                 error))
9854                                         return -rte_errno;
9855                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9856                                 break;
9857                         }
9858                         /* Fall-through */
9859                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9860                         /* Legacy (non-extensive) MARK action. */
9861                         tag_be = mlx5_flow_mark_set
9862                               (((const struct rte_flow_action_mark *)
9863                                (actions->conf))->id);
9864                         MLX5_ASSERT(!handle->dvh.rix_tag);
9865                         if (flow_dv_tag_resource_register(dev, tag_be,
9866                                                           dev_flow, error))
9867                                 return -rte_errno;
9868                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9869                         dev_flow->dv.actions[actions_n++] =
9870                                         dev_flow->dv.tag_resource->action;
9871                         break;
9872                 case RTE_FLOW_ACTION_TYPE_SET_META:
9873                         if (flow_dv_convert_action_set_meta
9874                                 (dev, mhdr_res, attr,
9875                                  (const struct rte_flow_action_set_meta *)
9876                                   actions->conf, error))
9877                                 return -rte_errno;
9878                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9879                         break;
9880                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9881                         if (flow_dv_convert_action_set_tag
9882                                 (dev, mhdr_res,
9883                                  (const struct rte_flow_action_set_tag *)
9884                                   actions->conf, error))
9885                                 return -rte_errno;
9886                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9887                         break;
9888                 case RTE_FLOW_ACTION_TYPE_DROP:
9889                         action_flags |= MLX5_FLOW_ACTION_DROP;
9890                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9891                         break;
9892                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9893                         queue = actions->conf;
9894                         rss_desc->queue_num = 1;
9895                         rss_desc->queue[0] = queue->index;
9896                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9897                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9898                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9899                         num_of_dest++;
9900                         break;
9901                 case RTE_FLOW_ACTION_TYPE_RSS:
9902                         rss = actions->conf;
9903                         memcpy(rss_desc->queue, rss->queue,
9904                                rss->queue_num * sizeof(uint16_t));
9905                         rss_desc->queue_num = rss->queue_num;
9906                         /* NULL RSS key indicates default RSS key. */
9907                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9908                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9909                         /*
9910                          * rss->level and rss.types should be set in advance
9911                          * when expanding items for RSS.
9912                          */
9913                         action_flags |= MLX5_FLOW_ACTION_RSS;
9914                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
9915                                 MLX5_FLOW_FATE_SHARED_RSS :
9916                                 MLX5_FLOW_FATE_QUEUE;
9917                         break;
9918                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
9919                         flow->age = (uint32_t)(uintptr_t)(action->conf);
9920                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
9921                         __atomic_fetch_add(&age_act->refcnt, 1,
9922                                            __ATOMIC_RELAXED);
9923                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
9924                         action_flags |= MLX5_FLOW_ACTION_AGE;
9925                         break;
9926                 case RTE_FLOW_ACTION_TYPE_AGE:
9927                         if (priv->sh->flow_hit_aso_en && attr->group) {
9928                                 flow->age = flow_dv_translate_create_aso_age
9929                                                 (dev, action->conf, error);
9930                                 if (!flow->age)
9931                                         return rte_flow_error_set
9932                                                 (error, rte_errno,
9933                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9934                                                  NULL,
9935                                                  "can't create ASO age action");
9936                                 dev_flow->dv.actions[actions_n++] =
9937                                           (flow_aso_age_get_by_idx
9938                                                 (dev, flow->age))->dr_action;
9939                                 action_flags |= MLX5_FLOW_ACTION_AGE;
9940                                 break;
9941                         }
9942                         /* Fall-through */
9943                 case RTE_FLOW_ACTION_TYPE_COUNT:
9944                         if (!dev_conf->devx) {
9945                                 return rte_flow_error_set
9946                                               (error, ENOTSUP,
9947                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9948                                                NULL,
9949                                                "count action not supported");
9950                         }
9951                         /* Save information first, will apply later. */
9952                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9953                                 count = action->conf;
9954                         else
9955                                 age = action->conf;
9956                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9957                         break;
9958                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9959                         dev_flow->dv.actions[actions_n++] =
9960                                                 priv->sh->pop_vlan_action;
9961                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9962                         break;
9963                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9964                         if (!(action_flags &
9965                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9966                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9967                         vlan.eth_proto = rte_be_to_cpu_16
9968                              ((((const struct rte_flow_action_of_push_vlan *)
9969                                                    actions->conf)->ethertype));
9970                         found_action = mlx5_flow_find_action
9971                                         (actions + 1,
9972                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9973                         if (found_action)
9974                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9975                         found_action = mlx5_flow_find_action
9976                                         (actions + 1,
9977                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9978                         if (found_action)
9979                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9980                         if (flow_dv_create_action_push_vlan
9981                                             (dev, attr, &vlan, dev_flow, error))
9982                                 return -rte_errno;
9983                         dev_flow->dv.actions[actions_n++] =
9984                                         dev_flow->dv.push_vlan_res->action;
9985                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9986                         break;
9987                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9988                         /* of_vlan_push action handled this action */
9989                         MLX5_ASSERT(action_flags &
9990                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9991                         break;
9992                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9993                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9994                                 break;
9995                         flow_dev_get_vlan_info_from_items(items, &vlan);
9996                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9997                         /* If no VLAN push - this is a modify header action */
9998                         if (flow_dv_convert_action_modify_vlan_vid
9999                                                 (mhdr_res, actions, error))
10000                                 return -rte_errno;
10001                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
10002                         break;
10003                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10004                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10005                         if (flow_dv_create_action_l2_encap(dev, actions,
10006                                                            dev_flow,
10007                                                            attr->transfer,
10008                                                            error))
10009                                 return -rte_errno;
10010                         dev_flow->dv.actions[actions_n++] =
10011                                         dev_flow->dv.encap_decap->action;
10012                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10013                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10014                                 sample_act->action_flags |=
10015                                                         MLX5_FLOW_ACTION_ENCAP;
10016                         break;
10017                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
10018                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
10019                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10020                                                            attr->transfer,
10021                                                            error))
10022                                 return -rte_errno;
10023                         dev_flow->dv.actions[actions_n++] =
10024                                         dev_flow->dv.encap_decap->action;
10025                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10026                         break;
10027                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10028                         /* Handle encap with preceding decap. */
10029                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
10030                                 if (flow_dv_create_action_raw_encap
10031                                         (dev, actions, dev_flow, attr, error))
10032                                         return -rte_errno;
10033                                 dev_flow->dv.actions[actions_n++] =
10034                                         dev_flow->dv.encap_decap->action;
10035                         } else {
10036                                 /* Handle encap without preceding decap. */
10037                                 if (flow_dv_create_action_l2_encap
10038                                     (dev, actions, dev_flow, attr->transfer,
10039                                      error))
10040                                         return -rte_errno;
10041                                 dev_flow->dv.actions[actions_n++] =
10042                                         dev_flow->dv.encap_decap->action;
10043                         }
10044                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10045                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
10046                                 sample_act->action_flags |=
10047                                                         MLX5_FLOW_ACTION_ENCAP;
10048                         break;
10049                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
10050                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
10051                                 ;
10052                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
10053                                 if (flow_dv_create_action_l2_decap
10054                                     (dev, dev_flow, attr->transfer, error))
10055                                         return -rte_errno;
10056                                 dev_flow->dv.actions[actions_n++] =
10057                                         dev_flow->dv.encap_decap->action;
10058                         }
10059                         /* If decap is followed by encap, handle it at encap. */
10060                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10061                         break;
10062                 case RTE_FLOW_ACTION_TYPE_JUMP:
10063                         jump_group = ((const struct rte_flow_action_jump *)
10064                                                         action->conf)->group;
10065                         grp_info.std_tbl_fix = 0;
10066                         grp_info.skip_scale = 0;
10067                         ret = mlx5_flow_group_to_table(dev, tunnel,
10068                                                        jump_group,
10069                                                        &table,
10070                                                        &grp_info, error);
10071                         if (ret)
10072                                 return ret;
10073                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
10074                                                        attr->transfer,
10075                                                        !!dev_flow->external,
10076                                                        tunnel, jump_group, 0,
10077                                                        error);
10078                         if (!tbl)
10079                                 return rte_flow_error_set
10080                                                 (error, errno,
10081                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10082                                                  NULL,
10083                                                  "cannot create jump action.");
10084                         if (flow_dv_jump_tbl_resource_register
10085                             (dev, tbl, dev_flow, error)) {
10086                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10087                                 return rte_flow_error_set
10088                                                 (error, errno,
10089                                                  RTE_FLOW_ERROR_TYPE_ACTION,
10090                                                  NULL,
10091                                                  "cannot create jump action.");
10092                         }
10093                         dev_flow->dv.actions[actions_n++] =
10094                                         dev_flow->dv.jump->action;
10095                         action_flags |= MLX5_FLOW_ACTION_JUMP;
10096                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
10097                         break;
10098                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
10099                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
10100                         if (flow_dv_convert_action_modify_mac
10101                                         (mhdr_res, actions, error))
10102                                 return -rte_errno;
10103                         action_flags |= actions->type ==
10104                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
10105                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
10106                                         MLX5_FLOW_ACTION_SET_MAC_DST;
10107                         break;
10108                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
10109                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
10110                         if (flow_dv_convert_action_modify_ipv4
10111                                         (mhdr_res, actions, error))
10112                                 return -rte_errno;
10113                         action_flags |= actions->type ==
10114                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
10115                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
10116                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
10117                         break;
10118                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
10119                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
10120                         if (flow_dv_convert_action_modify_ipv6
10121                                         (mhdr_res, actions, error))
10122                                 return -rte_errno;
10123                         action_flags |= actions->type ==
10124                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
10125                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
10126                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
10127                         break;
10128                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
10129                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
10130                         if (flow_dv_convert_action_modify_tp
10131                                         (mhdr_res, actions, items,
10132                                          &flow_attr, dev_flow, !!(action_flags &
10133                                          MLX5_FLOW_ACTION_DECAP), error))
10134                                 return -rte_errno;
10135                         action_flags |= actions->type ==
10136                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
10137                                         MLX5_FLOW_ACTION_SET_TP_SRC :
10138                                         MLX5_FLOW_ACTION_SET_TP_DST;
10139                         break;
10140                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
10141                         if (flow_dv_convert_action_modify_dec_ttl
10142                                         (mhdr_res, items, &flow_attr, dev_flow,
10143                                          !!(action_flags &
10144                                          MLX5_FLOW_ACTION_DECAP), error))
10145                                 return -rte_errno;
10146                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
10147                         break;
10148                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
10149                         if (flow_dv_convert_action_modify_ttl
10150                                         (mhdr_res, actions, items, &flow_attr,
10151                                          dev_flow, !!(action_flags &
10152                                          MLX5_FLOW_ACTION_DECAP), error))
10153                                 return -rte_errno;
10154                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
10155                         break;
10156                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
10157                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
10158                         if (flow_dv_convert_action_modify_tcp_seq
10159                                         (mhdr_res, actions, error))
10160                                 return -rte_errno;
10161                         action_flags |= actions->type ==
10162                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
10163                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
10164                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
10165                         break;
10166
10167                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
10168                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
10169                         if (flow_dv_convert_action_modify_tcp_ack
10170                                         (mhdr_res, actions, error))
10171                                 return -rte_errno;
10172                         action_flags |= actions->type ==
10173                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
10174                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
10175                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
10176                         break;
10177                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
10178                         if (flow_dv_convert_action_set_reg
10179                                         (mhdr_res, actions, error))
10180                                 return -rte_errno;
10181                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10182                         break;
10183                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
10184                         if (flow_dv_convert_action_copy_mreg
10185                                         (dev, mhdr_res, actions, error))
10186                                 return -rte_errno;
10187                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
10188                         break;
10189                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
10190                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
10191                         dev_flow->handle->fate_action =
10192                                         MLX5_FLOW_FATE_DEFAULT_MISS;
10193                         break;
10194                 case RTE_FLOW_ACTION_TYPE_METER:
10195                         mtr = actions->conf;
10196                         if (!flow->meter) {
10197                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
10198                                                             attr, error);
10199                                 if (!fm)
10200                                         return rte_flow_error_set(error,
10201                                                 rte_errno,
10202                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10203                                                 NULL,
10204                                                 "meter not found "
10205                                                 "or invalid parameters");
10206                                 flow->meter = fm->idx;
10207                         }
10208                         /* Set the meter action. */
10209                         if (!fm) {
10210                                 fm = mlx5_ipool_get(priv->sh->ipool
10211                                                 [MLX5_IPOOL_MTR], flow->meter);
10212                                 if (!fm)
10213                                         return rte_flow_error_set(error,
10214                                                 rte_errno,
10215                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10216                                                 NULL,
10217                                                 "meter not found "
10218                                                 "or invalid parameters");
10219                         }
10220                         dev_flow->dv.actions[actions_n++] =
10221                                 fm->mfts->meter_action;
10222                         action_flags |= MLX5_FLOW_ACTION_METER;
10223                         break;
10224                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
10225                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
10226                                                               actions, error))
10227                                 return -rte_errno;
10228                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
10229                         break;
10230                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
10231                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
10232                                                               actions, error))
10233                                 return -rte_errno;
10234                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
10235                         break;
10236                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
10237                         sample_act_pos = actions_n;
10238                         ret = flow_dv_translate_action_sample(dev,
10239                                                               actions,
10240                                                               dev_flow, attr,
10241                                                               &num_of_dest,
10242                                                               sample_actions,
10243                                                               &sample_res,
10244                                                               error);
10245                         if (ret < 0)
10246                                 return ret;
10247                         actions_n++;
10248                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
10249                         /* put encap action into group if work with port id */
10250                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
10251                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
10252                                 sample_act->action_flags |=
10253                                                         MLX5_FLOW_ACTION_ENCAP;
10254                         break;
10255                 case RTE_FLOW_ACTION_TYPE_END:
10256                         actions_end = true;
10257                         if (mhdr_res->actions_num) {
10258                                 /* create modify action if needed. */
10259                                 if (flow_dv_modify_hdr_resource_register
10260                                         (dev, mhdr_res, dev_flow, error))
10261                                         return -rte_errno;
10262                                 dev_flow->dv.actions[modify_action_position] =
10263                                         handle->dvh.modify_hdr->action;
10264                         }
10265                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
10266                                 flow->counter =
10267                                         flow_dv_translate_create_counter(dev,
10268                                                 dev_flow, count, age);
10269
10270                                 if (!flow->counter)
10271                                         return rte_flow_error_set
10272                                                 (error, rte_errno,
10273                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10274                                                 NULL,
10275                                                 "cannot create counter"
10276                                                 " object.");
10277                                 dev_flow->dv.actions[actions_n] =
10278                                           (flow_dv_counter_get_by_idx(dev,
10279                                           flow->counter, NULL))->action;
10280                                 actions_n++;
10281                         }
10282                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
10283                                 ret = flow_dv_create_action_sample(dev,
10284                                                           dev_flow,
10285                                                           num_of_dest,
10286                                                           &sample_res,
10287                                                           &mdest_res,
10288                                                           sample_actions,
10289                                                           action_flags,
10290                                                           error);
10291                                 if (ret < 0)
10292                                         return rte_flow_error_set
10293                                                 (error, rte_errno,
10294                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10295                                                 NULL,
10296                                                 "cannot create sample action");
10297                                 if (num_of_dest > 1) {
10298                                         dev_flow->dv.actions[sample_act_pos] =
10299                                         dev_flow->dv.dest_array_res->action;
10300                                 } else {
10301                                         dev_flow->dv.actions[sample_act_pos] =
10302                                         dev_flow->dv.sample_res->verbs_action;
10303                                 }
10304                         }
10305                         break;
10306                 default:
10307                         break;
10308                 }
10309                 if (mhdr_res->actions_num &&
10310                     modify_action_position == UINT32_MAX)
10311                         modify_action_position = actions_n++;
10312         }
10313         /*
10314          * For multiple destination (sample action with ratio=1), the encap
10315          * action and port id action will be combined into group action.
10316          * So need remove the original these actions in the flow and only
10317          * use the sample action instead of.
10318          */
10319         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
10320                 int i;
10321                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10322
10323                 for (i = 0; i < actions_n; i++) {
10324                         if ((sample_act->dr_encap_action &&
10325                                 sample_act->dr_encap_action ==
10326                                 dev_flow->dv.actions[i]) ||
10327                                 (sample_act->dr_port_id_action &&
10328                                 sample_act->dr_port_id_action ==
10329                                 dev_flow->dv.actions[i]))
10330                                 continue;
10331                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
10332                 }
10333                 memcpy((void *)dev_flow->dv.actions,
10334                                 (void *)temp_actions,
10335                                 tmp_actions_n * sizeof(void *));
10336                 actions_n = tmp_actions_n;
10337         }
10338         dev_flow->dv.actions_n = actions_n;
10339         dev_flow->act_flags = action_flags;
10340         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
10341                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
10342                 int item_type = items->type;
10343
10344                 if (!mlx5_flow_os_item_supported(item_type))
10345                         return rte_flow_error_set(error, ENOTSUP,
10346                                                   RTE_FLOW_ERROR_TYPE_ITEM,
10347                                                   NULL, "item not supported");
10348                 switch (item_type) {
10349                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
10350                         flow_dv_translate_item_port_id
10351                                 (dev, match_mask, match_value, items, attr);
10352                         last_item = MLX5_FLOW_ITEM_PORT_ID;
10353                         break;
10354                 case RTE_FLOW_ITEM_TYPE_ETH:
10355                         flow_dv_translate_item_eth(match_mask, match_value,
10356                                                    items, tunnel,
10357                                                    dev_flow->dv.group);
10358                         matcher.priority = action_flags &
10359                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
10360                                         !dev_flow->external ?
10361                                         MLX5_PRIORITY_MAP_L3 :
10362                                         MLX5_PRIORITY_MAP_L2;
10363                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
10364                                              MLX5_FLOW_LAYER_OUTER_L2;
10365                         break;
10366                 case RTE_FLOW_ITEM_TYPE_VLAN:
10367                         flow_dv_translate_item_vlan(dev_flow,
10368                                                     match_mask, match_value,
10369                                                     items, tunnel,
10370                                                     dev_flow->dv.group);
10371                         matcher.priority = MLX5_PRIORITY_MAP_L2;
10372                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
10373                                               MLX5_FLOW_LAYER_INNER_VLAN) :
10374                                              (MLX5_FLOW_LAYER_OUTER_L2 |
10375                                               MLX5_FLOW_LAYER_OUTER_VLAN);
10376                         break;
10377                 case RTE_FLOW_ITEM_TYPE_IPV4:
10378                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10379                                                   &item_flags, &tunnel);
10380                         flow_dv_translate_item_ipv4(match_mask, match_value,
10381                                                     items, tunnel,
10382                                                     dev_flow->dv.group);
10383                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10384                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
10385                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
10386                         if (items->mask != NULL &&
10387                             ((const struct rte_flow_item_ipv4 *)
10388                              items->mask)->hdr.next_proto_id) {
10389                                 next_protocol =
10390                                         ((const struct rte_flow_item_ipv4 *)
10391                                          (items->spec))->hdr.next_proto_id;
10392                                 next_protocol &=
10393                                         ((const struct rte_flow_item_ipv4 *)
10394                                          (items->mask))->hdr.next_proto_id;
10395                         } else {
10396                                 /* Reset for inner layer. */
10397                                 next_protocol = 0xff;
10398                         }
10399                         break;
10400                 case RTE_FLOW_ITEM_TYPE_IPV6:
10401                         mlx5_flow_tunnel_ip_check(items, next_protocol,
10402                                                   &item_flags, &tunnel);
10403                         flow_dv_translate_item_ipv6(match_mask, match_value,
10404                                                     items, tunnel,
10405                                                     dev_flow->dv.group);
10406                         matcher.priority = MLX5_PRIORITY_MAP_L3;
10407                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
10408                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
10409                         if (items->mask != NULL &&
10410                             ((const struct rte_flow_item_ipv6 *)
10411                              items->mask)->hdr.proto) {
10412                                 next_protocol =
10413                                         ((const struct rte_flow_item_ipv6 *)
10414                                          items->spec)->hdr.proto;
10415                                 next_protocol &=
10416                                         ((const struct rte_flow_item_ipv6 *)
10417                                          items->mask)->hdr.proto;
10418                         } else {
10419                                 /* Reset for inner layer. */
10420                                 next_protocol = 0xff;
10421                         }
10422                         break;
10423                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
10424                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
10425                                                              match_value,
10426                                                              items, tunnel);
10427                         last_item = tunnel ?
10428                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
10429                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
10430                         if (items->mask != NULL &&
10431                             ((const struct rte_flow_item_ipv6_frag_ext *)
10432                              items->mask)->hdr.next_header) {
10433                                 next_protocol =
10434                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10435                                  items->spec)->hdr.next_header;
10436                                 next_protocol &=
10437                                 ((const struct rte_flow_item_ipv6_frag_ext *)
10438                                  items->mask)->hdr.next_header;
10439                         } else {
10440                                 /* Reset for inner layer. */
10441                                 next_protocol = 0xff;
10442                         }
10443                         break;
10444                 case RTE_FLOW_ITEM_TYPE_TCP:
10445                         flow_dv_translate_item_tcp(match_mask, match_value,
10446                                                    items, tunnel);
10447                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10448                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
10449                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
10450                         break;
10451                 case RTE_FLOW_ITEM_TYPE_UDP:
10452                         flow_dv_translate_item_udp(match_mask, match_value,
10453                                                    items, tunnel);
10454                         matcher.priority = MLX5_PRIORITY_MAP_L4;
10455                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
10456                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
10457                         break;
10458                 case RTE_FLOW_ITEM_TYPE_GRE:
10459                         flow_dv_translate_item_gre(match_mask, match_value,
10460                                                    items, tunnel);
10461                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10462                         last_item = MLX5_FLOW_LAYER_GRE;
10463                         break;
10464                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10465                         flow_dv_translate_item_gre_key(match_mask,
10466                                                        match_value, items);
10467                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10468                         break;
10469                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10470                         flow_dv_translate_item_nvgre(match_mask, match_value,
10471                                                      items, tunnel);
10472                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10473                         last_item = MLX5_FLOW_LAYER_GRE;
10474                         break;
10475                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10476                         flow_dv_translate_item_vxlan(match_mask, match_value,
10477                                                      items, tunnel);
10478                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10479                         last_item = MLX5_FLOW_LAYER_VXLAN;
10480                         break;
10481                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10482                         flow_dv_translate_item_vxlan_gpe(match_mask,
10483                                                          match_value, items,
10484                                                          tunnel);
10485                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10486                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10487                         break;
10488                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10489                         flow_dv_translate_item_geneve(match_mask, match_value,
10490                                                       items, tunnel);
10491                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10492                         last_item = MLX5_FLOW_LAYER_GENEVE;
10493                         break;
10494                 case RTE_FLOW_ITEM_TYPE_MPLS:
10495                         flow_dv_translate_item_mpls(match_mask, match_value,
10496                                                     items, last_item, tunnel);
10497                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10498                         last_item = MLX5_FLOW_LAYER_MPLS;
10499                         break;
10500                 case RTE_FLOW_ITEM_TYPE_MARK:
10501                         flow_dv_translate_item_mark(dev, match_mask,
10502                                                     match_value, items);
10503                         last_item = MLX5_FLOW_ITEM_MARK;
10504                         break;
10505                 case RTE_FLOW_ITEM_TYPE_META:
10506                         flow_dv_translate_item_meta(dev, match_mask,
10507                                                     match_value, attr, items);
10508                         last_item = MLX5_FLOW_ITEM_METADATA;
10509                         break;
10510                 case RTE_FLOW_ITEM_TYPE_ICMP:
10511                         flow_dv_translate_item_icmp(match_mask, match_value,
10512                                                     items, tunnel);
10513                         last_item = MLX5_FLOW_LAYER_ICMP;
10514                         break;
10515                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10516                         flow_dv_translate_item_icmp6(match_mask, match_value,
10517                                                       items, tunnel);
10518                         last_item = MLX5_FLOW_LAYER_ICMP6;
10519                         break;
10520                 case RTE_FLOW_ITEM_TYPE_TAG:
10521                         flow_dv_translate_item_tag(dev, match_mask,
10522                                                    match_value, items);
10523                         last_item = MLX5_FLOW_ITEM_TAG;
10524                         break;
10525                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10526                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10527                                                         match_value, items);
10528                         last_item = MLX5_FLOW_ITEM_TAG;
10529                         break;
10530                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10531                         flow_dv_translate_item_tx_queue(dev, match_mask,
10532                                                         match_value,
10533                                                         items);
10534                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10535                         break;
10536                 case RTE_FLOW_ITEM_TYPE_GTP:
10537                         flow_dv_translate_item_gtp(match_mask, match_value,
10538                                                    items, tunnel);
10539                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10540                         last_item = MLX5_FLOW_LAYER_GTP;
10541                         break;
10542                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10543                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10544                                 /* Create it only the first time to be used. */
10545                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10546                                 if (ret)
10547                                         return rte_flow_error_set
10548                                                 (error, -ret,
10549                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10550                                                 NULL,
10551                                                 "cannot create eCPRI parser");
10552                         }
10553                         /* Adjust the length matcher and device flow value. */
10554                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10555                         dev_flow->dv.value.size =
10556                                         MLX5_ST_SZ_BYTES(fte_match_param);
10557                         flow_dv_translate_item_ecpri(dev, match_mask,
10558                                                      match_value, items);
10559                         /* No other protocol should follow eCPRI layer. */
10560                         last_item = MLX5_FLOW_LAYER_ECPRI;
10561                         break;
10562                 default:
10563                         break;
10564                 }
10565                 item_flags |= last_item;
10566         }
10567         /*
10568          * When E-Switch mode is enabled, we have two cases where we need to
10569          * set the source port manually.
10570          * The first one, is in case of Nic steering rule, and the second is
10571          * E-Switch rule where no port_id item was found. In both cases
10572          * the source port is set according the current port in use.
10573          */
10574         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10575             (priv->representor || priv->master)) {
10576                 if (flow_dv_translate_item_port_id(dev, match_mask,
10577                                                    match_value, NULL, attr))
10578                         return -rte_errno;
10579         }
10580 #ifdef RTE_LIBRTE_MLX5_DEBUG
10581         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10582                                               dev_flow->dv.value.buf));
10583 #endif
10584         /*
10585          * Layers may be already initialized from prefix flow if this dev_flow
10586          * is the suffix flow.
10587          */
10588         handle->layers |= item_flags;
10589         if (action_flags & MLX5_FLOW_ACTION_RSS)
10590                 flow_dv_hashfields_set(dev_flow, rss_desc);
10591         /* Register matcher. */
10592         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10593                                     matcher.mask.size);
10594         matcher.priority = mlx5_os_flow_adjust_priority(dev,
10595                                                         priority,
10596                                                         matcher.priority);
10597         /* reserved field no needs to be set to 0 here. */
10598         tbl_key.domain = attr->transfer;
10599         tbl_key.direction = attr->egress;
10600         tbl_key.table_id = dev_flow->dv.group;
10601         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
10602                                      tunnel, attr->group, error))
10603                 return -rte_errno;
10604         return 0;
10605 }
10606
10607 /**
10608  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10609  * and tunnel.
10610  *
10611  * @param[in, out] action
10612  *   Shred RSS action holding hash RX queue objects.
10613  * @param[in] hash_fields
10614  *   Defines combination of packet fields to participate in RX hash.
10615  * @param[in] tunnel
10616  *   Tunnel type
10617  * @param[in] hrxq_idx
10618  *   Hash RX queue index to set.
10619  *
10620  * @return
10621  *   0 on success, otherwise negative errno value.
10622  */
10623 static int
10624 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10625                               const uint64_t hash_fields,
10626                               const int tunnel,
10627                               uint32_t hrxq_idx)
10628 {
10629         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10630
10631         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10632         case MLX5_RSS_HASH_IPV4:
10633                 hrxqs[0] = hrxq_idx;
10634                 return 0;
10635         case MLX5_RSS_HASH_IPV4_TCP:
10636                 hrxqs[1] = hrxq_idx;
10637                 return 0;
10638         case MLX5_RSS_HASH_IPV4_UDP:
10639                 hrxqs[2] = hrxq_idx;
10640                 return 0;
10641         case MLX5_RSS_HASH_IPV6:
10642                 hrxqs[3] = hrxq_idx;
10643                 return 0;
10644         case MLX5_RSS_HASH_IPV6_TCP:
10645                 hrxqs[4] = hrxq_idx;
10646                 return 0;
10647         case MLX5_RSS_HASH_IPV6_UDP:
10648                 hrxqs[5] = hrxq_idx;
10649                 return 0;
10650         case MLX5_RSS_HASH_NONE:
10651                 hrxqs[6] = hrxq_idx;
10652                 return 0;
10653         default:
10654                 return -1;
10655         }
10656 }
10657
10658 /**
10659  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10660  * and tunnel.
10661  *
10662  * @param[in] dev
10663  *   Pointer to the Ethernet device structure.
10664  * @param[in] idx
10665  *   Shared RSS action ID holding hash RX queue objects.
10666  * @param[in] hash_fields
10667  *   Defines combination of packet fields to participate in RX hash.
10668  * @param[in] tunnel
10669  *   Tunnel type
10670  *
10671  * @return
10672  *   Valid hash RX queue index, otherwise 0.
10673  */
10674 static uint32_t
10675 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
10676                                  const uint64_t hash_fields,
10677                                  const int tunnel)
10678 {
10679         struct mlx5_priv *priv = dev->data->dev_private;
10680         struct mlx5_shared_action_rss *shared_rss =
10681             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
10682         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
10683                                                         shared_rss->hrxq_tunnel;
10684
10685         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10686         case MLX5_RSS_HASH_IPV4:
10687                 return hrxqs[0];
10688         case MLX5_RSS_HASH_IPV4_TCP:
10689                 return hrxqs[1];
10690         case MLX5_RSS_HASH_IPV4_UDP:
10691                 return hrxqs[2];
10692         case MLX5_RSS_HASH_IPV6:
10693                 return hrxqs[3];
10694         case MLX5_RSS_HASH_IPV6_TCP:
10695                 return hrxqs[4];
10696         case MLX5_RSS_HASH_IPV6_UDP:
10697                 return hrxqs[5];
10698         case MLX5_RSS_HASH_NONE:
10699                 return hrxqs[6];
10700         default:
10701                 return 0;
10702         }
10703 }
10704
10705 /**
10706  * Apply the flow to the NIC, lock free,
10707  * (mutex should be acquired by caller).
10708  *
10709  * @param[in] dev
10710  *   Pointer to the Ethernet device structure.
10711  * @param[in, out] flow
10712  *   Pointer to flow structure.
10713  * @param[out] error
10714  *   Pointer to error structure.
10715  *
10716  * @return
10717  *   0 on success, a negative errno value otherwise and rte_errno is set.
10718  */
10719 static int
10720 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10721               struct rte_flow_error *error)
10722 {
10723         struct mlx5_flow_dv_workspace *dv;
10724         struct mlx5_flow_handle *dh;
10725         struct mlx5_flow_handle_dv *dv_h;
10726         struct mlx5_flow *dev_flow;
10727         struct mlx5_priv *priv = dev->data->dev_private;
10728         uint32_t handle_idx;
10729         int n;
10730         int err;
10731         int idx;
10732         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10733         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
10734
10735         MLX5_ASSERT(wks);
10736         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
10737                 dev_flow = &wks->flows[idx];
10738                 dv = &dev_flow->dv;
10739                 dh = dev_flow->handle;
10740                 dv_h = &dh->dvh;
10741                 n = dv->actions_n;
10742                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10743                         if (dv->transfer) {
10744                                 dv->actions[n++] = priv->sh->esw_drop_action;
10745                         } else {
10746                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10747                                 dv->actions[n++] =
10748                                                 priv->drop_queue.hrxq->action;
10749                         }
10750                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10751                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
10752                         struct mlx5_hrxq *hrxq;
10753                         uint32_t hrxq_idx;
10754
10755                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10756                                                     &hrxq_idx);
10757                         if (!hrxq) {
10758                                 rte_flow_error_set
10759                                         (error, rte_errno,
10760                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10761                                          "cannot get hash queue");
10762                                 goto error;
10763                         }
10764                         dh->rix_hrxq = hrxq_idx;
10765                         dv->actions[n++] = hrxq->action;
10766                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10767                         struct mlx5_hrxq *hrxq = NULL;
10768                         uint32_t hrxq_idx;
10769
10770                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
10771                                                 rss_desc->shared_rss,
10772                                                 dev_flow->hash_fields,
10773                                                 !!(dh->layers &
10774                                                 MLX5_FLOW_LAYER_TUNNEL));
10775                         if (hrxq_idx)
10776                                 hrxq = mlx5_ipool_get
10777                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
10778                                          hrxq_idx);
10779                         if (!hrxq) {
10780                                 rte_flow_error_set
10781                                         (error, rte_errno,
10782                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10783                                          "cannot get hash queue");
10784                                 goto error;
10785                         }
10786                         dh->rix_srss = rss_desc->shared_rss;
10787                         dv->actions[n++] = hrxq->action;
10788                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10789                         if (!priv->sh->default_miss_action) {
10790                                 rte_flow_error_set
10791                                         (error, rte_errno,
10792                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10793                                          "default miss action not be created.");
10794                                 goto error;
10795                         }
10796                         dv->actions[n++] = priv->sh->default_miss_action;
10797                 }
10798                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10799                                                (void *)&dv->value, n,
10800                                                dv->actions, &dh->drv_flow);
10801                 if (err) {
10802                         rte_flow_error_set(error, errno,
10803                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10804                                            NULL,
10805                                            "hardware refuses to create flow");
10806                         goto error;
10807                 }
10808                 if (priv->vmwa_context &&
10809                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10810                         /*
10811                          * The rule contains the VLAN pattern.
10812                          * For VF we are going to create VLAN
10813                          * interface to make hypervisor set correct
10814                          * e-Switch vport context.
10815                          */
10816                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10817                 }
10818         }
10819         return 0;
10820 error:
10821         err = rte_errno; /* Save rte_errno before cleanup. */
10822         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10823                        handle_idx, dh, next) {
10824                 /* hrxq is union, don't clear it if the flag is not set. */
10825                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10826                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10827                         dh->rix_hrxq = 0;
10828                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
10829                         dh->rix_srss = 0;
10830                 }
10831                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10832                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10833         }
10834         rte_errno = err; /* Restore rte_errno. */
10835         return -rte_errno;
10836 }
10837
10838 void
10839 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
10840                           struct mlx5_cache_entry *entry)
10841 {
10842         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
10843                                                           entry);
10844
10845         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
10846         mlx5_free(cache);
10847 }
10848
10849 /**
10850  * Release the flow matcher.
10851  *
10852  * @param dev
10853  *   Pointer to Ethernet device.
10854  * @param handle
10855  *   Pointer to mlx5_flow_handle.
10856  *
10857  * @return
10858  *   1 while a reference on it exists, 0 when freed.
10859  */
10860 static int
10861 flow_dv_matcher_release(struct rte_eth_dev *dev,
10862                         struct mlx5_flow_handle *handle)
10863 {
10864         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10865         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
10866                                                             typeof(*tbl), tbl);
10867         int ret;
10868
10869         MLX5_ASSERT(matcher->matcher_object);
10870         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
10871         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
10872         return ret;
10873 }
10874
10875 /**
10876  * Release encap_decap resource.
10877  *
10878  * @param list
10879  *   Pointer to the hash list.
10880  * @param entry
10881  *   Pointer to exist resource entry object.
10882  */
10883 void
10884 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
10885                               struct mlx5_hlist_entry *entry)
10886 {
10887         struct mlx5_dev_ctx_shared *sh = list->ctx;
10888         struct mlx5_flow_dv_encap_decap_resource *res =
10889                 container_of(entry, typeof(*res), entry);
10890
10891         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10892         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
10893 }
10894
10895 /**
10896  * Release an encap/decap resource.
10897  *
10898  * @param dev
10899  *   Pointer to Ethernet device.
10900  * @param encap_decap_idx
10901  *   Index of encap decap resource.
10902  *
10903  * @return
10904  *   1 while a reference on it exists, 0 when freed.
10905  */
10906 static int
10907 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10908                                      uint32_t encap_decap_idx)
10909 {
10910         struct mlx5_priv *priv = dev->data->dev_private;
10911         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10912
10913         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10914                                         encap_decap_idx);
10915         if (!cache_resource)
10916                 return 0;
10917         MLX5_ASSERT(cache_resource->action);
10918         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
10919                                      &cache_resource->entry);
10920 }
10921
10922 /**
10923  * Release an jump to table action resource.
10924  *
10925  * @param dev
10926  *   Pointer to Ethernet device.
10927  * @param handle
10928  *   Pointer to mlx5_flow_handle.
10929  *
10930  * @return
10931  *   1 while a reference on it exists, 0 when freed.
10932  */
10933 static int
10934 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10935                                   struct mlx5_flow_handle *handle)
10936 {
10937         struct mlx5_priv *priv = dev->data->dev_private;
10938         struct mlx5_flow_tbl_data_entry *tbl_data;
10939
10940         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10941                              handle->rix_jump);
10942         if (!tbl_data)
10943                 return 0;
10944         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
10945 }
10946
10947 void
10948 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
10949                          struct mlx5_hlist_entry *entry)
10950 {
10951         struct mlx5_flow_dv_modify_hdr_resource *res =
10952                 container_of(entry, typeof(*res), entry);
10953
10954         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10955         mlx5_free(entry);
10956 }
10957
10958 /**
10959  * Release a modify-header resource.
10960  *
10961  * @param dev
10962  *   Pointer to Ethernet device.
10963  * @param handle
10964  *   Pointer to mlx5_flow_handle.
10965  *
10966  * @return
10967  *   1 while a reference on it exists, 0 when freed.
10968  */
10969 static int
10970 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10971                                     struct mlx5_flow_handle *handle)
10972 {
10973         struct mlx5_priv *priv = dev->data->dev_private;
10974         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
10975
10976         MLX5_ASSERT(entry->action);
10977         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
10978 }
10979
10980 void
10981 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
10982                           struct mlx5_cache_entry *entry)
10983 {
10984         struct mlx5_dev_ctx_shared *sh = list->ctx;
10985         struct mlx5_flow_dv_port_id_action_resource *cache =
10986                         container_of(entry, typeof(*cache), entry);
10987
10988         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
10989         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
10990 }
10991
10992 /**
10993  * Release port ID action resource.
10994  *
10995  * @param dev
10996  *   Pointer to Ethernet device.
10997  * @param handle
10998  *   Pointer to mlx5_flow_handle.
10999  *
11000  * @return
11001  *   1 while a reference on it exists, 0 when freed.
11002  */
11003 static int
11004 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
11005                                         uint32_t port_id)
11006 {
11007         struct mlx5_priv *priv = dev->data->dev_private;
11008         struct mlx5_flow_dv_port_id_action_resource *cache;
11009
11010         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
11011         if (!cache)
11012                 return 0;
11013         MLX5_ASSERT(cache->action);
11014         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
11015                                      &cache->entry);
11016 }
11017
11018 /**
11019  * Release shared RSS action resource.
11020  *
11021  * @param dev
11022  *   Pointer to Ethernet device.
11023  * @param srss
11024  *   Shared RSS action index.
11025  */
11026 static void
11027 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
11028 {
11029         struct mlx5_priv *priv = dev->data->dev_private;
11030         struct mlx5_shared_action_rss *shared_rss;
11031
11032         shared_rss = mlx5_ipool_get
11033                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
11034         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
11035 }
11036
11037 void
11038 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
11039                             struct mlx5_cache_entry *entry)
11040 {
11041         struct mlx5_dev_ctx_shared *sh = list->ctx;
11042         struct mlx5_flow_dv_push_vlan_action_resource *cache =
11043                         container_of(entry, typeof(*cache), entry);
11044
11045         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
11046         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
11047 }
11048
11049 /**
11050  * Release push vlan action resource.
11051  *
11052  * @param dev
11053  *   Pointer to Ethernet device.
11054  * @param handle
11055  *   Pointer to mlx5_flow_handle.
11056  *
11057  * @return
11058  *   1 while a reference on it exists, 0 when freed.
11059  */
11060 static int
11061 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
11062                                           struct mlx5_flow_handle *handle)
11063 {
11064         struct mlx5_priv *priv = dev->data->dev_private;
11065         struct mlx5_flow_dv_push_vlan_action_resource *cache;
11066         uint32_t idx = handle->dvh.rix_push_vlan;
11067
11068         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
11069         if (!cache)
11070                 return 0;
11071         MLX5_ASSERT(cache->action);
11072         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
11073                                      &cache->entry);
11074 }
11075
11076 /**
11077  * Release the fate resource.
11078  *
11079  * @param dev
11080  *   Pointer to Ethernet device.
11081  * @param handle
11082  *   Pointer to mlx5_flow_handle.
11083  */
11084 static void
11085 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
11086                                struct mlx5_flow_handle *handle)
11087 {
11088         if (!handle->rix_fate)
11089                 return;
11090         switch (handle->fate_action) {
11091         case MLX5_FLOW_FATE_QUEUE:
11092                 mlx5_hrxq_release(dev, handle->rix_hrxq);
11093                 break;
11094         case MLX5_FLOW_FATE_JUMP:
11095                 flow_dv_jump_tbl_resource_release(dev, handle);
11096                 break;
11097         case MLX5_FLOW_FATE_PORT_ID:
11098                 flow_dv_port_id_action_resource_release(dev,
11099                                 handle->rix_port_id_action);
11100                 break;
11101         default:
11102                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
11103                 break;
11104         }
11105         handle->rix_fate = 0;
11106 }
11107
11108 void
11109 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
11110                          struct mlx5_cache_entry *entry)
11111 {
11112         struct mlx5_flow_dv_sample_resource *cache_resource =
11113                         container_of(entry, typeof(*cache_resource), entry);
11114         struct rte_eth_dev *dev = cache_resource->dev;
11115         struct mlx5_priv *priv = dev->data->dev_private;
11116
11117         if (cache_resource->verbs_action)
11118                 claim_zero(mlx5_flow_os_destroy_flow_action
11119                                 (cache_resource->verbs_action));
11120         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11121                 if (cache_resource->default_miss)
11122                         claim_zero(mlx5_flow_os_destroy_flow_action
11123                           (cache_resource->default_miss));
11124         }
11125         if (cache_resource->normal_path_tbl)
11126                 flow_dv_tbl_resource_release(MLX5_SH(dev),
11127                         cache_resource->normal_path_tbl);
11128         flow_dv_sample_sub_actions_release(dev,
11129                                 &cache_resource->sample_idx);
11130         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11131                         cache_resource->idx);
11132         DRV_LOG(DEBUG, "sample resource %p: removed",
11133                 (void *)cache_resource);
11134 }
11135
11136 /**
11137  * Release an sample resource.
11138  *
11139  * @param dev
11140  *   Pointer to Ethernet device.
11141  * @param handle
11142  *   Pointer to mlx5_flow_handle.
11143  *
11144  * @return
11145  *   1 while a reference on it exists, 0 when freed.
11146  */
11147 static int
11148 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
11149                                      struct mlx5_flow_handle *handle)
11150 {
11151         struct mlx5_priv *priv = dev->data->dev_private;
11152         struct mlx5_flow_dv_sample_resource *cache_resource;
11153
11154         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
11155                          handle->dvh.rix_sample);
11156         if (!cache_resource)
11157                 return 0;
11158         MLX5_ASSERT(cache_resource->verbs_action);
11159         return mlx5_cache_unregister(&priv->sh->sample_action_list,
11160                                      &cache_resource->entry);
11161 }
11162
11163 void
11164 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
11165                              struct mlx5_cache_entry *entry)
11166 {
11167         struct mlx5_flow_dv_dest_array_resource *cache_resource =
11168                         container_of(entry, typeof(*cache_resource), entry);
11169         struct rte_eth_dev *dev = cache_resource->dev;
11170         struct mlx5_priv *priv = dev->data->dev_private;
11171         uint32_t i = 0;
11172
11173         MLX5_ASSERT(cache_resource->action);
11174         if (cache_resource->action)
11175                 claim_zero(mlx5_flow_os_destroy_flow_action
11176                                         (cache_resource->action));
11177         for (; i < cache_resource->num_of_dest; i++)
11178                 flow_dv_sample_sub_actions_release(dev,
11179                                 &cache_resource->sample_idx[i]);
11180         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11181                         cache_resource->idx);
11182         DRV_LOG(DEBUG, "destination array resource %p: removed",
11183                 (void *)cache_resource);
11184 }
11185
11186 /**
11187  * Release an destination array resource.
11188  *
11189  * @param dev
11190  *   Pointer to Ethernet device.
11191  * @param handle
11192  *   Pointer to mlx5_flow_handle.
11193  *
11194  * @return
11195  *   1 while a reference on it exists, 0 when freed.
11196  */
11197 static int
11198 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
11199                                     struct mlx5_flow_handle *handle)
11200 {
11201         struct mlx5_priv *priv = dev->data->dev_private;
11202         struct mlx5_flow_dv_dest_array_resource *cache;
11203
11204         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11205                                handle->dvh.rix_dest_array);
11206         if (!cache)
11207                 return 0;
11208         MLX5_ASSERT(cache->action);
11209         return mlx5_cache_unregister(&priv->sh->dest_array_list,
11210                                      &cache->entry);
11211 }
11212
11213 /**
11214  * Remove the flow from the NIC but keeps it in memory.
11215  * Lock free, (mutex should be acquired by caller).
11216  *
11217  * @param[in] dev
11218  *   Pointer to Ethernet device.
11219  * @param[in, out] flow
11220  *   Pointer to flow structure.
11221  */
11222 static void
11223 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
11224 {
11225         struct mlx5_flow_handle *dh;
11226         uint32_t handle_idx;
11227         struct mlx5_priv *priv = dev->data->dev_private;
11228
11229         if (!flow)
11230                 return;
11231         handle_idx = flow->dev_handles;
11232         while (handle_idx) {
11233                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11234                                     handle_idx);
11235                 if (!dh)
11236                         return;
11237                 if (dh->drv_flow) {
11238                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
11239                         dh->drv_flow = NULL;
11240                 }
11241                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
11242                         flow_dv_fate_resource_release(dev, dh);
11243                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
11244                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
11245                 handle_idx = dh->next.next;
11246         }
11247 }
11248
11249 /**
11250  * Remove the flow from the NIC and the memory.
11251  * Lock free, (mutex should be acquired by caller).
11252  *
11253  * @param[in] dev
11254  *   Pointer to the Ethernet device structure.
11255  * @param[in, out] flow
11256  *   Pointer to flow structure.
11257  */
11258 static void
11259 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
11260 {
11261         struct mlx5_flow_handle *dev_handle;
11262         struct mlx5_priv *priv = dev->data->dev_private;
11263         uint32_t srss = 0;
11264
11265         if (!flow)
11266                 return;
11267         flow_dv_remove(dev, flow);
11268         if (flow->counter) {
11269                 flow_dv_counter_free(dev, flow->counter);
11270                 flow->counter = 0;
11271         }
11272         if (flow->meter) {
11273                 struct mlx5_flow_meter *fm;
11274
11275                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
11276                                     flow->meter);
11277                 if (fm)
11278                         mlx5_flow_meter_detach(fm);
11279                 flow->meter = 0;
11280         }
11281         if (flow->age)
11282                 flow_dv_aso_age_release(dev, flow->age);
11283         while (flow->dev_handles) {
11284                 uint32_t tmp_idx = flow->dev_handles;
11285
11286                 dev_handle = mlx5_ipool_get(priv->sh->ipool
11287                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
11288                 if (!dev_handle)
11289                         return;
11290                 flow->dev_handles = dev_handle->next.next;
11291                 if (dev_handle->dvh.matcher)
11292                         flow_dv_matcher_release(dev, dev_handle);
11293                 if (dev_handle->dvh.rix_sample)
11294                         flow_dv_sample_resource_release(dev, dev_handle);
11295                 if (dev_handle->dvh.rix_dest_array)
11296                         flow_dv_dest_array_resource_release(dev, dev_handle);
11297                 if (dev_handle->dvh.rix_encap_decap)
11298                         flow_dv_encap_decap_resource_release(dev,
11299                                 dev_handle->dvh.rix_encap_decap);
11300                 if (dev_handle->dvh.modify_hdr)
11301                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
11302                 if (dev_handle->dvh.rix_push_vlan)
11303                         flow_dv_push_vlan_action_resource_release(dev,
11304                                                                   dev_handle);
11305                 if (dev_handle->dvh.rix_tag)
11306                         flow_dv_tag_release(dev,
11307                                             dev_handle->dvh.rix_tag);
11308                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
11309                         flow_dv_fate_resource_release(dev, dev_handle);
11310                 else if (!srss)
11311                         srss = dev_handle->rix_srss;
11312                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
11313                            tmp_idx);
11314         }
11315         if (srss)
11316                 flow_dv_shared_rss_action_release(dev, srss);
11317 }
11318
11319 /**
11320  * Release array of hash RX queue objects.
11321  * Helper function.
11322  *
11323  * @param[in] dev
11324  *   Pointer to the Ethernet device structure.
11325  * @param[in, out] hrxqs
11326  *   Array of hash RX queue objects.
11327  *
11328  * @return
11329  *   Total number of references to hash RX queue objects in *hrxqs* array
11330  *   after this operation.
11331  */
11332 static int
11333 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
11334                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
11335 {
11336         size_t i;
11337         int remaining = 0;
11338
11339         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
11340                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
11341
11342                 if (!ret)
11343                         (*hrxqs)[i] = 0;
11344                 remaining += ret;
11345         }
11346         return remaining;
11347 }
11348
11349 /**
11350  * Release all hash RX queue objects representing shared RSS action.
11351  *
11352  * @param[in] dev
11353  *   Pointer to the Ethernet device structure.
11354  * @param[in, out] action
11355  *   Shared RSS action to remove hash RX queue objects from.
11356  *
11357  * @return
11358  *   Total number of references to hash RX queue objects stored in *action*
11359  *   after this operation.
11360  *   Expected to be 0 if no external references held.
11361  */
11362 static int
11363 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11364                                  struct mlx5_shared_action_rss *action)
11365 {
11366         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11367                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11368 }
11369
11370 /**
11371  * Setup shared RSS action.
11372  * Prepare set of hash RX queue objects sufficient to handle all valid
11373  * hash_fields combinations (see enum ibv_rx_hash_fields).
11374  *
11375  * @param[in] dev
11376  *   Pointer to the Ethernet device structure.
11377  * @param[in] action_idx
11378  *   Shared RSS action ipool index.
11379  * @param[in, out] action
11380  *   Partially initialized shared RSS action.
11381  * @param[out] error
11382  *   Perform verbose error reporting if not NULL. Initialized in case of
11383  *   error only.
11384  *
11385  * @return
11386  *   0 on success, otherwise negative errno value.
11387  */
11388 static int
11389 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11390                            uint32_t action_idx,
11391                            struct mlx5_shared_action_rss *action,
11392                            struct rte_flow_error *error)
11393 {
11394         struct mlx5_flow_rss_desc rss_desc = { 0 };
11395         size_t i;
11396         int err;
11397
11398         if (mlx5_ind_table_obj_setup(dev, action->ind_tbl)) {
11399                 return rte_flow_error_set(error, rte_errno,
11400                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11401                                           "cannot setup indirection table");
11402         }
11403         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
11404         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
11405         rss_desc.const_q = action->origin.queue;
11406         rss_desc.queue_num = action->origin.queue_num;
11407         /* Set non-zero value to indicate a shared RSS. */
11408         rss_desc.shared_rss = action_idx;
11409         rss_desc.ind_tbl = action->ind_tbl;
11410         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11411                 uint32_t hrxq_idx;
11412                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11413                 int tunnel;
11414
11415                 for (tunnel = 0; tunnel < 2; tunnel++) {
11416                         rss_desc.tunnel = tunnel;
11417                         rss_desc.hash_fields = hash_fields;
11418                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
11419                         if (!hrxq_idx) {
11420                                 rte_flow_error_set
11421                                         (error, rte_errno,
11422                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11423                                          "cannot get hash queue");
11424                                 goto error_hrxq_new;
11425                         }
11426                         err = __flow_dv_action_rss_hrxq_set
11427                                 (action, hash_fields, tunnel, hrxq_idx);
11428                         MLX5_ASSERT(!err);
11429                 }
11430         }
11431         return 0;
11432 error_hrxq_new:
11433         err = rte_errno;
11434         __flow_dv_action_rss_hrxqs_release(dev, action);
11435         if (!mlx5_ind_table_obj_release(dev, action->ind_tbl, true))
11436                 action->ind_tbl = NULL;
11437         rte_errno = err;
11438         return -rte_errno;
11439 }
11440
11441 /**
11442  * Create shared RSS action.
11443  *
11444  * @param[in] dev
11445  *   Pointer to the Ethernet device structure.
11446  * @param[in] conf
11447  *   Shared action configuration.
11448  * @param[in] rss
11449  *   RSS action specification used to create shared action.
11450  * @param[out] error
11451  *   Perform verbose error reporting if not NULL. Initialized in case of
11452  *   error only.
11453  *
11454  * @return
11455  *   A valid shared action ID in case of success, 0 otherwise and
11456  *   rte_errno is set.
11457  */
11458 static uint32_t
11459 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11460                             const struct rte_flow_shared_action_conf *conf,
11461                             const struct rte_flow_action_rss *rss,
11462                             struct rte_flow_error *error)
11463 {
11464         struct mlx5_priv *priv = dev->data->dev_private;
11465         struct mlx5_shared_action_rss *shared_action = NULL;
11466         void *queue = NULL;
11467         struct rte_flow_action_rss *origin;
11468         const uint8_t *rss_key;
11469         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11470         uint32_t idx;
11471
11472         RTE_SET_USED(conf);
11473         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11474                             0, SOCKET_ID_ANY);
11475         shared_action = mlx5_ipool_zmalloc
11476                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
11477         if (!shared_action || !queue) {
11478                 rte_flow_error_set(error, ENOMEM,
11479                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11480                                    "cannot allocate resource memory");
11481                 goto error_rss_init;
11482         }
11483         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
11484                 rte_flow_error_set(error, E2BIG,
11485                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11486                                    "rss action number out of range");
11487                 goto error_rss_init;
11488         }
11489         shared_action->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
11490                                              sizeof(*shared_action->ind_tbl),
11491                                              0, SOCKET_ID_ANY);
11492         if (!shared_action->ind_tbl) {
11493                 rte_flow_error_set(error, ENOMEM,
11494                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11495                                    "cannot allocate resource memory");
11496                 goto error_rss_init;
11497         }
11498         memcpy(queue, rss->queue, queue_size);
11499         shared_action->ind_tbl->queues = queue;
11500         shared_action->ind_tbl->queues_n = rss->queue_num;
11501         origin = &shared_action->origin;
11502         origin->func = rss->func;
11503         origin->level = rss->level;
11504         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11505         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11506         /* NULL RSS key indicates default RSS key. */
11507         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11508         memcpy(shared_action->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11509         origin->key = &shared_action->key[0];
11510         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11511         origin->queue = queue;
11512         origin->queue_num = rss->queue_num;
11513         if (__flow_dv_action_rss_setup(dev, idx, shared_action, error))
11514                 goto error_rss_init;
11515         rte_spinlock_init(&shared_action->action_rss_sl);
11516         __atomic_add_fetch(&shared_action->refcnt, 1, __ATOMIC_RELAXED);
11517         rte_spinlock_lock(&priv->shared_act_sl);
11518         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11519                      &priv->rss_shared_actions, idx, shared_action, next);
11520         rte_spinlock_unlock(&priv->shared_act_sl);
11521         return idx;
11522 error_rss_init:
11523         if (shared_action) {
11524                 if (shared_action->ind_tbl)
11525                         mlx5_free(shared_action->ind_tbl);
11526                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11527                                 idx);
11528         }
11529         if (queue)
11530                 mlx5_free(queue);
11531         return 0;
11532 }
11533
11534 /**
11535  * Destroy the shared RSS action.
11536  * Release related hash RX queue objects.
11537  *
11538  * @param[in] dev
11539  *   Pointer to the Ethernet device structure.
11540  * @param[in] idx
11541  *   The shared RSS action object ID to be removed.
11542  * @param[out] error
11543  *   Perform verbose error reporting if not NULL. Initialized in case of
11544  *   error only.
11545  *
11546  * @return
11547  *   0 on success, otherwise negative errno value.
11548  */
11549 static int
11550 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
11551                              struct rte_flow_error *error)
11552 {
11553         struct mlx5_priv *priv = dev->data->dev_private;
11554         struct mlx5_shared_action_rss *shared_rss =
11555             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11556         uint32_t old_refcnt = 1;
11557         int remaining;
11558         uint16_t *queue = NULL;
11559
11560         if (!shared_rss)
11561                 return rte_flow_error_set(error, EINVAL,
11562                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11563                                           "invalid shared action");
11564         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11565         if (remaining)
11566                 return rte_flow_error_set(error, EBUSY,
11567                                           RTE_FLOW_ERROR_TYPE_ACTION,
11568                                           NULL,
11569                                           "shared rss hrxq has references");
11570         queue = shared_rss->ind_tbl->queues;
11571         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
11572         if (remaining)
11573                 return rte_flow_error_set(error, EBUSY,
11574                                           RTE_FLOW_ERROR_TYPE_ACTION,
11575                                           NULL,
11576                                           "shared rss indirection table has"
11577                                           " references");
11578         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
11579                                          0, 0, __ATOMIC_ACQUIRE,
11580                                          __ATOMIC_RELAXED))
11581                 return rte_flow_error_set(error, EBUSY,
11582                                           RTE_FLOW_ERROR_TYPE_ACTION,
11583                                           NULL,
11584                                           "shared rss has references");
11585         mlx5_free(queue);
11586         rte_spinlock_lock(&priv->shared_act_sl);
11587         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11588                      &priv->rss_shared_actions, idx, shared_rss, next);
11589         rte_spinlock_unlock(&priv->shared_act_sl);
11590         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
11591                         idx);
11592         return 0;
11593 }
11594
11595 /**
11596  * Create shared action, lock free,
11597  * (mutex should be acquired by caller).
11598  * Dispatcher for action type specific call.
11599  *
11600  * @param[in] dev
11601  *   Pointer to the Ethernet device structure.
11602  * @param[in] conf
11603  *   Shared action configuration.
11604  * @param[in] action
11605  *   Action specification used to create shared action.
11606  * @param[out] error
11607  *   Perform verbose error reporting if not NULL. Initialized in case of
11608  *   error only.
11609  *
11610  * @return
11611  *   A valid shared action handle in case of success, NULL otherwise and
11612  *   rte_errno is set.
11613  */
11614 static struct rte_flow_shared_action *
11615 flow_dv_action_create(struct rte_eth_dev *dev,
11616                       const struct rte_flow_shared_action_conf *conf,
11617                       const struct rte_flow_action *action,
11618                       struct rte_flow_error *err)
11619 {
11620         uint32_t idx = 0;
11621         uint32_t ret = 0;
11622
11623         switch (action->type) {
11624         case RTE_FLOW_ACTION_TYPE_RSS:
11625                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
11626                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
11627                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11628                 break;
11629         case RTE_FLOW_ACTION_TYPE_AGE:
11630                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
11631                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
11632                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
11633                 if (ret) {
11634                         struct mlx5_aso_age_action *aso_age =
11635                                               flow_aso_age_get_by_idx(dev, ret);
11636
11637                         if (!aso_age->age_params.context)
11638                                 aso_age->age_params.context =
11639                                                          (void *)(uintptr_t)idx;
11640                 }
11641                 break;
11642         default:
11643                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11644                                    NULL, "action type not supported");
11645                 break;
11646         }
11647         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
11648 }
11649
11650 /**
11651  * Destroy the shared action.
11652  * Release action related resources on the NIC and the memory.
11653  * Lock free, (mutex should be acquired by caller).
11654  * Dispatcher for action type specific call.
11655  *
11656  * @param[in] dev
11657  *   Pointer to the Ethernet device structure.
11658  * @param[in] action
11659  *   The shared action object to be removed.
11660  * @param[out] error
11661  *   Perform verbose error reporting if not NULL. Initialized in case of
11662  *   error only.
11663  *
11664  * @return
11665  *   0 on success, otherwise negative errno value.
11666  */
11667 static int
11668 flow_dv_action_destroy(struct rte_eth_dev *dev,
11669                        struct rte_flow_shared_action *action,
11670                        struct rte_flow_error *error)
11671 {
11672         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11673         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11674         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11675         int ret;
11676
11677         switch (type) {
11678         case MLX5_SHARED_ACTION_TYPE_RSS:
11679                 return __flow_dv_action_rss_release(dev, idx, error);
11680         case MLX5_SHARED_ACTION_TYPE_AGE:
11681                 ret = flow_dv_aso_age_release(dev, idx);
11682                 if (ret)
11683                         /*
11684                          * In this case, the last flow has a reference will
11685                          * actually release the age action.
11686                          */
11687                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
11688                                 " released with references %d.", idx, ret);
11689                 return 0;
11690         default:
11691                 return rte_flow_error_set(error, ENOTSUP,
11692                                           RTE_FLOW_ERROR_TYPE_ACTION,
11693                                           NULL,
11694                                           "action type not supported");
11695         }
11696 }
11697
11698 /**
11699  * Updates in place shared RSS action configuration.
11700  *
11701  * @param[in] dev
11702  *   Pointer to the Ethernet device structure.
11703  * @param[in] idx
11704  *   The shared RSS action object ID to be updated.
11705  * @param[in] action_conf
11706  *   RSS action specification used to modify *shared_rss*.
11707  * @param[out] error
11708  *   Perform verbose error reporting if not NULL. Initialized in case of
11709  *   error only.
11710  *
11711  * @return
11712  *   0 on success, otherwise negative errno value.
11713  * @note: currently only support update of RSS queues.
11714  */
11715 static int
11716 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
11717                             const struct rte_flow_action_rss *action_conf,
11718                             struct rte_flow_error *error)
11719 {
11720         struct mlx5_priv *priv = dev->data->dev_private;
11721         struct mlx5_shared_action_rss *shared_rss =
11722             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11723         int ret = 0;
11724         void *queue = NULL;
11725         uint16_t *queue_old = NULL;
11726         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11727
11728         if (!shared_rss)
11729                 return rte_flow_error_set(error, EINVAL,
11730                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11731                                           "invalid shared action to update");
11732         queue = mlx5_malloc(MLX5_MEM_ZERO,
11733                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11734                             0, SOCKET_ID_ANY);
11735         if (!queue)
11736                 return rte_flow_error_set(error, ENOMEM,
11737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11738                                           NULL,
11739                                           "cannot allocate resource memory");
11740         memcpy(queue, action_conf->queue, queue_size);
11741         MLX5_ASSERT(shared_rss->ind_tbl);
11742         rte_spinlock_lock(&shared_rss->action_rss_sl);
11743         queue_old = shared_rss->ind_tbl->queues;
11744         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
11745                                         queue, action_conf->queue_num, true);
11746         if (ret) {
11747                 mlx5_free(queue);
11748                 ret = rte_flow_error_set(error, rte_errno,
11749                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11750                                           "cannot update indirection table");
11751         } else {
11752                 mlx5_free(queue_old);
11753                 shared_rss->origin.queue = queue;
11754                 shared_rss->origin.queue_num = action_conf->queue_num;
11755         }
11756         rte_spinlock_unlock(&shared_rss->action_rss_sl);
11757         return ret;
11758 }
11759
11760 /**
11761  * Updates in place shared action configuration, lock free,
11762  * (mutex should be acquired by caller).
11763  *
11764  * @param[in] dev
11765  *   Pointer to the Ethernet device structure.
11766  * @param[in] action
11767  *   The shared action object to be updated.
11768  * @param[in] action_conf
11769  *   Action specification used to modify *action*.
11770  *   *action_conf* should be of type correlating with type of the *action*,
11771  *   otherwise considered as invalid.
11772  * @param[out] error
11773  *   Perform verbose error reporting if not NULL. Initialized in case of
11774  *   error only.
11775  *
11776  * @return
11777  *   0 on success, otherwise negative errno value.
11778  */
11779 static int
11780 flow_dv_action_update(struct rte_eth_dev *dev,
11781                         struct rte_flow_shared_action *action,
11782                         const void *action_conf,
11783                         struct rte_flow_error *err)
11784 {
11785         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11786         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11787         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11788
11789         switch (type) {
11790         case MLX5_SHARED_ACTION_TYPE_RSS:
11791                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
11792         default:
11793                 return rte_flow_error_set(err, ENOTSUP,
11794                                           RTE_FLOW_ERROR_TYPE_ACTION,
11795                                           NULL,
11796                                           "action type update not supported");
11797         }
11798 }
11799
11800 static int
11801 flow_dv_action_query(struct rte_eth_dev *dev,
11802                      const struct rte_flow_shared_action *action, void *data,
11803                      struct rte_flow_error *error)
11804 {
11805         struct mlx5_age_param *age_param;
11806         struct rte_flow_query_age *resp;
11807         uint32_t act_idx = (uint32_t)(uintptr_t)action;
11808         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
11809         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
11810
11811         switch (type) {
11812         case MLX5_SHARED_ACTION_TYPE_AGE:
11813                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
11814                 resp = data;
11815                 resp->aged = __atomic_load_n(&age_param->state,
11816                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
11817                                                                           1 : 0;
11818                 resp->sec_since_last_hit_valid = !resp->aged;
11819                 if (resp->sec_since_last_hit_valid)
11820                         resp->sec_since_last_hit = __atomic_load_n
11821                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11822                 return 0;
11823         default:
11824                 return rte_flow_error_set(error, ENOTSUP,
11825                                           RTE_FLOW_ERROR_TYPE_ACTION,
11826                                           NULL,
11827                                           "action type query not supported");
11828         }
11829 }
11830
11831 /**
11832  * Query a dv flow  rule for its statistics via devx.
11833  *
11834  * @param[in] dev
11835  *   Pointer to Ethernet device.
11836  * @param[in] flow
11837  *   Pointer to the sub flow.
11838  * @param[out] data
11839  *   data retrieved by the query.
11840  * @param[out] error
11841  *   Perform verbose error reporting if not NULL.
11842  *
11843  * @return
11844  *   0 on success, a negative errno value otherwise and rte_errno is set.
11845  */
11846 static int
11847 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11848                     void *data, struct rte_flow_error *error)
11849 {
11850         struct mlx5_priv *priv = dev->data->dev_private;
11851         struct rte_flow_query_count *qc = data;
11852
11853         if (!priv->config.devx)
11854                 return rte_flow_error_set(error, ENOTSUP,
11855                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11856                                           NULL,
11857                                           "counters are not supported");
11858         if (flow->counter) {
11859                 uint64_t pkts, bytes;
11860                 struct mlx5_flow_counter *cnt;
11861
11862                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11863                                                  NULL);
11864                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11865                                                &bytes);
11866
11867                 if (err)
11868                         return rte_flow_error_set(error, -err,
11869                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11870                                         NULL, "cannot read counters");
11871                 qc->hits_set = 1;
11872                 qc->bytes_set = 1;
11873                 qc->hits = pkts - cnt->hits;
11874                 qc->bytes = bytes - cnt->bytes;
11875                 if (qc->reset) {
11876                         cnt->hits = pkts;
11877                         cnt->bytes = bytes;
11878                 }
11879                 return 0;
11880         }
11881         return rte_flow_error_set(error, EINVAL,
11882                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11883                                   NULL,
11884                                   "counters are not available");
11885 }
11886
11887 /**
11888  * Query a flow rule AGE action for aging information.
11889  *
11890  * @param[in] dev
11891  *   Pointer to Ethernet device.
11892  * @param[in] flow
11893  *   Pointer to the sub flow.
11894  * @param[out] data
11895  *   data retrieved by the query.
11896  * @param[out] error
11897  *   Perform verbose error reporting if not NULL.
11898  *
11899  * @return
11900  *   0 on success, a negative errno value otherwise and rte_errno is set.
11901  */
11902 static int
11903 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11904                   void *data, struct rte_flow_error *error)
11905 {
11906         struct rte_flow_query_age *resp = data;
11907         struct mlx5_age_param *age_param;
11908
11909         if (flow->age) {
11910                 struct mlx5_aso_age_action *act =
11911                                      flow_aso_age_get_by_idx(dev, flow->age);
11912
11913                 age_param = &act->age_params;
11914         } else if (flow->counter) {
11915                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
11916
11917                 if (!age_param || !age_param->timeout)
11918                         return rte_flow_error_set
11919                                         (error, EINVAL,
11920                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11921                                          NULL, "cannot read age data");
11922         } else {
11923                 return rte_flow_error_set(error, EINVAL,
11924                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11925                                           NULL, "age data not available");
11926         }
11927         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
11928                                      AGE_TMOUT ? 1 : 0;
11929         resp->sec_since_last_hit_valid = !resp->aged;
11930         if (resp->sec_since_last_hit_valid)
11931                 resp->sec_since_last_hit = __atomic_load_n
11932                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
11933         return 0;
11934 }
11935
11936 /**
11937  * Query a flow.
11938  *
11939  * @see rte_flow_query()
11940  * @see rte_flow_ops
11941  */
11942 static int
11943 flow_dv_query(struct rte_eth_dev *dev,
11944               struct rte_flow *flow __rte_unused,
11945               const struct rte_flow_action *actions __rte_unused,
11946               void *data __rte_unused,
11947               struct rte_flow_error *error __rte_unused)
11948 {
11949         int ret = -EINVAL;
11950
11951         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11952                 switch (actions->type) {
11953                 case RTE_FLOW_ACTION_TYPE_VOID:
11954                         break;
11955                 case RTE_FLOW_ACTION_TYPE_COUNT:
11956                         ret = flow_dv_query_count(dev, flow, data, error);
11957                         break;
11958                 case RTE_FLOW_ACTION_TYPE_AGE:
11959                         ret = flow_dv_query_age(dev, flow, data, error);
11960                         break;
11961                 default:
11962                         return rte_flow_error_set(error, ENOTSUP,
11963                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11964                                                   actions,
11965                                                   "action not supported");
11966                 }
11967         }
11968         return ret;
11969 }
11970
11971 /**
11972  * Destroy the meter table set.
11973  * Lock free, (mutex should be acquired by caller).
11974  *
11975  * @param[in] dev
11976  *   Pointer to Ethernet device.
11977  * @param[in] tbl
11978  *   Pointer to the meter table set.
11979  *
11980  * @return
11981  *   Always 0.
11982  */
11983 static int
11984 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11985                         struct mlx5_meter_domains_infos *tbl)
11986 {
11987         struct mlx5_priv *priv = dev->data->dev_private;
11988         struct mlx5_meter_domains_infos *mtd =
11989                                 (struct mlx5_meter_domains_infos *)tbl;
11990
11991         if (!mtd || !priv->config.dv_flow_en)
11992                 return 0;
11993         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11994                 claim_zero(mlx5_flow_os_destroy_flow
11995                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11996         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11997                 claim_zero(mlx5_flow_os_destroy_flow
11998                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11999         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
12000                 claim_zero(mlx5_flow_os_destroy_flow
12001                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
12002         if (mtd->egress.color_matcher)
12003                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12004                            (mtd->egress.color_matcher));
12005         if (mtd->egress.any_matcher)
12006                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12007                            (mtd->egress.any_matcher));
12008         if (mtd->egress.tbl)
12009                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
12010         if (mtd->egress.sfx_tbl)
12011                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
12012         if (mtd->ingress.color_matcher)
12013                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12014                            (mtd->ingress.color_matcher));
12015         if (mtd->ingress.any_matcher)
12016                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12017                            (mtd->ingress.any_matcher));
12018         if (mtd->ingress.tbl)
12019                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
12020         if (mtd->ingress.sfx_tbl)
12021                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12022                                              mtd->ingress.sfx_tbl);
12023         if (mtd->transfer.color_matcher)
12024                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12025                            (mtd->transfer.color_matcher));
12026         if (mtd->transfer.any_matcher)
12027                 claim_zero(mlx5_flow_os_destroy_flow_matcher
12028                            (mtd->transfer.any_matcher));
12029         if (mtd->transfer.tbl)
12030                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
12031         if (mtd->transfer.sfx_tbl)
12032                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12033                                              mtd->transfer.sfx_tbl);
12034         if (mtd->drop_actn)
12035                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
12036         mlx5_free(mtd);
12037         return 0;
12038 }
12039
12040 /* Number of meter flow actions, count and jump or count and drop. */
12041 #define METER_ACTIONS 2
12042
12043 /**
12044  * Create specify domain meter table and suffix table.
12045  *
12046  * @param[in] dev
12047  *   Pointer to Ethernet device.
12048  * @param[in,out] mtb
12049  *   Pointer to DV meter table set.
12050  * @param[in] egress
12051  *   Table attribute.
12052  * @param[in] transfer
12053  *   Table attribute.
12054  * @param[in] color_reg_c_idx
12055  *   Reg C index for color match.
12056  *
12057  * @return
12058  *   0 on success, -1 otherwise and rte_errno is set.
12059  */
12060 static int
12061 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
12062                            struct mlx5_meter_domains_infos *mtb,
12063                            uint8_t egress, uint8_t transfer,
12064                            uint32_t color_reg_c_idx)
12065 {
12066         struct mlx5_priv *priv = dev->data->dev_private;
12067         struct mlx5_dev_ctx_shared *sh = priv->sh;
12068         struct mlx5_flow_dv_match_params mask = {
12069                 .size = sizeof(mask.buf),
12070         };
12071         struct mlx5_flow_dv_match_params value = {
12072                 .size = sizeof(value.buf),
12073         };
12074         struct mlx5dv_flow_matcher_attr dv_attr = {
12075                 .type = IBV_FLOW_ATTR_NORMAL,
12076                 .priority = 0,
12077                 .match_criteria_enable = 0,
12078                 .match_mask = (void *)&mask,
12079         };
12080         void *actions[METER_ACTIONS];
12081         struct mlx5_meter_domain_info *dtb;
12082         struct rte_flow_error error;
12083         int i = 0;
12084         int ret;
12085
12086         if (transfer)
12087                 dtb = &mtb->transfer;
12088         else if (egress)
12089                 dtb = &mtb->egress;
12090         else
12091                 dtb = &mtb->ingress;
12092         /* Create the meter table with METER level. */
12093         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
12094                                             egress, transfer, false, NULL, 0,
12095                                             0, &error);
12096         if (!dtb->tbl) {
12097                 DRV_LOG(ERR, "Failed to create meter policer table.");
12098                 return -1;
12099         }
12100         /* Create the meter suffix table with SUFFIX level. */
12101         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
12102                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
12103                                             egress, transfer, false, NULL, 0,
12104                                             0, &error);
12105         if (!dtb->sfx_tbl) {
12106                 DRV_LOG(ERR, "Failed to create meter suffix table.");
12107                 return -1;
12108         }
12109         /* Create matchers, Any and Color. */
12110         dv_attr.priority = 3;
12111         dv_attr.match_criteria_enable = 0;
12112         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12113                                                &dtb->any_matcher);
12114         if (ret) {
12115                 DRV_LOG(ERR, "Failed to create meter"
12116                              " policer default matcher.");
12117                 goto error_exit;
12118         }
12119         dv_attr.priority = 0;
12120         dv_attr.match_criteria_enable =
12121                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
12122         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
12123                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
12124         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
12125                                                &dtb->color_matcher);
12126         if (ret) {
12127                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
12128                 goto error_exit;
12129         }
12130         if (mtb->count_actns[RTE_MTR_DROPPED])
12131                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
12132         actions[i++] = mtb->drop_actn;
12133         /* Default rule: lowest priority, match any, actions: drop. */
12134         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
12135                                        actions,
12136                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
12137         if (ret) {
12138                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
12139                 goto error_exit;
12140         }
12141         return 0;
12142 error_exit:
12143         return -1;
12144 }
12145
12146 /**
12147  * Create the needed meter and suffix tables.
12148  * Lock free, (mutex should be acquired by caller).
12149  *
12150  * @param[in] dev
12151  *   Pointer to Ethernet device.
12152  * @param[in] fm
12153  *   Pointer to the flow meter.
12154  *
12155  * @return
12156  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
12157  */
12158 static struct mlx5_meter_domains_infos *
12159 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
12160                        const struct mlx5_flow_meter *fm)
12161 {
12162         struct mlx5_priv *priv = dev->data->dev_private;
12163         struct mlx5_meter_domains_infos *mtb;
12164         int ret;
12165         int i;
12166
12167         if (!priv->mtr_en) {
12168                 rte_errno = ENOTSUP;
12169                 return NULL;
12170         }
12171         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
12172         if (!mtb) {
12173                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
12174                 return NULL;
12175         }
12176         /* Create meter count actions */
12177         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
12178                 struct mlx5_flow_counter *cnt;
12179                 if (!fm->policer_stats.cnt[i])
12180                         continue;
12181                 cnt = flow_dv_counter_get_by_idx(dev,
12182                       fm->policer_stats.cnt[i], NULL);
12183                 mtb->count_actns[i] = cnt->action;
12184         }
12185         /* Create drop action. */
12186         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
12187         if (ret) {
12188                 DRV_LOG(ERR, "Failed to create drop action.");
12189                 goto error_exit;
12190         }
12191         /* Egress meter table. */
12192         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
12193         if (ret) {
12194                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
12195                 goto error_exit;
12196         }
12197         /* Ingress meter table. */
12198         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
12199         if (ret) {
12200                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
12201                 goto error_exit;
12202         }
12203         /* FDB meter table. */
12204         if (priv->config.dv_esw_en) {
12205                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
12206                                                  priv->mtr_color_reg);
12207                 if (ret) {
12208                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
12209                         goto error_exit;
12210                 }
12211         }
12212         return mtb;
12213 error_exit:
12214         flow_dv_destroy_mtr_tbl(dev, mtb);
12215         return NULL;
12216 }
12217
12218 /**
12219  * Destroy domain policer rule.
12220  *
12221  * @param[in] dt
12222  *   Pointer to domain table.
12223  */
12224 static void
12225 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
12226 {
12227         int i;
12228
12229         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12230                 if (dt->policer_rules[i]) {
12231                         claim_zero(mlx5_flow_os_destroy_flow
12232                                    (dt->policer_rules[i]));
12233                         dt->policer_rules[i] = NULL;
12234                 }
12235         }
12236         if (dt->jump_actn) {
12237                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
12238                 dt->jump_actn = NULL;
12239         }
12240 }
12241
12242 /**
12243  * Destroy policer rules.
12244  *
12245  * @param[in] dev
12246  *   Pointer to Ethernet device.
12247  * @param[in] fm
12248  *   Pointer to flow meter structure.
12249  * @param[in] attr
12250  *   Pointer to flow attributes.
12251  *
12252  * @return
12253  *   Always 0.
12254  */
12255 static int
12256 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
12257                               const struct mlx5_flow_meter *fm,
12258                               const struct rte_flow_attr *attr)
12259 {
12260         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
12261
12262         if (!mtb)
12263                 return 0;
12264         if (attr->egress)
12265                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
12266         if (attr->ingress)
12267                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
12268         if (attr->transfer)
12269                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
12270         return 0;
12271 }
12272
12273 /**
12274  * Create specify domain meter policer rule.
12275  *
12276  * @param[in] fm
12277  *   Pointer to flow meter structure.
12278  * @param[in] mtb
12279  *   Pointer to DV meter table set.
12280  * @param[in] mtr_reg_c
12281  *   Color match REG_C.
12282  *
12283  * @return
12284  *   0 on success, -1 otherwise.
12285  */
12286 static int
12287 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
12288                                     struct mlx5_meter_domain_info *dtb,
12289                                     uint8_t mtr_reg_c)
12290 {
12291         struct mlx5_flow_dv_match_params matcher = {
12292                 .size = sizeof(matcher.buf),
12293         };
12294         struct mlx5_flow_dv_match_params value = {
12295                 .size = sizeof(value.buf),
12296         };
12297         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12298         void *actions[METER_ACTIONS];
12299         int i;
12300         int ret = 0;
12301
12302         /* Create jump action. */
12303         if (!dtb->jump_actn)
12304                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
12305                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
12306         if (ret) {
12307                 DRV_LOG(ERR, "Failed to create policer jump action.");
12308                 goto error;
12309         }
12310         for (i = 0; i < RTE_MTR_DROPPED; i++) {
12311                 int j = 0;
12312
12313                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
12314                                        rte_col_2_mlx5_col(i), UINT8_MAX);
12315                 if (mtb->count_actns[i])
12316                         actions[j++] = mtb->count_actns[i];
12317                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
12318                         actions[j++] = mtb->drop_actn;
12319                 else
12320                         actions[j++] = dtb->jump_actn;
12321                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
12322                                                (void *)&value, j, actions,
12323                                                &dtb->policer_rules[i]);
12324                 if (ret) {
12325                         DRV_LOG(ERR, "Failed to create policer rule.");
12326                         goto error;
12327                 }
12328         }
12329         return 0;
12330 error:
12331         rte_errno = errno;
12332         return -1;
12333 }
12334
12335 /**
12336  * Create policer rules.
12337  *
12338  * @param[in] dev
12339  *   Pointer to Ethernet device.
12340  * @param[in] fm
12341  *   Pointer to flow meter structure.
12342  * @param[in] attr
12343  *   Pointer to flow attributes.
12344  *
12345  * @return
12346  *   0 on success, -1 otherwise.
12347  */
12348 static int
12349 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
12350                              struct mlx5_flow_meter *fm,
12351                              const struct rte_flow_attr *attr)
12352 {
12353         struct mlx5_priv *priv = dev->data->dev_private;
12354         struct mlx5_meter_domains_infos *mtb = fm->mfts;
12355         int ret;
12356
12357         if (attr->egress) {
12358                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
12359                                                 priv->mtr_color_reg);
12360                 if (ret) {
12361                         DRV_LOG(ERR, "Failed to create egress policer.");
12362                         goto error;
12363                 }
12364         }
12365         if (attr->ingress) {
12366                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
12367                                                 priv->mtr_color_reg);
12368                 if (ret) {
12369                         DRV_LOG(ERR, "Failed to create ingress policer.");
12370                         goto error;
12371                 }
12372         }
12373         if (attr->transfer) {
12374                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
12375                                                 priv->mtr_color_reg);
12376                 if (ret) {
12377                         DRV_LOG(ERR, "Failed to create transfer policer.");
12378                         goto error;
12379                 }
12380         }
12381         return 0;
12382 error:
12383         flow_dv_destroy_policer_rules(dev, fm, attr);
12384         return -1;
12385 }
12386
12387 /**
12388  * Validate the batch counter support in root table.
12389  *
12390  * Create a simple flow with invalid counter and drop action on root table to
12391  * validate if batch counter with offset on root table is supported or not.
12392  *
12393  * @param[in] dev
12394  *   Pointer to rte_eth_dev structure.
12395  *
12396  * @return
12397  *   0 on success, a negative errno value otherwise and rte_errno is set.
12398  */
12399 int
12400 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
12401 {
12402         struct mlx5_priv *priv = dev->data->dev_private;
12403         struct mlx5_dev_ctx_shared *sh = priv->sh;
12404         struct mlx5_flow_dv_match_params mask = {
12405                 .size = sizeof(mask.buf),
12406         };
12407         struct mlx5_flow_dv_match_params value = {
12408                 .size = sizeof(value.buf),
12409         };
12410         struct mlx5dv_flow_matcher_attr dv_attr = {
12411                 .type = IBV_FLOW_ATTR_NORMAL,
12412                 .priority = 0,
12413                 .match_criteria_enable = 0,
12414                 .match_mask = (void *)&mask,
12415         };
12416         void *actions[2] = { 0 };
12417         struct mlx5_flow_tbl_resource *tbl = NULL;
12418         struct mlx5_devx_obj *dcs = NULL;
12419         void *matcher = NULL;
12420         void *flow = NULL;
12421         int ret = -1;
12422
12423         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
12424         if (!tbl)
12425                 goto err;
12426         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
12427         if (!dcs)
12428                 goto err;
12429         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
12430                                                     &actions[0]);
12431         if (ret)
12432                 goto err;
12433         actions[1] = priv->drop_queue.hrxq->action;
12434         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
12435         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
12436                                                &matcher);
12437         if (ret)
12438                 goto err;
12439         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
12440                                        actions, &flow);
12441 err:
12442         /*
12443          * If batch counter with offset is not supported, the driver will not
12444          * validate the invalid offset value, flow create should success.
12445          * In this case, it means batch counter is not supported in root table.
12446          *
12447          * Otherwise, if flow create is failed, counter offset is supported.
12448          */
12449         if (flow) {
12450                 DRV_LOG(INFO, "Batch counter is not supported in root "
12451                               "table. Switch to fallback mode.");
12452                 rte_errno = ENOTSUP;
12453                 ret = -rte_errno;
12454                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12455         } else {
12456                 /* Check matcher to make sure validate fail at flow create. */
12457                 if (!matcher || (matcher && errno != EINVAL))
12458                         DRV_LOG(ERR, "Unexpected error in counter offset "
12459                                      "support detection");
12460                 ret = 0;
12461         }
12462         if (actions[0])
12463                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
12464         if (matcher)
12465                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12466         if (tbl)
12467                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
12468         if (dcs)
12469                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12470         return ret;
12471 }
12472
12473 /**
12474  * Query a devx counter.
12475  *
12476  * @param[in] dev
12477  *   Pointer to the Ethernet device structure.
12478  * @param[in] cnt
12479  *   Index to the flow counter.
12480  * @param[in] clear
12481  *   Set to clear the counter statistics.
12482  * @param[out] pkts
12483  *   The statistics value of packets.
12484  * @param[out] bytes
12485  *   The statistics value of bytes.
12486  *
12487  * @return
12488  *   0 on success, otherwise return -1.
12489  */
12490 static int
12491 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12492                       uint64_t *pkts, uint64_t *bytes)
12493 {
12494         struct mlx5_priv *priv = dev->data->dev_private;
12495         struct mlx5_flow_counter *cnt;
12496         uint64_t inn_pkts, inn_bytes;
12497         int ret;
12498
12499         if (!priv->config.devx)
12500                 return -1;
12501
12502         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12503         if (ret)
12504                 return -1;
12505         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12506         *pkts = inn_pkts - cnt->hits;
12507         *bytes = inn_bytes - cnt->bytes;
12508         if (clear) {
12509                 cnt->hits = inn_pkts;
12510                 cnt->bytes = inn_bytes;
12511         }
12512         return 0;
12513 }
12514
12515 /**
12516  * Get aged-out flows.
12517  *
12518  * @param[in] dev
12519  *   Pointer to the Ethernet device structure.
12520  * @param[in] context
12521  *   The address of an array of pointers to the aged-out flows contexts.
12522  * @param[in] nb_contexts
12523  *   The length of context array pointers.
12524  * @param[out] error
12525  *   Perform verbose error reporting if not NULL. Initialized in case of
12526  *   error only.
12527  *
12528  * @return
12529  *   how many contexts get in success, otherwise negative errno value.
12530  *   if nb_contexts is 0, return the amount of all aged contexts.
12531  *   if nb_contexts is not 0 , return the amount of aged flows reported
12532  *   in the context array.
12533  * @note: only stub for now
12534  */
12535 static int
12536 flow_get_aged_flows(struct rte_eth_dev *dev,
12537                     void **context,
12538                     uint32_t nb_contexts,
12539                     struct rte_flow_error *error)
12540 {
12541         struct mlx5_priv *priv = dev->data->dev_private;
12542         struct mlx5_age_info *age_info;
12543         struct mlx5_age_param *age_param;
12544         struct mlx5_flow_counter *counter;
12545         struct mlx5_aso_age_action *act;
12546         int nb_flows = 0;
12547
12548         if (nb_contexts && !context)
12549                 return rte_flow_error_set(error, EINVAL,
12550                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12551                                           NULL, "empty context");
12552         age_info = GET_PORT_AGE_INFO(priv);
12553         rte_spinlock_lock(&age_info->aged_sl);
12554         LIST_FOREACH(act, &age_info->aged_aso, next) {
12555                 nb_flows++;
12556                 if (nb_contexts) {
12557                         context[nb_flows - 1] =
12558                                                 act->age_params.context;
12559                         if (!(--nb_contexts))
12560                                 break;
12561                 }
12562         }
12563         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12564                 nb_flows++;
12565                 if (nb_contexts) {
12566                         age_param = MLX5_CNT_TO_AGE(counter);
12567                         context[nb_flows - 1] = age_param->context;
12568                         if (!(--nb_contexts))
12569                                 break;
12570                 }
12571         }
12572         rte_spinlock_unlock(&age_info->aged_sl);
12573         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12574         return nb_flows;
12575 }
12576
12577 /*
12578  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12579  */
12580 static uint32_t
12581 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12582 {
12583         return flow_dv_counter_alloc(dev, 0);
12584 }
12585
12586 /**
12587  * Validate shared action.
12588  * Dispatcher for action type specific validation.
12589  *
12590  * @param[in] dev
12591  *   Pointer to the Ethernet device structure.
12592  * @param[in] conf
12593  *   Shared action configuration.
12594  * @param[in] action
12595  *   The shared action object to validate.
12596  * @param[out] error
12597  *   Perform verbose error reporting if not NULL. Initialized in case of
12598  *   error only.
12599  *
12600  * @return
12601  *   0 on success, otherwise negative errno value.
12602  */
12603 static int
12604 flow_dv_action_validate(struct rte_eth_dev *dev,
12605                         const struct rte_flow_shared_action_conf *conf,
12606                         const struct rte_flow_action *action,
12607                         struct rte_flow_error *err)
12608 {
12609         struct mlx5_priv *priv = dev->data->dev_private;
12610
12611         RTE_SET_USED(conf);
12612         switch (action->type) {
12613         case RTE_FLOW_ACTION_TYPE_RSS:
12614                 return mlx5_validate_action_rss(dev, action, err);
12615         case RTE_FLOW_ACTION_TYPE_AGE:
12616                 if (!priv->sh->aso_age_mng)
12617                         return rte_flow_error_set(err, ENOTSUP,
12618                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12619                                                 NULL,
12620                                              "shared age action not supported");
12621                 return flow_dv_validate_action_age(0, action, dev, err);
12622         default:
12623                 return rte_flow_error_set(err, ENOTSUP,
12624                                           RTE_FLOW_ERROR_TYPE_ACTION,
12625                                           NULL,
12626                                           "action type not supported");
12627         }
12628 }
12629
12630 static int
12631 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12632 {
12633         struct mlx5_priv *priv = dev->data->dev_private;
12634         int ret = 0;
12635
12636         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12637                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
12638                                                 flags);
12639                 if (ret != 0)
12640                         return ret;
12641         }
12642         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12643                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
12644                 if (ret != 0)
12645                         return ret;
12646         }
12647         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12648                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
12649                 if (ret != 0)
12650                         return ret;
12651         }
12652         return 0;
12653 }
12654
12655 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12656         .validate = flow_dv_validate,
12657         .prepare = flow_dv_prepare,
12658         .translate = flow_dv_translate,
12659         .apply = flow_dv_apply,
12660         .remove = flow_dv_remove,
12661         .destroy = flow_dv_destroy,
12662         .query = flow_dv_query,
12663         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12664         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12665         .create_policer_rules = flow_dv_create_policer_rules,
12666         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12667         .counter_alloc = flow_dv_counter_allocate,
12668         .counter_free = flow_dv_counter_free,
12669         .counter_query = flow_dv_counter_query,
12670         .get_aged_flows = flow_get_aged_flows,
12671         .action_validate = flow_dv_action_validate,
12672         .action_create = flow_dv_action_create,
12673         .action_destroy = flow_dv_action_destroy,
12674         .action_update = flow_dv_action_update,
12675         .action_query = flow_dv_action_query,
12676         .sync_domain = flow_dv_sync_domain,
12677 };
12678
12679 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12680