drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rx.h"
  36 #include "mlx5_tx.h"
  37 #include "rte_pmd_mlx5.h"
  38
  39 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  40
  41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  43 #endif
  44
  45 #ifndef HAVE_MLX5DV_DR_ESWITCH
  46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  48 #endif
  49 #endif
  50
  51 #ifndef HAVE_MLX5DV_DR
  52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  53 #endif
  54
  55 /* VLAN header definitions */
  56 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  57 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  58 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  61
  62 union flow_dv_attr {
  63         struct {
  64                 uint32_t valid:1;
  65                 uint32_t ipv4:1;
  66                 uint32_t ipv6:1;
  67                 uint32_t tcp:1;
  68                 uint32_t udp:1;
  69                 uint32_t reserved:27;
  70         };
  71         uint32_t attr;
  72 };
  73
  74 static int
  75 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  76                              struct mlx5_flow_tbl_resource *tbl);
  77
  78 static int
  79 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  80                                      uint32_t encap_decap_idx);
  81
  82 static int
  83 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  84                                         uint32_t port_id);
  85 static void
  86 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  87
  88 static int
  89 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  90                                   uint32_t rix_jump);
  91
  92 /**
  93  * Initialize flow attributes structure according to flow items' types.
  94  *
  95  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  96  * mode. For tunnel mode, the items to be modified are the outermost ones.
  97  *
  98  * @param[in] item
  99  *   Pointer to item specification.
 100  * @param[out] attr
 101  *   Pointer to flow attributes structure.
 102  * @param[in] dev_flow
 103  *   Pointer to the sub flow.
 104  * @param[in] tunnel_decap
 105  *   Whether action is after tunnel decapsulation.
 106  */
 107 static void
 108 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 109                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 110 {
 111         uint64_t layers = dev_flow->handle->layers;
 112
 113         /*
 114          * If layers is already initialized, it means this dev_flow is the
 115          * suffix flow, the layers flags is set by the prefix flow. Need to
 116          * use the layer flags from prefix flow as the suffix flow may not
 117          * have the user defined items as the flow is split.
 118          */
 119         if (layers) {
 120                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 121                         attr->ipv4 = 1;
 122                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 123                         attr->ipv6 = 1;
 124                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 125                         attr->tcp = 1;
 126                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 127                         attr->udp = 1;
 128                 attr->valid = 1;
 129                 return;
 130         }
 131         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 132                 uint8_t next_protocol = 0xff;
 133                 switch (item->type) {
 134                 case RTE_FLOW_ITEM_TYPE_GRE:
 135                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 137                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 138                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 139                 case RTE_FLOW_ITEM_TYPE_MPLS:
 140                         if (tunnel_decap)
 141                                 attr->attr = 0;
 142                         break;
 143                 case RTE_FLOW_ITEM_TYPE_IPV4:
 144                         if (!attr->ipv6)
 145                                 attr->ipv4 = 1;
 146                         if (item->mask != NULL &&
 147                             ((const struct rte_flow_item_ipv4 *)
 148                             item->mask)->hdr.next_proto_id)
 149                                 next_protocol =
 150                                     ((const struct rte_flow_item_ipv4 *)
 151                                       (item->spec))->hdr.next_proto_id &
 152                                     ((const struct rte_flow_item_ipv4 *)
 153                                       (item->mask))->hdr.next_proto_id;
 154                         if ((next_protocol == IPPROTO_IPIP ||
 155                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 156                                 attr->attr = 0;
 157                         break;
 158                 case RTE_FLOW_ITEM_TYPE_IPV6:
 159                         if (!attr->ipv4)
 160                                 attr->ipv6 = 1;
 161                         if (item->mask != NULL &&
 162                             ((const struct rte_flow_item_ipv6 *)
 163                             item->mask)->hdr.proto)
 164                                 next_protocol =
 165                                     ((const struct rte_flow_item_ipv6 *)
 166                                       (item->spec))->hdr.proto &
 167                                     ((const struct rte_flow_item_ipv6 *)
 168                                       (item->mask))->hdr.proto;
 169                         if ((next_protocol == IPPROTO_IPIP ||
 170                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 171                                 attr->attr = 0;
 172                         break;
 173                 case RTE_FLOW_ITEM_TYPE_UDP:
 174                         if (!attr->tcp)
 175                                 attr->udp = 1;
 176                         break;
 177                 case RTE_FLOW_ITEM_TYPE_TCP:
 178                         if (!attr->udp)
 179                                 attr->tcp = 1;
 180                         break;
 181                 default:
 182                         break;
 183                 }
 184         }
 185         attr->valid = 1;
 186 }
 187
 188 /**
 189  * Convert rte_mtr_color to mlx5 color.
 190  *
 191  * @param[in] rcol
 192  *   rte_mtr_color.
 193  *
 194  * @return
 195  *   mlx5 color.
 196  */
 197 static int
 198 rte_col_2_mlx5_col(enum rte_color rcol)
 199 {
 200         switch (rcol) {
 201         case RTE_COLOR_GREEN:
 202                 return MLX5_FLOW_COLOR_GREEN;
 203         case RTE_COLOR_YELLOW:
 204                 return MLX5_FLOW_COLOR_YELLOW;
 205         case RTE_COLOR_RED:
 206                 return MLX5_FLOW_COLOR_RED;
 207         default:
 208                 break;
 209         }
 210         return MLX5_FLOW_COLOR_UNDEFINED;
 211 }
 212
 213 struct field_modify_info {
 214         uint32_t size; /* Size of field in protocol header, in bytes. */
 215         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 216         enum mlx5_modification_field id;
 217 };
 218
 219 struct field_modify_info modify_eth[] = {
 220         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 221         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 222         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 223         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 224         {0, 0, 0},
 225 };
 226
 227 struct field_modify_info modify_vlan_out_first_vid[] = {
 228         /* Size in bits !!! */
 229         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 230         {0, 0, 0},
 231 };
 232
 233 struct field_modify_info modify_ipv4[] = {
 234         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 235         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 236         {4, 12, MLX5_MODI_OUT_SIPV4},
 237         {4, 16, MLX5_MODI_OUT_DIPV4},
 238         {0, 0, 0},
 239 };
 240
 241 struct field_modify_info modify_ipv6[] = {
 242         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 243         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 244         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 245         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 246         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 247         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 248         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 249         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 250         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 251         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 252         {0, 0, 0},
 253 };
 254
 255 struct field_modify_info modify_udp[] = {
 256         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 257         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 258         {0, 0, 0},
 259 };
 260
 261 struct field_modify_info modify_tcp[] = {
 262         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 263         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 264         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 265         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 266         {0, 0, 0},
 267 };
 268
 269 static void
 270 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 271                           uint8_t next_protocol, uint64_t *item_flags,
 272                           int *tunnel)
 273 {
 274         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 275                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 276         if (next_protocol == IPPROTO_IPIP) {
 277                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 278                 *tunnel = 1;
 279         }
 280         if (next_protocol == IPPROTO_IPV6) {
 281                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 282                 *tunnel = 1;
 283         }
 284 }
 285
 286 /* Update VLAN's VID/PCP based on input rte_flow_action.
 287  *
 288  * @param[in] action
 289  *   Pointer to struct rte_flow_action.
 290  * @param[out] vlan
 291  *   Pointer to struct rte_vlan_hdr.
 292  */
 293 static void
 294 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 295                          struct rte_vlan_hdr *vlan)
 296 {
 297         uint16_t vlan_tci;
 298         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 299                 vlan_tci =
 300                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 301                                                action->conf)->vlan_pcp;
 302                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 303                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 304                 vlan->vlan_tci |= vlan_tci;
 305         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 306                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 307                 vlan->vlan_tci |= rte_be_to_cpu_16
 308                     (((const struct rte_flow_action_of_set_vlan_vid *)
 309                                              action->conf)->vlan_vid);
 310         }
 311 }
 312
 313 /**
 314  * Fetch 1, 2, 3 or 4 byte field from the byte array
 315  * and return as unsigned integer in host-endian format.
 316  *
 317  * @param[in] data
 318  *   Pointer to data array.
 319  * @param[in] size
 320  *   Size of field to extract.
 321  *
 322  * @return
 323  *   converted field in host endian format.
 324  */
 325 static inline uint32_t
 326 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 327 {
 328         uint32_t ret;
 329
 330         switch (size) {
 331         case 1:
 332                 ret = *data;
 333                 break;
 334         case 2:
 335                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 336                 break;
 337         case 3:
 338                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 339                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 340                 break;
 341         case 4:
 342                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 343                 break;
 344         default:
 345                 MLX5_ASSERT(false);
 346                 ret = 0;
 347                 break;
 348         }
 349         return ret;
 350 }
 351
 352 /**
 353  * Convert modify-header action to DV specification.
 354  *
 355  * Data length of each action is determined by provided field description
 356  * and the item mask. Data bit offset and width of each action is determined
 357  * by provided item mask.
 358  *
 359  * @param[in] item
 360  *   Pointer to item specification.
 361  * @param[in] field
 362  *   Pointer to field modification information.
 363  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 365  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 366  * @param[in] dcopy
 367  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 368  *   Negative offset value sets the same offset as source offset.
 369  *   size field is ignored, value is taken from source field.
 370  * @param[in,out] resource
 371  *   Pointer to the modify-header resource.
 372  * @param[in] type
 373  *   Type of modification.
 374  * @param[out] error
 375  *   Pointer to the error structure.
 376  *
 377  * @return
 378  *   0 on success, a negative errno value otherwise and rte_errno is set.
 379  */
 380 static int
 381 flow_dv_convert_modify_action(struct rte_flow_item *item,
 382                               struct field_modify_info *field,
 383                               struct field_modify_info *dcopy,
 384                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 385                               uint32_t type, struct rte_flow_error *error)
 386 {
 387         uint32_t i = resource->actions_num;
 388         struct mlx5_modification_cmd *actions = resource->actions;
 389
 390         /*
 391          * The item and mask are provided in big-endian format.
 392          * The fields should be presented as in big-endian format either.
 393          * Mask must be always present, it defines the actual field width.
 394          */
 395         MLX5_ASSERT(item->mask);
 396         MLX5_ASSERT(field->size);
 397         do {
 398                 unsigned int size_b;
 399                 unsigned int off_b;
 400                 uint32_t mask;
 401                 uint32_t data;
 402
 403                 if (i >= MLX5_MAX_MODIFY_NUM)
 404                         return rte_flow_error_set(error, EINVAL,
 405                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 406                                  "too many items to modify");
 407                 /* Fetch variable byte size mask from the array. */
 408                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 409                                            field->offset, field->size);
 410                 if (!mask) {
 411                         ++field;
 412                         continue;
 413                 }
 414                 /* Deduce actual data width in bits from mask value. */
 415                 off_b = rte_bsf32(mask);
 416                 size_b = sizeof(uint32_t) * CHAR_BIT -
 417                          off_b - __builtin_clz(mask);
 418                 MLX5_ASSERT(size_b);
 419                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 420                 actions[i] = (struct mlx5_modification_cmd) {
 421                         .action_type = type,
 422                         .field = field->id,
 423                         .offset = off_b,
 424                         .length = size_b,
 425                 };
 426                 /* Convert entire record to expected big-endian format. */
 427                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 428                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 429                         MLX5_ASSERT(dcopy);
 430                         actions[i].dst_field = dcopy->id;
 431                         actions[i].dst_offset =
 432                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 433                         /* Convert entire record to big-endian format. */
 434                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 435                         ++dcopy;
 436                 } else {
 437                         MLX5_ASSERT(item->spec);
 438                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 439                                                    field->offset, field->size);
 440                         /* Shift out the trailing masked bits from data. */
 441                         data = (data & mask) >> off_b;
 442                         actions[i].data1 = rte_cpu_to_be_32(data);
 443                 }
 444                 ++i;
 445                 ++field;
 446         } while (field->size);
 447         if (resource->actions_num == i)
 448                 return rte_flow_error_set(error, EINVAL,
 449                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 450                                           "invalid modification flow item");
 451         resource->actions_num = i;
 452         return 0;
 453 }
 454
 455 /**
 456  * Convert modify-header set IPv4 address action to DV specification.
 457  *
 458  * @param[in,out] resource
 459  *   Pointer to the modify-header resource.
 460  * @param[in] action
 461  *   Pointer to action specification.
 462  * @param[out] error
 463  *   Pointer to the error structure.
 464  *
 465  * @return
 466  *   0 on success, a negative errno value otherwise and rte_errno is set.
 467  */
 468 static int
 469 flow_dv_convert_action_modify_ipv4
 470                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 471                          const struct rte_flow_action *action,
 472                          struct rte_flow_error *error)
 473 {
 474         const struct rte_flow_action_set_ipv4 *conf =
 475                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 476         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 477         struct rte_flow_item_ipv4 ipv4;
 478         struct rte_flow_item_ipv4 ipv4_mask;
 479
 480         memset(&ipv4, 0, sizeof(ipv4));
 481         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 482         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 483                 ipv4.hdr.src_addr = conf->ipv4_addr;
 484                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 485         } else {
 486                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 487                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 488         }
 489         item.spec = &ipv4;
 490         item.mask = &ipv4_mask;
 491         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 492                                              MLX5_MODIFICATION_TYPE_SET, error);
 493 }
 494
 495 /**
 496  * Convert modify-header set IPv6 address action to DV specification.
 497  *
 498  * @param[in,out] resource
 499  *   Pointer to the modify-header resource.
 500  * @param[in] action
 501  *   Pointer to action specification.
 502  * @param[out] error
 503  *   Pointer to the error structure.
 504  *
 505  * @return
 506  *   0 on success, a negative errno value otherwise and rte_errno is set.
 507  */
 508 static int
 509 flow_dv_convert_action_modify_ipv6
 510                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 511                          const struct rte_flow_action *action,
 512                          struct rte_flow_error *error)
 513 {
 514         const struct rte_flow_action_set_ipv6 *conf =
 515                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 516         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 517         struct rte_flow_item_ipv6 ipv6;
 518         struct rte_flow_item_ipv6 ipv6_mask;
 519
 520         memset(&ipv6, 0, sizeof(ipv6));
 521         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 522         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 523                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 524                        sizeof(ipv6.hdr.src_addr));
 525                 memcpy(&ipv6_mask.hdr.src_addr,
 526                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 527                        sizeof(ipv6.hdr.src_addr));
 528         } else {
 529                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 530                        sizeof(ipv6.hdr.dst_addr));
 531                 memcpy(&ipv6_mask.hdr.dst_addr,
 532                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 533                        sizeof(ipv6.hdr.dst_addr));
 534         }
 535         item.spec = &ipv6;
 536         item.mask = &ipv6_mask;
 537         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 538                                              MLX5_MODIFICATION_TYPE_SET, error);
 539 }
 540
 541 /**
 542  * Convert modify-header set MAC address action to DV specification.
 543  *
 544  * @param[in,out] resource
 545  *   Pointer to the modify-header resource.
 546  * @param[in] action
 547  *   Pointer to action specification.
 548  * @param[out] error
 549  *   Pointer to the error structure.
 550  *
 551  * @return
 552  *   0 on success, a negative errno value otherwise and rte_errno is set.
 553  */
 554 static int
 555 flow_dv_convert_action_modify_mac
 556                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 557                          const struct rte_flow_action *action,
 558                          struct rte_flow_error *error)
 559 {
 560         const struct rte_flow_action_set_mac *conf =
 561                 (const struct rte_flow_action_set_mac *)(action->conf);
 562         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 563         struct rte_flow_item_eth eth;
 564         struct rte_flow_item_eth eth_mask;
 565
 566         memset(&eth, 0, sizeof(eth));
 567         memset(&eth_mask, 0, sizeof(eth_mask));
 568         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 569                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 570                        sizeof(eth.src.addr_bytes));
 571                 memcpy(&eth_mask.src.addr_bytes,
 572                        &rte_flow_item_eth_mask.src.addr_bytes,
 573                        sizeof(eth_mask.src.addr_bytes));
 574         } else {
 575                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 576                        sizeof(eth.dst.addr_bytes));
 577                 memcpy(&eth_mask.dst.addr_bytes,
 578                        &rte_flow_item_eth_mask.dst.addr_bytes,
 579                        sizeof(eth_mask.dst.addr_bytes));
 580         }
 581         item.spec = &eth;
 582         item.mask = &eth_mask;
 583         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 584                                              MLX5_MODIFICATION_TYPE_SET, error);
 585 }
 586
 587 /**
 588  * Convert modify-header set VLAN VID action to DV specification.
 589  *
 590  * @param[in,out] resource
 591  *   Pointer to the modify-header resource.
 592  * @param[in] action
 593  *   Pointer to action specification.
 594  * @param[out] error
 595  *   Pointer to the error structure.
 596  *
 597  * @return
 598  *   0 on success, a negative errno value otherwise and rte_errno is set.
 599  */
 600 static int
 601 flow_dv_convert_action_modify_vlan_vid
 602                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 603                          const struct rte_flow_action *action,
 604                          struct rte_flow_error *error)
 605 {
 606         const struct rte_flow_action_of_set_vlan_vid *conf =
 607                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 608         int i = resource->actions_num;
 609         struct mlx5_modification_cmd *actions = resource->actions;
 610         struct field_modify_info *field = modify_vlan_out_first_vid;
 611
 612         if (i >= MLX5_MAX_MODIFY_NUM)
 613                 return rte_flow_error_set(error, EINVAL,
 614                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 615                          "too many items to modify");
 616         actions[i] = (struct mlx5_modification_cmd) {
 617                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 618                 .field = field->id,
 619                 .length = field->size,
 620                 .offset = field->offset,
 621         };
 622         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 623         actions[i].data1 = conf->vlan_vid;
 624         actions[i].data1 = actions[i].data1 << 16;
 625         resource->actions_num = ++i;
 626         return 0;
 627 }
 628
 629 /**
 630  * Convert modify-header set TP action to DV specification.
 631  *
 632  * @param[in,out] resource
 633  *   Pointer to the modify-header resource.
 634  * @param[in] action
 635  *   Pointer to action specification.
 636  * @param[in] items
 637  *   Pointer to rte_flow_item objects list.
 638  * @param[in] attr
 639  *   Pointer to flow attributes structure.
 640  * @param[in] dev_flow
 641  *   Pointer to the sub flow.
 642  * @param[in] tunnel_decap
 643  *   Whether action is after tunnel decapsulation.
 644  * @param[out] error
 645  *   Pointer to the error structure.
 646  *
 647  * @return
 648  *   0 on success, a negative errno value otherwise and rte_errno is set.
 649  */
 650 static int
 651 flow_dv_convert_action_modify_tp
 652                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 653                          const struct rte_flow_action *action,
 654                          const struct rte_flow_item *items,
 655                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 656                          bool tunnel_decap, struct rte_flow_error *error)
 657 {
 658         const struct rte_flow_action_set_tp *conf =
 659                 (const struct rte_flow_action_set_tp *)(action->conf);
 660         struct rte_flow_item item;
 661         struct rte_flow_item_udp udp;
 662         struct rte_flow_item_udp udp_mask;
 663         struct rte_flow_item_tcp tcp;
 664         struct rte_flow_item_tcp tcp_mask;
 665         struct field_modify_info *field;
 666
 667         if (!attr->valid)
 668                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 669         if (attr->udp) {
 670                 memset(&udp, 0, sizeof(udp));
 671                 memset(&udp_mask, 0, sizeof(udp_mask));
 672                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 673                         udp.hdr.src_port = conf->port;
 674                         udp_mask.hdr.src_port =
 675                                         rte_flow_item_udp_mask.hdr.src_port;
 676                 } else {
 677                         udp.hdr.dst_port = conf->port;
 678                         udp_mask.hdr.dst_port =
 679                                         rte_flow_item_udp_mask.hdr.dst_port;
 680                 }
 681                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 682                 item.spec = &udp;
 683                 item.mask = &udp_mask;
 684                 field = modify_udp;
 685         } else {
 686                 MLX5_ASSERT(attr->tcp);
 687                 memset(&tcp, 0, sizeof(tcp));
 688                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 689                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 690                         tcp.hdr.src_port = conf->port;
 691                         tcp_mask.hdr.src_port =
 692                                         rte_flow_item_tcp_mask.hdr.src_port;
 693                 } else {
 694                         tcp.hdr.dst_port = conf->port;
 695                         tcp_mask.hdr.dst_port =
 696                                         rte_flow_item_tcp_mask.hdr.dst_port;
 697                 }
 698                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 699                 item.spec = &tcp;
 700                 item.mask = &tcp_mask;
 701                 field = modify_tcp;
 702         }
 703         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 704                                              MLX5_MODIFICATION_TYPE_SET, error);
 705 }
 706
 707 /**
 708  * Convert modify-header set TTL action to DV specification.
 709  *
 710  * @param[in,out] resource
 711  *   Pointer to the modify-header resource.
 712  * @param[in] action
 713  *   Pointer to action specification.
 714  * @param[in] items
 715  *   Pointer to rte_flow_item objects list.
 716  * @param[in] attr
 717  *   Pointer to flow attributes structure.
 718  * @param[in] dev_flow
 719  *   Pointer to the sub flow.
 720  * @param[in] tunnel_decap
 721  *   Whether action is after tunnel decapsulation.
 722  * @param[out] error
 723  *   Pointer to the error structure.
 724  *
 725  * @return
 726  *   0 on success, a negative errno value otherwise and rte_errno is set.
 727  */
 728 static int
 729 flow_dv_convert_action_modify_ttl
 730                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 731                          const struct rte_flow_action *action,
 732                          const struct rte_flow_item *items,
 733                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 734                          bool tunnel_decap, struct rte_flow_error *error)
 735 {
 736         const struct rte_flow_action_set_ttl *conf =
 737                 (const struct rte_flow_action_set_ttl *)(action->conf);
 738         struct rte_flow_item item;
 739         struct rte_flow_item_ipv4 ipv4;
 740         struct rte_flow_item_ipv4 ipv4_mask;
 741         struct rte_flow_item_ipv6 ipv6;
 742         struct rte_flow_item_ipv6 ipv6_mask;
 743         struct field_modify_info *field;
 744
 745         if (!attr->valid)
 746                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 747         if (attr->ipv4) {
 748                 memset(&ipv4, 0, sizeof(ipv4));
 749                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 750                 ipv4.hdr.time_to_live = conf->ttl_value;
 751                 ipv4_mask.hdr.time_to_live = 0xFF;
 752                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 753                 item.spec = &ipv4;
 754                 item.mask = &ipv4_mask;
 755                 field = modify_ipv4;
 756         } else {
 757                 MLX5_ASSERT(attr->ipv6);
 758                 memset(&ipv6, 0, sizeof(ipv6));
 759                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 760                 ipv6.hdr.hop_limits = conf->ttl_value;
 761                 ipv6_mask.hdr.hop_limits = 0xFF;
 762                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 763                 item.spec = &ipv6;
 764                 item.mask = &ipv6_mask;
 765                 field = modify_ipv6;
 766         }
 767         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 768                                              MLX5_MODIFICATION_TYPE_SET, error);
 769 }
 770
 771 /**
 772  * Convert modify-header decrement TTL action to DV specification.
 773  *
 774  * @param[in,out] resource
 775  *   Pointer to the modify-header resource.
 776  * @param[in] action
 777  *   Pointer to action specification.
 778  * @param[in] items
 779  *   Pointer to rte_flow_item objects list.
 780  * @param[in] attr
 781  *   Pointer to flow attributes structure.
 782  * @param[in] dev_flow
 783  *   Pointer to the sub flow.
 784  * @param[in] tunnel_decap
 785  *   Whether action is after tunnel decapsulation.
 786  * @param[out] error
 787  *   Pointer to the error structure.
 788  *
 789  * @return
 790  *   0 on success, a negative errno value otherwise and rte_errno is set.
 791  */
 792 static int
 793 flow_dv_convert_action_modify_dec_ttl
 794                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 795                          const struct rte_flow_item *items,
 796                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 797                          bool tunnel_decap, struct rte_flow_error *error)
 798 {
 799         struct rte_flow_item item;
 800         struct rte_flow_item_ipv4 ipv4;
 801         struct rte_flow_item_ipv4 ipv4_mask;
 802         struct rte_flow_item_ipv6 ipv6;
 803         struct rte_flow_item_ipv6 ipv6_mask;
 804         struct field_modify_info *field;
 805
 806         if (!attr->valid)
 807                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 808         if (attr->ipv4) {
 809                 memset(&ipv4, 0, sizeof(ipv4));
 810                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 811                 ipv4.hdr.time_to_live = 0xFF;
 812                 ipv4_mask.hdr.time_to_live = 0xFF;
 813                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 814                 item.spec = &ipv4;
 815                 item.mask = &ipv4_mask;
 816                 field = modify_ipv4;
 817         } else {
 818                 MLX5_ASSERT(attr->ipv6);
 819                 memset(&ipv6, 0, sizeof(ipv6));
 820                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 821                 ipv6.hdr.hop_limits = 0xFF;
 822                 ipv6_mask.hdr.hop_limits = 0xFF;
 823                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 824                 item.spec = &ipv6;
 825                 item.mask = &ipv6_mask;
 826                 field = modify_ipv6;
 827         }
 828         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 829                                              MLX5_MODIFICATION_TYPE_ADD, error);
 830 }
 831
 832 /**
 833  * Convert modify-header increment/decrement TCP Sequence number
 834  * to DV specification.
 835  *
 836  * @param[in,out] resource
 837  *   Pointer to the modify-header resource.
 838  * @param[in] action
 839  *   Pointer to action specification.
 840  * @param[out] error
 841  *   Pointer to the error structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 static int
 847 flow_dv_convert_action_modify_tcp_seq
 848                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 849                          const struct rte_flow_action *action,
 850                          struct rte_flow_error *error)
 851 {
 852         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 853         uint64_t value = rte_be_to_cpu_32(*conf);
 854         struct rte_flow_item item;
 855         struct rte_flow_item_tcp tcp;
 856         struct rte_flow_item_tcp tcp_mask;
 857
 858         memset(&tcp, 0, sizeof(tcp));
 859         memset(&tcp_mask, 0, sizeof(tcp_mask));
 860         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 861                 /*
 862                  * The HW has no decrement operation, only increment operation.
 863                  * To simulate decrement X from Y using increment operation
 864                  * we need to add UINT32_MAX X times to Y.
 865                  * Each adding of UINT32_MAX decrements Y by 1.
 866                  */
 867                 value *= UINT32_MAX;
 868         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 869         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 870         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 871         item.spec = &tcp;
 872         item.mask = &tcp_mask;
 873         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 874                                              MLX5_MODIFICATION_TYPE_ADD, error);
 875 }
 876
 877 /**
 878  * Convert modify-header increment/decrement TCP Acknowledgment number
 879  * to DV specification.
 880  *
 881  * @param[in,out] resource
 882  *   Pointer to the modify-header resource.
 883  * @param[in] action
 884  *   Pointer to action specification.
 885  * @param[out] error
 886  *   Pointer to the error structure.
 887  *
 888  * @return
 889  *   0 on success, a negative errno value otherwise and rte_errno is set.
 890  */
 891 static int
 892 flow_dv_convert_action_modify_tcp_ack
 893                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 894                          const struct rte_flow_action *action,
 895                          struct rte_flow_error *error)
 896 {
 897         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 898         uint64_t value = rte_be_to_cpu_32(*conf);
 899         struct rte_flow_item item;
 900         struct rte_flow_item_tcp tcp;
 901         struct rte_flow_item_tcp tcp_mask;
 902
 903         memset(&tcp, 0, sizeof(tcp));
 904         memset(&tcp_mask, 0, sizeof(tcp_mask));
 905         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 906                 /*
 907                  * The HW has no decrement operation, only increment operation.
 908                  * To simulate decrement X from Y using increment operation
 909                  * we need to add UINT32_MAX X times to Y.
 910                  * Each adding of UINT32_MAX decrements Y by 1.
 911                  */
 912                 value *= UINT32_MAX;
 913         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 914         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 915         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 916         item.spec = &tcp;
 917         item.mask = &tcp_mask;
 918         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 919                                              MLX5_MODIFICATION_TYPE_ADD, error);
 920 }
 921
 922 static enum mlx5_modification_field reg_to_field[] = {
 923         [REG_NON] = MLX5_MODI_OUT_NONE,
 924         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 925         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 926         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 927         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 928         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 929         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 930         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 931         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 932         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 933         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 934 };
 935
 936 /**
 937  * Convert register set to DV specification.
 938  *
 939  * @param[in,out] resource
 940  *   Pointer to the modify-header resource.
 941  * @param[in] action
 942  *   Pointer to action specification.
 943  * @param[out] error
 944  *   Pointer to the error structure.
 945  *
 946  * @return
 947  *   0 on success, a negative errno value otherwise and rte_errno is set.
 948  */
 949 static int
 950 flow_dv_convert_action_set_reg
 951                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 952                          const struct rte_flow_action *action,
 953                          struct rte_flow_error *error)
 954 {
 955         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 956         struct mlx5_modification_cmd *actions = resource->actions;
 957         uint32_t i = resource->actions_num;
 958
 959         if (i >= MLX5_MAX_MODIFY_NUM)
 960                 return rte_flow_error_set(error, EINVAL,
 961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 962                                           "too many items to modify");
 963         MLX5_ASSERT(conf->id != REG_NON);
 964         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 965         actions[i] = (struct mlx5_modification_cmd) {
 966                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 967                 .field = reg_to_field[conf->id],
 968                 .offset = conf->offset,
 969                 .length = conf->length,
 970         };
 971         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 972         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 973         ++i;
 974         resource->actions_num = i;
 975         return 0;
 976 }
 977
 978 /**
 979  * Convert SET_TAG action to DV specification.
 980  *
 981  * @param[in] dev
 982  *   Pointer to the rte_eth_dev structure.
 983  * @param[in,out] resource
 984  *   Pointer to the modify-header resource.
 985  * @param[in] conf
 986  *   Pointer to action specification.
 987  * @param[out] error
 988  *   Pointer to the error structure.
 989  *
 990  * @return
 991  *   0 on success, a negative errno value otherwise and rte_errno is set.
 992  */
 993 static int
 994 flow_dv_convert_action_set_tag
 995                         (struct rte_eth_dev *dev,
 996                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 997                          const struct rte_flow_action_set_tag *conf,
 998                          struct rte_flow_error *error)
 999 {
1000         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1001         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1002         struct rte_flow_item item = {
1003                 .spec = &data,
1004                 .mask = &mask,
1005         };
1006         struct field_modify_info reg_c_x[] = {
1007                 [1] = {0, 0, 0},
1008         };
1009         enum mlx5_modification_field reg_type;
1010         int ret;
1011
1012         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1013         if (ret < 0)
1014                 return ret;
1015         MLX5_ASSERT(ret != REG_NON);
1016         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1017         reg_type = reg_to_field[ret];
1018         MLX5_ASSERT(reg_type > 0);
1019         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1020         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1021                                              MLX5_MODIFICATION_TYPE_SET, error);
1022 }
1023
1024 /**
1025  * Convert internal COPY_REG action to DV specification.
1026  *
1027  * @param[in] dev
1028  *   Pointer to the rte_eth_dev structure.
1029  * @param[in,out] res
1030  *   Pointer to the modify-header resource.
1031  * @param[in] action
1032  *   Pointer to action specification.
1033  * @param[out] error
1034  *   Pointer to the error structure.
1035  *
1036  * @return
1037  *   0 on success, a negative errno value otherwise and rte_errno is set.
1038  */
1039 static int
1040 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1041                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1042                                  const struct rte_flow_action *action,
1043                                  struct rte_flow_error *error)
1044 {
1045         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1046         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1047         struct rte_flow_item item = {
1048                 .spec = NULL,
1049                 .mask = &mask,
1050         };
1051         struct field_modify_info reg_src[] = {
1052                 {4, 0, reg_to_field[conf->src]},
1053                 {0, 0, 0},
1054         };
1055         struct field_modify_info reg_dst = {
1056                 .offset = 0,
1057                 .id = reg_to_field[conf->dst],
1058         };
1059         /* Adjust reg_c[0] usage according to reported mask. */
1060         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1061                 struct mlx5_priv *priv = dev->data->dev_private;
1062                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1063
1064                 MLX5_ASSERT(reg_c0);
1065                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1066                 if (conf->dst == REG_C_0) {
1067                         /* Copy to reg_c[0], within mask only. */
1068                         reg_dst.offset = rte_bsf32(reg_c0);
1069                         /*
1070                          * Mask is ignoring the enianness, because
1071                          * there is no conversion in datapath.
1072                          */
1073 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1074                         /* Copy from destination lower bits to reg_c[0]. */
1075                         mask = reg_c0 >> reg_dst.offset;
1076 #else
1077                         /* Copy from destination upper bits to reg_c[0]. */
1078                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1079                                           rte_fls_u32(reg_c0));
1080 #endif
1081                 } else {
1082                         mask = rte_cpu_to_be_32(reg_c0);
1083 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1084                         /* Copy from reg_c[0] to destination lower bits. */
1085                         reg_dst.offset = 0;
1086 #else
1087                         /* Copy from reg_c[0] to destination upper bits. */
1088                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1089                                          (rte_fls_u32(reg_c0) -
1090                                           rte_bsf32(reg_c0));
1091 #endif
1092                 }
1093         }
1094         return flow_dv_convert_modify_action(&item,
1095                                              reg_src, &reg_dst, res,
1096                                              MLX5_MODIFICATION_TYPE_COPY,
1097                                              error);
1098 }
1099
1100 /**
1101  * Convert MARK action to DV specification. This routine is used
1102  * in extensive metadata only and requires metadata register to be
1103  * handled. In legacy mode hardware tag resource is engaged.
1104  *
1105  * @param[in] dev
1106  *   Pointer to the rte_eth_dev structure.
1107  * @param[in] conf
1108  *   Pointer to MARK action specification.
1109  * @param[in,out] resource
1110  *   Pointer to the modify-header resource.
1111  * @param[out] error
1112  *   Pointer to the error structure.
1113  *
1114  * @return
1115  *   0 on success, a negative errno value otherwise and rte_errno is set.
1116  */
1117 static int
1118 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1119                             const struct rte_flow_action_mark *conf,
1120                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1121                             struct rte_flow_error *error)
1122 {
1123         struct mlx5_priv *priv = dev->data->dev_private;
1124         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1125                                            priv->sh->dv_mark_mask);
1126         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1127         struct rte_flow_item item = {
1128                 .spec = &data,
1129                 .mask = &mask,
1130         };
1131         struct field_modify_info reg_c_x[] = {
1132                 [1] = {0, 0, 0},
1133         };
1134         int reg;
1135
1136         if (!mask)
1137                 return rte_flow_error_set(error, EINVAL,
1138                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1139                                           NULL, "zero mark action mask");
1140         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1141         if (reg < 0)
1142                 return reg;
1143         MLX5_ASSERT(reg > 0);
1144         if (reg == REG_C_0) {
1145                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1146                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1147
1148                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1149                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1150                 mask = rte_cpu_to_be_32(mask << shl_c0);
1151         }
1152         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1153         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1154                                              MLX5_MODIFICATION_TYPE_SET, error);
1155 }
1156
1157 /**
1158  * Get metadata register index for specified steering domain.
1159  *
1160  * @param[in] dev
1161  *   Pointer to the rte_eth_dev structure.
1162  * @param[in] attr
1163  *   Attributes of flow to determine steering domain.
1164  * @param[out] error
1165  *   Pointer to the error structure.
1166  *
1167  * @return
1168  *   positive index on success, a negative errno value otherwise
1169  *   and rte_errno is set.
1170  */
1171 static enum modify_reg
1172 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1173                          const struct rte_flow_attr *attr,
1174                          struct rte_flow_error *error)
1175 {
1176         int reg =
1177                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1178                                           MLX5_METADATA_FDB :
1179                                             attr->egress ?
1180                                             MLX5_METADATA_TX :
1181                                             MLX5_METADATA_RX, 0, error);
1182         if (reg < 0)
1183                 return rte_flow_error_set(error,
1184                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1185                                           NULL, "unavailable "
1186                                           "metadata register");
1187         return reg;
1188 }
1189
1190 /**
1191  * Convert SET_META action to DV specification.
1192  *
1193  * @param[in] dev
1194  *   Pointer to the rte_eth_dev structure.
1195  * @param[in,out] resource
1196  *   Pointer to the modify-header resource.
1197  * @param[in] attr
1198  *   Attributes of flow that includes this item.
1199  * @param[in] conf
1200  *   Pointer to action specification.
1201  * @param[out] error
1202  *   Pointer to the error structure.
1203  *
1204  * @return
1205  *   0 on success, a negative errno value otherwise and rte_errno is set.
1206  */
1207 static int
1208 flow_dv_convert_action_set_meta
1209                         (struct rte_eth_dev *dev,
1210                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1211                          const struct rte_flow_attr *attr,
1212                          const struct rte_flow_action_set_meta *conf,
1213                          struct rte_flow_error *error)
1214 {
1215         uint32_t data = conf->data;
1216         uint32_t mask = conf->mask;
1217         struct rte_flow_item item = {
1218                 .spec = &data,
1219                 .mask = &mask,
1220         };
1221         struct field_modify_info reg_c_x[] = {
1222                 [1] = {0, 0, 0},
1223         };
1224         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1225
1226         if (reg < 0)
1227                 return reg;
1228         MLX5_ASSERT(reg != REG_NON);
1229         /*
1230          * In datapath code there is no endianness
1231          * coversions for perfromance reasons, all
1232          * pattern conversions are done in rte_flow.
1233          */
1234         if (reg == REG_C_0) {
1235                 struct mlx5_priv *priv = dev->data->dev_private;
1236                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1237                 uint32_t shl_c0;
1238
1239                 MLX5_ASSERT(msk_c0);
1240 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1241                 shl_c0 = rte_bsf32(msk_c0);
1242 #else
1243                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1244 #endif
1245                 mask <<= shl_c0;
1246                 data <<= shl_c0;
1247                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1248         }
1249         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1250         /* The routine expects parameters in memory as big-endian ones. */
1251         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1252                                              MLX5_MODIFICATION_TYPE_SET, error);
1253 }
1254
1255 /**
1256  * Convert modify-header set IPv4 DSCP action to DV specification.
1257  *
1258  * @param[in,out] resource
1259  *   Pointer to the modify-header resource.
1260  * @param[in] action
1261  *   Pointer to action specification.
1262  * @param[out] error
1263  *   Pointer to the error structure.
1264  *
1265  * @return
1266  *   0 on success, a negative errno value otherwise and rte_errno is set.
1267  */
1268 static int
1269 flow_dv_convert_action_modify_ipv4_dscp
1270                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1271                          const struct rte_flow_action *action,
1272                          struct rte_flow_error *error)
1273 {
1274         const struct rte_flow_action_set_dscp *conf =
1275                 (const struct rte_flow_action_set_dscp *)(action->conf);
1276         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1277         struct rte_flow_item_ipv4 ipv4;
1278         struct rte_flow_item_ipv4 ipv4_mask;
1279
1280         memset(&ipv4, 0, sizeof(ipv4));
1281         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1282         ipv4.hdr.type_of_service = conf->dscp;
1283         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1284         item.spec = &ipv4;
1285         item.mask = &ipv4_mask;
1286         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1287                                              MLX5_MODIFICATION_TYPE_SET, error);
1288 }
1289
1290 /**
1291  * Convert modify-header set IPv6 DSCP action to DV specification.
1292  *
1293  * @param[in,out] resource
1294  *   Pointer to the modify-header resource.
1295  * @param[in] action
1296  *   Pointer to action specification.
1297  * @param[out] error
1298  *   Pointer to the error structure.
1299  *
1300  * @return
1301  *   0 on success, a negative errno value otherwise and rte_errno is set.
1302  */
1303 static int
1304 flow_dv_convert_action_modify_ipv6_dscp
1305                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1306                          const struct rte_flow_action *action,
1307                          struct rte_flow_error *error)
1308 {
1309         const struct rte_flow_action_set_dscp *conf =
1310                 (const struct rte_flow_action_set_dscp *)(action->conf);
1311         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1312         struct rte_flow_item_ipv6 ipv6;
1313         struct rte_flow_item_ipv6 ipv6_mask;
1314
1315         memset(&ipv6, 0, sizeof(ipv6));
1316         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1317         /*
1318          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1319          * rdma-core only accept the DSCP bits byte aligned start from
1320          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1321          * bits in IPv6 case as rdma-core requires byte aligned value.
1322          */
1323         ipv6.hdr.vtc_flow = conf->dscp;
1324         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1325         item.spec = &ipv6;
1326         item.mask = &ipv6_mask;
1327         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1328                                              MLX5_MODIFICATION_TYPE_SET, error);
1329 }
1330
1331 static int
1332 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1333 {
1334         switch (field) {
1335         case RTE_FLOW_FIELD_START:
1336                 return 32;
1337         case RTE_FLOW_FIELD_MAC_DST:
1338         case RTE_FLOW_FIELD_MAC_SRC:
1339                 return 48;
1340         case RTE_FLOW_FIELD_VLAN_TYPE:
1341                 return 16;
1342         case RTE_FLOW_FIELD_VLAN_ID:
1343                 return 12;
1344         case RTE_FLOW_FIELD_MAC_TYPE:
1345                 return 16;
1346         case RTE_FLOW_FIELD_IPV4_DSCP:
1347                 return 6;
1348         case RTE_FLOW_FIELD_IPV4_TTL:
1349                 return 8;
1350         case RTE_FLOW_FIELD_IPV4_SRC:
1351         case RTE_FLOW_FIELD_IPV4_DST:
1352                 return 32;
1353         case RTE_FLOW_FIELD_IPV6_DSCP:
1354                 return 6;
1355         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1356                 return 8;
1357         case RTE_FLOW_FIELD_IPV6_SRC:
1358         case RTE_FLOW_FIELD_IPV6_DST:
1359                 return 128;
1360         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1361         case RTE_FLOW_FIELD_TCP_PORT_DST:
1362                 return 16;
1363         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1364         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1365                 return 32;
1366         case RTE_FLOW_FIELD_TCP_FLAGS:
1367                 return 6;
1368         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1369         case RTE_FLOW_FIELD_UDP_PORT_DST:
1370                 return 16;
1371         case RTE_FLOW_FIELD_VXLAN_VNI:
1372         case RTE_FLOW_FIELD_GENEVE_VNI:
1373                 return 24;
1374         case RTE_FLOW_FIELD_GTP_TEID:
1375         case RTE_FLOW_FIELD_TAG:
1376                 return 32;
1377         case RTE_FLOW_FIELD_MARK:
1378                 return 24;
1379         case RTE_FLOW_FIELD_META:
1380                 return 32;
1381         case RTE_FLOW_FIELD_POINTER:
1382         case RTE_FLOW_FIELD_VALUE:
1383                 return 64;
1384         default:
1385                 MLX5_ASSERT(false);
1386         }
1387         return 0;
1388 }
1389
1390 static void
1391 mlx5_flow_field_id_to_modify_info
1392                 (const struct rte_flow_action_modify_data *data,
1393                  struct field_modify_info *info,
1394                  uint32_t *mask, uint32_t *value,
1395                  uint32_t width, uint32_t dst_width,
1396                  struct rte_eth_dev *dev,
1397                  const struct rte_flow_attr *attr,
1398                  struct rte_flow_error *error)
1399 {
1400         uint32_t idx = 0;
1401         uint64_t val = 0;
1402         switch (data->field) {
1403         case RTE_FLOW_FIELD_START:
1404                 /* not supported yet */
1405                 MLX5_ASSERT(false);
1406                 break;
1407         case RTE_FLOW_FIELD_MAC_DST:
1408                 if (mask) {
1409                         if (data->offset < 32) {
1410                                 info[idx] = (struct field_modify_info){4, 0,
1411                                                 MLX5_MODI_OUT_DMAC_47_16};
1412                                 if (width < 32) {
1413                                         mask[idx] =
1414                                                 rte_cpu_to_be_32(0xffffffff >>
1415                                                                  (32 - width));
1416                                         width = 0;
1417                                 } else {
1418                                         mask[idx] = RTE_BE32(0xffffffff);
1419                                         width -= 32;
1420                                 }
1421                                 if (!width)
1422                                         break;
1423                                 ++idx;
1424                         }
1425                         info[idx] = (struct field_modify_info){2, 4 * idx,
1426                                                 MLX5_MODI_OUT_DMAC_15_0};
1427                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1428                 } else {
1429                         if (data->offset < 32)
1430                                 info[idx++] = (struct field_modify_info){4, 0,
1431                                                 MLX5_MODI_OUT_DMAC_47_16};
1432                         info[idx] = (struct field_modify_info){2, 0,
1433                                                 MLX5_MODI_OUT_DMAC_15_0};
1434                 }
1435                 break;
1436         case RTE_FLOW_FIELD_MAC_SRC:
1437                 if (mask) {
1438                         if (data->offset < 32) {
1439                                 info[idx] = (struct field_modify_info){4, 0,
1440                                                 MLX5_MODI_OUT_SMAC_47_16};
1441                                 if (width < 32) {
1442                                         mask[idx] =
1443                                                 rte_cpu_to_be_32(0xffffffff >>
1444                                                                 (32 - width));
1445                                         width = 0;
1446                                 } else {
1447                                         mask[idx] = RTE_BE32(0xffffffff);
1448                                         width -= 32;
1449                                 }
1450                                 if (!width)
1451                                         break;
1452                                 ++idx;
1453                         }
1454                         info[idx] = (struct field_modify_info){2, 4 * idx,
1455                                                 MLX5_MODI_OUT_SMAC_15_0};
1456                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1457                 } else {
1458                         if (data->offset < 32)
1459                                 info[idx++] = (struct field_modify_info){4, 0,
1460                                                 MLX5_MODI_OUT_SMAC_47_16};
1461                         info[idx] = (struct field_modify_info){2, 0,
1462                                                 MLX5_MODI_OUT_SMAC_15_0};
1463                 }
1464                 break;
1465         case RTE_FLOW_FIELD_VLAN_TYPE:
1466                 /* not supported yet */
1467                 break;
1468         case RTE_FLOW_FIELD_VLAN_ID:
1469                 info[idx] = (struct field_modify_info){2, 0,
1470                                         MLX5_MODI_OUT_FIRST_VID};
1471                 if (mask)
1472                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1473                 break;
1474         case RTE_FLOW_FIELD_MAC_TYPE:
1475                 info[idx] = (struct field_modify_info){2, 0,
1476                                         MLX5_MODI_OUT_ETHERTYPE};
1477                 if (mask)
1478                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1479                 break;
1480         case RTE_FLOW_FIELD_IPV4_DSCP:
1481                 info[idx] = (struct field_modify_info){1, 0,
1482                                         MLX5_MODI_OUT_IP_DSCP};
1483                 if (mask)
1484                         mask[idx] = 0x3f >> (6 - width);
1485                 break;
1486         case RTE_FLOW_FIELD_IPV4_TTL:
1487                 info[idx] = (struct field_modify_info){1, 0,
1488                                         MLX5_MODI_OUT_IPV4_TTL};
1489                 if (mask)
1490                         mask[idx] = 0xff >> (8 - width);
1491                 break;
1492         case RTE_FLOW_FIELD_IPV4_SRC:
1493                 info[idx] = (struct field_modify_info){4, 0,
1494                                         MLX5_MODI_OUT_SIPV4};
1495                 if (mask)
1496                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1497                                                      (32 - width));
1498                 break;
1499         case RTE_FLOW_FIELD_IPV4_DST:
1500                 info[idx] = (struct field_modify_info){4, 0,
1501                                         MLX5_MODI_OUT_DIPV4};
1502                 if (mask)
1503                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1504                                                      (32 - width));
1505                 break;
1506         case RTE_FLOW_FIELD_IPV6_DSCP:
1507                 info[idx] = (struct field_modify_info){1, 0,
1508                                         MLX5_MODI_OUT_IP_DSCP};
1509                 if (mask)
1510                         mask[idx] = 0x3f >> (6 - width);
1511                 break;
1512         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1513                 info[idx] = (struct field_modify_info){1, 0,
1514                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1515                 if (mask)
1516                         mask[idx] = 0xff >> (8 - width);
1517                 break;
1518         case RTE_FLOW_FIELD_IPV6_SRC:
1519                 if (mask) {
1520                         if (data->offset < 32) {
1521                                 info[idx] = (struct field_modify_info){4,
1522                                                 4 * idx,
1523                                                 MLX5_MODI_OUT_SIPV6_31_0};
1524                                 if (width < 32) {
1525                                         mask[idx] =
1526                                                 rte_cpu_to_be_32(0xffffffff >>
1527                                                                  (32 - width));
1528                                         width = 0;
1529                                 } else {
1530                                         mask[idx] = RTE_BE32(0xffffffff);
1531                                         width -= 32;
1532                                 }
1533                                 if (!width)
1534                                         break;
1535                                 ++idx;
1536                         }
1537                         if (data->offset < 64) {
1538                                 info[idx] = (struct field_modify_info){4,
1539                                                 4 * idx,
1540                                                 MLX5_MODI_OUT_SIPV6_63_32};
1541                                 if (width < 32) {
1542                                         mask[idx] =
1543                                                 rte_cpu_to_be_32(0xffffffff >>
1544                                                                  (32 - width));
1545                                         width = 0;
1546                                 } else {
1547                                         mask[idx] = RTE_BE32(0xffffffff);
1548                                         width -= 32;
1549                                 }
1550                                 if (!width)
1551                                         break;
1552                                 ++idx;
1553                         }
1554                         if (data->offset < 96) {
1555                                 info[idx] = (struct field_modify_info){4,
1556                                                 4 * idx,
1557                                                 MLX5_MODI_OUT_SIPV6_95_64};
1558                                 if (width < 32) {
1559                                         mask[idx] =
1560                                                 rte_cpu_to_be_32(0xffffffff >>
1561                                                                  (32 - width));
1562                                         width = 0;
1563                                 } else {
1564                                         mask[idx] = RTE_BE32(0xffffffff);
1565                                         width -= 32;
1566                                 }
1567                                 if (!width)
1568                                         break;
1569                                 ++idx;
1570                         }
1571                         info[idx] = (struct field_modify_info){4, 4 * idx,
1572                                                 MLX5_MODI_OUT_SIPV6_127_96};
1573                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574                                                      (32 - width));
1575                 } else {
1576                         if (data->offset < 32)
1577                                 info[idx++] = (struct field_modify_info){4, 0,
1578                                                 MLX5_MODI_OUT_SIPV6_31_0};
1579                         if (data->offset < 64)
1580                                 info[idx++] = (struct field_modify_info){4, 0,
1581                                                 MLX5_MODI_OUT_SIPV6_63_32};
1582                         if (data->offset < 96)
1583                                 info[idx++] = (struct field_modify_info){4, 0,
1584                                                 MLX5_MODI_OUT_SIPV6_95_64};
1585                         if (data->offset < 128)
1586                                 info[idx++] = (struct field_modify_info){4, 0,
1587                                                 MLX5_MODI_OUT_SIPV6_127_96};
1588                 }
1589                 break;
1590         case RTE_FLOW_FIELD_IPV6_DST:
1591                 if (mask) {
1592                         if (data->offset < 32) {
1593                                 info[idx] = (struct field_modify_info){4,
1594                                                 4 * idx,
1595                                                 MLX5_MODI_OUT_DIPV6_31_0};
1596                                 if (width < 32) {
1597                                         mask[idx] =
1598                                                 rte_cpu_to_be_32(0xffffffff >>
1599                                                                  (32 - width));
1600                                         width = 0;
1601                                 } else {
1602                                         mask[idx] = RTE_BE32(0xffffffff);
1603                                         width -= 32;
1604                                 }
1605                                 if (!width)
1606                                         break;
1607                                 ++idx;
1608                         }
1609                         if (data->offset < 64) {
1610                                 info[idx] = (struct field_modify_info){4,
1611                                                 4 * idx,
1612                                                 MLX5_MODI_OUT_DIPV6_63_32};
1613                                 if (width < 32) {
1614                                         mask[idx] =
1615                                                 rte_cpu_to_be_32(0xffffffff >>
1616                                                                  (32 - width));
1617                                         width = 0;
1618                                 } else {
1619                                         mask[idx] = RTE_BE32(0xffffffff);
1620                                         width -= 32;
1621                                 }
1622                                 if (!width)
1623                                         break;
1624                                 ++idx;
1625                         }
1626                         if (data->offset < 96) {
1627                                 info[idx] = (struct field_modify_info){4,
1628                                                 4 * idx,
1629                                                 MLX5_MODI_OUT_DIPV6_95_64};
1630                                 if (width < 32) {
1631                                         mask[idx] =
1632                                                 rte_cpu_to_be_32(0xffffffff >>
1633                                                                  (32 - width));
1634                                         width = 0;
1635                                 } else {
1636                                         mask[idx] = RTE_BE32(0xffffffff);
1637                                         width -= 32;
1638                                 }
1639                                 if (!width)
1640                                         break;
1641                                 ++idx;
1642                         }
1643                         info[idx] = (struct field_modify_info){4, 4 * idx,
1644                                                 MLX5_MODI_OUT_DIPV6_127_96};
1645                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1646                                                      (32 - width));
1647                 } else {
1648                         if (data->offset < 32)
1649                                 info[idx++] = (struct field_modify_info){4, 0,
1650                                                 MLX5_MODI_OUT_DIPV6_31_0};
1651                         if (data->offset < 64)
1652                                 info[idx++] = (struct field_modify_info){4, 0,
1653                                                 MLX5_MODI_OUT_DIPV6_63_32};
1654                         if (data->offset < 96)
1655                                 info[idx++] = (struct field_modify_info){4, 0,
1656                                                 MLX5_MODI_OUT_DIPV6_95_64};
1657                         if (data->offset < 128)
1658                                 info[idx++] = (struct field_modify_info){4, 0,
1659                                                 MLX5_MODI_OUT_DIPV6_127_96};
1660                 }
1661                 break;
1662         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1663                 info[idx] = (struct field_modify_info){2, 0,
1664                                         MLX5_MODI_OUT_TCP_SPORT};
1665                 if (mask)
1666                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1667                 break;
1668         case RTE_FLOW_FIELD_TCP_PORT_DST:
1669                 info[idx] = (struct field_modify_info){2, 0,
1670                                         MLX5_MODI_OUT_TCP_DPORT};
1671                 if (mask)
1672                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1673                 break;
1674         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1675                 info[idx] = (struct field_modify_info){4, 0,
1676                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1677                 if (mask)
1678                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1679                                                      (32 - width));
1680                 break;
1681         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1682                 info[idx] = (struct field_modify_info){4, 0,
1683                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1684                 if (mask)
1685                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1686                                                      (32 - width));
1687                 break;
1688         case RTE_FLOW_FIELD_TCP_FLAGS:
1689                 info[idx] = (struct field_modify_info){1, 0,
1690                                         MLX5_MODI_OUT_TCP_FLAGS};
1691                 if (mask)
1692                         mask[idx] = 0x3f >> (6 - width);
1693                 break;
1694         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1695                 info[idx] = (struct field_modify_info){2, 0,
1696                                         MLX5_MODI_OUT_UDP_SPORT};
1697                 if (mask)
1698                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1699                 break;
1700         case RTE_FLOW_FIELD_UDP_PORT_DST:
1701                 info[idx] = (struct field_modify_info){2, 0,
1702                                         MLX5_MODI_OUT_UDP_DPORT};
1703                 if (mask)
1704                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1705                 break;
1706         case RTE_FLOW_FIELD_VXLAN_VNI:
1707                 /* not supported yet */
1708                 break;
1709         case RTE_FLOW_FIELD_GENEVE_VNI:
1710                 /* not supported yet*/
1711                 break;
1712         case RTE_FLOW_FIELD_GTP_TEID:
1713                 info[idx] = (struct field_modify_info){4, 0,
1714                                         MLX5_MODI_GTP_TEID};
1715                 if (mask)
1716                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1717                                                      (32 - width));
1718                 break;
1719         case RTE_FLOW_FIELD_TAG:
1720                 {
1721                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1722                                                    data->level, error);
1723                         if (reg < 0)
1724                                 return;
1725                         MLX5_ASSERT(reg != REG_NON);
1726                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1727                         info[idx] = (struct field_modify_info){4, 0,
1728                                                 reg_to_field[reg]};
1729                         if (mask)
1730                                 mask[idx] =
1731                                         rte_cpu_to_be_32(0xffffffff >>
1732                                                          (32 - width));
1733                 }
1734                 break;
1735         case RTE_FLOW_FIELD_MARK:
1736                 {
1737                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1738                                                        0, error);
1739                         if (reg < 0)
1740                                 return;
1741                         MLX5_ASSERT(reg != REG_NON);
1742                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1743                         info[idx] = (struct field_modify_info){4, 0,
1744                                                 reg_to_field[reg]};
1745                         if (mask)
1746                                 mask[idx] =
1747                                         rte_cpu_to_be_32(0xffffffff >>
1748                                                          (32 - width));
1749                 }
1750                 break;
1751         case RTE_FLOW_FIELD_META:
1752                 {
1753                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1754                         if (reg < 0)
1755                                 return;
1756                         MLX5_ASSERT(reg != REG_NON);
1757                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1758                         info[idx] = (struct field_modify_info){4, 0,
1759                                                 reg_to_field[reg]};
1760                         if (mask)
1761                                 mask[idx] =
1762                                         rte_cpu_to_be_32(0xffffffff >>
1763                                                          (32 - width));
1764                 }
1765                 break;
1766         case RTE_FLOW_FIELD_POINTER:
1767         case RTE_FLOW_FIELD_VALUE:
1768                 if (data->field == RTE_FLOW_FIELD_POINTER)
1769                         memcpy(&val, (void *)(uintptr_t)data->value,
1770                                sizeof(uint64_t));
1771                 else
1772                         val = data->value;
1773                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1774                         if (mask[idx]) {
1775                                 if (dst_width > 16) {
1776                                         value[idx] = rte_cpu_to_be_32(val);
1777                                         val >>= 32;
1778                                 } else if (dst_width > 8) {
1779                                         value[idx] = rte_cpu_to_be_16(val);
1780                                         val >>= 16;
1781                                 } else {
1782                                         value[idx] = (uint8_t)val;
1783                                         val >>= 8;
1784                                 }
1785                                 if (!val)
1786                                         break;
1787                         }
1788                 }
1789                 break;
1790         default:
1791                 MLX5_ASSERT(false);
1792                 break;
1793         }
1794 }
1795
1796 /**
1797  * Convert modify_field action to DV specification.
1798  *
1799  * @param[in] dev
1800  *   Pointer to the rte_eth_dev structure.
1801  * @param[in,out] resource
1802  *   Pointer to the modify-header resource.
1803  * @param[in] action
1804  *   Pointer to action specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to the error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_convert_action_modify_field
1815                         (struct rte_eth_dev *dev,
1816                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1817                          const struct rte_flow_action *action,
1818                          const struct rte_flow_attr *attr,
1819                          struct rte_flow_error *error)
1820 {
1821         const struct rte_flow_action_modify_field *conf =
1822                 (const struct rte_flow_action_modify_field *)(action->conf);
1823         struct rte_flow_item item;
1824         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1825                                                                 {0, 0, 0} };
1826         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1827                                                                 {0, 0, 0} };
1828         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1829         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1830         uint32_t type;
1831         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1832
1833         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1834                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1835                 type = MLX5_MODIFICATION_TYPE_SET;
1836                 /** For SET fill the destination field (field) first. */
1837                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1838                         value, conf->width, dst_width, dev, attr, error);
1839                 /** Then copy immediate value from source as per mask. */
1840                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1841                         value, conf->width, dst_width, dev, attr, error);
1842                 item.spec = &value;
1843         } else {
1844                 type = MLX5_MODIFICATION_TYPE_COPY;
1845                 /** For COPY fill the destination field (dcopy) without mask. */
1846                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1847                         value, conf->width, dst_width, dev, attr, error);
1848                 /** Then construct the source field (field) with mask. */
1849                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1850                         value, conf->width, dst_width, dev, attr, error);
1851         }
1852         item.mask = &mask;
1853         return flow_dv_convert_modify_action(&item,
1854                         field, dcopy, resource, type, error);
1855 }
1856
1857 /**
1858  * Validate MARK item.
1859  *
1860  * @param[in] dev
1861  *   Pointer to the rte_eth_dev structure.
1862  * @param[in] item
1863  *   Item specification.
1864  * @param[in] attr
1865  *   Attributes of flow that includes this item.
1866  * @param[out] error
1867  *   Pointer to error structure.
1868  *
1869  * @return
1870  *   0 on success, a negative errno value otherwise and rte_errno is set.
1871  */
1872 static int
1873 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1874                            const struct rte_flow_item *item,
1875                            const struct rte_flow_attr *attr __rte_unused,
1876                            struct rte_flow_error *error)
1877 {
1878         struct mlx5_priv *priv = dev->data->dev_private;
1879         struct mlx5_dev_config *config = &priv->config;
1880         const struct rte_flow_item_mark *spec = item->spec;
1881         const struct rte_flow_item_mark *mask = item->mask;
1882         const struct rte_flow_item_mark nic_mask = {
1883                 .id = priv->sh->dv_mark_mask,
1884         };
1885         int ret;
1886
1887         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1888                 return rte_flow_error_set(error, ENOTSUP,
1889                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1890                                           "extended metadata feature"
1891                                           " isn't enabled");
1892         if (!mlx5_flow_ext_mreg_supported(dev))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1895                                           "extended metadata register"
1896                                           " isn't supported");
1897         if (!nic_mask.id)
1898                 return rte_flow_error_set(error, ENOTSUP,
1899                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1900                                           "extended metadata register"
1901                                           " isn't available");
1902         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1903         if (ret < 0)
1904                 return ret;
1905         if (!spec)
1906                 return rte_flow_error_set(error, EINVAL,
1907                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1908                                           item->spec,
1909                                           "data cannot be empty");
1910         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1911                 return rte_flow_error_set(error, EINVAL,
1912                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1913                                           &spec->id,
1914                                           "mark id exceeds the limit");
1915         if (!mask)
1916                 mask = &nic_mask;
1917         if (!mask->id)
1918                 return rte_flow_error_set(error, EINVAL,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1920                                         "mask cannot be zero");
1921
1922         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1923                                         (const uint8_t *)&nic_mask,
1924                                         sizeof(struct rte_flow_item_mark),
1925                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1926         if (ret < 0)
1927                 return ret;
1928         return 0;
1929 }
1930
1931 /**
1932  * Validate META item.
1933  *
1934  * @param[in] dev
1935  *   Pointer to the rte_eth_dev structure.
1936  * @param[in] item
1937  *   Item specification.
1938  * @param[in] attr
1939  *   Attributes of flow that includes this item.
1940  * @param[out] error
1941  *   Pointer to error structure.
1942  *
1943  * @return
1944  *   0 on success, a negative errno value otherwise and rte_errno is set.
1945  */
1946 static int
1947 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1948                            const struct rte_flow_item *item,
1949                            const struct rte_flow_attr *attr,
1950                            struct rte_flow_error *error)
1951 {
1952         struct mlx5_priv *priv = dev->data->dev_private;
1953         struct mlx5_dev_config *config = &priv->config;
1954         const struct rte_flow_item_meta *spec = item->spec;
1955         const struct rte_flow_item_meta *mask = item->mask;
1956         struct rte_flow_item_meta nic_mask = {
1957                 .data = UINT32_MAX
1958         };
1959         int reg;
1960         int ret;
1961
1962         if (!spec)
1963                 return rte_flow_error_set(error, EINVAL,
1964                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965                                           item->spec,
1966                                           "data cannot be empty");
1967         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1968                 if (!mlx5_flow_ext_mreg_supported(dev))
1969                         return rte_flow_error_set(error, ENOTSUP,
1970                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1971                                           "extended metadata register"
1972                                           " isn't supported");
1973                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1974                 if (reg < 0)
1975                         return reg;
1976                 if (reg == REG_NON)
1977                         return rte_flow_error_set(error, ENOTSUP,
1978                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1979                                         "unavalable extended metadata register");
1980                 if (reg == REG_B)
1981                         return rte_flow_error_set(error, ENOTSUP,
1982                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1983                                           "match on reg_b "
1984                                           "isn't supported");
1985                 if (reg != REG_A)
1986                         nic_mask.data = priv->sh->dv_meta_mask;
1987         } else {
1988                 if (attr->transfer)
1989                         return rte_flow_error_set(error, ENOTSUP,
1990                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1991                                         "extended metadata feature "
1992                                         "should be enabled when "
1993                                         "meta item is requested "
1994                                         "with e-switch mode ");
1995                 if (attr->ingress)
1996                         return rte_flow_error_set(error, ENOTSUP,
1997                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1998                                         "match on metadata for ingress "
1999                                         "is not supported in legacy "
2000                                         "metadata mode");
2001         }
2002         if (!mask)
2003                 mask = &rte_flow_item_meta_mask;
2004         if (!mask->data)
2005                 return rte_flow_error_set(error, EINVAL,
2006                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2007                                         "mask cannot be zero");
2008
2009         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2010                                         (const uint8_t *)&nic_mask,
2011                                         sizeof(struct rte_flow_item_meta),
2012                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2013         return ret;
2014 }
2015
2016 /**
2017  * Validate TAG item.
2018  *
2019  * @param[in] dev
2020  *   Pointer to the rte_eth_dev structure.
2021  * @param[in] item
2022  *   Item specification.
2023  * @param[in] attr
2024  *   Attributes of flow that includes this item.
2025  * @param[out] error
2026  *   Pointer to error structure.
2027  *
2028  * @return
2029  *   0 on success, a negative errno value otherwise and rte_errno is set.
2030  */
2031 static int
2032 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2033                           const struct rte_flow_item *item,
2034                           const struct rte_flow_attr *attr __rte_unused,
2035                           struct rte_flow_error *error)
2036 {
2037         const struct rte_flow_item_tag *spec = item->spec;
2038         const struct rte_flow_item_tag *mask = item->mask;
2039         const struct rte_flow_item_tag nic_mask = {
2040                 .data = RTE_BE32(UINT32_MAX),
2041                 .index = 0xff,
2042         };
2043         int ret;
2044
2045         if (!mlx5_flow_ext_mreg_supported(dev))
2046                 return rte_flow_error_set(error, ENOTSUP,
2047                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2048                                           "extensive metadata register"
2049                                           " isn't supported");
2050         if (!spec)
2051                 return rte_flow_error_set(error, EINVAL,
2052                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2053                                           item->spec,
2054                                           "data cannot be empty");
2055         if (!mask)
2056                 mask = &rte_flow_item_tag_mask;
2057         if (!mask->data)
2058                 return rte_flow_error_set(error, EINVAL,
2059                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2060                                         "mask cannot be zero");
2061
2062         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2063                                         (const uint8_t *)&nic_mask,
2064                                         sizeof(struct rte_flow_item_tag),
2065                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2066         if (ret < 0)
2067                 return ret;
2068         if (mask->index != 0xff)
2069                 return rte_flow_error_set(error, EINVAL,
2070                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2071                                           "partial mask for tag index"
2072                                           " is not supported");
2073         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2074         if (ret < 0)
2075                 return ret;
2076         MLX5_ASSERT(ret != REG_NON);
2077         return 0;
2078 }
2079
2080 /**
2081  * Validate vport item.
2082  *
2083  * @param[in] dev
2084  *   Pointer to the rte_eth_dev structure.
2085  * @param[in] item
2086  *   Item specification.
2087  * @param[in] attr
2088  *   Attributes of flow that includes this item.
2089  * @param[in] item_flags
2090  *   Bit-fields that holds the items detected until now.
2091  * @param[out] error
2092  *   Pointer to error structure.
2093  *
2094  * @return
2095  *   0 on success, a negative errno value otherwise and rte_errno is set.
2096  */
2097 static int
2098 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2099                               const struct rte_flow_item *item,
2100                               const struct rte_flow_attr *attr,
2101                               uint64_t item_flags,
2102                               struct rte_flow_error *error)
2103 {
2104         const struct rte_flow_item_port_id *spec = item->spec;
2105         const struct rte_flow_item_port_id *mask = item->mask;
2106         const struct rte_flow_item_port_id switch_mask = {
2107                         .id = 0xffffffff,
2108         };
2109         struct mlx5_priv *esw_priv;
2110         struct mlx5_priv *dev_priv;
2111         int ret;
2112
2113         if (!attr->transfer)
2114                 return rte_flow_error_set(error, EINVAL,
2115                                           RTE_FLOW_ERROR_TYPE_ITEM,
2116                                           NULL,
2117                                           "match on port id is valid only"
2118                                           " when transfer flag is enabled");
2119         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2120                 return rte_flow_error_set(error, ENOTSUP,
2121                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2122                                           "multiple source ports are not"
2123                                           " supported");
2124         if (!mask)
2125                 mask = &switch_mask;
2126         if (mask->id != 0xffffffff)
2127                 return rte_flow_error_set(error, ENOTSUP,
2128                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2129                                            mask,
2130                                            "no support for partial mask on"
2131                                            " \"id\" field");
2132         ret = mlx5_flow_item_acceptable
2133                                 (item, (const uint8_t *)mask,
2134                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2135                                  sizeof(struct rte_flow_item_port_id),
2136                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2137         if (ret)
2138                 return ret;
2139         if (!spec)
2140                 return 0;
2141         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2142         if (!esw_priv)
2143                 return rte_flow_error_set(error, rte_errno,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2145                                           "failed to obtain E-Switch info for"
2146                                           " port");
2147         dev_priv = mlx5_dev_to_eswitch_info(dev);
2148         if (!dev_priv)
2149                 return rte_flow_error_set(error, rte_errno,
2150                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2151                                           NULL,
2152                                           "failed to obtain E-Switch info");
2153         if (esw_priv->domain_id != dev_priv->domain_id)
2154                 return rte_flow_error_set(error, EINVAL,
2155                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2156                                           "cannot match on a port from a"
2157                                           " different E-Switch");
2158         return 0;
2159 }
2160
2161 /**
2162  * Validate VLAN item.
2163  *
2164  * @param[in] item
2165  *   Item specification.
2166  * @param[in] item_flags
2167  *   Bit-fields that holds the items detected until now.
2168  * @param[in] dev
2169  *   Ethernet device flow is being created on.
2170  * @param[out] error
2171  *   Pointer to error structure.
2172  *
2173  * @return
2174  *   0 on success, a negative errno value otherwise and rte_errno is set.
2175  */
2176 static int
2177 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2178                            uint64_t item_flags,
2179                            struct rte_eth_dev *dev,
2180                            struct rte_flow_error *error)
2181 {
2182         const struct rte_flow_item_vlan *mask = item->mask;
2183         const struct rte_flow_item_vlan nic_mask = {
2184                 .tci = RTE_BE16(UINT16_MAX),
2185                 .inner_type = RTE_BE16(UINT16_MAX),
2186                 .has_more_vlan = 1,
2187         };
2188         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2189         int ret;
2190         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2191                                         MLX5_FLOW_LAYER_INNER_L4) :
2192                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2193                                         MLX5_FLOW_LAYER_OUTER_L4);
2194         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2195                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2196
2197         if (item_flags & vlanm)
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2200                                           "multiple VLAN layers not supported");
2201         else if ((item_flags & l34m) != 0)
2202                 return rte_flow_error_set(error, EINVAL,
2203                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2204                                           "VLAN cannot follow L3/L4 layer");
2205         if (!mask)
2206                 mask = &rte_flow_item_vlan_mask;
2207         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2208                                         (const uint8_t *)&nic_mask,
2209                                         sizeof(struct rte_flow_item_vlan),
2210                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2211         if (ret)
2212                 return ret;
2213         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2214                 struct mlx5_priv *priv = dev->data->dev_private;
2215
2216                 if (priv->vmwa_context) {
2217                         /*
2218                          * Non-NULL context means we have a virtual machine
2219                          * and SR-IOV enabled, we have to create VLAN interface
2220                          * to make hypervisor to setup E-Switch vport
2221                          * context correctly. We avoid creating the multiple
2222                          * VLAN interfaces, so we cannot support VLAN tag mask.
2223                          */
2224                         return rte_flow_error_set(error, EINVAL,
2225                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2226                                                   item,
2227                                                   "VLAN tag mask is not"
2228                                                   " supported in virtual"
2229                                                   " environment");
2230                 }
2231         }
2232         return 0;
2233 }
2234
2235 /*
2236  * GTP flags are contained in 1 byte of the format:
2237  * -------------------------------------------
2238  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2239  * |-----------------------------------------|
2240  * | value | Version | PT | Res | E | S | PN |
2241  * -------------------------------------------
2242  *
2243  * Matching is supported only for GTP flags E, S, PN.
2244  */
2245 #define MLX5_GTP_FLAGS_MASK     0x07
2246
2247 /**
2248  * Validate GTP item.
2249  *
2250  * @param[in] dev
2251  *   Pointer to the rte_eth_dev structure.
2252  * @param[in] item
2253  *   Item specification.
2254  * @param[in] item_flags
2255  *   Bit-fields that holds the items detected until now.
2256  * @param[out] error
2257  *   Pointer to error structure.
2258  *
2259  * @return
2260  *   0 on success, a negative errno value otherwise and rte_errno is set.
2261  */
2262 static int
2263 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2264                           const struct rte_flow_item *item,
2265                           uint64_t item_flags,
2266                           struct rte_flow_error *error)
2267 {
2268         struct mlx5_priv *priv = dev->data->dev_private;
2269         const struct rte_flow_item_gtp *spec = item->spec;
2270         const struct rte_flow_item_gtp *mask = item->mask;
2271         const struct rte_flow_item_gtp nic_mask = {
2272                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2273                 .msg_type = 0xff,
2274                 .teid = RTE_BE32(0xffffffff),
2275         };
2276
2277         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2278                 return rte_flow_error_set(error, ENOTSUP,
2279                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                                           "GTP support is not enabled");
2281         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2282                 return rte_flow_error_set(error, ENOTSUP,
2283                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2284                                           "multiple tunnel layers not"
2285                                           " supported");
2286         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2287                 return rte_flow_error_set(error, EINVAL,
2288                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                                           "no outer UDP layer found");
2290         if (!mask)
2291                 mask = &rte_flow_item_gtp_mask;
2292         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2293                 return rte_flow_error_set(error, ENOTSUP,
2294                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2295                                           "Match is supported for GTP"
2296                                           " flags only");
2297         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2298                                          (const uint8_t *)&nic_mask,
2299                                          sizeof(struct rte_flow_item_gtp),
2300                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2301 }
2302
2303 /**
2304  * Validate GTP PSC item.
2305  *
2306  * @param[in] item
2307  *   Item specification.
2308  * @param[in] last_item
2309  *   Previous validated item in the pattern items.
2310  * @param[in] gtp_item
2311  *   Previous GTP item specification.
2312  * @param[in] attr
2313  *   Pointer to flow attributes.
2314  * @param[out] error
2315  *   Pointer to error structure.
2316  *
2317  * @return
2318  *   0 on success, a negative errno value otherwise and rte_errno is set.
2319  */
2320 static int
2321 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2322                               uint64_t last_item,
2323                               const struct rte_flow_item *gtp_item,
2324                               const struct rte_flow_attr *attr,
2325                               struct rte_flow_error *error)
2326 {
2327         const struct rte_flow_item_gtp *gtp_spec;
2328         const struct rte_flow_item_gtp *gtp_mask;
2329         const struct rte_flow_item_gtp_psc *spec;
2330         const struct rte_flow_item_gtp_psc *mask;
2331         const struct rte_flow_item_gtp_psc nic_mask = {
2332                 .pdu_type = 0xFF,
2333                 .qfi = 0xFF,
2334         };
2335
2336         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2337                 return rte_flow_error_set
2338                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2339                          "GTP PSC item must be preceded with GTP item");
2340         gtp_spec = gtp_item->spec;
2341         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2342         /* GTP spec and E flag is requested to match zero. */
2343         if (gtp_spec &&
2344                 (gtp_mask->v_pt_rsv_flags &
2345                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2346                 return rte_flow_error_set
2347                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2348                          "GTP E flag must be 1 to match GTP PSC");
2349         /* Check the flow is not created in group zero. */
2350         if (!attr->transfer && !attr->group)
2351                 return rte_flow_error_set
2352                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2353                          "GTP PSC is not supported for group 0");
2354         /* GTP spec is here and E flag is requested to match zero. */
2355         if (!item->spec)
2356                 return 0;
2357         spec = item->spec;
2358         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2359         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2360                 return rte_flow_error_set
2361                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2362                          "PDU type should be smaller than 16");
2363         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2364                                          (const uint8_t *)&nic_mask,
2365                                          sizeof(struct rte_flow_item_gtp_psc),
2366                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2367 }
2368
2369 /**
2370  * Validate IPV4 item.
2371  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2372  * add specific validation of fragment_offset field,
2373  *
2374  * @param[in] item
2375  *   Item specification.
2376  * @param[in] item_flags
2377  *   Bit-fields that holds the items detected until now.
2378  * @param[out] error
2379  *   Pointer to error structure.
2380  *
2381  * @return
2382  *   0 on success, a negative errno value otherwise and rte_errno is set.
2383  */
2384 static int
2385 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2386                            uint64_t item_flags,
2387                            uint64_t last_item,
2388                            uint16_t ether_type,
2389                            struct rte_flow_error *error)
2390 {
2391         int ret;
2392         const struct rte_flow_item_ipv4 *spec = item->spec;
2393         const struct rte_flow_item_ipv4 *last = item->last;
2394         const struct rte_flow_item_ipv4 *mask = item->mask;
2395         rte_be16_t fragment_offset_spec = 0;
2396         rte_be16_t fragment_offset_last = 0;
2397         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2398                 .hdr = {
2399                         .src_addr = RTE_BE32(0xffffffff),
2400                         .dst_addr = RTE_BE32(0xffffffff),
2401                         .type_of_service = 0xff,
2402                         .fragment_offset = RTE_BE16(0xffff),
2403                         .next_proto_id = 0xff,
2404                         .time_to_live = 0xff,
2405                 },
2406         };
2407
2408         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2409                                            ether_type, &nic_ipv4_mask,
2410                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2411         if (ret < 0)
2412                 return ret;
2413         if (spec && mask)
2414                 fragment_offset_spec = spec->hdr.fragment_offset &
2415                                        mask->hdr.fragment_offset;
2416         if (!fragment_offset_spec)
2417                 return 0;
2418         /*
2419          * spec and mask are valid, enforce using full mask to make sure the
2420          * complete value is used correctly.
2421          */
2422         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2423                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2424                 return rte_flow_error_set(error, EINVAL,
2425                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2426                                           item, "must use full mask for"
2427                                           " fragment_offset");
2428         /*
2429          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2430          * indicating this is 1st fragment of fragmented packet.
2431          * This is not yet supported in MLX5, return appropriate error message.
2432          */
2433         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2434                 return rte_flow_error_set(error, ENOTSUP,
2435                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2436                                           "match on first fragment not "
2437                                           "supported");
2438         if (fragment_offset_spec && !last)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2441                                           "specified value not supported");
2442         /* spec and last are valid, validate the specified range. */
2443         fragment_offset_last = last->hdr.fragment_offset &
2444                                mask->hdr.fragment_offset;
2445         /*
2446          * Match on fragment_offset spec 0x2001 and last 0x3fff
2447          * means MF is 1 and frag-offset is > 0.
2448          * This packet is fragment 2nd and onward, excluding last.
2449          * This is not yet supported in MLX5, return appropriate
2450          * error message.
2451          */
2452         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2453             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2454                 return rte_flow_error_set(error, ENOTSUP,
2455                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2456                                           last, "match on following "
2457                                           "fragments not supported");
2458         /*
2459          * Match on fragment_offset spec 0x0001 and last 0x1fff
2460          * means MF is 0 and frag-offset is > 0.
2461          * This packet is last fragment of fragmented packet.
2462          * This is not yet supported in MLX5, return appropriate
2463          * error message.
2464          */
2465         if (fragment_offset_spec == RTE_BE16(1) &&
2466             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2467                 return rte_flow_error_set(error, ENOTSUP,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2469                                           last, "match on last "
2470                                           "fragment not supported");
2471         /*
2472          * Match on fragment_offset spec 0x0001 and last 0x3fff
2473          * means MF and/or frag-offset is not 0.
2474          * This is a fragmented packet.
2475          * Other range values are invalid and rejected.
2476          */
2477         if (!(fragment_offset_spec == RTE_BE16(1) &&
2478               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2481                                           "specified range not supported");
2482         return 0;
2483 }
2484
2485 /**
2486  * Validate IPV6 fragment extension item.
2487  *
2488  * @param[in] item
2489  *   Item specification.
2490  * @param[in] item_flags
2491  *   Bit-fields that holds the items detected until now.
2492  * @param[out] error
2493  *   Pointer to error structure.
2494  *
2495  * @return
2496  *   0 on success, a negative errno value otherwise and rte_errno is set.
2497  */
2498 static int
2499 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2500                                     uint64_t item_flags,
2501                                     struct rte_flow_error *error)
2502 {
2503         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2504         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2505         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2506         rte_be16_t frag_data_spec = 0;
2507         rte_be16_t frag_data_last = 0;
2508         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2509         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2510                                       MLX5_FLOW_LAYER_OUTER_L4;
2511         int ret = 0;
2512         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2513                 .hdr = {
2514                         .next_header = 0xff,
2515                         .frag_data = RTE_BE16(0xffff),
2516                 },
2517         };
2518
2519         if (item_flags & l4m)
2520                 return rte_flow_error_set(error, EINVAL,
2521                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2522                                           "ipv6 fragment extension item cannot "
2523                                           "follow L4 item.");
2524         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2525             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2526                 return rte_flow_error_set(error, EINVAL,
2527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2528                                           "ipv6 fragment extension item must "
2529                                           "follow ipv6 item");
2530         if (spec && mask)
2531                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2532         if (!frag_data_spec)
2533                 return 0;
2534         /*
2535          * spec and mask are valid, enforce using full mask to make sure the
2536          * complete value is used correctly.
2537          */
2538         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2539                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2540                 return rte_flow_error_set(error, EINVAL,
2541                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2542                                           item, "must use full mask for"
2543                                           " frag_data");
2544         /*
2545          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2546          * This is 1st fragment of fragmented packet.
2547          */
2548         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2549                 return rte_flow_error_set(error, ENOTSUP,
2550                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2551                                           "match on first fragment not "
2552                                           "supported");
2553         if (frag_data_spec && !last)
2554                 return rte_flow_error_set(error, EINVAL,
2555                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2556                                           "specified value not supported");
2557         ret = mlx5_flow_item_acceptable
2558                                 (item, (const uint8_t *)mask,
2559                                  (const uint8_t *)&nic_mask,
2560                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2561                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2562         if (ret)
2563                 return ret;
2564         /* spec and last are valid, validate the specified range. */
2565         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2566         /*
2567          * Match on frag_data spec 0x0009 and last 0xfff9
2568          * means M is 1 and frag-offset is > 0.
2569          * This packet is fragment 2nd and onward, excluding last.
2570          * This is not yet supported in MLX5, return appropriate
2571          * error message.
2572          */
2573         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2574                                        RTE_IPV6_EHDR_MF_MASK) &&
2575             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2576                 return rte_flow_error_set(error, ENOTSUP,
2577                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2578                                           last, "match on following "
2579                                           "fragments not supported");
2580         /*
2581          * Match on frag_data spec 0x0008 and last 0xfff8
2582          * means M is 0 and frag-offset is > 0.
2583          * This packet is last fragment of fragmented packet.
2584          * This is not yet supported in MLX5, return appropriate
2585          * error message.
2586          */
2587         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2588             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2589                 return rte_flow_error_set(error, ENOTSUP,
2590                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2591                                           last, "match on last "
2592                                           "fragment not supported");
2593         /* Other range values are invalid and rejected. */
2594         return rte_flow_error_set(error, EINVAL,
2595                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2596                                   "specified range not supported");
2597 }
2598
2599 /**
2600  * Validate the pop VLAN action.
2601  *
2602  * @param[in] dev
2603  *   Pointer to the rte_eth_dev structure.
2604  * @param[in] action_flags
2605  *   Holds the actions detected until now.
2606  * @param[in] action
2607  *   Pointer to the pop vlan action.
2608  * @param[in] item_flags
2609  *   The items found in this flow rule.
2610  * @param[in] attr
2611  *   Pointer to flow attributes.
2612  * @param[out] error
2613  *   Pointer to error structure.
2614  *
2615  * @return
2616  *   0 on success, a negative errno value otherwise and rte_errno is set.
2617  */
2618 static int
2619 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2620                                  uint64_t action_flags,
2621                                  const struct rte_flow_action *action,
2622                                  uint64_t item_flags,
2623                                  const struct rte_flow_attr *attr,
2624                                  struct rte_flow_error *error)
2625 {
2626         const struct mlx5_priv *priv = dev->data->dev_private;
2627
2628         (void)action;
2629         (void)attr;
2630         if (!priv->sh->pop_vlan_action)
2631                 return rte_flow_error_set(error, ENOTSUP,
2632                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2633                                           NULL,
2634                                           "pop vlan action is not supported");
2635         if (attr->egress)
2636                 return rte_flow_error_set(error, ENOTSUP,
2637                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2638                                           NULL,
2639                                           "pop vlan action not supported for "
2640                                           "egress");
2641         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2642                 return rte_flow_error_set(error, ENOTSUP,
2643                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2644                                           "no support for multiple VLAN "
2645                                           "actions");
2646         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2647         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2648             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2649                 return rte_flow_error_set(error, ENOTSUP,
2650                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2651                                           NULL,
2652                                           "cannot pop vlan after decap without "
2653                                           "match on inner vlan in the flow");
2654         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2655         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2656             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2657                 return rte_flow_error_set(error, ENOTSUP,
2658                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2659                                           NULL,
2660                                           "cannot pop vlan without a "
2661                                           "match on (outer) vlan in the flow");
2662         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2663                 return rte_flow_error_set(error, EINVAL,
2664                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2665                                           "wrong action order, port_id should "
2666                                           "be after pop VLAN action");
2667         if (!attr->transfer && priv->representor)
2668                 return rte_flow_error_set(error, ENOTSUP,
2669                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2670                                           "pop vlan action for VF representor "
2671                                           "not supported on NIC table");
2672         return 0;
2673 }
2674
2675 /**
2676  * Get VLAN default info from vlan match info.
2677  *
2678  * @param[in] items
2679  *   the list of item specifications.
2680  * @param[out] vlan
2681  *   pointer VLAN info to fill to.
2682  *
2683  * @return
2684  *   0 on success, a negative errno value otherwise and rte_errno is set.
2685  */
2686 static void
2687 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2688                                   struct rte_vlan_hdr *vlan)
2689 {
2690         const struct rte_flow_item_vlan nic_mask = {
2691                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2692                                 MLX5DV_FLOW_VLAN_VID_MASK),
2693                 .inner_type = RTE_BE16(0xffff),
2694         };
2695
2696         if (items == NULL)
2697                 return;
2698         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2699                 int type = items->type;
2700
2701                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2702                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2703                         break;
2704         }
2705         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2706                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2707                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2708
2709                 /* If VLAN item in pattern doesn't contain data, return here. */
2710                 if (!vlan_v)
2711                         return;
2712                 if (!vlan_m)
2713                         vlan_m = &nic_mask;
2714                 /* Only full match values are accepted */
2715                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2716                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2717                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2718                         vlan->vlan_tci |=
2719                                 rte_be_to_cpu_16(vlan_v->tci &
2720                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2721                 }
2722                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2723                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2724                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2725                         vlan->vlan_tci |=
2726                                 rte_be_to_cpu_16(vlan_v->tci &
2727                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2728                 }
2729                 if (vlan_m->inner_type == nic_mask.inner_type)
2730                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2731                                                            vlan_m->inner_type);
2732         }
2733 }
2734
2735 /**
2736  * Validate the push VLAN action.
2737  *
2738  * @param[in] dev
2739  *   Pointer to the rte_eth_dev structure.
2740  * @param[in] action_flags
2741  *   Holds the actions detected until now.
2742  * @param[in] item_flags
2743  *   The items found in this flow rule.
2744  * @param[in] action
2745  *   Pointer to the action structure.
2746  * @param[in] attr
2747  *   Pointer to flow attributes
2748  * @param[out] error
2749  *   Pointer to error structure.
2750  *
2751  * @return
2752  *   0 on success, a negative errno value otherwise and rte_errno is set.
2753  */
2754 static int
2755 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2756                                   uint64_t action_flags,
2757                                   const struct rte_flow_item_vlan *vlan_m,
2758                                   const struct rte_flow_action *action,
2759                                   const struct rte_flow_attr *attr,
2760                                   struct rte_flow_error *error)
2761 {
2762         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2763         const struct mlx5_priv *priv = dev->data->dev_private;
2764
2765         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2766             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2767                 return rte_flow_error_set(error, EINVAL,
2768                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2769                                           "invalid vlan ethertype");
2770         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2771                 return rte_flow_error_set(error, EINVAL,
2772                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2773                                           "wrong action order, port_id should "
2774                                           "be after push VLAN");
2775         if (!attr->transfer && priv->representor)
2776                 return rte_flow_error_set(error, ENOTSUP,
2777                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2778                                           "push vlan action for VF representor "
2779                                           "not supported on NIC table");
2780         if (vlan_m &&
2781             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2782             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2783                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2784             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2785             !(mlx5_flow_find_action
2786                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "not full match mask on VLAN PCP and "
2790                                           "there is no of_set_vlan_pcp action, "
2791                                           "push VLAN action cannot figure out "
2792                                           "PCP value");
2793         if (vlan_m &&
2794             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2795             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2796                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2797             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2798             !(mlx5_flow_find_action
2799                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2800                 return rte_flow_error_set(error, EINVAL,
2801                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2802                                           "not full match mask on VLAN VID and "
2803                                           "there is no of_set_vlan_vid action, "
2804                                           "push VLAN action cannot figure out "
2805                                           "VID value");
2806         (void)attr;
2807         return 0;
2808 }
2809
2810 /**
2811  * Validate the set VLAN PCP.
2812  *
2813  * @param[in] action_flags
2814  *   Holds the actions detected until now.
2815  * @param[in] actions
2816  *   Pointer to the list of actions remaining in the flow rule.
2817  * @param[out] error
2818  *   Pointer to error structure.
2819  *
2820  * @return
2821  *   0 on success, a negative errno value otherwise and rte_errno is set.
2822  */
2823 static int
2824 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2825                                      const struct rte_flow_action actions[],
2826                                      struct rte_flow_error *error)
2827 {
2828         const struct rte_flow_action *action = actions;
2829         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2830
2831         if (conf->vlan_pcp > 7)
2832                 return rte_flow_error_set(error, EINVAL,
2833                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2834                                           "VLAN PCP value is too big");
2835         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2836                 return rte_flow_error_set(error, ENOTSUP,
2837                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2838                                           "set VLAN PCP action must follow "
2839                                           "the push VLAN action");
2840         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2841                 return rte_flow_error_set(error, ENOTSUP,
2842                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2843                                           "Multiple VLAN PCP modification are "
2844                                           "not supported");
2845         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2846                 return rte_flow_error_set(error, EINVAL,
2847                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2848                                           "wrong action order, port_id should "
2849                                           "be after set VLAN PCP");
2850         return 0;
2851 }
2852
2853 /**
2854  * Validate the set VLAN VID.
2855  *
2856  * @param[in] item_flags
2857  *   Holds the items detected in this rule.
2858  * @param[in] action_flags
2859  *   Holds the actions detected until now.
2860  * @param[in] actions
2861  *   Pointer to the list of actions remaining in the flow rule.
2862  * @param[out] error
2863  *   Pointer to error structure.
2864  *
2865  * @return
2866  *   0 on success, a negative errno value otherwise and rte_errno is set.
2867  */
2868 static int
2869 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2870                                      uint64_t action_flags,
2871                                      const struct rte_flow_action actions[],
2872                                      struct rte_flow_error *error)
2873 {
2874         const struct rte_flow_action *action = actions;
2875         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2876
2877         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2878                 return rte_flow_error_set(error, EINVAL,
2879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2880                                           "VLAN VID value is too big");
2881         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2882             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2883                 return rte_flow_error_set(error, ENOTSUP,
2884                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2885                                           "set VLAN VID action must follow push"
2886                                           " VLAN action or match on VLAN item");
2887         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2888                 return rte_flow_error_set(error, ENOTSUP,
2889                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2890                                           "Multiple VLAN VID modifications are "
2891                                           "not supported");
2892         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2893                 return rte_flow_error_set(error, EINVAL,
2894                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2895                                           "wrong action order, port_id should "
2896                                           "be after set VLAN VID");
2897         return 0;
2898 }
2899
2900 /*
2901  * Validate the FLAG action.
2902  *
2903  * @param[in] dev
2904  *   Pointer to the rte_eth_dev structure.
2905  * @param[in] action_flags
2906  *   Holds the actions detected until now.
2907  * @param[in] attr
2908  *   Pointer to flow attributes
2909  * @param[out] error
2910  *   Pointer to error structure.
2911  *
2912  * @return
2913  *   0 on success, a negative errno value otherwise and rte_errno is set.
2914  */
2915 static int
2916 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         int ret;
2924
2925         /* Fall back if no extended metadata register support. */
2926         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2927                 return mlx5_flow_validate_action_flag(action_flags, attr,
2928                                                       error);
2929         /* Extensive metadata mode requires registers. */
2930         if (!mlx5_flow_ext_mreg_supported(dev))
2931                 return rte_flow_error_set(error, ENOTSUP,
2932                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2933                                           "no metadata registers "
2934                                           "to support flag action");
2935         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2936                 return rte_flow_error_set(error, ENOTSUP,
2937                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2938                                           "extended metadata register"
2939                                           " isn't available");
2940         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2941         if (ret < 0)
2942                 return ret;
2943         MLX5_ASSERT(ret > 0);
2944         if (action_flags & MLX5_FLOW_ACTION_MARK)
2945                 return rte_flow_error_set(error, EINVAL,
2946                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2947                                           "can't mark and flag in same flow");
2948         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2949                 return rte_flow_error_set(error, EINVAL,
2950                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2951                                           "can't have 2 flag"
2952                                           " actions in same flow");
2953         return 0;
2954 }
2955
2956 /**
2957  * Validate MARK action.
2958  *
2959  * @param[in] dev
2960  *   Pointer to the rte_eth_dev structure.
2961  * @param[in] action
2962  *   Pointer to action.
2963  * @param[in] action_flags
2964  *   Holds the actions detected until now.
2965  * @param[in] attr
2966  *   Pointer to flow attributes
2967  * @param[out] error
2968  *   Pointer to error structure.
2969  *
2970  * @return
2971  *   0 on success, a negative errno value otherwise and rte_errno is set.
2972  */
2973 static int
2974 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2975                              const struct rte_flow_action *action,
2976                              uint64_t action_flags,
2977                              const struct rte_flow_attr *attr,
2978                              struct rte_flow_error *error)
2979 {
2980         struct mlx5_priv *priv = dev->data->dev_private;
2981         struct mlx5_dev_config *config = &priv->config;
2982         const struct rte_flow_action_mark *mark = action->conf;
2983         int ret;
2984
2985         if (is_tunnel_offload_active(dev))
2986                 return rte_flow_error_set(error, ENOTSUP,
2987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2988                                           "no mark action "
2989                                           "if tunnel offload active");
2990         /* Fall back if no extended metadata register support. */
2991         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2992                 return mlx5_flow_validate_action_mark(action, action_flags,
2993                                                       attr, error);
2994         /* Extensive metadata mode requires registers. */
2995         if (!mlx5_flow_ext_mreg_supported(dev))
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2998                                           "no metadata registers "
2999                                           "to support mark action");
3000         if (!priv->sh->dv_mark_mask)
3001                 return rte_flow_error_set(error, ENOTSUP,
3002                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3003                                           "extended metadata register"
3004                                           " isn't available");
3005         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3006         if (ret < 0)
3007                 return ret;
3008         MLX5_ASSERT(ret > 0);
3009         if (!mark)
3010                 return rte_flow_error_set(error, EINVAL,
3011                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3012                                           "configuration cannot be null");
3013         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3014                 return rte_flow_error_set(error, EINVAL,
3015                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3016                                           &mark->id,
3017                                           "mark id exceeds the limit");
3018         if (action_flags & MLX5_FLOW_ACTION_FLAG)
3019                 return rte_flow_error_set(error, EINVAL,
3020                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3021                                           "can't flag and mark in same flow");
3022         if (action_flags & MLX5_FLOW_ACTION_MARK)
3023                 return rte_flow_error_set(error, EINVAL,
3024                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3025                                           "can't have 2 mark actions in same"
3026                                           " flow");
3027         return 0;
3028 }
3029
3030 /**
3031  * Validate SET_META action.
3032  *
3033  * @param[in] dev
3034  *   Pointer to the rte_eth_dev structure.
3035  * @param[in] action
3036  *   Pointer to the action structure.
3037  * @param[in] action_flags
3038  *   Holds the actions detected until now.
3039  * @param[in] attr
3040  *   Pointer to flow attributes
3041  * @param[out] error
3042  *   Pointer to error structure.
3043  *
3044  * @return
3045  *   0 on success, a negative errno value otherwise and rte_errno is set.
3046  */
3047 static int
3048 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3049                                  const struct rte_flow_action *action,
3050                                  uint64_t action_flags __rte_unused,
3051                                  const struct rte_flow_attr *attr,
3052                                  struct rte_flow_error *error)
3053 {
3054         const struct rte_flow_action_set_meta *conf;
3055         uint32_t nic_mask = UINT32_MAX;
3056         int reg;
3057
3058         if (!mlx5_flow_ext_mreg_supported(dev))
3059                 return rte_flow_error_set(error, ENOTSUP,
3060                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3061                                           "extended metadata register"
3062                                           " isn't supported");
3063         reg = flow_dv_get_metadata_reg(dev, attr, error);
3064         if (reg < 0)
3065                 return reg;
3066         if (reg == REG_NON)
3067                 return rte_flow_error_set(error, ENOTSUP,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3069                                           "unavalable extended metadata register");
3070         if (reg != REG_A && reg != REG_B) {
3071                 struct mlx5_priv *priv = dev->data->dev_private;
3072
3073                 nic_mask = priv->sh->dv_meta_mask;
3074         }
3075         if (!(action->conf))
3076                 return rte_flow_error_set(error, EINVAL,
3077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3078                                           "configuration cannot be null");
3079         conf = (const struct rte_flow_action_set_meta *)action->conf;
3080         if (!conf->mask)
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "zero mask doesn't have any effect");
3084         if (conf->mask & ~nic_mask)
3085                 return rte_flow_error_set(error, EINVAL,
3086                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3087                                           "meta data must be within reg C0");
3088         return 0;
3089 }
3090
3091 /**
3092  * Validate SET_TAG action.
3093  *
3094  * @param[in] dev
3095  *   Pointer to the rte_eth_dev structure.
3096  * @param[in] action
3097  *   Pointer to the action structure.
3098  * @param[in] action_flags
3099  *   Holds the actions detected until now.
3100  * @param[in] attr
3101  *   Pointer to flow attributes
3102  * @param[out] error
3103  *   Pointer to error structure.
3104  *
3105  * @return
3106  *   0 on success, a negative errno value otherwise and rte_errno is set.
3107  */
3108 static int
3109 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3110                                 const struct rte_flow_action *action,
3111                                 uint64_t action_flags,
3112                                 const struct rte_flow_attr *attr,
3113                                 struct rte_flow_error *error)
3114 {
3115         const struct rte_flow_action_set_tag *conf;
3116         const uint64_t terminal_action_flags =
3117                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3118                 MLX5_FLOW_ACTION_RSS;
3119         int ret;
3120
3121         if (!mlx5_flow_ext_mreg_supported(dev))
3122                 return rte_flow_error_set(error, ENOTSUP,
3123                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3124                                           "extensive metadata register"
3125                                           " isn't supported");
3126         if (!(action->conf))
3127                 return rte_flow_error_set(error, EINVAL,
3128                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3129                                           "configuration cannot be null");
3130         conf = (const struct rte_flow_action_set_tag *)action->conf;
3131         if (!conf->mask)
3132                 return rte_flow_error_set(error, EINVAL,
3133                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3134                                           "zero mask doesn't have any effect");
3135         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3136         if (ret < 0)
3137                 return ret;
3138         if (!attr->transfer && attr->ingress &&
3139             (action_flags & terminal_action_flags))
3140                 return rte_flow_error_set(error, EINVAL,
3141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3142                                           "set_tag has no effect"
3143                                           " with terminal actions");
3144         return 0;
3145 }
3146
3147 /**
3148  * Validate count action.
3149  *
3150  * @param[in] dev
3151  *   Pointer to rte_eth_dev structure.
3152  * @param[in] action
3153  *   Pointer to the action structure.
3154  * @param[in] action_flags
3155  *   Holds the actions detected until now.
3156  * @param[out] error
3157  *   Pointer to error structure.
3158  *
3159  * @return
3160  *   0 on success, a negative errno value otherwise and rte_errno is set.
3161  */
3162 static int
3163 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3164                               const struct rte_flow_action *action,
3165                               uint64_t action_flags,
3166                               struct rte_flow_error *error)
3167 {
3168         struct mlx5_priv *priv = dev->data->dev_private;
3169         const struct rte_flow_action_count *count;
3170
3171         if (!priv->config.devx)
3172                 goto notsup_err;
3173         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3174                 return rte_flow_error_set(error, EINVAL,
3175                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3176                                           "duplicate count actions set");
3177         count = (const struct rte_flow_action_count *)action->conf;
3178         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3179             !priv->sh->flow_hit_aso_en)
3180                 return rte_flow_error_set(error, EINVAL,
3181                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3182                                           "old age and shared count combination is not supported");
3183 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3184         return 0;
3185 #endif
3186 notsup_err:
3187         return rte_flow_error_set
3188                       (error, ENOTSUP,
3189                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3190                        NULL,
3191                        "count action not supported");
3192 }
3193
3194 /**
3195  * Validate the L2 encap action.
3196  *
3197  * @param[in] dev
3198  *   Pointer to the rte_eth_dev structure.
3199  * @param[in] action_flags
3200  *   Holds the actions detected until now.
3201  * @param[in] action
3202  *   Pointer to the action structure.
3203  * @param[in] attr
3204  *   Pointer to flow attributes.
3205  * @param[out] error
3206  *   Pointer to error structure.
3207  *
3208  * @return
3209  *   0 on success, a negative errno value otherwise and rte_errno is set.
3210  */
3211 static int
3212 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3213                                  uint64_t action_flags,
3214                                  const struct rte_flow_action *action,
3215                                  const struct rte_flow_attr *attr,
3216                                  struct rte_flow_error *error)
3217 {
3218         const struct mlx5_priv *priv = dev->data->dev_private;
3219
3220         if (!(action->conf))
3221                 return rte_flow_error_set(error, EINVAL,
3222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3223                                           "configuration cannot be null");
3224         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3225                 return rte_flow_error_set(error, EINVAL,
3226                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3227                                           "can only have a single encap action "
3228                                           "in a flow");
3229         if (!attr->transfer && priv->representor)
3230                 return rte_flow_error_set(error, ENOTSUP,
3231                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3232                                           "encap action for VF representor "
3233                                           "not supported on NIC table");
3234         return 0;
3235 }
3236
3237 /**
3238  * Validate a decap action.
3239  *
3240  * @param[in] dev
3241  *   Pointer to the rte_eth_dev structure.
3242  * @param[in] action_flags
3243  *   Holds the actions detected until now.
3244  * @param[in] action
3245  *   Pointer to the action structure.
3246  * @param[in] item_flags
3247  *   Holds the items detected.
3248  * @param[in] attr
3249  *   Pointer to flow attributes
3250  * @param[out] error
3251  *   Pointer to error structure.
3252  *
3253  * @return
3254  *   0 on success, a negative errno value otherwise and rte_errno is set.
3255  */
3256 static int
3257 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3258                               uint64_t action_flags,
3259                               const struct rte_flow_action *action,
3260                               const uint64_t item_flags,
3261                               const struct rte_flow_attr *attr,
3262                               struct rte_flow_error *error)
3263 {
3264         const struct mlx5_priv *priv = dev->data->dev_private;
3265
3266         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3267             !priv->config.decap_en)
3268                 return rte_flow_error_set(error, ENOTSUP,
3269                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3270                                           "decap is not enabled");
3271         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3272                 return rte_flow_error_set(error, ENOTSUP,
3273                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3274                                           action_flags &
3275                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3276                                           "have a single decap action" : "decap "
3277                                           "after encap is not supported");
3278         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3279                 return rte_flow_error_set(error, EINVAL,
3280                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3281                                           "can't have decap action after"
3282                                           " modify action");
3283         if (attr->egress)
3284                 return rte_flow_error_set(error, ENOTSUP,
3285                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3286                                           NULL,
3287                                           "decap action not supported for "
3288                                           "egress");
3289         if (!attr->transfer && priv->representor)
3290                 return rte_flow_error_set(error, ENOTSUP,
3291                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3292                                           "decap action for VF representor "
3293                                           "not supported on NIC table");
3294         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3295             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3296                 return rte_flow_error_set(error, ENOTSUP,
3297                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3298                                 "VXLAN item should be present for VXLAN decap");
3299         return 0;
3300 }
3301
3302 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3303
3304 /**
3305  * Validate the raw encap and decap actions.
3306  *
3307  * @param[in] dev
3308  *   Pointer to the rte_eth_dev structure.
3309  * @param[in] decap
3310  *   Pointer to the decap action.
3311  * @param[in] encap
3312  *   Pointer to the encap action.
3313  * @param[in] attr
3314  *   Pointer to flow attributes
3315  * @param[in/out] action_flags
3316  *   Holds the actions detected until now.
3317  * @param[out] actions_n
3318  *   pointer to the number of actions counter.
3319  * @param[in] action
3320  *   Pointer to the action structure.
3321  * @param[in] item_flags
3322  *   Holds the items detected.
3323  * @param[out] error
3324  *   Pointer to error structure.
3325  *
3326  * @return
3327  *   0 on success, a negative errno value otherwise and rte_errno is set.
3328  */
3329 static int
3330 flow_dv_validate_action_raw_encap_decap
3331         (struct rte_eth_dev *dev,
3332          const struct rte_flow_action_raw_decap *decap,
3333          const struct rte_flow_action_raw_encap *encap,
3334          const struct rte_flow_attr *attr, uint64_t *action_flags,
3335          int *actions_n, const struct rte_flow_action *action,
3336          uint64_t item_flags, struct rte_flow_error *error)
3337 {
3338         const struct mlx5_priv *priv = dev->data->dev_private;
3339         int ret;
3340
3341         if (encap && (!encap->size || !encap->data))
3342                 return rte_flow_error_set(error, EINVAL,
3343                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3344                                           "raw encap data cannot be empty");
3345         if (decap && encap) {
3346                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3347                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3348                         /* L3 encap. */
3349                         decap = NULL;
3350                 else if (encap->size <=
3351                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3352                            decap->size >
3353                            MLX5_ENCAPSULATION_DECISION_SIZE)
3354                         /* L3 decap. */
3355                         encap = NULL;
3356                 else if (encap->size >
3357                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3358                            decap->size >
3359                            MLX5_ENCAPSULATION_DECISION_SIZE)
3360                         /* 2 L2 actions: encap and decap. */
3361                         ;
3362                 else
3363                         return rte_flow_error_set(error,
3364                                 ENOTSUP,
3365                                 RTE_FLOW_ERROR_TYPE_ACTION,
3366                                 NULL, "unsupported too small "
3367                                 "raw decap and too small raw "
3368                                 "encap combination");
3369         }
3370         if (decap) {
3371                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3372                                                     item_flags, attr, error);
3373                 if (ret < 0)
3374                         return ret;
3375                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3376                 ++(*actions_n);
3377         }
3378         if (encap) {
3379                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3380                         return rte_flow_error_set(error, ENOTSUP,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "small raw encap size");
3384                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3385                         return rte_flow_error_set(error, EINVAL,
3386                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3387                                                   NULL,
3388                                                   "more than one encap action");
3389                 if (!attr->transfer && priv->representor)
3390                         return rte_flow_error_set
3391                                         (error, ENOTSUP,
3392                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3393                                          "encap action for VF representor "
3394                                          "not supported on NIC table");
3395                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3396                 ++(*actions_n);
3397         }
3398         return 0;
3399 }
3400
3401 /**
3402  * Match encap_decap resource.
3403  *
3404  * @param list
3405  *   Pointer to the hash list.
3406  * @param entry
3407  *   Pointer to exist resource entry object.
3408  * @param key
3409  *   Key of the new entry.
3410  * @param ctx_cb
3411  *   Pointer to new encap_decap resource.
3412  *
3413  * @return
3414  *   0 on matching, none-zero otherwise.
3415  */
3416 int
3417 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3418                              struct mlx5_hlist_entry *entry,
3419                              uint64_t key __rte_unused, void *cb_ctx)
3420 {
3421         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3422         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3423         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3424
3425         cache_resource = container_of(entry,
3426                                       struct mlx5_flow_dv_encap_decap_resource,
3427                                       entry);
3428         if (resource->reformat_type == cache_resource->reformat_type &&
3429             resource->ft_type == cache_resource->ft_type &&
3430             resource->flags == cache_resource->flags &&
3431             resource->size == cache_resource->size &&
3432             !memcmp((const void *)resource->buf,
3433                     (const void *)cache_resource->buf,
3434                     resource->size))
3435                 return 0;
3436         return -1;
3437 }
3438
3439 /**
3440  * Allocate encap_decap resource.
3441  *
3442  * @param list
3443  *   Pointer to the hash list.
3444  * @param entry
3445  *   Pointer to exist resource entry object.
3446  * @param ctx_cb
3447  *   Pointer to new encap_decap resource.
3448  *
3449  * @return
3450  *   0 on matching, none-zero otherwise.
3451  */
3452 struct mlx5_hlist_entry *
3453 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3454                               uint64_t key __rte_unused,
3455                               void *cb_ctx)
3456 {
3457         struct mlx5_dev_ctx_shared *sh = list->ctx;
3458         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3459         struct mlx5dv_dr_domain *domain;
3460         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3461         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3462         uint32_t idx;
3463         int ret;
3464
3465         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3466                 domain = sh->fdb_domain;
3467         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3468                 domain = sh->rx_domain;
3469         else
3470                 domain = sh->tx_domain;
3471         /* Register new encap/decap resource. */
3472         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3473                                        &idx);
3474         if (!cache_resource) {
3475                 rte_flow_error_set(ctx->error, ENOMEM,
3476                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3477                                    "cannot allocate resource memory");
3478                 return NULL;
3479         }
3480         *cache_resource = *resource;
3481         cache_resource->idx = idx;
3482         ret = mlx5_flow_os_create_flow_action_packet_reformat
3483                                         (sh->ctx, domain, cache_resource,
3484                                          &cache_resource->action);
3485         if (ret) {
3486                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3487                 rte_flow_error_set(ctx->error, ENOMEM,
3488                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3489                                    NULL, "cannot create action");
3490                 return NULL;
3491         }
3492
3493         return &cache_resource->entry;
3494 }
3495
3496 /**
3497  * Find existing encap/decap resource or create and register a new one.
3498  *
3499  * @param[in, out] dev
3500  *   Pointer to rte_eth_dev structure.
3501  * @param[in, out] resource
3502  *   Pointer to encap/decap resource.
3503  * @parm[in, out] dev_flow
3504  *   Pointer to the dev_flow.
3505  * @param[out] error
3506  *   pointer to error structure.
3507  *
3508  * @return
3509  *   0 on success otherwise -errno and errno is set.
3510  */
3511 static int
3512 flow_dv_encap_decap_resource_register
3513                         (struct rte_eth_dev *dev,
3514                          struct mlx5_flow_dv_encap_decap_resource *resource,
3515                          struct mlx5_flow *dev_flow,
3516                          struct rte_flow_error *error)
3517 {
3518         struct mlx5_priv *priv = dev->data->dev_private;
3519         struct mlx5_dev_ctx_shared *sh = priv->sh;
3520         struct mlx5_hlist_entry *entry;
3521         union {
3522                 struct {
3523                         uint32_t ft_type:8;
3524                         uint32_t refmt_type:8;
3525                         /*
3526                          * Header reformat actions can be shared between
3527                          * non-root tables. One bit to indicate non-root
3528                          * table or not.
3529                          */
3530                         uint32_t is_root:1;
3531                         uint32_t reserve:15;
3532                 };
3533                 uint32_t v32;
3534         } encap_decap_key = {
3535                 {
3536                         .ft_type = resource->ft_type,
3537                         .refmt_type = resource->reformat_type,
3538                         .is_root = !!dev_flow->dv.group,
3539                         .reserve = 0,
3540                 }
3541         };
3542         struct mlx5_flow_cb_ctx ctx = {
3543                 .error = error,
3544                 .data = resource,
3545         };
3546         uint64_t key64;
3547
3548         resource->flags = dev_flow->dv.group ? 0 : 1;
3549         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3550                                  sizeof(encap_decap_key.v32), 0);
3551         if (resource->reformat_type !=
3552             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3553             resource->size)
3554                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3555         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3556         if (!entry)
3557                 return -rte_errno;
3558         resource = container_of(entry, typeof(*resource), entry);
3559         dev_flow->dv.encap_decap = resource;
3560         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3561         return 0;
3562 }
3563
3564 /**
3565  * Find existing table jump resource or create and register a new one.
3566  *
3567  * @param[in, out] dev
3568  *   Pointer to rte_eth_dev structure.
3569  * @param[in, out] tbl
3570  *   Pointer to flow table resource.
3571  * @parm[in, out] dev_flow
3572  *   Pointer to the dev_flow.
3573  * @param[out] error
3574  *   pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success otherwise -errno and errno is set.
3578  */
3579 static int
3580 flow_dv_jump_tbl_resource_register
3581                         (struct rte_eth_dev *dev __rte_unused,
3582                          struct mlx5_flow_tbl_resource *tbl,
3583                          struct mlx5_flow *dev_flow,
3584                          struct rte_flow_error *error __rte_unused)
3585 {
3586         struct mlx5_flow_tbl_data_entry *tbl_data =
3587                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3588
3589         MLX5_ASSERT(tbl);
3590         MLX5_ASSERT(tbl_data->jump.action);
3591         dev_flow->handle->rix_jump = tbl_data->idx;
3592         dev_flow->dv.jump = &tbl_data->jump;
3593         return 0;
3594 }
3595
3596 int
3597 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3598                          struct mlx5_cache_entry *entry, void *cb_ctx)
3599 {
3600         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3601         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3602         struct mlx5_flow_dv_port_id_action_resource *res =
3603                         container_of(entry, typeof(*res), entry);
3604
3605         return ref->port_id != res->port_id;
3606 }
3607
3608 struct mlx5_cache_entry *
3609 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3610                           struct mlx5_cache_entry *entry __rte_unused,
3611                           void *cb_ctx)
3612 {
3613         struct mlx5_dev_ctx_shared *sh = list->ctx;
3614         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3615         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3616         struct mlx5_flow_dv_port_id_action_resource *cache;
3617         uint32_t idx;
3618         int ret;
3619
3620         /* Register new port id action resource. */
3621         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3622         if (!cache) {
3623                 rte_flow_error_set(ctx->error, ENOMEM,
3624                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3625                                    "cannot allocate port_id action cache memory");
3626                 return NULL;
3627         }
3628         *cache = *ref;
3629         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3630                                                         ref->port_id,
3631                                                         &cache->action);
3632         if (ret) {
3633                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3634                 rte_flow_error_set(ctx->error, ENOMEM,
3635                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3636                                    "cannot create action");
3637                 return NULL;
3638         }
3639         cache->idx = idx;
3640         return &cache->entry;
3641 }
3642
3643 /**
3644  * Find existing table port ID resource or create and register a new one.
3645  *
3646  * @param[in, out] dev
3647  *   Pointer to rte_eth_dev structure.
3648  * @param[in, out] resource
3649  *   Pointer to port ID action resource.
3650  * @parm[in, out] dev_flow
3651  *   Pointer to the dev_flow.
3652  * @param[out] error
3653  *   pointer to error structure.
3654  *
3655  * @return
3656  *   0 on success otherwise -errno and errno is set.
3657  */
3658 static int
3659 flow_dv_port_id_action_resource_register
3660                         (struct rte_eth_dev *dev,
3661                          struct mlx5_flow_dv_port_id_action_resource *resource,
3662                          struct mlx5_flow *dev_flow,
3663                          struct rte_flow_error *error)
3664 {
3665         struct mlx5_priv *priv = dev->data->dev_private;
3666         struct mlx5_cache_entry *entry;
3667         struct mlx5_flow_dv_port_id_action_resource *cache;
3668         struct mlx5_flow_cb_ctx ctx = {
3669                 .error = error,
3670                 .data = resource,
3671         };
3672
3673         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3674         if (!entry)
3675                 return -rte_errno;
3676         cache = container_of(entry, typeof(*cache), entry);
3677         dev_flow->dv.port_id_action = cache;
3678         dev_flow->handle->rix_port_id_action = cache->idx;
3679         return 0;
3680 }
3681
3682 int
3683 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3684                          struct mlx5_cache_entry *entry, void *cb_ctx)
3685 {
3686         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3687         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3688         struct mlx5_flow_dv_push_vlan_action_resource *res =
3689                         container_of(entry, typeof(*res), entry);
3690
3691         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3692 }
3693
3694 struct mlx5_cache_entry *
3695 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3696                           struct mlx5_cache_entry *entry __rte_unused,
3697                           void *cb_ctx)
3698 {
3699         struct mlx5_dev_ctx_shared *sh = list->ctx;
3700         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3701         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3702         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3703         struct mlx5dv_dr_domain *domain;
3704         uint32_t idx;
3705         int ret;
3706
3707         /* Register new port id action resource. */
3708         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3709         if (!cache) {
3710                 rte_flow_error_set(ctx->error, ENOMEM,
3711                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3712                                    "cannot allocate push_vlan action cache memory");
3713                 return NULL;
3714         }
3715         *cache = *ref;
3716         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3717                 domain = sh->fdb_domain;
3718         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3719                 domain = sh->rx_domain;
3720         else
3721                 domain = sh->tx_domain;
3722         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3723                                                         &cache->action);
3724         if (ret) {
3725                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3726                 rte_flow_error_set(ctx->error, ENOMEM,
3727                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3728                                    "cannot create push vlan action");
3729                 return NULL;
3730         }
3731         cache->idx = idx;
3732         return &cache->entry;
3733 }
3734
3735 /**
3736  * Find existing push vlan resource or create and register a new one.
3737  *
3738  * @param [in, out] dev
3739  *   Pointer to rte_eth_dev structure.
3740  * @param[in, out] resource
3741  *   Pointer to port ID action resource.
3742  * @parm[in, out] dev_flow
3743  *   Pointer to the dev_flow.
3744  * @param[out] error
3745  *   pointer to error structure.
3746  *
3747  * @return
3748  *   0 on success otherwise -errno and errno is set.
3749  */
3750 static int
3751 flow_dv_push_vlan_action_resource_register
3752                        (struct rte_eth_dev *dev,
3753                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3754                         struct mlx5_flow *dev_flow,
3755                         struct rte_flow_error *error)
3756 {
3757         struct mlx5_priv *priv = dev->data->dev_private;
3758         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3759         struct mlx5_cache_entry *entry;
3760         struct mlx5_flow_cb_ctx ctx = {
3761                 .error = error,
3762                 .data = resource,
3763         };
3764
3765         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3766         if (!entry)
3767                 return -rte_errno;
3768         cache = container_of(entry, typeof(*cache), entry);
3769
3770         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3771         dev_flow->dv.push_vlan_res = cache;
3772         return 0;
3773 }
3774
3775 /**
3776  * Get the size of specific rte_flow_item_type hdr size
3777  *
3778  * @param[in] item_type
3779  *   Tested rte_flow_item_type.
3780  *
3781  * @return
3782  *   sizeof struct item_type, 0 if void or irrelevant.
3783  */
3784 static size_t
3785 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3786 {
3787         size_t retval;
3788
3789         switch (item_type) {
3790         case RTE_FLOW_ITEM_TYPE_ETH:
3791                 retval = sizeof(struct rte_ether_hdr);
3792                 break;
3793         case RTE_FLOW_ITEM_TYPE_VLAN:
3794                 retval = sizeof(struct rte_vlan_hdr);
3795                 break;
3796         case RTE_FLOW_ITEM_TYPE_IPV4:
3797                 retval = sizeof(struct rte_ipv4_hdr);
3798                 break;
3799         case RTE_FLOW_ITEM_TYPE_IPV6:
3800                 retval = sizeof(struct rte_ipv6_hdr);
3801                 break;
3802         case RTE_FLOW_ITEM_TYPE_UDP:
3803                 retval = sizeof(struct rte_udp_hdr);
3804                 break;
3805         case RTE_FLOW_ITEM_TYPE_TCP:
3806                 retval = sizeof(struct rte_tcp_hdr);
3807                 break;
3808         case RTE_FLOW_ITEM_TYPE_VXLAN:
3809         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3810                 retval = sizeof(struct rte_vxlan_hdr);
3811                 break;
3812         case RTE_FLOW_ITEM_TYPE_GRE:
3813         case RTE_FLOW_ITEM_TYPE_NVGRE:
3814                 retval = sizeof(struct rte_gre_hdr);
3815                 break;
3816         case RTE_FLOW_ITEM_TYPE_MPLS:
3817                 retval = sizeof(struct rte_mpls_hdr);
3818                 break;
3819         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3820         default:
3821                 retval = 0;
3822                 break;
3823         }
3824         return retval;
3825 }
3826
3827 #define MLX5_ENCAP_IPV4_VERSION         0x40
3828 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3829 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3830 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3831 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3832 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3833 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3834
3835 /**
3836  * Convert the encap action data from list of rte_flow_item to raw buffer
3837  *
3838  * @param[in] items
3839  *   Pointer to rte_flow_item objects list.
3840  * @param[out] buf
3841  *   Pointer to the output buffer.
3842  * @param[out] size
3843  *   Pointer to the output buffer size.
3844  * @param[out] error
3845  *   Pointer to the error structure.
3846  *
3847  * @return
3848  *   0 on success, a negative errno value otherwise and rte_errno is set.
3849  */
3850 static int
3851 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3852                            size_t *size, struct rte_flow_error *error)
3853 {
3854         struct rte_ether_hdr *eth = NULL;
3855         struct rte_vlan_hdr *vlan = NULL;
3856         struct rte_ipv4_hdr *ipv4 = NULL;
3857         struct rte_ipv6_hdr *ipv6 = NULL;
3858         struct rte_udp_hdr *udp = NULL;
3859         struct rte_vxlan_hdr *vxlan = NULL;
3860         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3861         struct rte_gre_hdr *gre = NULL;
3862         size_t len;
3863         size_t temp_size = 0;
3864
3865         if (!items)
3866                 return rte_flow_error_set(error, EINVAL,
3867                                           RTE_FLOW_ERROR_TYPE_ACTION,
3868                                           NULL, "invalid empty data");
3869         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3870                 len = flow_dv_get_item_hdr_len(items->type);
3871                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3872                         return rte_flow_error_set(error, EINVAL,
3873                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                   (void *)items->type,
3875                                                   "items total size is too big"
3876                                                   " for encap action");
3877                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3878                 switch (items->type) {
3879                 case RTE_FLOW_ITEM_TYPE_ETH:
3880                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3881                         break;
3882                 case RTE_FLOW_ITEM_TYPE_VLAN:
3883                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3884                         if (!eth)
3885                                 return rte_flow_error_set(error, EINVAL,
3886                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3887                                                 (void *)items->type,
3888                                                 "eth header not found");
3889                         if (!eth->ether_type)
3890                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3891                         break;
3892                 case RTE_FLOW_ITEM_TYPE_IPV4:
3893                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3894                         if (!vlan && !eth)
3895                                 return rte_flow_error_set(error, EINVAL,
3896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3897                                                 (void *)items->type,
3898                                                 "neither eth nor vlan"
3899                                                 " header found");
3900                         if (vlan && !vlan->eth_proto)
3901                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3902                         else if (eth && !eth->ether_type)
3903                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3904                         if (!ipv4->version_ihl)
3905                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3906                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3907                         if (!ipv4->time_to_live)
3908                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3909                         break;
3910                 case RTE_FLOW_ITEM_TYPE_IPV6:
3911                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3912                         if (!vlan && !eth)
3913                                 return rte_flow_error_set(error, EINVAL,
3914                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3915                                                 (void *)items->type,
3916                                                 "neither eth nor vlan"
3917                                                 " header found");
3918                         if (vlan && !vlan->eth_proto)
3919                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3920                         else if (eth && !eth->ether_type)
3921                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3922                         if (!ipv6->vtc_flow)
3923                                 ipv6->vtc_flow =
3924                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3925                         if (!ipv6->hop_limits)
3926                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3927                         break;
3928                 case RTE_FLOW_ITEM_TYPE_UDP:
3929                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3930                         if (!ipv4 && !ipv6)
3931                                 return rte_flow_error_set(error, EINVAL,
3932                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3933                                                 (void *)items->type,
3934                                                 "ip header not found");
3935                         if (ipv4 && !ipv4->next_proto_id)
3936                                 ipv4->next_proto_id = IPPROTO_UDP;
3937                         else if (ipv6 && !ipv6->proto)
3938                                 ipv6->proto = IPPROTO_UDP;
3939                         break;
3940                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3941                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3942                         if (!udp)
3943                                 return rte_flow_error_set(error, EINVAL,
3944                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3945                                                 (void *)items->type,
3946                                                 "udp header not found");
3947                         if (!udp->dst_port)
3948                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3949                         if (!vxlan->vx_flags)
3950                                 vxlan->vx_flags =
3951                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3952                         break;
3953                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3954                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3955                         if (!udp)
3956                                 return rte_flow_error_set(error, EINVAL,
3957                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3958                                                 (void *)items->type,
3959                                                 "udp header not found");
3960                         if (!vxlan_gpe->proto)
3961                                 return rte_flow_error_set(error, EINVAL,
3962                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3963                                                 (void *)items->type,
3964                                                 "next protocol not found");
3965                         if (!udp->dst_port)
3966                                 udp->dst_port =
3967                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3968                         if (!vxlan_gpe->vx_flags)
3969                                 vxlan_gpe->vx_flags =
3970                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3971                         break;
3972                 case RTE_FLOW_ITEM_TYPE_GRE:
3973                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3974                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3975                         if (!gre->proto)
3976                                 return rte_flow_error_set(error, EINVAL,
3977                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3978                                                 (void *)items->type,
3979                                                 "next protocol not found");
3980                         if (!ipv4 && !ipv6)
3981                                 return rte_flow_error_set(error, EINVAL,
3982                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3983                                                 (void *)items->type,
3984                                                 "ip header not found");
3985                         if (ipv4 && !ipv4->next_proto_id)
3986                                 ipv4->next_proto_id = IPPROTO_GRE;
3987                         else if (ipv6 && !ipv6->proto)
3988                                 ipv6->proto = IPPROTO_GRE;
3989                         break;
3990                 case RTE_FLOW_ITEM_TYPE_VOID:
3991                         break;
3992                 default:
3993                         return rte_flow_error_set(error, EINVAL,
3994                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3995                                                   (void *)items->type,
3996                                                   "unsupported item type");
3997                         break;
3998                 }
3999                 temp_size += len;
4000         }
4001         *size = temp_size;
4002         return 0;
4003 }
4004
4005 static int
4006 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4007 {
4008         struct rte_ether_hdr *eth = NULL;
4009         struct rte_vlan_hdr *vlan = NULL;
4010         struct rte_ipv6_hdr *ipv6 = NULL;
4011         struct rte_udp_hdr *udp = NULL;
4012         char *next_hdr;
4013         uint16_t proto;
4014
4015         eth = (struct rte_ether_hdr *)data;
4016         next_hdr = (char *)(eth + 1);
4017         proto = RTE_BE16(eth->ether_type);
4018
4019         /* VLAN skipping */
4020         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4021                 vlan = (struct rte_vlan_hdr *)next_hdr;
4022                 proto = RTE_BE16(vlan->eth_proto);
4023                 next_hdr += sizeof(struct rte_vlan_hdr);
4024         }
4025
4026         /* HW calculates IPv4 csum. no need to proceed */
4027         if (proto == RTE_ETHER_TYPE_IPV4)
4028                 return 0;
4029
4030         /* non IPv4/IPv6 header. not supported */
4031         if (proto != RTE_ETHER_TYPE_IPV6) {
4032                 return rte_flow_error_set(error, ENOTSUP,
4033                                           RTE_FLOW_ERROR_TYPE_ACTION,
4034                                           NULL, "Cannot offload non IPv4/IPv6");
4035         }
4036
4037         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4038
4039         /* ignore non UDP */
4040         if (ipv6->proto != IPPROTO_UDP)
4041                 return 0;
4042
4043         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4044         udp->dgram_cksum = 0;
4045
4046         return 0;
4047 }
4048
4049 /**
4050  * Convert L2 encap action to DV specification.
4051  *
4052  * @param[in] dev
4053  *   Pointer to rte_eth_dev structure.
4054  * @param[in] action
4055  *   Pointer to action structure.
4056  * @param[in, out] dev_flow
4057  *   Pointer to the mlx5_flow.
4058  * @param[in] transfer
4059  *   Mark if the flow is E-Switch flow.
4060  * @param[out] error
4061  *   Pointer to the error structure.
4062  *
4063  * @return
4064  *   0 on success, a negative errno value otherwise and rte_errno is set.
4065  */
4066 static int
4067 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4068                                const struct rte_flow_action *action,
4069                                struct mlx5_flow *dev_flow,
4070                                uint8_t transfer,
4071                                struct rte_flow_error *error)
4072 {
4073         const struct rte_flow_item *encap_data;
4074         const struct rte_flow_action_raw_encap *raw_encap_data;
4075         struct mlx5_flow_dv_encap_decap_resource res = {
4076                 .reformat_type =
4077                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4078                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4079                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4080         };
4081
4082         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4083                 raw_encap_data =
4084                         (const struct rte_flow_action_raw_encap *)action->conf;
4085                 res.size = raw_encap_data->size;
4086                 memcpy(res.buf, raw_encap_data->data, res.size);
4087         } else {
4088                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4089                         encap_data =
4090                                 ((const struct rte_flow_action_vxlan_encap *)
4091                                                 action->conf)->definition;
4092                 else
4093                         encap_data =
4094                                 ((const struct rte_flow_action_nvgre_encap *)
4095                                                 action->conf)->definition;
4096                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4097                                                &res.size, error))
4098                         return -rte_errno;
4099         }
4100         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4101                 return -rte_errno;
4102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4103                 return rte_flow_error_set(error, EINVAL,
4104                                           RTE_FLOW_ERROR_TYPE_ACTION,
4105                                           NULL, "can't create L2 encap action");
4106         return 0;
4107 }
4108
4109 /**
4110  * Convert L2 decap action to DV specification.
4111  *
4112  * @param[in] dev
4113  *   Pointer to rte_eth_dev structure.
4114  * @param[in, out] dev_flow
4115  *   Pointer to the mlx5_flow.
4116  * @param[in] transfer
4117  *   Mark if the flow is E-Switch flow.
4118  * @param[out] error
4119  *   Pointer to the error structure.
4120  *
4121  * @return
4122  *   0 on success, a negative errno value otherwise and rte_errno is set.
4123  */
4124 static int
4125 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4126                                struct mlx5_flow *dev_flow,
4127                                uint8_t transfer,
4128                                struct rte_flow_error *error)
4129 {
4130         struct mlx5_flow_dv_encap_decap_resource res = {
4131                 .size = 0,
4132                 .reformat_type =
4133                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4134                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4135                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4136         };
4137
4138         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4139                 return rte_flow_error_set(error, EINVAL,
4140                                           RTE_FLOW_ERROR_TYPE_ACTION,
4141                                           NULL, "can't create L2 decap action");
4142         return 0;
4143 }
4144
4145 /**
4146  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4147  *
4148  * @param[in] dev
4149  *   Pointer to rte_eth_dev structure.
4150  * @param[in] action
4151  *   Pointer to action structure.
4152  * @param[in, out] dev_flow
4153  *   Pointer to the mlx5_flow.
4154  * @param[in] attr
4155  *   Pointer to the flow attributes.
4156  * @param[out] error
4157  *   Pointer to the error structure.
4158  *
4159  * @return
4160  *   0 on success, a negative errno value otherwise and rte_errno is set.
4161  */
4162 static int
4163 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4164                                 const struct rte_flow_action *action,
4165                                 struct mlx5_flow *dev_flow,
4166                                 const struct rte_flow_attr *attr,
4167                                 struct rte_flow_error *error)
4168 {
4169         const struct rte_flow_action_raw_encap *encap_data;
4170         struct mlx5_flow_dv_encap_decap_resource res;
4171
4172         memset(&res, 0, sizeof(res));
4173         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4174         res.size = encap_data->size;
4175         memcpy(res.buf, encap_data->data, res.size);
4176         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4177                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4178                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4179         if (attr->transfer)
4180                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4181         else
4182                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4183                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4184         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4185                 return rte_flow_error_set(error, EINVAL,
4186                                           RTE_FLOW_ERROR_TYPE_ACTION,
4187                                           NULL, "can't create encap action");
4188         return 0;
4189 }
4190
4191 /**
4192  * Create action push VLAN.
4193  *
4194  * @param[in] dev
4195  *   Pointer to rte_eth_dev structure.
4196  * @param[in] attr
4197  *   Pointer to the flow attributes.
4198  * @param[in] vlan
4199  *   Pointer to the vlan to push to the Ethernet header.
4200  * @param[in, out] dev_flow
4201  *   Pointer to the mlx5_flow.
4202  * @param[out] error
4203  *   Pointer to the error structure.
4204  *
4205  * @return
4206  *   0 on success, a negative errno value otherwise and rte_errno is set.
4207  */
4208 static int
4209 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4210                                 const struct rte_flow_attr *attr,
4211                                 const struct rte_vlan_hdr *vlan,
4212                                 struct mlx5_flow *dev_flow,
4213                                 struct rte_flow_error *error)
4214 {
4215         struct mlx5_flow_dv_push_vlan_action_resource res;
4216
4217         memset(&res, 0, sizeof(res));
4218         res.vlan_tag =
4219                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4220                                  vlan->vlan_tci);
4221         if (attr->transfer)
4222                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4223         else
4224                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4225                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4226         return flow_dv_push_vlan_action_resource_register
4227                                             (dev, &res, dev_flow, error);
4228 }
4229
4230 /**
4231  * Validate the modify-header actions.
4232  *
4233  * @param[in] action_flags
4234  *   Holds the actions detected until now.
4235  * @param[in] action
4236  *   Pointer to the modify action.
4237  * @param[out] error
4238  *   Pointer to error structure.
4239  *
4240  * @return
4241  *   0 on success, a negative errno value otherwise and rte_errno is set.
4242  */
4243 static int
4244 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4245                                    const struct rte_flow_action *action,
4246                                    struct rte_flow_error *error)
4247 {
4248         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4249                 return rte_flow_error_set(error, EINVAL,
4250                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4251                                           NULL, "action configuration not set");
4252         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4253                 return rte_flow_error_set(error, EINVAL,
4254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4255                                           "can't have encap action before"
4256                                           " modify action");
4257         return 0;
4258 }
4259
4260 /**
4261  * Validate the modify-header MAC address actions.
4262  *
4263  * @param[in] action_flags
4264  *   Holds the actions detected until now.
4265  * @param[in] action
4266  *   Pointer to the modify action.
4267  * @param[in] item_flags
4268  *   Holds the items detected.
4269  * @param[out] error
4270  *   Pointer to error structure.
4271  *
4272  * @return
4273  *   0 on success, a negative errno value otherwise and rte_errno is set.
4274  */
4275 static int
4276 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4277                                    const struct rte_flow_action *action,
4278                                    const uint64_t item_flags,
4279                                    struct rte_flow_error *error)
4280 {
4281         int ret = 0;
4282
4283         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4284         if (!ret) {
4285                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4286                         return rte_flow_error_set(error, EINVAL,
4287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4288                                                   NULL,
4289                                                   "no L2 item in pattern");
4290         }
4291         return ret;
4292 }
4293
4294 /**
4295  * Validate the modify-header IPv4 address actions.
4296  *
4297  * @param[in] action_flags
4298  *   Holds the actions detected until now.
4299  * @param[in] action
4300  *   Pointer to the modify action.
4301  * @param[in] item_flags
4302  *   Holds the items detected.
4303  * @param[out] error
4304  *   Pointer to error structure.
4305  *
4306  * @return
4307  *   0 on success, a negative errno value otherwise and rte_errno is set.
4308  */
4309 static int
4310 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4311                                     const struct rte_flow_action *action,
4312                                     const uint64_t item_flags,
4313                                     struct rte_flow_error *error)
4314 {
4315         int ret = 0;
4316         uint64_t layer;
4317
4318         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4319         if (!ret) {
4320                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4321                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4322                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4323                 if (!(item_flags & layer))
4324                         return rte_flow_error_set(error, EINVAL,
4325                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4326                                                   NULL,
4327                                                   "no ipv4 item in pattern");
4328         }
4329         return ret;
4330 }
4331
4332 /**
4333  * Validate the modify-header IPv6 address actions.
4334  *
4335  * @param[in] action_flags
4336  *   Holds the actions detected until now.
4337  * @param[in] action
4338  *   Pointer to the modify action.
4339  * @param[in] item_flags
4340  *   Holds the items detected.
4341  * @param[out] error
4342  *   Pointer to error structure.
4343  *
4344  * @return
4345  *   0 on success, a negative errno value otherwise and rte_errno is set.
4346  */
4347 static int
4348 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4349                                     const struct rte_flow_action *action,
4350                                     const uint64_t item_flags,
4351                                     struct rte_flow_error *error)
4352 {
4353         int ret = 0;
4354         uint64_t layer;
4355
4356         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4357         if (!ret) {
4358                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4359                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4360                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4361                 if (!(item_flags & layer))
4362                         return rte_flow_error_set(error, EINVAL,
4363                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4364                                                   NULL,
4365                                                   "no ipv6 item in pattern");
4366         }
4367         return ret;
4368 }
4369
4370 /**
4371  * Validate the modify-header TP actions.
4372  *
4373  * @param[in] action_flags
4374  *   Holds the actions detected until now.
4375  * @param[in] action
4376  *   Pointer to the modify action.
4377  * @param[in] item_flags
4378  *   Holds the items detected.
4379  * @param[out] error
4380  *   Pointer to error structure.
4381  *
4382  * @return
4383  *   0 on success, a negative errno value otherwise and rte_errno is set.
4384  */
4385 static int
4386 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4387                                   const struct rte_flow_action *action,
4388                                   const uint64_t item_flags,
4389                                   struct rte_flow_error *error)
4390 {
4391         int ret = 0;
4392         uint64_t layer;
4393
4394         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4395         if (!ret) {
4396                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4397                                  MLX5_FLOW_LAYER_INNER_L4 :
4398                                  MLX5_FLOW_LAYER_OUTER_L4;
4399                 if (!(item_flags & layer))
4400                         return rte_flow_error_set(error, EINVAL,
4401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4402                                                   NULL, "no transport layer "
4403                                                   "in pattern");
4404         }
4405         return ret;
4406 }
4407
4408 /**
4409  * Validate the modify-header actions of increment/decrement
4410  * TCP Sequence-number.
4411  *
4412  * @param[in] action_flags
4413  *   Holds the actions detected until now.
4414  * @param[in] action
4415  *   Pointer to the modify action.
4416  * @param[in] item_flags
4417  *   Holds the items detected.
4418  * @param[out] error
4419  *   Pointer to error structure.
4420  *
4421  * @return
4422  *   0 on success, a negative errno value otherwise and rte_errno is set.
4423  */
4424 static int
4425 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4426                                        const struct rte_flow_action *action,
4427                                        const uint64_t item_flags,
4428                                        struct rte_flow_error *error)
4429 {
4430         int ret = 0;
4431         uint64_t layer;
4432
4433         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4434         if (!ret) {
4435                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4436                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4437                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4438                 if (!(item_flags & layer))
4439                         return rte_flow_error_set(error, EINVAL,
4440                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4441                                                   NULL, "no TCP item in"
4442                                                   " pattern");
4443                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4444                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4445                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4446                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4447                         return rte_flow_error_set(error, EINVAL,
4448                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4449                                                   NULL,
4450                                                   "cannot decrease and increase"
4451                                                   " TCP sequence number"
4452                                                   " at the same time");
4453         }
4454         return ret;
4455 }
4456
4457 /**
4458  * Validate the modify-header actions of increment/decrement
4459  * TCP Acknowledgment number.
4460  *
4461  * @param[in] action_flags
4462  *   Holds the actions detected until now.
4463  * @param[in] action
4464  *   Pointer to the modify action.
4465  * @param[in] item_flags
4466  *   Holds the items detected.
4467  * @param[out] error
4468  *   Pointer to error structure.
4469  *
4470  * @return
4471  *   0 on success, a negative errno value otherwise and rte_errno is set.
4472  */
4473 static int
4474 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4475                                        const struct rte_flow_action *action,
4476                                        const uint64_t item_flags,
4477                                        struct rte_flow_error *error)
4478 {
4479         int ret = 0;
4480         uint64_t layer;
4481
4482         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4483         if (!ret) {
4484                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4485                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4486                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4487                 if (!(item_flags & layer))
4488                         return rte_flow_error_set(error, EINVAL,
4489                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4490                                                   NULL, "no TCP item in"
4491                                                   " pattern");
4492                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4493                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4494                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4495                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4496                         return rte_flow_error_set(error, EINVAL,
4497                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4498                                                   NULL,
4499                                                   "cannot decrease and increase"
4500                                                   " TCP acknowledgment number"
4501                                                   " at the same time");
4502         }
4503         return ret;
4504 }
4505
4506 /**
4507  * Validate the modify-header TTL actions.
4508  *
4509  * @param[in] action_flags
4510  *   Holds the actions detected until now.
4511  * @param[in] action
4512  *   Pointer to the modify action.
4513  * @param[in] item_flags
4514  *   Holds the items detected.
4515  * @param[out] error
4516  *   Pointer to error structure.
4517  *
4518  * @return
4519  *   0 on success, a negative errno value otherwise and rte_errno is set.
4520  */
4521 static int
4522 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4523                                    const struct rte_flow_action *action,
4524                                    const uint64_t item_flags,
4525                                    struct rte_flow_error *error)
4526 {
4527         int ret = 0;
4528         uint64_t layer;
4529
4530         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4531         if (!ret) {
4532                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4533                                  MLX5_FLOW_LAYER_INNER_L3 :
4534                                  MLX5_FLOW_LAYER_OUTER_L3;
4535                 if (!(item_flags & layer))
4536                         return rte_flow_error_set(error, EINVAL,
4537                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4538                                                   NULL,
4539                                                   "no IP protocol in pattern");
4540         }
4541         return ret;
4542 }
4543
4544 /**
4545  * Validate the generic modify field actions.
4546  * @param[in] dev
4547  *   Pointer to the rte_eth_dev structure.
4548  * @param[in] action_flags
4549  *   Holds the actions detected until now.
4550  * @param[in] action
4551  *   Pointer to the modify action.
4552  * @param[in] attr
4553  *   Pointer to the flow attributes.
4554  * @param[out] error
4555  *   Pointer to error structure.
4556  *
4557  * @return
4558  *   Number of header fields to modify (0 or more) on success,
4559  *   a negative errno value otherwise and rte_errno is set.
4560  */
4561 static int
4562 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4563                                    const uint64_t action_flags,
4564                                    const struct rte_flow_action *action,
4565                                    const struct rte_flow_attr *attr,
4566                                    struct rte_flow_error *error)
4567 {
4568         int ret = 0;
4569         struct mlx5_priv *priv = dev->data->dev_private;
4570         struct mlx5_dev_config *config = &priv->config;
4571         const struct rte_flow_action_modify_field *action_modify_field =
4572                 action->conf;
4573         uint32_t dst_width =
4574                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4575         uint32_t src_width =
4576                 mlx5_flow_item_field_width(action_modify_field->src.field);
4577
4578         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4579         if (ret)
4580                 return ret;
4581
4582         if (action_modify_field->width == 0)
4583                 return rte_flow_error_set(error, EINVAL,
4584                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4585                                 "no bits are requested to be modified");
4586         else if (action_modify_field->width > dst_width ||
4587                  action_modify_field->width > src_width)
4588                 return rte_flow_error_set(error, EINVAL,
4589                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4590                                 "cannot modify more bits than"
4591                                 " the width of a field");
4592         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4593             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4594                 if ((action_modify_field->dst.offset +
4595                      action_modify_field->width > dst_width) ||
4596                     (action_modify_field->dst.offset % 32))
4597                         return rte_flow_error_set(error, EINVAL,
4598                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4599                                         "destination offset is too big"
4600                                         " or not aligned to 4 bytes");
4601                 if (action_modify_field->dst.level &&
4602                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4603                         return rte_flow_error_set(error, ENOTSUP,
4604                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4605                                         "inner header fields modification"
4606                                         " is not supported");
4607         }
4608         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4609             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4610                 if (!attr->transfer && !attr->group)
4611                         return rte_flow_error_set(error, ENOTSUP,
4612                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4613                                         "modify field action is not"
4614                                         " supported for group 0");
4615                 if ((action_modify_field->src.offset +
4616                      action_modify_field->width > src_width) ||
4617                     (action_modify_field->src.offset % 32))
4618                         return rte_flow_error_set(error, EINVAL,
4619                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4620                                         "source offset is too big"
4621                                         " or not aligned to 4 bytes");
4622                 if (action_modify_field->src.level &&
4623                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4624                         return rte_flow_error_set(error, ENOTSUP,
4625                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4626                                         "inner header fields modification"
4627                                         " is not supported");
4628         }
4629         if (action_modify_field->dst.field ==
4630             action_modify_field->src.field)
4631                 return rte_flow_error_set(error, EINVAL,
4632                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4633                                 "source and destination fields"
4634                                 " cannot be the same");
4635         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4636             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4637                 return rte_flow_error_set(error, EINVAL,
4638                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4639                                 "immediate value or a pointer to it"
4640                                 " cannot be used as a destination");
4641         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4642             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4643                 return rte_flow_error_set(error, ENOTSUP,
4644                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4645                                 "modifications of an arbitrary"
4646                                 " place in a packet is not supported");
4647         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4648             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4649                 return rte_flow_error_set(error, ENOTSUP,
4650                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4651                                 "modifications of the 802.1Q Tag"
4652                                 " Identifier is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4655                 return rte_flow_error_set(error, ENOTSUP,
4656                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4657                                 "modifications of the VXLAN Network"
4658                                 " Identifier is not supported");
4659         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4660             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4661                 return rte_flow_error_set(error, ENOTSUP,
4662                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4663                                 "modifications of the GENEVE Network"
4664                                 " Identifier is not supported");
4665         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4666             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4667             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4668             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4669                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4670                     !mlx5_flow_ext_mreg_supported(dev))
4671                         return rte_flow_error_set(error, ENOTSUP,
4672                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4673                                         "cannot modify mark or metadata without"
4674                                         " extended metadata register support");
4675         }
4676         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4677                 return rte_flow_error_set(error, ENOTSUP,
4678                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4679                                 "add and sub operations"
4680                                 " are not supported");
4681         return (action_modify_field->width / 32) +
4682                !!(action_modify_field->width % 32);
4683 }
4684
4685 /**
4686  * Validate jump action.
4687  *
4688  * @param[in] action
4689  *   Pointer to the jump action.
4690  * @param[in] action_flags
4691  *   Holds the actions detected until now.
4692  * @param[in] attributes
4693  *   Pointer to flow attributes
4694  * @param[in] external
4695  *   Action belongs to flow rule created by request external to PMD.
4696  * @param[out] error
4697  *   Pointer to error structure.
4698  *
4699  * @return
4700  *   0 on success, a negative errno value otherwise and rte_errno is set.
4701  */
4702 static int
4703 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4704                              const struct mlx5_flow_tunnel *tunnel,
4705                              const struct rte_flow_action *action,
4706                              uint64_t action_flags,
4707                              const struct rte_flow_attr *attributes,
4708                              bool external, struct rte_flow_error *error)
4709 {
4710         uint32_t target_group, table;
4711         int ret = 0;
4712         struct flow_grp_info grp_info = {
4713                 .external = !!external,
4714                 .transfer = !!attributes->transfer,
4715                 .fdb_def_rule = 1,
4716                 .std_tbl_fix = 0
4717         };
4718         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4719                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4720                 return rte_flow_error_set(error, EINVAL,
4721                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4722                                           "can't have 2 fate actions in"
4723                                           " same flow");
4724         if (action_flags & MLX5_FLOW_ACTION_METER)
4725                 return rte_flow_error_set(error, ENOTSUP,
4726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4727                                           "jump with meter not support");
4728         if (!action->conf)
4729                 return rte_flow_error_set(error, EINVAL,
4730                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4731                                           NULL, "action configuration not set");
4732         target_group =
4733                 ((const struct rte_flow_action_jump *)action->conf)->group;
4734         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4735                                        &grp_info, error);
4736         if (ret)
4737                 return ret;
4738         if (attributes->group == target_group &&
4739             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4740                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4741                 return rte_flow_error_set(error, EINVAL,
4742                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4743                                           "target group must be other than"
4744                                           " the current flow group");
4745         return 0;
4746 }
4747
4748 /*
4749  * Validate the port_id action.
4750  *
4751  * @param[in] dev
4752  *   Pointer to rte_eth_dev structure.
4753  * @param[in] action_flags
4754  *   Bit-fields that holds the actions detected until now.
4755  * @param[in] action
4756  *   Port_id RTE action structure.
4757  * @param[in] attr
4758  *   Attributes of flow that includes this action.
4759  * @param[out] error
4760  *   Pointer to error structure.
4761  *
4762  * @return
4763  *   0 on success, a negative errno value otherwise and rte_errno is set.
4764  */
4765 static int
4766 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4767                                 uint64_t action_flags,
4768                                 const struct rte_flow_action *action,
4769                                 const struct rte_flow_attr *attr,
4770                                 struct rte_flow_error *error)
4771 {
4772         const struct rte_flow_action_port_id *port_id;
4773         struct mlx5_priv *act_priv;
4774         struct mlx5_priv *dev_priv;
4775         uint16_t port;
4776
4777         if (!attr->transfer)
4778                 return rte_flow_error_set(error, ENOTSUP,
4779                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4780                                           NULL,
4781                                           "port id action is valid in transfer"
4782                                           " mode only");
4783         if (!action || !action->conf)
4784                 return rte_flow_error_set(error, ENOTSUP,
4785                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4786                                           NULL,
4787                                           "port id action parameters must be"
4788                                           " specified");
4789         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4790                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4791                 return rte_flow_error_set(error, EINVAL,
4792                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4793                                           "can have only one fate actions in"
4794                                           " a flow");
4795         dev_priv = mlx5_dev_to_eswitch_info(dev);
4796         if (!dev_priv)
4797                 return rte_flow_error_set(error, rte_errno,
4798                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4799                                           NULL,
4800                                           "failed to obtain E-Switch info");
4801         port_id = action->conf;
4802         port = port_id->original ? dev->data->port_id : port_id->id;
4803         act_priv = mlx5_port_to_eswitch_info(port, false);
4804         if (!act_priv)
4805                 return rte_flow_error_set
4806                                 (error, rte_errno,
4807                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4808                                  "failed to obtain E-Switch port id for port");
4809         if (act_priv->domain_id != dev_priv->domain_id)
4810                 return rte_flow_error_set
4811                                 (error, EINVAL,
4812                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4813                                  "port does not belong to"
4814                                  " E-Switch being configured");
4815         return 0;
4816 }
4817
4818 /**
4819  * Get the maximum number of modify header actions.
4820  *
4821  * @param dev
4822  *   Pointer to rte_eth_dev structure.
4823  * @param flags
4824  *   Flags bits to check if root level.
4825  *
4826  * @return
4827  *   Max number of modify header actions device can support.
4828  */
4829 static inline unsigned int
4830 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4831                               uint64_t flags)
4832 {
4833         /*
4834          * There's no way to directly query the max capacity from FW.
4835          * The maximal value on root table should be assumed to be supported.
4836          */
4837         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4838                 return MLX5_MAX_MODIFY_NUM;
4839         else
4840                 return MLX5_ROOT_TBL_MODIFY_NUM;
4841 }
4842
4843 /**
4844  * Validate the meter action.
4845  *
4846  * @param[in] dev
4847  *   Pointer to rte_eth_dev structure.
4848  * @param[in] action_flags
4849  *   Bit-fields that holds the actions detected until now.
4850  * @param[in] action
4851  *   Pointer to the meter action.
4852  * @param[in] attr
4853  *   Attributes of flow that includes this action.
4854  * @param[out] error
4855  *   Pointer to error structure.
4856  *
4857  * @return
4858  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4859  */
4860 static int
4861 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4862                                 uint64_t action_flags,
4863                                 const struct rte_flow_action *action,
4864                                 const struct rte_flow_attr *attr,
4865                                 struct rte_flow_error *error)
4866 {
4867         struct mlx5_priv *priv = dev->data->dev_private;
4868         const struct rte_flow_action_meter *am = action->conf;
4869         struct mlx5_flow_meter_info *fm;
4870
4871         if (!am)
4872                 return rte_flow_error_set(error, EINVAL,
4873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4874                                           "meter action conf is NULL");
4875
4876         if (action_flags & MLX5_FLOW_ACTION_METER)
4877                 return rte_flow_error_set(error, ENOTSUP,
4878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4879                                           "meter chaining not support");
4880         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4881                 return rte_flow_error_set(error, ENOTSUP,
4882                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4883                                           "meter with jump not support");
4884         if (!priv->mtr_en)
4885                 return rte_flow_error_set(error, ENOTSUP,
4886                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4887                                           NULL,
4888                                           "meter action not supported");
4889         fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
4890         if (!fm)
4891                 return rte_flow_error_set(error, EINVAL,
4892                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4893                                           "Meter not found");
4894         /* aso meter can always be shared by different domains */
4895         if (fm->ref_cnt && !priv->sh->meter_aso_en &&
4896             !(fm->transfer == attr->transfer ||
4897               (!fm->ingress && !attr->ingress && attr->egress) ||
4898               (!fm->egress && !attr->egress && attr->ingress)))
4899                 return rte_flow_error_set(error, EINVAL,
4900                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4901                                           "Flow attributes are either invalid "
4902                                           "or have a conflict with current "
4903                                           "meter attributes");
4904         return 0;
4905 }
4906
4907 /**
4908  * Validate the age action.
4909  *
4910  * @param[in] action_flags
4911  *   Holds the actions detected until now.
4912  * @param[in] action
4913  *   Pointer to the age action.
4914  * @param[in] dev
4915  *   Pointer to the Ethernet device structure.
4916  * @param[out] error
4917  *   Pointer to error structure.
4918  *
4919  * @return
4920  *   0 on success, a negative errno value otherwise and rte_errno is set.
4921  */
4922 static int
4923 flow_dv_validate_action_age(uint64_t action_flags,
4924                             const struct rte_flow_action *action,
4925                             struct rte_eth_dev *dev,
4926                             struct rte_flow_error *error)
4927 {
4928         struct mlx5_priv *priv = dev->data->dev_private;
4929         const struct rte_flow_action_age *age = action->conf;
4930
4931         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4932             !priv->sh->aso_age_mng))
4933                 return rte_flow_error_set(error, ENOTSUP,
4934                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4935                                           NULL,
4936                                           "age action not supported");
4937         if (!(action->conf))
4938                 return rte_flow_error_set(error, EINVAL,
4939                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4940                                           "configuration cannot be null");
4941         if (!(age->timeout))
4942                 return rte_flow_error_set(error, EINVAL,
4943                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4944                                           "invalid timeout value 0");
4945         if (action_flags & MLX5_FLOW_ACTION_AGE)
4946                 return rte_flow_error_set(error, EINVAL,
4947                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4948                                           "duplicate age actions set");
4949         return 0;
4950 }
4951
4952 /**
4953  * Validate the modify-header IPv4 DSCP actions.
4954  *
4955  * @param[in] action_flags
4956  *   Holds the actions detected until now.
4957  * @param[in] action
4958  *   Pointer to the modify action.
4959  * @param[in] item_flags
4960  *   Holds the items detected.
4961  * @param[out] error
4962  *   Pointer to error structure.
4963  *
4964  * @return
4965  *   0 on success, a negative errno value otherwise and rte_errno is set.
4966  */
4967 static int
4968 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4969                                          const struct rte_flow_action *action,
4970                                          const uint64_t item_flags,
4971                                          struct rte_flow_error *error)
4972 {
4973         int ret = 0;
4974
4975         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4976         if (!ret) {
4977                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4978                         return rte_flow_error_set(error, EINVAL,
4979                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4980                                                   NULL,
4981                                                   "no ipv4 item in pattern");
4982         }
4983         return ret;
4984 }
4985
4986 /**
4987  * Validate the modify-header IPv6 DSCP actions.
4988  *
4989  * @param[in] action_flags
4990  *   Holds the actions detected until now.
4991  * @param[in] action
4992  *   Pointer to the modify action.
4993  * @param[in] item_flags
4994  *   Holds the items detected.
4995  * @param[out] error
4996  *   Pointer to error structure.
4997  *
4998  * @return
4999  *   0 on success, a negative errno value otherwise and rte_errno is set.
5000  */
5001 static int
5002 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5003                                          const struct rte_flow_action *action,
5004                                          const uint64_t item_flags,
5005                                          struct rte_flow_error *error)
5006 {
5007         int ret = 0;
5008
5009         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5010         if (!ret) {
5011                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5012                         return rte_flow_error_set(error, EINVAL,
5013                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5014                                                   NULL,
5015                                                   "no ipv6 item in pattern");
5016         }
5017         return ret;
5018 }
5019
5020 /**
5021  * Match modify-header resource.
5022  *
5023  * @param list
5024  *   Pointer to the hash list.
5025  * @param entry
5026  *   Pointer to exist resource entry object.
5027  * @param key
5028  *   Key of the new entry.
5029  * @param ctx
5030  *   Pointer to new modify-header resource.
5031  *
5032  * @return
5033  *   0 on matching, non-zero otherwise.
5034  */
5035 int
5036 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5037                         struct mlx5_hlist_entry *entry,
5038                         uint64_t key __rte_unused, void *cb_ctx)
5039 {
5040         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5041         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5042         struct mlx5_flow_dv_modify_hdr_resource *resource =
5043                         container_of(entry, typeof(*resource), entry);
5044         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5045
5046         key_len += ref->actions_num * sizeof(ref->actions[0]);
5047         return ref->actions_num != resource->actions_num ||
5048                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5049 }
5050
5051 struct mlx5_hlist_entry *
5052 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5053                          void *cb_ctx)
5054 {
5055         struct mlx5_dev_ctx_shared *sh = list->ctx;
5056         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5057         struct mlx5dv_dr_domain *ns;
5058         struct mlx5_flow_dv_modify_hdr_resource *entry;
5059         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5060         int ret;
5061         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5062         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5063
5064         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5065                             SOCKET_ID_ANY);
5066         if (!entry) {
5067                 rte_flow_error_set(ctx->error, ENOMEM,
5068                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5069                                    "cannot allocate resource memory");
5070                 return NULL;
5071         }
5072         rte_memcpy(&entry->ft_type,
5073                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5074                    key_len + data_len);
5075         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5076                 ns = sh->fdb_domain;
5077         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5078                 ns = sh->tx_domain;
5079         else
5080                 ns = sh->rx_domain;
5081         ret = mlx5_flow_os_create_flow_action_modify_header
5082                                         (sh->ctx, ns, entry,
5083                                          data_len, &entry->action);
5084         if (ret) {
5085                 mlx5_free(entry);
5086                 rte_flow_error_set(ctx->error, ENOMEM,
5087                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5088                                    NULL, "cannot create modification action");
5089                 return NULL;
5090         }
5091         return &entry->entry;
5092 }
5093
5094 /**
5095  * Validate the sample action.
5096  *
5097  * @param[in, out] action_flags
5098  *   Holds the actions detected until now.
5099  * @param[in] action
5100  *   Pointer to the sample action.
5101  * @param[in] dev
5102  *   Pointer to the Ethernet device structure.
5103  * @param[in] attr
5104  *   Attributes of flow that includes this action.
5105  * @param[in] item_flags
5106  *   Holds the items detected.
5107  * @param[in] rss
5108  *   Pointer to the RSS action.
5109  * @param[out] sample_rss
5110  *   Pointer to the RSS action in sample action list.
5111  * @param[out] count
5112  *   Pointer to the COUNT action in sample action list.
5113  * @param[out] fdb_mirror_limit
5114  *   Pointer to the FDB mirror limitation flag.
5115  * @param[out] error
5116  *   Pointer to error structure.
5117  *
5118  * @return
5119  *   0 on success, a negative errno value otherwise and rte_errno is set.
5120  */
5121 static int
5122 flow_dv_validate_action_sample(uint64_t *action_flags,
5123                                const struct rte_flow_action *action,
5124                                struct rte_eth_dev *dev,
5125                                const struct rte_flow_attr *attr,
5126                                uint64_t item_flags,
5127                                const struct rte_flow_action_rss *rss,
5128                                const struct rte_flow_action_rss **sample_rss,
5129                                const struct rte_flow_action_count **count,
5130                                int *fdb_mirror_limit,
5131                                struct rte_flow_error *error)
5132 {
5133         struct mlx5_priv *priv = dev->data->dev_private;
5134         struct mlx5_dev_config *dev_conf = &priv->config;
5135         const struct rte_flow_action_sample *sample = action->conf;
5136         const struct rte_flow_action *act;
5137         uint64_t sub_action_flags = 0;
5138         uint16_t queue_index = 0xFFFF;
5139         int actions_n = 0;
5140         int ret;
5141
5142         if (!sample)
5143                 return rte_flow_error_set(error, EINVAL,
5144                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5145                                           "configuration cannot be NULL");
5146         if (sample->ratio == 0)
5147                 return rte_flow_error_set(error, EINVAL,
5148                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5149                                           "ratio value starts from 1");
5150         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5151                 return rte_flow_error_set(error, ENOTSUP,
5152                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5153                                           NULL,
5154                                           "sample action not supported");
5155         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5156                 return rte_flow_error_set(error, EINVAL,
5157                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5158                                           "Multiple sample actions not "
5159                                           "supported");
5160         if (*action_flags & MLX5_FLOW_ACTION_METER)
5161                 return rte_flow_error_set(error, EINVAL,
5162                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5163                                           "wrong action order, meter should "
5164                                           "be after sample action");
5165         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5166                 return rte_flow_error_set(error, EINVAL,
5167                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5168                                           "wrong action order, jump should "
5169                                           "be after sample action");
5170         act = sample->actions;
5171         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5172                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5173                         return rte_flow_error_set(error, ENOTSUP,
5174                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5175                                                   act, "too many actions");
5176                 switch (act->type) {
5177                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5178                         ret = mlx5_flow_validate_action_queue(act,
5179                                                               sub_action_flags,
5180                                                               dev,
5181                                                               attr, error);
5182                         if (ret < 0)
5183                                 return ret;
5184                         queue_index = ((const struct rte_flow_action_queue *)
5185                                                         (act->conf))->index;
5186                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5187                         ++actions_n;
5188                         break;
5189                 case RTE_FLOW_ACTION_TYPE_RSS:
5190                         *sample_rss = act->conf;
5191                         ret = mlx5_flow_validate_action_rss(act,
5192                                                             sub_action_flags,
5193                                                             dev, attr,
5194                                                             item_flags,
5195                                                             error);
5196                         if (ret < 0)
5197                                 return ret;
5198                         if (rss && *sample_rss &&
5199                             ((*sample_rss)->level != rss->level ||
5200                             (*sample_rss)->types != rss->types))
5201                                 return rte_flow_error_set(error, ENOTSUP,
5202                                         RTE_FLOW_ERROR_TYPE_ACTION,
5203                                         NULL,
5204                                         "Can't use the different RSS types "
5205                                         "or level in the same flow");
5206                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5207                                 queue_index = (*sample_rss)->queue[0];
5208                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5209                         ++actions_n;
5210                         break;
5211                 case RTE_FLOW_ACTION_TYPE_MARK:
5212                         ret = flow_dv_validate_action_mark(dev, act,
5213                                                            sub_action_flags,
5214                                                            attr, error);
5215                         if (ret < 0)
5216                                 return ret;
5217                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5218                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5219                                                 MLX5_FLOW_ACTION_MARK_EXT;
5220                         else
5221                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5222                         ++actions_n;
5223                         break;
5224                 case RTE_FLOW_ACTION_TYPE_COUNT:
5225                         ret = flow_dv_validate_action_count
5226                                 (dev, act,
5227                                  *action_flags | sub_action_flags,
5228                                  error);
5229                         if (ret < 0)
5230                                 return ret;
5231                         *count = act->conf;
5232                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5233                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5234                         ++actions_n;
5235                         break;
5236                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5237                         ret = flow_dv_validate_action_port_id(dev,
5238                                                               sub_action_flags,
5239                                                               act,
5240                                                               attr,
5241                                                               error);
5242                         if (ret)
5243                                 return ret;
5244                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5245                         ++actions_n;
5246                         break;
5247                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5248                         ret = flow_dv_validate_action_raw_encap_decap
5249                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5250                                  &actions_n, action, item_flags, error);
5251                         if (ret < 0)
5252                                 return ret;
5253                         ++actions_n;
5254                         break;
5255                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5256                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5257                         ret = flow_dv_validate_action_l2_encap(dev,
5258                                                                sub_action_flags,
5259                                                                act, attr,
5260                                                                error);
5261                         if (ret < 0)
5262                                 return ret;
5263                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5264                         ++actions_n;
5265                         break;
5266                 default:
5267                         return rte_flow_error_set(error, ENOTSUP,
5268                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5269                                                   NULL,
5270                                                   "Doesn't support optional "
5271                                                   "action");
5272                 }
5273         }
5274         if (attr->ingress && !attr->transfer) {
5275                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5276                                           MLX5_FLOW_ACTION_RSS)))
5277                         return rte_flow_error_set(error, EINVAL,
5278                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5279                                                   NULL,
5280                                                   "Ingress must has a dest "
5281                                                   "QUEUE for Sample");
5282         } else if (attr->egress && !attr->transfer) {
5283                 return rte_flow_error_set(error, ENOTSUP,
5284                                           RTE_FLOW_ERROR_TYPE_ACTION,
5285                                           NULL,
5286                                           "Sample Only support Ingress "
5287                                           "or E-Switch");
5288         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5289                 MLX5_ASSERT(attr->transfer);
5290                 if (sample->ratio > 1)
5291                         return rte_flow_error_set(error, ENOTSUP,
5292                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5293                                                   NULL,
5294                                                   "E-Switch doesn't support "
5295                                                   "any optional action "
5296                                                   "for sampling");
5297                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5298                         return rte_flow_error_set(error, ENOTSUP,
5299                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5300                                                   NULL,
5301                                                   "unsupported action QUEUE");
5302                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5303                         return rte_flow_error_set(error, ENOTSUP,
5304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5305                                                   NULL,
5306                                                   "unsupported action QUEUE");
5307                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5308                         return rte_flow_error_set(error, EINVAL,
5309                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5310                                                   NULL,
5311                                                   "E-Switch must has a dest "
5312                                                   "port for mirroring");
5313                 if (!priv->config.hca_attr.reg_c_preserve &&
5314                      priv->representor_id != -1)
5315                         *fdb_mirror_limit = 1;
5316         }
5317         /* Continue validation for Xcap actions.*/
5318         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5319             (queue_index == 0xFFFF ||
5320              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5321                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5322                      MLX5_FLOW_XCAP_ACTIONS)
5323                         return rte_flow_error_set(error, ENOTSUP,
5324                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5325                                                   NULL, "encap and decap "
5326                                                   "combination aren't "
5327                                                   "supported");
5328                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5329                                                         MLX5_FLOW_ACTION_ENCAP))
5330                         return rte_flow_error_set(error, ENOTSUP,
5331                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5332                                                   NULL, "encap is not supported"
5333                                                   " for ingress traffic");
5334         }
5335         return 0;
5336 }
5337
5338 /**
5339  * Find existing modify-header resource or create and register a new one.
5340  *
5341  * @param dev[in, out]
5342  *   Pointer to rte_eth_dev structure.
5343  * @param[in, out] resource
5344  *   Pointer to modify-header resource.
5345  * @parm[in, out] dev_flow
5346  *   Pointer to the dev_flow.
5347  * @param[out] error
5348  *   pointer to error structure.
5349  *
5350  * @return
5351  *   0 on success otherwise -errno and errno is set.
5352  */
5353 static int
5354 flow_dv_modify_hdr_resource_register
5355                         (struct rte_eth_dev *dev,
5356                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5357                          struct mlx5_flow *dev_flow,
5358                          struct rte_flow_error *error)
5359 {
5360         struct mlx5_priv *priv = dev->data->dev_private;
5361         struct mlx5_dev_ctx_shared *sh = priv->sh;
5362         uint32_t key_len = sizeof(*resource) -
5363                            offsetof(typeof(*resource), ft_type) +
5364                            resource->actions_num * sizeof(resource->actions[0]);
5365         struct mlx5_hlist_entry *entry;
5366         struct mlx5_flow_cb_ctx ctx = {
5367                 .error = error,
5368                 .data = resource,
5369         };
5370         uint64_t key64;
5371
5372         resource->flags = dev_flow->dv.group ? 0 :
5373                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5374         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5375                                     resource->flags))
5376                 return rte_flow_error_set(error, EOVERFLOW,
5377                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5378                                           "too many modify header items");
5379         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5380         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5381         if (!entry)
5382                 return -rte_errno;
5383         resource = container_of(entry, typeof(*resource), entry);
5384         dev_flow->handle->dvh.modify_hdr = resource;
5385         return 0;
5386 }
5387
5388 /**
5389  * Get DV flow counter by index.
5390  *
5391  * @param[in] dev
5392  *   Pointer to the Ethernet device structure.
5393  * @param[in] idx
5394  *   mlx5 flow counter index in the container.
5395  * @param[out] ppool
5396  *   mlx5 flow counter pool in the container,
5397  *
5398  * @return
5399  *   Pointer to the counter, NULL otherwise.
5400  */
5401 static struct mlx5_flow_counter *
5402 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5403                            uint32_t idx,
5404                            struct mlx5_flow_counter_pool **ppool)
5405 {
5406         struct mlx5_priv *priv = dev->data->dev_private;
5407         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5408         struct mlx5_flow_counter_pool *pool;
5409
5410         /* Decrease to original index and clear shared bit. */
5411         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5412         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5413         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5414         MLX5_ASSERT(pool);
5415         if (ppool)
5416                 *ppool = pool;
5417         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5418 }
5419
5420 /**
5421  * Check the devx counter belongs to the pool.
5422  *
5423  * @param[in] pool
5424  *   Pointer to the counter pool.
5425  * @param[in] id
5426  *   The counter devx ID.
5427  *
5428  * @return
5429  *   True if counter belongs to the pool, false otherwise.
5430  */
5431 static bool
5432 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5433 {
5434         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5435                    MLX5_COUNTERS_PER_POOL;
5436
5437         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5438                 return true;
5439         return false;
5440 }
5441
5442 /**
5443  * Get a pool by devx counter ID.
5444  *
5445  * @param[in] cmng
5446  *   Pointer to the counter management.
5447  * @param[in] id
5448  *   The counter devx ID.
5449  *
5450  * @return
5451  *   The counter pool pointer if exists, NULL otherwise,
5452  */
5453 static struct mlx5_flow_counter_pool *
5454 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5455 {
5456         uint32_t i;
5457         struct mlx5_flow_counter_pool *pool = NULL;
5458
5459         rte_spinlock_lock(&cmng->pool_update_sl);
5460         /* Check last used pool. */
5461         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5462             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5463                 pool = cmng->pools[cmng->last_pool_idx];
5464                 goto out;
5465         }
5466         /* ID out of range means no suitable pool in the container. */
5467         if (id > cmng->max_id || id < cmng->min_id)
5468                 goto out;
5469         /*
5470          * Find the pool from the end of the container, since mostly counter
5471          * ID is sequence increasing, and the last pool should be the needed
5472          * one.
5473          */
5474         i = cmng->n_valid;
5475         while (i--) {
5476                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5477
5478                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5479                         pool = pool_tmp;
5480                         break;
5481                 }
5482         }
5483 out:
5484         rte_spinlock_unlock(&cmng->pool_update_sl);
5485         return pool;
5486 }
5487
5488 /**
5489  * Resize a counter container.
5490  *
5491  * @param[in] dev
5492  *   Pointer to the Ethernet device structure.
5493  *
5494  * @return
5495  *   0 on success, otherwise negative errno value and rte_errno is set.
5496  */
5497 static int
5498 flow_dv_container_resize(struct rte_eth_dev *dev)
5499 {
5500         struct mlx5_priv *priv = dev->data->dev_private;
5501         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5502         void *old_pools = cmng->pools;
5503         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5504         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5505         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5506
5507         if (!pools) {
5508                 rte_errno = ENOMEM;
5509                 return -ENOMEM;
5510         }
5511         if (old_pools)
5512                 memcpy(pools, old_pools, cmng->n *
5513                                        sizeof(struct mlx5_flow_counter_pool *));
5514         cmng->n = resize;
5515         cmng->pools = pools;
5516         if (old_pools)
5517                 mlx5_free(old_pools);
5518         return 0;
5519 }
5520
5521 /**
5522  * Query a devx flow counter.
5523  *
5524  * @param[in] dev
5525  *   Pointer to the Ethernet device structure.
5526  * @param[in] cnt
5527  *   Index to the flow counter.
5528  * @param[out] pkts
5529  *   The statistics value of packets.
5530  * @param[out] bytes
5531  *   The statistics value of bytes.
5532  *
5533  * @return
5534  *   0 on success, otherwise a negative errno value and rte_errno is set.
5535  */
5536 static inline int
5537 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5538                      uint64_t *bytes)
5539 {
5540         struct mlx5_priv *priv = dev->data->dev_private;
5541         struct mlx5_flow_counter_pool *pool = NULL;
5542         struct mlx5_flow_counter *cnt;
5543         int offset;
5544
5545         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5546         MLX5_ASSERT(pool);
5547         if (priv->sh->cmng.counter_fallback)
5548                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5549                                         0, pkts, bytes, 0, NULL, NULL, 0);
5550         rte_spinlock_lock(&pool->sl);
5551         if (!pool->raw) {
5552                 *pkts = 0;
5553                 *bytes = 0;
5554         } else {
5555                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5556                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5557                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5558         }
5559         rte_spinlock_unlock(&pool->sl);
5560         return 0;
5561 }
5562
5563 /**
5564  * Create and initialize a new counter pool.
5565  *
5566  * @param[in] dev
5567  *   Pointer to the Ethernet device structure.
5568  * @param[out] dcs
5569  *   The devX counter handle.
5570  * @param[in] age
5571  *   Whether the pool is for counter that was allocated for aging.
5572  * @param[in/out] cont_cur
5573  *   Pointer to the container pointer, it will be update in pool resize.
5574  *
5575  * @return
5576  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5577  */
5578 static struct mlx5_flow_counter_pool *
5579 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5580                     uint32_t age)
5581 {
5582         struct mlx5_priv *priv = dev->data->dev_private;
5583         struct mlx5_flow_counter_pool *pool;
5584         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5585         bool fallback = priv->sh->cmng.counter_fallback;
5586         uint32_t size = sizeof(*pool);
5587
5588         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5589         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5590         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5591         if (!pool) {
5592                 rte_errno = ENOMEM;
5593                 return NULL;
5594         }
5595         pool->raw = NULL;
5596         pool->is_aged = !!age;
5597         pool->query_gen = 0;
5598         pool->min_dcs = dcs;
5599         rte_spinlock_init(&pool->sl);
5600         rte_spinlock_init(&pool->csl);
5601         TAILQ_INIT(&pool->counters[0]);
5602         TAILQ_INIT(&pool->counters[1]);
5603         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5604         rte_spinlock_lock(&cmng->pool_update_sl);
5605         pool->index = cmng->n_valid;
5606         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5607                 mlx5_free(pool);
5608                 rte_spinlock_unlock(&cmng->pool_update_sl);
5609                 return NULL;
5610         }
5611         cmng->pools[pool->index] = pool;
5612         cmng->n_valid++;
5613         if (unlikely(fallback)) {
5614                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5615
5616                 if (base < cmng->min_id)
5617                         cmng->min_id = base;
5618                 if (base > cmng->max_id)
5619                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5620                 cmng->last_pool_idx = pool->index;
5621         }
5622         rte_spinlock_unlock(&cmng->pool_update_sl);
5623         return pool;
5624 }
5625
5626 /**
5627  * Prepare a new counter and/or a new counter pool.
5628  *
5629  * @param[in] dev
5630  *   Pointer to the Ethernet device structure.
5631  * @param[out] cnt_free
5632  *   Where to put the pointer of a new counter.
5633  * @param[in] age
5634  *   Whether the pool is for counter that was allocated for aging.
5635  *
5636  * @return
5637  *   The counter pool pointer and @p cnt_free is set on success,
5638  *   NULL otherwise and rte_errno is set.
5639  */
5640 static struct mlx5_flow_counter_pool *
5641 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5642                              struct mlx5_flow_counter **cnt_free,
5643                              uint32_t age)
5644 {
5645         struct mlx5_priv *priv = dev->data->dev_private;
5646         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5647         struct mlx5_flow_counter_pool *pool;
5648         struct mlx5_counters tmp_tq;
5649         struct mlx5_devx_obj *dcs = NULL;
5650         struct mlx5_flow_counter *cnt;
5651         enum mlx5_counter_type cnt_type =
5652                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5653         bool fallback = priv->sh->cmng.counter_fallback;
5654         uint32_t i;
5655
5656         if (fallback) {
5657                 /* bulk_bitmap must be 0 for single counter allocation. */
5658                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5659                 if (!dcs)
5660                         return NULL;
5661                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5662                 if (!pool) {
5663                         pool = flow_dv_pool_create(dev, dcs, age);
5664                         if (!pool) {
5665                                 mlx5_devx_cmd_destroy(dcs);
5666                                 return NULL;
5667                         }
5668                 }
5669                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5670                 cnt = MLX5_POOL_GET_CNT(pool, i);
5671                 cnt->pool = pool;
5672                 cnt->dcs_when_free = dcs;
5673                 *cnt_free = cnt;
5674                 return pool;
5675         }
5676         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5677         if (!dcs) {
5678                 rte_errno = ENODATA;
5679                 return NULL;
5680         }
5681         pool = flow_dv_pool_create(dev, dcs, age);
5682         if (!pool) {
5683                 mlx5_devx_cmd_destroy(dcs);
5684                 return NULL;
5685         }
5686         TAILQ_INIT(&tmp_tq);
5687         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5688                 cnt = MLX5_POOL_GET_CNT(pool, i);
5689                 cnt->pool = pool;
5690                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5691         }
5692         rte_spinlock_lock(&cmng->csl[cnt_type]);
5693         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5694         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5695         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5696         (*cnt_free)->pool = pool;
5697         return pool;
5698 }
5699
5700 /**
5701  * Allocate a flow counter.
5702  *
5703  * @param[in] dev
5704  *   Pointer to the Ethernet device structure.
5705  * @param[in] age
5706  *   Whether the counter was allocated for aging.
5707  *
5708  * @return
5709  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5710  */
5711 static uint32_t
5712 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5713 {
5714         struct mlx5_priv *priv = dev->data->dev_private;
5715         struct mlx5_flow_counter_pool *pool = NULL;
5716         struct mlx5_flow_counter *cnt_free = NULL;
5717         bool fallback = priv->sh->cmng.counter_fallback;
5718         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5719         enum mlx5_counter_type cnt_type =
5720                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5721         uint32_t cnt_idx;
5722
5723         if (!priv->config.devx) {
5724                 rte_errno = ENOTSUP;
5725                 return 0;
5726         }
5727         /* Get free counters from container. */
5728         rte_spinlock_lock(&cmng->csl[cnt_type]);
5729         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5730         if (cnt_free)
5731                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5732         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5733         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5734                 goto err;
5735         pool = cnt_free->pool;
5736         if (fallback)
5737                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5738         /* Create a DV counter action only in the first time usage. */
5739         if (!cnt_free->action) {
5740                 uint16_t offset;
5741                 struct mlx5_devx_obj *dcs;
5742                 int ret;
5743
5744                 if (!fallback) {
5745                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5746                         dcs = pool->min_dcs;
5747                 } else {
5748                         offset = 0;
5749                         dcs = cnt_free->dcs_when_free;
5750                 }
5751                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5752                                                             &cnt_free->action);
5753                 if (ret) {
5754                         rte_errno = errno;
5755                         goto err;
5756                 }
5757         }
5758         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5759                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5760         /* Update the counter reset values. */
5761         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5762                                  &cnt_free->bytes))
5763                 goto err;
5764         if (!fallback && !priv->sh->cmng.query_thread_on)
5765                 /* Start the asynchronous batch query by the host thread. */
5766                 mlx5_set_query_alarm(priv->sh);
5767         return cnt_idx;
5768 err:
5769         if (cnt_free) {
5770                 cnt_free->pool = pool;
5771                 if (fallback)
5772                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5773                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5774                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5775                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5776         }
5777         return 0;
5778 }
5779
5780 /**
5781  * Allocate a shared flow counter.
5782  *
5783  * @param[in] ctx
5784  *   Pointer to the shared counter configuration.
5785  * @param[in] data
5786  *   Pointer to save the allocated counter index.
5787  *
5788  * @return
5789  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5790  */
5791
5792 static int32_t
5793 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5794 {
5795         struct mlx5_shared_counter_conf *conf = ctx;
5796         struct rte_eth_dev *dev = conf->dev;
5797         struct mlx5_flow_counter *cnt;
5798
5799         data->dword = flow_dv_counter_alloc(dev, 0);
5800         data->dword |= MLX5_CNT_SHARED_OFFSET;
5801         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5802         cnt->shared_info.id = conf->id;
5803         return 0;
5804 }
5805
5806 /**
5807  * Get a shared flow counter.
5808  *
5809  * @param[in] dev
5810  *   Pointer to the Ethernet device structure.
5811  * @param[in] id
5812  *   Counter identifier.
5813  *
5814  * @return
5815  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5816  */
5817 static uint32_t
5818 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5819 {
5820         struct mlx5_priv *priv = dev->data->dev_private;
5821         struct mlx5_shared_counter_conf conf = {
5822                 .dev = dev,
5823                 .id = id,
5824         };
5825         union mlx5_l3t_data data = {
5826                 .dword = 0,
5827         };
5828
5829         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5830                                flow_dv_counter_alloc_shared_cb, &conf);
5831         return data.dword;
5832 }
5833
5834 /**
5835  * Get age param from counter index.
5836  *
5837  * @param[in] dev
5838  *   Pointer to the Ethernet device structure.
5839  * @param[in] counter
5840  *   Index to the counter handler.
5841  *
5842  * @return
5843  *   The aging parameter specified for the counter index.
5844  */
5845 static struct mlx5_age_param*
5846 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5847                                 uint32_t counter)
5848 {
5849         struct mlx5_flow_counter *cnt;
5850         struct mlx5_flow_counter_pool *pool = NULL;
5851
5852         flow_dv_counter_get_by_idx(dev, counter, &pool);
5853         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5854         cnt = MLX5_POOL_GET_CNT(pool, counter);
5855         return MLX5_CNT_TO_AGE(cnt);
5856 }
5857
5858 /**
5859  * Remove a flow counter from aged counter list.
5860  *
5861  * @param[in] dev
5862  *   Pointer to the Ethernet device structure.
5863  * @param[in] counter
5864  *   Index to the counter handler.
5865  * @param[in] cnt
5866  *   Pointer to the counter handler.
5867  */
5868 static void
5869 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5870                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5871 {
5872         struct mlx5_age_info *age_info;
5873         struct mlx5_age_param *age_param;
5874         struct mlx5_priv *priv = dev->data->dev_private;
5875         uint16_t expected = AGE_CANDIDATE;
5876
5877         age_info = GET_PORT_AGE_INFO(priv);
5878         age_param = flow_dv_counter_idx_get_age(dev, counter);
5879         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5880                                          AGE_FREE, false, __ATOMIC_RELAXED,
5881                                          __ATOMIC_RELAXED)) {
5882                 /**
5883                  * We need the lock even it is age timeout,
5884                  * since counter may still in process.
5885                  */
5886                 rte_spinlock_lock(&age_info->aged_sl);
5887                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5888                 rte_spinlock_unlock(&age_info->aged_sl);
5889                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5890         }
5891 }
5892
5893 /**
5894  * Release a flow counter.
5895  *
5896  * @param[in] dev
5897  *   Pointer to the Ethernet device structure.
5898  * @param[in] counter
5899  *   Index to the counter handler.
5900  */
5901 static void
5902 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5903 {
5904         struct mlx5_priv *priv = dev->data->dev_private;
5905         struct mlx5_flow_counter_pool *pool = NULL;
5906         struct mlx5_flow_counter *cnt;
5907         enum mlx5_counter_type cnt_type;
5908
5909         if (!counter)
5910                 return;
5911         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5912         MLX5_ASSERT(pool);
5913         if (IS_SHARED_CNT(counter) &&
5914             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5915                 return;
5916         if (pool->is_aged)
5917                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5918         cnt->pool = pool;
5919         /*
5920          * Put the counter back to list to be updated in none fallback mode.
5921          * Currently, we are using two list alternately, while one is in query,
5922          * add the freed counter to the other list based on the pool query_gen
5923          * value. After query finishes, add counter the list to the global
5924          * container counter list. The list changes while query starts. In
5925          * this case, lock will not be needed as query callback and release
5926          * function both operate with the different list.
5927          *
5928          */
5929         if (!priv->sh->cmng.counter_fallback) {
5930                 rte_spinlock_lock(&pool->csl);
5931                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5932                 rte_spinlock_unlock(&pool->csl);
5933         } else {
5934                 cnt->dcs_when_free = cnt->dcs_when_active;
5935                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5936                                            MLX5_COUNTER_TYPE_ORIGIN;
5937                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5938                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5939                                   cnt, next);
5940                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5941         }
5942 }
5943
5944 /**
5945  * Resize a meter id container.
5946  *
5947  * @param[in] dev
5948  *   Pointer to the Ethernet device structure.
5949  *
5950  * @return
5951  *   0 on success, otherwise negative errno value and rte_errno is set.
5952  */
5953 static int
5954 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
5955 {
5956         struct mlx5_priv *priv = dev->data->dev_private;
5957         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
5958         void *old_pools = mtrmng->pools;
5959         uint32_t resize = mtrmng->n + MLX5_MTRS_CONTAINER_RESIZE;
5960         uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
5961         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5962
5963         if (!pools) {
5964                 rte_errno = ENOMEM;
5965                 return -ENOMEM;
5966         }
5967         if (!mtrmng->n)
5968                 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
5969                         mlx5_free(pools);
5970                         return -ENOMEM;
5971                 }
5972         if (old_pools)
5973                 memcpy(pools, old_pools, mtrmng->n *
5974                                        sizeof(struct mlx5_aso_mtr_pool *));
5975         mtrmng->n = resize;
5976         mtrmng->pools = pools;
5977         if (old_pools)
5978                 mlx5_free(old_pools);
5979         return 0;
5980 }
5981
5982 /**
5983  * Prepare a new meter and/or a new meter pool.
5984  *
5985  * @param[in] dev
5986  *   Pointer to the Ethernet device structure.
5987  * @param[out] mtr_free
5988  *   Where to put the pointer of a new meter.g.
5989  *
5990  * @return
5991  *   The meter pool pointer and @mtr_free is set on success,
5992  *   NULL otherwise and rte_errno is set.
5993  */
5994 static struct mlx5_aso_mtr_pool *
5995 flow_dv_mtr_pool_create(struct rte_eth_dev *dev,
5996                              struct mlx5_aso_mtr **mtr_free)
5997 {
5998         struct mlx5_priv *priv = dev->data->dev_private;
5999         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6000         struct mlx5_aso_mtr_pool *pool = NULL;
6001         struct mlx5_devx_obj *dcs = NULL;
6002         uint32_t i;
6003         uint32_t log_obj_size;
6004
6005         log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6006         dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->ctx,
6007                         priv->sh->pdn, log_obj_size);
6008         if (!dcs) {
6009                 rte_errno = ENODATA;
6010                 return NULL;
6011         }
6012         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6013         if (!pool) {
6014                 rte_errno = ENOMEM;
6015                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6016                 return NULL;
6017         }
6018         pool->devx_obj = dcs;
6019         pool->index = mtrmng->n_valid;
6020         if (pool->index == mtrmng->n && flow_dv_mtr_container_resize(dev)) {
6021                 mlx5_free(pool);
6022                 claim_zero(mlx5_devx_cmd_destroy(dcs));
6023                 return NULL;
6024         }
6025         mtrmng->pools[pool->index] = pool;
6026         mtrmng->n_valid++;
6027         for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6028                 pool->mtrs[i].offset = i;
6029                 pool->mtrs[i].fm.meter_id = UINT32_MAX;
6030                 LIST_INSERT_HEAD(&mtrmng->meters,
6031                                                 &pool->mtrs[i], next);
6032         }
6033         pool->mtrs[0].offset = 0;
6034         pool->mtrs[0].fm.meter_id = UINT32_MAX;
6035         *mtr_free = &pool->mtrs[0];
6036         return pool;
6037 }
6038
6039 /**
6040  * Release a flow meter into pool.
6041  *
6042  * @param[in] dev
6043  *   Pointer to the Ethernet device structure.
6044  * @param[in] mtr_idx
6045  *   Index to aso flow meter.
6046  */
6047 static void
6048 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6049 {
6050         struct mlx5_priv *priv = dev->data->dev_private;
6051         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6052         struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6053
6054         MLX5_ASSERT(aso_mtr);
6055         rte_spinlock_lock(&mtrmng->mtrsl);
6056         memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6057         aso_mtr->state = ASO_METER_FREE;
6058         aso_mtr->fm.meter_id = UINT32_MAX;
6059         LIST_INSERT_HEAD(&mtrmng->meters, aso_mtr, next);
6060         rte_spinlock_unlock(&mtrmng->mtrsl);
6061 }
6062
6063 /**
6064  * Allocate a aso flow meter.
6065  *
6066  * @param[in] dev
6067  *   Pointer to the Ethernet device structure.
6068  *
6069  * @return
6070  *   Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6071  */
6072 static uint32_t
6073 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6074 {
6075         struct mlx5_priv *priv = dev->data->dev_private;
6076         struct mlx5_aso_mtr *mtr_free = NULL;
6077         struct mlx5_aso_mtr_pools_mng *mtrmng = priv->sh->mtrmng;
6078         struct mlx5_aso_mtr_pool *pool;
6079         uint32_t mtr_idx = 0;
6080
6081         if (!priv->config.devx) {
6082                 rte_errno = ENOTSUP;
6083                 return 0;
6084         }
6085         /* Allocate the flow meter memory. */
6086         /* Get free meters from management. */
6087         rte_spinlock_lock(&mtrmng->mtrsl);
6088         mtr_free = LIST_FIRST(&mtrmng->meters);
6089         if (mtr_free)
6090                 LIST_REMOVE(mtr_free, next);
6091         if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6092                 rte_spinlock_unlock(&mtrmng->mtrsl);
6093                 return 0;
6094         }
6095         mtr_free->state = ASO_METER_WAIT;
6096         rte_spinlock_unlock(&mtrmng->mtrsl);
6097         pool = container_of(mtr_free,
6098                                         struct mlx5_aso_mtr_pool,
6099                                         mtrs[mtr_free->offset]);
6100         mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6101         if (!mtr_free->fm.meter_action) {
6102 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6103                 struct rte_flow_error error;
6104                 uint8_t reg_id;
6105
6106                 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6107                 mtr_free->fm.meter_action =
6108                         mlx5_glue->dv_create_flow_action_aso
6109                                                 (priv->sh->rx_domain,
6110                                                  pool->devx_obj->obj,
6111                                                  mtr_free->offset,
6112                                                  (1 << MLX5_FLOW_COLOR_GREEN),
6113                                                  reg_id - REG_C_0);
6114 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6115                 if (!mtr_free->fm.meter_action) {
6116                         flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6117                         return 0;
6118                 }
6119         }
6120         return mtr_idx;
6121 }
6122
6123 /**
6124  * Verify the @p attributes will be correctly understood by the NIC and store
6125  * them in the @p flow if everything is correct.
6126  *
6127  * @param[in] dev
6128  *   Pointer to dev struct.
6129  * @param[in] attributes
6130  *   Pointer to flow attributes
6131  * @param[in] external
6132  *   This flow rule is created by request external to PMD.
6133  * @param[out] error
6134  *   Pointer to error structure.
6135  *
6136  * @return
6137  *   - 0 on success and non root table.
6138  *   - 1 on success and root table.
6139  *   - a negative errno value otherwise and rte_errno is set.
6140  */
6141 static int
6142 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6143                             const struct mlx5_flow_tunnel *tunnel,
6144                             const struct rte_flow_attr *attributes,
6145                             const struct flow_grp_info *grp_info,
6146                             struct rte_flow_error *error)
6147 {
6148         struct mlx5_priv *priv = dev->data->dev_private;
6149         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6150         int ret = 0;
6151
6152 #ifndef HAVE_MLX5DV_DR
6153         RTE_SET_USED(tunnel);
6154         RTE_SET_USED(grp_info);
6155         if (attributes->group)
6156                 return rte_flow_error_set(error, ENOTSUP,
6157                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6158                                           NULL,
6159                                           "groups are not supported");
6160 #else
6161         uint32_t table = 0;
6162
6163         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6164                                        grp_info, error);
6165         if (ret)
6166                 return ret;
6167         if (!table)
6168                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6169 #endif
6170         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6171             attributes->priority > lowest_priority)
6172                 return rte_flow_error_set(error, ENOTSUP,
6173                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6174                                           NULL,
6175                                           "priority out of range");
6176         if (attributes->transfer) {
6177                 if (!priv->config.dv_esw_en)
6178                         return rte_flow_error_set
6179                                 (error, ENOTSUP,
6180                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6181                                  "E-Switch dr is not supported");
6182                 if (!(priv->representor || priv->master))
6183                         return rte_flow_error_set
6184                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6185                                  NULL, "E-Switch configuration can only be"
6186                                  " done by a master or a representor device");
6187                 if (attributes->egress)
6188                         return rte_flow_error_set
6189                                 (error, ENOTSUP,
6190                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6191                                  "egress is not supported");
6192         }
6193         if (!(attributes->egress ^ attributes->ingress))
6194                 return rte_flow_error_set(error, ENOTSUP,
6195                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6196                                           "must specify exactly one of "
6197                                           "ingress or egress");
6198         return ret;
6199 }
6200
6201 /**
6202  * Internal validation function. For validating both actions and items.
6203  *
6204  * @param[in] dev
6205  *   Pointer to the rte_eth_dev structure.
6206  * @param[in] attr
6207  *   Pointer to the flow attributes.
6208  * @param[in] items
6209  *   Pointer to the list of items.
6210  * @param[in] actions
6211  *   Pointer to the list of actions.
6212  * @param[in] external
6213  *   This flow rule is created by request external to PMD.
6214  * @param[in] hairpin
6215  *   Number of hairpin TX actions, 0 means classic flow.
6216  * @param[out] error
6217  *   Pointer to the error structure.
6218  *
6219  * @return
6220  *   0 on success, a negative errno value otherwise and rte_errno is set.
6221  */
6222 static int
6223 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6224                  const struct rte_flow_item items[],
6225                  const struct rte_flow_action actions[],
6226                  bool external, int hairpin, struct rte_flow_error *error)
6227 {
6228         int ret;
6229         uint64_t action_flags = 0;
6230         uint64_t item_flags = 0;
6231         uint64_t last_item = 0;
6232         uint8_t next_protocol = 0xff;
6233         uint16_t ether_type = 0;
6234         int actions_n = 0;
6235         uint8_t item_ipv6_proto = 0;
6236         int fdb_mirror_limit = 0;
6237         int modify_after_mirror = 0;
6238         const struct rte_flow_item *geneve_item = NULL;
6239         const struct rte_flow_item *gre_item = NULL;
6240         const struct rte_flow_item *gtp_item = NULL;
6241         const struct rte_flow_action_raw_decap *decap;
6242         const struct rte_flow_action_raw_encap *encap;
6243         const struct rte_flow_action_rss *rss = NULL;
6244         const struct rte_flow_action_rss *sample_rss = NULL;
6245         const struct rte_flow_action_count *count = NULL;
6246         const struct rte_flow_action_count *sample_count = NULL;
6247         const struct rte_flow_item_tcp nic_tcp_mask = {
6248                 .hdr = {
6249                         .tcp_flags = 0xFF,
6250                         .src_port = RTE_BE16(UINT16_MAX),
6251                         .dst_port = RTE_BE16(UINT16_MAX),
6252                 }
6253         };
6254         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6255                 .hdr = {
6256                         .src_addr =
6257                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6258                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6259                         .dst_addr =
6260                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6261                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6262                         .vtc_flow = RTE_BE32(0xffffffff),
6263                         .proto = 0xff,
6264                         .hop_limits = 0xff,
6265                 },
6266                 .has_frag_ext = 1,
6267         };
6268         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6269                 .hdr = {
6270                         .common = {
6271                                 .u32 =
6272                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6273                                         .type = 0xFF,
6274                                         }).u32),
6275                         },
6276                         .dummy[0] = 0xffffffff,
6277                 },
6278         };
6279         struct mlx5_priv *priv = dev->data->dev_private;
6280         struct mlx5_dev_config *dev_conf = &priv->config;
6281         uint16_t queue_index = 0xFFFF;
6282         const struct rte_flow_item_vlan *vlan_m = NULL;
6283         uint32_t rw_act_num = 0;
6284         uint64_t is_root;
6285         const struct mlx5_flow_tunnel *tunnel;
6286         struct flow_grp_info grp_info = {
6287                 .external = !!external,
6288                 .transfer = !!attr->transfer,
6289                 .fdb_def_rule = !!priv->fdb_def_rule,
6290         };
6291         const struct rte_eth_hairpin_conf *conf;
6292
6293         if (items == NULL)
6294                 return -1;
6295         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6296                 tunnel = flow_items_to_tunnel(items);
6297                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6298                                 MLX5_FLOW_ACTION_DECAP;
6299         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6300                 tunnel = flow_actions_to_tunnel(actions);
6301                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6302         } else {
6303                 tunnel = NULL;
6304         }
6305         if (tunnel && priv->representor)
6306                 return rte_flow_error_set(error, ENOTSUP,
6307                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6308                                           "decap not supported "
6309                                           "for VF representor");
6310         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6311                                 (dev, tunnel, attr, items, actions);
6312         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6313         if (ret < 0)
6314                 return ret;
6315         is_root = (uint64_t)ret;
6316         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6317                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6318                 int type = items->type;
6319
6320                 if (!mlx5_flow_os_item_supported(type))
6321                         return rte_flow_error_set(error, ENOTSUP,
6322                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6323                                                   NULL, "item not supported");
6324                 switch (type) {
6325                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6326                         if (items[0].type != (typeof(items[0].type))
6327                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6328                                 return rte_flow_error_set
6329                                                 (error, EINVAL,
6330                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6331                                                 NULL, "MLX5 private items "
6332                                                 "must be the first");
6333                         break;
6334                 case RTE_FLOW_ITEM_TYPE_VOID:
6335                         break;
6336                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6337                         ret = flow_dv_validate_item_port_id
6338                                         (dev, items, attr, item_flags, error);
6339                         if (ret < 0)
6340                                 return ret;
6341                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6342                         break;
6343                 case RTE_FLOW_ITEM_TYPE_ETH:
6344                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6345                                                           true, error);
6346                         if (ret < 0)
6347                                 return ret;
6348                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6349                                              MLX5_FLOW_LAYER_OUTER_L2;
6350                         if (items->mask != NULL && items->spec != NULL) {
6351                                 ether_type =
6352                                         ((const struct rte_flow_item_eth *)
6353                                          items->spec)->type;
6354                                 ether_type &=
6355                                         ((const struct rte_flow_item_eth *)
6356                                          items->mask)->type;
6357                                 ether_type = rte_be_to_cpu_16(ether_type);
6358                         } else {
6359                                 ether_type = 0;
6360                         }
6361                         break;
6362                 case RTE_FLOW_ITEM_TYPE_VLAN:
6363                         ret = flow_dv_validate_item_vlan(items, item_flags,
6364                                                          dev, error);
6365                         if (ret < 0)
6366                                 return ret;
6367                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6368                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6369                         if (items->mask != NULL && items->spec != NULL) {
6370                                 ether_type =
6371                                         ((const struct rte_flow_item_vlan *)
6372                                          items->spec)->inner_type;
6373                                 ether_type &=
6374                                         ((const struct rte_flow_item_vlan *)
6375                                          items->mask)->inner_type;
6376                                 ether_type = rte_be_to_cpu_16(ether_type);
6377                         } else {
6378                                 ether_type = 0;
6379                         }
6380                         /* Store outer VLAN mask for of_push_vlan action. */
6381                         if (!tunnel)
6382                                 vlan_m = items->mask;
6383                         break;
6384                 case RTE_FLOW_ITEM_TYPE_IPV4:
6385                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6386                                                   &item_flags, &tunnel);
6387                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6388                                                          last_item, ether_type,
6389                                                          error);
6390                         if (ret < 0)
6391                                 return ret;
6392                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6393                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6394                         if (items->mask != NULL &&
6395                             ((const struct rte_flow_item_ipv4 *)
6396                              items->mask)->hdr.next_proto_id) {
6397                                 next_protocol =
6398                                         ((const struct rte_flow_item_ipv4 *)
6399                                          (items->spec))->hdr.next_proto_id;
6400                                 next_protocol &=
6401                                         ((const struct rte_flow_item_ipv4 *)
6402                                          (items->mask))->hdr.next_proto_id;
6403                         } else {
6404                                 /* Reset for inner layer. */
6405                                 next_protocol = 0xff;
6406                         }
6407                         break;
6408                 case RTE_FLOW_ITEM_TYPE_IPV6:
6409                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6410                                                   &item_flags, &tunnel);
6411                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6412                                                            last_item,
6413                                                            ether_type,
6414                                                            &nic_ipv6_mask,
6415                                                            error);
6416                         if (ret < 0)
6417                                 return ret;
6418                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6419                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6420                         if (items->mask != NULL &&
6421                             ((const struct rte_flow_item_ipv6 *)
6422                              items->mask)->hdr.proto) {
6423                                 item_ipv6_proto =
6424                                         ((const struct rte_flow_item_ipv6 *)
6425                                          items->spec)->hdr.proto;
6426                                 next_protocol =
6427                                         ((const struct rte_flow_item_ipv6 *)
6428                                          items->spec)->hdr.proto;
6429                                 next_protocol &=
6430                                         ((const struct rte_flow_item_ipv6 *)
6431                                          items->mask)->hdr.proto;
6432                         } else {
6433                                 /* Reset for inner layer. */
6434                                 next_protocol = 0xff;
6435                         }
6436                         break;
6437                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6438                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6439                                                                   item_flags,
6440                                                                   error);
6441                         if (ret < 0)
6442                                 return ret;
6443                         last_item = tunnel ?
6444                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6445                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6446                         if (items->mask != NULL &&
6447                             ((const struct rte_flow_item_ipv6_frag_ext *)
6448                              items->mask)->hdr.next_header) {
6449                                 next_protocol =
6450                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6451                                  items->spec)->hdr.next_header;
6452                                 next_protocol &=
6453                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6454                                  items->mask)->hdr.next_header;
6455                         } else {
6456                                 /* Reset for inner layer. */
6457                                 next_protocol = 0xff;
6458                         }
6459                         break;
6460                 case RTE_FLOW_ITEM_TYPE_TCP:
6461                         ret = mlx5_flow_validate_item_tcp
6462                                                 (items, item_flags,
6463                                                  next_protocol,
6464                                                  &nic_tcp_mask,
6465                                                  error);
6466                         if (ret < 0)
6467                                 return ret;
6468                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6469                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6470                         break;
6471                 case RTE_FLOW_ITEM_TYPE_UDP:
6472                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6473                                                           next_protocol,
6474                                                           error);
6475                         if (ret < 0)
6476                                 return ret;
6477                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6478                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6479                         break;
6480                 case RTE_FLOW_ITEM_TYPE_GRE:
6481                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6482                                                           next_protocol, error);
6483                         if (ret < 0)
6484                                 return ret;
6485                         gre_item = items;
6486                         last_item = MLX5_FLOW_LAYER_GRE;
6487                         break;
6488                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6489                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6490                                                             next_protocol,
6491                                                             error);
6492                         if (ret < 0)
6493                                 return ret;
6494                         last_item = MLX5_FLOW_LAYER_NVGRE;
6495                         break;
6496                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6497                         ret = mlx5_flow_validate_item_gre_key
6498                                 (items, item_flags, gre_item, error);
6499                         if (ret < 0)
6500                                 return ret;
6501                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6502                         break;
6503                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6504                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6505                                                             error);
6506                         if (ret < 0)
6507                                 return ret;
6508                         last_item = MLX5_FLOW_LAYER_VXLAN;
6509                         break;
6510                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6511                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6512                                                                 item_flags, dev,
6513                                                                 error);
6514                         if (ret < 0)
6515                                 return ret;
6516                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6517                         break;
6518                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6519                         ret = mlx5_flow_validate_item_geneve(items,
6520                                                              item_flags, dev,
6521                                                              error);
6522                         if (ret < 0)
6523                                 return ret;
6524                         geneve_item = items;
6525                         last_item = MLX5_FLOW_LAYER_GENEVE;
6526                         break;
6527                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6528                         ret = mlx5_flow_validate_item_geneve_opt(items,
6529                                                                  last_item,
6530                                                                  geneve_item,
6531                                                                  dev,
6532                                                                  error);
6533                         if (ret < 0)
6534                                 return ret;
6535                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6536                         break;
6537                 case RTE_FLOW_ITEM_TYPE_MPLS:
6538                         ret = mlx5_flow_validate_item_mpls(dev, items,
6539                                                            item_flags,
6540                                                            last_item, error);
6541                         if (ret < 0)
6542                                 return ret;
6543                         last_item = MLX5_FLOW_LAYER_MPLS;
6544                         break;
6545
6546                 case RTE_FLOW_ITEM_TYPE_MARK:
6547                         ret = flow_dv_validate_item_mark(dev, items, attr,
6548                                                          error);
6549                         if (ret < 0)
6550                                 return ret;
6551                         last_item = MLX5_FLOW_ITEM_MARK;
6552                         break;
6553                 case RTE_FLOW_ITEM_TYPE_META:
6554                         ret = flow_dv_validate_item_meta(dev, items, attr,
6555                                                          error);
6556                         if (ret < 0)
6557                                 return ret;
6558                         last_item = MLX5_FLOW_ITEM_METADATA;
6559                         break;
6560                 case RTE_FLOW_ITEM_TYPE_ICMP:
6561                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6562                                                            next_protocol,
6563                                                            error);
6564                         if (ret < 0)
6565                                 return ret;
6566                         last_item = MLX5_FLOW_LAYER_ICMP;
6567                         break;
6568                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6569                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6570                                                             next_protocol,
6571                                                             error);
6572                         if (ret < 0)
6573                                 return ret;
6574                         item_ipv6_proto = IPPROTO_ICMPV6;
6575                         last_item = MLX5_FLOW_LAYER_ICMP6;
6576                         break;
6577                 case RTE_FLOW_ITEM_TYPE_TAG:
6578                         ret = flow_dv_validate_item_tag(dev, items,
6579                                                         attr, error);
6580                         if (ret < 0)
6581                                 return ret;
6582                         last_item = MLX5_FLOW_ITEM_TAG;
6583                         break;
6584                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6585                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6586                         break;
6587                 case RTE_FLOW_ITEM_TYPE_GTP:
6588                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6589                                                         error);
6590                         if (ret < 0)
6591                                 return ret;
6592                         gtp_item = items;
6593                         last_item = MLX5_FLOW_LAYER_GTP;
6594                         break;
6595                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6596                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6597                                                             gtp_item, attr,
6598                                                             error);
6599                         if (ret < 0)
6600                                 return ret;
6601                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6602                         break;
6603                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6604                         /* Capacity will be checked in the translate stage. */
6605                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6606                                                             last_item,
6607                                                             ether_type,
6608                                                             &nic_ecpri_mask,
6609                                                             error);
6610                         if (ret < 0)
6611                                 return ret;
6612                         last_item = MLX5_FLOW_LAYER_ECPRI;
6613                         break;
6614                 default:
6615                         return rte_flow_error_set(error, ENOTSUP,
6616                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6617                                                   NULL, "item not supported");
6618                 }
6619                 item_flags |= last_item;
6620         }
6621         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6622                 int type = actions->type;
6623
6624                 if (!mlx5_flow_os_action_supported(type))
6625                         return rte_flow_error_set(error, ENOTSUP,
6626                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6627                                                   actions,
6628                                                   "action not supported");
6629                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6630                         return rte_flow_error_set(error, ENOTSUP,
6631                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6632                                                   actions, "too many actions");
6633                 switch (type) {
6634                 case RTE_FLOW_ACTION_TYPE_VOID:
6635                         break;
6636                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6637                         ret = flow_dv_validate_action_port_id(dev,
6638                                                               action_flags,
6639                                                               actions,
6640                                                               attr,
6641                                                               error);
6642                         if (ret)
6643                                 return ret;
6644                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6645                         ++actions_n;
6646                         break;
6647                 case RTE_FLOW_ACTION_TYPE_FLAG:
6648                         ret = flow_dv_validate_action_flag(dev, action_flags,
6649                                                            attr, error);
6650                         if (ret < 0)
6651                                 return ret;
6652                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6653                                 /* Count all modify-header actions as one. */
6654                                 if (!(action_flags &
6655                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6656                                         ++actions_n;
6657                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6658                                                 MLX5_FLOW_ACTION_MARK_EXT;
6659                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6660                                         modify_after_mirror = 1;
6661
6662                         } else {
6663                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6664                                 ++actions_n;
6665                         }
6666                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6667                         break;
6668                 case RTE_FLOW_ACTION_TYPE_MARK:
6669                         ret = flow_dv_validate_action_mark(dev, actions,
6670                                                            action_flags,
6671                                                            attr, error);
6672                         if (ret < 0)
6673                                 return ret;
6674                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6675                                 /* Count all modify-header actions as one. */
6676                                 if (!(action_flags &
6677                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6678                                         ++actions_n;
6679                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6680                                                 MLX5_FLOW_ACTION_MARK_EXT;
6681                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6682                                         modify_after_mirror = 1;
6683                         } else {
6684                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6685                                 ++actions_n;
6686                         }
6687                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6688                         break;
6689                 case RTE_FLOW_ACTION_TYPE_SET_META:
6690                         ret = flow_dv_validate_action_set_meta(dev, actions,
6691                                                                action_flags,
6692                                                                attr, error);
6693                         if (ret < 0)
6694                                 return ret;
6695                         /* Count all modify-header actions as one action. */
6696                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6697                                 ++actions_n;
6698                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6699                                 modify_after_mirror = 1;
6700                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6701                         rw_act_num += MLX5_ACT_NUM_SET_META;
6702                         break;
6703                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6704                         ret = flow_dv_validate_action_set_tag(dev, actions,
6705                                                               action_flags,
6706                                                               attr, error);
6707                         if (ret < 0)
6708                                 return ret;
6709                         /* Count all modify-header actions as one action. */
6710                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6711                                 ++actions_n;
6712                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6713                                 modify_after_mirror = 1;
6714                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6715                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6716                         break;
6717                 case RTE_FLOW_ACTION_TYPE_DROP:
6718                         ret = mlx5_flow_validate_action_drop(action_flags,
6719                                                              attr, error);
6720                         if (ret < 0)
6721                                 return ret;
6722                         action_flags |= MLX5_FLOW_ACTION_DROP;
6723                         ++actions_n;
6724                         break;
6725                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6726                         ret = mlx5_flow_validate_action_queue(actions,
6727                                                               action_flags, dev,
6728                                                               attr, error);
6729                         if (ret < 0)
6730                                 return ret;
6731                         queue_index = ((const struct rte_flow_action_queue *)
6732                                                         (actions->conf))->index;
6733                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6734                         ++actions_n;
6735                         break;
6736                 case RTE_FLOW_ACTION_TYPE_RSS:
6737                         rss = actions->conf;
6738                         ret = mlx5_flow_validate_action_rss(actions,
6739                                                             action_flags, dev,
6740                                                             attr, item_flags,
6741                                                             error);
6742                         if (ret < 0)
6743                                 return ret;
6744                         if (rss && sample_rss &&
6745                             (sample_rss->level != rss->level ||
6746                             sample_rss->types != rss->types))
6747                                 return rte_flow_error_set(error, ENOTSUP,
6748                                         RTE_FLOW_ERROR_TYPE_ACTION,
6749                                         NULL,
6750                                         "Can't use the different RSS types "
6751                                         "or level in the same flow");
6752                         if (rss != NULL && rss->queue_num)
6753                                 queue_index = rss->queue[0];
6754                         action_flags |= MLX5_FLOW_ACTION_RSS;
6755                         ++actions_n;
6756                         break;
6757                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6758                         ret =
6759                         mlx5_flow_validate_action_default_miss(action_flags,
6760                                         attr, error);
6761                         if (ret < 0)
6762                                 return ret;
6763                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6764                         ++actions_n;
6765                         break;
6766                 case RTE_FLOW_ACTION_TYPE_COUNT:
6767                         ret = flow_dv_validate_action_count(dev, actions,
6768                                                             action_flags,
6769                                                             error);
6770                         if (ret < 0)
6771                                 return ret;
6772                         count = actions->conf;
6773                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6774                         ++actions_n;
6775                         break;
6776                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6777                         if (flow_dv_validate_action_pop_vlan(dev,
6778                                                              action_flags,
6779                                                              actions,
6780                                                              item_flags, attr,
6781                                                              error))
6782                                 return -rte_errno;
6783                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6784                                 modify_after_mirror = 1;
6785                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6786                         ++actions_n;
6787                         break;
6788                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6789                         ret = flow_dv_validate_action_push_vlan(dev,
6790                                                                 action_flags,
6791                                                                 vlan_m,
6792                                                                 actions, attr,
6793                                                                 error);
6794                         if (ret < 0)
6795                                 return ret;
6796                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6797                                 modify_after_mirror = 1;
6798                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6799                         ++actions_n;
6800                         break;
6801                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6802                         ret = flow_dv_validate_action_set_vlan_pcp
6803                                                 (action_flags, actions, error);
6804                         if (ret < 0)
6805                                 return ret;
6806                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6807                                 modify_after_mirror = 1;
6808                         /* Count PCP with push_vlan command. */
6809                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6810                         break;
6811                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6812                         ret = flow_dv_validate_action_set_vlan_vid
6813                                                 (item_flags, action_flags,
6814                                                  actions, error);
6815                         if (ret < 0)
6816                                 return ret;
6817                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6818                                 modify_after_mirror = 1;
6819                         /* Count VID with push_vlan command. */
6820                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6821                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6822                         break;
6823                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6824                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6825                         ret = flow_dv_validate_action_l2_encap(dev,
6826                                                                action_flags,
6827                                                                actions, attr,
6828                                                                error);
6829                         if (ret < 0)
6830                                 return ret;
6831                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6832                         ++actions_n;
6833                         break;
6834                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6835                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6836                         ret = flow_dv_validate_action_decap(dev, action_flags,
6837                                                             actions, item_flags,
6838                                                             attr, error);
6839                         if (ret < 0)
6840                                 return ret;
6841                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6842                                 modify_after_mirror = 1;
6843                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6844                         ++actions_n;
6845                         break;
6846                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6847                         ret = flow_dv_validate_action_raw_encap_decap
6848                                 (dev, NULL, actions->conf, attr, &action_flags,
6849                                  &actions_n, actions, item_flags, error);
6850                         if (ret < 0)
6851                                 return ret;
6852                         break;
6853                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6854                         decap = actions->conf;
6855                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6856                                 ;
6857                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6858                                 encap = NULL;
6859                                 actions--;
6860                         } else {
6861                                 encap = actions->conf;
6862                         }
6863                         ret = flow_dv_validate_action_raw_encap_decap
6864                                            (dev,
6865                                             decap ? decap : &empty_decap, encap,
6866                                             attr, &action_flags, &actions_n,
6867                                             actions, item_flags, error);
6868                         if (ret < 0)
6869                                 return ret;
6870                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6871                             (action_flags & MLX5_FLOW_ACTION_DECAP))
6872                                 modify_after_mirror = 1;
6873                         break;
6874                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6875                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6876                         ret = flow_dv_validate_action_modify_mac(action_flags,
6877                                                                  actions,
6878                                                                  item_flags,
6879                                                                  error);
6880                         if (ret < 0)
6881                                 return ret;
6882                         /* Count all modify-header actions as one action. */
6883                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6884                                 ++actions_n;
6885                         action_flags |= actions->type ==
6886                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6887                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6888                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6889                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6890                                 modify_after_mirror = 1;
6891                         /*
6892                          * Even if the source and destination MAC addresses have
6893                          * overlap in the header with 4B alignment, the convert
6894                          * function will handle them separately and 4 SW actions
6895                          * will be created. And 2 actions will be added each
6896                          * time no matter how many bytes of address will be set.
6897                          */
6898                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6899                         break;
6900                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6901                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6902                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6903                                                                   actions,
6904                                                                   item_flags,
6905                                                                   error);
6906                         if (ret < 0)
6907                                 return ret;
6908                         /* Count all modify-header actions as one action. */
6909                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6910                                 ++actions_n;
6911                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6912                                 modify_after_mirror = 1;
6913                         action_flags |= actions->type ==
6914                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6915                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6916                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6917                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6918                         break;
6919                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6920                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6921                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6922                                                                   actions,
6923                                                                   item_flags,
6924                                                                   error);
6925                         if (ret < 0)
6926                                 return ret;
6927                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6928                                 return rte_flow_error_set(error, ENOTSUP,
6929                                         RTE_FLOW_ERROR_TYPE_ACTION,
6930                                         actions,
6931                                         "Can't change header "
6932                                         "with ICMPv6 proto");
6933                         /* Count all modify-header actions as one action. */
6934                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6935                                 ++actions_n;
6936                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6937                                 modify_after_mirror = 1;
6938                         action_flags |= actions->type ==
6939                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6940                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6941                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6942                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6943                         break;
6944                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6945                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6946                         ret = flow_dv_validate_action_modify_tp(action_flags,
6947                                                                 actions,
6948                                                                 item_flags,
6949                                                                 error);
6950                         if (ret < 0)
6951                                 return ret;
6952                         /* Count all modify-header actions as one action. */
6953                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6954                                 ++actions_n;
6955                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6956                                 modify_after_mirror = 1;
6957                         action_flags |= actions->type ==
6958                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6959                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6960                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6961                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6962                         break;
6963                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6964                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6965                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6966                                                                  actions,
6967                                                                  item_flags,
6968                                                                  error);
6969                         if (ret < 0)
6970                                 return ret;
6971                         /* Count all modify-header actions as one action. */
6972                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6973                                 ++actions_n;
6974                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6975                                 modify_after_mirror = 1;
6976                         action_flags |= actions->type ==
6977                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6978                                                 MLX5_FLOW_ACTION_SET_TTL :
6979                                                 MLX5_FLOW_ACTION_DEC_TTL;
6980                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6981                         break;
6982                 case RTE_FLOW_ACTION_TYPE_JUMP:
6983                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6984                                                            action_flags,
6985                                                            attr, external,
6986                                                            error);
6987                         if (ret)
6988                                 return ret;
6989                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6990                             fdb_mirror_limit)
6991                                 return rte_flow_error_set(error, EINVAL,
6992                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6993                                                   NULL,
6994                                                   "sample and jump action combination is not supported");
6995                         ++actions_n;
6996                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6997                         break;
6998                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6999                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7000                         ret = flow_dv_validate_action_modify_tcp_seq
7001                                                                 (action_flags,
7002                                                                  actions,
7003                                                                  item_flags,
7004                                                                  error);
7005                         if (ret < 0)
7006                                 return ret;
7007                         /* Count all modify-header actions as one action. */
7008                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7009                                 ++actions_n;
7010                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7011                                 modify_after_mirror = 1;
7012                         action_flags |= actions->type ==
7013                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7014                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7015                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7016                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7017                         break;
7018                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7019                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7020                         ret = flow_dv_validate_action_modify_tcp_ack
7021                                                                 (action_flags,
7022                                                                  actions,
7023                                                                  item_flags,
7024                                                                  error);
7025                         if (ret < 0)
7026                                 return ret;
7027                         /* Count all modify-header actions as one action. */
7028                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7029                                 ++actions_n;
7030                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7031                                 modify_after_mirror = 1;
7032                         action_flags |= actions->type ==
7033                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7034                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
7035                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7036                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7037                         break;
7038                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7039                         break;
7040                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7041                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7042                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7043                         break;
7044                 case RTE_FLOW_ACTION_TYPE_METER:
7045                         ret = mlx5_flow_validate_action_meter(dev,
7046                                                               action_flags,
7047                                                               actions, attr,
7048                                                               error);
7049                         if (ret < 0)
7050                                 return ret;
7051                         action_flags |= MLX5_FLOW_ACTION_METER;
7052                         ++actions_n;
7053                         /* Meter action will add one more TAG action. */
7054                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
7055                         break;
7056                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7057                         if (!attr->transfer && !attr->group)
7058                                 return rte_flow_error_set(error, ENOTSUP,
7059                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7060                                                                            NULL,
7061                           "Shared ASO age action is not supported for group 0");
7062                         action_flags |= MLX5_FLOW_ACTION_AGE;
7063                         ++actions_n;
7064                         break;
7065                 case RTE_FLOW_ACTION_TYPE_AGE:
7066                         ret = flow_dv_validate_action_age(action_flags,
7067                                                           actions, dev,
7068                                                           error);
7069                         if (ret < 0)
7070                                 return ret;
7071                         /*
7072                          * Validate the regular AGE action (using counter)
7073                          * mutual exclusion with share counter actions.
7074                          */
7075                         if (!priv->sh->flow_hit_aso_en) {
7076                                 if (count && count->shared)
7077                                         return rte_flow_error_set
7078                                                 (error, EINVAL,
7079                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7080                                                 NULL,
7081                                                 "old age and shared count combination is not supported");
7082                                 if (sample_count)
7083                                         return rte_flow_error_set
7084                                                 (error, EINVAL,
7085                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7086                                                 NULL,
7087                                                 "old age action and count must be in the same sub flow");
7088                         }
7089                         action_flags |= MLX5_FLOW_ACTION_AGE;
7090                         ++actions_n;
7091                         break;
7092                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7093                         ret = flow_dv_validate_action_modify_ipv4_dscp
7094                                                          (action_flags,
7095                                                           actions,
7096                                                           item_flags,
7097                                                           error);
7098                         if (ret < 0)
7099                                 return ret;
7100                         /* Count all modify-header actions as one action. */
7101                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7102                                 ++actions_n;
7103                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7104                                 modify_after_mirror = 1;
7105                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7106                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7107                         break;
7108                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7109                         ret = flow_dv_validate_action_modify_ipv6_dscp
7110                                                                 (action_flags,
7111                                                                  actions,
7112                                                                  item_flags,
7113                                                                  error);
7114                         if (ret < 0)
7115                                 return ret;
7116                         /* Count all modify-header actions as one action. */
7117                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7118                                 ++actions_n;
7119                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7120                                 modify_after_mirror = 1;
7121                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7122                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7123                         break;
7124                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7125                         ret = flow_dv_validate_action_sample(&action_flags,
7126                                                              actions, dev,
7127                                                              attr, item_flags,
7128                                                              rss, &sample_rss,
7129                                                              &sample_count,
7130                                                              &fdb_mirror_limit,
7131                                                              error);
7132                         if (ret < 0)
7133                                 return ret;
7134                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7135                         ++actions_n;
7136                         break;
7137                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7138                         if (actions[0].type != (typeof(actions[0].type))
7139                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
7140                                 return rte_flow_error_set
7141                                                 (error, EINVAL,
7142                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7143                                                 NULL, "MLX5 private action "
7144                                                 "must be the first");
7145
7146                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
7147                         break;
7148                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7149                         ret = flow_dv_validate_action_modify_field(dev,
7150                                                                    action_flags,
7151                                                                    actions,
7152                                                                    attr,
7153                                                                    error);
7154                         if (ret < 0)
7155                                 return ret;
7156                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7157                                 modify_after_mirror = 1;
7158                         /* Count all modify-header actions as one action. */
7159                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
7160                                 ++actions_n;
7161                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7162                         rw_act_num += ret;
7163                         break;
7164                 default:
7165                         return rte_flow_error_set(error, ENOTSUP,
7166                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7167                                                   actions,
7168                                                   "action not supported");
7169                 }
7170         }
7171         /*
7172          * Validate actions in flow rules
7173          * - Explicit decap action is prohibited by the tunnel offload API.
7174          * - Drop action in tunnel steer rule is prohibited by the API.
7175          * - Application cannot use MARK action because it's value can mask
7176          *   tunnel default miss nitification.
7177          * - JUMP in tunnel match rule has no support in current PMD
7178          *   implementation.
7179          * - TAG & META are reserved for future uses.
7180          */
7181         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7182                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
7183                                             MLX5_FLOW_ACTION_MARK     |
7184                                             MLX5_FLOW_ACTION_SET_TAG  |
7185                                             MLX5_FLOW_ACTION_SET_META |
7186                                             MLX5_FLOW_ACTION_DROP;
7187
7188                 if (action_flags & bad_actions_mask)
7189                         return rte_flow_error_set
7190                                         (error, EINVAL,
7191                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7192                                         "Invalid RTE action in tunnel "
7193                                         "set decap rule");
7194                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7195                         return rte_flow_error_set
7196                                         (error, EINVAL,
7197                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7198                                         "tunnel set decap rule must terminate "
7199                                         "with JUMP");
7200                 if (!attr->ingress)
7201                         return rte_flow_error_set
7202                                         (error, EINVAL,
7203                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7204                                         "tunnel flows for ingress traffic only");
7205         }
7206         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7207                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7208                                             MLX5_FLOW_ACTION_MARK    |
7209                                             MLX5_FLOW_ACTION_SET_TAG |
7210                                             MLX5_FLOW_ACTION_SET_META;
7211
7212                 if (action_flags & bad_actions_mask)
7213                         return rte_flow_error_set
7214                                         (error, EINVAL,
7215                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7216                                         "Invalid RTE action in tunnel "
7217                                         "set match rule");
7218         }
7219         /*
7220          * Validate the drop action mutual exclusion with other actions.
7221          * Drop action is mutually-exclusive with any other action, except for
7222          * Count action.
7223          * Drop action compatibility with tunnel offload was already validated.
7224          */
7225         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7226                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7227         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7228             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7229                 return rte_flow_error_set(error, EINVAL,
7230                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7231                                           "Drop action is mutually-exclusive "
7232                                           "with any other action, except for "
7233                                           "Count action");
7234         /* Eswitch has few restrictions on using items and actions */
7235         if (attr->transfer) {
7236                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7237                     action_flags & MLX5_FLOW_ACTION_FLAG)
7238                         return rte_flow_error_set(error, ENOTSUP,
7239                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7240                                                   NULL,
7241                                                   "unsupported action FLAG");
7242                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7243                     action_flags & MLX5_FLOW_ACTION_MARK)
7244                         return rte_flow_error_set(error, ENOTSUP,
7245                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7246                                                   NULL,
7247                                                   "unsupported action MARK");
7248                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7249                         return rte_flow_error_set(error, ENOTSUP,
7250                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7251                                                   NULL,
7252                                                   "unsupported action QUEUE");
7253                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7254                         return rte_flow_error_set(error, ENOTSUP,
7255                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7256                                                   NULL,
7257                                                   "unsupported action RSS");
7258                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7259                         return rte_flow_error_set(error, EINVAL,
7260                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7261                                                   actions,
7262                                                   "no fate action is found");
7263         } else {
7264                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7265                         return rte_flow_error_set(error, EINVAL,
7266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7267                                                   actions,
7268                                                   "no fate action is found");
7269         }
7270         /*
7271          * Continue validation for Xcap and VLAN actions.
7272          * If hairpin is working in explicit TX rule mode, there is no actions
7273          * splitting and the validation of hairpin ingress flow should be the
7274          * same as other standard flows.
7275          */
7276         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7277                              MLX5_FLOW_VLAN_ACTIONS)) &&
7278             (queue_index == 0xFFFF ||
7279              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7280              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7281              conf->tx_explicit != 0))) {
7282                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7283                     MLX5_FLOW_XCAP_ACTIONS)
7284                         return rte_flow_error_set(error, ENOTSUP,
7285                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7286                                                   NULL, "encap and decap "
7287                                                   "combination aren't supported");
7288                 if (!attr->transfer && attr->ingress) {
7289                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7290                                 return rte_flow_error_set
7291                                                 (error, ENOTSUP,
7292                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7293                                                  NULL, "encap is not supported"
7294                                                  " for ingress traffic");
7295                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7296                                 return rte_flow_error_set
7297                                                 (error, ENOTSUP,
7298                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7299                                                  NULL, "push VLAN action not "
7300                                                  "supported for ingress");
7301                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7302                                         MLX5_FLOW_VLAN_ACTIONS)
7303                                 return rte_flow_error_set
7304                                                 (error, ENOTSUP,
7305                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7306                                                  NULL, "no support for "
7307                                                  "multiple VLAN actions");
7308                 }
7309         }
7310         /*
7311          * Hairpin flow will add one more TAG action in TX implicit mode.
7312          * In TX explicit mode, there will be no hairpin flow ID.
7313          */
7314         if (hairpin > 0)
7315                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7316         /* extra metadata enabled: one more TAG action will be add. */
7317         if (dev_conf->dv_flow_en &&
7318             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7319             mlx5_flow_ext_mreg_supported(dev))
7320                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7321         if (rw_act_num >
7322                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7323                 return rte_flow_error_set(error, ENOTSUP,
7324                                           RTE_FLOW_ERROR_TYPE_ACTION,
7325                                           NULL, "too many header modify"
7326                                           " actions to support");
7327         }
7328         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7329         if (fdb_mirror_limit && modify_after_mirror)
7330                 return rte_flow_error_set(error, EINVAL,
7331                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7332                                 "sample before modify action is not supported");
7333         return 0;
7334 }
7335
7336 /**
7337  * Internal preparation function. Allocates the DV flow size,
7338  * this size is constant.
7339  *
7340  * @param[in] dev
7341  *   Pointer to the rte_eth_dev structure.
7342  * @param[in] attr
7343  *   Pointer to the flow attributes.
7344  * @param[in] items
7345  *   Pointer to the list of items.
7346  * @param[in] actions
7347  *   Pointer to the list of actions.
7348  * @param[out] error
7349  *   Pointer to the error structure.
7350  *
7351  * @return
7352  *   Pointer to mlx5_flow object on success,
7353  *   otherwise NULL and rte_errno is set.
7354  */
7355 static struct mlx5_flow *
7356 flow_dv_prepare(struct rte_eth_dev *dev,
7357                 const struct rte_flow_attr *attr __rte_unused,
7358                 const struct rte_flow_item items[] __rte_unused,
7359                 const struct rte_flow_action actions[] __rte_unused,
7360                 struct rte_flow_error *error)
7361 {
7362         uint32_t handle_idx = 0;
7363         struct mlx5_flow *dev_flow;
7364         struct mlx5_flow_handle *dev_handle;
7365         struct mlx5_priv *priv = dev->data->dev_private;
7366         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7367
7368         MLX5_ASSERT(wks);
7369         /* In case of corrupting the memory. */
7370         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7371                 rte_flow_error_set(error, ENOSPC,
7372                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7373                                    "not free temporary device flow");
7374                 return NULL;
7375         }
7376         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7377                                    &handle_idx);
7378         if (!dev_handle) {
7379                 rte_flow_error_set(error, ENOMEM,
7380                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7381                                    "not enough memory to create flow handle");
7382                 return NULL;
7383         }
7384         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7385         dev_flow = &wks->flows[wks->flow_idx++];
7386         memset(dev_flow, 0, sizeof(*dev_flow));
7387         dev_flow->handle = dev_handle;
7388         dev_flow->handle_idx = handle_idx;
7389         /*
7390          * In some old rdma-core releases, before continuing, a check of the
7391          * length of matching parameter will be done at first. It needs to use
7392          * the length without misc4 param. If the flow has misc4 support, then
7393          * the length needs to be adjusted accordingly. Each param member is
7394          * aligned with a 64B boundary naturally.
7395          */
7396         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7397                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7398         dev_flow->ingress = attr->ingress;
7399         dev_flow->dv.transfer = attr->transfer;
7400         return dev_flow;
7401 }
7402
7403 #ifdef RTE_LIBRTE_MLX5_DEBUG
7404 /**
7405  * Sanity check for match mask and value. Similar to check_valid_spec() in
7406  * kernel driver. If unmasked bit is present in value, it returns failure.
7407  *
7408  * @param match_mask
7409  *   pointer to match mask buffer.
7410  * @param match_value
7411  *   pointer to match value buffer.
7412  *
7413  * @return
7414  *   0 if valid, -EINVAL otherwise.
7415  */
7416 static int
7417 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7418 {
7419         uint8_t *m = match_mask;
7420         uint8_t *v = match_value;
7421         unsigned int i;
7422
7423         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7424                 if (v[i] & ~m[i]) {
7425                         DRV_LOG(ERR,
7426                                 "match_value differs from match_criteria"
7427                                 " %p[%u] != %p[%u]",
7428                                 match_value, i, match_mask, i);
7429                         return -EINVAL;
7430                 }
7431         }
7432         return 0;
7433 }
7434 #endif
7435
7436 /**
7437  * Add match of ip_version.
7438  *
7439  * @param[in] group
7440  *   Flow group.
7441  * @param[in] headers_v
7442  *   Values header pointer.
7443  * @param[in] headers_m
7444  *   Masks header pointer.
7445  * @param[in] ip_version
7446  *   The IP version to set.
7447  */
7448 static inline void
7449 flow_dv_set_match_ip_version(uint32_t group,
7450                              void *headers_v,
7451                              void *headers_m,
7452                              uint8_t ip_version)
7453 {
7454         if (group == 0)
7455                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7456         else
7457                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7458                          ip_version);
7459         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7460         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7461         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7462 }
7463
7464 /**
7465  * Add Ethernet item to matcher and to the value.
7466  *
7467  * @param[in, out] matcher
7468  *   Flow matcher.
7469  * @param[in, out] key
7470  *   Flow matcher value.
7471  * @param[in] item
7472  *   Flow pattern to translate.
7473  * @param[in] inner
7474  *   Item is inner pattern.
7475  */
7476 static void
7477 flow_dv_translate_item_eth(void *matcher, void *key,
7478                            const struct rte_flow_item *item, int inner,
7479                            uint32_t group)
7480 {
7481         const struct rte_flow_item_eth *eth_m = item->mask;
7482         const struct rte_flow_item_eth *eth_v = item->spec;
7483         const struct rte_flow_item_eth nic_mask = {
7484                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7485                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7486                 .type = RTE_BE16(0xffff),
7487                 .has_vlan = 0,
7488         };
7489         void *hdrs_m;
7490         void *hdrs_v;
7491         char *l24_v;
7492         unsigned int i;
7493
7494         if (!eth_v)
7495                 return;
7496         if (!eth_m)
7497                 eth_m = &nic_mask;
7498         if (inner) {
7499                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7500                                          inner_headers);
7501                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7502         } else {
7503                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7504                                          outer_headers);
7505                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7506         }
7507         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7508                &eth_m->dst, sizeof(eth_m->dst));
7509         /* The value must be in the range of the mask. */
7510         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7511         for (i = 0; i < sizeof(eth_m->dst); ++i)
7512                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7513         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7514                &eth_m->src, sizeof(eth_m->src));
7515         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7516         /* The value must be in the range of the mask. */
7517         for (i = 0; i < sizeof(eth_m->dst); ++i)
7518                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7519         /*
7520          * HW supports match on one Ethertype, the Ethertype following the last
7521          * VLAN tag of the packet (see PRM).
7522          * Set match on ethertype only if ETH header is not followed by VLAN.
7523          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7524          * ethertype, and use ip_version field instead.
7525          * eCPRI over Ether layer will use type value 0xAEFE.
7526          */
7527         if (eth_m->type == 0xFFFF) {
7528                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7529                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7530                 switch (eth_v->type) {
7531                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7532                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7533                         return;
7534                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7535                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7536                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7537                         return;
7538                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7539                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7540                         return;
7541                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7542                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7543                         return;
7544                 default:
7545                         break;
7546                 }
7547         }
7548         if (eth_m->has_vlan) {
7549                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7550                 if (eth_v->has_vlan) {
7551                         /*
7552                          * Here, when also has_more_vlan field in VLAN item is
7553                          * not set, only single-tagged packets will be matched.
7554                          */
7555                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7556                         return;
7557                 }
7558         }
7559         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7560                  rte_be_to_cpu_16(eth_m->type));
7561         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7562         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7563 }
7564
7565 /**
7566  * Add VLAN item to matcher and to the value.
7567  *
7568  * @param[in, out] dev_flow
7569  *   Flow descriptor.
7570  * @param[in, out] matcher
7571  *   Flow matcher.
7572  * @param[in, out] key
7573  *   Flow matcher value.
7574  * @param[in] item
7575  *   Flow pattern to translate.
7576  * @param[in] inner
7577  *   Item is inner pattern.
7578  */
7579 static void
7580 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7581                             void *matcher, void *key,
7582                             const struct rte_flow_item *item,
7583                             int inner, uint32_t group)
7584 {
7585         const struct rte_flow_item_vlan *vlan_m = item->mask;
7586         const struct rte_flow_item_vlan *vlan_v = item->spec;
7587         void *hdrs_m;
7588         void *hdrs_v;
7589         uint16_t tci_m;
7590         uint16_t tci_v;
7591
7592         if (inner) {
7593                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7594                                          inner_headers);
7595                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7596         } else {
7597                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7598                                          outer_headers);
7599                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7600                 /*
7601                  * This is workaround, masks are not supported,
7602                  * and pre-validated.
7603                  */
7604                 if (vlan_v)
7605                         dev_flow->handle->vf_vlan.tag =
7606                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7607         }
7608         /*
7609          * When VLAN item exists in flow, mark packet as tagged,
7610          * even if TCI is not specified.
7611          */
7612         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7613                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7614                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7615         }
7616         if (!vlan_v)
7617                 return;
7618         if (!vlan_m)
7619                 vlan_m = &rte_flow_item_vlan_mask;
7620         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7621         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7622         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7623         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7624         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7625         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7626         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7627         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7628         /*
7629          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7630          * ethertype, and use ip_version field instead.
7631          */
7632         if (vlan_m->inner_type == 0xFFFF) {
7633                 switch (vlan_v->inner_type) {
7634                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7635                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7636                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7637                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7638                         return;
7639                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7640                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7641                         return;
7642                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7643                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7644                         return;
7645                 default:
7646                         break;
7647                 }
7648         }
7649         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7650                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7651                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7652                 /* Only one vlan_tag bit can be set. */
7653                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7654                 return;
7655         }
7656         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7657                  rte_be_to_cpu_16(vlan_m->inner_type));
7658         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7659                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7660 }
7661
7662 /**
7663  * Add IPV4 item to matcher and to the value.
7664  *
7665  * @param[in, out] matcher
7666  *   Flow matcher.
7667  * @param[in, out] key
7668  *   Flow matcher value.
7669  * @param[in] item
7670  *   Flow pattern to translate.
7671  * @param[in] inner
7672  *   Item is inner pattern.
7673  * @param[in] group
7674  *   The group to insert the rule.
7675  */
7676 static void
7677 flow_dv_translate_item_ipv4(void *matcher, void *key,
7678                             const struct rte_flow_item *item,
7679                             int inner, uint32_t group)
7680 {
7681         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7682         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7683         const struct rte_flow_item_ipv4 nic_mask = {
7684                 .hdr = {
7685                         .src_addr = RTE_BE32(0xffffffff),
7686                         .dst_addr = RTE_BE32(0xffffffff),
7687                         .type_of_service = 0xff,
7688                         .next_proto_id = 0xff,
7689                         .time_to_live = 0xff,
7690                 },
7691         };
7692         void *headers_m;
7693         void *headers_v;
7694         char *l24_m;
7695         char *l24_v;
7696         uint8_t tos;
7697
7698         if (inner) {
7699                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7700                                          inner_headers);
7701                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7702         } else {
7703                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7704                                          outer_headers);
7705                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7706         }
7707         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7708         if (!ipv4_v)
7709                 return;
7710         if (!ipv4_m)
7711                 ipv4_m = &nic_mask;
7712         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7713                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7714         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7715                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7716         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7717         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7718         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7719                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7720         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7721                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7722         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7723         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7724         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7725         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7726                  ipv4_m->hdr.type_of_service);
7727         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7729                  ipv4_m->hdr.type_of_service >> 2);
7730         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7731         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7732                  ipv4_m->hdr.next_proto_id);
7733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7734                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7735         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7736                  ipv4_m->hdr.time_to_live);
7737         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7738                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7739         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7740                  !!(ipv4_m->hdr.fragment_offset));
7741         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7742                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7743 }
7744
7745 /**
7746  * Add IPV6 item to matcher and to the value.
7747  *
7748  * @param[in, out] matcher
7749  *   Flow matcher.
7750  * @param[in, out] key
7751  *   Flow matcher value.
7752  * @param[in] item
7753  *   Flow pattern to translate.
7754  * @param[in] inner
7755  *   Item is inner pattern.
7756  * @param[in] group
7757  *   The group to insert the rule.
7758  */
7759 static void
7760 flow_dv_translate_item_ipv6(void *matcher, void *key,
7761                             const struct rte_flow_item *item,
7762                             int inner, uint32_t group)
7763 {
7764         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7765         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7766         const struct rte_flow_item_ipv6 nic_mask = {
7767                 .hdr = {
7768                         .src_addr =
7769                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7770                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7771                         .dst_addr =
7772                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7773                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7774                         .vtc_flow = RTE_BE32(0xffffffff),
7775                         .proto = 0xff,
7776                         .hop_limits = 0xff,
7777                 },
7778         };
7779         void *headers_m;
7780         void *headers_v;
7781         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7782         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7783         char *l24_m;
7784         char *l24_v;
7785         uint32_t vtc_m;
7786         uint32_t vtc_v;
7787         int i;
7788         int size;
7789
7790         if (inner) {
7791                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7792                                          inner_headers);
7793                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7794         } else {
7795                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7796                                          outer_headers);
7797                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7798         }
7799         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7800         if (!ipv6_v)
7801                 return;
7802         if (!ipv6_m)
7803                 ipv6_m = &nic_mask;
7804         size = sizeof(ipv6_m->hdr.dst_addr);
7805         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7806                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7807         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7808                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7809         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7810         for (i = 0; i < size; ++i)
7811                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7812         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7813                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7814         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7815                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7816         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7817         for (i = 0; i < size; ++i)
7818                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7819         /* TOS. */
7820         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7821         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7822         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7823         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7824         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7825         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7826         /* Label. */
7827         if (inner) {
7828                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7829                          vtc_m);
7830                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7831                          vtc_v);
7832         } else {
7833                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7834                          vtc_m);
7835                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7836                          vtc_v);
7837         }
7838         /* Protocol. */
7839         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7840                  ipv6_m->hdr.proto);
7841         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7842                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7843         /* Hop limit. */
7844         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7845                  ipv6_m->hdr.hop_limits);
7846         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7847                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7848         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7849                  !!(ipv6_m->has_frag_ext));
7850         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7851                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7852 }
7853
7854 /**
7855  * Add IPV6 fragment extension item to matcher and to the value.
7856  *
7857  * @param[in, out] matcher
7858  *   Flow matcher.
7859  * @param[in, out] key
7860  *   Flow matcher value.
7861  * @param[in] item
7862  *   Flow pattern to translate.
7863  * @param[in] inner
7864  *   Item is inner pattern.
7865  */
7866 static void
7867 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7868                                      const struct rte_flow_item *item,
7869                                      int inner)
7870 {
7871         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7872         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7873         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7874                 .hdr = {
7875                         .next_header = 0xff,
7876                         .frag_data = RTE_BE16(0xffff),
7877                 },
7878         };
7879         void *headers_m;
7880         void *headers_v;
7881
7882         if (inner) {
7883                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7884                                          inner_headers);
7885                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7886         } else {
7887                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7888                                          outer_headers);
7889                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7890         }
7891         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7892         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7893         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7894         if (!ipv6_frag_ext_v)
7895                 return;
7896         if (!ipv6_frag_ext_m)
7897                 ipv6_frag_ext_m = &nic_mask;
7898         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7899                  ipv6_frag_ext_m->hdr.next_header);
7900         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7901                  ipv6_frag_ext_v->hdr.next_header &
7902                  ipv6_frag_ext_m->hdr.next_header);
7903 }
7904
7905 /**
7906  * Add TCP item to matcher and to the value.
7907  *
7908  * @param[in, out] matcher
7909  *   Flow matcher.
7910  * @param[in, out] key
7911  *   Flow matcher value.
7912  * @param[in] item
7913  *   Flow pattern to translate.
7914  * @param[in] inner
7915  *   Item is inner pattern.
7916  */
7917 static void
7918 flow_dv_translate_item_tcp(void *matcher, void *key,
7919                            const struct rte_flow_item *item,
7920                            int inner)
7921 {
7922         const struct rte_flow_item_tcp *tcp_m = item->mask;
7923         const struct rte_flow_item_tcp *tcp_v = item->spec;
7924         void *headers_m;
7925         void *headers_v;
7926
7927         if (inner) {
7928                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7929                                          inner_headers);
7930                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7931         } else {
7932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7933                                          outer_headers);
7934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7935         }
7936         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7937         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7938         if (!tcp_v)
7939                 return;
7940         if (!tcp_m)
7941                 tcp_m = &rte_flow_item_tcp_mask;
7942         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7943                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7944         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7945                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7946         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7947                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7948         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7949                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7950         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7951                  tcp_m->hdr.tcp_flags);
7952         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7953                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7954 }
7955
7956 /**
7957  * Add UDP item to matcher and to the value.
7958  *
7959  * @param[in, out] matcher
7960  *   Flow matcher.
7961  * @param[in, out] key
7962  *   Flow matcher value.
7963  * @param[in] item
7964  *   Flow pattern to translate.
7965  * @param[in] inner
7966  *   Item is inner pattern.
7967  */
7968 static void
7969 flow_dv_translate_item_udp(void *matcher, void *key,
7970                            const struct rte_flow_item *item,
7971                            int inner)
7972 {
7973         const struct rte_flow_item_udp *udp_m = item->mask;
7974         const struct rte_flow_item_udp *udp_v = item->spec;
7975         void *headers_m;
7976         void *headers_v;
7977
7978         if (inner) {
7979                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7980                                          inner_headers);
7981                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7982         } else {
7983                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7984                                          outer_headers);
7985                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7986         }
7987         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7988         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7989         if (!udp_v)
7990                 return;
7991         if (!udp_m)
7992                 udp_m = &rte_flow_item_udp_mask;
7993         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7994                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7995         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7996                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7997         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7998                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7999         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8000                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8001 }
8002
8003 /**
8004  * Add GRE optional Key item to matcher and to the value.
8005  *
8006  * @param[in, out] matcher
8007  *   Flow matcher.
8008  * @param[in, out] key
8009  *   Flow matcher value.
8010  * @param[in] item
8011  *   Flow pattern to translate.
8012  * @param[in] inner
8013  *   Item is inner pattern.
8014  */
8015 static void
8016 flow_dv_translate_item_gre_key(void *matcher, void *key,
8017                                    const struct rte_flow_item *item)
8018 {
8019         const rte_be32_t *key_m = item->mask;
8020         const rte_be32_t *key_v = item->spec;
8021         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8022         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8023         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8024
8025         /* GRE K bit must be on and should already be validated */
8026         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8027         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8028         if (!key_v)
8029                 return;
8030         if (!key_m)
8031                 key_m = &gre_key_default_mask;
8032         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8033                  rte_be_to_cpu_32(*key_m) >> 8);
8034         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8035                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8036         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8037                  rte_be_to_cpu_32(*key_m) & 0xFF);
8038         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8039                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8040 }
8041
8042 /**
8043  * Add GRE item to matcher and to the value.
8044  *
8045  * @param[in, out] matcher
8046  *   Flow matcher.
8047  * @param[in, out] key
8048  *   Flow matcher value.
8049  * @param[in] item
8050  *   Flow pattern to translate.
8051  * @param[in] inner
8052  *   Item is inner pattern.
8053  */
8054 static void
8055 flow_dv_translate_item_gre(void *matcher, void *key,
8056                            const struct rte_flow_item *item,
8057                            int inner)
8058 {
8059         const struct rte_flow_item_gre *gre_m = item->mask;
8060         const struct rte_flow_item_gre *gre_v = item->spec;
8061         void *headers_m;
8062         void *headers_v;
8063         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8064         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8065         struct {
8066                 union {
8067                         __extension__
8068                         struct {
8069                                 uint16_t version:3;
8070                                 uint16_t rsvd0:9;
8071                                 uint16_t s_present:1;
8072                                 uint16_t k_present:1;
8073                                 uint16_t rsvd_bit1:1;
8074                                 uint16_t c_present:1;
8075                         };
8076                         uint16_t value;
8077                 };
8078         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8079
8080         if (inner) {
8081                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8082                                          inner_headers);
8083                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8084         } else {
8085                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8086                                          outer_headers);
8087                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8088         }
8089         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8090         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8091         if (!gre_v)
8092                 return;
8093         if (!gre_m)
8094                 gre_m = &rte_flow_item_gre_mask;
8095         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
8096                  rte_be_to_cpu_16(gre_m->protocol));
8097         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8098                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
8099         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8100         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8101         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8102                  gre_crks_rsvd0_ver_m.c_present);
8103         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8104                  gre_crks_rsvd0_ver_v.c_present &
8105                  gre_crks_rsvd0_ver_m.c_present);
8106         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8107                  gre_crks_rsvd0_ver_m.k_present);
8108         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8109                  gre_crks_rsvd0_ver_v.k_present &
8110                  gre_crks_rsvd0_ver_m.k_present);
8111         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8112                  gre_crks_rsvd0_ver_m.s_present);
8113         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8114                  gre_crks_rsvd0_ver_v.s_present &
8115                  gre_crks_rsvd0_ver_m.s_present);
8116 }
8117
8118 /**
8119  * Add NVGRE item to matcher and to the value.
8120  *
8121  * @param[in, out] matcher
8122  *   Flow matcher.
8123  * @param[in, out] key
8124  *   Flow matcher value.
8125  * @param[in] item
8126  *   Flow pattern to translate.
8127  * @param[in] inner
8128  *   Item is inner pattern.
8129  */
8130 static void
8131 flow_dv_translate_item_nvgre(void *matcher, void *key,
8132                              const struct rte_flow_item *item,
8133                              int inner)
8134 {
8135         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8136         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8137         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8138         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8139         const char *tni_flow_id_m;
8140         const char *tni_flow_id_v;
8141         char *gre_key_m;
8142         char *gre_key_v;
8143         int size;
8144         int i;
8145
8146         /* For NVGRE, GRE header fields must be set with defined values. */
8147         const struct rte_flow_item_gre gre_spec = {
8148                 .c_rsvd0_ver = RTE_BE16(0x2000),
8149                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8150         };
8151         const struct rte_flow_item_gre gre_mask = {
8152                 .c_rsvd0_ver = RTE_BE16(0xB000),
8153                 .protocol = RTE_BE16(UINT16_MAX),
8154         };
8155         const struct rte_flow_item gre_item = {
8156                 .spec = &gre_spec,
8157                 .mask = &gre_mask,
8158                 .last = NULL,
8159         };
8160         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
8161         if (!nvgre_v)
8162                 return;
8163         if (!nvgre_m)
8164                 nvgre_m = &rte_flow_item_nvgre_mask;
8165         tni_flow_id_m = (const char *)nvgre_m->tni;
8166         tni_flow_id_v = (const char *)nvgre_v->tni;
8167         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8168         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8169         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8170         memcpy(gre_key_m, tni_flow_id_m, size);
8171         for (i = 0; i < size; ++i)
8172                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8173 }
8174
8175 /**
8176  * Add VXLAN item to matcher and to the value.
8177  *
8178  * @param[in, out] matcher
8179  *   Flow matcher.
8180  * @param[in, out] key
8181  *   Flow matcher value.
8182  * @param[in] item
8183  *   Flow pattern to translate.
8184  * @param[in] inner
8185  *   Item is inner pattern.
8186  */
8187 static void
8188 flow_dv_translate_item_vxlan(void *matcher, void *key,
8189                              const struct rte_flow_item *item,
8190                              int inner)
8191 {
8192         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8193         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8194         void *headers_m;
8195         void *headers_v;
8196         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8197         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8198         char *vni_m;
8199         char *vni_v;
8200         uint16_t dport;
8201         int size;
8202         int i;
8203
8204         if (inner) {
8205                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8206                                          inner_headers);
8207                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8208         } else {
8209                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8210                                          outer_headers);
8211                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8212         }
8213         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8214                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8215         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8216                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8217                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8218         }
8219         if (!vxlan_v)
8220                 return;
8221         if (!vxlan_m)
8222                 vxlan_m = &rte_flow_item_vxlan_mask;
8223         size = sizeof(vxlan_m->vni);
8224         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8225         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8226         memcpy(vni_m, vxlan_m->vni, size);
8227         for (i = 0; i < size; ++i)
8228                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8229 }
8230
8231 /**
8232  * Add VXLAN-GPE item to matcher and to the value.
8233  *
8234  * @param[in, out] matcher
8235  *   Flow matcher.
8236  * @param[in, out] key
8237  *   Flow matcher value.
8238  * @param[in] item
8239  *   Flow pattern to translate.
8240  * @param[in] inner
8241  *   Item is inner pattern.
8242  */
8243
8244 static void
8245 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8246                                  const struct rte_flow_item *item, int inner)
8247 {
8248         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8249         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8250         void *headers_m;
8251         void *headers_v;
8252         void *misc_m =
8253                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8254         void *misc_v =
8255                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8256         char *vni_m;
8257         char *vni_v;
8258         uint16_t dport;
8259         int size;
8260         int i;
8261         uint8_t flags_m = 0xff;
8262         uint8_t flags_v = 0xc;
8263
8264         if (inner) {
8265                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8266                                          inner_headers);
8267                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8268         } else {
8269                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8270                                          outer_headers);
8271                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8272         }
8273         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8274                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8275         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8276                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8277                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8278         }
8279         if (!vxlan_v)
8280                 return;
8281         if (!vxlan_m)
8282                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8283         size = sizeof(vxlan_m->vni);
8284         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8285         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8286         memcpy(vni_m, vxlan_m->vni, size);
8287         for (i = 0; i < size; ++i)
8288                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8289         if (vxlan_m->flags) {
8290                 flags_m = vxlan_m->flags;
8291                 flags_v = vxlan_v->flags;
8292         }
8293         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8294         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8295         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8296                  vxlan_m->protocol);
8297         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8298                  vxlan_v->protocol);
8299 }
8300
8301 /**
8302  * Add Geneve item to matcher and to the value.
8303  *
8304  * @param[in, out] matcher
8305  *   Flow matcher.
8306  * @param[in, out] key
8307  *   Flow matcher value.
8308  * @param[in] item
8309  *   Flow pattern to translate.
8310  * @param[in] inner
8311  *   Item is inner pattern.
8312  */
8313
8314 static void
8315 flow_dv_translate_item_geneve(void *matcher, void *key,
8316                               const struct rte_flow_item *item, int inner)
8317 {
8318         const struct rte_flow_item_geneve *geneve_m = item->mask;
8319         const struct rte_flow_item_geneve *geneve_v = item->spec;
8320         void *headers_m;
8321         void *headers_v;
8322         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8323         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8324         uint16_t dport;
8325         uint16_t gbhdr_m;
8326         uint16_t gbhdr_v;
8327         char *vni_m;
8328         char *vni_v;
8329         size_t size, i;
8330
8331         if (inner) {
8332                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8333                                          inner_headers);
8334                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8335         } else {
8336                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8337                                          outer_headers);
8338                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8339         }
8340         dport = MLX5_UDP_PORT_GENEVE;
8341         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8342                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8343                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8344         }
8345         if (!geneve_v)
8346                 return;
8347         if (!geneve_m)
8348                 geneve_m = &rte_flow_item_geneve_mask;
8349         size = sizeof(geneve_m->vni);
8350         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8351         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8352         memcpy(vni_m, geneve_m->vni, size);
8353         for (i = 0; i < size; ++i)
8354                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8355         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8356                  rte_be_to_cpu_16(geneve_m->protocol));
8357         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8358                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8359         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8360         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8361         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8362                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8363         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8364                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8365         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8366                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8367         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8368                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8369                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8370 }
8371
8372 /**
8373  * Create Geneve TLV option resource.
8374  *
8375  * @param dev[in, out]
8376  *   Pointer to rte_eth_dev structure.
8377  * @param[in, out] tag_be24
8378  *   Tag value in big endian then R-shift 8.
8379  * @parm[in, out] dev_flow
8380  *   Pointer to the dev_flow.
8381  * @param[out] error
8382  *   pointer to error structure.
8383  *
8384  * @return
8385  *   0 on success otherwise -errno and errno is set.
8386  */
8387
8388 int
8389 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8390                                              const struct rte_flow_item *item,
8391                                              struct rte_flow_error *error)
8392 {
8393         struct mlx5_priv *priv = dev->data->dev_private;
8394         struct mlx5_dev_ctx_shared *sh = priv->sh;
8395         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8396                         sh->geneve_tlv_option_resource;
8397         struct mlx5_devx_obj *obj;
8398         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8399         int ret = 0;
8400
8401         if (!geneve_opt_v)
8402                 return -1;
8403         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8404         if (geneve_opt_resource != NULL) {
8405                 if (geneve_opt_resource->option_class ==
8406                         geneve_opt_v->option_class &&
8407                         geneve_opt_resource->option_type ==
8408                         geneve_opt_v->option_type &&
8409                         geneve_opt_resource->length ==
8410                         geneve_opt_v->option_len) {
8411                         /* We already have GENVE TLV option obj allocated. */
8412                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8413                                            __ATOMIC_RELAXED);
8414                 } else {
8415                         ret = rte_flow_error_set(error, ENOMEM,
8416                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8417                                 "Only one GENEVE TLV option supported");
8418                         goto exit;
8419                 }
8420         } else {
8421                 /* Create a GENEVE TLV object and resource. */
8422                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8423                                 geneve_opt_v->option_class,
8424                                 geneve_opt_v->option_type,
8425                                 geneve_opt_v->option_len);
8426                 if (!obj) {
8427                         ret = rte_flow_error_set(error, ENODATA,
8428                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8429                                 "Failed to create GENEVE TLV Devx object");
8430                         goto exit;
8431                 }
8432                 sh->geneve_tlv_option_resource =
8433                                 mlx5_malloc(MLX5_MEM_ZERO,
8434                                                 sizeof(*geneve_opt_resource),
8435                                                 0, SOCKET_ID_ANY);
8436                 if (!sh->geneve_tlv_option_resource) {
8437                         claim_zero(mlx5_devx_cmd_destroy(obj));
8438                         ret = rte_flow_error_set(error, ENOMEM,
8439                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8440                                 "GENEVE TLV object memory allocation failed");
8441                         goto exit;
8442                 }
8443                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8444                 geneve_opt_resource->obj = obj;
8445                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8446                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8447                 geneve_opt_resource->length = geneve_opt_v->option_len;
8448                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8449                                 __ATOMIC_RELAXED);
8450         }
8451 exit:
8452         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8453         return ret;
8454 }
8455
8456 /**
8457  * Add Geneve TLV option item to matcher.
8458  *
8459  * @param[in, out] dev
8460  *   Pointer to rte_eth_dev structure.
8461  * @param[in, out] matcher
8462  *   Flow matcher.
8463  * @param[in, out] key
8464  *   Flow matcher value.
8465  * @param[in] item
8466  *   Flow pattern to translate.
8467  * @param[out] error
8468  *   Pointer to error structure.
8469  */
8470 static int
8471 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8472                                   void *key, const struct rte_flow_item *item,
8473                                   struct rte_flow_error *error)
8474 {
8475         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8476         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8477         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8478         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8479         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8480                         misc_parameters_3);
8481         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8482         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8483         int ret = 0;
8484
8485         if (!geneve_opt_v)
8486                 return -1;
8487         if (!geneve_opt_m)
8488                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8489         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8490                                                            error);
8491         if (ret) {
8492                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8493                 return ret;
8494         }
8495         /*
8496          * Set the option length in GENEVE header if not requested.
8497          * The GENEVE TLV option length is expressed by the option length field
8498          * in the GENEVE header.
8499          * If the option length was not requested but the GENEVE TLV option item
8500          * is present we set the option length field implicitly.
8501          */
8502         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8503                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8504                          MLX5_GENEVE_OPTLEN_MASK);
8505                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8506                          geneve_opt_v->option_len + 1);
8507         }
8508         /* Set the data. */
8509         if (geneve_opt_v->data) {
8510                 memcpy(&opt_data_key, geneve_opt_v->data,
8511                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8512                                 sizeof(opt_data_key)));
8513                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8514                                 sizeof(opt_data_key));
8515                 memcpy(&opt_data_mask, geneve_opt_m->data,
8516                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8517                                 sizeof(opt_data_mask)));
8518                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8519                                 sizeof(opt_data_mask));
8520                 MLX5_SET(fte_match_set_misc3, misc3_m,
8521                                 geneve_tlv_option_0_data,
8522                                 rte_be_to_cpu_32(opt_data_mask));
8523                 MLX5_SET(fte_match_set_misc3, misc3_v,
8524                                 geneve_tlv_option_0_data,
8525                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8526         }
8527         return ret;
8528 }
8529
8530 /**
8531  * Add MPLS item to matcher and to the value.
8532  *
8533  * @param[in, out] matcher
8534  *   Flow matcher.
8535  * @param[in, out] key
8536  *   Flow matcher value.
8537  * @param[in] item
8538  *   Flow pattern to translate.
8539  * @param[in] prev_layer
8540  *   The protocol layer indicated in previous item.
8541  * @param[in] inner
8542  *   Item is inner pattern.
8543  */
8544 static void
8545 flow_dv_translate_item_mpls(void *matcher, void *key,
8546                             const struct rte_flow_item *item,
8547                             uint64_t prev_layer,
8548                             int inner)
8549 {
8550         const uint32_t *in_mpls_m = item->mask;
8551         const uint32_t *in_mpls_v = item->spec;
8552         uint32_t *out_mpls_m = 0;
8553         uint32_t *out_mpls_v = 0;
8554         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8555         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8556         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8557                                      misc_parameters_2);
8558         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8559         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8560         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8561
8562         switch (prev_layer) {
8563         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8564                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8565                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8566                          MLX5_UDP_PORT_MPLS);
8567                 break;
8568         case MLX5_FLOW_LAYER_GRE:
8569                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8570                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8571                          RTE_ETHER_TYPE_MPLS);
8572                 break;
8573         default:
8574                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8575                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8576                          IPPROTO_MPLS);
8577                 break;
8578         }
8579         if (!in_mpls_v)
8580                 return;
8581         if (!in_mpls_m)
8582                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8583         switch (prev_layer) {
8584         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8585                 out_mpls_m =
8586                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8587                                                  outer_first_mpls_over_udp);
8588                 out_mpls_v =
8589                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8590                                                  outer_first_mpls_over_udp);
8591                 break;
8592         case MLX5_FLOW_LAYER_GRE:
8593                 out_mpls_m =
8594                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8595                                                  outer_first_mpls_over_gre);
8596                 out_mpls_v =
8597                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8598                                                  outer_first_mpls_over_gre);
8599                 break;
8600         default:
8601                 /* Inner MPLS not over GRE is not supported. */
8602                 if (!inner) {
8603                         out_mpls_m =
8604                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8605                                                          misc2_m,
8606                                                          outer_first_mpls);
8607                         out_mpls_v =
8608                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8609                                                          misc2_v,
8610                                                          outer_first_mpls);
8611                 }
8612                 break;
8613         }
8614         if (out_mpls_m && out_mpls_v) {
8615                 *out_mpls_m = *in_mpls_m;
8616                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8617         }
8618 }
8619
8620 /**
8621  * Add metadata register item to matcher
8622  *
8623  * @param[in, out] matcher
8624  *   Flow matcher.
8625  * @param[in, out] key
8626  *   Flow matcher value.
8627  * @param[in] reg_type
8628  *   Type of device metadata register
8629  * @param[in] value
8630  *   Register value
8631  * @param[in] mask
8632  *   Register mask
8633  */
8634 static void
8635 flow_dv_match_meta_reg(void *matcher, void *key,
8636                        enum modify_reg reg_type,
8637                        uint32_t data, uint32_t mask)
8638 {
8639         void *misc2_m =
8640                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8641         void *misc2_v =
8642                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8643         uint32_t temp;
8644
8645         data &= mask;
8646         switch (reg_type) {
8647         case REG_A:
8648                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8649                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8650                 break;
8651         case REG_B:
8652                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8653                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8654                 break;
8655         case REG_C_0:
8656                 /*
8657                  * The metadata register C0 field might be divided into
8658                  * source vport index and META item value, we should set
8659                  * this field according to specified mask, not as whole one.
8660                  */
8661                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8662                 temp |= mask;
8663                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8664                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8665                 temp &= ~mask;
8666                 temp |= data;
8667                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8668                 break;
8669         case REG_C_1:
8670                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8671                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8672                 break;
8673         case REG_C_2:
8674                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8675                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8676                 break;
8677         case REG_C_3:
8678                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8679                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8680                 break;
8681         case REG_C_4:
8682                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8683                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8684                 break;
8685         case REG_C_5:
8686                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8687                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8688                 break;
8689         case REG_C_6:
8690                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8691                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8692                 break;
8693         case REG_C_7:
8694                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8695                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8696                 break;
8697         default:
8698                 MLX5_ASSERT(false);
8699                 break;
8700         }
8701 }
8702
8703 /**
8704  * Add MARK item to matcher
8705  *
8706  * @param[in] dev
8707  *   The device to configure through.
8708  * @param[in, out] matcher
8709  *   Flow matcher.
8710  * @param[in, out] key
8711  *   Flow matcher value.
8712  * @param[in] item
8713  *   Flow pattern to translate.
8714  */
8715 static void
8716 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8717                             void *matcher, void *key,
8718                             const struct rte_flow_item *item)
8719 {
8720         struct mlx5_priv *priv = dev->data->dev_private;
8721         const struct rte_flow_item_mark *mark;
8722         uint32_t value;
8723         uint32_t mask;
8724
8725         mark = item->mask ? (const void *)item->mask :
8726                             &rte_flow_item_mark_mask;
8727         mask = mark->id & priv->sh->dv_mark_mask;
8728         mark = (const void *)item->spec;
8729         MLX5_ASSERT(mark);
8730         value = mark->id & priv->sh->dv_mark_mask & mask;
8731         if (mask) {
8732                 enum modify_reg reg;
8733
8734                 /* Get the metadata register index for the mark. */
8735                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8736                 MLX5_ASSERT(reg > 0);
8737                 if (reg == REG_C_0) {
8738                         struct mlx5_priv *priv = dev->data->dev_private;
8739                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8740                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8741
8742                         mask &= msk_c0;
8743                         mask <<= shl_c0;
8744                         value <<= shl_c0;
8745                 }
8746                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8747         }
8748 }
8749
8750 /**
8751  * Add META item to matcher
8752  *
8753  * @param[in] dev
8754  *   The devich to configure through.
8755  * @param[in, out] matcher
8756  *   Flow matcher.
8757  * @param[in, out] key
8758  *   Flow matcher value.
8759  * @param[in] attr
8760  *   Attributes of flow that includes this item.
8761  * @param[in] item
8762  *   Flow pattern to translate.
8763  */
8764 static void
8765 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8766                             void *matcher, void *key,
8767                             const struct rte_flow_attr *attr,
8768                             const struct rte_flow_item *item)
8769 {
8770         const struct rte_flow_item_meta *meta_m;
8771         const struct rte_flow_item_meta *meta_v;
8772
8773         meta_m = (const void *)item->mask;
8774         if (!meta_m)
8775                 meta_m = &rte_flow_item_meta_mask;
8776         meta_v = (const void *)item->spec;
8777         if (meta_v) {
8778                 int reg;
8779                 uint32_t value = meta_v->data;
8780                 uint32_t mask = meta_m->data;
8781
8782                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8783                 if (reg < 0)
8784                         return;
8785                 MLX5_ASSERT(reg != REG_NON);
8786                 /*
8787                  * In datapath code there is no endianness
8788                  * coversions for perfromance reasons, all
8789                  * pattern conversions are done in rte_flow.
8790                  */
8791                 value = rte_cpu_to_be_32(value);
8792                 mask = rte_cpu_to_be_32(mask);
8793                 if (reg == REG_C_0) {
8794                         struct mlx5_priv *priv = dev->data->dev_private;
8795                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8796                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8797 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8798                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8799
8800                         value >>= shr_c0;
8801                         mask >>= shr_c0;
8802 #endif
8803                         value <<= shl_c0;
8804                         mask <<= shl_c0;
8805                         MLX5_ASSERT(msk_c0);
8806                         MLX5_ASSERT(!(~msk_c0 & mask));
8807                 }
8808                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8809         }
8810 }
8811
8812 /**
8813  * Add vport metadata Reg C0 item to matcher
8814  *
8815  * @param[in, out] matcher
8816  *   Flow matcher.
8817  * @param[in, out] key
8818  *   Flow matcher value.
8819  * @param[in] reg
8820  *   Flow pattern to translate.
8821  */
8822 static void
8823 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8824                                   uint32_t value, uint32_t mask)
8825 {
8826         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8827 }
8828
8829 /**
8830  * Add tag item to matcher
8831  *
8832  * @param[in] dev
8833  *   The devich to configure through.
8834  * @param[in, out] matcher
8835  *   Flow matcher.
8836  * @param[in, out] key
8837  *   Flow matcher value.
8838  * @param[in] item
8839  *   Flow pattern to translate.
8840  */
8841 static void
8842 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8843                                 void *matcher, void *key,
8844                                 const struct rte_flow_item *item)
8845 {
8846         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8847         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8848         uint32_t mask, value;
8849
8850         MLX5_ASSERT(tag_v);
8851         value = tag_v->data;
8852         mask = tag_m ? tag_m->data : UINT32_MAX;
8853         if (tag_v->id == REG_C_0) {
8854                 struct mlx5_priv *priv = dev->data->dev_private;
8855                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8856                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8857
8858                 mask &= msk_c0;
8859                 mask <<= shl_c0;
8860                 value <<= shl_c0;
8861         }
8862         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8863 }
8864
8865 /**
8866  * Add TAG item to matcher
8867  *
8868  * @param[in] dev
8869  *   The devich to configure through.
8870  * @param[in, out] matcher
8871  *   Flow matcher.
8872  * @param[in, out] key
8873  *   Flow matcher value.
8874  * @param[in] item
8875  *   Flow pattern to translate.
8876  */
8877 static void
8878 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8879                            void *matcher, void *key,
8880                            const struct rte_flow_item *item)
8881 {
8882         const struct rte_flow_item_tag *tag_v = item->spec;
8883         const struct rte_flow_item_tag *tag_m = item->mask;
8884         enum modify_reg reg;
8885
8886         MLX5_ASSERT(tag_v);
8887         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8888         /* Get the metadata register index for the tag. */
8889         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8890         MLX5_ASSERT(reg > 0);
8891         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8892 }
8893
8894 /**
8895  * Add source vport match to the specified matcher.
8896  *
8897  * @param[in, out] matcher
8898  *   Flow matcher.
8899  * @param[in, out] key
8900  *   Flow matcher value.
8901  * @param[in] port
8902  *   Source vport value to match
8903  * @param[in] mask
8904  *   Mask
8905  */
8906 static void
8907 flow_dv_translate_item_source_vport(void *matcher, void *key,
8908                                     int16_t port, uint16_t mask)
8909 {
8910         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8911         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8912
8913         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8914         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8915 }
8916
8917 /**
8918  * Translate port-id item to eswitch match on  port-id.
8919  *
8920  * @param[in] dev
8921  *   The devich to configure through.
8922  * @param[in, out] matcher
8923  *   Flow matcher.
8924  * @param[in, out] key
8925  *   Flow matcher value.
8926  * @param[in] item
8927  *   Flow pattern to translate.
8928  * @param[in]
8929  *   Flow attributes.
8930  *
8931  * @return
8932  *   0 on success, a negative errno value otherwise.
8933  */
8934 static int
8935 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8936                                void *key, const struct rte_flow_item *item,
8937                                const struct rte_flow_attr *attr)
8938 {
8939         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8940         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8941         struct mlx5_priv *priv;
8942         uint16_t mask, id;
8943
8944         mask = pid_m ? pid_m->id : 0xffff;
8945         id = pid_v ? pid_v->id : dev->data->port_id;
8946         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8947         if (!priv)
8948                 return -rte_errno;
8949         /*
8950          * Translate to vport field or to metadata, depending on mode.
8951          * Kernel can use either misc.source_port or half of C0 metadata
8952          * register.
8953          */
8954         if (priv->vport_meta_mask) {
8955                 /*
8956                  * Provide the hint for SW steering library
8957                  * to insert the flow into ingress domain and
8958                  * save the extra vport match.
8959                  */
8960                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8961                     priv->pf_bond < 0 && attr->transfer)
8962                         flow_dv_translate_item_source_vport
8963                                 (matcher, key, priv->vport_id, mask);
8964                 /*
8965                  * We should always set the vport metadata register,
8966                  * otherwise the SW steering library can drop
8967                  * the rule if wire vport metadata value is not zero,
8968                  * it depends on kernel configuration.
8969                  */
8970                 flow_dv_translate_item_meta_vport(matcher, key,
8971                                                   priv->vport_meta_tag,
8972                                                   priv->vport_meta_mask);
8973         } else {
8974                 flow_dv_translate_item_source_vport(matcher, key,
8975                                                     priv->vport_id, mask);
8976         }
8977         return 0;
8978 }
8979
8980 /**
8981  * Add ICMP6 item to matcher and to the value.
8982  *
8983  * @param[in, out] matcher
8984  *   Flow matcher.
8985  * @param[in, out] key
8986  *   Flow matcher value.
8987  * @param[in] item
8988  *   Flow pattern to translate.
8989  * @param[in] inner
8990  *   Item is inner pattern.
8991  */
8992 static void
8993 flow_dv_translate_item_icmp6(void *matcher, void *key,
8994                               const struct rte_flow_item *item,
8995                               int inner)
8996 {
8997         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8998         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8999         void *headers_m;
9000         void *headers_v;
9001         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9002                                      misc_parameters_3);
9003         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9004         if (inner) {
9005                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9006                                          inner_headers);
9007                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9008         } else {
9009                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9010                                          outer_headers);
9011                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9012         }
9013         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9014         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9015         if (!icmp6_v)
9016                 return;
9017         if (!icmp6_m)
9018                 icmp6_m = &rte_flow_item_icmp6_mask;
9019         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9020         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9021                  icmp6_v->type & icmp6_m->type);
9022         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9023         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9024                  icmp6_v->code & icmp6_m->code);
9025 }
9026
9027 /**
9028  * Add ICMP item to matcher and to the value.
9029  *
9030  * @param[in, out] matcher
9031  *   Flow matcher.
9032  * @param[in, out] key
9033  *   Flow matcher value.
9034  * @param[in] item
9035  *   Flow pattern to translate.
9036  * @param[in] inner
9037  *   Item is inner pattern.
9038  */
9039 static void
9040 flow_dv_translate_item_icmp(void *matcher, void *key,
9041                             const struct rte_flow_item *item,
9042                             int inner)
9043 {
9044         const struct rte_flow_item_icmp *icmp_m = item->mask;
9045         const struct rte_flow_item_icmp *icmp_v = item->spec;
9046         uint32_t icmp_header_data_m = 0;
9047         uint32_t icmp_header_data_v = 0;
9048         void *headers_m;
9049         void *headers_v;
9050         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9051                                      misc_parameters_3);
9052         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9053         if (inner) {
9054                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9055                                          inner_headers);
9056                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9057         } else {
9058                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9059                                          outer_headers);
9060                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9061         }
9062         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9063         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9064         if (!icmp_v)
9065                 return;
9066         if (!icmp_m)
9067                 icmp_m = &rte_flow_item_icmp_mask;
9068         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9069                  icmp_m->hdr.icmp_type);
9070         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9071                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9072         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9073                  icmp_m->hdr.icmp_code);
9074         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9075                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9076         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9077         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9078         if (icmp_header_data_m) {
9079                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9080                 icmp_header_data_v |=
9081                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9082                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9083                          icmp_header_data_m);
9084                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9085                          icmp_header_data_v & icmp_header_data_m);
9086         }
9087 }
9088
9089 /**
9090  * Add GTP item to matcher and to the value.
9091  *
9092  * @param[in, out] matcher
9093  *   Flow matcher.
9094  * @param[in, out] key
9095  *   Flow matcher value.
9096  * @param[in] item
9097  *   Flow pattern to translate.
9098  * @param[in] inner
9099  *   Item is inner pattern.
9100  */
9101 static void
9102 flow_dv_translate_item_gtp(void *matcher, void *key,
9103                            const struct rte_flow_item *item, int inner)
9104 {
9105         const struct rte_flow_item_gtp *gtp_m = item->mask;
9106         const struct rte_flow_item_gtp *gtp_v = item->spec;
9107         void *headers_m;
9108         void *headers_v;
9109         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9110                                      misc_parameters_3);
9111         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9112         uint16_t dport = RTE_GTPU_UDP_PORT;
9113
9114         if (inner) {
9115                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9116                                          inner_headers);
9117                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9118         } else {
9119                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9120                                          outer_headers);
9121                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9122         }
9123         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9124                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9125                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9126         }
9127         if (!gtp_v)
9128                 return;
9129         if (!gtp_m)
9130                 gtp_m = &rte_flow_item_gtp_mask;
9131         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9132                  gtp_m->v_pt_rsv_flags);
9133         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9134                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9135         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9136         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9137                  gtp_v->msg_type & gtp_m->msg_type);
9138         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9139                  rte_be_to_cpu_32(gtp_m->teid));
9140         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9141                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9142 }
9143
9144 /**
9145  * Add GTP PSC item to matcher.
9146  *
9147  * @param[in, out] matcher
9148  *   Flow matcher.
9149  * @param[in, out] key
9150  *   Flow matcher value.
9151  * @param[in] item
9152  *   Flow pattern to translate.
9153  */
9154 static int
9155 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9156                                const struct rte_flow_item *item)
9157 {
9158         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9159         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9160         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9161                         misc_parameters_3);
9162         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9163         union {
9164                 uint32_t w32;
9165                 struct {
9166                         uint16_t seq_num;
9167                         uint8_t npdu_num;
9168                         uint8_t next_ext_header_type;
9169                 };
9170         } dw_2;
9171         uint8_t gtp_flags;
9172
9173         /* Always set E-flag match on one, regardless of GTP item settings. */
9174         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9175         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9176         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9177         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9178         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9179         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9180         /*Set next extension header type. */
9181         dw_2.seq_num = 0;
9182         dw_2.npdu_num = 0;
9183         dw_2.next_ext_header_type = 0xff;
9184         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9185                  rte_cpu_to_be_32(dw_2.w32));
9186         dw_2.seq_num = 0;
9187         dw_2.npdu_num = 0;
9188         dw_2.next_ext_header_type = 0x85;
9189         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9190                  rte_cpu_to_be_32(dw_2.w32));
9191         if (gtp_psc_v) {
9192                 union {
9193                         uint32_t w32;
9194                         struct {
9195                                 uint8_t len;
9196                                 uint8_t type_flags;
9197                                 uint8_t qfi;
9198                                 uint8_t reserved;
9199                         };
9200                 } dw_0;
9201
9202                 /*Set extension header PDU type and Qos. */
9203                 if (!gtp_psc_m)
9204                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9205                 dw_0.w32 = 0;
9206                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9207                 dw_0.qfi = gtp_psc_m->qfi;
9208                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9209                          rte_cpu_to_be_32(dw_0.w32));
9210                 dw_0.w32 = 0;
9211                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9212                                                         gtp_psc_m->pdu_type);
9213                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9214                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9215                          rte_cpu_to_be_32(dw_0.w32));
9216         }
9217         return 0;
9218 }
9219
9220 /**
9221  * Add eCPRI item to matcher and to the value.
9222  *
9223  * @param[in] dev
9224  *   The devich to configure through.
9225  * @param[in, out] matcher
9226  *   Flow matcher.
9227  * @param[in, out] key
9228  *   Flow matcher value.
9229  * @param[in] item
9230  *   Flow pattern to translate.
9231  * @param[in] samples
9232  *   Sample IDs to be used in the matching.
9233  */
9234 static void
9235 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9236                              void *key, const struct rte_flow_item *item)
9237 {
9238         struct mlx5_priv *priv = dev->data->dev_private;
9239         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9240         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9241         struct rte_ecpri_common_hdr common;
9242         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9243                                      misc_parameters_4);
9244         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9245         uint32_t *samples;
9246         void *dw_m;
9247         void *dw_v;
9248
9249         if (!ecpri_v)
9250                 return;
9251         if (!ecpri_m)
9252                 ecpri_m = &rte_flow_item_ecpri_mask;
9253         /*
9254          * Maximal four DW samples are supported in a single matching now.
9255          * Two are used now for a eCPRI matching:
9256          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9257          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9258          *    if any.
9259          */
9260         if (!ecpri_m->hdr.common.u32)
9261                 return;
9262         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9263         /* Need to take the whole DW as the mask to fill the entry. */
9264         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9265                             prog_sample_field_value_0);
9266         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9267                             prog_sample_field_value_0);
9268         /* Already big endian (network order) in the header. */
9269         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9270         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9271         /* Sample#0, used for matching type, offset 0. */
9272         MLX5_SET(fte_match_set_misc4, misc4_m,
9273                  prog_sample_field_id_0, samples[0]);
9274         /* It makes no sense to set the sample ID in the mask field. */
9275         MLX5_SET(fte_match_set_misc4, misc4_v,
9276                  prog_sample_field_id_0, samples[0]);
9277         /*
9278          * Checking if message body part needs to be matched.
9279          * Some wildcard rules only matching type field should be supported.
9280          */
9281         if (ecpri_m->hdr.dummy[0]) {
9282                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9283                 switch (common.type) {
9284                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9285                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9286                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9287                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9288                                             prog_sample_field_value_1);
9289                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9290                                             prog_sample_field_value_1);
9291                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9292                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9293                                             ecpri_m->hdr.dummy[0];
9294                         /* Sample#1, to match message body, offset 4. */
9295                         MLX5_SET(fte_match_set_misc4, misc4_m,
9296                                  prog_sample_field_id_1, samples[1]);
9297                         MLX5_SET(fte_match_set_misc4, misc4_v,
9298                                  prog_sample_field_id_1, samples[1]);
9299                         break;
9300                 default:
9301                         /* Others, do not match any sample ID. */
9302                         break;
9303                 }
9304         }
9305 }
9306
9307 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9308
9309 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9310         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9311                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9312
9313 /**
9314  * Calculate flow matcher enable bitmap.
9315  *
9316  * @param match_criteria
9317  *   Pointer to flow matcher criteria.
9318  *
9319  * @return
9320  *   Bitmap of enabled fields.
9321  */
9322 static uint8_t
9323 flow_dv_matcher_enable(uint32_t *match_criteria)
9324 {
9325         uint8_t match_criteria_enable;
9326
9327         match_criteria_enable =
9328                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9329                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9330         match_criteria_enable |=
9331                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9332                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9333         match_criteria_enable |=
9334                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9335                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9336         match_criteria_enable |=
9337                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9338                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9339         match_criteria_enable |=
9340                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9341                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9342         match_criteria_enable |=
9343                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9344                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9345         return match_criteria_enable;
9346 }
9347
9348 struct mlx5_hlist_entry *
9349 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9350 {
9351         struct mlx5_dev_ctx_shared *sh = list->ctx;
9352         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9353         struct rte_eth_dev *dev = ctx->dev;
9354         struct mlx5_flow_tbl_data_entry *tbl_data;
9355         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9356         struct rte_flow_error *error = ctx->error;
9357         union mlx5_flow_tbl_key key = { .v64 = key64 };
9358         struct mlx5_flow_tbl_resource *tbl;
9359         void *domain;
9360         uint32_t idx = 0;
9361         int ret;
9362
9363         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9364         if (!tbl_data) {
9365                 rte_flow_error_set(error, ENOMEM,
9366                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9367                                    NULL,
9368                                    "cannot allocate flow table data entry");
9369                 return NULL;
9370         }
9371         tbl_data->idx = idx;
9372         tbl_data->tunnel = tt_prm->tunnel;
9373         tbl_data->group_id = tt_prm->group_id;
9374         tbl_data->external = !!tt_prm->external;
9375         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9376         tbl_data->is_egress = !!key.is_egress;
9377         tbl_data->is_transfer = !!key.is_fdb;
9378         tbl_data->dummy = !!key.dummy;
9379         tbl_data->level = key.level;
9380         tbl_data->id = key.id;
9381         tbl = &tbl_data->tbl;
9382         if (key.dummy)
9383                 return &tbl_data->entry;
9384         if (key.is_fdb)
9385                 domain = sh->fdb_domain;
9386         else if (key.is_egress)
9387                 domain = sh->tx_domain;
9388         else
9389                 domain = sh->rx_domain;
9390         ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
9391         if (ret) {
9392                 rte_flow_error_set(error, ENOMEM,
9393                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9394                                    NULL, "cannot create flow table object");
9395                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9396                 return NULL;
9397         }
9398         if (key.level != 0) {
9399                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9400                                         (tbl->obj, &tbl_data->jump.action);
9401                 if (ret) {
9402                         rte_flow_error_set(error, ENOMEM,
9403                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9404                                            NULL,
9405                                            "cannot create flow jump action");
9406                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9407                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9408                         return NULL;
9409                 }
9410         }
9411         MKSTR(matcher_name, "%s_%s_%u_%u_matcher_cache",
9412               key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
9413               key.level, key.id);
9414         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9415                              flow_dv_matcher_create_cb,
9416                              flow_dv_matcher_match_cb,
9417                              flow_dv_matcher_remove_cb);
9418         return &tbl_data->entry;
9419 }
9420
9421 int
9422 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9423                      struct mlx5_hlist_entry *entry, uint64_t key64,
9424                      void *cb_ctx __rte_unused)
9425 {
9426         struct mlx5_flow_tbl_data_entry *tbl_data =
9427                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9428         union mlx5_flow_tbl_key key = { .v64 = key64 };
9429
9430         return tbl_data->level != key.level ||
9431                tbl_data->id != key.id ||
9432                tbl_data->dummy != key.dummy ||
9433                tbl_data->is_transfer != !!key.is_fdb ||
9434                tbl_data->is_egress != !!key.is_egress;
9435 }
9436
9437 /**
9438  * Get a flow table.
9439  *
9440  * @param[in, out] dev
9441  *   Pointer to rte_eth_dev structure.
9442  * @param[in] table_level
9443  *   Table level to use.
9444  * @param[in] egress
9445  *   Direction of the table.
9446  * @param[in] transfer
9447  *   E-Switch or NIC flow.
9448  * @param[in] dummy
9449  *   Dummy entry for dv API.
9450  * @param[in] table_id
9451  *   Table id to use.
9452  * @param[out] error
9453  *   pointer to error structure.
9454  *
9455  * @return
9456  *   Returns tables resource based on the index, NULL in case of failed.
9457  */
9458 struct mlx5_flow_tbl_resource *
9459 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9460                          uint32_t table_level, uint8_t egress,
9461                          uint8_t transfer,
9462                          bool external,
9463                          const struct mlx5_flow_tunnel *tunnel,
9464                          uint32_t group_id, uint8_t dummy,
9465                          uint32_t table_id,
9466                          struct rte_flow_error *error)
9467 {
9468         struct mlx5_priv *priv = dev->data->dev_private;
9469         union mlx5_flow_tbl_key table_key = {
9470                 {
9471                         .level = table_level,
9472                         .id = table_id,
9473                         .reserved = 0,
9474                         .dummy = !!dummy,
9475                         .is_fdb = !!transfer,
9476                         .is_egress = !!egress,
9477                 }
9478         };
9479         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9480                 .tunnel = tunnel,
9481                 .group_id = group_id,
9482                 .external = external,
9483         };
9484         struct mlx5_flow_cb_ctx ctx = {
9485                 .dev = dev,
9486                 .error = error,
9487                 .data = &tt_prm,
9488         };
9489         struct mlx5_hlist_entry *entry;
9490         struct mlx5_flow_tbl_data_entry *tbl_data;
9491
9492         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9493         if (!entry) {
9494                 rte_flow_error_set(error, ENOMEM,
9495                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9496                                    "cannot get table");
9497                 return NULL;
9498         }
9499         DRV_LOG(DEBUG, "table_level %u table_id %u "
9500                 "tunnel %u group %u registered.",
9501                 table_level, table_id,
9502                 tunnel ? tunnel->tunnel_id : 0, group_id);
9503         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9504         return &tbl_data->tbl;
9505 }
9506
9507 void
9508 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9509                       struct mlx5_hlist_entry *entry)
9510 {
9511         struct mlx5_dev_ctx_shared *sh = list->ctx;
9512         struct mlx5_flow_tbl_data_entry *tbl_data =
9513                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9514
9515         MLX5_ASSERT(entry && sh);
9516         if (tbl_data->jump.action)
9517                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9518         if (tbl_data->tbl.obj)
9519                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9520         if (tbl_data->tunnel_offload && tbl_data->external) {
9521                 struct mlx5_hlist_entry *he;
9522                 struct mlx5_hlist *tunnel_grp_hash;
9523                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9524                 union tunnel_tbl_key tunnel_key = {
9525                         .tunnel_id = tbl_data->tunnel ?
9526                                         tbl_data->tunnel->tunnel_id : 0,
9527                         .group = tbl_data->group_id
9528                 };
9529                 uint32_t table_level = tbl_data->level;
9530
9531                 tunnel_grp_hash = tbl_data->tunnel ?
9532                                         tbl_data->tunnel->groups :
9533                                         thub->groups;
9534                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9535                 if (he)
9536                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9537                 DRV_LOG(DEBUG,
9538                         "table_level %u id %u tunnel %u group %u released.",
9539                         table_level,
9540                         tbl_data->id,
9541                         tbl_data->tunnel ?
9542                         tbl_data->tunnel->tunnel_id : 0,
9543                         tbl_data->group_id);
9544         }
9545         mlx5_cache_list_destroy(&tbl_data->matchers);
9546         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9547 }
9548
9549 /**
9550  * Release a flow table.
9551  *
9552  * @param[in] sh
9553  *   Pointer to device shared structure.
9554  * @param[in] tbl
9555  *   Table resource to be released.
9556  *
9557  * @return
9558  *   Returns 0 if table was released, else return 1;
9559  */
9560 static int
9561 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9562                              struct mlx5_flow_tbl_resource *tbl)
9563 {
9564         struct mlx5_flow_tbl_data_entry *tbl_data =
9565                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9566
9567         if (!tbl)
9568                 return 0;
9569         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9570 }
9571
9572 int
9573 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9574                          struct mlx5_cache_entry *entry, void *cb_ctx)
9575 {
9576         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9577         struct mlx5_flow_dv_matcher *ref = ctx->data;
9578         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9579                                                         entry);
9580
9581         return cur->crc != ref->crc ||
9582                cur->priority != ref->priority ||
9583                memcmp((const void *)cur->mask.buf,
9584                       (const void *)ref->mask.buf, ref->mask.size);
9585 }
9586
9587 struct mlx5_cache_entry *
9588 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9589                           struct mlx5_cache_entry *entry __rte_unused,
9590                           void *cb_ctx)
9591 {
9592         struct mlx5_dev_ctx_shared *sh = list->ctx;
9593         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9594         struct mlx5_flow_dv_matcher *ref = ctx->data;
9595         struct mlx5_flow_dv_matcher *cache;
9596         struct mlx5dv_flow_matcher_attr dv_attr = {
9597                 .type = IBV_FLOW_ATTR_NORMAL,
9598                 .match_mask = (void *)&ref->mask,
9599         };
9600         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9601                                                             typeof(*tbl), tbl);
9602         int ret;
9603
9604         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9605         if (!cache) {
9606                 rte_flow_error_set(ctx->error, ENOMEM,
9607                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9608                                    "cannot create matcher");
9609                 return NULL;
9610         }
9611         *cache = *ref;
9612         dv_attr.match_criteria_enable =
9613                 flow_dv_matcher_enable(cache->mask.buf);
9614         dv_attr.priority = ref->priority;
9615         if (tbl->is_egress)
9616                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9617         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9618                                                &cache->matcher_object);
9619         if (ret) {
9620                 mlx5_free(cache);
9621                 rte_flow_error_set(ctx->error, ENOMEM,
9622                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9623                                    "cannot create matcher");
9624                 return NULL;
9625         }
9626         return &cache->entry;
9627 }
9628
9629 /**
9630  * Register the flow matcher.
9631  *
9632  * @param[in, out] dev
9633  *   Pointer to rte_eth_dev structure.
9634  * @param[in, out] matcher
9635  *   Pointer to flow matcher.
9636  * @param[in, out] key
9637  *   Pointer to flow table key.
9638  * @parm[in, out] dev_flow
9639  *   Pointer to the dev_flow.
9640  * @param[out] error
9641  *   pointer to error structure.
9642  *
9643  * @return
9644  *   0 on success otherwise -errno and errno is set.
9645  */
9646 static int
9647 flow_dv_matcher_register(struct rte_eth_dev *dev,
9648                          struct mlx5_flow_dv_matcher *ref,
9649                          union mlx5_flow_tbl_key *key,
9650                          struct mlx5_flow *dev_flow,
9651                          const struct mlx5_flow_tunnel *tunnel,
9652                          uint32_t group_id,
9653                          struct rte_flow_error *error)
9654 {
9655         struct mlx5_cache_entry *entry;
9656         struct mlx5_flow_dv_matcher *cache;
9657         struct mlx5_flow_tbl_resource *tbl;
9658         struct mlx5_flow_tbl_data_entry *tbl_data;
9659         struct mlx5_flow_cb_ctx ctx = {
9660                 .error = error,
9661                 .data = ref,
9662         };
9663
9664         /**
9665          * tunnel offload API requires this registration for cases when
9666          * tunnel match rule was inserted before tunnel set rule.
9667          */
9668         tbl = flow_dv_tbl_resource_get(dev, key->level,
9669                                        key->is_egress, key->is_fdb,
9670                                        dev_flow->external, tunnel,
9671                                        group_id, 0, key->id, error);
9672         if (!tbl)
9673                 return -rte_errno;      /* No need to refill the error info */
9674         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9675         ref->tbl = tbl;
9676         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9677         if (!entry) {
9678                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9679                 return rte_flow_error_set(error, ENOMEM,
9680                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9681                                           "cannot allocate ref memory");
9682         }
9683         cache = container_of(entry, typeof(*cache), entry);
9684         dev_flow->handle->dvh.matcher = cache;
9685         return 0;
9686 }
9687
9688 struct mlx5_hlist_entry *
9689 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9690 {
9691         struct mlx5_dev_ctx_shared *sh = list->ctx;
9692         struct rte_flow_error *error = ctx;
9693         struct mlx5_flow_dv_tag_resource *entry;
9694         uint32_t idx = 0;
9695         int ret;
9696
9697         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9698         if (!entry) {
9699                 rte_flow_error_set(error, ENOMEM,
9700                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9701                                    "cannot allocate resource memory");
9702                 return NULL;
9703         }
9704         entry->idx = idx;
9705         entry->tag_id = key;
9706         ret = mlx5_flow_os_create_flow_action_tag(key,
9707                                                   &entry->action);
9708         if (ret) {
9709                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9710                 rte_flow_error_set(error, ENOMEM,
9711                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9712                                    NULL, "cannot create action");
9713                 return NULL;
9714         }
9715         return &entry->entry;
9716 }
9717
9718 int
9719 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9720                      struct mlx5_hlist_entry *entry, uint64_t key,
9721                      void *cb_ctx __rte_unused)
9722 {
9723         struct mlx5_flow_dv_tag_resource *tag =
9724                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9725
9726         return key != tag->tag_id;
9727 }
9728
9729 /**
9730  * Find existing tag resource or create and register a new one.
9731  *
9732  * @param dev[in, out]
9733  *   Pointer to rte_eth_dev structure.
9734  * @param[in, out] tag_be24
9735  *   Tag value in big endian then R-shift 8.
9736  * @parm[in, out] dev_flow
9737  *   Pointer to the dev_flow.
9738  * @param[out] error
9739  *   pointer to error structure.
9740  *
9741  * @return
9742  *   0 on success otherwise -errno and errno is set.
9743  */
9744 static int
9745 flow_dv_tag_resource_register
9746                         (struct rte_eth_dev *dev,
9747                          uint32_t tag_be24,
9748                          struct mlx5_flow *dev_flow,
9749                          struct rte_flow_error *error)
9750 {
9751         struct mlx5_priv *priv = dev->data->dev_private;
9752         struct mlx5_flow_dv_tag_resource *cache_resource;
9753         struct mlx5_hlist_entry *entry;
9754
9755         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9756         if (entry) {
9757                 cache_resource = container_of
9758                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9759                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9760                 dev_flow->dv.tag_resource = cache_resource;
9761                 return 0;
9762         }
9763         return -rte_errno;
9764 }
9765
9766 void
9767 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9768                       struct mlx5_hlist_entry *entry)
9769 {
9770         struct mlx5_dev_ctx_shared *sh = list->ctx;
9771         struct mlx5_flow_dv_tag_resource *tag =
9772                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9773
9774         MLX5_ASSERT(tag && sh && tag->action);
9775         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9776         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9777         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9778 }
9779
9780 /**
9781  * Release the tag.
9782  *
9783  * @param dev
9784  *   Pointer to Ethernet device.
9785  * @param tag_idx
9786  *   Tag index.
9787  *
9788  * @return
9789  *   1 while a reference on it exists, 0 when freed.
9790  */
9791 static int
9792 flow_dv_tag_release(struct rte_eth_dev *dev,
9793                     uint32_t tag_idx)
9794 {
9795         struct mlx5_priv *priv = dev->data->dev_private;
9796         struct mlx5_flow_dv_tag_resource *tag;
9797
9798         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9799         if (!tag)
9800                 return 0;
9801         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9802                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9803         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9804 }
9805
9806 /**
9807  * Translate port ID action to vport.
9808  *
9809  * @param[in] dev
9810  *   Pointer to rte_eth_dev structure.
9811  * @param[in] action
9812  *   Pointer to the port ID action.
9813  * @param[out] dst_port_id
9814  *   The target port ID.
9815  * @param[out] error
9816  *   Pointer to the error structure.
9817  *
9818  * @return
9819  *   0 on success, a negative errno value otherwise and rte_errno is set.
9820  */
9821 static int
9822 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9823                                  const struct rte_flow_action *action,
9824                                  uint32_t *dst_port_id,
9825                                  struct rte_flow_error *error)
9826 {
9827         uint32_t port;
9828         struct mlx5_priv *priv;
9829         const struct rte_flow_action_port_id *conf =
9830                         (const struct rte_flow_action_port_id *)action->conf;
9831
9832         port = conf->original ? dev->data->port_id : conf->id;
9833         priv = mlx5_port_to_eswitch_info(port, false);
9834         if (!priv)
9835                 return rte_flow_error_set(error, -rte_errno,
9836                                           RTE_FLOW_ERROR_TYPE_ACTION,
9837                                           NULL,
9838                                           "No eswitch info was found for port");
9839 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9840         /*
9841          * This parameter is transferred to
9842          * mlx5dv_dr_action_create_dest_ib_port().
9843          */
9844         *dst_port_id = priv->dev_port;
9845 #else
9846         /*
9847          * Legacy mode, no LAG configurations is supported.
9848          * This parameter is transferred to
9849          * mlx5dv_dr_action_create_dest_vport().
9850          */
9851         *dst_port_id = priv->vport_id;
9852 #endif
9853         return 0;
9854 }
9855
9856 /**
9857  * Create a counter with aging configuration.
9858  *
9859  * @param[in] dev
9860  *   Pointer to rte_eth_dev structure.
9861  * @param[out] count
9862  *   Pointer to the counter action configuration.
9863  * @param[in] age
9864  *   Pointer to the aging action configuration.
9865  *
9866  * @return
9867  *   Index to flow counter on success, 0 otherwise.
9868  */
9869 static uint32_t
9870 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9871                                 struct mlx5_flow *dev_flow,
9872                                 const struct rte_flow_action_count *count,
9873                                 const struct rte_flow_action_age *age)
9874 {
9875         uint32_t counter;
9876         struct mlx5_age_param *age_param;
9877
9878         if (count && count->shared)
9879                 counter = flow_dv_counter_get_shared(dev, count->id);
9880         else
9881                 counter = flow_dv_counter_alloc(dev, !!age);
9882         if (!counter || age == NULL)
9883                 return counter;
9884         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9885         age_param->context = age->context ? age->context :
9886                 (void *)(uintptr_t)(dev_flow->flow_idx);
9887         age_param->timeout = age->timeout;
9888         age_param->port_id = dev->data->port_id;
9889         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9890         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9891         return counter;
9892 }
9893
9894 /**
9895  * Add Tx queue matcher
9896  *
9897  * @param[in] dev
9898  *   Pointer to the dev struct.
9899  * @param[in, out] matcher
9900  *   Flow matcher.
9901  * @param[in, out] key
9902  *   Flow matcher value.
9903  * @param[in] item
9904  *   Flow pattern to translate.
9905  * @param[in] inner
9906  *   Item is inner pattern.
9907  */
9908 static void
9909 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9910                                 void *matcher, void *key,
9911                                 const struct rte_flow_item *item)
9912 {
9913         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9914         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9915         void *misc_m =
9916                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9917         void *misc_v =
9918                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9919         struct mlx5_txq_ctrl *txq;
9920         uint32_t queue;
9921
9922
9923         queue_m = (const void *)item->mask;
9924         if (!queue_m)
9925                 return;
9926         queue_v = (const void *)item->spec;
9927         if (!queue_v)
9928                 return;
9929         txq = mlx5_txq_get(dev, queue_v->queue);
9930         if (!txq)
9931                 return;
9932         queue = txq->obj->sq->id;
9933         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9934         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9935                  queue & queue_m->queue);
9936         mlx5_txq_release(dev, queue_v->queue);
9937 }
9938
9939 /**
9940  * Set the hash fields according to the @p flow information.
9941  *
9942  * @param[in] dev_flow
9943  *   Pointer to the mlx5_flow.
9944  * @param[in] rss_desc
9945  *   Pointer to the mlx5_flow_rss_desc.
9946  */
9947 static void
9948 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9949                        struct mlx5_flow_rss_desc *rss_desc)
9950 {
9951         uint64_t items = dev_flow->handle->layers;
9952         int rss_inner = 0;
9953         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9954
9955         dev_flow->hash_fields = 0;
9956 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9957         if (rss_desc->level >= 2) {
9958                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9959                 rss_inner = 1;
9960         }
9961 #endif
9962         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9963             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9964                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9965                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9966                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9967                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9968                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9969                         else
9970                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9971                 }
9972         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9973                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9974                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9975                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9976                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9977                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9978                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9979                         else
9980                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9981                 }
9982         }
9983         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9984             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9985                 if (rss_types & ETH_RSS_UDP) {
9986                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9987                                 dev_flow->hash_fields |=
9988                                                 IBV_RX_HASH_SRC_PORT_UDP;
9989                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9990                                 dev_flow->hash_fields |=
9991                                                 IBV_RX_HASH_DST_PORT_UDP;
9992                         else
9993                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9994                 }
9995         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9996                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9997                 if (rss_types & ETH_RSS_TCP) {
9998                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9999                                 dev_flow->hash_fields |=
10000                                                 IBV_RX_HASH_SRC_PORT_TCP;
10001                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
10002                                 dev_flow->hash_fields |=
10003                                                 IBV_RX_HASH_DST_PORT_TCP;
10004                         else
10005                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
10006                 }
10007         }
10008 }
10009
10010 /**
10011  * Prepare an Rx Hash queue.
10012  *
10013  * @param dev
10014  *   Pointer to Ethernet device.
10015  * @param[in] dev_flow
10016  *   Pointer to the mlx5_flow.
10017  * @param[in] rss_desc
10018  *   Pointer to the mlx5_flow_rss_desc.
10019  * @param[out] hrxq_idx
10020  *   Hash Rx queue index.
10021  *
10022  * @return
10023  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
10024  */
10025 static struct mlx5_hrxq *
10026 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
10027                      struct mlx5_flow *dev_flow,
10028                      struct mlx5_flow_rss_desc *rss_desc,
10029                      uint32_t *hrxq_idx)
10030 {
10031         struct mlx5_priv *priv = dev->data->dev_private;
10032         struct mlx5_flow_handle *dh = dev_flow->handle;
10033         struct mlx5_hrxq *hrxq;
10034
10035         MLX5_ASSERT(rss_desc->queue_num);
10036         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
10037         rss_desc->hash_fields = dev_flow->hash_fields;
10038         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
10039         rss_desc->shared_rss = 0;
10040         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
10041         if (!*hrxq_idx)
10042                 return NULL;
10043         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10044                               *hrxq_idx);
10045         return hrxq;
10046 }
10047
10048 /**
10049  * Release sample sub action resource.
10050  *
10051  * @param[in, out] dev
10052  *   Pointer to rte_eth_dev structure.
10053  * @param[in] act_res
10054  *   Pointer to sample sub action resource.
10055  */
10056 static void
10057 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
10058                                    struct mlx5_flow_sub_actions_idx *act_res)
10059 {
10060         if (act_res->rix_hrxq) {
10061                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
10062                 act_res->rix_hrxq = 0;
10063         }
10064         if (act_res->rix_encap_decap) {
10065                 flow_dv_encap_decap_resource_release(dev,
10066                                                      act_res->rix_encap_decap);
10067                 act_res->rix_encap_decap = 0;
10068         }
10069         if (act_res->rix_port_id_action) {
10070                 flow_dv_port_id_action_resource_release(dev,
10071                                                 act_res->rix_port_id_action);
10072                 act_res->rix_port_id_action = 0;
10073         }
10074         if (act_res->rix_tag) {
10075                 flow_dv_tag_release(dev, act_res->rix_tag);
10076                 act_res->rix_tag = 0;
10077         }
10078         if (act_res->rix_jump) {
10079                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
10080                 act_res->rix_jump = 0;
10081         }
10082 }
10083
10084 int
10085 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
10086                         struct mlx5_cache_entry *entry, void *cb_ctx)
10087 {
10088         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10089         struct rte_eth_dev *dev = ctx->dev;
10090         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10091         struct mlx5_flow_dv_sample_resource *cache_resource =
10092                         container_of(entry, typeof(*cache_resource), entry);
10093
10094         if (resource->ratio == cache_resource->ratio &&
10095             resource->ft_type == cache_resource->ft_type &&
10096             resource->ft_id == cache_resource->ft_id &&
10097             resource->set_action == cache_resource->set_action &&
10098             !memcmp((void *)&resource->sample_act,
10099                     (void *)&cache_resource->sample_act,
10100                     sizeof(struct mlx5_flow_sub_actions_list))) {
10101                 /*
10102                  * Existing sample action should release the prepared
10103                  * sub-actions reference counter.
10104                  */
10105                 flow_dv_sample_sub_actions_release(dev,
10106                                                 &resource->sample_idx);
10107                 return 0;
10108         }
10109         return 1;
10110 }
10111
10112 struct mlx5_cache_entry *
10113 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
10114                          struct mlx5_cache_entry *entry __rte_unused,
10115                          void *cb_ctx)
10116 {
10117         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10118         struct rte_eth_dev *dev = ctx->dev;
10119         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
10120         void **sample_dv_actions = resource->sub_actions;
10121         struct mlx5_flow_dv_sample_resource *cache_resource;
10122         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
10123         struct mlx5_priv *priv = dev->data->dev_private;
10124         struct mlx5_dev_ctx_shared *sh = priv->sh;
10125         struct mlx5_flow_tbl_resource *tbl;
10126         uint32_t idx = 0;
10127         const uint32_t next_ft_step = 1;
10128         uint32_t next_ft_id = resource->ft_id + next_ft_step;
10129         uint8_t is_egress = 0;
10130         uint8_t is_transfer = 0;
10131         struct rte_flow_error *error = ctx->error;
10132
10133         /* Register new sample resource. */
10134         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
10135         if (!cache_resource) {
10136                 rte_flow_error_set(error, ENOMEM,
10137                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10138                                           NULL,
10139                                           "cannot allocate resource memory");
10140                 return NULL;
10141         }
10142         *cache_resource = *resource;
10143         /* Create normal path table level */
10144         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10145                 is_transfer = 1;
10146         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
10147                 is_egress = 1;
10148         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
10149                                         is_egress, is_transfer,
10150                                         true, NULL, 0, 0, 0, error);
10151         if (!tbl) {
10152                 rte_flow_error_set(error, ENOMEM,
10153                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10154                                           NULL,
10155                                           "fail to create normal path table "
10156                                           "for sample");
10157                 goto error;
10158         }
10159         cache_resource->normal_path_tbl = tbl;
10160         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10161                 if (!sh->default_miss_action) {
10162                         rte_flow_error_set(error, ENOMEM,
10163                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10164                                                 NULL,
10165                                                 "default miss action was not "
10166                                                 "created");
10167                         goto error;
10168                 }
10169                 sample_dv_actions[resource->sample_act.actions_num++] =
10170                                                 sh->default_miss_action;
10171         }
10172         /* Create a DR sample action */
10173         sampler_attr.sample_ratio = cache_resource->ratio;
10174         sampler_attr.default_next_table = tbl->obj;
10175         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
10176         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
10177                                                         &sample_dv_actions[0];
10178         sampler_attr.action = cache_resource->set_action;
10179         if (mlx5_os_flow_dr_create_flow_action_sampler
10180                         (&sampler_attr, &cache_resource->verbs_action)) {
10181                 rte_flow_error_set(error, ENOMEM,
10182                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10183                                         NULL, "cannot create sample action");
10184                 goto error;
10185         }
10186         cache_resource->idx = idx;
10187         cache_resource->dev = dev;
10188         return &cache_resource->entry;
10189 error:
10190         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
10191                 flow_dv_sample_sub_actions_release(dev,
10192                                                    &cache_resource->sample_idx);
10193         if (cache_resource->normal_path_tbl)
10194                 flow_dv_tbl_resource_release(MLX5_SH(dev),
10195                                 cache_resource->normal_path_tbl);
10196         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10197         return NULL;
10198
10199 }
10200
10201 /**
10202  * Find existing sample resource or create and register a new one.
10203  *
10204  * @param[in, out] dev
10205  *   Pointer to rte_eth_dev structure.
10206  * @param[in] resource
10207  *   Pointer to sample resource.
10208  * @parm[in, out] dev_flow
10209  *   Pointer to the dev_flow.
10210  * @param[out] error
10211  *   pointer to error structure.
10212  *
10213  * @return
10214  *   0 on success otherwise -errno and errno is set.
10215  */
10216 static int
10217 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10218                          struct mlx5_flow_dv_sample_resource *resource,
10219                          struct mlx5_flow *dev_flow,
10220                          struct rte_flow_error *error)
10221 {
10222         struct mlx5_flow_dv_sample_resource *cache_resource;
10223         struct mlx5_cache_entry *entry;
10224         struct mlx5_priv *priv = dev->data->dev_private;
10225         struct mlx5_flow_cb_ctx ctx = {
10226                 .dev = dev,
10227                 .error = error,
10228                 .data = resource,
10229         };
10230
10231         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10232         if (!entry)
10233                 return -rte_errno;
10234         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10235         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10236         dev_flow->dv.sample_res = cache_resource;
10237         return 0;
10238 }
10239
10240 int
10241 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10242                             struct mlx5_cache_entry *entry, void *cb_ctx)
10243 {
10244         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10245         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10246         struct rte_eth_dev *dev = ctx->dev;
10247         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10248                         container_of(entry, typeof(*cache_resource), entry);
10249         uint32_t idx = 0;
10250
10251         if (resource->num_of_dest == cache_resource->num_of_dest &&
10252             resource->ft_type == cache_resource->ft_type &&
10253             !memcmp((void *)cache_resource->sample_act,
10254                     (void *)resource->sample_act,
10255                    (resource->num_of_dest *
10256                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10257                 /*
10258                  * Existing sample action should release the prepared
10259                  * sub-actions reference counter.
10260                  */
10261                 for (idx = 0; idx < resource->num_of_dest; idx++)
10262                         flow_dv_sample_sub_actions_release(dev,
10263                                         &resource->sample_idx[idx]);
10264                 return 0;
10265         }
10266         return 1;
10267 }
10268
10269 struct mlx5_cache_entry *
10270 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10271                          struct mlx5_cache_entry *entry __rte_unused,
10272                          void *cb_ctx)
10273 {
10274         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10275         struct rte_eth_dev *dev = ctx->dev;
10276         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10277         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10278         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10279         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10280         struct mlx5_priv *priv = dev->data->dev_private;
10281         struct mlx5_dev_ctx_shared *sh = priv->sh;
10282         struct mlx5_flow_sub_actions_list *sample_act;
10283         struct mlx5dv_dr_domain *domain;
10284         uint32_t idx = 0, res_idx = 0;
10285         struct rte_flow_error *error = ctx->error;
10286         uint64_t action_flags;
10287         int ret;
10288
10289         /* Register new destination array resource. */
10290         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10291                                             &res_idx);
10292         if (!cache_resource) {
10293                 rte_flow_error_set(error, ENOMEM,
10294                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10295                                           NULL,
10296                                           "cannot allocate resource memory");
10297                 return NULL;
10298         }
10299         *cache_resource = *resource;
10300         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10301                 domain = sh->fdb_domain;
10302         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10303                 domain = sh->rx_domain;
10304         else
10305                 domain = sh->tx_domain;
10306         for (idx = 0; idx < resource->num_of_dest; idx++) {
10307                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10308                                  mlx5_malloc(MLX5_MEM_ZERO,
10309                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10310                                  0, SOCKET_ID_ANY);
10311                 if (!dest_attr[idx]) {
10312                         rte_flow_error_set(error, ENOMEM,
10313                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10314                                            NULL,
10315                                            "cannot allocate resource memory");
10316                         goto error;
10317                 }
10318                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10319                 sample_act = &resource->sample_act[idx];
10320                 action_flags = sample_act->action_flags;
10321                 switch (action_flags) {
10322                 case MLX5_FLOW_ACTION_QUEUE:
10323                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10324                         break;
10325                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10326                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10327                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10328                         dest_attr[idx]->dest_reformat->reformat =
10329                                         sample_act->dr_encap_action;
10330                         dest_attr[idx]->dest_reformat->dest =
10331                                         sample_act->dr_port_id_action;
10332                         break;
10333                 case MLX5_FLOW_ACTION_PORT_ID:
10334                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10335                         break;
10336                 case MLX5_FLOW_ACTION_JUMP:
10337                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10338                         break;
10339                 default:
10340                         rte_flow_error_set(error, EINVAL,
10341                                            RTE_FLOW_ERROR_TYPE_ACTION,
10342                                            NULL,
10343                                            "unsupported actions type");
10344                         goto error;
10345                 }
10346         }
10347         /* create a dest array actioin */
10348         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10349                                                 (domain,
10350                                                  cache_resource->num_of_dest,
10351                                                  dest_attr,
10352                                                  &cache_resource->action);
10353         if (ret) {
10354                 rte_flow_error_set(error, ENOMEM,
10355                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10356                                    NULL,
10357                                    "cannot create destination array action");
10358                 goto error;
10359         }
10360         cache_resource->idx = res_idx;
10361         cache_resource->dev = dev;
10362         for (idx = 0; idx < resource->num_of_dest; idx++)
10363                 mlx5_free(dest_attr[idx]);
10364         return &cache_resource->entry;
10365 error:
10366         for (idx = 0; idx < resource->num_of_dest; idx++) {
10367                 flow_dv_sample_sub_actions_release(dev,
10368                                 &cache_resource->sample_idx[idx]);
10369                 if (dest_attr[idx])
10370                         mlx5_free(dest_attr[idx]);
10371         }
10372
10373         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10374         return NULL;
10375 }
10376
10377 /**
10378  * Find existing destination array resource or create and register a new one.
10379  *
10380  * @param[in, out] dev
10381  *   Pointer to rte_eth_dev structure.
10382  * @param[in] resource
10383  *   Pointer to destination array resource.
10384  * @parm[in, out] dev_flow
10385  *   Pointer to the dev_flow.
10386  * @param[out] error
10387  *   pointer to error structure.
10388  *
10389  * @return
10390  *   0 on success otherwise -errno and errno is set.
10391  */
10392 static int
10393 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10394                          struct mlx5_flow_dv_dest_array_resource *resource,
10395                          struct mlx5_flow *dev_flow,
10396                          struct rte_flow_error *error)
10397 {
10398         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10399         struct mlx5_priv *priv = dev->data->dev_private;
10400         struct mlx5_cache_entry *entry;
10401         struct mlx5_flow_cb_ctx ctx = {
10402                 .dev = dev,
10403                 .error = error,
10404                 .data = resource,
10405         };
10406
10407         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10408         if (!entry)
10409                 return -rte_errno;
10410         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10411         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10412         dev_flow->dv.dest_array_res = cache_resource;
10413         return 0;
10414 }
10415
10416 /**
10417  * Convert Sample action to DV specification.
10418  *
10419  * @param[in] dev
10420  *   Pointer to rte_eth_dev structure.
10421  * @param[in] action
10422  *   Pointer to sample action structure.
10423  * @param[in, out] dev_flow
10424  *   Pointer to the mlx5_flow.
10425  * @param[in] attr
10426  *   Pointer to the flow attributes.
10427  * @param[in, out] num_of_dest
10428  *   Pointer to the num of destination.
10429  * @param[in, out] sample_actions
10430  *   Pointer to sample actions list.
10431  * @param[in, out] res
10432  *   Pointer to sample resource.
10433  * @param[out] error
10434  *   Pointer to the error structure.
10435  *
10436  * @return
10437  *   0 on success, a negative errno value otherwise and rte_errno is set.
10438  */
10439 static int
10440 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10441                                 const struct rte_flow_action_sample *action,
10442                                 struct mlx5_flow *dev_flow,
10443                                 const struct rte_flow_attr *attr,
10444                                 uint32_t *num_of_dest,
10445                                 void **sample_actions,
10446                                 struct mlx5_flow_dv_sample_resource *res,
10447                                 struct rte_flow_error *error)
10448 {
10449         struct mlx5_priv *priv = dev->data->dev_private;
10450         const struct rte_flow_action *sub_actions;
10451         struct mlx5_flow_sub_actions_list *sample_act;
10452         struct mlx5_flow_sub_actions_idx *sample_idx;
10453         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10454         struct rte_flow *flow = dev_flow->flow;
10455         struct mlx5_flow_rss_desc *rss_desc;
10456         uint64_t action_flags = 0;
10457
10458         MLX5_ASSERT(wks);
10459         rss_desc = &wks->rss_desc;
10460         sample_act = &res->sample_act;
10461         sample_idx = &res->sample_idx;
10462         res->ratio = action->ratio;
10463         sub_actions = action->actions;
10464         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10465                 int type = sub_actions->type;
10466                 uint32_t pre_rix = 0;
10467                 void *pre_r;
10468                 switch (type) {
10469                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10470                 {
10471                         const struct rte_flow_action_queue *queue;
10472                         struct mlx5_hrxq *hrxq;
10473                         uint32_t hrxq_idx;
10474
10475                         queue = sub_actions->conf;
10476                         rss_desc->queue_num = 1;
10477                         rss_desc->queue[0] = queue->index;
10478                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10479                                                     rss_desc, &hrxq_idx);
10480                         if (!hrxq)
10481                                 return rte_flow_error_set
10482                                         (error, rte_errno,
10483                                          RTE_FLOW_ERROR_TYPE_ACTION,
10484                                          NULL,
10485                                          "cannot create fate queue");
10486                         sample_act->dr_queue_action = hrxq->action;
10487                         sample_idx->rix_hrxq = hrxq_idx;
10488                         sample_actions[sample_act->actions_num++] =
10489                                                 hrxq->action;
10490                         (*num_of_dest)++;
10491                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10492                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10493                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10494                         dev_flow->handle->fate_action =
10495                                         MLX5_FLOW_FATE_QUEUE;
10496                         break;
10497                 }
10498                 case RTE_FLOW_ACTION_TYPE_RSS:
10499                 {
10500                         struct mlx5_hrxq *hrxq;
10501                         uint32_t hrxq_idx;
10502                         const struct rte_flow_action_rss *rss;
10503                         const uint8_t *rss_key;
10504
10505                         rss = sub_actions->conf;
10506                         memcpy(rss_desc->queue, rss->queue,
10507                                rss->queue_num * sizeof(uint16_t));
10508                         rss_desc->queue_num = rss->queue_num;
10509                         /* NULL RSS key indicates default RSS key. */
10510                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10511                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10512                         /*
10513                          * rss->level and rss.types should be set in advance
10514                          * when expanding items for RSS.
10515                          */
10516                         flow_dv_hashfields_set(dev_flow, rss_desc);
10517                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10518                                                     rss_desc, &hrxq_idx);
10519                         if (!hrxq)
10520                                 return rte_flow_error_set
10521                                         (error, rte_errno,
10522                                          RTE_FLOW_ERROR_TYPE_ACTION,
10523                                          NULL,
10524                                          "cannot create fate queue");
10525                         sample_act->dr_queue_action = hrxq->action;
10526                         sample_idx->rix_hrxq = hrxq_idx;
10527                         sample_actions[sample_act->actions_num++] =
10528                                                 hrxq->action;
10529                         (*num_of_dest)++;
10530                         action_flags |= MLX5_FLOW_ACTION_RSS;
10531                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10532                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10533                         dev_flow->handle->fate_action =
10534                                         MLX5_FLOW_FATE_QUEUE;
10535                         break;
10536                 }
10537                 case RTE_FLOW_ACTION_TYPE_MARK:
10538                 {
10539                         uint32_t tag_be = mlx5_flow_mark_set
10540                                 (((const struct rte_flow_action_mark *)
10541                                 (sub_actions->conf))->id);
10542
10543                         dev_flow->handle->mark = 1;
10544                         pre_rix = dev_flow->handle->dvh.rix_tag;
10545                         /* Save the mark resource before sample */
10546                         pre_r = dev_flow->dv.tag_resource;
10547                         if (flow_dv_tag_resource_register(dev, tag_be,
10548                                                   dev_flow, error))
10549                                 return -rte_errno;
10550                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10551                         sample_act->dr_tag_action =
10552                                 dev_flow->dv.tag_resource->action;
10553                         sample_idx->rix_tag =
10554                                 dev_flow->handle->dvh.rix_tag;
10555                         sample_actions[sample_act->actions_num++] =
10556                                                 sample_act->dr_tag_action;
10557                         /* Recover the mark resource after sample */
10558                         dev_flow->dv.tag_resource = pre_r;
10559                         dev_flow->handle->dvh.rix_tag = pre_rix;
10560                         action_flags |= MLX5_FLOW_ACTION_MARK;
10561                         break;
10562                 }
10563                 case RTE_FLOW_ACTION_TYPE_COUNT:
10564                 {
10565                         if (!flow->counter) {
10566                                 flow->counter =
10567                                         flow_dv_translate_create_counter(dev,
10568                                                 dev_flow, sub_actions->conf,
10569                                                 0);
10570                                 if (!flow->counter)
10571                                         return rte_flow_error_set
10572                                                 (error, rte_errno,
10573                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10574                                                 NULL,
10575                                                 "cannot create counter"
10576                                                 " object.");
10577                         }
10578                         sample_act->dr_cnt_action =
10579                                   (flow_dv_counter_get_by_idx(dev,
10580                                   flow->counter, NULL))->action;
10581                         sample_actions[sample_act->actions_num++] =
10582                                                 sample_act->dr_cnt_action;
10583                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10584                         break;
10585                 }
10586                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10587                 {
10588                         struct mlx5_flow_dv_port_id_action_resource
10589                                         port_id_resource;
10590                         uint32_t port_id = 0;
10591
10592                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10593                         /* Save the port id resource before sample */
10594                         pre_rix = dev_flow->handle->rix_port_id_action;
10595                         pre_r = dev_flow->dv.port_id_action;
10596                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10597                                                              &port_id, error))
10598                                 return -rte_errno;
10599                         port_id_resource.port_id = port_id;
10600                         if (flow_dv_port_id_action_resource_register
10601                             (dev, &port_id_resource, dev_flow, error))
10602                                 return -rte_errno;
10603                         sample_act->dr_port_id_action =
10604                                 dev_flow->dv.port_id_action->action;
10605                         sample_idx->rix_port_id_action =
10606                                 dev_flow->handle->rix_port_id_action;
10607                         sample_actions[sample_act->actions_num++] =
10608                                                 sample_act->dr_port_id_action;
10609                         /* Recover the port id resource after sample */
10610                         dev_flow->dv.port_id_action = pre_r;
10611                         dev_flow->handle->rix_port_id_action = pre_rix;
10612                         (*num_of_dest)++;
10613                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10614                         break;
10615                 }
10616                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10617                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10618                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10619                         /* Save the encap resource before sample */
10620                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10621                         pre_r = dev_flow->dv.encap_decap;
10622                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10623                                                            dev_flow,
10624                                                            attr->transfer,
10625                                                            error))
10626                                 return -rte_errno;
10627                         sample_act->dr_encap_action =
10628                                 dev_flow->dv.encap_decap->action;
10629                         sample_idx->rix_encap_decap =
10630                                 dev_flow->handle->dvh.rix_encap_decap;
10631                         sample_actions[sample_act->actions_num++] =
10632                                                 sample_act->dr_encap_action;
10633                         /* Recover the encap resource after sample */
10634                         dev_flow->dv.encap_decap = pre_r;
10635                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10636                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10637                         break;
10638                 default:
10639                         return rte_flow_error_set(error, EINVAL,
10640                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10641                                 NULL,
10642                                 "Not support for sampler action");
10643                 }
10644         }
10645         sample_act->action_flags = action_flags;
10646         res->ft_id = dev_flow->dv.group;
10647         if (attr->transfer) {
10648                 union {
10649                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10650                         uint64_t set_action;
10651                 } action_ctx = { .set_action = 0 };
10652
10653                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10654                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10655                          MLX5_MODIFICATION_TYPE_SET);
10656                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10657                          MLX5_MODI_META_REG_C_0);
10658                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10659                          priv->vport_meta_tag);
10660                 res->set_action = action_ctx.set_action;
10661         } else if (attr->ingress) {
10662                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10663         } else {
10664                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10665         }
10666         return 0;
10667 }
10668
10669 /**
10670  * Convert Sample action to DV specification.
10671  *
10672  * @param[in] dev
10673  *   Pointer to rte_eth_dev structure.
10674  * @param[in, out] dev_flow
10675  *   Pointer to the mlx5_flow.
10676  * @param[in] num_of_dest
10677  *   The num of destination.
10678  * @param[in, out] res
10679  *   Pointer to sample resource.
10680  * @param[in, out] mdest_res
10681  *   Pointer to destination array resource.
10682  * @param[in] sample_actions
10683  *   Pointer to sample path actions list.
10684  * @param[in] action_flags
10685  *   Holds the actions detected until now.
10686  * @param[out] error
10687  *   Pointer to the error structure.
10688  *
10689  * @return
10690  *   0 on success, a negative errno value otherwise and rte_errno is set.
10691  */
10692 static int
10693 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10694                              struct mlx5_flow *dev_flow,
10695                              uint32_t num_of_dest,
10696                              struct mlx5_flow_dv_sample_resource *res,
10697                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10698                              void **sample_actions,
10699                              uint64_t action_flags,
10700                              struct rte_flow_error *error)
10701 {
10702         /* update normal path action resource into last index of array */
10703         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10704         struct mlx5_flow_sub_actions_list *sample_act =
10705                                         &mdest_res->sample_act[dest_index];
10706         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10707         struct mlx5_flow_rss_desc *rss_desc;
10708         uint32_t normal_idx = 0;
10709         struct mlx5_hrxq *hrxq;
10710         uint32_t hrxq_idx;
10711
10712         MLX5_ASSERT(wks);
10713         rss_desc = &wks->rss_desc;
10714         if (num_of_dest > 1) {
10715                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10716                         /* Handle QP action for mirroring */
10717                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10718                                                     rss_desc, &hrxq_idx);
10719                         if (!hrxq)
10720                                 return rte_flow_error_set
10721                                      (error, rte_errno,
10722                                       RTE_FLOW_ERROR_TYPE_ACTION,
10723                                       NULL,
10724                                       "cannot create rx queue");
10725                         normal_idx++;
10726                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10727                         sample_act->dr_queue_action = hrxq->action;
10728                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10729                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10730                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10731                 }
10732                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10733                         normal_idx++;
10734                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10735                                 dev_flow->handle->dvh.rix_encap_decap;
10736                         sample_act->dr_encap_action =
10737                                 dev_flow->dv.encap_decap->action;
10738                         dev_flow->handle->dvh.rix_encap_decap = 0;
10739                 }
10740                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10741                         normal_idx++;
10742                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10743                                 dev_flow->handle->rix_port_id_action;
10744                         sample_act->dr_port_id_action =
10745                                 dev_flow->dv.port_id_action->action;
10746                         dev_flow->handle->rix_port_id_action = 0;
10747                 }
10748                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10749                         normal_idx++;
10750                         mdest_res->sample_idx[dest_index].rix_jump =
10751                                 dev_flow->handle->rix_jump;
10752                         sample_act->dr_jump_action =
10753                                 dev_flow->dv.jump->action;
10754                         dev_flow->handle->rix_jump = 0;
10755                 }
10756                 sample_act->actions_num = normal_idx;
10757                 /* update sample action resource into first index of array */
10758                 mdest_res->ft_type = res->ft_type;
10759                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10760                                 sizeof(struct mlx5_flow_sub_actions_idx));
10761                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10762                                 sizeof(struct mlx5_flow_sub_actions_list));
10763                 mdest_res->num_of_dest = num_of_dest;
10764                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10765                                                          dev_flow, error))
10766                         return rte_flow_error_set(error, EINVAL,
10767                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10768                                                   NULL, "can't create sample "
10769                                                   "action");
10770         } else {
10771                 res->sub_actions = sample_actions;
10772                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10773                         return rte_flow_error_set(error, EINVAL,
10774                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10775                                                   NULL,
10776                                                   "can't create sample action");
10777         }
10778         return 0;
10779 }
10780
10781 /**
10782  * Remove an ASO age action from age actions list.
10783  *
10784  * @param[in] dev
10785  *   Pointer to the Ethernet device structure.
10786  * @param[in] age
10787  *   Pointer to the aso age action handler.
10788  */
10789 static void
10790 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10791                                 struct mlx5_aso_age_action *age)
10792 {
10793         struct mlx5_age_info *age_info;
10794         struct mlx5_age_param *age_param = &age->age_params;
10795         struct mlx5_priv *priv = dev->data->dev_private;
10796         uint16_t expected = AGE_CANDIDATE;
10797
10798         age_info = GET_PORT_AGE_INFO(priv);
10799         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10800                                          AGE_FREE, false, __ATOMIC_RELAXED,
10801                                          __ATOMIC_RELAXED)) {
10802                 /**
10803                  * We need the lock even it is age timeout,
10804                  * since age action may still in process.
10805                  */
10806                 rte_spinlock_lock(&age_info->aged_sl);
10807                 LIST_REMOVE(age, next);
10808                 rte_spinlock_unlock(&age_info->aged_sl);
10809                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10810         }
10811 }
10812
10813 /**
10814  * Release an ASO age action.
10815  *
10816  * @param[in] dev
10817  *   Pointer to the Ethernet device structure.
10818  * @param[in] age_idx
10819  *   Index of ASO age action to release.
10820  * @param[in] flow
10821  *   True if the release operation is during flow destroy operation.
10822  *   False if the release operation is during action destroy operation.
10823  *
10824  * @return
10825  *   0 when age action was removed, otherwise the number of references.
10826  */
10827 static int
10828 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10829 {
10830         struct mlx5_priv *priv = dev->data->dev_private;
10831         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10832         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10833         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10834
10835         if (!ret) {
10836                 flow_dv_aso_age_remove_from_age(dev, age);
10837                 rte_spinlock_lock(&mng->free_sl);
10838                 LIST_INSERT_HEAD(&mng->free, age, next);
10839                 rte_spinlock_unlock(&mng->free_sl);
10840         }
10841         return ret;
10842 }
10843
10844 /**
10845  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10846  *
10847  * @param[in] dev
10848  *   Pointer to the Ethernet device structure.
10849  *
10850  * @return
10851  *   0 on success, otherwise negative errno value and rte_errno is set.
10852  */
10853 static int
10854 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10855 {
10856         struct mlx5_priv *priv = dev->data->dev_private;
10857         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10858         void *old_pools = mng->pools;
10859         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10860         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10861         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10862
10863         if (!pools) {
10864                 rte_errno = ENOMEM;
10865                 return -ENOMEM;
10866         }
10867         if (old_pools) {
10868                 memcpy(pools, old_pools,
10869                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10870                 mlx5_free(old_pools);
10871         } else {
10872                 /* First ASO flow hit allocation - starting ASO data-path. */
10873                 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
10874
10875                 if (ret) {
10876                         mlx5_free(pools);
10877                         return ret;
10878                 }
10879         }
10880         mng->n = resize;
10881         mng->pools = pools;
10882         return 0;
10883 }
10884
10885 /**
10886  * Create and initialize a new ASO aging pool.
10887  *
10888  * @param[in] dev
10889  *   Pointer to the Ethernet device structure.
10890  * @param[out] age_free
10891  *   Where to put the pointer of a new age action.
10892  *
10893  * @return
10894  *   The age actions pool pointer and @p age_free is set on success,
10895  *   NULL otherwise and rte_errno is set.
10896  */
10897 static struct mlx5_aso_age_pool *
10898 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10899                         struct mlx5_aso_age_action **age_free)
10900 {
10901         struct mlx5_priv *priv = dev->data->dev_private;
10902         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10903         struct mlx5_aso_age_pool *pool = NULL;
10904         struct mlx5_devx_obj *obj = NULL;
10905         uint32_t i;
10906
10907         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10908                                                     priv->sh->pdn);
10909         if (!obj) {
10910                 rte_errno = ENODATA;
10911                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10912                 return NULL;
10913         }
10914         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10915         if (!pool) {
10916                 claim_zero(mlx5_devx_cmd_destroy(obj));
10917                 rte_errno = ENOMEM;
10918                 return NULL;
10919         }
10920         pool->flow_hit_aso_obj = obj;
10921         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10922         rte_spinlock_lock(&mng->resize_sl);
10923         pool->index = mng->next;
10924         /* Resize pools array if there is no room for the new pool in it. */
10925         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10926                 claim_zero(mlx5_devx_cmd_destroy(obj));
10927                 mlx5_free(pool);
10928                 rte_spinlock_unlock(&mng->resize_sl);
10929                 return NULL;
10930         }
10931         mng->pools[pool->index] = pool;
10932         mng->next++;
10933         rte_spinlock_unlock(&mng->resize_sl);
10934         /* Assign the first action in the new pool, the rest go to free list. */
10935         *age_free = &pool->actions[0];
10936         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10937                 pool->actions[i].offset = i;
10938                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10939         }
10940         return pool;
10941 }
10942
10943 /**
10944  * Allocate a ASO aging bit.
10945  *
10946  * @param[in] dev
10947  *   Pointer to the Ethernet device structure.
10948  * @param[out] error
10949  *   Pointer to the error structure.
10950  *
10951  * @return
10952  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10953  */
10954 static uint32_t
10955 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10956 {
10957         struct mlx5_priv *priv = dev->data->dev_private;
10958         const struct mlx5_aso_age_pool *pool;
10959         struct mlx5_aso_age_action *age_free = NULL;
10960         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10961
10962         MLX5_ASSERT(mng);
10963         /* Try to get the next free age action bit. */
10964         rte_spinlock_lock(&mng->free_sl);
10965         age_free = LIST_FIRST(&mng->free);
10966         if (age_free) {
10967                 LIST_REMOVE(age_free, next);
10968         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10969                 rte_spinlock_unlock(&mng->free_sl);
10970                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10971                                    NULL, "failed to create ASO age pool");
10972                 return 0; /* 0 is an error. */
10973         }
10974         rte_spinlock_unlock(&mng->free_sl);
10975         pool = container_of
10976           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10977                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10978                                                                        actions);
10979         if (!age_free->dr_action) {
10980                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10981                                                  error);
10982
10983                 if (reg_c < 0) {
10984                         rte_flow_error_set(error, rte_errno,
10985                                            RTE_FLOW_ERROR_TYPE_ACTION,
10986                                            NULL, "failed to get reg_c "
10987                                            "for ASO flow hit");
10988                         return 0; /* 0 is an error. */
10989                 }
10990 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10991                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10992                                 (priv->sh->rx_domain,
10993                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10994                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10995                                  (reg_c - REG_C_0));
10996 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10997                 if (!age_free->dr_action) {
10998                         rte_errno = errno;
10999                         rte_spinlock_lock(&mng->free_sl);
11000                         LIST_INSERT_HEAD(&mng->free, age_free, next);
11001                         rte_spinlock_unlock(&mng->free_sl);
11002                         rte_flow_error_set(error, rte_errno,
11003                                            RTE_FLOW_ERROR_TYPE_ACTION,
11004                                            NULL, "failed to create ASO "
11005                                            "flow hit action");
11006                         return 0; /* 0 is an error. */
11007                 }
11008         }
11009         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
11010         return pool->index | ((age_free->offset + 1) << 16);
11011 }
11012
11013 /**
11014  * Create a age action using ASO mechanism.
11015  *
11016  * @param[in] dev
11017  *   Pointer to rte_eth_dev structure.
11018  * @param[in] age
11019  *   Pointer to the aging action configuration.
11020  * @param[out] error
11021  *   Pointer to the error structure.
11022  *
11023  * @return
11024  *   Index to flow counter on success, 0 otherwise.
11025  */
11026 static uint32_t
11027 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
11028                                  const struct rte_flow_action_age *age,
11029                                  struct rte_flow_error *error)
11030 {
11031         uint32_t age_idx = 0;
11032         struct mlx5_aso_age_action *aso_age;
11033
11034         age_idx = flow_dv_aso_age_alloc(dev, error);
11035         if (!age_idx)
11036                 return 0;
11037         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
11038         aso_age->age_params.context = age->context;
11039         aso_age->age_params.timeout = age->timeout;
11040         aso_age->age_params.port_id = dev->data->port_id;
11041         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
11042                          __ATOMIC_RELAXED);
11043         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
11044                          __ATOMIC_RELAXED);
11045         return age_idx;
11046 }
11047
11048 /**
11049  * Fill the flow with DV spec, lock free
11050  * (mutex should be acquired by caller).
11051  *
11052  * @param[in] dev
11053  *   Pointer to rte_eth_dev structure.
11054  * @param[in, out] dev_flow
11055  *   Pointer to the sub flow.
11056  * @param[in] attr
11057  *   Pointer to the flow attributes.
11058  * @param[in] items
11059  *   Pointer to the list of items.
11060  * @param[in] actions
11061  *   Pointer to the list of actions.
11062  * @param[out] error
11063  *   Pointer to the error structure.
11064  *
11065  * @return
11066  *   0 on success, a negative errno value otherwise and rte_errno is set.
11067  */
11068 static int
11069 flow_dv_translate(struct rte_eth_dev *dev,
11070                   struct mlx5_flow *dev_flow,
11071                   const struct rte_flow_attr *attr,
11072                   const struct rte_flow_item items[],
11073                   const struct rte_flow_action actions[],
11074                   struct rte_flow_error *error)
11075 {
11076         struct mlx5_priv *priv = dev->data->dev_private;
11077         struct mlx5_dev_config *dev_conf = &priv->config;
11078         struct rte_flow *flow = dev_flow->flow;
11079         struct mlx5_flow_handle *handle = dev_flow->handle;
11080         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11081         struct mlx5_flow_rss_desc *rss_desc;
11082         uint64_t item_flags = 0;
11083         uint64_t last_item = 0;
11084         uint64_t action_flags = 0;
11085         struct mlx5_flow_dv_matcher matcher = {
11086                 .mask = {
11087                         .size = sizeof(matcher.mask.buf) -
11088                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
11089                 },
11090         };
11091         int actions_n = 0;
11092         bool actions_end = false;
11093         union {
11094                 struct mlx5_flow_dv_modify_hdr_resource res;
11095                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
11096                             sizeof(struct mlx5_modification_cmd) *
11097                             (MLX5_MAX_MODIFY_NUM + 1)];
11098         } mhdr_dummy;
11099         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
11100         const struct rte_flow_action_count *count = NULL;
11101         const struct rte_flow_action_age *age = NULL;
11102         union flow_dv_attr flow_attr = { .attr = 0 };
11103         uint32_t tag_be;
11104         union mlx5_flow_tbl_key tbl_key;
11105         uint32_t modify_action_position = UINT32_MAX;
11106         void *match_mask = matcher.mask.buf;
11107         void *match_value = dev_flow->dv.value.buf;
11108         uint8_t next_protocol = 0xff;
11109         struct rte_vlan_hdr vlan = { 0 };
11110         struct mlx5_flow_dv_dest_array_resource mdest_res;
11111         struct mlx5_flow_dv_sample_resource sample_res;
11112         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11113         const struct rte_flow_action_sample *sample = NULL;
11114         struct mlx5_flow_sub_actions_list *sample_act;
11115         uint32_t sample_act_pos = UINT32_MAX;
11116         uint32_t num_of_dest = 0;
11117         int tmp_actions_n = 0;
11118         uint32_t table;
11119         int ret = 0;
11120         const struct mlx5_flow_tunnel *tunnel;
11121         struct flow_grp_info grp_info = {
11122                 .external = !!dev_flow->external,
11123                 .transfer = !!attr->transfer,
11124                 .fdb_def_rule = !!priv->fdb_def_rule,
11125                 .skip_scale = dev_flow->skip_scale &
11126                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
11127         };
11128
11129         if (!wks)
11130                 return rte_flow_error_set(error, ENOMEM,
11131                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11132                                           NULL,
11133                                           "failed to push flow workspace");
11134         rss_desc = &wks->rss_desc;
11135         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
11136         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
11137         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11138                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11139         /* update normal path action resource into last index of array */
11140         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
11141         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
11142                  flow_items_to_tunnel(items) :
11143                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
11144                  flow_actions_to_tunnel(actions) :
11145                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
11146         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
11147                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11148         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
11149                                 (dev, tunnel, attr, items, actions);
11150         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
11151                                        &grp_info, error);
11152         if (ret)
11153                 return ret;
11154         dev_flow->dv.group = table;
11155         if (attr->transfer)
11156                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11157         /* number of actions must be set to 0 in case of dirty stack. */
11158         mhdr_res->actions_num = 0;
11159         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
11160                 /*
11161                  * do not add decap action if match rule drops packet
11162                  * HW rejects rules with decap & drop
11163                  *
11164                  * if tunnel match rule was inserted before matching tunnel set
11165                  * rule flow table used in the match rule must be registered.
11166                  * current implementation handles that in the
11167                  * flow_dv_match_register() at the function end.
11168                  */
11169                 bool add_decap = true;
11170                 const struct rte_flow_action *ptr = actions;
11171
11172                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
11173                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
11174                                 add_decap = false;
11175                                 break;
11176                         }
11177                 }
11178                 if (add_decap) {
11179                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11180                                                            attr->transfer,
11181                                                            error))
11182                                 return -rte_errno;
11183                         dev_flow->dv.actions[actions_n++] =
11184                                         dev_flow->dv.encap_decap->action;
11185                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11186                 }
11187         }
11188         for (; !actions_end ; actions++) {
11189                 const struct rte_flow_action_queue *queue;
11190                 const struct rte_flow_action_rss *rss;
11191                 const struct rte_flow_action *action = actions;
11192                 const uint8_t *rss_key;
11193                 struct mlx5_flow_tbl_resource *tbl;
11194                 struct mlx5_aso_age_action *age_act;
11195                 uint32_t port_id = 0;
11196                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
11197                 int action_type = actions->type;
11198                 const struct rte_flow_action *found_action = NULL;
11199                 uint32_t jump_group = 0;
11200
11201                 if (!mlx5_flow_os_action_supported(action_type))
11202                         return rte_flow_error_set(error, ENOTSUP,
11203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11204                                                   actions,
11205                                                   "action not supported");
11206                 switch (action_type) {
11207                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11208                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11209                         break;
11210                 case RTE_FLOW_ACTION_TYPE_VOID:
11211                         break;
11212                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11213                         if (flow_dv_translate_action_port_id(dev, action,
11214                                                              &port_id, error))
11215                                 return -rte_errno;
11216                         port_id_resource.port_id = port_id;
11217                         MLX5_ASSERT(!handle->rix_port_id_action);
11218                         if (flow_dv_port_id_action_resource_register
11219                             (dev, &port_id_resource, dev_flow, error))
11220                                 return -rte_errno;
11221                         dev_flow->dv.actions[actions_n++] =
11222                                         dev_flow->dv.port_id_action->action;
11223                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11224                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11225                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11226                         num_of_dest++;
11227                         break;
11228                 case RTE_FLOW_ACTION_TYPE_FLAG:
11229                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11230                         dev_flow->handle->mark = 1;
11231                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11232                                 struct rte_flow_action_mark mark = {
11233                                         .id = MLX5_FLOW_MARK_DEFAULT,
11234                                 };
11235
11236                                 if (flow_dv_convert_action_mark(dev, &mark,
11237                                                                 mhdr_res,
11238                                                                 error))
11239                                         return -rte_errno;
11240                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11241                                 break;
11242                         }
11243                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11244                         /*
11245                          * Only one FLAG or MARK is supported per device flow
11246                          * right now. So the pointer to the tag resource must be
11247                          * zero before the register process.
11248                          */
11249                         MLX5_ASSERT(!handle->dvh.rix_tag);
11250                         if (flow_dv_tag_resource_register(dev, tag_be,
11251                                                           dev_flow, error))
11252                                 return -rte_errno;
11253                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11254                         dev_flow->dv.actions[actions_n++] =
11255                                         dev_flow->dv.tag_resource->action;
11256                         break;
11257                 case RTE_FLOW_ACTION_TYPE_MARK:
11258                         action_flags |= MLX5_FLOW_ACTION_MARK;
11259                         dev_flow->handle->mark = 1;
11260                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11261                                 const struct rte_flow_action_mark *mark =
11262                                         (const struct rte_flow_action_mark *)
11263                                                 actions->conf;
11264
11265                                 if (flow_dv_convert_action_mark(dev, mark,
11266                                                                 mhdr_res,
11267                                                                 error))
11268                                         return -rte_errno;
11269                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11270                                 break;
11271                         }
11272                         /* Fall-through */
11273                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11274                         /* Legacy (non-extensive) MARK action. */
11275                         tag_be = mlx5_flow_mark_set
11276                               (((const struct rte_flow_action_mark *)
11277                                (actions->conf))->id);
11278                         MLX5_ASSERT(!handle->dvh.rix_tag);
11279                         if (flow_dv_tag_resource_register(dev, tag_be,
11280                                                           dev_flow, error))
11281                                 return -rte_errno;
11282                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11283                         dev_flow->dv.actions[actions_n++] =
11284                                         dev_flow->dv.tag_resource->action;
11285                         break;
11286                 case RTE_FLOW_ACTION_TYPE_SET_META:
11287                         if (flow_dv_convert_action_set_meta
11288                                 (dev, mhdr_res, attr,
11289                                  (const struct rte_flow_action_set_meta *)
11290                                   actions->conf, error))
11291                                 return -rte_errno;
11292                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11293                         break;
11294                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11295                         if (flow_dv_convert_action_set_tag
11296                                 (dev, mhdr_res,
11297                                  (const struct rte_flow_action_set_tag *)
11298                                   actions->conf, error))
11299                                 return -rte_errno;
11300                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11301                         break;
11302                 case RTE_FLOW_ACTION_TYPE_DROP:
11303                         action_flags |= MLX5_FLOW_ACTION_DROP;
11304                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11305                         break;
11306                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11307                         queue = actions->conf;
11308                         rss_desc->queue_num = 1;
11309                         rss_desc->queue[0] = queue->index;
11310                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11311                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11312                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11313                         num_of_dest++;
11314                         break;
11315                 case RTE_FLOW_ACTION_TYPE_RSS:
11316                         rss = actions->conf;
11317                         memcpy(rss_desc->queue, rss->queue,
11318                                rss->queue_num * sizeof(uint16_t));
11319                         rss_desc->queue_num = rss->queue_num;
11320                         /* NULL RSS key indicates default RSS key. */
11321                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11322                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11323                         /*
11324                          * rss->level and rss.types should be set in advance
11325                          * when expanding items for RSS.
11326                          */
11327                         action_flags |= MLX5_FLOW_ACTION_RSS;
11328                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11329                                 MLX5_FLOW_FATE_SHARED_RSS :
11330                                 MLX5_FLOW_FATE_QUEUE;
11331                         break;
11332                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11333                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11334                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11335                         __atomic_fetch_add(&age_act->refcnt, 1,
11336                                            __ATOMIC_RELAXED);
11337                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11338                         action_flags |= MLX5_FLOW_ACTION_AGE;
11339                         break;
11340                 case RTE_FLOW_ACTION_TYPE_AGE:
11341                         if (priv->sh->flow_hit_aso_en && attr->group) {
11342                                 /*
11343                                  * Create one shared age action, to be used
11344                                  * by all sub-flows.
11345                                  */
11346                                 if (!flow->age) {
11347                                         flow->age =
11348                                                 flow_dv_translate_create_aso_age
11349                                                         (dev, action->conf,
11350                                                          error);
11351                                         if (!flow->age)
11352                                                 return rte_flow_error_set
11353                                                 (error, rte_errno,
11354                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11355                                                  NULL,
11356                                                  "can't create ASO age action");
11357                                 }
11358                                 dev_flow->dv.actions[actions_n++] =
11359                                           (flow_aso_age_get_by_idx
11360                                                 (dev, flow->age))->dr_action;
11361                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11362                                 break;
11363                         }
11364                         /* Fall-through */
11365                 case RTE_FLOW_ACTION_TYPE_COUNT:
11366                         if (!dev_conf->devx) {
11367                                 return rte_flow_error_set
11368                                               (error, ENOTSUP,
11369                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11370                                                NULL,
11371                                                "count action not supported");
11372                         }
11373                         /* Save information first, will apply later. */
11374                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11375                                 count = action->conf;
11376                         else
11377                                 age = action->conf;
11378                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11379                         break;
11380                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11381                         dev_flow->dv.actions[actions_n++] =
11382                                                 priv->sh->pop_vlan_action;
11383                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11384                         break;
11385                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11386                         if (!(action_flags &
11387                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11388                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11389                         vlan.eth_proto = rte_be_to_cpu_16
11390                              ((((const struct rte_flow_action_of_push_vlan *)
11391                                                    actions->conf)->ethertype));
11392                         found_action = mlx5_flow_find_action
11393                                         (actions + 1,
11394                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11395                         if (found_action)
11396                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11397                         found_action = mlx5_flow_find_action
11398                                         (actions + 1,
11399                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11400                         if (found_action)
11401                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11402                         if (flow_dv_create_action_push_vlan
11403                                             (dev, attr, &vlan, dev_flow, error))
11404                                 return -rte_errno;
11405                         dev_flow->dv.actions[actions_n++] =
11406                                         dev_flow->dv.push_vlan_res->action;
11407                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11408                         break;
11409                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11410                         /* of_vlan_push action handled this action */
11411                         MLX5_ASSERT(action_flags &
11412                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11413                         break;
11414                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11415                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11416                                 break;
11417                         flow_dev_get_vlan_info_from_items(items, &vlan);
11418                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11419                         /* If no VLAN push - this is a modify header action */
11420                         if (flow_dv_convert_action_modify_vlan_vid
11421                                                 (mhdr_res, actions, error))
11422                                 return -rte_errno;
11423                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11424                         break;
11425                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11426                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11427                         if (flow_dv_create_action_l2_encap(dev, actions,
11428                                                            dev_flow,
11429                                                            attr->transfer,
11430                                                            error))
11431                                 return -rte_errno;
11432                         dev_flow->dv.actions[actions_n++] =
11433                                         dev_flow->dv.encap_decap->action;
11434                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11435                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11436                                 sample_act->action_flags |=
11437                                                         MLX5_FLOW_ACTION_ENCAP;
11438                         break;
11439                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11440                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11441                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11442                                                            attr->transfer,
11443                                                            error))
11444                                 return -rte_errno;
11445                         dev_flow->dv.actions[actions_n++] =
11446                                         dev_flow->dv.encap_decap->action;
11447                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11448                         break;
11449                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11450                         /* Handle encap with preceding decap. */
11451                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11452                                 if (flow_dv_create_action_raw_encap
11453                                         (dev, actions, dev_flow, attr, error))
11454                                         return -rte_errno;
11455                                 dev_flow->dv.actions[actions_n++] =
11456                                         dev_flow->dv.encap_decap->action;
11457                         } else {
11458                                 /* Handle encap without preceding decap. */
11459                                 if (flow_dv_create_action_l2_encap
11460                                     (dev, actions, dev_flow, attr->transfer,
11461                                      error))
11462                                         return -rte_errno;
11463                                 dev_flow->dv.actions[actions_n++] =
11464                                         dev_flow->dv.encap_decap->action;
11465                         }
11466                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11467                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11468                                 sample_act->action_flags |=
11469                                                         MLX5_FLOW_ACTION_ENCAP;
11470                         break;
11471                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11472                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11473                                 ;
11474                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11475                                 if (flow_dv_create_action_l2_decap
11476                                     (dev, dev_flow, attr->transfer, error))
11477                                         return -rte_errno;
11478                                 dev_flow->dv.actions[actions_n++] =
11479                                         dev_flow->dv.encap_decap->action;
11480                         }
11481                         /* If decap is followed by encap, handle it at encap. */
11482                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11483                         break;
11484                 case RTE_FLOW_ACTION_TYPE_JUMP:
11485                         jump_group = ((const struct rte_flow_action_jump *)
11486                                                         action->conf)->group;
11487                         grp_info.std_tbl_fix = 0;
11488                         if (dev_flow->skip_scale &
11489                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11490                                 grp_info.skip_scale = 1;
11491                         else
11492                                 grp_info.skip_scale = 0;
11493                         ret = mlx5_flow_group_to_table(dev, tunnel,
11494                                                        jump_group,
11495                                                        &table,
11496                                                        &grp_info, error);
11497                         if (ret)
11498                                 return ret;
11499                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11500                                                        attr->transfer,
11501                                                        !!dev_flow->external,
11502                                                        tunnel, jump_group, 0,
11503                                                        0, error);
11504                         if (!tbl)
11505                                 return rte_flow_error_set
11506                                                 (error, errno,
11507                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11508                                                  NULL,
11509                                                  "cannot create jump action.");
11510                         if (flow_dv_jump_tbl_resource_register
11511                             (dev, tbl, dev_flow, error)) {
11512                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11513                                 return rte_flow_error_set
11514                                                 (error, errno,
11515                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11516                                                  NULL,
11517                                                  "cannot create jump action.");
11518                         }
11519                         dev_flow->dv.actions[actions_n++] =
11520                                         dev_flow->dv.jump->action;
11521                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11522                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11523                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11524                         num_of_dest++;
11525                         break;
11526                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11527                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11528                         if (flow_dv_convert_action_modify_mac
11529                                         (mhdr_res, actions, error))
11530                                 return -rte_errno;
11531                         action_flags |= actions->type ==
11532                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11533                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11534                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11535                         break;
11536                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11537                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11538                         if (flow_dv_convert_action_modify_ipv4
11539                                         (mhdr_res, actions, error))
11540                                 return -rte_errno;
11541                         action_flags |= actions->type ==
11542                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11543                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11544                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11545                         break;
11546                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11547                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11548                         if (flow_dv_convert_action_modify_ipv6
11549                                         (mhdr_res, actions, error))
11550                                 return -rte_errno;
11551                         action_flags |= actions->type ==
11552                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11553                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11554                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11555                         break;
11556                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11557                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11558                         if (flow_dv_convert_action_modify_tp
11559                                         (mhdr_res, actions, items,
11560                                          &flow_attr, dev_flow, !!(action_flags &
11561                                          MLX5_FLOW_ACTION_DECAP), error))
11562                                 return -rte_errno;
11563                         action_flags |= actions->type ==
11564                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11565                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11566                                         MLX5_FLOW_ACTION_SET_TP_DST;
11567                         break;
11568                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11569                         if (flow_dv_convert_action_modify_dec_ttl
11570                                         (mhdr_res, items, &flow_attr, dev_flow,
11571                                          !!(action_flags &
11572                                          MLX5_FLOW_ACTION_DECAP), error))
11573                                 return -rte_errno;
11574                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11575                         break;
11576                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11577                         if (flow_dv_convert_action_modify_ttl
11578                                         (mhdr_res, actions, items, &flow_attr,
11579                                          dev_flow, !!(action_flags &
11580                                          MLX5_FLOW_ACTION_DECAP), error))
11581                                 return -rte_errno;
11582                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11583                         break;
11584                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11585                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11586                         if (flow_dv_convert_action_modify_tcp_seq
11587                                         (mhdr_res, actions, error))
11588                                 return -rte_errno;
11589                         action_flags |= actions->type ==
11590                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11591                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11592                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11593                         break;
11594
11595                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11596                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11597                         if (flow_dv_convert_action_modify_tcp_ack
11598                                         (mhdr_res, actions, error))
11599                                 return -rte_errno;
11600                         action_flags |= actions->type ==
11601                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11602                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11603                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11604                         break;
11605                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11606                         if (flow_dv_convert_action_set_reg
11607                                         (mhdr_res, actions, error))
11608                                 return -rte_errno;
11609                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11610                         break;
11611                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11612                         if (flow_dv_convert_action_copy_mreg
11613                                         (dev, mhdr_res, actions, error))
11614                                 return -rte_errno;
11615                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11616                         break;
11617                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11618                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11619                         dev_flow->handle->fate_action =
11620                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11621                         break;
11622                 case RTE_FLOW_ACTION_TYPE_METER:
11623                         if (!wks->fm)
11624                                 return rte_flow_error_set(error, rte_errno,
11625                                         RTE_FLOW_ERROR_TYPE_ACTION,
11626                                         NULL, "Failed to get meter in flow.");
11627                         /* Set the meter action. */
11628                         dev_flow->dv.actions[actions_n++] =
11629                                 wks->fm->meter_action;
11630                         action_flags |= MLX5_FLOW_ACTION_METER;
11631                         break;
11632                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11633                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11634                                                               actions, error))
11635                                 return -rte_errno;
11636                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11637                         break;
11638                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11639                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11640                                                               actions, error))
11641                                 return -rte_errno;
11642                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11643                         break;
11644                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11645                         sample_act_pos = actions_n;
11646                         sample = (const struct rte_flow_action_sample *)
11647                                  action->conf;
11648                         actions_n++;
11649                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11650                         /* put encap action into group if work with port id */
11651                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11652                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11653                                 sample_act->action_flags |=
11654                                                         MLX5_FLOW_ACTION_ENCAP;
11655                         break;
11656                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11657                         if (flow_dv_convert_action_modify_field
11658                                         (dev, mhdr_res, actions, attr, error))
11659                                 return -rte_errno;
11660                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11661                         break;
11662                 case RTE_FLOW_ACTION_TYPE_END:
11663                         actions_end = true;
11664                         if (mhdr_res->actions_num) {
11665                                 /* create modify action if needed. */
11666                                 if (flow_dv_modify_hdr_resource_register
11667                                         (dev, mhdr_res, dev_flow, error))
11668                                         return -rte_errno;
11669                                 dev_flow->dv.actions[modify_action_position] =
11670                                         handle->dvh.modify_hdr->action;
11671                         }
11672                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11673                                 /*
11674                                  * Create one count action, to be used
11675                                  * by all sub-flows.
11676                                  */
11677                                 if (!flow->counter) {
11678                                         flow->counter =
11679                                                 flow_dv_translate_create_counter
11680                                                         (dev, dev_flow, count,
11681                                                          age);
11682                                         if (!flow->counter)
11683                                                 return rte_flow_error_set
11684                                                 (error, rte_errno,
11685                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11686                                                  NULL, "cannot create counter"
11687                                                  " object.");
11688                                 }
11689                                 dev_flow->dv.actions[actions_n] =
11690                                           (flow_dv_counter_get_by_idx(dev,
11691                                           flow->counter, NULL))->action;
11692                                 actions_n++;
11693                         }
11694                 default:
11695                         break;
11696                 }
11697                 if (mhdr_res->actions_num &&
11698                     modify_action_position == UINT32_MAX)
11699                         modify_action_position = actions_n++;
11700         }
11701         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11702                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11703                 int item_type = items->type;
11704
11705                 if (!mlx5_flow_os_item_supported(item_type))
11706                         return rte_flow_error_set(error, ENOTSUP,
11707                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11708                                                   NULL, "item not supported");
11709                 switch (item_type) {
11710                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11711                         flow_dv_translate_item_port_id
11712                                 (dev, match_mask, match_value, items, attr);
11713                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11714                         break;
11715                 case RTE_FLOW_ITEM_TYPE_ETH:
11716                         flow_dv_translate_item_eth(match_mask, match_value,
11717                                                    items, tunnel,
11718                                                    dev_flow->dv.group);
11719                         matcher.priority = action_flags &
11720                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11721                                         !dev_flow->external ?
11722                                         MLX5_PRIORITY_MAP_L3 :
11723                                         MLX5_PRIORITY_MAP_L2;
11724                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11725                                              MLX5_FLOW_LAYER_OUTER_L2;
11726                         break;
11727                 case RTE_FLOW_ITEM_TYPE_VLAN:
11728                         flow_dv_translate_item_vlan(dev_flow,
11729                                                     match_mask, match_value,
11730                                                     items, tunnel,
11731                                                     dev_flow->dv.group);
11732                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11733                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11734                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11735                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11736                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11737                         break;
11738                 case RTE_FLOW_ITEM_TYPE_IPV4:
11739                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11740                                                   &item_flags, &tunnel);
11741                         flow_dv_translate_item_ipv4(match_mask, match_value,
11742                                                     items, tunnel,
11743                                                     dev_flow->dv.group);
11744                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11745                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11746                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11747                         if (items->mask != NULL &&
11748                             ((const struct rte_flow_item_ipv4 *)
11749                              items->mask)->hdr.next_proto_id) {
11750                                 next_protocol =
11751                                         ((const struct rte_flow_item_ipv4 *)
11752                                          (items->spec))->hdr.next_proto_id;
11753                                 next_protocol &=
11754                                         ((const struct rte_flow_item_ipv4 *)
11755                                          (items->mask))->hdr.next_proto_id;
11756                         } else {
11757                                 /* Reset for inner layer. */
11758                                 next_protocol = 0xff;
11759                         }
11760                         break;
11761                 case RTE_FLOW_ITEM_TYPE_IPV6:
11762                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11763                                                   &item_flags, &tunnel);
11764                         flow_dv_translate_item_ipv6(match_mask, match_value,
11765                                                     items, tunnel,
11766                                                     dev_flow->dv.group);
11767                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11768                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11769                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11770                         if (items->mask != NULL &&
11771                             ((const struct rte_flow_item_ipv6 *)
11772                              items->mask)->hdr.proto) {
11773                                 next_protocol =
11774                                         ((const struct rte_flow_item_ipv6 *)
11775                                          items->spec)->hdr.proto;
11776                                 next_protocol &=
11777                                         ((const struct rte_flow_item_ipv6 *)
11778                                          items->mask)->hdr.proto;
11779                         } else {
11780                                 /* Reset for inner layer. */
11781                                 next_protocol = 0xff;
11782                         }
11783                         break;
11784                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11785                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11786                                                              match_value,
11787                                                              items, tunnel);
11788                         last_item = tunnel ?
11789                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11790                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11791                         if (items->mask != NULL &&
11792                             ((const struct rte_flow_item_ipv6_frag_ext *)
11793                              items->mask)->hdr.next_header) {
11794                                 next_protocol =
11795                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11796                                  items->spec)->hdr.next_header;
11797                                 next_protocol &=
11798                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11799                                  items->mask)->hdr.next_header;
11800                         } else {
11801                                 /* Reset for inner layer. */
11802                                 next_protocol = 0xff;
11803                         }
11804                         break;
11805                 case RTE_FLOW_ITEM_TYPE_TCP:
11806                         flow_dv_translate_item_tcp(match_mask, match_value,
11807                                                    items, tunnel);
11808                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11809                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11810                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11811                         break;
11812                 case RTE_FLOW_ITEM_TYPE_UDP:
11813                         flow_dv_translate_item_udp(match_mask, match_value,
11814                                                    items, tunnel);
11815                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11816                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11817                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11818                         break;
11819                 case RTE_FLOW_ITEM_TYPE_GRE:
11820                         flow_dv_translate_item_gre(match_mask, match_value,
11821                                                    items, tunnel);
11822                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11823                         last_item = MLX5_FLOW_LAYER_GRE;
11824                         break;
11825                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11826                         flow_dv_translate_item_gre_key(match_mask,
11827                                                        match_value, items);
11828                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11829                         break;
11830                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11831                         flow_dv_translate_item_nvgre(match_mask, match_value,
11832                                                      items, tunnel);
11833                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11834                         last_item = MLX5_FLOW_LAYER_GRE;
11835                         break;
11836                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11837                         flow_dv_translate_item_vxlan(match_mask, match_value,
11838                                                      items, tunnel);
11839                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11840                         last_item = MLX5_FLOW_LAYER_VXLAN;
11841                         break;
11842                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11843                         flow_dv_translate_item_vxlan_gpe(match_mask,
11844                                                          match_value, items,
11845                                                          tunnel);
11846                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11847                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11848                         break;
11849                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11850                         flow_dv_translate_item_geneve(match_mask, match_value,
11851                                                       items, tunnel);
11852                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11853                         last_item = MLX5_FLOW_LAYER_GENEVE;
11854                         break;
11855                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11856                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11857                                                           match_value,
11858                                                           items, error);
11859                         if (ret)
11860                                 return rte_flow_error_set(error, -ret,
11861                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11862                                         "cannot create GENEVE TLV option");
11863                         flow->geneve_tlv_option = 1;
11864                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11865                         break;
11866                 case RTE_FLOW_ITEM_TYPE_MPLS:
11867                         flow_dv_translate_item_mpls(match_mask, match_value,
11868                                                     items, last_item, tunnel);
11869                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11870                         last_item = MLX5_FLOW_LAYER_MPLS;
11871                         break;
11872                 case RTE_FLOW_ITEM_TYPE_MARK:
11873                         flow_dv_translate_item_mark(dev, match_mask,
11874                                                     match_value, items);
11875                         last_item = MLX5_FLOW_ITEM_MARK;
11876                         break;
11877                 case RTE_FLOW_ITEM_TYPE_META:
11878                         flow_dv_translate_item_meta(dev, match_mask,
11879                                                     match_value, attr, items);
11880                         last_item = MLX5_FLOW_ITEM_METADATA;
11881                         break;
11882                 case RTE_FLOW_ITEM_TYPE_ICMP:
11883                         flow_dv_translate_item_icmp(match_mask, match_value,
11884                                                     items, tunnel);
11885                         last_item = MLX5_FLOW_LAYER_ICMP;
11886                         break;
11887                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11888                         flow_dv_translate_item_icmp6(match_mask, match_value,
11889                                                       items, tunnel);
11890                         last_item = MLX5_FLOW_LAYER_ICMP6;
11891                         break;
11892                 case RTE_FLOW_ITEM_TYPE_TAG:
11893                         flow_dv_translate_item_tag(dev, match_mask,
11894                                                    match_value, items);
11895                         last_item = MLX5_FLOW_ITEM_TAG;
11896                         break;
11897                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11898                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11899                                                         match_value, items);
11900                         last_item = MLX5_FLOW_ITEM_TAG;
11901                         break;
11902                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11903                         flow_dv_translate_item_tx_queue(dev, match_mask,
11904                                                         match_value,
11905                                                         items);
11906                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11907                         break;
11908                 case RTE_FLOW_ITEM_TYPE_GTP:
11909                         flow_dv_translate_item_gtp(match_mask, match_value,
11910                                                    items, tunnel);
11911                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11912                         last_item = MLX5_FLOW_LAYER_GTP;
11913                         break;
11914                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11915                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11916                                                           match_value,
11917                                                           items);
11918                         if (ret)
11919                                 return rte_flow_error_set(error, -ret,
11920                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11921                                         "cannot create GTP PSC item");
11922                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11923                         break;
11924                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11925                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11926                                 /* Create it only the first time to be used. */
11927                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11928                                 if (ret)
11929                                         return rte_flow_error_set
11930                                                 (error, -ret,
11931                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11932                                                 NULL,
11933                                                 "cannot create eCPRI parser");
11934                         }
11935                         /* Adjust the length matcher and device flow value. */
11936                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11937                         dev_flow->dv.value.size =
11938                                         MLX5_ST_SZ_BYTES(fte_match_param);
11939                         flow_dv_translate_item_ecpri(dev, match_mask,
11940                                                      match_value, items);
11941                         /* No other protocol should follow eCPRI layer. */
11942                         last_item = MLX5_FLOW_LAYER_ECPRI;
11943                         break;
11944                 default:
11945                         break;
11946                 }
11947                 item_flags |= last_item;
11948         }
11949         /*
11950          * When E-Switch mode is enabled, we have two cases where we need to
11951          * set the source port manually.
11952          * The first one, is in case of Nic steering rule, and the second is
11953          * E-Switch rule where no port_id item was found. In both cases
11954          * the source port is set according the current port in use.
11955          */
11956         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11957             (priv->representor || priv->master)) {
11958                 if (flow_dv_translate_item_port_id(dev, match_mask,
11959                                                    match_value, NULL, attr))
11960                         return -rte_errno;
11961         }
11962 #ifdef RTE_LIBRTE_MLX5_DEBUG
11963         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11964                                               dev_flow->dv.value.buf));
11965 #endif
11966         /*
11967          * Layers may be already initialized from prefix flow if this dev_flow
11968          * is the suffix flow.
11969          */
11970         handle->layers |= item_flags;
11971         if (action_flags & MLX5_FLOW_ACTION_RSS)
11972                 flow_dv_hashfields_set(dev_flow, rss_desc);
11973         /* If has RSS action in the sample action, the Sample/Mirror resource
11974          * should be registered after the hash filed be update.
11975          */
11976         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11977                 ret = flow_dv_translate_action_sample(dev,
11978                                                       sample,
11979                                                       dev_flow, attr,
11980                                                       &num_of_dest,
11981                                                       sample_actions,
11982                                                       &sample_res,
11983                                                       error);
11984                 if (ret < 0)
11985                         return ret;
11986                 ret = flow_dv_create_action_sample(dev,
11987                                                    dev_flow,
11988                                                    num_of_dest,
11989                                                    &sample_res,
11990                                                    &mdest_res,
11991                                                    sample_actions,
11992                                                    action_flags,
11993                                                    error);
11994                 if (ret < 0)
11995                         return rte_flow_error_set
11996                                                 (error, rte_errno,
11997                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11998                                                 NULL,
11999                                                 "cannot create sample action");
12000                 if (num_of_dest > 1) {
12001                         dev_flow->dv.actions[sample_act_pos] =
12002                         dev_flow->dv.dest_array_res->action;
12003                 } else {
12004                         dev_flow->dv.actions[sample_act_pos] =
12005                         dev_flow->dv.sample_res->verbs_action;
12006                 }
12007         }
12008         /*
12009          * For multiple destination (sample action with ratio=1), the encap
12010          * action and port id action will be combined into group action.
12011          * So need remove the original these actions in the flow and only
12012          * use the sample action instead of.
12013          */
12014         if (num_of_dest > 1 &&
12015             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
12016                 int i;
12017                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12018
12019                 for (i = 0; i < actions_n; i++) {
12020                         if ((sample_act->dr_encap_action &&
12021                                 sample_act->dr_encap_action ==
12022                                 dev_flow->dv.actions[i]) ||
12023                                 (sample_act->dr_port_id_action &&
12024                                 sample_act->dr_port_id_action ==
12025                                 dev_flow->dv.actions[i]) ||
12026                                 (sample_act->dr_jump_action &&
12027                                 sample_act->dr_jump_action ==
12028                                 dev_flow->dv.actions[i]))
12029                                 continue;
12030                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
12031                 }
12032                 memcpy((void *)dev_flow->dv.actions,
12033                                 (void *)temp_actions,
12034                                 tmp_actions_n * sizeof(void *));
12035                 actions_n = tmp_actions_n;
12036         }
12037         dev_flow->dv.actions_n = actions_n;
12038         dev_flow->act_flags = action_flags;
12039         /* Register matcher. */
12040         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
12041                                     matcher.mask.size);
12042         matcher.priority = mlx5_get_matcher_priority(dev, attr,
12043                                         matcher.priority);
12044         /* reserved field no needs to be set to 0 here. */
12045         tbl_key.is_fdb = attr->transfer;
12046         tbl_key.is_egress = attr->egress;
12047         tbl_key.level = dev_flow->dv.group;
12048         tbl_key.id = dev_flow->dv.table_id;
12049         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
12050                                      tunnel, attr->group, error))
12051                 return -rte_errno;
12052         return 0;
12053 }
12054
12055 /**
12056  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12057  * and tunnel.
12058  *
12059  * @param[in, out] action
12060  *   Shred RSS action holding hash RX queue objects.
12061  * @param[in] hash_fields
12062  *   Defines combination of packet fields to participate in RX hash.
12063  * @param[in] tunnel
12064  *   Tunnel type
12065  * @param[in] hrxq_idx
12066  *   Hash RX queue index to set.
12067  *
12068  * @return
12069  *   0 on success, otherwise negative errno value.
12070  */
12071 static int
12072 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
12073                               const uint64_t hash_fields,
12074                               uint32_t hrxq_idx)
12075 {
12076         uint32_t *hrxqs = action->hrxq;
12077
12078         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12079         case MLX5_RSS_HASH_IPV4:
12080                 /* fall-through. */
12081         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12082                 /* fall-through. */
12083         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12084                 hrxqs[0] = hrxq_idx;
12085                 return 0;
12086         case MLX5_RSS_HASH_IPV4_TCP:
12087                 /* fall-through. */
12088         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12089                 /* fall-through. */
12090         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12091                 hrxqs[1] = hrxq_idx;
12092                 return 0;
12093         case MLX5_RSS_HASH_IPV4_UDP:
12094                 /* fall-through. */
12095         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12096                 /* fall-through. */
12097         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12098                 hrxqs[2] = hrxq_idx;
12099                 return 0;
12100         case MLX5_RSS_HASH_IPV6:
12101                 /* fall-through. */
12102         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12103                 /* fall-through. */
12104         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12105                 hrxqs[3] = hrxq_idx;
12106                 return 0;
12107         case MLX5_RSS_HASH_IPV6_TCP:
12108                 /* fall-through. */
12109         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12110                 /* fall-through. */
12111         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12112                 hrxqs[4] = hrxq_idx;
12113                 return 0;
12114         case MLX5_RSS_HASH_IPV6_UDP:
12115                 /* fall-through. */
12116         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12117                 /* fall-through. */
12118         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12119                 hrxqs[5] = hrxq_idx;
12120                 return 0;
12121         case MLX5_RSS_HASH_NONE:
12122                 hrxqs[6] = hrxq_idx;
12123                 return 0;
12124         default:
12125                 return -1;
12126         }
12127 }
12128
12129 /**
12130  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
12131  * and tunnel.
12132  *
12133  * @param[in] dev
12134  *   Pointer to the Ethernet device structure.
12135  * @param[in] idx
12136  *   Shared RSS action ID holding hash RX queue objects.
12137  * @param[in] hash_fields
12138  *   Defines combination of packet fields to participate in RX hash.
12139  * @param[in] tunnel
12140  *   Tunnel type
12141  *
12142  * @return
12143  *   Valid hash RX queue index, otherwise 0.
12144  */
12145 static uint32_t
12146 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
12147                                  const uint64_t hash_fields)
12148 {
12149         struct mlx5_priv *priv = dev->data->dev_private;
12150         struct mlx5_shared_action_rss *shared_rss =
12151             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12152         const uint32_t *hrxqs = shared_rss->hrxq;
12153
12154         switch (hash_fields & ~IBV_RX_HASH_INNER) {
12155         case MLX5_RSS_HASH_IPV4:
12156                 /* fall-through. */
12157         case MLX5_RSS_HASH_IPV4_DST_ONLY:
12158                 /* fall-through. */
12159         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
12160                 return hrxqs[0];
12161         case MLX5_RSS_HASH_IPV4_TCP:
12162                 /* fall-through. */
12163         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
12164                 /* fall-through. */
12165         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
12166                 return hrxqs[1];
12167         case MLX5_RSS_HASH_IPV4_UDP:
12168                 /* fall-through. */
12169         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
12170                 /* fall-through. */
12171         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
12172                 return hrxqs[2];
12173         case MLX5_RSS_HASH_IPV6:
12174                 /* fall-through. */
12175         case MLX5_RSS_HASH_IPV6_DST_ONLY:
12176                 /* fall-through. */
12177         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
12178                 return hrxqs[3];
12179         case MLX5_RSS_HASH_IPV6_TCP:
12180                 /* fall-through. */
12181         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
12182                 /* fall-through. */
12183         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
12184                 return hrxqs[4];
12185         case MLX5_RSS_HASH_IPV6_UDP:
12186                 /* fall-through. */
12187         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12188                 /* fall-through. */
12189         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12190                 return hrxqs[5];
12191         case MLX5_RSS_HASH_NONE:
12192                 return hrxqs[6];
12193         default:
12194                 return 0;
12195         }
12196
12197 }
12198
12199 /**
12200  * Apply the flow to the NIC, lock free,
12201  * (mutex should be acquired by caller).
12202  *
12203  * @param[in] dev
12204  *   Pointer to the Ethernet device structure.
12205  * @param[in, out] flow
12206  *   Pointer to flow structure.
12207  * @param[out] error
12208  *   Pointer to error structure.
12209  *
12210  * @return
12211  *   0 on success, a negative errno value otherwise and rte_errno is set.
12212  */
12213 static int
12214 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12215               struct rte_flow_error *error)
12216 {
12217         struct mlx5_flow_dv_workspace *dv;
12218         struct mlx5_flow_handle *dh;
12219         struct mlx5_flow_handle_dv *dv_h;
12220         struct mlx5_flow *dev_flow;
12221         struct mlx5_priv *priv = dev->data->dev_private;
12222         uint32_t handle_idx;
12223         int n;
12224         int err;
12225         int idx;
12226         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12227         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12228
12229         MLX5_ASSERT(wks);
12230         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12231                 dev_flow = &wks->flows[idx];
12232                 dv = &dev_flow->dv;
12233                 dh = dev_flow->handle;
12234                 dv_h = &dh->dvh;
12235                 n = dv->actions_n;
12236                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12237                         if (dv->transfer) {
12238                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12239                                 dv->actions[n++] = priv->sh->dr_drop_action;
12240                         } else {
12241 #ifdef HAVE_MLX5DV_DR
12242                                 /* DR supports drop action placeholder. */
12243                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12244                                 dv->actions[n++] = priv->sh->dr_drop_action;
12245 #else
12246                                 /* For DV we use the explicit drop queue. */
12247                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12248                                 dv->actions[n++] =
12249                                                 priv->drop_queue.hrxq->action;
12250 #endif
12251                         }
12252                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12253                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12254                         struct mlx5_hrxq *hrxq;
12255                         uint32_t hrxq_idx;
12256
12257                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12258                                                     &hrxq_idx);
12259                         if (!hrxq) {
12260                                 rte_flow_error_set
12261                                         (error, rte_errno,
12262                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12263                                          "cannot get hash queue");
12264                                 goto error;
12265                         }
12266                         dh->rix_hrxq = hrxq_idx;
12267                         dv->actions[n++] = hrxq->action;
12268                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12269                         struct mlx5_hrxq *hrxq = NULL;
12270                         uint32_t hrxq_idx;
12271
12272                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12273                                                 rss_desc->shared_rss,
12274                                                 dev_flow->hash_fields);
12275                         if (hrxq_idx)
12276                                 hrxq = mlx5_ipool_get
12277                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12278                                          hrxq_idx);
12279                         if (!hrxq) {
12280                                 rte_flow_error_set
12281                                         (error, rte_errno,
12282                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12283                                          "cannot get hash queue");
12284                                 goto error;
12285                         }
12286                         dh->rix_srss = rss_desc->shared_rss;
12287                         dv->actions[n++] = hrxq->action;
12288                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12289                         if (!priv->sh->default_miss_action) {
12290                                 rte_flow_error_set
12291                                         (error, rte_errno,
12292                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12293                                          "default miss action not be created.");
12294                                 goto error;
12295                         }
12296                         dv->actions[n++] = priv->sh->default_miss_action;
12297                 }
12298                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12299                                                (void *)&dv->value, n,
12300                                                dv->actions, &dh->drv_flow);
12301                 if (err) {
12302                         rte_flow_error_set(error, errno,
12303                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12304                                            NULL,
12305                                            "hardware refuses to create flow");
12306                         goto error;
12307                 }
12308                 if (priv->vmwa_context &&
12309                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12310                         /*
12311                          * The rule contains the VLAN pattern.
12312                          * For VF we are going to create VLAN
12313                          * interface to make hypervisor set correct
12314                          * e-Switch vport context.
12315                          */
12316                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12317                 }
12318         }
12319         return 0;
12320 error:
12321         err = rte_errno; /* Save rte_errno before cleanup. */
12322         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12323                        handle_idx, dh, next) {
12324                 /* hrxq is union, don't clear it if the flag is not set. */
12325                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12326                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12327                         dh->rix_hrxq = 0;
12328                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12329                         dh->rix_srss = 0;
12330                 }
12331                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12332                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12333         }
12334         rte_errno = err; /* Restore rte_errno. */
12335         return -rte_errno;
12336 }
12337
12338 void
12339 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12340                           struct mlx5_cache_entry *entry)
12341 {
12342         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12343                                                           entry);
12344
12345         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12346         mlx5_free(cache);
12347 }
12348
12349 /**
12350  * Release the flow matcher.
12351  *
12352  * @param dev
12353  *   Pointer to Ethernet device.
12354  * @param port_id
12355  *   Index to port ID action resource.
12356  *
12357  * @return
12358  *   1 while a reference on it exists, 0 when freed.
12359  */
12360 static int
12361 flow_dv_matcher_release(struct rte_eth_dev *dev,
12362                         struct mlx5_flow_handle *handle)
12363 {
12364         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12365         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12366                                                             typeof(*tbl), tbl);
12367         int ret;
12368
12369         MLX5_ASSERT(matcher->matcher_object);
12370         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12371         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12372         return ret;
12373 }
12374
12375 /**
12376  * Release encap_decap resource.
12377  *
12378  * @param list
12379  *   Pointer to the hash list.
12380  * @param entry
12381  *   Pointer to exist resource entry object.
12382  */
12383 void
12384 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12385                               struct mlx5_hlist_entry *entry)
12386 {
12387         struct mlx5_dev_ctx_shared *sh = list->ctx;
12388         struct mlx5_flow_dv_encap_decap_resource *res =
12389                 container_of(entry, typeof(*res), entry);
12390
12391         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12392         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12393 }
12394
12395 /**
12396  * Release an encap/decap resource.
12397  *
12398  * @param dev
12399  *   Pointer to Ethernet device.
12400  * @param encap_decap_idx
12401  *   Index of encap decap resource.
12402  *
12403  * @return
12404  *   1 while a reference on it exists, 0 when freed.
12405  */
12406 static int
12407 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12408                                      uint32_t encap_decap_idx)
12409 {
12410         struct mlx5_priv *priv = dev->data->dev_private;
12411         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12412
12413         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12414                                         encap_decap_idx);
12415         if (!cache_resource)
12416                 return 0;
12417         MLX5_ASSERT(cache_resource->action);
12418         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12419                                      &cache_resource->entry);
12420 }
12421
12422 /**
12423  * Release an jump to table action resource.
12424  *
12425  * @param dev
12426  *   Pointer to Ethernet device.
12427  * @param rix_jump
12428  *   Index to the jump action resource.
12429  *
12430  * @return
12431  *   1 while a reference on it exists, 0 when freed.
12432  */
12433 static int
12434 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12435                                   uint32_t rix_jump)
12436 {
12437         struct mlx5_priv *priv = dev->data->dev_private;
12438         struct mlx5_flow_tbl_data_entry *tbl_data;
12439
12440         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12441                                   rix_jump);
12442         if (!tbl_data)
12443                 return 0;
12444         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12445 }
12446
12447 void
12448 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12449                          struct mlx5_hlist_entry *entry)
12450 {
12451         struct mlx5_flow_dv_modify_hdr_resource *res =
12452                 container_of(entry, typeof(*res), entry);
12453
12454         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12455         mlx5_free(entry);
12456 }
12457
12458 /**
12459  * Release a modify-header resource.
12460  *
12461  * @param dev
12462  *   Pointer to Ethernet device.
12463  * @param handle
12464  *   Pointer to mlx5_flow_handle.
12465  *
12466  * @return
12467  *   1 while a reference on it exists, 0 when freed.
12468  */
12469 static int
12470 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12471                                     struct mlx5_flow_handle *handle)
12472 {
12473         struct mlx5_priv *priv = dev->data->dev_private;
12474         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12475
12476         MLX5_ASSERT(entry->action);
12477         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12478 }
12479
12480 void
12481 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12482                           struct mlx5_cache_entry *entry)
12483 {
12484         struct mlx5_dev_ctx_shared *sh = list->ctx;
12485         struct mlx5_flow_dv_port_id_action_resource *cache =
12486                         container_of(entry, typeof(*cache), entry);
12487
12488         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12489         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12490 }
12491
12492 /**
12493  * Release port ID action resource.
12494  *
12495  * @param dev
12496  *   Pointer to Ethernet device.
12497  * @param handle
12498  *   Pointer to mlx5_flow_handle.
12499  *
12500  * @return
12501  *   1 while a reference on it exists, 0 when freed.
12502  */
12503 static int
12504 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12505                                         uint32_t port_id)
12506 {
12507         struct mlx5_priv *priv = dev->data->dev_private;
12508         struct mlx5_flow_dv_port_id_action_resource *cache;
12509
12510         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12511         if (!cache)
12512                 return 0;
12513         MLX5_ASSERT(cache->action);
12514         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12515                                      &cache->entry);
12516 }
12517
12518 /**
12519  * Release shared RSS action resource.
12520  *
12521  * @param dev
12522  *   Pointer to Ethernet device.
12523  * @param srss
12524  *   Shared RSS action index.
12525  */
12526 static void
12527 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12528 {
12529         struct mlx5_priv *priv = dev->data->dev_private;
12530         struct mlx5_shared_action_rss *shared_rss;
12531
12532         shared_rss = mlx5_ipool_get
12533                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12534         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12535 }
12536
12537 void
12538 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12539                             struct mlx5_cache_entry *entry)
12540 {
12541         struct mlx5_dev_ctx_shared *sh = list->ctx;
12542         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12543                         container_of(entry, typeof(*cache), entry);
12544
12545         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12546         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12547 }
12548
12549 /**
12550  * Release push vlan action resource.
12551  *
12552  * @param dev
12553  *   Pointer to Ethernet device.
12554  * @param handle
12555  *   Pointer to mlx5_flow_handle.
12556  *
12557  * @return
12558  *   1 while a reference on it exists, 0 when freed.
12559  */
12560 static int
12561 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12562                                           struct mlx5_flow_handle *handle)
12563 {
12564         struct mlx5_priv *priv = dev->data->dev_private;
12565         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12566         uint32_t idx = handle->dvh.rix_push_vlan;
12567
12568         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12569         if (!cache)
12570                 return 0;
12571         MLX5_ASSERT(cache->action);
12572         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12573                                      &cache->entry);
12574 }
12575
12576 /**
12577  * Release the fate resource.
12578  *
12579  * @param dev
12580  *   Pointer to Ethernet device.
12581  * @param handle
12582  *   Pointer to mlx5_flow_handle.
12583  */
12584 static void
12585 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12586                                struct mlx5_flow_handle *handle)
12587 {
12588         if (!handle->rix_fate)
12589                 return;
12590         switch (handle->fate_action) {
12591         case MLX5_FLOW_FATE_QUEUE:
12592                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12593                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12594                 break;
12595         case MLX5_FLOW_FATE_JUMP:
12596                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12597                 break;
12598         case MLX5_FLOW_FATE_PORT_ID:
12599                 flow_dv_port_id_action_resource_release(dev,
12600                                 handle->rix_port_id_action);
12601                 break;
12602         default:
12603                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12604                 break;
12605         }
12606         handle->rix_fate = 0;
12607 }
12608
12609 void
12610 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12611                          struct mlx5_cache_entry *entry)
12612 {
12613         struct mlx5_flow_dv_sample_resource *cache_resource =
12614                         container_of(entry, typeof(*cache_resource), entry);
12615         struct rte_eth_dev *dev = cache_resource->dev;
12616         struct mlx5_priv *priv = dev->data->dev_private;
12617
12618         if (cache_resource->verbs_action)
12619                 claim_zero(mlx5_flow_os_destroy_flow_action
12620                                 (cache_resource->verbs_action));
12621         if (cache_resource->normal_path_tbl)
12622                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12623                         cache_resource->normal_path_tbl);
12624         flow_dv_sample_sub_actions_release(dev,
12625                                 &cache_resource->sample_idx);
12626         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12627                         cache_resource->idx);
12628         DRV_LOG(DEBUG, "sample resource %p: removed",
12629                 (void *)cache_resource);
12630 }
12631
12632 /**
12633  * Release an sample resource.
12634  *
12635  * @param dev
12636  *   Pointer to Ethernet device.
12637  * @param handle
12638  *   Pointer to mlx5_flow_handle.
12639  *
12640  * @return
12641  *   1 while a reference on it exists, 0 when freed.
12642  */
12643 static int
12644 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12645                                      struct mlx5_flow_handle *handle)
12646 {
12647         struct mlx5_priv *priv = dev->data->dev_private;
12648         struct mlx5_flow_dv_sample_resource *cache_resource;
12649
12650         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12651                          handle->dvh.rix_sample);
12652         if (!cache_resource)
12653                 return 0;
12654         MLX5_ASSERT(cache_resource->verbs_action);
12655         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12656                                      &cache_resource->entry);
12657 }
12658
12659 void
12660 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12661                              struct mlx5_cache_entry *entry)
12662 {
12663         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12664                         container_of(entry, typeof(*cache_resource), entry);
12665         struct rte_eth_dev *dev = cache_resource->dev;
12666         struct mlx5_priv *priv = dev->data->dev_private;
12667         uint32_t i = 0;
12668
12669         MLX5_ASSERT(cache_resource->action);
12670         if (cache_resource->action)
12671                 claim_zero(mlx5_flow_os_destroy_flow_action
12672                                         (cache_resource->action));
12673         for (; i < cache_resource->num_of_dest; i++)
12674                 flow_dv_sample_sub_actions_release(dev,
12675                                 &cache_resource->sample_idx[i]);
12676         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12677                         cache_resource->idx);
12678         DRV_LOG(DEBUG, "destination array resource %p: removed",
12679                 (void *)cache_resource);
12680 }
12681
12682 /**
12683  * Release an destination array resource.
12684  *
12685  * @param dev
12686  *   Pointer to Ethernet device.
12687  * @param handle
12688  *   Pointer to mlx5_flow_handle.
12689  *
12690  * @return
12691  *   1 while a reference on it exists, 0 when freed.
12692  */
12693 static int
12694 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12695                                     struct mlx5_flow_handle *handle)
12696 {
12697         struct mlx5_priv *priv = dev->data->dev_private;
12698         struct mlx5_flow_dv_dest_array_resource *cache;
12699
12700         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12701                                handle->dvh.rix_dest_array);
12702         if (!cache)
12703                 return 0;
12704         MLX5_ASSERT(cache->action);
12705         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12706                                      &cache->entry);
12707 }
12708
12709 static void
12710 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12711 {
12712         struct mlx5_priv *priv = dev->data->dev_private;
12713         struct mlx5_dev_ctx_shared *sh = priv->sh;
12714         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12715                                 sh->geneve_tlv_option_resource;
12716         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12717         if (geneve_opt_resource) {
12718                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12719                                          __ATOMIC_RELAXED))) {
12720                         claim_zero(mlx5_devx_cmd_destroy
12721                                         (geneve_opt_resource->obj));
12722                         mlx5_free(sh->geneve_tlv_option_resource);
12723                         sh->geneve_tlv_option_resource = NULL;
12724                 }
12725         }
12726         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12727 }
12728
12729 /**
12730  * Remove the flow from the NIC but keeps it in memory.
12731  * Lock free, (mutex should be acquired by caller).
12732  *
12733  * @param[in] dev
12734  *   Pointer to Ethernet device.
12735  * @param[in, out] flow
12736  *   Pointer to flow structure.
12737  */
12738 static void
12739 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12740 {
12741         struct mlx5_flow_handle *dh;
12742         uint32_t handle_idx;
12743         struct mlx5_priv *priv = dev->data->dev_private;
12744
12745         if (!flow)
12746                 return;
12747         handle_idx = flow->dev_handles;
12748         while (handle_idx) {
12749                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12750                                     handle_idx);
12751                 if (!dh)
12752                         return;
12753                 if (dh->drv_flow) {
12754                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12755                         dh->drv_flow = NULL;
12756                 }
12757                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12758                         flow_dv_fate_resource_release(dev, dh);
12759                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12760                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12761                 handle_idx = dh->next.next;
12762         }
12763 }
12764
12765 /**
12766  * Remove the flow from the NIC and the memory.
12767  * Lock free, (mutex should be acquired by caller).
12768  *
12769  * @param[in] dev
12770  *   Pointer to the Ethernet device structure.
12771  * @param[in, out] flow
12772  *   Pointer to flow structure.
12773  */
12774 static void
12775 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12776 {
12777         struct mlx5_flow_handle *dev_handle;
12778         struct mlx5_priv *priv = dev->data->dev_private;
12779         struct mlx5_flow_meter_info *fm = NULL;
12780         uint32_t srss = 0;
12781
12782         if (!flow)
12783                 return;
12784         flow_dv_remove(dev, flow);
12785         if (flow->counter) {
12786                 flow_dv_counter_free(dev, flow->counter);
12787                 flow->counter = 0;
12788         }
12789         if (flow->meter) {
12790                 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
12791                 if (fm)
12792                         mlx5_flow_meter_detach(priv, fm);
12793                 flow->meter = 0;
12794         }
12795         if (flow->age)
12796                 flow_dv_aso_age_release(dev, flow->age);
12797         if (flow->geneve_tlv_option) {
12798                 flow_dv_geneve_tlv_option_resource_release(dev);
12799                 flow->geneve_tlv_option = 0;
12800         }
12801         while (flow->dev_handles) {
12802                 uint32_t tmp_idx = flow->dev_handles;
12803
12804                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12805                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12806                 if (!dev_handle)
12807                         return;
12808                 flow->dev_handles = dev_handle->next.next;
12809                 if (dev_handle->dvh.matcher)
12810                         flow_dv_matcher_release(dev, dev_handle);
12811                 if (dev_handle->dvh.rix_sample)
12812                         flow_dv_sample_resource_release(dev, dev_handle);
12813                 if (dev_handle->dvh.rix_dest_array)
12814                         flow_dv_dest_array_resource_release(dev, dev_handle);
12815                 if (dev_handle->dvh.rix_encap_decap)
12816                         flow_dv_encap_decap_resource_release(dev,
12817                                 dev_handle->dvh.rix_encap_decap);
12818                 if (dev_handle->dvh.modify_hdr)
12819                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12820                 if (dev_handle->dvh.rix_push_vlan)
12821                         flow_dv_push_vlan_action_resource_release(dev,
12822                                                                   dev_handle);
12823                 if (dev_handle->dvh.rix_tag)
12824                         flow_dv_tag_release(dev,
12825                                             dev_handle->dvh.rix_tag);
12826                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12827                         flow_dv_fate_resource_release(dev, dev_handle);
12828                 else if (!srss)
12829                         srss = dev_handle->rix_srss;
12830                 if (fm && dev_handle->is_meter_flow_id &&
12831                     dev_handle->split_flow_id)
12832                         mlx5_ipool_free(fm->flow_ipool,
12833                                         dev_handle->split_flow_id);
12834                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12835                            tmp_idx);
12836         }
12837         if (srss)
12838                 flow_dv_shared_rss_action_release(dev, srss);
12839 }
12840
12841 /**
12842  * Release array of hash RX queue objects.
12843  * Helper function.
12844  *
12845  * @param[in] dev
12846  *   Pointer to the Ethernet device structure.
12847  * @param[in, out] hrxqs
12848  *   Array of hash RX queue objects.
12849  *
12850  * @return
12851  *   Total number of references to hash RX queue objects in *hrxqs* array
12852  *   after this operation.
12853  */
12854 static int
12855 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12856                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12857 {
12858         size_t i;
12859         int remaining = 0;
12860
12861         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12862                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12863
12864                 if (!ret)
12865                         (*hrxqs)[i] = 0;
12866                 remaining += ret;
12867         }
12868         return remaining;
12869 }
12870
12871 /**
12872  * Release all hash RX queue objects representing shared RSS action.
12873  *
12874  * @param[in] dev
12875  *   Pointer to the Ethernet device structure.
12876  * @param[in, out] action
12877  *   Shared RSS action to remove hash RX queue objects from.
12878  *
12879  * @return
12880  *   Total number of references to hash RX queue objects stored in *action*
12881  *   after this operation.
12882  *   Expected to be 0 if no external references held.
12883  */
12884 static int
12885 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12886                                  struct mlx5_shared_action_rss *shared_rss)
12887 {
12888         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12889 }
12890
12891 /**
12892  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12893  * user input.
12894  *
12895  * Only one hash value is available for one L3+L4 combination:
12896  * for example:
12897  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12898  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12899  * same slot in mlx5_rss_hash_fields.
12900  *
12901  * @param[in] rss
12902  *   Pointer to the shared action RSS conf.
12903  * @param[in, out] hash_field
12904  *   hash_field variable needed to be adjusted.
12905  *
12906  * @return
12907  *   void
12908  */
12909 static void
12910 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12911                                      uint64_t *hash_field)
12912 {
12913         uint64_t rss_types = rss->origin.types;
12914
12915         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12916         case MLX5_RSS_HASH_IPV4:
12917                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12918                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12919                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12920                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12921                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12922                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12923                         else
12924                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12925                 }
12926                 return;
12927         case MLX5_RSS_HASH_IPV6:
12928                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12929                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12930                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12931                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12932                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12933                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12934                         else
12935                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12936                 }
12937                 return;
12938         case MLX5_RSS_HASH_IPV4_UDP:
12939                 /* fall-through. */
12940         case MLX5_RSS_HASH_IPV6_UDP:
12941                 if (rss_types & ETH_RSS_UDP) {
12942                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12943                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12944                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12945                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12946                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12947                         else
12948                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12949                 }
12950                 return;
12951         case MLX5_RSS_HASH_IPV4_TCP:
12952                 /* fall-through. */
12953         case MLX5_RSS_HASH_IPV6_TCP:
12954                 if (rss_types & ETH_RSS_TCP) {
12955                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12956                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12957                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12958                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12959                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12960                         else
12961                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12962                 }
12963                 return;
12964         default:
12965                 return;
12966         }
12967 }
12968
12969 /**
12970  * Setup shared RSS action.
12971  * Prepare set of hash RX queue objects sufficient to handle all valid
12972  * hash_fields combinations (see enum ibv_rx_hash_fields).
12973  *
12974  * @param[in] dev
12975  *   Pointer to the Ethernet device structure.
12976  * @param[in] action_idx
12977  *   Shared RSS action ipool index.
12978  * @param[in, out] action
12979  *   Partially initialized shared RSS action.
12980  * @param[out] error
12981  *   Perform verbose error reporting if not NULL. Initialized in case of
12982  *   error only.
12983  *
12984  * @return
12985  *   0 on success, otherwise negative errno value.
12986  */
12987 static int
12988 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12989                            uint32_t action_idx,
12990                            struct mlx5_shared_action_rss *shared_rss,
12991                            struct rte_flow_error *error)
12992 {
12993         struct mlx5_flow_rss_desc rss_desc = { 0 };
12994         size_t i;
12995         int err;
12996
12997         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12998                 return rte_flow_error_set(error, rte_errno,
12999                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13000                                           "cannot setup indirection table");
13001         }
13002         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
13003         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
13004         rss_desc.const_q = shared_rss->origin.queue;
13005         rss_desc.queue_num = shared_rss->origin.queue_num;
13006         /* Set non-zero value to indicate a shared RSS. */
13007         rss_desc.shared_rss = action_idx;
13008         rss_desc.ind_tbl = shared_rss->ind_tbl;
13009         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
13010                 uint32_t hrxq_idx;
13011                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
13012                 int tunnel = 0;
13013
13014                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
13015                 if (shared_rss->origin.level > 1) {
13016                         hash_fields |= IBV_RX_HASH_INNER;
13017                         tunnel = 1;
13018                 }
13019                 rss_desc.tunnel = tunnel;
13020                 rss_desc.hash_fields = hash_fields;
13021                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
13022                 if (!hrxq_idx) {
13023                         rte_flow_error_set
13024                                 (error, rte_errno,
13025                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13026                                  "cannot get hash queue");
13027                         goto error_hrxq_new;
13028                 }
13029                 err = __flow_dv_action_rss_hrxq_set
13030                         (shared_rss, hash_fields, hrxq_idx);
13031                 MLX5_ASSERT(!err);
13032         }
13033         return 0;
13034 error_hrxq_new:
13035         err = rte_errno;
13036         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13037         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
13038                 shared_rss->ind_tbl = NULL;
13039         rte_errno = err;
13040         return -rte_errno;
13041 }
13042
13043 /**
13044  * Create shared RSS action.
13045  *
13046  * @param[in] dev
13047  *   Pointer to the Ethernet device structure.
13048  * @param[in] conf
13049  *   Shared action configuration.
13050  * @param[in] rss
13051  *   RSS action specification used to create shared action.
13052  * @param[out] error
13053  *   Perform verbose error reporting if not NULL. Initialized in case of
13054  *   error only.
13055  *
13056  * @return
13057  *   A valid shared action ID in case of success, 0 otherwise and
13058  *   rte_errno is set.
13059  */
13060 static uint32_t
13061 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
13062                             const struct rte_flow_indir_action_conf *conf,
13063                             const struct rte_flow_action_rss *rss,
13064                             struct rte_flow_error *error)
13065 {
13066         struct mlx5_priv *priv = dev->data->dev_private;
13067         struct mlx5_shared_action_rss *shared_rss = NULL;
13068         void *queue = NULL;
13069         struct rte_flow_action_rss *origin;
13070         const uint8_t *rss_key;
13071         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
13072         uint32_t idx;
13073
13074         RTE_SET_USED(conf);
13075         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13076                             0, SOCKET_ID_ANY);
13077         shared_rss = mlx5_ipool_zmalloc
13078                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
13079         if (!shared_rss || !queue) {
13080                 rte_flow_error_set(error, ENOMEM,
13081                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13082                                    "cannot allocate resource memory");
13083                 goto error_rss_init;
13084         }
13085         if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
13086                 rte_flow_error_set(error, E2BIG,
13087                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13088                                    "rss action number out of range");
13089                 goto error_rss_init;
13090         }
13091         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
13092                                           sizeof(*shared_rss->ind_tbl),
13093                                           0, SOCKET_ID_ANY);
13094         if (!shared_rss->ind_tbl) {
13095                 rte_flow_error_set(error, ENOMEM,
13096                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13097                                    "cannot allocate resource memory");
13098                 goto error_rss_init;
13099         }
13100         memcpy(queue, rss->queue, queue_size);
13101         shared_rss->ind_tbl->queues = queue;
13102         shared_rss->ind_tbl->queues_n = rss->queue_num;
13103         origin = &shared_rss->origin;
13104         origin->func = rss->func;
13105         origin->level = rss->level;
13106         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
13107         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
13108         /* NULL RSS key indicates default RSS key. */
13109         rss_key = !rss->key ? rss_hash_default_key : rss->key;
13110         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
13111         origin->key = &shared_rss->key[0];
13112         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
13113         origin->queue = queue;
13114         origin->queue_num = rss->queue_num;
13115         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
13116                 goto error_rss_init;
13117         rte_spinlock_init(&shared_rss->action_rss_sl);
13118         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
13119         rte_spinlock_lock(&priv->shared_act_sl);
13120         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13121                      &priv->rss_shared_actions, idx, shared_rss, next);
13122         rte_spinlock_unlock(&priv->shared_act_sl);
13123         return idx;
13124 error_rss_init:
13125         if (shared_rss) {
13126                 if (shared_rss->ind_tbl)
13127                         mlx5_free(shared_rss->ind_tbl);
13128                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13129                                 idx);
13130         }
13131         if (queue)
13132                 mlx5_free(queue);
13133         return 0;
13134 }
13135
13136 /**
13137  * Destroy the shared RSS action.
13138  * Release related hash RX queue objects.
13139  *
13140  * @param[in] dev
13141  *   Pointer to the Ethernet device structure.
13142  * @param[in] idx
13143  *   The shared RSS action object ID to be removed.
13144  * @param[out] error
13145  *   Perform verbose error reporting if not NULL. Initialized in case of
13146  *   error only.
13147  *
13148  * @return
13149  *   0 on success, otherwise negative errno value.
13150  */
13151 static int
13152 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
13153                              struct rte_flow_error *error)
13154 {
13155         struct mlx5_priv *priv = dev->data->dev_private;
13156         struct mlx5_shared_action_rss *shared_rss =
13157             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13158         uint32_t old_refcnt = 1;
13159         int remaining;
13160         uint16_t *queue = NULL;
13161
13162         if (!shared_rss)
13163                 return rte_flow_error_set(error, EINVAL,
13164                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13165                                           "invalid shared action");
13166         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
13167         if (remaining)
13168                 return rte_flow_error_set(error, EBUSY,
13169                                           RTE_FLOW_ERROR_TYPE_ACTION,
13170                                           NULL,
13171                                           "shared rss hrxq has references");
13172         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
13173                                          0, 0, __ATOMIC_ACQUIRE,
13174                                          __ATOMIC_RELAXED))
13175                 return rte_flow_error_set(error, EBUSY,
13176                                           RTE_FLOW_ERROR_TYPE_ACTION,
13177                                           NULL,
13178                                           "shared rss has references");
13179         queue = shared_rss->ind_tbl->queues;
13180         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
13181         if (remaining)
13182                 return rte_flow_error_set(error, EBUSY,
13183                                           RTE_FLOW_ERROR_TYPE_ACTION,
13184                                           NULL,
13185                                           "shared rss indirection table has"
13186                                           " references");
13187         mlx5_free(queue);
13188         rte_spinlock_lock(&priv->shared_act_sl);
13189         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13190                      &priv->rss_shared_actions, idx, shared_rss, next);
13191         rte_spinlock_unlock(&priv->shared_act_sl);
13192         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13193                         idx);
13194         return 0;
13195 }
13196
13197 /**
13198  * Create indirect action, lock free,
13199  * (mutex should be acquired by caller).
13200  * Dispatcher for action type specific call.
13201  *
13202  * @param[in] dev
13203  *   Pointer to the Ethernet device structure.
13204  * @param[in] conf
13205  *   Shared action configuration.
13206  * @param[in] action
13207  *   Action specification used to create indirect action.
13208  * @param[out] error
13209  *   Perform verbose error reporting if not NULL. Initialized in case of
13210  *   error only.
13211  *
13212  * @return
13213  *   A valid shared action handle in case of success, NULL otherwise and
13214  *   rte_errno is set.
13215  */
13216 static struct rte_flow_action_handle *
13217 flow_dv_action_create(struct rte_eth_dev *dev,
13218                       const struct rte_flow_indir_action_conf *conf,
13219                       const struct rte_flow_action *action,
13220                       struct rte_flow_error *err)
13221 {
13222         uint32_t idx = 0;
13223         uint32_t ret = 0;
13224
13225         switch (action->type) {
13226         case RTE_FLOW_ACTION_TYPE_RSS:
13227                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13228                 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
13229                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13230                 break;
13231         case RTE_FLOW_ACTION_TYPE_AGE:
13232                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13233                 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
13234                        MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
13235                 if (ret) {
13236                         struct mlx5_aso_age_action *aso_age =
13237                                               flow_aso_age_get_by_idx(dev, ret);
13238
13239                         if (!aso_age->age_params.context)
13240                                 aso_age->age_params.context =
13241                                                          (void *)(uintptr_t)idx;
13242                 }
13243                 break;
13244         default:
13245                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13246                                    NULL, "action type not supported");
13247                 break;
13248         }
13249         return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
13250 }
13251
13252 /**
13253  * Destroy the indirect action.
13254  * Release action related resources on the NIC and the memory.
13255  * Lock free, (mutex should be acquired by caller).
13256  * Dispatcher for action type specific call.
13257  *
13258  * @param[in] dev
13259  *   Pointer to the Ethernet device structure.
13260  * @param[in] handle
13261  *   The indirect action object handle to be removed.
13262  * @param[out] error
13263  *   Perform verbose error reporting if not NULL. Initialized in case of
13264  *   error only.
13265  *
13266  * @return
13267  *   0 on success, otherwise negative errno value.
13268  */
13269 static int
13270 flow_dv_action_destroy(struct rte_eth_dev *dev,
13271                        struct rte_flow_action_handle *handle,
13272                        struct rte_flow_error *error)
13273 {
13274         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13275         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13276         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13277         int ret;
13278
13279         switch (type) {
13280         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13281                 return __flow_dv_action_rss_release(dev, idx, error);
13282         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13283                 ret = flow_dv_aso_age_release(dev, idx);
13284                 if (ret)
13285                         /*
13286                          * In this case, the last flow has a reference will
13287                          * actually release the age action.
13288                          */
13289                         DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
13290                                 " released with references %d.", idx, ret);
13291                 return 0;
13292         default:
13293                 return rte_flow_error_set(error, ENOTSUP,
13294                                           RTE_FLOW_ERROR_TYPE_ACTION,
13295                                           NULL,
13296                                           "action type not supported");
13297         }
13298 }
13299
13300 /**
13301  * Updates in place shared RSS action configuration.
13302  *
13303  * @param[in] dev
13304  *   Pointer to the Ethernet device structure.
13305  * @param[in] idx
13306  *   The shared RSS action object ID to be updated.
13307  * @param[in] action_conf
13308  *   RSS action specification used to modify *shared_rss*.
13309  * @param[out] error
13310  *   Perform verbose error reporting if not NULL. Initialized in case of
13311  *   error only.
13312  *
13313  * @return
13314  *   0 on success, otherwise negative errno value.
13315  * @note: currently only support update of RSS queues.
13316  */
13317 static int
13318 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13319                             const struct rte_flow_action_rss *action_conf,
13320                             struct rte_flow_error *error)
13321 {
13322         struct mlx5_priv *priv = dev->data->dev_private;
13323         struct mlx5_shared_action_rss *shared_rss =
13324             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13325         int ret = 0;
13326         void *queue = NULL;
13327         uint16_t *queue_old = NULL;
13328         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13329
13330         if (!shared_rss)
13331                 return rte_flow_error_set(error, EINVAL,
13332                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13333                                           "invalid shared action to update");
13334         if (priv->obj_ops.ind_table_modify == NULL)
13335                 return rte_flow_error_set(error, ENOTSUP,
13336                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13337                                           "cannot modify indirection table");
13338         queue = mlx5_malloc(MLX5_MEM_ZERO,
13339                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13340                             0, SOCKET_ID_ANY);
13341         if (!queue)
13342                 return rte_flow_error_set(error, ENOMEM,
13343                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13344                                           NULL,
13345                                           "cannot allocate resource memory");
13346         memcpy(queue, action_conf->queue, queue_size);
13347         MLX5_ASSERT(shared_rss->ind_tbl);
13348         rte_spinlock_lock(&shared_rss->action_rss_sl);
13349         queue_old = shared_rss->ind_tbl->queues;
13350         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13351                                         queue, action_conf->queue_num, true);
13352         if (ret) {
13353                 mlx5_free(queue);
13354                 ret = rte_flow_error_set(error, rte_errno,
13355                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13356                                           "cannot update indirection table");
13357         } else {
13358                 mlx5_free(queue_old);
13359                 shared_rss->origin.queue = queue;
13360                 shared_rss->origin.queue_num = action_conf->queue_num;
13361         }
13362         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13363         return ret;
13364 }
13365
13366 /**
13367  * Updates in place shared action configuration, lock free,
13368  * (mutex should be acquired by caller).
13369  *
13370  * @param[in] dev
13371  *   Pointer to the Ethernet device structure.
13372  * @param[in] handle
13373  *   The indirect action object handle to be updated.
13374  * @param[in] update
13375  *   Action specification used to modify the action pointed by *handle*.
13376  *   *update* could be of same type with the action pointed by the *handle*
13377  *   handle argument, or some other structures like a wrapper, depending on
13378  *   the indirect action type.
13379  * @param[out] error
13380  *   Perform verbose error reporting if not NULL. Initialized in case of
13381  *   error only.
13382  *
13383  * @return
13384  *   0 on success, otherwise negative errno value.
13385  */
13386 static int
13387 flow_dv_action_update(struct rte_eth_dev *dev,
13388                         struct rte_flow_action_handle *handle,
13389                         const void *update,
13390                         struct rte_flow_error *err)
13391 {
13392         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13393         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13394         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13395         const void *action_conf;
13396
13397         switch (type) {
13398         case MLX5_INDIRECT_ACTION_TYPE_RSS:
13399                 action_conf = ((const struct rte_flow_action *)update)->conf;
13400                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13401         default:
13402                 return rte_flow_error_set(err, ENOTSUP,
13403                                           RTE_FLOW_ERROR_TYPE_ACTION,
13404                                           NULL,
13405                                           "action type update not supported");
13406         }
13407 }
13408
13409 static int
13410 flow_dv_action_query(struct rte_eth_dev *dev,
13411                      const struct rte_flow_action_handle *handle, void *data,
13412                      struct rte_flow_error *error)
13413 {
13414         struct mlx5_age_param *age_param;
13415         struct rte_flow_query_age *resp;
13416         uint32_t act_idx = (uint32_t)(uintptr_t)handle;
13417         uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
13418         uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
13419
13420         switch (type) {
13421         case MLX5_INDIRECT_ACTION_TYPE_AGE:
13422                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13423                 resp = data;
13424                 resp->aged = __atomic_load_n(&age_param->state,
13425                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13426                                                                           1 : 0;
13427                 resp->sec_since_last_hit_valid = !resp->aged;
13428                 if (resp->sec_since_last_hit_valid)
13429                         resp->sec_since_last_hit = __atomic_load_n
13430                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13431                 return 0;
13432         default:
13433                 return rte_flow_error_set(error, ENOTSUP,
13434                                           RTE_FLOW_ERROR_TYPE_ACTION,
13435                                           NULL,
13436                                           "action type query not supported");
13437         }
13438 }
13439
13440 /**
13441  * Query a dv flow  rule for its statistics via devx.
13442  *
13443  * @param[in] dev
13444  *   Pointer to Ethernet device.
13445  * @param[in] flow
13446  *   Pointer to the sub flow.
13447  * @param[out] data
13448  *   data retrieved by the query.
13449  * @param[out] error
13450  *   Perform verbose error reporting if not NULL.
13451  *
13452  * @return
13453  *   0 on success, a negative errno value otherwise and rte_errno is set.
13454  */
13455 static int
13456 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13457                     void *data, struct rte_flow_error *error)
13458 {
13459         struct mlx5_priv *priv = dev->data->dev_private;
13460         struct rte_flow_query_count *qc = data;
13461
13462         if (!priv->config.devx)
13463                 return rte_flow_error_set(error, ENOTSUP,
13464                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13465                                           NULL,
13466                                           "counters are not supported");
13467         if (flow->counter) {
13468                 uint64_t pkts, bytes;
13469                 struct mlx5_flow_counter *cnt;
13470
13471                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13472                                                  NULL);
13473                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13474                                                &bytes);
13475
13476                 if (err)
13477                         return rte_flow_error_set(error, -err,
13478                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13479                                         NULL, "cannot read counters");
13480                 qc->hits_set = 1;
13481                 qc->bytes_set = 1;
13482                 qc->hits = pkts - cnt->hits;
13483                 qc->bytes = bytes - cnt->bytes;
13484                 if (qc->reset) {
13485                         cnt->hits = pkts;
13486                         cnt->bytes = bytes;
13487                 }
13488                 return 0;
13489         }
13490         return rte_flow_error_set(error, EINVAL,
13491                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13492                                   NULL,
13493                                   "counters are not available");
13494 }
13495
13496 /**
13497  * Query a flow rule AGE action for aging information.
13498  *
13499  * @param[in] dev
13500  *   Pointer to Ethernet device.
13501  * @param[in] flow
13502  *   Pointer to the sub flow.
13503  * @param[out] data
13504  *   data retrieved by the query.
13505  * @param[out] error
13506  *   Perform verbose error reporting if not NULL.
13507  *
13508  * @return
13509  *   0 on success, a negative errno value otherwise and rte_errno is set.
13510  */
13511 static int
13512 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13513                   void *data, struct rte_flow_error *error)
13514 {
13515         struct rte_flow_query_age *resp = data;
13516         struct mlx5_age_param *age_param;
13517
13518         if (flow->age) {
13519                 struct mlx5_aso_age_action *act =
13520                                      flow_aso_age_get_by_idx(dev, flow->age);
13521
13522                 age_param = &act->age_params;
13523         } else if (flow->counter) {
13524                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13525
13526                 if (!age_param || !age_param->timeout)
13527                         return rte_flow_error_set
13528                                         (error, EINVAL,
13529                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13530                                          NULL, "cannot read age data");
13531         } else {
13532                 return rte_flow_error_set(error, EINVAL,
13533                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13534                                           NULL, "age data not available");
13535         }
13536         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13537                                      AGE_TMOUT ? 1 : 0;
13538         resp->sec_since_last_hit_valid = !resp->aged;
13539         if (resp->sec_since_last_hit_valid)
13540                 resp->sec_since_last_hit = __atomic_load_n
13541                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13542         return 0;
13543 }
13544
13545 /**
13546  * Query a flow.
13547  *
13548  * @see rte_flow_query()
13549  * @see rte_flow_ops
13550  */
13551 static int
13552 flow_dv_query(struct rte_eth_dev *dev,
13553               struct rte_flow *flow __rte_unused,
13554               const struct rte_flow_action *actions __rte_unused,
13555               void *data __rte_unused,
13556               struct rte_flow_error *error __rte_unused)
13557 {
13558         int ret = -EINVAL;
13559
13560         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13561                 switch (actions->type) {
13562                 case RTE_FLOW_ACTION_TYPE_VOID:
13563                         break;
13564                 case RTE_FLOW_ACTION_TYPE_COUNT:
13565                         ret = flow_dv_query_count(dev, flow, data, error);
13566                         break;
13567                 case RTE_FLOW_ACTION_TYPE_AGE:
13568                         ret = flow_dv_query_age(dev, flow, data, error);
13569                         break;
13570                 default:
13571                         return rte_flow_error_set(error, ENOTSUP,
13572                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13573                                                   actions,
13574                                                   "action not supported");
13575                 }
13576         }
13577         return ret;
13578 }
13579
13580 /**
13581  * Destroy the meter table set.
13582  * Lock free, (mutex should be acquired by caller).
13583  *
13584  * @param[in] dev
13585  *   Pointer to Ethernet device.
13586  * @param[in] tbl
13587  *   Pointer to the meter table set.
13588  *
13589  * @return
13590  *   Always 0.
13591  */
13592 static int
13593 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13594                         struct mlx5_meter_domains_infos *tbl)
13595 {
13596         struct mlx5_priv *priv = dev->data->dev_private;
13597         struct mlx5_meter_domains_infos *mtd =
13598                                 (struct mlx5_meter_domains_infos *)tbl;
13599
13600         if (!mtd || !priv->config.dv_flow_en)
13601                 return 0;
13602         if (mtd->egress.tbl)
13603                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13604         if (mtd->egress.sfx_tbl)
13605                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13606         if (mtd->ingress.tbl)
13607                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13608         if (mtd->ingress.sfx_tbl)
13609                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13610                                              mtd->ingress.sfx_tbl);
13611         if (mtd->transfer.tbl)
13612                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13613         if (mtd->transfer.sfx_tbl)
13614                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13615                                              mtd->transfer.sfx_tbl);
13616         mlx5_free(mtd);
13617         return 0;
13618 }
13619
13620 /* Number of meter flow actions, count and jump or count and drop. */
13621 #define METER_ACTIONS 2
13622
13623 /**
13624  * Create specify domain meter table and suffix table.
13625  *
13626  * @param[in] dev
13627  *   Pointer to Ethernet device.
13628  * @param[in,out] mtb
13629  *   Pointer to DV meter table set.
13630  * @param[in] egress
13631  *   Table attribute.
13632  * @param[in] transfer
13633  *   Table attribute.
13634  *
13635  * @return
13636  *   0 on success, -1 otherwise.
13637  */
13638 static int
13639 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13640                            struct mlx5_meter_domains_infos *mtb,
13641                            uint8_t egress, uint8_t transfer)
13642 {
13643         struct rte_flow_error error;
13644         struct mlx5_meter_domain_info *dtb;
13645
13646         if (transfer)
13647                 dtb = &mtb->transfer;
13648         else if (egress)
13649                 dtb = &mtb->egress;
13650         else
13651                 dtb = &mtb->ingress;
13652         /* Create the meter table with METER level. */
13653         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13654                                             egress, transfer, false, NULL, 0,
13655                                             0, 0, &error);
13656         if (!dtb->tbl) {
13657                 DRV_LOG(ERR, "Failed to create meter policer table.");
13658                 return -1;
13659         }
13660         /* Create the meter suffix table with SUFFIX level. */
13661         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13662                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13663                                             egress, transfer, false, NULL, 0,
13664                                             0, 0, &error);
13665         if (!dtb->sfx_tbl) {
13666                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13667                 return -1;
13668         }
13669         return 0;
13670 }
13671
13672 /**
13673  * Create the needed meter and suffix tables.
13674  * Lock free, (mutex should be acquired by caller).
13675  *
13676  * @param[in] dev
13677  *   Pointer to Ethernet device.
13678  *
13679  * @return
13680  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13681  */
13682 static struct mlx5_meter_domains_infos *
13683 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev)
13684 {
13685         struct mlx5_priv *priv = dev->data->dev_private;
13686         struct mlx5_meter_domains_infos *mtb;
13687         int ret;
13688
13689         if (!priv->mtr_en) {
13690                 rte_errno = ENOTSUP;
13691                 return NULL;
13692         }
13693         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13694         if (!mtb) {
13695                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13696                 return NULL;
13697         }
13698         /* Egress meter table. */
13699         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0);
13700         if (ret) {
13701                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13702                 goto error_exit;
13703         }
13704         /* Ingress meter table. */
13705         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0);
13706         if (ret) {
13707                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13708                 goto error_exit;
13709         }
13710         /* FDB meter table. */
13711         if (priv->config.dv_esw_en) {
13712                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1);
13713                 if (ret) {
13714                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13715                         goto error_exit;
13716                 }
13717         }
13718         return mtb;
13719 error_exit:
13720         flow_dv_destroy_mtr_tbl(dev, mtb);
13721         return NULL;
13722 }
13723
13724 /**
13725  * Destroy the meter table matchers.
13726  * Lock free, (mutex should be acquired by caller).
13727  *
13728  * @param[in] dev
13729  *   Pointer to Ethernet device.
13730  * @param[in,out] dtb
13731  *   Pointer to DV meter table.
13732  *
13733  * @return
13734  *   Always 0.
13735  */
13736 static int
13737 flow_dv_destroy_mtr_matchers(struct rte_eth_dev *dev,
13738                              struct mlx5_meter_domain_info *dtb)
13739 {
13740         struct mlx5_priv *priv = dev->data->dev_private;
13741         struct mlx5_flow_tbl_data_entry *tbl;
13742
13743         if (!priv->config.dv_flow_en)
13744                 return 0;
13745         if (dtb->drop_matcher) {
13746                 tbl = container_of(dtb->drop_matcher->tbl, typeof(*tbl), tbl);
13747                 mlx5_cache_unregister(&tbl->matchers,
13748                                       &dtb->drop_matcher->entry);
13749                 dtb->drop_matcher = NULL;
13750         }
13751         if (dtb->color_matcher) {
13752                 tbl = container_of(dtb->color_matcher->tbl, typeof(*tbl), tbl);
13753                 mlx5_cache_unregister(&tbl->matchers,
13754                                       &dtb->color_matcher->entry);
13755                 dtb->color_matcher = NULL;
13756         }
13757         return 0;
13758 }
13759
13760 /**
13761  * Create the matchers for meter table.
13762  *
13763  * @param[in] dev
13764  *   Pointer to Ethernet device.
13765  * @param[in] color_reg_c_idx
13766  *   Reg C index for color match.
13767  * @param[in] mtr_id_reg_c_idx
13768  *   Reg C index for meter_id match.
13769  * @param[in] mtr_id_mask
13770  *   Mask for meter_id match criteria.
13771  * @param[in,out] dtb
13772  *   Pointer to DV meter table.
13773  * @param[out] error
13774  *   Perform verbose error reporting if not NULL.
13775  *
13776  * @return
13777  *   0 on success, a negative errno value otherwise and rte_errno is set.
13778  */
13779 static int
13780 flow_dv_prepare_mtr_matchers(struct rte_eth_dev *dev,
13781                              uint32_t color_reg_c_idx,
13782                              uint32_t mtr_id_reg_c_idx,
13783                              uint32_t mtr_id_mask,
13784                              struct mlx5_meter_domain_info *dtb,
13785                              struct rte_flow_error *error)
13786 {
13787         struct mlx5_priv *priv = dev->data->dev_private;
13788         struct mlx5_flow_tbl_data_entry *tbl_data;
13789         struct mlx5_cache_entry *entry;
13790         struct mlx5_flow_dv_matcher matcher = {
13791                 .mask = {
13792                         .size = sizeof(matcher.mask.buf) -
13793                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13794                 },
13795                 .tbl = dtb->tbl,
13796         };
13797         struct mlx5_flow_dv_match_params value = {
13798                 .size = sizeof(value.buf) -
13799                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13800         };
13801         struct mlx5_flow_cb_ctx ctx = {
13802                 .error = error,
13803                 .data = &matcher,
13804         };
13805         uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
13806
13807         tbl_data = container_of(dtb->tbl, struct mlx5_flow_tbl_data_entry, tbl);
13808         if (!dtb->drop_matcher) {
13809                 /* Create matchers for Drop. */
13810                 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13811                                        mtr_id_reg_c_idx, 0, mtr_id_mask);
13812                 matcher.priority = MLX5_REG_BITS * 2 - priv->max_mtr_bits;
13813                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13814                                         matcher.mask.size);
13815                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13816                 if (!entry) {
13817                         DRV_LOG(ERR, "Failed to register meter drop matcher.");
13818                         return -1;
13819                 }
13820                 dtb->drop_matcher =
13821                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13822         }
13823         if (!dtb->color_matcher) {
13824                 /* Create matchers for Color + meter_id. */
13825                 if (priv->mtr_reg_share) {
13826                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13827                                         color_reg_c_idx, 0,
13828                                         (mtr_id_mask | color_mask));
13829                 } else {
13830                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13831                                         color_reg_c_idx, 0, color_mask);
13832                         flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
13833                                         mtr_id_reg_c_idx, 0, mtr_id_mask);
13834                 }
13835                 matcher.priority = MLX5_REG_BITS - priv->max_mtr_bits;
13836                 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13837                                         matcher.mask.size);
13838                 entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
13839                 if (!entry) {
13840                         DRV_LOG(ERR, "Failed to register meter color matcher.");
13841                         return -1;
13842                 }
13843                 dtb->color_matcher =
13844                         container_of(entry, struct mlx5_flow_dv_matcher, entry);
13845         }
13846         return 0;
13847 }
13848
13849 /**
13850  * Destroy domain policer rule.
13851  *
13852  * @param[in] dev
13853  *   Pointer to Ethernet device.
13854  * @param[in] dt
13855  *   Pointer to domain table.
13856  */
13857 static void
13858 flow_dv_destroy_domain_policer_rule(struct rte_eth_dev *dev,
13859                                     struct mlx5_meter_domain_info *dt)
13860 {
13861         if (dt->drop_rule) {
13862                 claim_zero(mlx5_flow_os_destroy_flow(dt->drop_rule));
13863                 dt->drop_rule = NULL;
13864         }
13865         if (dt->green_rule) {
13866                 claim_zero(mlx5_flow_os_destroy_flow(dt->green_rule));
13867                 dt->green_rule = NULL;
13868         }
13869         flow_dv_destroy_mtr_matchers(dev, dt);
13870         if (dt->jump_actn) {
13871                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13872                 dt->jump_actn = NULL;
13873         }
13874 }
13875
13876 /**
13877  * Destroy policer rules.
13878  *
13879  * @param[in] dev
13880  *   Pointer to Ethernet device.
13881  * @param[in] fm
13882  *   Pointer to flow meter structure.
13883  * @param[in] attr
13884  *   Pointer to flow attributes.
13885  *
13886  * @return
13887  *   Always 0.
13888  */
13889 static int
13890 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev,
13891                               const struct mlx5_flow_meter_info *fm,
13892                               const struct rte_flow_attr *attr)
13893 {
13894         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13895
13896         if (!mtb)
13897                 return 0;
13898         if (attr->egress)
13899                 flow_dv_destroy_domain_policer_rule(dev, &mtb->egress);
13900         if (attr->ingress)
13901                 flow_dv_destroy_domain_policer_rule(dev, &mtb->ingress);
13902         if (attr->transfer)
13903                 flow_dv_destroy_domain_policer_rule(dev, &mtb->transfer);
13904         return 0;
13905 }
13906
13907 /**
13908  * Create specify domain meter policer rule.
13909  *
13910  * @param[in] dev
13911  *   Pointer to Ethernet device.
13912  * @param[in] fm
13913  *   Pointer to flow meter structure.
13914  * @param[in] mtr_idx
13915  *   meter index.
13916  * @param[in] mtb
13917  *   Pointer to DV meter table set.
13918  * @param[out] drop_rule
13919  *   The address of pointer saving drop rule.
13920  * @param[out] color_rule
13921  *   The address of pointer saving green rule.
13922  *
13923  * @return
13924  *   0 on success, -1 otherwise.
13925  */
13926 static int
13927 flow_dv_create_policer_forward_rule(struct rte_eth_dev *dev,
13928                                     struct mlx5_flow_meter_info *fm,
13929                                     uint32_t mtr_idx,
13930                                     struct mlx5_meter_domain_info *dtb,
13931                                     void **drop_rule,
13932                                     void **green_rule)
13933 {
13934         struct mlx5_priv *priv = dev->data->dev_private;
13935         struct mlx5_flow_dv_match_params matcher = {
13936                 .size = sizeof(matcher.buf) -
13937                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13938         };
13939         struct mlx5_flow_dv_match_params value = {
13940                 .size = sizeof(value.buf) -
13941                         MLX5_ST_SZ_BYTES(fte_match_set_misc4),
13942         };
13943         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13944         struct rte_flow_error error;
13945         uint32_t color_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR,
13946                                                     0, &error);
13947         uint32_t mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
13948                                                      0, &error);
13949         uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
13950         uint32_t mtr_id_mask =
13951                 ((UINT32_C(1) << priv->max_mtr_bits) - 1) << mtr_id_offset;
13952         void *actions[METER_ACTIONS];
13953         int i;
13954         int ret = 0;
13955
13956         /* Create jump action. */
13957         if (!dtb->jump_actn)
13958                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13959                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13960         if (ret) {
13961                 DRV_LOG(ERR, "Failed to create policer jump action.");
13962                 goto error;
13963         }
13964         /* Prepare matchers. */
13965         if (!dtb->drop_matcher || !dtb->color_matcher) {
13966                 ret = flow_dv_prepare_mtr_matchers(dev, color_reg_c,
13967                                                    mtr_id_reg_c, mtr_id_mask,
13968                                                    dtb, &error);
13969                 if (ret) {
13970                         DRV_LOG(ERR, "Failed to setup matchers for mtr table.");
13971                         goto error;
13972                 }
13973         }
13974         /* Create Drop flow, matching meter_id only. */
13975         i = 0;
13976         flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13977                                (mtr_idx << mtr_id_offset), UINT32_MAX);
13978         if (mtb->drop_count)
13979                 actions[i++] = mtb->drop_count;
13980         actions[i++] = priv->sh->dr_drop_action;
13981         ret = mlx5_flow_os_create_flow(dtb->drop_matcher->matcher_object,
13982                                        (void *)&value, i, actions, drop_rule);
13983         if (ret) {
13984                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13985                 goto error;
13986         }
13987         /* Create flow matching Green color + meter_id. */
13988         i = 0;
13989         if (priv->mtr_reg_share) {
13990                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13991                                        ((mtr_idx << mtr_id_offset) |
13992                                         rte_col_2_mlx5_col(RTE_COLOR_GREEN)),
13993                                        UINT32_MAX);
13994         } else {
13995                 flow_dv_match_meta_reg(matcher.buf, value.buf, color_reg_c,
13996                                        rte_col_2_mlx5_col(RTE_COLOR_GREEN),
13997                                        UINT32_MAX);
13998                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_id_reg_c,
13999                                        mtr_idx, UINT32_MAX);
14000         }
14001         if (mtb->green_count)
14002                 actions[i++] = mtb->green_count;
14003         actions[i++] = dtb->jump_actn;
14004         ret = mlx5_flow_os_create_flow(dtb->color_matcher->matcher_object,
14005                                        (void *)&value, i, actions, green_rule);
14006         if (ret) {
14007                 DRV_LOG(ERR, "Failed to create meter policer color rule.");
14008                 goto error;
14009         }
14010         return 0;
14011 error:
14012         rte_errno = errno;
14013         return -1;
14014 }
14015
14016 /**
14017  * Prepare policer rules for all domains.
14018  * If meter already initialized, this will replace all old rules with new ones.
14019  *
14020  * @param[in] dev
14021  *   Pointer to Ethernet device.
14022  * @param[in] fm
14023  *   Pointer to flow meter structure.
14024  * @param[in] attr
14025  *   Pointer to flow attributes.
14026  *
14027  * @return
14028  *   0 on success, -1 otherwise.
14029  */
14030 static int
14031 flow_dv_prepare_policer_rules(struct rte_eth_dev *dev,
14032                               struct mlx5_flow_meter_info *fm,
14033                               const struct rte_flow_attr *attr)
14034 {
14035         struct mlx5_priv *priv = dev->data->dev_private;
14036         struct mlx5_meter_domains_infos *mtb = fm->mfts;
14037         bool initialized = false;
14038         struct mlx5_flow_counter *cnt;
14039         void *egress_drop_rule = NULL;
14040         void *egress_green_rule = NULL;
14041         void *ingress_drop_rule = NULL;
14042         void *ingress_green_rule = NULL;
14043         void *transfer_drop_rule = NULL;
14044         void *transfer_green_rule = NULL;
14045         uint32_t mtr_idx;
14046         int ret;
14047
14048         /* Get the statistics counters for green/drop. */
14049         if (fm->policer_stats.pass_cnt) {
14050                 cnt = flow_dv_counter_get_by_idx(dev,
14051                                         fm->policer_stats.pass_cnt,
14052                                         NULL);
14053                 mtb->green_count = cnt->action;
14054         } else {
14055                 mtb->green_count = NULL;
14056         }
14057         if (fm->policer_stats.drop_cnt) {
14058                 cnt = flow_dv_counter_get_by_idx(dev,
14059                                         fm->policer_stats.drop_cnt,
14060                                         NULL);
14061                 mtb->drop_count = cnt->action;
14062         } else {
14063                 mtb->drop_count = NULL;
14064         }
14065         /**
14066          * If flow meter has been initialized, all policer rules
14067          * are created. So can get if meter initialized by checking
14068          * any policer rule.
14069          */
14070         if (mtb->egress.drop_rule)
14071                 initialized = true;
14072         if (priv->sh->meter_aso_en) {
14073                 struct mlx5_aso_mtr *aso_mtr = NULL;
14074                 struct mlx5_aso_mtr_pool *pool;
14075
14076                 aso_mtr = container_of(fm, struct mlx5_aso_mtr, fm);
14077                 pool = container_of(aso_mtr, struct mlx5_aso_mtr_pool,
14078                                     mtrs[aso_mtr->offset]);
14079                 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, aso_mtr->offset);
14080         } else {
14081                 struct mlx5_legacy_flow_meter *legacy_fm;
14082
14083                 legacy_fm = container_of(fm, struct mlx5_legacy_flow_meter, fm);
14084                 mtr_idx = legacy_fm->idx;
14085         }
14086         if (attr->egress) {
14087                 ret = flow_dv_create_policer_forward_rule(dev,
14088                                 fm, mtr_idx, &mtb->egress,
14089                                 &egress_drop_rule, &egress_green_rule);
14090                 if (ret) {
14091                         DRV_LOG(ERR, "Failed to create egress policer.");
14092                         goto error;
14093                 }
14094         }
14095         if (attr->ingress) {
14096                 ret = flow_dv_create_policer_forward_rule(dev,
14097                                 fm, mtr_idx, &mtb->ingress,
14098                                 &ingress_drop_rule, &ingress_green_rule);
14099                 if (ret) {
14100                         DRV_LOG(ERR, "Failed to create ingress policer.");
14101                         goto error;
14102                 }
14103         }
14104         if (attr->transfer) {
14105                 ret = flow_dv_create_policer_forward_rule(dev,
14106                                 fm, mtr_idx, &mtb->transfer,
14107                                 &transfer_drop_rule, &transfer_green_rule);
14108                 if (ret) {
14109                         DRV_LOG(ERR, "Failed to create transfer policer.");
14110                         goto error;
14111                 }
14112         }
14113         /* Replace old flows if existing. */
14114         if (mtb->egress.drop_rule)
14115                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.drop_rule));
14116         if (mtb->egress.green_rule)
14117                 claim_zero(mlx5_flow_os_destroy_flow(mtb->egress.green_rule));
14118         if (mtb->ingress.drop_rule)
14119                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.drop_rule));
14120         if (mtb->ingress.green_rule)
14121                 claim_zero(mlx5_flow_os_destroy_flow(mtb->ingress.green_rule));
14122         if (mtb->transfer.drop_rule)
14123                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.drop_rule));
14124         if (mtb->transfer.green_rule)
14125                 claim_zero(mlx5_flow_os_destroy_flow(mtb->transfer.green_rule));
14126         mtb->egress.drop_rule = egress_drop_rule;
14127         mtb->egress.green_rule = egress_green_rule;
14128         mtb->ingress.drop_rule = ingress_drop_rule;
14129         mtb->ingress.green_rule = ingress_green_rule;
14130         mtb->transfer.drop_rule = transfer_drop_rule;
14131         mtb->transfer.green_rule = transfer_green_rule;
14132         return 0;
14133 error:
14134         if (egress_drop_rule)
14135                 claim_zero(mlx5_flow_os_destroy_flow(egress_drop_rule));
14136         if (egress_green_rule)
14137                 claim_zero(mlx5_flow_os_destroy_flow(egress_green_rule));
14138         if (ingress_drop_rule)
14139                 claim_zero(mlx5_flow_os_destroy_flow(ingress_drop_rule));
14140         if (ingress_green_rule)
14141                 claim_zero(mlx5_flow_os_destroy_flow(ingress_green_rule));
14142         if (transfer_drop_rule)
14143                 claim_zero(mlx5_flow_os_destroy_flow(transfer_drop_rule));
14144         if (transfer_green_rule)
14145                 claim_zero(mlx5_flow_os_destroy_flow(transfer_green_rule));
14146         if (!initialized)
14147                 flow_dv_destroy_policer_rules(dev, fm, attr);
14148         return -1;
14149 }
14150
14151 /**
14152  * Validate the batch counter support in root table.
14153  *
14154  * Create a simple flow with invalid counter and drop action on root table to
14155  * validate if batch counter with offset on root table is supported or not.
14156  *
14157  * @param[in] dev
14158  *   Pointer to rte_eth_dev structure.
14159  *
14160  * @return
14161  *   0 on success, a negative errno value otherwise and rte_errno is set.
14162  */
14163 int
14164 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
14165 {
14166         struct mlx5_priv *priv = dev->data->dev_private;
14167         struct mlx5_dev_ctx_shared *sh = priv->sh;
14168         struct mlx5_flow_dv_match_params mask = {
14169                 .size = sizeof(mask.buf),
14170         };
14171         struct mlx5_flow_dv_match_params value = {
14172                 .size = sizeof(value.buf),
14173         };
14174         struct mlx5dv_flow_matcher_attr dv_attr = {
14175                 .type = IBV_FLOW_ATTR_NORMAL,
14176                 .priority = 0,
14177                 .match_criteria_enable = 0,
14178                 .match_mask = (void *)&mask,
14179         };
14180         void *actions[2] = { 0 };
14181         struct mlx5_flow_tbl_resource *tbl = NULL;
14182         struct mlx5_devx_obj *dcs = NULL;
14183         void *matcher = NULL;
14184         void *flow = NULL;
14185         int ret = -1;
14186
14187         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
14188                                         0, 0, 0, NULL);
14189         if (!tbl)
14190                 goto err;
14191         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
14192         if (!dcs)
14193                 goto err;
14194         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
14195                                                     &actions[0]);
14196         if (ret)
14197                 goto err;
14198         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
14199                                           priv->drop_queue.hrxq->action;
14200         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
14201         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
14202                                                &matcher);
14203         if (ret)
14204                 goto err;
14205         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
14206                                        actions, &flow);
14207 err:
14208         /*
14209          * If batch counter with offset is not supported, the driver will not
14210          * validate the invalid offset value, flow create should success.
14211          * In this case, it means batch counter is not supported in root table.
14212          *
14213          * Otherwise, if flow create is failed, counter offset is supported.
14214          */
14215         if (flow) {
14216                 DRV_LOG(INFO, "Batch counter is not supported in root "
14217                               "table. Switch to fallback mode.");
14218                 rte_errno = ENOTSUP;
14219                 ret = -rte_errno;
14220                 claim_zero(mlx5_flow_os_destroy_flow(flow));
14221         } else {
14222                 /* Check matcher to make sure validate fail at flow create. */
14223                 if (!matcher || (matcher && errno != EINVAL))
14224                         DRV_LOG(ERR, "Unexpected error in counter offset "
14225                                      "support detection");
14226                 ret = 0;
14227         }
14228         if (actions[0])
14229                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
14230         if (matcher)
14231                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
14232         if (tbl)
14233                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
14234         if (dcs)
14235                 claim_zero(mlx5_devx_cmd_destroy(dcs));
14236         return ret;
14237 }
14238
14239 /**
14240  * Query a devx counter.
14241  *
14242  * @param[in] dev
14243  *   Pointer to the Ethernet device structure.
14244  * @param[in] cnt
14245  *   Index to the flow counter.
14246  * @param[in] clear
14247  *   Set to clear the counter statistics.
14248  * @param[out] pkts
14249  *   The statistics value of packets.
14250  * @param[out] bytes
14251  *   The statistics value of bytes.
14252  *
14253  * @return
14254  *   0 on success, otherwise return -1.
14255  */
14256 static int
14257 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
14258                       uint64_t *pkts, uint64_t *bytes)
14259 {
14260         struct mlx5_priv *priv = dev->data->dev_private;
14261         struct mlx5_flow_counter *cnt;
14262         uint64_t inn_pkts, inn_bytes;
14263         int ret;
14264
14265         if (!priv->config.devx)
14266                 return -1;
14267
14268         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
14269         if (ret)
14270                 return -1;
14271         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
14272         *pkts = inn_pkts - cnt->hits;
14273         *bytes = inn_bytes - cnt->bytes;
14274         if (clear) {
14275                 cnt->hits = inn_pkts;
14276                 cnt->bytes = inn_bytes;
14277         }
14278         return 0;
14279 }
14280
14281 /**
14282  * Get aged-out flows.
14283  *
14284  * @param[in] dev
14285  *   Pointer to the Ethernet device structure.
14286  * @param[in] context
14287  *   The address of an array of pointers to the aged-out flows contexts.
14288  * @param[in] nb_contexts
14289  *   The length of context array pointers.
14290  * @param[out] error
14291  *   Perform verbose error reporting if not NULL. Initialized in case of
14292  *   error only.
14293  *
14294  * @return
14295  *   how many contexts get in success, otherwise negative errno value.
14296  *   if nb_contexts is 0, return the amount of all aged contexts.
14297  *   if nb_contexts is not 0 , return the amount of aged flows reported
14298  *   in the context array.
14299  * @note: only stub for now
14300  */
14301 static int
14302 flow_get_aged_flows(struct rte_eth_dev *dev,
14303                     void **context,
14304                     uint32_t nb_contexts,
14305                     struct rte_flow_error *error)
14306 {
14307         struct mlx5_priv *priv = dev->data->dev_private;
14308         struct mlx5_age_info *age_info;
14309         struct mlx5_age_param *age_param;
14310         struct mlx5_flow_counter *counter;
14311         struct mlx5_aso_age_action *act;
14312         int nb_flows = 0;
14313
14314         if (nb_contexts && !context)
14315                 return rte_flow_error_set(error, EINVAL,
14316                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14317                                           NULL, "empty context");
14318         age_info = GET_PORT_AGE_INFO(priv);
14319         rte_spinlock_lock(&age_info->aged_sl);
14320         LIST_FOREACH(act, &age_info->aged_aso, next) {
14321                 nb_flows++;
14322                 if (nb_contexts) {
14323                         context[nb_flows - 1] =
14324                                                 act->age_params.context;
14325                         if (!(--nb_contexts))
14326                                 break;
14327                 }
14328         }
14329         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
14330                 nb_flows++;
14331                 if (nb_contexts) {
14332                         age_param = MLX5_CNT_TO_AGE(counter);
14333                         context[nb_flows - 1] = age_param->context;
14334                         if (!(--nb_contexts))
14335                                 break;
14336                 }
14337         }
14338         rte_spinlock_unlock(&age_info->aged_sl);
14339         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
14340         return nb_flows;
14341 }
14342
14343 /*
14344  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
14345  */
14346 static uint32_t
14347 flow_dv_counter_allocate(struct rte_eth_dev *dev)
14348 {
14349         return flow_dv_counter_alloc(dev, 0);
14350 }
14351
14352 /**
14353  * Validate indirect action.
14354  * Dispatcher for action type specific validation.
14355  *
14356  * @param[in] dev
14357  *   Pointer to the Ethernet device structure.
14358  * @param[in] conf
14359  *   Shared action configuration.
14360  * @param[in] action
14361  *   The indirect action object to validate.
14362  * @param[out] error
14363  *   Perform verbose error reporting if not NULL. Initialized in case of
14364  *   error only.
14365  *
14366  * @return
14367  *   0 on success, otherwise negative errno value.
14368  */
14369 static int
14370 flow_dv_action_validate(struct rte_eth_dev *dev,
14371                         const struct rte_flow_indir_action_conf *conf,
14372                         const struct rte_flow_action *action,
14373                         struct rte_flow_error *err)
14374 {
14375         struct mlx5_priv *priv = dev->data->dev_private;
14376
14377         RTE_SET_USED(conf);
14378         switch (action->type) {
14379         case RTE_FLOW_ACTION_TYPE_RSS:
14380                 /*
14381                  * priv->obj_ops is set according to driver capabilities.
14382                  * When DevX capabilities are
14383                  * sufficient, it is set to devx_obj_ops.
14384                  * Otherwise, it is set to ibv_obj_ops.
14385                  * ibv_obj_ops doesn't support ind_table_modify operation.
14386                  * In this case the shared RSS action can't be used.
14387                  */
14388                 if (priv->obj_ops.ind_table_modify == NULL)
14389                         return rte_flow_error_set
14390                                         (err, ENOTSUP,
14391                                          RTE_FLOW_ERROR_TYPE_ACTION,
14392                                          NULL,
14393                                          "shared RSS action not supported");
14394                 return mlx5_validate_action_rss(dev, action, err);
14395         case RTE_FLOW_ACTION_TYPE_AGE:
14396                 if (!priv->sh->aso_age_mng)
14397                         return rte_flow_error_set(err, ENOTSUP,
14398                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14399                                                 NULL,
14400                                              "shared age action not supported");
14401                 return flow_dv_validate_action_age(0, action, dev, err);
14402         default:
14403                 return rte_flow_error_set(err, ENOTSUP,
14404                                           RTE_FLOW_ERROR_TYPE_ACTION,
14405                                           NULL,
14406                                           "action type not supported");
14407         }
14408 }
14409
14410 static int
14411 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14412 {
14413         struct mlx5_priv *priv = dev->data->dev_private;
14414         int ret = 0;
14415
14416         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14417                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14418                                                 flags);
14419                 if (ret != 0)
14420                         return ret;
14421         }
14422         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14423                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14424                 if (ret != 0)
14425                         return ret;
14426         }
14427         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14428                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14429                 if (ret != 0)
14430                         return ret;
14431         }
14432         return 0;
14433 }
14434
14435 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14436         .validate = flow_dv_validate,
14437         .prepare = flow_dv_prepare,
14438         .translate = flow_dv_translate,
14439         .apply = flow_dv_apply,
14440         .remove = flow_dv_remove,
14441         .destroy = flow_dv_destroy,
14442         .query = flow_dv_query,
14443         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14444         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14445         .prepare_policer_rules = flow_dv_prepare_policer_rules,
14446         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14447         .create_meter = flow_dv_mtr_alloc,
14448         .free_meter = flow_dv_aso_mtr_release_to_pool,
14449         .counter_alloc = flow_dv_counter_allocate,
14450         .counter_free = flow_dv_counter_free,
14451         .counter_query = flow_dv_counter_query,
14452         .get_aged_flows = flow_get_aged_flows,
14453         .action_validate = flow_dv_action_validate,
14454         .action_create = flow_dv_action_create,
14455         .action_destroy = flow_dv_action_destroy,
14456         .action_update = flow_dv_action_update,
14457         .action_query = flow_dv_action_query,
14458         .sync_domain = flow_dv_sync_domain,
14459 };
14460
14461 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14462