drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static int
  77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  78                              struct mlx5_flow_tbl_resource *tbl);
  79
  80 /**
  81  * Initialize flow attributes structure according to flow items' types.
  82  *
  83  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  84  * mode. For tunnel mode, the items to be modified are the outermost ones.
  85  *
  86  * @param[in] item
  87  *   Pointer to item specification.
  88  * @param[out] attr
  89  *   Pointer to flow attributes structure.
  90  * @param[in] dev_flow
  91  *   Pointer to the sub flow.
  92  * @param[in] tunnel_decap
  93  *   Whether action is after tunnel decapsulation.
  94  */
  95 static void
  96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  97                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  98 {
  99         uint64_t layers = dev_flow->handle->layers;
 100
 101         /*
 102          * If layers is already initialized, it means this dev_flow is the
 103          * suffix flow, the layers flags is set by the prefix flow. Need to
 104          * use the layer flags from prefix flow as the suffix flow may not
 105          * have the user defined items as the flow is split.
 106          */
 107         if (layers) {
 108                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 109                         attr->ipv4 = 1;
 110                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 111                         attr->ipv6 = 1;
 112                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 113                         attr->tcp = 1;
 114                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 115                         attr->udp = 1;
 116                 attr->valid = 1;
 117                 return;
 118         }
 119         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 120                 uint8_t next_protocol = 0xff;
 121                 switch (item->type) {
 122                 case RTE_FLOW_ITEM_TYPE_GRE:
 123                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 126                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 127                 case RTE_FLOW_ITEM_TYPE_MPLS:
 128                         if (tunnel_decap)
 129                                 attr->attr = 0;
 130                         break;
 131                 case RTE_FLOW_ITEM_TYPE_IPV4:
 132                         if (!attr->ipv6)
 133                                 attr->ipv4 = 1;
 134                         if (item->mask != NULL &&
 135                             ((const struct rte_flow_item_ipv4 *)
 136                             item->mask)->hdr.next_proto_id)
 137                                 next_protocol =
 138                                     ((const struct rte_flow_item_ipv4 *)
 139                                       (item->spec))->hdr.next_proto_id &
 140                                     ((const struct rte_flow_item_ipv4 *)
 141                                       (item->mask))->hdr.next_proto_id;
 142                         if ((next_protocol == IPPROTO_IPIP ||
 143                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 144                                 attr->attr = 0;
 145                         break;
 146                 case RTE_FLOW_ITEM_TYPE_IPV6:
 147                         if (!attr->ipv4)
 148                                 attr->ipv6 = 1;
 149                         if (item->mask != NULL &&
 150                             ((const struct rte_flow_item_ipv6 *)
 151                             item->mask)->hdr.proto)
 152                                 next_protocol =
 153                                     ((const struct rte_flow_item_ipv6 *)
 154                                       (item->spec))->hdr.proto &
 155                                     ((const struct rte_flow_item_ipv6 *)
 156                                       (item->mask))->hdr.proto;
 157                         if ((next_protocol == IPPROTO_IPIP ||
 158                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 159                                 attr->attr = 0;
 160                         break;
 161                 case RTE_FLOW_ITEM_TYPE_UDP:
 162                         if (!attr->tcp)
 163                                 attr->udp = 1;
 164                         break;
 165                 case RTE_FLOW_ITEM_TYPE_TCP:
 166                         if (!attr->udp)
 167                                 attr->tcp = 1;
 168                         break;
 169                 default:
 170                         break;
 171                 }
 172         }
 173         attr->valid = 1;
 174 }
 175
 176 /**
 177  * Convert rte_mtr_color to mlx5 color.
 178  *
 179  * @param[in] rcol
 180  *   rte_mtr_color.
 181  *
 182  * @return
 183  *   mlx5 color.
 184  */
 185 static int
 186 rte_col_2_mlx5_col(enum rte_color rcol)
 187 {
 188         switch (rcol) {
 189         case RTE_COLOR_GREEN:
 190                 return MLX5_FLOW_COLOR_GREEN;
 191         case RTE_COLOR_YELLOW:
 192                 return MLX5_FLOW_COLOR_YELLOW;
 193         case RTE_COLOR_RED:
 194                 return MLX5_FLOW_COLOR_RED;
 195         default:
 196                 break;
 197         }
 198         return MLX5_FLOW_COLOR_UNDEFINED;
 199 }
 200
 201 struct field_modify_info {
 202         uint32_t size; /* Size of field in protocol header, in bytes. */
 203         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 204         enum mlx5_modification_field id;
 205 };
 206
 207 struct field_modify_info modify_eth[] = {
 208         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 209         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 210         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 211         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 212         {0, 0, 0},
 213 };
 214
 215 struct field_modify_info modify_vlan_out_first_vid[] = {
 216         /* Size in bits !!! */
 217         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 218         {0, 0, 0},
 219 };
 220
 221 struct field_modify_info modify_ipv4[] = {
 222         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 223         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 224         {4, 12, MLX5_MODI_OUT_SIPV4},
 225         {4, 16, MLX5_MODI_OUT_DIPV4},
 226         {0, 0, 0},
 227 };
 228
 229 struct field_modify_info modify_ipv6[] = {
 230         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 231         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 232         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 233         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 234         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 235         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 236         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 237         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 238         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 239         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 240         {0, 0, 0},
 241 };
 242
 243 struct field_modify_info modify_udp[] = {
 244         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 245         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 246         {0, 0, 0},
 247 };
 248
 249 struct field_modify_info modify_tcp[] = {
 250         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 251         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 252         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 253         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 254         {0, 0, 0},
 255 };
 256
 257 static void
 258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 259                           uint8_t next_protocol, uint64_t *item_flags,
 260                           int *tunnel)
 261 {
 262         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 263                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 264         if (next_protocol == IPPROTO_IPIP) {
 265                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 266                 *tunnel = 1;
 267         }
 268         if (next_protocol == IPPROTO_IPV6) {
 269                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 270                 *tunnel = 1;
 271         }
 272 }
 273
 274 /**
 275  * Acquire the synchronizing object to protect multithreaded access
 276  * to shared dv context. Lock occurs only if context is actually
 277  * shared, i.e. we have multiport IB device and representors are
 278  * created.
 279  *
 280  * @param[in] dev
 281  *   Pointer to the rte_eth_dev structure.
 282  */
 283 static void
 284 flow_dv_shared_lock(struct rte_eth_dev *dev)
 285 {
 286         struct mlx5_priv *priv = dev->data->dev_private;
 287         struct mlx5_ibv_shared *sh = priv->sh;
 288
 289         if (sh->dv_refcnt > 1) {
 290                 int ret;
 291
 292                 ret = pthread_mutex_lock(&sh->dv_mutex);
 293                 MLX5_ASSERT(!ret);
 294                 (void)ret;
 295         }
 296 }
 297
 298 static void
 299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 300 {
 301         struct mlx5_priv *priv = dev->data->dev_private;
 302         struct mlx5_ibv_shared *sh = priv->sh;
 303
 304         if (sh->dv_refcnt > 1) {
 305                 int ret;
 306
 307                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 308                 MLX5_ASSERT(!ret);
 309                 (void)ret;
 310         }
 311 }
 312
 313 /* Update VLAN's VID/PCP based on input rte_flow_action.
 314  *
 315  * @param[in] action
 316  *   Pointer to struct rte_flow_action.
 317  * @param[out] vlan
 318  *   Pointer to struct rte_vlan_hdr.
 319  */
 320 static void
 321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 322                          struct rte_vlan_hdr *vlan)
 323 {
 324         uint16_t vlan_tci;
 325         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 326                 vlan_tci =
 327                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 328                                                action->conf)->vlan_pcp;
 329                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 330                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 331                 vlan->vlan_tci |= vlan_tci;
 332         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 334                 vlan->vlan_tci |= rte_be_to_cpu_16
 335                     (((const struct rte_flow_action_of_set_vlan_vid *)
 336                                              action->conf)->vlan_vid);
 337         }
 338 }
 339
 340 /**
 341  * Fetch 1, 2, 3 or 4 byte field from the byte array
 342  * and return as unsigned integer in host-endian format.
 343  *
 344  * @param[in] data
 345  *   Pointer to data array.
 346  * @param[in] size
 347  *   Size of field to extract.
 348  *
 349  * @return
 350  *   converted field in host endian format.
 351  */
 352 static inline uint32_t
 353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 354 {
 355         uint32_t ret;
 356
 357         switch (size) {
 358         case 1:
 359                 ret = *data;
 360                 break;
 361         case 2:
 362                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 363                 break;
 364         case 3:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 367                 break;
 368         case 4:
 369                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 370                 break;
 371         default:
 372                 MLX5_ASSERT(false);
 373                 ret = 0;
 374                 break;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Convert modify-header action to DV specification.
 381  *
 382  * Data length of each action is determined by provided field description
 383  * and the item mask. Data bit offset and width of each action is determined
 384  * by provided item mask.
 385  *
 386  * @param[in] item
 387  *   Pointer to item specification.
 388  * @param[in] field
 389  *   Pointer to field modification information.
 390  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 393  * @param[in] dcopy
 394  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 395  *   Negative offset value sets the same offset as source offset.
 396  *   size field is ignored, value is taken from source field.
 397  * @param[in,out] resource
 398  *   Pointer to the modify-header resource.
 399  * @param[in] type
 400  *   Type of modification.
 401  * @param[out] error
 402  *   Pointer to the error structure.
 403  *
 404  * @return
 405  *   0 on success, a negative errno value otherwise and rte_errno is set.
 406  */
 407 static int
 408 flow_dv_convert_modify_action(struct rte_flow_item *item,
 409                               struct field_modify_info *field,
 410                               struct field_modify_info *dcopy,
 411                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 412                               uint32_t type, struct rte_flow_error *error)
 413 {
 414         uint32_t i = resource->actions_num;
 415         struct mlx5_modification_cmd *actions = resource->actions;
 416
 417         /*
 418          * The item and mask are provided in big-endian format.
 419          * The fields should be presented as in big-endian format either.
 420          * Mask must be always present, it defines the actual field width.
 421          */
 422         MLX5_ASSERT(item->mask);
 423         MLX5_ASSERT(field->size);
 424         do {
 425                 unsigned int size_b;
 426                 unsigned int off_b;
 427                 uint32_t mask;
 428                 uint32_t data;
 429
 430                 if (i >= MLX5_MAX_MODIFY_NUM)
 431                         return rte_flow_error_set(error, EINVAL,
 432                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 433                                  "too many items to modify");
 434                 /* Fetch variable byte size mask from the array. */
 435                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 436                                            field->offset, field->size);
 437                 if (!mask) {
 438                         ++field;
 439                         continue;
 440                 }
 441                 /* Deduce actual data width in bits from mask value. */
 442                 off_b = rte_bsf32(mask);
 443                 size_b = sizeof(uint32_t) * CHAR_BIT -
 444                          off_b - __builtin_clz(mask);
 445                 MLX5_ASSERT(size_b);
 446                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 447                 actions[i] = (struct mlx5_modification_cmd) {
 448                         .action_type = type,
 449                         .field = field->id,
 450                         .offset = off_b,
 451                         .length = size_b,
 452                 };
 453                 /* Convert entire record to expected big-endian format. */
 454                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 455                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 456                         MLX5_ASSERT(dcopy);
 457                         actions[i].dst_field = dcopy->id;
 458                         actions[i].dst_offset =
 459                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 460                         /* Convert entire record to big-endian format. */
 461                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 462                 } else {
 463                         MLX5_ASSERT(item->spec);
 464                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 465                                                    field->offset, field->size);
 466                         /* Shift out the trailing masked bits from data. */
 467                         data = (data & mask) >> off_b;
 468                         actions[i].data1 = rte_cpu_to_be_32(data);
 469                 }
 470                 ++i;
 471                 ++field;
 472         } while (field->size);
 473         if (resource->actions_num == i)
 474                 return rte_flow_error_set(error, EINVAL,
 475                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 476                                           "invalid modification flow item");
 477         resource->actions_num = i;
 478         return 0;
 479 }
 480
 481 /**
 482  * Convert modify-header set IPv4 address action to DV specification.
 483  *
 484  * @param[in,out] resource
 485  *   Pointer to the modify-header resource.
 486  * @param[in] action
 487  *   Pointer to action specification.
 488  * @param[out] error
 489  *   Pointer to the error structure.
 490  *
 491  * @return
 492  *   0 on success, a negative errno value otherwise and rte_errno is set.
 493  */
 494 static int
 495 flow_dv_convert_action_modify_ipv4
 496                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 497                          const struct rte_flow_action *action,
 498                          struct rte_flow_error *error)
 499 {
 500         const struct rte_flow_action_set_ipv4 *conf =
 501                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 502         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 503         struct rte_flow_item_ipv4 ipv4;
 504         struct rte_flow_item_ipv4 ipv4_mask;
 505
 506         memset(&ipv4, 0, sizeof(ipv4));
 507         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 508         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 509                 ipv4.hdr.src_addr = conf->ipv4_addr;
 510                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 511         } else {
 512                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 514         }
 515         item.spec = &ipv4;
 516         item.mask = &ipv4_mask;
 517         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 518                                              MLX5_MODIFICATION_TYPE_SET, error);
 519 }
 520
 521 /**
 522  * Convert modify-header set IPv6 address action to DV specification.
 523  *
 524  * @param[in,out] resource
 525  *   Pointer to the modify-header resource.
 526  * @param[in] action
 527  *   Pointer to action specification.
 528  * @param[out] error
 529  *   Pointer to the error structure.
 530  *
 531  * @return
 532  *   0 on success, a negative errno value otherwise and rte_errno is set.
 533  */
 534 static int
 535 flow_dv_convert_action_modify_ipv6
 536                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 537                          const struct rte_flow_action *action,
 538                          struct rte_flow_error *error)
 539 {
 540         const struct rte_flow_action_set_ipv6 *conf =
 541                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 542         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 543         struct rte_flow_item_ipv6 ipv6;
 544         struct rte_flow_item_ipv6 ipv6_mask;
 545
 546         memset(&ipv6, 0, sizeof(ipv6));
 547         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 548         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 549                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 550                        sizeof(ipv6.hdr.src_addr));
 551                 memcpy(&ipv6_mask.hdr.src_addr,
 552                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554         } else {
 555                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 556                        sizeof(ipv6.hdr.dst_addr));
 557                 memcpy(&ipv6_mask.hdr.dst_addr,
 558                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560         }
 561         item.spec = &ipv6;
 562         item.mask = &ipv6_mask;
 563         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 564                                              MLX5_MODIFICATION_TYPE_SET, error);
 565 }
 566
 567 /**
 568  * Convert modify-header set MAC address action to DV specification.
 569  *
 570  * @param[in,out] resource
 571  *   Pointer to the modify-header resource.
 572  * @param[in] action
 573  *   Pointer to action specification.
 574  * @param[out] error
 575  *   Pointer to the error structure.
 576  *
 577  * @return
 578  *   0 on success, a negative errno value otherwise and rte_errno is set.
 579  */
 580 static int
 581 flow_dv_convert_action_modify_mac
 582                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 583                          const struct rte_flow_action *action,
 584                          struct rte_flow_error *error)
 585 {
 586         const struct rte_flow_action_set_mac *conf =
 587                 (const struct rte_flow_action_set_mac *)(action->conf);
 588         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 589         struct rte_flow_item_eth eth;
 590         struct rte_flow_item_eth eth_mask;
 591
 592         memset(&eth, 0, sizeof(eth));
 593         memset(&eth_mask, 0, sizeof(eth_mask));
 594         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 595                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 596                        sizeof(eth.src.addr_bytes));
 597                 memcpy(&eth_mask.src.addr_bytes,
 598                        &rte_flow_item_eth_mask.src.addr_bytes,
 599                        sizeof(eth_mask.src.addr_bytes));
 600         } else {
 601                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 602                        sizeof(eth.dst.addr_bytes));
 603                 memcpy(&eth_mask.dst.addr_bytes,
 604                        &rte_flow_item_eth_mask.dst.addr_bytes,
 605                        sizeof(eth_mask.dst.addr_bytes));
 606         }
 607         item.spec = &eth;
 608         item.mask = &eth_mask;
 609         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 610                                              MLX5_MODIFICATION_TYPE_SET, error);
 611 }
 612
 613 /**
 614  * Convert modify-header set VLAN VID action to DV specification.
 615  *
 616  * @param[in,out] resource
 617  *   Pointer to the modify-header resource.
 618  * @param[in] action
 619  *   Pointer to action specification.
 620  * @param[out] error
 621  *   Pointer to the error structure.
 622  *
 623  * @return
 624  *   0 on success, a negative errno value otherwise and rte_errno is set.
 625  */
 626 static int
 627 flow_dv_convert_action_modify_vlan_vid
 628                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 629                          const struct rte_flow_action *action,
 630                          struct rte_flow_error *error)
 631 {
 632         const struct rte_flow_action_of_set_vlan_vid *conf =
 633                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 634         int i = resource->actions_num;
 635         struct mlx5_modification_cmd *actions = resource->actions;
 636         struct field_modify_info *field = modify_vlan_out_first_vid;
 637
 638         if (i >= MLX5_MAX_MODIFY_NUM)
 639                 return rte_flow_error_set(error, EINVAL,
 640                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 641                          "too many items to modify");
 642         actions[i] = (struct mlx5_modification_cmd) {
 643                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 644                 .field = field->id,
 645                 .length = field->size,
 646                 .offset = field->offset,
 647         };
 648         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 649         actions[i].data1 = conf->vlan_vid;
 650         actions[i].data1 = actions[i].data1 << 16;
 651         resource->actions_num = ++i;
 652         return 0;
 653 }
 654
 655 /**
 656  * Convert modify-header set TP action to DV specification.
 657  *
 658  * @param[in,out] resource
 659  *   Pointer to the modify-header resource.
 660  * @param[in] action
 661  *   Pointer to action specification.
 662  * @param[in] items
 663  *   Pointer to rte_flow_item objects list.
 664  * @param[in] attr
 665  *   Pointer to flow attributes structure.
 666  * @param[in] dev_flow
 667  *   Pointer to the sub flow.
 668  * @param[in] tunnel_decap
 669  *   Whether action is after tunnel decapsulation.
 670  * @param[out] error
 671  *   Pointer to the error structure.
 672  *
 673  * @return
 674  *   0 on success, a negative errno value otherwise and rte_errno is set.
 675  */
 676 static int
 677 flow_dv_convert_action_modify_tp
 678                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 679                          const struct rte_flow_action *action,
 680                          const struct rte_flow_item *items,
 681                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 682                          bool tunnel_decap, struct rte_flow_error *error)
 683 {
 684         const struct rte_flow_action_set_tp *conf =
 685                 (const struct rte_flow_action_set_tp *)(action->conf);
 686         struct rte_flow_item item;
 687         struct rte_flow_item_udp udp;
 688         struct rte_flow_item_udp udp_mask;
 689         struct rte_flow_item_tcp tcp;
 690         struct rte_flow_item_tcp tcp_mask;
 691         struct field_modify_info *field;
 692
 693         if (!attr->valid)
 694                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 695         if (attr->udp) {
 696                 memset(&udp, 0, sizeof(udp));
 697                 memset(&udp_mask, 0, sizeof(udp_mask));
 698                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 699                         udp.hdr.src_port = conf->port;
 700                         udp_mask.hdr.src_port =
 701                                         rte_flow_item_udp_mask.hdr.src_port;
 702                 } else {
 703                         udp.hdr.dst_port = conf->port;
 704                         udp_mask.hdr.dst_port =
 705                                         rte_flow_item_udp_mask.hdr.dst_port;
 706                 }
 707                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 708                 item.spec = &udp;
 709                 item.mask = &udp_mask;
 710                 field = modify_udp;
 711         } else {
 712                 MLX5_ASSERT(attr->tcp);
 713                 memset(&tcp, 0, sizeof(tcp));
 714                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 715                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 716                         tcp.hdr.src_port = conf->port;
 717                         tcp_mask.hdr.src_port =
 718                                         rte_flow_item_tcp_mask.hdr.src_port;
 719                 } else {
 720                         tcp.hdr.dst_port = conf->port;
 721                         tcp_mask.hdr.dst_port =
 722                                         rte_flow_item_tcp_mask.hdr.dst_port;
 723                 }
 724                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 725                 item.spec = &tcp;
 726                 item.mask = &tcp_mask;
 727                 field = modify_tcp;
 728         }
 729         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 730                                              MLX5_MODIFICATION_TYPE_SET, error);
 731 }
 732
 733 /**
 734  * Convert modify-header set TTL action to DV specification.
 735  *
 736  * @param[in,out] resource
 737  *   Pointer to the modify-header resource.
 738  * @param[in] action
 739  *   Pointer to action specification.
 740  * @param[in] items
 741  *   Pointer to rte_flow_item objects list.
 742  * @param[in] attr
 743  *   Pointer to flow attributes structure.
 744  * @param[in] dev_flow
 745  *   Pointer to the sub flow.
 746  * @param[in] tunnel_decap
 747  *   Whether action is after tunnel decapsulation.
 748  * @param[out] error
 749  *   Pointer to the error structure.
 750  *
 751  * @return
 752  *   0 on success, a negative errno value otherwise and rte_errno is set.
 753  */
 754 static int
 755 flow_dv_convert_action_modify_ttl
 756                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 757                          const struct rte_flow_action *action,
 758                          const struct rte_flow_item *items,
 759                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 760                          bool tunnel_decap, struct rte_flow_error *error)
 761 {
 762         const struct rte_flow_action_set_ttl *conf =
 763                 (const struct rte_flow_action_set_ttl *)(action->conf);
 764         struct rte_flow_item item;
 765         struct rte_flow_item_ipv4 ipv4;
 766         struct rte_flow_item_ipv4 ipv4_mask;
 767         struct rte_flow_item_ipv6 ipv6;
 768         struct rte_flow_item_ipv6 ipv6_mask;
 769         struct field_modify_info *field;
 770
 771         if (!attr->valid)
 772                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 773         if (attr->ipv4) {
 774                 memset(&ipv4, 0, sizeof(ipv4));
 775                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 776                 ipv4.hdr.time_to_live = conf->ttl_value;
 777                 ipv4_mask.hdr.time_to_live = 0xFF;
 778                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 779                 item.spec = &ipv4;
 780                 item.mask = &ipv4_mask;
 781                 field = modify_ipv4;
 782         } else {
 783                 MLX5_ASSERT(attr->ipv6);
 784                 memset(&ipv6, 0, sizeof(ipv6));
 785                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 786                 ipv6.hdr.hop_limits = conf->ttl_value;
 787                 ipv6_mask.hdr.hop_limits = 0xFF;
 788                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 789                 item.spec = &ipv6;
 790                 item.mask = &ipv6_mask;
 791                 field = modify_ipv6;
 792         }
 793         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 794                                              MLX5_MODIFICATION_TYPE_SET, error);
 795 }
 796
 797 /**
 798  * Convert modify-header decrement TTL action to DV specification.
 799  *
 800  * @param[in,out] resource
 801  *   Pointer to the modify-header resource.
 802  * @param[in] action
 803  *   Pointer to action specification.
 804  * @param[in] items
 805  *   Pointer to rte_flow_item objects list.
 806  * @param[in] attr
 807  *   Pointer to flow attributes structure.
 808  * @param[in] dev_flow
 809  *   Pointer to the sub flow.
 810  * @param[in] tunnel_decap
 811  *   Whether action is after tunnel decapsulation.
 812  * @param[out] error
 813  *   Pointer to the error structure.
 814  *
 815  * @return
 816  *   0 on success, a negative errno value otherwise and rte_errno is set.
 817  */
 818 static int
 819 flow_dv_convert_action_modify_dec_ttl
 820                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 821                          const struct rte_flow_item *items,
 822                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 823                          bool tunnel_decap, struct rte_flow_error *error)
 824 {
 825         struct rte_flow_item item;
 826         struct rte_flow_item_ipv4 ipv4;
 827         struct rte_flow_item_ipv4 ipv4_mask;
 828         struct rte_flow_item_ipv6 ipv6;
 829         struct rte_flow_item_ipv6 ipv6_mask;
 830         struct field_modify_info *field;
 831
 832         if (!attr->valid)
 833                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 834         if (attr->ipv4) {
 835                 memset(&ipv4, 0, sizeof(ipv4));
 836                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 837                 ipv4.hdr.time_to_live = 0xFF;
 838                 ipv4_mask.hdr.time_to_live = 0xFF;
 839                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 840                 item.spec = &ipv4;
 841                 item.mask = &ipv4_mask;
 842                 field = modify_ipv4;
 843         } else {
 844                 MLX5_ASSERT(attr->ipv6);
 845                 memset(&ipv6, 0, sizeof(ipv6));
 846                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 847                 ipv6.hdr.hop_limits = 0xFF;
 848                 ipv6_mask.hdr.hop_limits = 0xFF;
 849                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 850                 item.spec = &ipv6;
 851                 item.mask = &ipv6_mask;
 852                 field = modify_ipv6;
 853         }
 854         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 855                                              MLX5_MODIFICATION_TYPE_ADD, error);
 856 }
 857
 858 /**
 859  * Convert modify-header increment/decrement TCP Sequence number
 860  * to DV specification.
 861  *
 862  * @param[in,out] resource
 863  *   Pointer to the modify-header resource.
 864  * @param[in] action
 865  *   Pointer to action specification.
 866  * @param[out] error
 867  *   Pointer to the error structure.
 868  *
 869  * @return
 870  *   0 on success, a negative errno value otherwise and rte_errno is set.
 871  */
 872 static int
 873 flow_dv_convert_action_modify_tcp_seq
 874                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 875                          const struct rte_flow_action *action,
 876                          struct rte_flow_error *error)
 877 {
 878         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 879         uint64_t value = rte_be_to_cpu_32(*conf);
 880         struct rte_flow_item item;
 881         struct rte_flow_item_tcp tcp;
 882         struct rte_flow_item_tcp tcp_mask;
 883
 884         memset(&tcp, 0, sizeof(tcp));
 885         memset(&tcp_mask, 0, sizeof(tcp_mask));
 886         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 887                 /*
 888                  * The HW has no decrement operation, only increment operation.
 889                  * To simulate decrement X from Y using increment operation
 890                  * we need to add UINT32_MAX X times to Y.
 891                  * Each adding of UINT32_MAX decrements Y by 1.
 892                  */
 893                 value *= UINT32_MAX;
 894         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 895         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 896         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 897         item.spec = &tcp;
 898         item.mask = &tcp_mask;
 899         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 900                                              MLX5_MODIFICATION_TYPE_ADD, error);
 901 }
 902
 903 /**
 904  * Convert modify-header increment/decrement TCP Acknowledgment number
 905  * to DV specification.
 906  *
 907  * @param[in,out] resource
 908  *   Pointer to the modify-header resource.
 909  * @param[in] action
 910  *   Pointer to action specification.
 911  * @param[out] error
 912  *   Pointer to the error structure.
 913  *
 914  * @return
 915  *   0 on success, a negative errno value otherwise and rte_errno is set.
 916  */
 917 static int
 918 flow_dv_convert_action_modify_tcp_ack
 919                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 920                          const struct rte_flow_action *action,
 921                          struct rte_flow_error *error)
 922 {
 923         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 924         uint64_t value = rte_be_to_cpu_32(*conf);
 925         struct rte_flow_item item;
 926         struct rte_flow_item_tcp tcp;
 927         struct rte_flow_item_tcp tcp_mask;
 928
 929         memset(&tcp, 0, sizeof(tcp));
 930         memset(&tcp_mask, 0, sizeof(tcp_mask));
 931         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 932                 /*
 933                  * The HW has no decrement operation, only increment operation.
 934                  * To simulate decrement X from Y using increment operation
 935                  * we need to add UINT32_MAX X times to Y.
 936                  * Each adding of UINT32_MAX decrements Y by 1.
 937                  */
 938                 value *= UINT32_MAX;
 939         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 940         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 941         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 942         item.spec = &tcp;
 943         item.mask = &tcp_mask;
 944         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 945                                              MLX5_MODIFICATION_TYPE_ADD, error);
 946 }
 947
 948 static enum mlx5_modification_field reg_to_field[] = {
 949         [REG_NONE] = MLX5_MODI_OUT_NONE,
 950         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 951         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 952         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 953         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 954         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 955         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 956         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 957         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 958         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 959         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 960 };
 961
 962 /**
 963  * Convert register set to DV specification.
 964  *
 965  * @param[in,out] resource
 966  *   Pointer to the modify-header resource.
 967  * @param[in] action
 968  *   Pointer to action specification.
 969  * @param[out] error
 970  *   Pointer to the error structure.
 971  *
 972  * @return
 973  *   0 on success, a negative errno value otherwise and rte_errno is set.
 974  */
 975 static int
 976 flow_dv_convert_action_set_reg
 977                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 978                          const struct rte_flow_action *action,
 979                          struct rte_flow_error *error)
 980 {
 981         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 982         struct mlx5_modification_cmd *actions = resource->actions;
 983         uint32_t i = resource->actions_num;
 984
 985         if (i >= MLX5_MAX_MODIFY_NUM)
 986                 return rte_flow_error_set(error, EINVAL,
 987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 988                                           "too many items to modify");
 989         MLX5_ASSERT(conf->id != REG_NONE);
 990         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 991         actions[i] = (struct mlx5_modification_cmd) {
 992                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 993                 .field = reg_to_field[conf->id],
 994         };
 995         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 996         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 997         ++i;
 998         resource->actions_num = i;
 999         return 0;
1000 }
1001
1002 /**
1003  * Convert SET_TAG action to DV specification.
1004  *
1005  * @param[in] dev
1006  *   Pointer to the rte_eth_dev structure.
1007  * @param[in,out] resource
1008  *   Pointer to the modify-header resource.
1009  * @param[in] conf
1010  *   Pointer to action specification.
1011  * @param[out] error
1012  *   Pointer to the error structure.
1013  *
1014  * @return
1015  *   0 on success, a negative errno value otherwise and rte_errno is set.
1016  */
1017 static int
1018 flow_dv_convert_action_set_tag
1019                         (struct rte_eth_dev *dev,
1020                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1021                          const struct rte_flow_action_set_tag *conf,
1022                          struct rte_flow_error *error)
1023 {
1024         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026         struct rte_flow_item item = {
1027                 .spec = &data,
1028                 .mask = &mask,
1029         };
1030         struct field_modify_info reg_c_x[] = {
1031                 [1] = {0, 0, 0},
1032         };
1033         enum mlx5_modification_field reg_type;
1034         int ret;
1035
1036         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1037         if (ret < 0)
1038                 return ret;
1039         MLX5_ASSERT(ret != REG_NONE);
1040         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041         reg_type = reg_to_field[ret];
1042         MLX5_ASSERT(reg_type > 0);
1043         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045                                              MLX5_MODIFICATION_TYPE_SET, error);
1046 }
1047
1048 /**
1049  * Convert internal COPY_REG action to DV specification.
1050  *
1051  * @param[in] dev
1052  *   Pointer to the rte_eth_dev structure.
1053  * @param[in,out] res
1054  *   Pointer to the modify-header resource.
1055  * @param[in] action
1056  *   Pointer to action specification.
1057  * @param[out] error
1058  *   Pointer to the error structure.
1059  *
1060  * @return
1061  *   0 on success, a negative errno value otherwise and rte_errno is set.
1062  */
1063 static int
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1066                                  const struct rte_flow_action *action,
1067                                  struct rte_flow_error *error)
1068 {
1069         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071         struct rte_flow_item item = {
1072                 .spec = NULL,
1073                 .mask = &mask,
1074         };
1075         struct field_modify_info reg_src[] = {
1076                 {4, 0, reg_to_field[conf->src]},
1077                 {0, 0, 0},
1078         };
1079         struct field_modify_info reg_dst = {
1080                 .offset = 0,
1081                 .id = reg_to_field[conf->dst],
1082         };
1083         /* Adjust reg_c[0] usage according to reported mask. */
1084         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085                 struct mlx5_priv *priv = dev->data->dev_private;
1086                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087
1088                 MLX5_ASSERT(reg_c0);
1089                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090                 if (conf->dst == REG_C_0) {
1091                         /* Copy to reg_c[0], within mask only. */
1092                         reg_dst.offset = rte_bsf32(reg_c0);
1093                         /*
1094                          * Mask is ignoring the enianness, because
1095                          * there is no conversion in datapath.
1096                          */
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098                         /* Copy from destination lower bits to reg_c[0]. */
1099                         mask = reg_c0 >> reg_dst.offset;
1100 #else
1101                         /* Copy from destination upper bits to reg_c[0]. */
1102                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103                                           rte_fls_u32(reg_c0));
1104 #endif
1105                 } else {
1106                         mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108                         /* Copy from reg_c[0] to destination lower bits. */
1109                         reg_dst.offset = 0;
1110 #else
1111                         /* Copy from reg_c[0] to destination upper bits. */
1112                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113                                          (rte_fls_u32(reg_c0) -
1114                                           rte_bsf32(reg_c0));
1115 #endif
1116                 }
1117         }
1118         return flow_dv_convert_modify_action(&item,
1119                                              reg_src, &reg_dst, res,
1120                                              MLX5_MODIFICATION_TYPE_COPY,
1121                                              error);
1122 }
1123
1124 /**
1125  * Convert MARK action to DV specification. This routine is used
1126  * in extensive metadata only and requires metadata register to be
1127  * handled. In legacy mode hardware tag resource is engaged.
1128  *
1129  * @param[in] dev
1130  *   Pointer to the rte_eth_dev structure.
1131  * @param[in] conf
1132  *   Pointer to MARK action specification.
1133  * @param[in,out] resource
1134  *   Pointer to the modify-header resource.
1135  * @param[out] error
1136  *   Pointer to the error structure.
1137  *
1138  * @return
1139  *   0 on success, a negative errno value otherwise and rte_errno is set.
1140  */
1141 static int
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143                             const struct rte_flow_action_mark *conf,
1144                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1145                             struct rte_flow_error *error)
1146 {
1147         struct mlx5_priv *priv = dev->data->dev_private;
1148         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149                                            priv->sh->dv_mark_mask);
1150         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151         struct rte_flow_item item = {
1152                 .spec = &data,
1153                 .mask = &mask,
1154         };
1155         struct field_modify_info reg_c_x[] = {
1156                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1157                 {0, 0, 0},
1158         };
1159         int reg;
1160
1161         if (!mask)
1162                 return rte_flow_error_set(error, EINVAL,
1163                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164                                           NULL, "zero mark action mask");
1165         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1166         if (reg < 0)
1167                 return reg;
1168         MLX5_ASSERT(reg > 0);
1169         if (reg == REG_C_0) {
1170                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172
1173                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175                 mask = rte_cpu_to_be_32(mask << shl_c0);
1176         }
1177         reg_c_x[0].id = reg_to_field[reg];
1178         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179                                              MLX5_MODIFICATION_TYPE_SET, error);
1180 }
1181
1182 /**
1183  * Get metadata register index for specified steering domain.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in] attr
1188  *   Attributes of flow to determine steering domain.
1189  * @param[out] error
1190  *   Pointer to the error structure.
1191  *
1192  * @return
1193  *   positive index on success, a negative errno value otherwise
1194  *   and rte_errno is set.
1195  */
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198                          const struct rte_flow_attr *attr,
1199                          struct rte_flow_error *error)
1200 {
1201         int reg =
1202                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1203                                           MLX5_METADATA_FDB :
1204                                             attr->egress ?
1205                                             MLX5_METADATA_TX :
1206                                             MLX5_METADATA_RX, 0, error);
1207         if (reg < 0)
1208                 return rte_flow_error_set(error,
1209                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210                                           NULL, "unavailable "
1211                                           "metadata register");
1212         return reg;
1213 }
1214
1215 /**
1216  * Convert SET_META action to DV specification.
1217  *
1218  * @param[in] dev
1219  *   Pointer to the rte_eth_dev structure.
1220  * @param[in,out] resource
1221  *   Pointer to the modify-header resource.
1222  * @param[in] attr
1223  *   Attributes of flow that includes this item.
1224  * @param[in] conf
1225  *   Pointer to action specification.
1226  * @param[out] error
1227  *   Pointer to the error structure.
1228  *
1229  * @return
1230  *   0 on success, a negative errno value otherwise and rte_errno is set.
1231  */
1232 static int
1233 flow_dv_convert_action_set_meta
1234                         (struct rte_eth_dev *dev,
1235                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1236                          const struct rte_flow_attr *attr,
1237                          const struct rte_flow_action_set_meta *conf,
1238                          struct rte_flow_error *error)
1239 {
1240         uint32_t data = conf->data;
1241         uint32_t mask = conf->mask;
1242         struct rte_flow_item item = {
1243                 .spec = &data,
1244                 .mask = &mask,
1245         };
1246         struct field_modify_info reg_c_x[] = {
1247                 [1] = {0, 0, 0},
1248         };
1249         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250
1251         if (reg < 0)
1252                 return reg;
1253         /*
1254          * In datapath code there is no endianness
1255          * coversions for perfromance reasons, all
1256          * pattern conversions are done in rte_flow.
1257          */
1258         if (reg == REG_C_0) {
1259                 struct mlx5_priv *priv = dev->data->dev_private;
1260                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1261                 uint32_t shl_c0;
1262
1263                 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265                 shl_c0 = rte_bsf32(msk_c0);
1266 #else
1267                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1268 #endif
1269                 mask <<= shl_c0;
1270                 data <<= shl_c0;
1271                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272         }
1273         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274         /* The routine expects parameters in memory as big-endian ones. */
1275         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276                                              MLX5_MODIFICATION_TYPE_SET, error);
1277 }
1278
1279 /**
1280  * Convert modify-header set IPv4 DSCP action to DV specification.
1281  *
1282  * @param[in,out] resource
1283  *   Pointer to the modify-header resource.
1284  * @param[in] action
1285  *   Pointer to action specification.
1286  * @param[out] error
1287  *   Pointer to the error structure.
1288  *
1289  * @return
1290  *   0 on success, a negative errno value otherwise and rte_errno is set.
1291  */
1292 static int
1293 flow_dv_convert_action_modify_ipv4_dscp
1294                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295                          const struct rte_flow_action *action,
1296                          struct rte_flow_error *error)
1297 {
1298         const struct rte_flow_action_set_dscp *conf =
1299                 (const struct rte_flow_action_set_dscp *)(action->conf);
1300         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301         struct rte_flow_item_ipv4 ipv4;
1302         struct rte_flow_item_ipv4 ipv4_mask;
1303
1304         memset(&ipv4, 0, sizeof(ipv4));
1305         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306         ipv4.hdr.type_of_service = conf->dscp;
1307         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308         item.spec = &ipv4;
1309         item.mask = &ipv4_mask;
1310         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311                                              MLX5_MODIFICATION_TYPE_SET, error);
1312 }
1313
1314 /**
1315  * Convert modify-header set IPv6 DSCP action to DV specification.
1316  *
1317  * @param[in,out] resource
1318  *   Pointer to the modify-header resource.
1319  * @param[in] action
1320  *   Pointer to action specification.
1321  * @param[out] error
1322  *   Pointer to the error structure.
1323  *
1324  * @return
1325  *   0 on success, a negative errno value otherwise and rte_errno is set.
1326  */
1327 static int
1328 flow_dv_convert_action_modify_ipv6_dscp
1329                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330                          const struct rte_flow_action *action,
1331                          struct rte_flow_error *error)
1332 {
1333         const struct rte_flow_action_set_dscp *conf =
1334                 (const struct rte_flow_action_set_dscp *)(action->conf);
1335         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336         struct rte_flow_item_ipv6 ipv6;
1337         struct rte_flow_item_ipv6 ipv6_mask;
1338
1339         memset(&ipv6, 0, sizeof(ipv6));
1340         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341         /*
1342          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343          * rdma-core only accept the DSCP bits byte aligned start from
1344          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345          * bits in IPv6 case as rdma-core requires byte aligned value.
1346          */
1347         ipv6.hdr.vtc_flow = conf->dscp;
1348         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349         item.spec = &ipv6;
1350         item.mask = &ipv6_mask;
1351         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352                                              MLX5_MODIFICATION_TYPE_SET, error);
1353 }
1354
1355 /**
1356  * Validate MARK item.
1357  *
1358  * @param[in] dev
1359  *   Pointer to the rte_eth_dev structure.
1360  * @param[in] item
1361  *   Item specification.
1362  * @param[in] attr
1363  *   Attributes of flow that includes this item.
1364  * @param[out] error
1365  *   Pointer to error structure.
1366  *
1367  * @return
1368  *   0 on success, a negative errno value otherwise and rte_errno is set.
1369  */
1370 static int
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372                            const struct rte_flow_item *item,
1373                            const struct rte_flow_attr *attr __rte_unused,
1374                            struct rte_flow_error *error)
1375 {
1376         struct mlx5_priv *priv = dev->data->dev_private;
1377         struct mlx5_dev_config *config = &priv->config;
1378         const struct rte_flow_item_mark *spec = item->spec;
1379         const struct rte_flow_item_mark *mask = item->mask;
1380         const struct rte_flow_item_mark nic_mask = {
1381                 .id = priv->sh->dv_mark_mask,
1382         };
1383         int ret;
1384
1385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386                 return rte_flow_error_set(error, ENOTSUP,
1387                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1388                                           "extended metadata feature"
1389                                           " isn't enabled");
1390         if (!mlx5_flow_ext_mreg_supported(dev))
1391                 return rte_flow_error_set(error, ENOTSUP,
1392                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1393                                           "extended metadata register"
1394                                           " isn't supported");
1395         if (!nic_mask.id)
1396                 return rte_flow_error_set(error, ENOTSUP,
1397                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1398                                           "extended metadata register"
1399                                           " isn't available");
1400         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1401         if (ret < 0)
1402                 return ret;
1403         if (!spec)
1404                 return rte_flow_error_set(error, EINVAL,
1405                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406                                           item->spec,
1407                                           "data cannot be empty");
1408         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409                 return rte_flow_error_set(error, EINVAL,
1410                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411                                           &spec->id,
1412                                           "mark id exceeds the limit");
1413         if (!mask)
1414                 mask = &nic_mask;
1415         if (!mask->id)
1416                 return rte_flow_error_set(error, EINVAL,
1417                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418                                         "mask cannot be zero");
1419
1420         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421                                         (const uint8_t *)&nic_mask,
1422                                         sizeof(struct rte_flow_item_mark),
1423                                         error);
1424         if (ret < 0)
1425                 return ret;
1426         return 0;
1427 }
1428
1429 /**
1430  * Validate META item.
1431  *
1432  * @param[in] dev
1433  *   Pointer to the rte_eth_dev structure.
1434  * @param[in] item
1435  *   Item specification.
1436  * @param[in] attr
1437  *   Attributes of flow that includes this item.
1438  * @param[out] error
1439  *   Pointer to error structure.
1440  *
1441  * @return
1442  *   0 on success, a negative errno value otherwise and rte_errno is set.
1443  */
1444 static int
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446                            const struct rte_flow_item *item,
1447                            const struct rte_flow_attr *attr,
1448                            struct rte_flow_error *error)
1449 {
1450         struct mlx5_priv *priv = dev->data->dev_private;
1451         struct mlx5_dev_config *config = &priv->config;
1452         const struct rte_flow_item_meta *spec = item->spec;
1453         const struct rte_flow_item_meta *mask = item->mask;
1454         struct rte_flow_item_meta nic_mask = {
1455                 .data = UINT32_MAX
1456         };
1457         int reg;
1458         int ret;
1459
1460         if (!spec)
1461                 return rte_flow_error_set(error, EINVAL,
1462                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463                                           item->spec,
1464                                           "data cannot be empty");
1465         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466                 if (!mlx5_flow_ext_mreg_supported(dev))
1467                         return rte_flow_error_set(error, ENOTSUP,
1468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1469                                           "extended metadata register"
1470                                           " isn't supported");
1471                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1472                 if (reg < 0)
1473                         return reg;
1474                 if (reg == REG_B)
1475                         return rte_flow_error_set(error, ENOTSUP,
1476                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1477                                           "match on reg_b "
1478                                           "isn't supported");
1479                 if (reg != REG_A)
1480                         nic_mask.data = priv->sh->dv_meta_mask;
1481         }
1482         if (!mask)
1483                 mask = &rte_flow_item_meta_mask;
1484         if (!mask->data)
1485                 return rte_flow_error_set(error, EINVAL,
1486                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487                                         "mask cannot be zero");
1488
1489         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490                                         (const uint8_t *)&nic_mask,
1491                                         sizeof(struct rte_flow_item_meta),
1492                                         error);
1493         return ret;
1494 }
1495
1496 /**
1497  * Validate TAG item.
1498  *
1499  * @param[in] dev
1500  *   Pointer to the rte_eth_dev structure.
1501  * @param[in] item
1502  *   Item specification.
1503  * @param[in] attr
1504  *   Attributes of flow that includes this item.
1505  * @param[out] error
1506  *   Pointer to error structure.
1507  *
1508  * @return
1509  *   0 on success, a negative errno value otherwise and rte_errno is set.
1510  */
1511 static int
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513                           const struct rte_flow_item *item,
1514                           const struct rte_flow_attr *attr __rte_unused,
1515                           struct rte_flow_error *error)
1516 {
1517         const struct rte_flow_item_tag *spec = item->spec;
1518         const struct rte_flow_item_tag *mask = item->mask;
1519         const struct rte_flow_item_tag nic_mask = {
1520                 .data = RTE_BE32(UINT32_MAX),
1521                 .index = 0xff,
1522         };
1523         int ret;
1524
1525         if (!mlx5_flow_ext_mreg_supported(dev))
1526                 return rte_flow_error_set(error, ENOTSUP,
1527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1528                                           "extensive metadata register"
1529                                           " isn't supported");
1530         if (!spec)
1531                 return rte_flow_error_set(error, EINVAL,
1532                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1533                                           item->spec,
1534                                           "data cannot be empty");
1535         if (!mask)
1536                 mask = &rte_flow_item_tag_mask;
1537         if (!mask->data)
1538                 return rte_flow_error_set(error, EINVAL,
1539                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540                                         "mask cannot be zero");
1541
1542         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543                                         (const uint8_t *)&nic_mask,
1544                                         sizeof(struct rte_flow_item_tag),
1545                                         error);
1546         if (ret < 0)
1547                 return ret;
1548         if (mask->index != 0xff)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                           "partial mask for tag index"
1552                                           " is not supported");
1553         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1554         if (ret < 0)
1555                 return ret;
1556         MLX5_ASSERT(ret != REG_NONE);
1557         return 0;
1558 }
1559
1560 /**
1561  * Validate vport item.
1562  *
1563  * @param[in] dev
1564  *   Pointer to the rte_eth_dev structure.
1565  * @param[in] item
1566  *   Item specification.
1567  * @param[in] attr
1568  *   Attributes of flow that includes this item.
1569  * @param[in] item_flags
1570  *   Bit-fields that holds the items detected until now.
1571  * @param[out] error
1572  *   Pointer to error structure.
1573  *
1574  * @return
1575  *   0 on success, a negative errno value otherwise and rte_errno is set.
1576  */
1577 static int
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579                               const struct rte_flow_item *item,
1580                               const struct rte_flow_attr *attr,
1581                               uint64_t item_flags,
1582                               struct rte_flow_error *error)
1583 {
1584         const struct rte_flow_item_port_id *spec = item->spec;
1585         const struct rte_flow_item_port_id *mask = item->mask;
1586         const struct rte_flow_item_port_id switch_mask = {
1587                         .id = 0xffffffff,
1588         };
1589         struct mlx5_priv *esw_priv;
1590         struct mlx5_priv *dev_priv;
1591         int ret;
1592
1593         if (!attr->transfer)
1594                 return rte_flow_error_set(error, EINVAL,
1595                                           RTE_FLOW_ERROR_TYPE_ITEM,
1596                                           NULL,
1597                                           "match on port id is valid only"
1598                                           " when transfer flag is enabled");
1599         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600                 return rte_flow_error_set(error, ENOTSUP,
1601                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1602                                           "multiple source ports are not"
1603                                           " supported");
1604         if (!mask)
1605                 mask = &switch_mask;
1606         if (mask->id != 0xffffffff)
1607                 return rte_flow_error_set(error, ENOTSUP,
1608                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1609                                            mask,
1610                                            "no support for partial mask on"
1611                                            " \"id\" field");
1612         ret = mlx5_flow_item_acceptable
1613                                 (item, (const uint8_t *)mask,
1614                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1615                                  sizeof(struct rte_flow_item_port_id),
1616                                  error);
1617         if (ret)
1618                 return ret;
1619         if (!spec)
1620                 return 0;
1621         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1622         if (!esw_priv)
1623                 return rte_flow_error_set(error, rte_errno,
1624                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625                                           "failed to obtain E-Switch info for"
1626                                           " port");
1627         dev_priv = mlx5_dev_to_eswitch_info(dev);
1628         if (!dev_priv)
1629                 return rte_flow_error_set(error, rte_errno,
1630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1631                                           NULL,
1632                                           "failed to obtain E-Switch info");
1633         if (esw_priv->domain_id != dev_priv->domain_id)
1634                 return rte_flow_error_set(error, EINVAL,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "cannot match on a port from a"
1637                                           " different E-Switch");
1638         return 0;
1639 }
1640
1641 /**
1642  * Validate GTP item.
1643  *
1644  * @param[in] dev
1645  *   Pointer to the rte_eth_dev structure.
1646  * @param[in] item
1647  *   Item specification.
1648  * @param[in] item_flags
1649  *   Bit-fields that holds the items detected until now.
1650  * @param[out] error
1651  *   Pointer to error structure.
1652  *
1653  * @return
1654  *   0 on success, a negative errno value otherwise and rte_errno is set.
1655  */
1656 static int
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658                           const struct rte_flow_item *item,
1659                           uint64_t item_flags,
1660                           struct rte_flow_error *error)
1661 {
1662         struct mlx5_priv *priv = dev->data->dev_private;
1663         const struct rte_flow_item_gtp *mask = item->mask;
1664         const struct rte_flow_item_gtp nic_mask = {
1665                 .msg_type = 0xff,
1666                 .teid = RTE_BE32(0xffffffff),
1667         };
1668
1669         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670                 return rte_flow_error_set(error, ENOTSUP,
1671                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1672                                           "GTP support is not enabled");
1673         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674                 return rte_flow_error_set(error, ENOTSUP,
1675                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1676                                           "multiple tunnel layers not"
1677                                           " supported");
1678         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679                 return rte_flow_error_set(error, EINVAL,
1680                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1681                                           "no outer UDP layer found");
1682         if (!mask)
1683                 mask = &rte_flow_item_gtp_mask;
1684         return mlx5_flow_item_acceptable
1685                 (item, (const uint8_t *)mask,
1686                  (const uint8_t *)&nic_mask,
1687                  sizeof(struct rte_flow_item_gtp),
1688                  error);
1689 }
1690
1691 /**
1692  * Validate the pop VLAN action.
1693  *
1694  * @param[in] dev
1695  *   Pointer to the rte_eth_dev structure.
1696  * @param[in] action_flags
1697  *   Holds the actions detected until now.
1698  * @param[in] action
1699  *   Pointer to the pop vlan action.
1700  * @param[in] item_flags
1701  *   The items found in this flow rule.
1702  * @param[in] attr
1703  *   Pointer to flow attributes.
1704  * @param[out] error
1705  *   Pointer to error structure.
1706  *
1707  * @return
1708  *   0 on success, a negative errno value otherwise and rte_errno is set.
1709  */
1710 static int
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712                                  uint64_t action_flags,
1713                                  const struct rte_flow_action *action,
1714                                  uint64_t item_flags,
1715                                  const struct rte_flow_attr *attr,
1716                                  struct rte_flow_error *error)
1717 {
1718         const struct mlx5_priv *priv = dev->data->dev_private;
1719
1720         (void)action;
1721         (void)attr;
1722         if (!priv->sh->pop_vlan_action)
1723                 return rte_flow_error_set(error, ENOTSUP,
1724                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1725                                           NULL,
1726                                           "pop vlan action is not supported");
1727         if (attr->egress)
1728                 return rte_flow_error_set(error, ENOTSUP,
1729                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1730                                           NULL,
1731                                           "pop vlan action not supported for "
1732                                           "egress");
1733         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734                 return rte_flow_error_set(error, ENOTSUP,
1735                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1736                                           "no support for multiple VLAN "
1737                                           "actions");
1738         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739                 return rte_flow_error_set(error, ENOTSUP,
1740                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1741                                           NULL,
1742                                           "cannot pop vlan without a "
1743                                           "match on (outer) vlan in the flow");
1744         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745                 return rte_flow_error_set(error, EINVAL,
1746                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1747                                           "wrong action order, port_id should "
1748                                           "be after pop VLAN action");
1749         if (!attr->transfer && priv->representor)
1750                 return rte_flow_error_set(error, ENOTSUP,
1751                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752                                           "pop vlan action for VF representor "
1753                                           "not supported on NIC table");
1754         return 0;
1755 }
1756
1757 /**
1758  * Get VLAN default info from vlan match info.
1759  *
1760  * @param[in] items
1761  *   the list of item specifications.
1762  * @param[out] vlan
1763  *   pointer VLAN info to fill to.
1764  *
1765  * @return
1766  *   0 on success, a negative errno value otherwise and rte_errno is set.
1767  */
1768 static void
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770                                   struct rte_vlan_hdr *vlan)
1771 {
1772         const struct rte_flow_item_vlan nic_mask = {
1773                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774                                 MLX5DV_FLOW_VLAN_VID_MASK),
1775                 .inner_type = RTE_BE16(0xffff),
1776         };
1777
1778         if (items == NULL)
1779                 return;
1780         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781                 int type = items->type;
1782
1783                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1785                         break;
1786         }
1787         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1790
1791                 if (!vlan_m)
1792                         vlan_m = &nic_mask;
1793                 /* Only full match values are accepted */
1794                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1797                         vlan->vlan_tci |=
1798                                 rte_be_to_cpu_16(vlan_v->tci &
1799                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1800                 }
1801                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1804                         vlan->vlan_tci |=
1805                                 rte_be_to_cpu_16(vlan_v->tci &
1806                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1807                 }
1808                 if (vlan_m->inner_type == nic_mask.inner_type)
1809                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810                                                            vlan_m->inner_type);
1811         }
1812 }
1813
1814 /**
1815  * Validate the push VLAN action.
1816  *
1817  * @param[in] dev
1818  *   Pointer to the rte_eth_dev structure.
1819  * @param[in] action_flags
1820  *   Holds the actions detected until now.
1821  * @param[in] item_flags
1822  *   The items found in this flow rule.
1823  * @param[in] action
1824  *   Pointer to the action structure.
1825  * @param[in] attr
1826  *   Pointer to flow attributes
1827  * @param[out] error
1828  *   Pointer to error structure.
1829  *
1830  * @return
1831  *   0 on success, a negative errno value otherwise and rte_errno is set.
1832  */
1833 static int
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835                                   uint64_t action_flags,
1836                                   const struct rte_flow_item_vlan *vlan_m,
1837                                   const struct rte_flow_action *action,
1838                                   const struct rte_flow_attr *attr,
1839                                   struct rte_flow_error *error)
1840 {
1841         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842         const struct mlx5_priv *priv = dev->data->dev_private;
1843
1844         if (!attr->transfer && attr->ingress)
1845                 return rte_flow_error_set(error, ENOTSUP,
1846                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1847                                           NULL,
1848                                           "push VLAN action not supported for "
1849                                           "ingress");
1850         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1854                                           "invalid vlan ethertype");
1855         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856                 return rte_flow_error_set(error, ENOTSUP,
1857                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1858                                           "no support for multiple VLAN "
1859                                           "actions");
1860         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861                 return rte_flow_error_set(error, EINVAL,
1862                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1863                                           "wrong action order, port_id should "
1864                                           "be after push VLAN");
1865         if (!attr->transfer && priv->representor)
1866                 return rte_flow_error_set(error, ENOTSUP,
1867                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868                                           "push vlan action for VF representor "
1869                                           "not supported on NIC table");
1870         if (vlan_m &&
1871             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875             !(mlx5_flow_find_action
1876                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877                 return rte_flow_error_set(error, EINVAL,
1878                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1879                                           "not full match mask on VLAN PCP and "
1880                                           "there is no of_set_vlan_pcp action, "
1881                                           "push VLAN action cannot figure out "
1882                                           "PCP value");
1883         if (vlan_m &&
1884             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888             !(mlx5_flow_find_action
1889                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890                 return rte_flow_error_set(error, EINVAL,
1891                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1892                                           "not full match mask on VLAN VID and "
1893                                           "there is no of_set_vlan_vid action, "
1894                                           "push VLAN action cannot figure out "
1895                                           "VID value");
1896         (void)attr;
1897         return 0;
1898 }
1899
1900 /**
1901  * Validate the set VLAN PCP.
1902  *
1903  * @param[in] action_flags
1904  *   Holds the actions detected until now.
1905  * @param[in] actions
1906  *   Pointer to the list of actions remaining in the flow rule.
1907  * @param[out] error
1908  *   Pointer to error structure.
1909  *
1910  * @return
1911  *   0 on success, a negative errno value otherwise and rte_errno is set.
1912  */
1913 static int
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915                                      const struct rte_flow_action actions[],
1916                                      struct rte_flow_error *error)
1917 {
1918         const struct rte_flow_action *action = actions;
1919         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1920
1921         if (conf->vlan_pcp > 7)
1922                 return rte_flow_error_set(error, EINVAL,
1923                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1924                                           "VLAN PCP value is too big");
1925         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1928                                           "set VLAN PCP action must follow "
1929                                           "the push VLAN action");
1930         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931                 return rte_flow_error_set(error, ENOTSUP,
1932                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1933                                           "Multiple VLAN PCP modification are "
1934                                           "not supported");
1935         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936                 return rte_flow_error_set(error, EINVAL,
1937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1938                                           "wrong action order, port_id should "
1939                                           "be after set VLAN PCP");
1940         return 0;
1941 }
1942
1943 /**
1944  * Validate the set VLAN VID.
1945  *
1946  * @param[in] item_flags
1947  *   Holds the items detected in this rule.
1948  * @param[in] action_flags
1949  *   Holds the actions detected until now.
1950  * @param[in] actions
1951  *   Pointer to the list of actions remaining in the flow rule.
1952  * @param[out] error
1953  *   Pointer to error structure.
1954  *
1955  * @return
1956  *   0 on success, a negative errno value otherwise and rte_errno is set.
1957  */
1958 static int
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960                                      uint64_t action_flags,
1961                                      const struct rte_flow_action actions[],
1962                                      struct rte_flow_error *error)
1963 {
1964         const struct rte_flow_action *action = actions;
1965         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1966
1967         if (conf->vlan_vid > RTE_BE16(0xFFE))
1968                 return rte_flow_error_set(error, EINVAL,
1969                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1970                                           "VLAN VID value is too big");
1971         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973                 return rte_flow_error_set(error, ENOTSUP,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "set VLAN VID action must follow push"
1976                                           " VLAN action or match on VLAN item");
1977         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978                 return rte_flow_error_set(error, ENOTSUP,
1979                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1980                                           "Multiple VLAN VID modifications are "
1981                                           "not supported");
1982         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1985                                           "wrong action order, port_id should "
1986                                           "be after set VLAN VID");
1987         return 0;
1988 }
1989
1990 /*
1991  * Validate the FLAG action.
1992  *
1993  * @param[in] dev
1994  *   Pointer to the rte_eth_dev structure.
1995  * @param[in] action_flags
1996  *   Holds the actions detected until now.
1997  * @param[in] attr
1998  *   Pointer to flow attributes
1999  * @param[out] error
2000  *   Pointer to error structure.
2001  *
2002  * @return
2003  *   0 on success, a negative errno value otherwise and rte_errno is set.
2004  */
2005 static int
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007                              uint64_t action_flags,
2008                              const struct rte_flow_attr *attr,
2009                              struct rte_flow_error *error)
2010 {
2011         struct mlx5_priv *priv = dev->data->dev_private;
2012         struct mlx5_dev_config *config = &priv->config;
2013         int ret;
2014
2015         /* Fall back if no extended metadata register support. */
2016         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017                 return mlx5_flow_validate_action_flag(action_flags, attr,
2018                                                       error);
2019         /* Extensive metadata mode requires registers. */
2020         if (!mlx5_flow_ext_mreg_supported(dev))
2021                 return rte_flow_error_set(error, ENOTSUP,
2022                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023                                           "no metadata registers "
2024                                           "to support flag action");
2025         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026                 return rte_flow_error_set(error, ENOTSUP,
2027                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028                                           "extended metadata register"
2029                                           " isn't available");
2030         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2031         if (ret < 0)
2032                 return ret;
2033         MLX5_ASSERT(ret > 0);
2034         if (action_flags & MLX5_FLOW_ACTION_MARK)
2035                 return rte_flow_error_set(error, EINVAL,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037                                           "can't mark and flag in same flow");
2038         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039                 return rte_flow_error_set(error, EINVAL,
2040                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2041                                           "can't have 2 flag"
2042                                           " actions in same flow");
2043         return 0;
2044 }
2045
2046 /**
2047  * Validate MARK action.
2048  *
2049  * @param[in] dev
2050  *   Pointer to the rte_eth_dev structure.
2051  * @param[in] action
2052  *   Pointer to action.
2053  * @param[in] action_flags
2054  *   Holds the actions detected until now.
2055  * @param[in] attr
2056  *   Pointer to flow attributes
2057  * @param[out] error
2058  *   Pointer to error structure.
2059  *
2060  * @return
2061  *   0 on success, a negative errno value otherwise and rte_errno is set.
2062  */
2063 static int
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065                              const struct rte_flow_action *action,
2066                              uint64_t action_flags,
2067                              const struct rte_flow_attr *attr,
2068                              struct rte_flow_error *error)
2069 {
2070         struct mlx5_priv *priv = dev->data->dev_private;
2071         struct mlx5_dev_config *config = &priv->config;
2072         const struct rte_flow_action_mark *mark = action->conf;
2073         int ret;
2074
2075         /* Fall back if no extended metadata register support. */
2076         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077                 return mlx5_flow_validate_action_mark(action, action_flags,
2078                                                       attr, error);
2079         /* Extensive metadata mode requires registers. */
2080         if (!mlx5_flow_ext_mreg_supported(dev))
2081                 return rte_flow_error_set(error, ENOTSUP,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083                                           "no metadata registers "
2084                                           "to support mark action");
2085         if (!priv->sh->dv_mark_mask)
2086                 return rte_flow_error_set(error, ENOTSUP,
2087                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088                                           "extended metadata register"
2089                                           " isn't available");
2090         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2091         if (ret < 0)
2092                 return ret;
2093         MLX5_ASSERT(ret > 0);
2094         if (!mark)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2097                                           "configuration cannot be null");
2098         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099                 return rte_flow_error_set(error, EINVAL,
2100                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2101                                           &mark->id,
2102                                           "mark id exceeds the limit");
2103         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104                 return rte_flow_error_set(error, EINVAL,
2105                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106                                           "can't flag and mark in same flow");
2107         if (action_flags & MLX5_FLOW_ACTION_MARK)
2108                 return rte_flow_error_set(error, EINVAL,
2109                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110                                           "can't have 2 mark actions in same"
2111                                           " flow");
2112         return 0;
2113 }
2114
2115 /**
2116  * Validate SET_META action.
2117  *
2118  * @param[in] dev
2119  *   Pointer to the rte_eth_dev structure.
2120  * @param[in] action
2121  *   Pointer to the action structure.
2122  * @param[in] action_flags
2123  *   Holds the actions detected until now.
2124  * @param[in] attr
2125  *   Pointer to flow attributes
2126  * @param[out] error
2127  *   Pointer to error structure.
2128  *
2129  * @return
2130  *   0 on success, a negative errno value otherwise and rte_errno is set.
2131  */
2132 static int
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134                                  const struct rte_flow_action *action,
2135                                  uint64_t action_flags __rte_unused,
2136                                  const struct rte_flow_attr *attr,
2137                                  struct rte_flow_error *error)
2138 {
2139         const struct rte_flow_action_set_meta *conf;
2140         uint32_t nic_mask = UINT32_MAX;
2141         int reg;
2142
2143         if (!mlx5_flow_ext_mreg_supported(dev))
2144                 return rte_flow_error_set(error, ENOTSUP,
2145                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2146                                           "extended metadata register"
2147                                           " isn't supported");
2148         reg = flow_dv_get_metadata_reg(dev, attr, error);
2149         if (reg < 0)
2150                 return reg;
2151         if (reg != REG_A && reg != REG_B) {
2152                 struct mlx5_priv *priv = dev->data->dev_private;
2153
2154                 nic_mask = priv->sh->dv_meta_mask;
2155         }
2156         if (!(action->conf))
2157                 return rte_flow_error_set(error, EINVAL,
2158                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2159                                           "configuration cannot be null");
2160         conf = (const struct rte_flow_action_set_meta *)action->conf;
2161         if (!conf->mask)
2162                 return rte_flow_error_set(error, EINVAL,
2163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2164                                           "zero mask doesn't have any effect");
2165         if (conf->mask & ~nic_mask)
2166                 return rte_flow_error_set(error, EINVAL,
2167                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2168                                           "meta data must be within reg C0");
2169         return 0;
2170 }
2171
2172 /**
2173  * Validate SET_TAG action.
2174  *
2175  * @param[in] dev
2176  *   Pointer to the rte_eth_dev structure.
2177  * @param[in] action
2178  *   Pointer to the action structure.
2179  * @param[in] action_flags
2180  *   Holds the actions detected until now.
2181  * @param[in] attr
2182  *   Pointer to flow attributes
2183  * @param[out] error
2184  *   Pointer to error structure.
2185  *
2186  * @return
2187  *   0 on success, a negative errno value otherwise and rte_errno is set.
2188  */
2189 static int
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191                                 const struct rte_flow_action *action,
2192                                 uint64_t action_flags,
2193                                 const struct rte_flow_attr *attr,
2194                                 struct rte_flow_error *error)
2195 {
2196         const struct rte_flow_action_set_tag *conf;
2197         const uint64_t terminal_action_flags =
2198                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199                 MLX5_FLOW_ACTION_RSS;
2200         int ret;
2201
2202         if (!mlx5_flow_ext_mreg_supported(dev))
2203                 return rte_flow_error_set(error, ENOTSUP,
2204                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2205                                           "extensive metadata register"
2206                                           " isn't supported");
2207         if (!(action->conf))
2208                 return rte_flow_error_set(error, EINVAL,
2209                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2210                                           "configuration cannot be null");
2211         conf = (const struct rte_flow_action_set_tag *)action->conf;
2212         if (!conf->mask)
2213                 return rte_flow_error_set(error, EINVAL,
2214                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2215                                           "zero mask doesn't have any effect");
2216         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2217         if (ret < 0)
2218                 return ret;
2219         if (!attr->transfer && attr->ingress &&
2220             (action_flags & terminal_action_flags))
2221                 return rte_flow_error_set(error, EINVAL,
2222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2223                                           "set_tag has no effect"
2224                                           " with terminal actions");
2225         return 0;
2226 }
2227
2228 /**
2229  * Validate count action.
2230  *
2231  * @param[in] dev
2232  *   Pointer to rte_eth_dev structure.
2233  * @param[out] error
2234  *   Pointer to error structure.
2235  *
2236  * @return
2237  *   0 on success, a negative errno value otherwise and rte_errno is set.
2238  */
2239 static int
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241                               struct rte_flow_error *error)
2242 {
2243         struct mlx5_priv *priv = dev->data->dev_private;
2244
2245         if (!priv->config.devx)
2246                 goto notsup_err;
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2248         return 0;
2249 #endif
2250 notsup_err:
2251         return rte_flow_error_set
2252                       (error, ENOTSUP,
2253                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2254                        NULL,
2255                        "count action not supported");
2256 }
2257
2258 /**
2259  * Validate the L2 encap action.
2260  *
2261  * @param[in] dev
2262  *   Pointer to the rte_eth_dev structure.
2263  * @param[in] action_flags
2264  *   Holds the actions detected until now.
2265  * @param[in] action
2266  *   Pointer to the action structure.
2267  * @param[in] attr
2268  *   Pointer to flow attributes.
2269  * @param[out] error
2270  *   Pointer to error structure.
2271  *
2272  * @return
2273  *   0 on success, a negative errno value otherwise and rte_errno is set.
2274  */
2275 static int
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277                                  uint64_t action_flags,
2278                                  const struct rte_flow_action *action,
2279                                  const struct rte_flow_attr *attr,
2280                                  struct rte_flow_error *error)
2281 {
2282         const struct mlx5_priv *priv = dev->data->dev_private;
2283
2284         if (!(action->conf))
2285                 return rte_flow_error_set(error, EINVAL,
2286                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2287                                           "configuration cannot be null");
2288         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289                 return rte_flow_error_set(error, EINVAL,
2290                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291                                           "can only have a single encap action "
2292                                           "in a flow");
2293         if (!attr->transfer && priv->representor)
2294                 return rte_flow_error_set(error, ENOTSUP,
2295                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296                                           "encap action for VF representor "
2297                                           "not supported on NIC table");
2298         return 0;
2299 }
2300
2301 /**
2302  * Validate a decap action.
2303  *
2304  * @param[in] dev
2305  *   Pointer to the rte_eth_dev structure.
2306  * @param[in] action_flags
2307  *   Holds the actions detected until now.
2308  * @param[in] attr
2309  *   Pointer to flow attributes
2310  * @param[out] error
2311  *   Pointer to error structure.
2312  *
2313  * @return
2314  *   0 on success, a negative errno value otherwise and rte_errno is set.
2315  */
2316 static int
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318                               uint64_t action_flags,
2319                               const struct rte_flow_attr *attr,
2320                               struct rte_flow_error *error)
2321 {
2322         const struct mlx5_priv *priv = dev->data->dev_private;
2323
2324         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325                 return rte_flow_error_set(error, ENOTSUP,
2326                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2327                                           action_flags &
2328                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2329                                           "have a single decap action" : "decap "
2330                                           "after encap is not supported");
2331         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332                 return rte_flow_error_set(error, EINVAL,
2333                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334                                           "can't have decap action after"
2335                                           " modify action");
2336         if (attr->egress)
2337                 return rte_flow_error_set(error, ENOTSUP,
2338                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2339                                           NULL,
2340                                           "decap action not supported for "
2341                                           "egress");
2342         if (!attr->transfer && priv->representor)
2343                 return rte_flow_error_set(error, ENOTSUP,
2344                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345                                           "decap action for VF representor "
2346                                           "not supported on NIC table");
2347         return 0;
2348 }
2349
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2351
2352 /**
2353  * Validate the raw encap and decap actions.
2354  *
2355  * @param[in] dev
2356  *   Pointer to the rte_eth_dev structure.
2357  * @param[in] decap
2358  *   Pointer to the decap action.
2359  * @param[in] encap
2360  *   Pointer to the encap action.
2361  * @param[in] attr
2362  *   Pointer to flow attributes
2363  * @param[in/out] action_flags
2364  *   Holds the actions detected until now.
2365  * @param[out] actions_n
2366  *   pointer to the number of actions counter.
2367  * @param[out] error
2368  *   Pointer to error structure.
2369  *
2370  * @return
2371  *   0 on success, a negative errno value otherwise and rte_errno is set.
2372  */
2373 static int
2374 flow_dv_validate_action_raw_encap_decap
2375         (struct rte_eth_dev *dev,
2376          const struct rte_flow_action_raw_decap *decap,
2377          const struct rte_flow_action_raw_encap *encap,
2378          const struct rte_flow_attr *attr, uint64_t *action_flags,
2379          int *actions_n, struct rte_flow_error *error)
2380 {
2381         const struct mlx5_priv *priv = dev->data->dev_private;
2382         int ret;
2383
2384         if (encap && (!encap->size || !encap->data))
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "raw encap data cannot be empty");
2388         if (decap && encap) {
2389                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2391                         /* L3 encap. */
2392                         decap = NULL;
2393                 else if (encap->size <=
2394                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2395                            decap->size >
2396                            MLX5_ENCAPSULATION_DECISION_SIZE)
2397                         /* L3 decap. */
2398                         encap = NULL;
2399                 else if (encap->size >
2400                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2401                            decap->size >
2402                            MLX5_ENCAPSULATION_DECISION_SIZE)
2403                         /* 2 L2 actions: encap and decap. */
2404                         ;
2405                 else
2406                         return rte_flow_error_set(error,
2407                                 ENOTSUP,
2408                                 RTE_FLOW_ERROR_TYPE_ACTION,
2409                                 NULL, "unsupported too small "
2410                                 "raw decap and too small raw "
2411                                 "encap combination");
2412         }
2413         if (decap) {
2414                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2415                                                     error);
2416                 if (ret < 0)
2417                         return ret;
2418                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2419                 ++(*actions_n);
2420         }
2421         if (encap) {
2422                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423                         return rte_flow_error_set(error, ENOTSUP,
2424                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2425                                                   NULL,
2426                                                   "small raw encap size");
2427                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428                         return rte_flow_error_set(error, EINVAL,
2429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2430                                                   NULL,
2431                                                   "more than one encap action");
2432                 if (!attr->transfer && priv->representor)
2433                         return rte_flow_error_set
2434                                         (error, ENOTSUP,
2435                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436                                          "encap action for VF representor "
2437                                          "not supported on NIC table");
2438                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2439                 ++(*actions_n);
2440         }
2441         return 0;
2442 }
2443
2444 /**
2445  * Find existing encap/decap resource or create and register a new one.
2446  *
2447  * @param[in, out] dev
2448  *   Pointer to rte_eth_dev structure.
2449  * @param[in, out] resource
2450  *   Pointer to encap/decap resource.
2451  * @parm[in, out] dev_flow
2452  *   Pointer to the dev_flow.
2453  * @param[out] error
2454  *   pointer to error structure.
2455  *
2456  * @return
2457  *   0 on success otherwise -errno and errno is set.
2458  */
2459 static int
2460 flow_dv_encap_decap_resource_register
2461                         (struct rte_eth_dev *dev,
2462                          struct mlx5_flow_dv_encap_decap_resource *resource,
2463                          struct mlx5_flow *dev_flow,
2464                          struct rte_flow_error *error)
2465 {
2466         struct mlx5_priv *priv = dev->data->dev_private;
2467         struct mlx5_ibv_shared *sh = priv->sh;
2468         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469         struct mlx5dv_dr_domain *domain;
2470         uint32_t idx = 0;
2471
2472         resource->flags = dev_flow->dv.group ? 0 : 1;
2473         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2474                 domain = sh->fdb_domain;
2475         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2476                 domain = sh->rx_domain;
2477         else
2478                 domain = sh->tx_domain;
2479         /* Lookup a matching resource from cache. */
2480         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2481                       cache_resource, next) {
2482                 if (resource->reformat_type == cache_resource->reformat_type &&
2483                     resource->ft_type == cache_resource->ft_type &&
2484                     resource->flags == cache_resource->flags &&
2485                     resource->size == cache_resource->size &&
2486                     !memcmp((const void *)resource->buf,
2487                             (const void *)cache_resource->buf,
2488                             resource->size)) {
2489                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2490                                 (void *)cache_resource,
2491                                 rte_atomic32_read(&cache_resource->refcnt));
2492                         rte_atomic32_inc(&cache_resource->refcnt);
2493                         dev_flow->handle->dvh.encap_decap = idx;
2494                         dev_flow->dv.encap_decap = cache_resource;
2495                         return 0;
2496                 }
2497         }
2498         /* Register new encap/decap resource. */
2499         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2500                                        &dev_flow->handle->dvh.encap_decap);
2501         if (!cache_resource)
2502                 return rte_flow_error_set(error, ENOMEM,
2503                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2504                                           "cannot allocate resource memory");
2505         *cache_resource = *resource;
2506         cache_resource->verbs_action =
2507                 mlx5_glue->dv_create_flow_action_packet_reformat
2508                         (sh->ctx, cache_resource->reformat_type,
2509                          cache_resource->ft_type, domain, cache_resource->flags,
2510                          cache_resource->size,
2511                          (cache_resource->size ? cache_resource->buf : NULL));
2512         if (!cache_resource->verbs_action) {
2513                 rte_free(cache_resource);
2514                 return rte_flow_error_set(error, ENOMEM,
2515                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2516                                           NULL, "cannot create action");
2517         }
2518         rte_atomic32_init(&cache_resource->refcnt);
2519         rte_atomic32_inc(&cache_resource->refcnt);
2520         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2521                      dev_flow->handle->dvh.encap_decap, cache_resource, next);
2522         dev_flow->dv.encap_decap = cache_resource;
2523         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2524                 (void *)cache_resource,
2525                 rte_atomic32_read(&cache_resource->refcnt));
2526         return 0;
2527 }
2528
2529 /**
2530  * Find existing table jump resource or create and register a new one.
2531  *
2532  * @param[in, out] dev
2533  *   Pointer to rte_eth_dev structure.
2534  * @param[in, out] tbl
2535  *   Pointer to flow table resource.
2536  * @parm[in, out] dev_flow
2537  *   Pointer to the dev_flow.
2538  * @param[out] error
2539  *   pointer to error structure.
2540  *
2541  * @return
2542  *   0 on success otherwise -errno and errno is set.
2543  */
2544 static int
2545 flow_dv_jump_tbl_resource_register
2546                         (struct rte_eth_dev *dev __rte_unused,
2547                          struct mlx5_flow_tbl_resource *tbl,
2548                          struct mlx5_flow *dev_flow,
2549                          struct rte_flow_error *error)
2550 {
2551         struct mlx5_flow_tbl_data_entry *tbl_data =
2552                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2553         int cnt;
2554
2555         MLX5_ASSERT(tbl);
2556         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2557         if (!cnt) {
2558                 tbl_data->jump.action =
2559                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2560                         (tbl->obj);
2561                 if (!tbl_data->jump.action)
2562                         return rte_flow_error_set(error, ENOMEM,
2563                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564                                         NULL, "cannot create jump action");
2565                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2566                         (void *)&tbl_data->jump, cnt);
2567         } else {
2568                 /* old jump should not make the table ref++. */
2569                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2570                 MLX5_ASSERT(tbl_data->jump.action);
2571                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2572                         (void *)&tbl_data->jump, cnt);
2573         }
2574         rte_atomic32_inc(&tbl_data->jump.refcnt);
2575         dev_flow->handle->dvh.jump = &tbl_data->jump;
2576         return 0;
2577 }
2578
2579 /**
2580  * Find existing table port ID resource or create and register a new one.
2581  *
2582  * @param[in, out] dev
2583  *   Pointer to rte_eth_dev structure.
2584  * @param[in, out] resource
2585  *   Pointer to port ID action resource.
2586  * @parm[in, out] dev_flow
2587  *   Pointer to the dev_flow.
2588  * @param[out] error
2589  *   pointer to error structure.
2590  *
2591  * @return
2592  *   0 on success otherwise -errno and errno is set.
2593  */
2594 static int
2595 flow_dv_port_id_action_resource_register
2596                         (struct rte_eth_dev *dev,
2597                          struct mlx5_flow_dv_port_id_action_resource *resource,
2598                          struct mlx5_flow *dev_flow,
2599                          struct rte_flow_error *error)
2600 {
2601         struct mlx5_priv *priv = dev->data->dev_private;
2602         struct mlx5_ibv_shared *sh = priv->sh;
2603         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2604
2605         /* Lookup a matching resource from cache. */
2606         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2607                 if (resource->port_id == cache_resource->port_id) {
2608                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2609                                 "refcnt %d++",
2610                                 (void *)cache_resource,
2611                                 rte_atomic32_read(&cache_resource->refcnt));
2612                         rte_atomic32_inc(&cache_resource->refcnt);
2613                         dev_flow->handle->dvh.port_id_action = cache_resource;
2614                         return 0;
2615                 }
2616         }
2617         /* Register new port id action resource. */
2618         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2619         if (!cache_resource)
2620                 return rte_flow_error_set(error, ENOMEM,
2621                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2622                                           "cannot allocate resource memory");
2623         *cache_resource = *resource;
2624         /*
2625          * Depending on rdma_core version the glue routine calls
2626          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2627          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2628          */
2629         cache_resource->action =
2630                 mlx5_glue->dr_create_flow_action_dest_port
2631                         (priv->sh->fdb_domain, resource->port_id);
2632         if (!cache_resource->action) {
2633                 rte_free(cache_resource);
2634                 return rte_flow_error_set(error, ENOMEM,
2635                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2636                                           NULL, "cannot create action");
2637         }
2638         rte_atomic32_init(&cache_resource->refcnt);
2639         rte_atomic32_inc(&cache_resource->refcnt);
2640         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2641         dev_flow->handle->dvh.port_id_action = cache_resource;
2642         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2643                 (void *)cache_resource,
2644                 rte_atomic32_read(&cache_resource->refcnt));
2645         return 0;
2646 }
2647
2648 /**
2649  * Find existing push vlan resource or create and register a new one.
2650  *
2651  * @param [in, out] dev
2652  *   Pointer to rte_eth_dev structure.
2653  * @param[in, out] resource
2654  *   Pointer to port ID action resource.
2655  * @parm[in, out] dev_flow
2656  *   Pointer to the dev_flow.
2657  * @param[out] error
2658  *   pointer to error structure.
2659  *
2660  * @return
2661  *   0 on success otherwise -errno and errno is set.
2662  */
2663 static int
2664 flow_dv_push_vlan_action_resource_register
2665                        (struct rte_eth_dev *dev,
2666                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2667                         struct mlx5_flow *dev_flow,
2668                         struct rte_flow_error *error)
2669 {
2670         struct mlx5_priv *priv = dev->data->dev_private;
2671         struct mlx5_ibv_shared *sh = priv->sh;
2672         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2673         struct mlx5dv_dr_domain *domain;
2674         uint32_t idx = 0;
2675
2676         /* Lookup a matching resource from cache. */
2677         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2678                       sh->push_vlan_action_list, idx, cache_resource, next) {
2679                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2680                     resource->ft_type == cache_resource->ft_type) {
2681                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2682                                 "refcnt %d++",
2683                                 (void *)cache_resource,
2684                                 rte_atomic32_read(&cache_resource->refcnt));
2685                         rte_atomic32_inc(&cache_resource->refcnt);
2686                         dev_flow->handle->dvh.push_vlan_res = idx;
2687                         dev_flow->dv.push_vlan_res = cache_resource;
2688                         return 0;
2689                 }
2690         }
2691         /* Register new push_vlan action resource. */
2692         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2693                                        &dev_flow->handle->dvh.push_vlan_res);
2694         if (!cache_resource)
2695                 return rte_flow_error_set(error, ENOMEM,
2696                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2697                                           "cannot allocate resource memory");
2698         *cache_resource = *resource;
2699         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2700                 domain = sh->fdb_domain;
2701         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2702                 domain = sh->rx_domain;
2703         else
2704                 domain = sh->tx_domain;
2705         cache_resource->action =
2706                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2707                                                            resource->vlan_tag);
2708         if (!cache_resource->action) {
2709                 rte_free(cache_resource);
2710                 return rte_flow_error_set(error, ENOMEM,
2711                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2712                                           NULL, "cannot create action");
2713         }
2714         rte_atomic32_init(&cache_resource->refcnt);
2715         rte_atomic32_inc(&cache_resource->refcnt);
2716         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2717                      &sh->push_vlan_action_list,
2718                      dev_flow->handle->dvh.push_vlan_res,
2719                      cache_resource, next);
2720         dev_flow->dv.push_vlan_res = cache_resource;
2721         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2722                 (void *)cache_resource,
2723                 rte_atomic32_read(&cache_resource->refcnt));
2724         return 0;
2725 }
2726 /**
2727  * Get the size of specific rte_flow_item_type
2728  *
2729  * @param[in] item_type
2730  *   Tested rte_flow_item_type.
2731  *
2732  * @return
2733  *   sizeof struct item_type, 0 if void or irrelevant.
2734  */
2735 static size_t
2736 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2737 {
2738         size_t retval;
2739
2740         switch (item_type) {
2741         case RTE_FLOW_ITEM_TYPE_ETH:
2742                 retval = sizeof(struct rte_flow_item_eth);
2743                 break;
2744         case RTE_FLOW_ITEM_TYPE_VLAN:
2745                 retval = sizeof(struct rte_flow_item_vlan);
2746                 break;
2747         case RTE_FLOW_ITEM_TYPE_IPV4:
2748                 retval = sizeof(struct rte_flow_item_ipv4);
2749                 break;
2750         case RTE_FLOW_ITEM_TYPE_IPV6:
2751                 retval = sizeof(struct rte_flow_item_ipv6);
2752                 break;
2753         case RTE_FLOW_ITEM_TYPE_UDP:
2754                 retval = sizeof(struct rte_flow_item_udp);
2755                 break;
2756         case RTE_FLOW_ITEM_TYPE_TCP:
2757                 retval = sizeof(struct rte_flow_item_tcp);
2758                 break;
2759         case RTE_FLOW_ITEM_TYPE_VXLAN:
2760                 retval = sizeof(struct rte_flow_item_vxlan);
2761                 break;
2762         case RTE_FLOW_ITEM_TYPE_GRE:
2763                 retval = sizeof(struct rte_flow_item_gre);
2764                 break;
2765         case RTE_FLOW_ITEM_TYPE_NVGRE:
2766                 retval = sizeof(struct rte_flow_item_nvgre);
2767                 break;
2768         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2769                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2770                 break;
2771         case RTE_FLOW_ITEM_TYPE_MPLS:
2772                 retval = sizeof(struct rte_flow_item_mpls);
2773                 break;
2774         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2775         default:
2776                 retval = 0;
2777                 break;
2778         }
2779         return retval;
2780 }
2781
2782 #define MLX5_ENCAP_IPV4_VERSION         0x40
2783 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2784 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2785 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2786 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2787 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2788 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2789
2790 /**
2791  * Convert the encap action data from list of rte_flow_item to raw buffer
2792  *
2793  * @param[in] items
2794  *   Pointer to rte_flow_item objects list.
2795  * @param[out] buf
2796  *   Pointer to the output buffer.
2797  * @param[out] size
2798  *   Pointer to the output buffer size.
2799  * @param[out] error
2800  *   Pointer to the error structure.
2801  *
2802  * @return
2803  *   0 on success, a negative errno value otherwise and rte_errno is set.
2804  */
2805 static int
2806 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2807                            size_t *size, struct rte_flow_error *error)
2808 {
2809         struct rte_ether_hdr *eth = NULL;
2810         struct rte_vlan_hdr *vlan = NULL;
2811         struct rte_ipv4_hdr *ipv4 = NULL;
2812         struct rte_ipv6_hdr *ipv6 = NULL;
2813         struct rte_udp_hdr *udp = NULL;
2814         struct rte_vxlan_hdr *vxlan = NULL;
2815         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2816         struct rte_gre_hdr *gre = NULL;
2817         size_t len;
2818         size_t temp_size = 0;
2819
2820         if (!items)
2821                 return rte_flow_error_set(error, EINVAL,
2822                                           RTE_FLOW_ERROR_TYPE_ACTION,
2823                                           NULL, "invalid empty data");
2824         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2825                 len = flow_dv_get_item_len(items->type);
2826                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2827                         return rte_flow_error_set(error, EINVAL,
2828                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2829                                                   (void *)items->type,
2830                                                   "items total size is too big"
2831                                                   " for encap action");
2832                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2833                 switch (items->type) {
2834                 case RTE_FLOW_ITEM_TYPE_ETH:
2835                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2836                         break;
2837                 case RTE_FLOW_ITEM_TYPE_VLAN:
2838                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2839                         if (!eth)
2840                                 return rte_flow_error_set(error, EINVAL,
2841                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2842                                                 (void *)items->type,
2843                                                 "eth header not found");
2844                         if (!eth->ether_type)
2845                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2846                         break;
2847                 case RTE_FLOW_ITEM_TYPE_IPV4:
2848                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2849                         if (!vlan && !eth)
2850                                 return rte_flow_error_set(error, EINVAL,
2851                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2852                                                 (void *)items->type,
2853                                                 "neither eth nor vlan"
2854                                                 " header found");
2855                         if (vlan && !vlan->eth_proto)
2856                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2857                         else if (eth && !eth->ether_type)
2858                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2859                         if (!ipv4->version_ihl)
2860                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2861                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2862                         if (!ipv4->time_to_live)
2863                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2864                         break;
2865                 case RTE_FLOW_ITEM_TYPE_IPV6:
2866                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2867                         if (!vlan && !eth)
2868                                 return rte_flow_error_set(error, EINVAL,
2869                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2870                                                 (void *)items->type,
2871                                                 "neither eth nor vlan"
2872                                                 " header found");
2873                         if (vlan && !vlan->eth_proto)
2874                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2875                         else if (eth && !eth->ether_type)
2876                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2877                         if (!ipv6->vtc_flow)
2878                                 ipv6->vtc_flow =
2879                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2880                         if (!ipv6->hop_limits)
2881                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2882                         break;
2883                 case RTE_FLOW_ITEM_TYPE_UDP:
2884                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2885                         if (!ipv4 && !ipv6)
2886                                 return rte_flow_error_set(error, EINVAL,
2887                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2888                                                 (void *)items->type,
2889                                                 "ip header not found");
2890                         if (ipv4 && !ipv4->next_proto_id)
2891                                 ipv4->next_proto_id = IPPROTO_UDP;
2892                         else if (ipv6 && !ipv6->proto)
2893                                 ipv6->proto = IPPROTO_UDP;
2894                         break;
2895                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2896                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2897                         if (!udp)
2898                                 return rte_flow_error_set(error, EINVAL,
2899                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2900                                                 (void *)items->type,
2901                                                 "udp header not found");
2902                         if (!udp->dst_port)
2903                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2904                         if (!vxlan->vx_flags)
2905                                 vxlan->vx_flags =
2906                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2907                         break;
2908                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2909                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2910                         if (!udp)
2911                                 return rte_flow_error_set(error, EINVAL,
2912                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2913                                                 (void *)items->type,
2914                                                 "udp header not found");
2915                         if (!vxlan_gpe->proto)
2916                                 return rte_flow_error_set(error, EINVAL,
2917                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2918                                                 (void *)items->type,
2919                                                 "next protocol not found");
2920                         if (!udp->dst_port)
2921                                 udp->dst_port =
2922                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2923                         if (!vxlan_gpe->vx_flags)
2924                                 vxlan_gpe->vx_flags =
2925                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2926                         break;
2927                 case RTE_FLOW_ITEM_TYPE_GRE:
2928                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2929                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2930                         if (!gre->proto)
2931                                 return rte_flow_error_set(error, EINVAL,
2932                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2933                                                 (void *)items->type,
2934                                                 "next protocol not found");
2935                         if (!ipv4 && !ipv6)
2936                                 return rte_flow_error_set(error, EINVAL,
2937                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2938                                                 (void *)items->type,
2939                                                 "ip header not found");
2940                         if (ipv4 && !ipv4->next_proto_id)
2941                                 ipv4->next_proto_id = IPPROTO_GRE;
2942                         else if (ipv6 && !ipv6->proto)
2943                                 ipv6->proto = IPPROTO_GRE;
2944                         break;
2945                 case RTE_FLOW_ITEM_TYPE_VOID:
2946                         break;
2947                 default:
2948                         return rte_flow_error_set(error, EINVAL,
2949                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2950                                                   (void *)items->type,
2951                                                   "unsupported item type");
2952                         break;
2953                 }
2954                 temp_size += len;
2955         }
2956         *size = temp_size;
2957         return 0;
2958 }
2959
2960 static int
2961 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2962 {
2963         struct rte_ether_hdr *eth = NULL;
2964         struct rte_vlan_hdr *vlan = NULL;
2965         struct rte_ipv6_hdr *ipv6 = NULL;
2966         struct rte_udp_hdr *udp = NULL;
2967         char *next_hdr;
2968         uint16_t proto;
2969
2970         eth = (struct rte_ether_hdr *)data;
2971         next_hdr = (char *)(eth + 1);
2972         proto = RTE_BE16(eth->ether_type);
2973
2974         /* VLAN skipping */
2975         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2976                 vlan = (struct rte_vlan_hdr *)next_hdr;
2977                 proto = RTE_BE16(vlan->eth_proto);
2978                 next_hdr += sizeof(struct rte_vlan_hdr);
2979         }
2980
2981         /* HW calculates IPv4 csum. no need to proceed */
2982         if (proto == RTE_ETHER_TYPE_IPV4)
2983                 return 0;
2984
2985         /* non IPv4/IPv6 header. not supported */
2986         if (proto != RTE_ETHER_TYPE_IPV6) {
2987                 return rte_flow_error_set(error, ENOTSUP,
2988                                           RTE_FLOW_ERROR_TYPE_ACTION,
2989                                           NULL, "Cannot offload non IPv4/IPv6");
2990         }
2991
2992         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2993
2994         /* ignore non UDP */
2995         if (ipv6->proto != IPPROTO_UDP)
2996                 return 0;
2997
2998         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2999         udp->dgram_cksum = 0;
3000
3001         return 0;
3002 }
3003
3004 /**
3005  * Convert L2 encap action to DV specification.
3006  *
3007  * @param[in] dev
3008  *   Pointer to rte_eth_dev structure.
3009  * @param[in] action
3010  *   Pointer to action structure.
3011  * @param[in, out] dev_flow
3012  *   Pointer to the mlx5_flow.
3013  * @param[in] transfer
3014  *   Mark if the flow is E-Switch flow.
3015  * @param[out] error
3016  *   Pointer to the error structure.
3017  *
3018  * @return
3019  *   0 on success, a negative errno value otherwise and rte_errno is set.
3020  */
3021 static int
3022 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3023                                const struct rte_flow_action *action,
3024                                struct mlx5_flow *dev_flow,
3025                                uint8_t transfer,
3026                                struct rte_flow_error *error)
3027 {
3028         const struct rte_flow_item *encap_data;
3029         const struct rte_flow_action_raw_encap *raw_encap_data;
3030         struct mlx5_flow_dv_encap_decap_resource res = {
3031                 .reformat_type =
3032                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3033                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3034                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3035         };
3036
3037         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3038                 raw_encap_data =
3039                         (const struct rte_flow_action_raw_encap *)action->conf;
3040                 res.size = raw_encap_data->size;
3041                 memcpy(res.buf, raw_encap_data->data, res.size);
3042         } else {
3043                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3044                         encap_data =
3045                                 ((const struct rte_flow_action_vxlan_encap *)
3046                                                 action->conf)->definition;
3047                 else
3048                         encap_data =
3049                                 ((const struct rte_flow_action_nvgre_encap *)
3050                                                 action->conf)->definition;
3051                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3052                                                &res.size, error))
3053                         return -rte_errno;
3054         }
3055         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3056                 return -rte_errno;
3057         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3058                 return rte_flow_error_set(error, EINVAL,
3059                                           RTE_FLOW_ERROR_TYPE_ACTION,
3060                                           NULL, "can't create L2 encap action");
3061         return 0;
3062 }
3063
3064 /**
3065  * Convert L2 decap action to DV specification.
3066  *
3067  * @param[in] dev
3068  *   Pointer to rte_eth_dev structure.
3069  * @param[in, out] dev_flow
3070  *   Pointer to the mlx5_flow.
3071  * @param[in] transfer
3072  *   Mark if the flow is E-Switch flow.
3073  * @param[out] error
3074  *   Pointer to the error structure.
3075  *
3076  * @return
3077  *   0 on success, a negative errno value otherwise and rte_errno is set.
3078  */
3079 static int
3080 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3081                                struct mlx5_flow *dev_flow,
3082                                uint8_t transfer,
3083                                struct rte_flow_error *error)
3084 {
3085         struct mlx5_flow_dv_encap_decap_resource res = {
3086                 .size = 0,
3087                 .reformat_type =
3088                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3089                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3090                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3091         };
3092
3093         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3094                 return rte_flow_error_set(error, EINVAL,
3095                                           RTE_FLOW_ERROR_TYPE_ACTION,
3096                                           NULL, "can't create L2 decap action");
3097         return 0;
3098 }
3099
3100 /**
3101  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3102  *
3103  * @param[in] dev
3104  *   Pointer to rte_eth_dev structure.
3105  * @param[in] action
3106  *   Pointer to action structure.
3107  * @param[in, out] dev_flow
3108  *   Pointer to the mlx5_flow.
3109  * @param[in] attr
3110  *   Pointer to the flow attributes.
3111  * @param[out] error
3112  *   Pointer to the error structure.
3113  *
3114  * @return
3115  *   0 on success, a negative errno value otherwise and rte_errno is set.
3116  */
3117 static int
3118 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3119                                 const struct rte_flow_action *action,
3120                                 struct mlx5_flow *dev_flow,
3121                                 const struct rte_flow_attr *attr,
3122                                 struct rte_flow_error *error)
3123 {
3124         const struct rte_flow_action_raw_encap *encap_data;
3125         struct mlx5_flow_dv_encap_decap_resource res;
3126
3127         memset(&res, 0, sizeof(res));
3128         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3129         res.size = encap_data->size;
3130         memcpy(res.buf, encap_data->data, res.size);
3131         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3132                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3133                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3134         if (attr->transfer)
3135                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3136         else
3137                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3138                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3139         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3140                 return rte_flow_error_set(error, EINVAL,
3141                                           RTE_FLOW_ERROR_TYPE_ACTION,
3142                                           NULL, "can't create encap action");
3143         return 0;
3144 }
3145
3146 /**
3147  * Create action push VLAN.
3148  *
3149  * @param[in] dev
3150  *   Pointer to rte_eth_dev structure.
3151  * @param[in] attr
3152  *   Pointer to the flow attributes.
3153  * @param[in] vlan
3154  *   Pointer to the vlan to push to the Ethernet header.
3155  * @param[in, out] dev_flow
3156  *   Pointer to the mlx5_flow.
3157  * @param[out] error
3158  *   Pointer to the error structure.
3159  *
3160  * @return
3161  *   0 on success, a negative errno value otherwise and rte_errno is set.
3162  */
3163 static int
3164 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3165                                 const struct rte_flow_attr *attr,
3166                                 const struct rte_vlan_hdr *vlan,
3167                                 struct mlx5_flow *dev_flow,
3168                                 struct rte_flow_error *error)
3169 {
3170         struct mlx5_flow_dv_push_vlan_action_resource res;
3171
3172         memset(&res, 0, sizeof(res));
3173         res.vlan_tag =
3174                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3175                                  vlan->vlan_tci);
3176         if (attr->transfer)
3177                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3178         else
3179                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3180                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3181         return flow_dv_push_vlan_action_resource_register
3182                                             (dev, &res, dev_flow, error);
3183 }
3184
3185 /**
3186  * Validate the modify-header actions.
3187  *
3188  * @param[in] action_flags
3189  *   Holds the actions detected until now.
3190  * @param[in] action
3191  *   Pointer to the modify action.
3192  * @param[out] error
3193  *   Pointer to error structure.
3194  *
3195  * @return
3196  *   0 on success, a negative errno value otherwise and rte_errno is set.
3197  */
3198 static int
3199 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3200                                    const struct rte_flow_action *action,
3201                                    struct rte_flow_error *error)
3202 {
3203         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3204                 return rte_flow_error_set(error, EINVAL,
3205                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3206                                           NULL, "action configuration not set");
3207         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3208                 return rte_flow_error_set(error, EINVAL,
3209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3210                                           "can't have encap action before"
3211                                           " modify action");
3212         return 0;
3213 }
3214
3215 /**
3216  * Validate the modify-header MAC address actions.
3217  *
3218  * @param[in] action_flags
3219  *   Holds the actions detected until now.
3220  * @param[in] action
3221  *   Pointer to the modify action.
3222  * @param[in] item_flags
3223  *   Holds the items detected.
3224  * @param[out] error
3225  *   Pointer to error structure.
3226  *
3227  * @return
3228  *   0 on success, a negative errno value otherwise and rte_errno is set.
3229  */
3230 static int
3231 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3232                                    const struct rte_flow_action *action,
3233                                    const uint64_t item_flags,
3234                                    struct rte_flow_error *error)
3235 {
3236         int ret = 0;
3237
3238         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3239         if (!ret) {
3240                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3241                         return rte_flow_error_set(error, EINVAL,
3242                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3243                                                   NULL,
3244                                                   "no L2 item in pattern");
3245         }
3246         return ret;
3247 }
3248
3249 /**
3250  * Validate the modify-header IPv4 address actions.
3251  *
3252  * @param[in] action_flags
3253  *   Holds the actions detected until now.
3254  * @param[in] action
3255  *   Pointer to the modify action.
3256  * @param[in] item_flags
3257  *   Holds the items detected.
3258  * @param[out] error
3259  *   Pointer to error structure.
3260  *
3261  * @return
3262  *   0 on success, a negative errno value otherwise and rte_errno is set.
3263  */
3264 static int
3265 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3266                                     const struct rte_flow_action *action,
3267                                     const uint64_t item_flags,
3268                                     struct rte_flow_error *error)
3269 {
3270         int ret = 0;
3271         uint64_t layer;
3272
3273         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3274         if (!ret) {
3275                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3276                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3277                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3278                 if (!(item_flags & layer))
3279                         return rte_flow_error_set(error, EINVAL,
3280                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3281                                                   NULL,
3282                                                   "no ipv4 item in pattern");
3283         }
3284         return ret;
3285 }
3286
3287 /**
3288  * Validate the modify-header IPv6 address actions.
3289  *
3290  * @param[in] action_flags
3291  *   Holds the actions detected until now.
3292  * @param[in] action
3293  *   Pointer to the modify action.
3294  * @param[in] item_flags
3295  *   Holds the items detected.
3296  * @param[out] error
3297  *   Pointer to error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3304                                     const struct rte_flow_action *action,
3305                                     const uint64_t item_flags,
3306                                     struct rte_flow_error *error)
3307 {
3308         int ret = 0;
3309         uint64_t layer;
3310
3311         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3312         if (!ret) {
3313                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3314                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3315                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3316                 if (!(item_flags & layer))
3317                         return rte_flow_error_set(error, EINVAL,
3318                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3319                                                   NULL,
3320                                                   "no ipv6 item in pattern");
3321         }
3322         return ret;
3323 }
3324
3325 /**
3326  * Validate the modify-header TP actions.
3327  *
3328  * @param[in] action_flags
3329  *   Holds the actions detected until now.
3330  * @param[in] action
3331  *   Pointer to the modify action.
3332  * @param[in] item_flags
3333  *   Holds the items detected.
3334  * @param[out] error
3335  *   Pointer to error structure.
3336  *
3337  * @return
3338  *   0 on success, a negative errno value otherwise and rte_errno is set.
3339  */
3340 static int
3341 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3342                                   const struct rte_flow_action *action,
3343                                   const uint64_t item_flags,
3344                                   struct rte_flow_error *error)
3345 {
3346         int ret = 0;
3347         uint64_t layer;
3348
3349         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3350         if (!ret) {
3351                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3352                                  MLX5_FLOW_LAYER_INNER_L4 :
3353                                  MLX5_FLOW_LAYER_OUTER_L4;
3354                 if (!(item_flags & layer))
3355                         return rte_flow_error_set(error, EINVAL,
3356                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3357                                                   NULL, "no transport layer "
3358                                                   "in pattern");
3359         }
3360         return ret;
3361 }
3362
3363 /**
3364  * Validate the modify-header actions of increment/decrement
3365  * TCP Sequence-number.
3366  *
3367  * @param[in] action_flags
3368  *   Holds the actions detected until now.
3369  * @param[in] action
3370  *   Pointer to the modify action.
3371  * @param[in] item_flags
3372  *   Holds the items detected.
3373  * @param[out] error
3374  *   Pointer to error structure.
3375  *
3376  * @return
3377  *   0 on success, a negative errno value otherwise and rte_errno is set.
3378  */
3379 static int
3380 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3381                                        const struct rte_flow_action *action,
3382                                        const uint64_t item_flags,
3383                                        struct rte_flow_error *error)
3384 {
3385         int ret = 0;
3386         uint64_t layer;
3387
3388         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3389         if (!ret) {
3390                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3391                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3392                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3393                 if (!(item_flags & layer))
3394                         return rte_flow_error_set(error, EINVAL,
3395                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3396                                                   NULL, "no TCP item in"
3397                                                   " pattern");
3398                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3399                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3400                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3401                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3402                         return rte_flow_error_set(error, EINVAL,
3403                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3404                                                   NULL,
3405                                                   "cannot decrease and increase"
3406                                                   " TCP sequence number"
3407                                                   " at the same time");
3408         }
3409         return ret;
3410 }
3411
3412 /**
3413  * Validate the modify-header actions of increment/decrement
3414  * TCP Acknowledgment number.
3415  *
3416  * @param[in] action_flags
3417  *   Holds the actions detected until now.
3418  * @param[in] action
3419  *   Pointer to the modify action.
3420  * @param[in] item_flags
3421  *   Holds the items detected.
3422  * @param[out] error
3423  *   Pointer to error structure.
3424  *
3425  * @return
3426  *   0 on success, a negative errno value otherwise and rte_errno is set.
3427  */
3428 static int
3429 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3430                                        const struct rte_flow_action *action,
3431                                        const uint64_t item_flags,
3432                                        struct rte_flow_error *error)
3433 {
3434         int ret = 0;
3435         uint64_t layer;
3436
3437         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3438         if (!ret) {
3439                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3440                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3441                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3442                 if (!(item_flags & layer))
3443                         return rte_flow_error_set(error, EINVAL,
3444                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3445                                                   NULL, "no TCP item in"
3446                                                   " pattern");
3447                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3448                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3449                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3450                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3451                         return rte_flow_error_set(error, EINVAL,
3452                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3453                                                   NULL,
3454                                                   "cannot decrease and increase"
3455                                                   " TCP acknowledgment number"
3456                                                   " at the same time");
3457         }
3458         return ret;
3459 }
3460
3461 /**
3462  * Validate the modify-header TTL actions.
3463  *
3464  * @param[in] action_flags
3465  *   Holds the actions detected until now.
3466  * @param[in] action
3467  *   Pointer to the modify action.
3468  * @param[in] item_flags
3469  *   Holds the items detected.
3470  * @param[out] error
3471  *   Pointer to error structure.
3472  *
3473  * @return
3474  *   0 on success, a negative errno value otherwise and rte_errno is set.
3475  */
3476 static int
3477 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3478                                    const struct rte_flow_action *action,
3479                                    const uint64_t item_flags,
3480                                    struct rte_flow_error *error)
3481 {
3482         int ret = 0;
3483         uint64_t layer;
3484
3485         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3486         if (!ret) {
3487                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3488                                  MLX5_FLOW_LAYER_INNER_L3 :
3489                                  MLX5_FLOW_LAYER_OUTER_L3;
3490                 if (!(item_flags & layer))
3491                         return rte_flow_error_set(error, EINVAL,
3492                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3493                                                   NULL,
3494                                                   "no IP protocol in pattern");
3495         }
3496         return ret;
3497 }
3498
3499 /**
3500  * Validate jump action.
3501  *
3502  * @param[in] action
3503  *   Pointer to the jump action.
3504  * @param[in] action_flags
3505  *   Holds the actions detected until now.
3506  * @param[in] attributes
3507  *   Pointer to flow attributes
3508  * @param[in] external
3509  *   Action belongs to flow rule created by request external to PMD.
3510  * @param[out] error
3511  *   Pointer to error structure.
3512  *
3513  * @return
3514  *   0 on success, a negative errno value otherwise and rte_errno is set.
3515  */
3516 static int
3517 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3518                              uint64_t action_flags,
3519                              const struct rte_flow_attr *attributes,
3520                              bool external, struct rte_flow_error *error)
3521 {
3522         uint32_t target_group, table;
3523         int ret = 0;
3524
3525         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3526                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3527                 return rte_flow_error_set(error, EINVAL,
3528                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3529                                           "can't have 2 fate actions in"
3530                                           " same flow");
3531         if (action_flags & MLX5_FLOW_ACTION_METER)
3532                 return rte_flow_error_set(error, ENOTSUP,
3533                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3534                                           "jump with meter not support");
3535         if (!action->conf)
3536                 return rte_flow_error_set(error, EINVAL,
3537                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3538                                           NULL, "action configuration not set");
3539         target_group =
3540                 ((const struct rte_flow_action_jump *)action->conf)->group;
3541         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3542                                        true, &table, error);
3543         if (ret)
3544                 return ret;
3545         if (attributes->group == target_group)
3546                 return rte_flow_error_set(error, EINVAL,
3547                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3548                                           "target group must be other than"
3549                                           " the current flow group");
3550         return 0;
3551 }
3552
3553 /*
3554  * Validate the port_id action.
3555  *
3556  * @param[in] dev
3557  *   Pointer to rte_eth_dev structure.
3558  * @param[in] action_flags
3559  *   Bit-fields that holds the actions detected until now.
3560  * @param[in] action
3561  *   Port_id RTE action structure.
3562  * @param[in] attr
3563  *   Attributes of flow that includes this action.
3564  * @param[out] error
3565  *   Pointer to error structure.
3566  *
3567  * @return
3568  *   0 on success, a negative errno value otherwise and rte_errno is set.
3569  */
3570 static int
3571 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3572                                 uint64_t action_flags,
3573                                 const struct rte_flow_action *action,
3574                                 const struct rte_flow_attr *attr,
3575                                 struct rte_flow_error *error)
3576 {
3577         const struct rte_flow_action_port_id *port_id;
3578         struct mlx5_priv *act_priv;
3579         struct mlx5_priv *dev_priv;
3580         uint16_t port;
3581
3582         if (!attr->transfer)
3583                 return rte_flow_error_set(error, ENOTSUP,
3584                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3585                                           NULL,
3586                                           "port id action is valid in transfer"
3587                                           " mode only");
3588         if (!action || !action->conf)
3589                 return rte_flow_error_set(error, ENOTSUP,
3590                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3591                                           NULL,
3592                                           "port id action parameters must be"
3593                                           " specified");
3594         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3595                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3596                 return rte_flow_error_set(error, EINVAL,
3597                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3598                                           "can have only one fate actions in"
3599                                           " a flow");
3600         dev_priv = mlx5_dev_to_eswitch_info(dev);
3601         if (!dev_priv)
3602                 return rte_flow_error_set(error, rte_errno,
3603                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3604                                           NULL,
3605                                           "failed to obtain E-Switch info");
3606         port_id = action->conf;
3607         port = port_id->original ? dev->data->port_id : port_id->id;
3608         act_priv = mlx5_port_to_eswitch_info(port, false);
3609         if (!act_priv)
3610                 return rte_flow_error_set
3611                                 (error, rte_errno,
3612                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3613                                  "failed to obtain E-Switch port id for port");
3614         if (act_priv->domain_id != dev_priv->domain_id)
3615                 return rte_flow_error_set
3616                                 (error, EINVAL,
3617                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3618                                  "port does not belong to"
3619                                  " E-Switch being configured");
3620         return 0;
3621 }
3622
3623 /**
3624  * Get the maximum number of modify header actions.
3625  *
3626  * @param dev
3627  *   Pointer to rte_eth_dev structure.
3628  * @param flags
3629  *   Flags bits to check if root level.
3630  *
3631  * @return
3632  *   Max number of modify header actions device can support.
3633  */
3634 static unsigned int
3635 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3636 {
3637         /*
3638          * There's no way to directly query the max cap. Although it has to be
3639          * acquried by iterative trial, it is a safe assumption that more
3640          * actions are supported by FW if extensive metadata register is
3641          * supported. (Only in the root table)
3642          */
3643         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3644                 return MLX5_MAX_MODIFY_NUM;
3645         else
3646                 return mlx5_flow_ext_mreg_supported(dev) ?
3647                                         MLX5_ROOT_TBL_MODIFY_NUM :
3648                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3649 }
3650
3651 /**
3652  * Validate the meter action.
3653  *
3654  * @param[in] dev
3655  *   Pointer to rte_eth_dev structure.
3656  * @param[in] action_flags
3657  *   Bit-fields that holds the actions detected until now.
3658  * @param[in] action
3659  *   Pointer to the meter action.
3660  * @param[in] attr
3661  *   Attributes of flow that includes this action.
3662  * @param[out] error
3663  *   Pointer to error structure.
3664  *
3665  * @return
3666  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3667  */
3668 static int
3669 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3670                                 uint64_t action_flags,
3671                                 const struct rte_flow_action *action,
3672                                 const struct rte_flow_attr *attr,
3673                                 struct rte_flow_error *error)
3674 {
3675         struct mlx5_priv *priv = dev->data->dev_private;
3676         const struct rte_flow_action_meter *am = action->conf;
3677         struct mlx5_flow_meter *fm;
3678
3679         if (!am)
3680                 return rte_flow_error_set(error, EINVAL,
3681                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3682                                           "meter action conf is NULL");
3683
3684         if (action_flags & MLX5_FLOW_ACTION_METER)
3685                 return rte_flow_error_set(error, ENOTSUP,
3686                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687                                           "meter chaining not support");
3688         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3689                 return rte_flow_error_set(error, ENOTSUP,
3690                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3691                                           "meter with jump not support");
3692         if (!priv->mtr_en)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3695                                           NULL,
3696                                           "meter action not supported");
3697         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3698         if (!fm)
3699                 return rte_flow_error_set(error, EINVAL,
3700                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3701                                           "Meter not found");
3702         if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3703               (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3704               (!fm->attr.egress && !attr->egress && attr->ingress))))
3705                 return rte_flow_error_set(error, EINVAL,
3706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3707                                           "Flow attributes are either invalid "
3708                                           "or have a conflict with current "
3709                                           "meter attributes");
3710         return 0;
3711 }
3712
3713 /**
3714  * Validate the modify-header IPv4 DSCP actions.
3715  *
3716  * @param[in] action_flags
3717  *   Holds the actions detected until now.
3718  * @param[in] action
3719  *   Pointer to the modify action.
3720  * @param[in] item_flags
3721  *   Holds the items detected.
3722  * @param[out] error
3723  *   Pointer to error structure.
3724  *
3725  * @return
3726  *   0 on success, a negative errno value otherwise and rte_errno is set.
3727  */
3728 static int
3729 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3730                                          const struct rte_flow_action *action,
3731                                          const uint64_t item_flags,
3732                                          struct rte_flow_error *error)
3733 {
3734         int ret = 0;
3735
3736         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3737         if (!ret) {
3738                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3739                         return rte_flow_error_set(error, EINVAL,
3740                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3741                                                   NULL,
3742                                                   "no ipv4 item in pattern");
3743         }
3744         return ret;
3745 }
3746
3747 /**
3748  * Validate the modify-header IPv6 DSCP actions.
3749  *
3750  * @param[in] action_flags
3751  *   Holds the actions detected until now.
3752  * @param[in] action
3753  *   Pointer to the modify action.
3754  * @param[in] item_flags
3755  *   Holds the items detected.
3756  * @param[out] error
3757  *   Pointer to error structure.
3758  *
3759  * @return
3760  *   0 on success, a negative errno value otherwise and rte_errno is set.
3761  */
3762 static int
3763 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3764                                          const struct rte_flow_action *action,
3765                                          const uint64_t item_flags,
3766                                          struct rte_flow_error *error)
3767 {
3768         int ret = 0;
3769
3770         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3771         if (!ret) {
3772                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3773                         return rte_flow_error_set(error, EINVAL,
3774                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3775                                                   NULL,
3776                                                   "no ipv6 item in pattern");
3777         }
3778         return ret;
3779 }
3780
3781 /**
3782  * Find existing modify-header resource or create and register a new one.
3783  *
3784  * @param dev[in, out]
3785  *   Pointer to rte_eth_dev structure.
3786  * @param[in, out] resource
3787  *   Pointer to modify-header resource.
3788  * @parm[in, out] dev_flow
3789  *   Pointer to the dev_flow.
3790  * @param[out] error
3791  *   pointer to error structure.
3792  *
3793  * @return
3794  *   0 on success otherwise -errno and errno is set.
3795  */
3796 static int
3797 flow_dv_modify_hdr_resource_register
3798                         (struct rte_eth_dev *dev,
3799                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3800                          struct mlx5_flow *dev_flow,
3801                          struct rte_flow_error *error)
3802 {
3803         struct mlx5_priv *priv = dev->data->dev_private;
3804         struct mlx5_ibv_shared *sh = priv->sh;
3805         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3806         struct mlx5dv_dr_domain *ns;
3807         uint32_t actions_len;
3808
3809         resource->flags = dev_flow->dv.group ? 0 :
3810                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3811         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3812                                     resource->flags))
3813                 return rte_flow_error_set(error, EOVERFLOW,
3814                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3815                                           "too many modify header items");
3816         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3817                 ns = sh->fdb_domain;
3818         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3819                 ns = sh->tx_domain;
3820         else
3821                 ns = sh->rx_domain;
3822         /* Lookup a matching resource from cache. */
3823         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3824         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3825                 if (resource->ft_type == cache_resource->ft_type &&
3826                     resource->actions_num == cache_resource->actions_num &&
3827                     resource->flags == cache_resource->flags &&
3828                     !memcmp((const void *)resource->actions,
3829                             (const void *)cache_resource->actions,
3830                             actions_len)) {
3831                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3832                                 (void *)cache_resource,
3833                                 rte_atomic32_read(&cache_resource->refcnt));
3834                         rte_atomic32_inc(&cache_resource->refcnt);
3835                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3836                         return 0;
3837                 }
3838         }
3839         /* Register new modify-header resource. */
3840         cache_resource = rte_calloc(__func__, 1,
3841                                     sizeof(*cache_resource) + actions_len, 0);
3842         if (!cache_resource)
3843                 return rte_flow_error_set(error, ENOMEM,
3844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3845                                           "cannot allocate resource memory");
3846         *cache_resource = *resource;
3847         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3848         cache_resource->verbs_action =
3849                 mlx5_glue->dv_create_flow_action_modify_header
3850                                         (sh->ctx, cache_resource->ft_type, ns,
3851                                          cache_resource->flags, actions_len,
3852                                          (uint64_t *)cache_resource->actions);
3853         if (!cache_resource->verbs_action) {
3854                 rte_free(cache_resource);
3855                 return rte_flow_error_set(error, ENOMEM,
3856                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3857                                           NULL, "cannot create action");
3858         }
3859         rte_atomic32_init(&cache_resource->refcnt);
3860         rte_atomic32_inc(&cache_resource->refcnt);
3861         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3862         dev_flow->handle->dvh.modify_hdr = cache_resource;
3863         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3864                 (void *)cache_resource,
3865                 rte_atomic32_read(&cache_resource->refcnt));
3866         return 0;
3867 }
3868
3869 /**
3870  * Get DV flow counter by index.
3871  *
3872  * @param[in] dev
3873  *   Pointer to the Ethernet device structure.
3874  * @param[in] idx
3875  *   mlx5 flow counter index in the container.
3876  * @param[out] ppool
3877  *   mlx5 flow counter pool in the container,
3878  *
3879  * @return
3880  *   Pointer to the counter, NULL otherwise.
3881  */
3882 static struct mlx5_flow_counter *
3883 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3884                            uint32_t idx,
3885                            struct mlx5_flow_counter_pool **ppool)
3886 {
3887         struct mlx5_priv *priv = dev->data->dev_private;
3888         struct mlx5_pools_container *cont;
3889         struct mlx5_flow_counter_pool *pool;
3890         uint32_t batch = 0;
3891
3892         idx--;
3893         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3894                 idx -= MLX5_CNT_BATCH_OFFSET;
3895                 batch = 1;
3896         }
3897         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3898         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3899         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3900         MLX5_ASSERT(pool);
3901         if (ppool)
3902                 *ppool = pool;
3903         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3904 }
3905
3906 /**
3907  * Get a pool by devx counter ID.
3908  *
3909  * @param[in] cont
3910  *   Pointer to the counter container.
3911  * @param[in] id
3912  *   The counter devx ID.
3913  *
3914  * @return
3915  *   The counter pool pointer if exists, NULL otherwise,
3916  */
3917 static struct mlx5_flow_counter_pool *
3918 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3919 {
3920         uint32_t i;
3921         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3922
3923         for (i = 0; i < n_valid; i++) {
3924                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3925                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3926                            MLX5_COUNTERS_PER_POOL;
3927
3928                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3929                         /*
3930                          * Move the pool to the head, as counter allocate
3931                          * always gets the first pool in the container.
3932                          */
3933                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3934                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3935                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3936                         }
3937                         return pool;
3938                 }
3939         }
3940         return NULL;
3941 }
3942
3943 /**
3944  * Allocate a new memory for the counter values wrapped by all the needed
3945  * management.
3946  *
3947  * @param[in] dev
3948  *   Pointer to the Ethernet device structure.
3949  * @param[in] raws_n
3950  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3951  *
3952  * @return
3953  *   The new memory management pointer on success, otherwise NULL and rte_errno
3954  *   is set.
3955  */
3956 static struct mlx5_counter_stats_mem_mng *
3957 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3958 {
3959         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3960                                         (dev->data->dev_private))->sh;
3961         struct mlx5_devx_mkey_attr mkey_attr;
3962         struct mlx5_counter_stats_mem_mng *mem_mng;
3963         volatile struct flow_counter_stats *raw_data;
3964         int size = (sizeof(struct flow_counter_stats) *
3965                         MLX5_COUNTERS_PER_POOL +
3966                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3967                         sizeof(struct mlx5_counter_stats_mem_mng);
3968         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3969         int i;
3970
3971         if (!mem) {
3972                 rte_errno = ENOMEM;
3973                 return NULL;
3974         }
3975         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3976         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3977         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3978                                                  IBV_ACCESS_LOCAL_WRITE);
3979         if (!mem_mng->umem) {
3980                 rte_errno = errno;
3981                 rte_free(mem);
3982                 return NULL;
3983         }
3984         mkey_attr.addr = (uintptr_t)mem;
3985         mkey_attr.size = size;
3986         mkey_attr.umem_id = mem_mng->umem->umem_id;
3987         mkey_attr.pd = sh->pdn;
3988         mkey_attr.log_entity_size = 0;
3989         mkey_attr.pg_access = 0;
3990         mkey_attr.klm_array = NULL;
3991         mkey_attr.klm_num = 0;
3992         mkey_attr.relaxed_ordering = 1;
3993         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3994         if (!mem_mng->dm) {
3995                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3996                 rte_errno = errno;
3997                 rte_free(mem);
3998                 return NULL;
3999         }
4000         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4001         raw_data = (volatile struct flow_counter_stats *)mem;
4002         for (i = 0; i < raws_n; ++i) {
4003                 mem_mng->raws[i].mem_mng = mem_mng;
4004                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4005         }
4006         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4007         return mem_mng;
4008 }
4009
4010 /**
4011  * Resize a counter container.
4012  *
4013  * @param[in] dev
4014  *   Pointer to the Ethernet device structure.
4015  * @param[in] batch
4016  *   Whether the pool is for counter that was allocated by batch command.
4017  *
4018  * @return
4019  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4020  */
4021 static struct mlx5_pools_container *
4022 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4023 {
4024         struct mlx5_priv *priv = dev->data->dev_private;
4025         struct mlx5_pools_container *cont =
4026                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4027         struct mlx5_pools_container *new_cont =
4028                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4029         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4030         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4031         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4032         int i;
4033
4034         /* Fallback mode has no background thread. Skip the check. */
4035         if (!priv->counter_fallback &&
4036             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4037                 /* The last resize still hasn't detected by the host thread. */
4038                 rte_errno = EAGAIN;
4039                 return NULL;
4040         }
4041         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4042         if (!new_cont->pools) {
4043                 rte_errno = ENOMEM;
4044                 return NULL;
4045         }
4046         if (cont->n)
4047                 memcpy(new_cont->pools, cont->pools, cont->n *
4048                        sizeof(struct mlx5_flow_counter_pool *));
4049         /*
4050          * Fallback mode query the counter directly, no background query
4051          * resources are needed.
4052          */
4053         if (!priv->counter_fallback) {
4054                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4055                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4056                 if (!mem_mng) {
4057                         rte_free(new_cont->pools);
4058                         return NULL;
4059                 }
4060                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4061                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4062                                          mem_mng->raws +
4063                                          MLX5_CNT_CONTAINER_RESIZE +
4064                                          i, next);
4065         } else {
4066                 /*
4067                  * Release the old container pools directly as no background
4068                  * thread helps that.
4069                  */
4070                 rte_free(cont->pools);
4071         }
4072         new_cont->n = resize;
4073         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4074         TAILQ_INIT(&new_cont->pool_list);
4075         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4076         new_cont->init_mem_mng = mem_mng;
4077         rte_cio_wmb();
4078          /* Flip the master container. */
4079         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4080         return new_cont;
4081 }
4082
4083 /**
4084  * Query a devx flow counter.
4085  *
4086  * @param[in] dev
4087  *   Pointer to the Ethernet device structure.
4088  * @param[in] cnt
4089  *   Index to the flow counter.
4090  * @param[out] pkts
4091  *   The statistics value of packets.
4092  * @param[out] bytes
4093  *   The statistics value of bytes.
4094  *
4095  * @return
4096  *   0 on success, otherwise a negative errno value and rte_errno is set.
4097  */
4098 static inline int
4099 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4100                      uint64_t *bytes)
4101 {
4102         struct mlx5_priv *priv = dev->data->dev_private;
4103         struct mlx5_flow_counter_pool *pool = NULL;
4104         struct mlx5_flow_counter *cnt;
4105         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4106         int offset;
4107
4108         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4109         MLX5_ASSERT(pool);
4110         if (counter < MLX5_CNT_BATCH_OFFSET) {
4111                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4112                 if (priv->counter_fallback)
4113                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4114                                         0, pkts, bytes, 0, NULL, NULL, 0);
4115         }
4116
4117         rte_spinlock_lock(&pool->sl);
4118         /*
4119          * The single counters allocation may allocate smaller ID than the
4120          * current allocated in parallel to the host reading.
4121          * In this case the new counter values must be reported as 0.
4122          */
4123         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4124                 *pkts = 0;
4125                 *bytes = 0;
4126         } else {
4127                 offset = cnt - &pool->counters_raw[0];
4128                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4129                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4130         }
4131         rte_spinlock_unlock(&pool->sl);
4132         return 0;
4133 }
4134
4135 /**
4136  * Create and initialize a new counter pool.
4137  *
4138  * @param[in] dev
4139  *   Pointer to the Ethernet device structure.
4140  * @param[out] dcs
4141  *   The devX counter handle.
4142  * @param[in] batch
4143  *   Whether the pool is for counter that was allocated by batch command.
4144  * @param[in/out] cont_cur
4145  *   Pointer to the container pointer, it will be update in pool resize.
4146  *
4147  * @return
4148  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4149  */
4150 static struct mlx5_pools_container *
4151 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4152                     uint32_t batch)
4153 {
4154         struct mlx5_priv *priv = dev->data->dev_private;
4155         struct mlx5_flow_counter_pool *pool;
4156         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4157                                                                0);
4158         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4159         uint32_t size;
4160
4161         if (cont->n == n_valid) {
4162                 cont = flow_dv_container_resize(dev, batch);
4163                 if (!cont)
4164                         return NULL;
4165         }
4166         size = sizeof(*pool);
4167         if (!batch)
4168                 size += MLX5_COUNTERS_PER_POOL *
4169                         sizeof(struct mlx5_flow_counter_ext);
4170         pool = rte_calloc(__func__, 1, size, 0);
4171         if (!pool) {
4172                 rte_errno = ENOMEM;
4173                 return NULL;
4174         }
4175         pool->min_dcs = dcs;
4176         if (!priv->counter_fallback)
4177                 pool->raw = cont->init_mem_mng->raws + n_valid %
4178                                                      MLX5_CNT_CONTAINER_RESIZE;
4179         pool->raw_hw = NULL;
4180         rte_spinlock_init(&pool->sl);
4181         /*
4182          * The generation of the new allocated counters in this pool is 0, 2 in
4183          * the pool generation makes all the counters valid for allocation.
4184          * The start and end query generation protect the counters be released
4185          * between the query and update gap period will not be reallocated
4186          * without the last query finished and stats updated to the memory.
4187          */
4188         rte_atomic64_set(&pool->start_query_gen, 0x2);
4189         /*
4190          * There's no background query thread for fallback mode, set the
4191          * end_query_gen to the maximum value since no need to wait for
4192          * statistics update.
4193          */
4194         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4195                          INT64_MAX : 0x2);
4196         TAILQ_INIT(&pool->counters);
4197         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4198         pool->index = n_valid;
4199         cont->pools[n_valid] = pool;
4200         /* Pool initialization must be updated before host thread access. */
4201         rte_cio_wmb();
4202         rte_atomic16_add(&cont->n_valid, 1);
4203         return cont;
4204 }
4205
4206 /**
4207  * Prepare a new counter and/or a new counter pool.
4208  *
4209  * @param[in] dev
4210  *   Pointer to the Ethernet device structure.
4211  * @param[out] cnt_free
4212  *   Where to put the pointer of a new counter.
4213  * @param[in] batch
4214  *   Whether the pool is for counter that was allocated by batch command.
4215  *
4216  * @return
4217  *   The counter container pointer and @p cnt_free is set on success,
4218  *   NULL otherwise and rte_errno is set.
4219  */
4220 static struct mlx5_pools_container *
4221 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4222                              struct mlx5_flow_counter **cnt_free,
4223                              uint32_t batch)
4224 {
4225         struct mlx5_priv *priv = dev->data->dev_private;
4226         struct mlx5_pools_container *cont;
4227         struct mlx5_flow_counter_pool *pool;
4228         struct mlx5_devx_obj *dcs = NULL;
4229         struct mlx5_flow_counter *cnt;
4230         uint32_t i;
4231
4232         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4233         if (!batch) {
4234                 /* bulk_bitmap must be 0 for single counter allocation. */
4235                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4236                 if (!dcs)
4237                         return NULL;
4238                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4239                 if (!pool) {
4240                         cont = flow_dv_pool_create(dev, dcs, batch);
4241                         if (!cont) {
4242                                 mlx5_devx_cmd_destroy(dcs);
4243                                 return NULL;
4244                         }
4245                         pool = TAILQ_FIRST(&cont->pool_list);
4246                 } else if (dcs->id < pool->min_dcs->id) {
4247                         rte_atomic64_set(&pool->a64_dcs,
4248                                          (int64_t)(uintptr_t)dcs);
4249                 }
4250                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4251                 cnt = &pool->counters_raw[i];
4252                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4253                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4254                 *cnt_free = cnt;
4255                 return cont;
4256         }
4257         /* bulk_bitmap is in 128 counters units. */
4258         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4259                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4260         if (!dcs) {
4261                 rte_errno = ENODATA;
4262                 return NULL;
4263         }
4264         cont = flow_dv_pool_create(dev, dcs, batch);
4265         if (!cont) {
4266                 mlx5_devx_cmd_destroy(dcs);
4267                 return NULL;
4268         }
4269         pool = TAILQ_FIRST(&cont->pool_list);
4270         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4271                 cnt = &pool->counters_raw[i];
4272                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4273         }
4274         *cnt_free = &pool->counters_raw[0];
4275         return cont;
4276 }
4277
4278 /**
4279  * Search for existed shared counter.
4280  *
4281  * @param[in] cont
4282  *   Pointer to the relevant counter pool container.
4283  * @param[in] id
4284  *   The shared counter ID to search.
4285  * @param[out] ppool
4286  *   mlx5 flow counter pool in the container,
4287  *
4288  * @return
4289  *   NULL if not existed, otherwise pointer to the shared extend counter.
4290  */
4291 static struct mlx5_flow_counter_ext *
4292 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4293                               struct mlx5_flow_counter_pool **ppool)
4294 {
4295         static struct mlx5_flow_counter_ext *cnt;
4296         struct mlx5_flow_counter_pool *pool;
4297         uint32_t i;
4298         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4299
4300         for (i = 0; i < n_valid; i++) {
4301                 pool = cont->pools[i];
4302                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4303                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4304                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4305                                 if (ppool)
4306                                         *ppool = cont->pools[i];
4307                                 return cnt;
4308                         }
4309                 }
4310         }
4311         return NULL;
4312 }
4313
4314 /**
4315  * Allocate a flow counter.
4316  *
4317  * @param[in] dev
4318  *   Pointer to the Ethernet device structure.
4319  * @param[in] shared
4320  *   Indicate if this counter is shared with other flows.
4321  * @param[in] id
4322  *   Counter identifier.
4323  * @param[in] group
4324  *   Counter flow group.
4325  *
4326  * @return
4327  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4328  */
4329 static uint32_t
4330 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4331                       uint16_t group)
4332 {
4333         struct mlx5_priv *priv = dev->data->dev_private;
4334         struct mlx5_flow_counter_pool *pool = NULL;
4335         struct mlx5_flow_counter *cnt_free = NULL;
4336         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4337         /*
4338          * Currently group 0 flow counter cannot be assigned to a flow if it is
4339          * not the first one in the batch counter allocation, so it is better
4340          * to allocate counters one by one for these flows in a separate
4341          * container.
4342          * A counter can be shared between different groups so need to take
4343          * shared counters from the single container.
4344          */
4345         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4346         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4347                                                                0);
4348         uint32_t cnt_idx;
4349
4350         if (!priv->config.devx) {
4351                 rte_errno = ENOTSUP;
4352                 return 0;
4353         }
4354         if (shared) {
4355                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4356                 if (cnt_ext) {
4357                         if (cnt_ext->ref_cnt + 1 == 0) {
4358                                 rte_errno = E2BIG;
4359                                 return 0;
4360                         }
4361                         cnt_ext->ref_cnt++;
4362                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4363                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4364                                   + 1;
4365                         return cnt_idx;
4366                 }
4367         }
4368         /* Pools which has a free counters are in the start. */
4369         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4370                 /*
4371                  * The free counter reset values must be updated between the
4372                  * counter release to the counter allocation, so, at least one
4373                  * query must be done in this time. ensure it by saving the
4374                  * query generation in the release time.
4375                  * The free list is sorted according to the generation - so if
4376                  * the first one is not updated, all the others are not
4377                  * updated too.
4378                  */
4379                 cnt_free = TAILQ_FIRST(&pool->counters);
4380                 if (cnt_free && cnt_free->query_gen <
4381                     rte_atomic64_read(&pool->end_query_gen))
4382                         break;
4383                 cnt_free = NULL;
4384         }
4385         if (!cnt_free) {
4386                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4387                 if (!cont)
4388                         return 0;
4389                 pool = TAILQ_FIRST(&cont->pool_list);
4390         }
4391         if (!batch)
4392                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4393         /* Create a DV counter action only in the first time usage. */
4394         if (!cnt_free->action) {
4395                 uint16_t offset;
4396                 struct mlx5_devx_obj *dcs;
4397
4398                 if (batch) {
4399                         offset = cnt_free - &pool->counters_raw[0];
4400                         dcs = pool->min_dcs;
4401                 } else {
4402                         offset = 0;
4403                         dcs = cnt_ext->dcs;
4404                 }
4405                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4406                                         (dcs->obj, offset);
4407                 if (!cnt_free->action) {
4408                         rte_errno = errno;
4409                         return 0;
4410                 }
4411         }
4412         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4413                                     (cnt_free - pool->counters_raw));
4414         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4415         /* Update the counter reset values. */
4416         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4417                                  &cnt_free->bytes))
4418                 return 0;
4419         if (cnt_ext) {
4420                 cnt_ext->shared = shared;
4421                 cnt_ext->ref_cnt = 1;
4422                 cnt_ext->id = id;
4423         }
4424         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4425                 /* Start the asynchronous batch query by the host thread. */
4426                 mlx5_set_query_alarm(priv->sh);
4427         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4428         if (TAILQ_EMPTY(&pool->counters)) {
4429                 /* Move the pool to the end of the container pool list. */
4430                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4431                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4432         }
4433         return cnt_idx;
4434 }
4435
4436 /**
4437  * Release a flow counter.
4438  *
4439  * @param[in] dev
4440  *   Pointer to the Ethernet device structure.
4441  * @param[in] counter
4442  *   Index to the counter handler.
4443  */
4444 static void
4445 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4446 {
4447         struct mlx5_flow_counter_pool *pool = NULL;
4448         struct mlx5_flow_counter *cnt;
4449         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4450
4451         if (!counter)
4452                 return;
4453         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4454         MLX5_ASSERT(pool);
4455         if (counter < MLX5_CNT_BATCH_OFFSET) {
4456                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4457                 if (cnt_ext && --cnt_ext->ref_cnt)
4458                         return;
4459         }
4460         /* Put the counter in the end - the last updated one. */
4461         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4462         /*
4463          * Counters released between query trigger and handler need
4464          * to wait the next round of query. Since the packets arrive
4465          * in the gap period will not be taken into account to the
4466          * old counter.
4467          */
4468         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4469 }
4470
4471 /**
4472  * Verify the @p attributes will be correctly understood by the NIC and store
4473  * them in the @p flow if everything is correct.
4474  *
4475  * @param[in] dev
4476  *   Pointer to dev struct.
4477  * @param[in] attributes
4478  *   Pointer to flow attributes
4479  * @param[in] external
4480  *   This flow rule is created by request external to PMD.
4481  * @param[out] error
4482  *   Pointer to error structure.
4483  *
4484  * @return
4485  *   0 on success, a negative errno value otherwise and rte_errno is set.
4486  */
4487 static int
4488 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4489                             const struct rte_flow_attr *attributes,
4490                             bool external __rte_unused,
4491                             struct rte_flow_error *error)
4492 {
4493         struct mlx5_priv *priv = dev->data->dev_private;
4494         uint32_t priority_max = priv->config.flow_prio - 1;
4495
4496 #ifndef HAVE_MLX5DV_DR
4497         if (attributes->group)
4498                 return rte_flow_error_set(error, ENOTSUP,
4499                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4500                                           NULL,
4501                                           "groups are not supported");
4502 #else
4503         uint32_t table;
4504         int ret;
4505
4506         ret = mlx5_flow_group_to_table(attributes, external,
4507                                        attributes->group, !!priv->fdb_def_rule,
4508                                        &table, error);
4509         if (ret)
4510                 return ret;
4511 #endif
4512         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4513             attributes->priority >= priority_max)
4514                 return rte_flow_error_set(error, ENOTSUP,
4515                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4516                                           NULL,
4517                                           "priority out of range");
4518         if (attributes->transfer) {
4519                 if (!priv->config.dv_esw_en)
4520                         return rte_flow_error_set
4521                                 (error, ENOTSUP,
4522                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4523                                  "E-Switch dr is not supported");
4524                 if (!(priv->representor || priv->master))
4525                         return rte_flow_error_set
4526                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4527                                  NULL, "E-Switch configuration can only be"
4528                                  " done by a master or a representor device");
4529                 if (attributes->egress)
4530                         return rte_flow_error_set
4531                                 (error, ENOTSUP,
4532                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4533                                  "egress is not supported");
4534         }
4535         if (!(attributes->egress ^ attributes->ingress))
4536                 return rte_flow_error_set(error, ENOTSUP,
4537                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4538                                           "must specify exactly one of "
4539                                           "ingress or egress");
4540         return 0;
4541 }
4542
4543 /**
4544  * Internal validation function. For validating both actions and items.
4545  *
4546  * @param[in] dev
4547  *   Pointer to the rte_eth_dev structure.
4548  * @param[in] attr
4549  *   Pointer to the flow attributes.
4550  * @param[in] items
4551  *   Pointer to the list of items.
4552  * @param[in] actions
4553  *   Pointer to the list of actions.
4554  * @param[in] external
4555  *   This flow rule is created by request external to PMD.
4556  * @param[out] error
4557  *   Pointer to the error structure.
4558  *
4559  * @return
4560  *   0 on success, a negative errno value otherwise and rte_errno is set.
4561  */
4562 static int
4563 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4564                  const struct rte_flow_item items[],
4565                  const struct rte_flow_action actions[],
4566                  bool external, struct rte_flow_error *error)
4567 {
4568         int ret;
4569         uint64_t action_flags = 0;
4570         uint64_t item_flags = 0;
4571         uint64_t last_item = 0;
4572         uint8_t next_protocol = 0xff;
4573         uint16_t ether_type = 0;
4574         int actions_n = 0;
4575         uint8_t item_ipv6_proto = 0;
4576         const struct rte_flow_item *gre_item = NULL;
4577         const struct rte_flow_action_raw_decap *decap;
4578         const struct rte_flow_action_raw_encap *encap;
4579         const struct rte_flow_action_rss *rss;
4580         const struct rte_flow_item_tcp nic_tcp_mask = {
4581                 .hdr = {
4582                         .tcp_flags = 0xFF,
4583                         .src_port = RTE_BE16(UINT16_MAX),
4584                         .dst_port = RTE_BE16(UINT16_MAX),
4585                 }
4586         };
4587         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4588                 .hdr = {
4589                         .src_addr = RTE_BE32(0xffffffff),
4590                         .dst_addr = RTE_BE32(0xffffffff),
4591                         .type_of_service = 0xff,
4592                         .next_proto_id = 0xff,
4593                         .time_to_live = 0xff,
4594                 },
4595         };
4596         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4597                 .hdr = {
4598                         .src_addr =
4599                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4600                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4601                         .dst_addr =
4602                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4603                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4604                         .vtc_flow = RTE_BE32(0xffffffff),
4605                         .proto = 0xff,
4606                         .hop_limits = 0xff,
4607                 },
4608         };
4609         struct mlx5_priv *priv = dev->data->dev_private;
4610         struct mlx5_dev_config *dev_conf = &priv->config;
4611         uint16_t queue_index = 0xFFFF;
4612         const struct rte_flow_item_vlan *vlan_m = NULL;
4613
4614         if (items == NULL)
4615                 return -1;
4616         ret = flow_dv_validate_attributes(dev, attr, external, error);
4617         if (ret < 0)
4618                 return ret;
4619         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4620                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4621                 int type = items->type;
4622
4623                 switch (type) {
4624                 case RTE_FLOW_ITEM_TYPE_VOID:
4625                         break;
4626                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4627                         ret = flow_dv_validate_item_port_id
4628                                         (dev, items, attr, item_flags, error);
4629                         if (ret < 0)
4630                                 return ret;
4631                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4632                         break;
4633                 case RTE_FLOW_ITEM_TYPE_ETH:
4634                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4635                                                           error);
4636                         if (ret < 0)
4637                                 return ret;
4638                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4639                                              MLX5_FLOW_LAYER_OUTER_L2;
4640                         if (items->mask != NULL && items->spec != NULL) {
4641                                 ether_type =
4642                                         ((const struct rte_flow_item_eth *)
4643                                          items->spec)->type;
4644                                 ether_type &=
4645                                         ((const struct rte_flow_item_eth *)
4646                                          items->mask)->type;
4647                                 ether_type = rte_be_to_cpu_16(ether_type);
4648                         } else {
4649                                 ether_type = 0;
4650                         }
4651                         break;
4652                 case RTE_FLOW_ITEM_TYPE_VLAN:
4653                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4654                                                            dev, error);
4655                         if (ret < 0)
4656                                 return ret;
4657                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4658                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4659                         if (items->mask != NULL && items->spec != NULL) {
4660                                 ether_type =
4661                                         ((const struct rte_flow_item_vlan *)
4662                                          items->spec)->inner_type;
4663                                 ether_type &=
4664                                         ((const struct rte_flow_item_vlan *)
4665                                          items->mask)->inner_type;
4666                                 ether_type = rte_be_to_cpu_16(ether_type);
4667                         } else {
4668                                 ether_type = 0;
4669                         }
4670                         /* Store outer VLAN mask for of_push_vlan action. */
4671                         if (!tunnel)
4672                                 vlan_m = items->mask;
4673                         break;
4674                 case RTE_FLOW_ITEM_TYPE_IPV4:
4675                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4676                                                   &item_flags, &tunnel);
4677                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4678                                                            last_item,
4679                                                            ether_type,
4680                                                            &nic_ipv4_mask,
4681                                                            error);
4682                         if (ret < 0)
4683                                 return ret;
4684                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4685                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4686                         if (items->mask != NULL &&
4687                             ((const struct rte_flow_item_ipv4 *)
4688                              items->mask)->hdr.next_proto_id) {
4689                                 next_protocol =
4690                                         ((const struct rte_flow_item_ipv4 *)
4691                                          (items->spec))->hdr.next_proto_id;
4692                                 next_protocol &=
4693                                         ((const struct rte_flow_item_ipv4 *)
4694                                          (items->mask))->hdr.next_proto_id;
4695                         } else {
4696                                 /* Reset for inner layer. */
4697                                 next_protocol = 0xff;
4698                         }
4699                         break;
4700                 case RTE_FLOW_ITEM_TYPE_IPV6:
4701                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4702                                                   &item_flags, &tunnel);
4703                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4704                                                            last_item,
4705                                                            ether_type,
4706                                                            &nic_ipv6_mask,
4707                                                            error);
4708                         if (ret < 0)
4709                                 return ret;
4710                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4711                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4712                         if (items->mask != NULL &&
4713                             ((const struct rte_flow_item_ipv6 *)
4714                              items->mask)->hdr.proto) {
4715                                 item_ipv6_proto =
4716                                         ((const struct rte_flow_item_ipv6 *)
4717                                          items->spec)->hdr.proto;
4718                                 next_protocol =
4719                                         ((const struct rte_flow_item_ipv6 *)
4720                                          items->spec)->hdr.proto;
4721                                 next_protocol &=
4722                                         ((const struct rte_flow_item_ipv6 *)
4723                                          items->mask)->hdr.proto;
4724                         } else {
4725                                 /* Reset for inner layer. */
4726                                 next_protocol = 0xff;
4727                         }
4728                         break;
4729                 case RTE_FLOW_ITEM_TYPE_TCP:
4730                         ret = mlx5_flow_validate_item_tcp
4731                                                 (items, item_flags,
4732                                                  next_protocol,
4733                                                  &nic_tcp_mask,
4734                                                  error);
4735                         if (ret < 0)
4736                                 return ret;
4737                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4738                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4739                         break;
4740                 case RTE_FLOW_ITEM_TYPE_UDP:
4741                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4742                                                           next_protocol,
4743                                                           error);
4744                         if (ret < 0)
4745                                 return ret;
4746                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4747                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4748                         break;
4749                 case RTE_FLOW_ITEM_TYPE_GRE:
4750                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4751                                                           next_protocol, error);
4752                         if (ret < 0)
4753                                 return ret;
4754                         gre_item = items;
4755                         last_item = MLX5_FLOW_LAYER_GRE;
4756                         break;
4757                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4758                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4759                                                             next_protocol,
4760                                                             error);
4761                         if (ret < 0)
4762                                 return ret;
4763                         last_item = MLX5_FLOW_LAYER_NVGRE;
4764                         break;
4765                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4766                         ret = mlx5_flow_validate_item_gre_key
4767                                 (items, item_flags, gre_item, error);
4768                         if (ret < 0)
4769                                 return ret;
4770                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4771                         break;
4772                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4773                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4774                                                             error);
4775                         if (ret < 0)
4776                                 return ret;
4777                         last_item = MLX5_FLOW_LAYER_VXLAN;
4778                         break;
4779                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4780                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4781                                                                 item_flags, dev,
4782                                                                 error);
4783                         if (ret < 0)
4784                                 return ret;
4785                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4786                         break;
4787                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4788                         ret = mlx5_flow_validate_item_geneve(items,
4789                                                              item_flags, dev,
4790                                                              error);
4791                         if (ret < 0)
4792                                 return ret;
4793                         last_item = MLX5_FLOW_LAYER_GENEVE;
4794                         break;
4795                 case RTE_FLOW_ITEM_TYPE_MPLS:
4796                         ret = mlx5_flow_validate_item_mpls(dev, items,
4797                                                            item_flags,
4798                                                            last_item, error);
4799                         if (ret < 0)
4800                                 return ret;
4801                         last_item = MLX5_FLOW_LAYER_MPLS;
4802                         break;
4803
4804                 case RTE_FLOW_ITEM_TYPE_MARK:
4805                         ret = flow_dv_validate_item_mark(dev, items, attr,
4806                                                          error);
4807                         if (ret < 0)
4808                                 return ret;
4809                         last_item = MLX5_FLOW_ITEM_MARK;
4810                         break;
4811                 case RTE_FLOW_ITEM_TYPE_META:
4812                         ret = flow_dv_validate_item_meta(dev, items, attr,
4813                                                          error);
4814                         if (ret < 0)
4815                                 return ret;
4816                         last_item = MLX5_FLOW_ITEM_METADATA;
4817                         break;
4818                 case RTE_FLOW_ITEM_TYPE_ICMP:
4819                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4820                                                            next_protocol,
4821                                                            error);
4822                         if (ret < 0)
4823                                 return ret;
4824                         last_item = MLX5_FLOW_LAYER_ICMP;
4825                         break;
4826                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4827                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4828                                                             next_protocol,
4829                                                             error);
4830                         if (ret < 0)
4831                                 return ret;
4832                         item_ipv6_proto = IPPROTO_ICMPV6;
4833                         last_item = MLX5_FLOW_LAYER_ICMP6;
4834                         break;
4835                 case RTE_FLOW_ITEM_TYPE_TAG:
4836                         ret = flow_dv_validate_item_tag(dev, items,
4837                                                         attr, error);
4838                         if (ret < 0)
4839                                 return ret;
4840                         last_item = MLX5_FLOW_ITEM_TAG;
4841                         break;
4842                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4843                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4844                         break;
4845                 case RTE_FLOW_ITEM_TYPE_GTP:
4846                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4847                                                         error);
4848                         if (ret < 0)
4849                                 return ret;
4850                         last_item = MLX5_FLOW_LAYER_GTP;
4851                         break;
4852                 default:
4853                         return rte_flow_error_set(error, ENOTSUP,
4854                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4855                                                   NULL, "item not supported");
4856                 }
4857                 item_flags |= last_item;
4858         }
4859         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4860                 int type = actions->type;
4861                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4862                         return rte_flow_error_set(error, ENOTSUP,
4863                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4864                                                   actions, "too many actions");
4865                 switch (type) {
4866                 case RTE_FLOW_ACTION_TYPE_VOID:
4867                         break;
4868                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4869                         ret = flow_dv_validate_action_port_id(dev,
4870                                                               action_flags,
4871                                                               actions,
4872                                                               attr,
4873                                                               error);
4874                         if (ret)
4875                                 return ret;
4876                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4877                         ++actions_n;
4878                         break;
4879                 case RTE_FLOW_ACTION_TYPE_FLAG:
4880                         ret = flow_dv_validate_action_flag(dev, action_flags,
4881                                                            attr, error);
4882                         if (ret < 0)
4883                                 return ret;
4884                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4885                                 /* Count all modify-header actions as one. */
4886                                 if (!(action_flags &
4887                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4888                                         ++actions_n;
4889                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4890                                                 MLX5_FLOW_ACTION_MARK_EXT;
4891                         } else {
4892                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4893                                 ++actions_n;
4894                         }
4895                         break;
4896                 case RTE_FLOW_ACTION_TYPE_MARK:
4897                         ret = flow_dv_validate_action_mark(dev, actions,
4898                                                            action_flags,
4899                                                            attr, error);
4900                         if (ret < 0)
4901                                 return ret;
4902                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4903                                 /* Count all modify-header actions as one. */
4904                                 if (!(action_flags &
4905                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4906                                         ++actions_n;
4907                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4908                                                 MLX5_FLOW_ACTION_MARK_EXT;
4909                         } else {
4910                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4911                                 ++actions_n;
4912                         }
4913                         break;
4914                 case RTE_FLOW_ACTION_TYPE_SET_META:
4915                         ret = flow_dv_validate_action_set_meta(dev, actions,
4916                                                                action_flags,
4917                                                                attr, error);
4918                         if (ret < 0)
4919                                 return ret;
4920                         /* Count all modify-header actions as one action. */
4921                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4922                                 ++actions_n;
4923                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4924                         break;
4925                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4926                         ret = flow_dv_validate_action_set_tag(dev, actions,
4927                                                               action_flags,
4928                                                               attr, error);
4929                         if (ret < 0)
4930                                 return ret;
4931                         /* Count all modify-header actions as one action. */
4932                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4933                                 ++actions_n;
4934                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4935                         break;
4936                 case RTE_FLOW_ACTION_TYPE_DROP:
4937                         ret = mlx5_flow_validate_action_drop(action_flags,
4938                                                              attr, error);
4939                         if (ret < 0)
4940                                 return ret;
4941                         action_flags |= MLX5_FLOW_ACTION_DROP;
4942                         ++actions_n;
4943                         break;
4944                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4945                         ret = mlx5_flow_validate_action_queue(actions,
4946                                                               action_flags, dev,
4947                                                               attr, error);
4948                         if (ret < 0)
4949                                 return ret;
4950                         queue_index = ((const struct rte_flow_action_queue *)
4951                                                         (actions->conf))->index;
4952                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4953                         ++actions_n;
4954                         break;
4955                 case RTE_FLOW_ACTION_TYPE_RSS:
4956                         rss = actions->conf;
4957                         ret = mlx5_flow_validate_action_rss(actions,
4958                                                             action_flags, dev,
4959                                                             attr, item_flags,
4960                                                             error);
4961                         if (ret < 0)
4962                                 return ret;
4963                         if (rss != NULL && rss->queue_num)
4964                                 queue_index = rss->queue[0];
4965                         action_flags |= MLX5_FLOW_ACTION_RSS;
4966                         ++actions_n;
4967                         break;
4968                 case RTE_FLOW_ACTION_TYPE_COUNT:
4969                         ret = flow_dv_validate_action_count(dev, error);
4970                         if (ret < 0)
4971                                 return ret;
4972                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4973                         ++actions_n;
4974                         break;
4975                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4976                         if (flow_dv_validate_action_pop_vlan(dev,
4977                                                              action_flags,
4978                                                              actions,
4979                                                              item_flags, attr,
4980                                                              error))
4981                                 return -rte_errno;
4982                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4983                         ++actions_n;
4984                         break;
4985                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4986                         ret = flow_dv_validate_action_push_vlan(dev,
4987                                                                 action_flags,
4988                                                                 vlan_m,
4989                                                                 actions, attr,
4990                                                                 error);
4991                         if (ret < 0)
4992                                 return ret;
4993                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4994                         ++actions_n;
4995                         break;
4996                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4997                         ret = flow_dv_validate_action_set_vlan_pcp
4998                                                 (action_flags, actions, error);
4999                         if (ret < 0)
5000                                 return ret;
5001                         /* Count PCP with push_vlan command. */
5002                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5003                         break;
5004                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5005                         ret = flow_dv_validate_action_set_vlan_vid
5006                                                 (item_flags, action_flags,
5007                                                  actions, error);
5008                         if (ret < 0)
5009                                 return ret;
5010                         /* Count VID with push_vlan command. */
5011                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5012                         break;
5013                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5014                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5015                         ret = flow_dv_validate_action_l2_encap(dev,
5016                                                                action_flags,
5017                                                                actions, attr,
5018                                                                error);
5019                         if (ret < 0)
5020                                 return ret;
5021                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5022                         ++actions_n;
5023                         break;
5024                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5025                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5026                         ret = flow_dv_validate_action_decap(dev, action_flags,
5027                                                             attr, error);
5028                         if (ret < 0)
5029                                 return ret;
5030                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5031                         ++actions_n;
5032                         break;
5033                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5034                         ret = flow_dv_validate_action_raw_encap_decap
5035                                 (dev, NULL, actions->conf, attr, &action_flags,
5036                                  &actions_n, error);
5037                         if (ret < 0)
5038                                 return ret;
5039                         break;
5040                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5041                         decap = actions->conf;
5042                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5043                                 ;
5044                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5045                                 encap = NULL;
5046                                 actions--;
5047                         } else {
5048                                 encap = actions->conf;
5049                         }
5050                         ret = flow_dv_validate_action_raw_encap_decap
5051                                            (dev,
5052                                             decap ? decap : &empty_decap, encap,
5053                                             attr, &action_flags, &actions_n,
5054                                             error);
5055                         if (ret < 0)
5056                                 return ret;
5057                         break;
5058                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5059                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5060                         ret = flow_dv_validate_action_modify_mac(action_flags,
5061                                                                  actions,
5062                                                                  item_flags,
5063                                                                  error);
5064                         if (ret < 0)
5065                                 return ret;
5066                         /* Count all modify-header actions as one action. */
5067                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5068                                 ++actions_n;
5069                         action_flags |= actions->type ==
5070                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5071                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5072                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5073                         break;
5074
5075                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5076                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5077                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5078                                                                   actions,
5079                                                                   item_flags,
5080                                                                   error);
5081                         if (ret < 0)
5082                                 return ret;
5083                         /* Count all modify-header actions as one action. */
5084                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5085                                 ++actions_n;
5086                         action_flags |= actions->type ==
5087                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5088                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5089                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5090                         break;
5091                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5092                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5093                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5094                                                                   actions,
5095                                                                   item_flags,
5096                                                                   error);
5097                         if (ret < 0)
5098                                 return ret;
5099                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5100                                 return rte_flow_error_set(error, ENOTSUP,
5101                                         RTE_FLOW_ERROR_TYPE_ACTION,
5102                                         actions,
5103                                         "Can't change header "
5104                                         "with ICMPv6 proto");
5105                         /* Count all modify-header actions as one action. */
5106                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5107                                 ++actions_n;
5108                         action_flags |= actions->type ==
5109                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5110                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5111                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5112                         break;
5113                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5114                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5115                         ret = flow_dv_validate_action_modify_tp(action_flags,
5116                                                                 actions,
5117                                                                 item_flags,
5118                                                                 error);
5119                         if (ret < 0)
5120                                 return ret;
5121                         /* Count all modify-header actions as one action. */
5122                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5123                                 ++actions_n;
5124                         action_flags |= actions->type ==
5125                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5126                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5127                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5128                         break;
5129                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5130                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5131                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5132                                                                  actions,
5133                                                                  item_flags,
5134                                                                  error);
5135                         if (ret < 0)
5136                                 return ret;
5137                         /* Count all modify-header actions as one action. */
5138                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5139                                 ++actions_n;
5140                         action_flags |= actions->type ==
5141                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5142                                                 MLX5_FLOW_ACTION_SET_TTL :
5143                                                 MLX5_FLOW_ACTION_DEC_TTL;
5144                         break;
5145                 case RTE_FLOW_ACTION_TYPE_JUMP:
5146                         ret = flow_dv_validate_action_jump(actions,
5147                                                            action_flags,
5148                                                            attr, external,
5149                                                            error);
5150                         if (ret)
5151                                 return ret;
5152                         ++actions_n;
5153                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5154                         break;
5155                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5156                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5157                         ret = flow_dv_validate_action_modify_tcp_seq
5158                                                                 (action_flags,
5159                                                                  actions,
5160                                                                  item_flags,
5161                                                                  error);
5162                         if (ret < 0)
5163                                 return ret;
5164                         /* Count all modify-header actions as one action. */
5165                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5166                                 ++actions_n;
5167                         action_flags |= actions->type ==
5168                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5169                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5170                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5171                         break;
5172                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5173                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5174                         ret = flow_dv_validate_action_modify_tcp_ack
5175                                                                 (action_flags,
5176                                                                  actions,
5177                                                                  item_flags,
5178                                                                  error);
5179                         if (ret < 0)
5180                                 return ret;
5181                         /* Count all modify-header actions as one action. */
5182                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5183                                 ++actions_n;
5184                         action_flags |= actions->type ==
5185                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5186                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5187                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5188                         break;
5189                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5190                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5191                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5192                         break;
5193                 case RTE_FLOW_ACTION_TYPE_METER:
5194                         ret = mlx5_flow_validate_action_meter(dev,
5195                                                               action_flags,
5196                                                               actions, attr,
5197                                                               error);
5198                         if (ret < 0)
5199                                 return ret;
5200                         action_flags |= MLX5_FLOW_ACTION_METER;
5201                         ++actions_n;
5202                         break;
5203                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5204                         ret = flow_dv_validate_action_modify_ipv4_dscp
5205                                                          (action_flags,
5206                                                           actions,
5207                                                           item_flags,
5208                                                           error);
5209                         if (ret < 0)
5210                                 return ret;
5211                         /* Count all modify-header actions as one action. */
5212                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5213                                 ++actions_n;
5214                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5215                         break;
5216                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5217                         ret = flow_dv_validate_action_modify_ipv6_dscp
5218                                                                 (action_flags,
5219                                                                  actions,
5220                                                                  item_flags,
5221                                                                  error);
5222                         if (ret < 0)
5223                                 return ret;
5224                         /* Count all modify-header actions as one action. */
5225                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5226                                 ++actions_n;
5227                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5228                         break;
5229                 default:
5230                         return rte_flow_error_set(error, ENOTSUP,
5231                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5232                                                   actions,
5233                                                   "action not supported");
5234                 }
5235         }
5236         /*
5237          * Validate the drop action mutual exclusion with other actions.
5238          * Drop action is mutually-exclusive with any other action, except for
5239          * Count action.
5240          */
5241         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5242             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5243                 return rte_flow_error_set(error, EINVAL,
5244                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5245                                           "Drop action is mutually-exclusive "
5246                                           "with any other action, except for "
5247                                           "Count action");
5248         /* Eswitch has few restrictions on using items and actions */
5249         if (attr->transfer) {
5250                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5251                     action_flags & MLX5_FLOW_ACTION_FLAG)
5252                         return rte_flow_error_set(error, ENOTSUP,
5253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5254                                                   NULL,
5255                                                   "unsupported action FLAG");
5256                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5257                     action_flags & MLX5_FLOW_ACTION_MARK)
5258                         return rte_flow_error_set(error, ENOTSUP,
5259                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5260                                                   NULL,
5261                                                   "unsupported action MARK");
5262                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5263                         return rte_flow_error_set(error, ENOTSUP,
5264                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5265                                                   NULL,
5266                                                   "unsupported action QUEUE");
5267                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5268                         return rte_flow_error_set(error, ENOTSUP,
5269                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5270                                                   NULL,
5271                                                   "unsupported action RSS");
5272                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5273                         return rte_flow_error_set(error, EINVAL,
5274                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5275                                                   actions,
5276                                                   "no fate action is found");
5277         } else {
5278                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5279                         return rte_flow_error_set(error, EINVAL,
5280                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5281                                                   actions,
5282                                                   "no fate action is found");
5283         }
5284         /* Continue validation for Xcap actions.*/
5285         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5286             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5287                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5288                     MLX5_FLOW_XCAP_ACTIONS)
5289                         return rte_flow_error_set(error, ENOTSUP,
5290                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5291                                                   NULL, "encap and decap "
5292                                                   "combination aren't supported");
5293                 if (!attr->transfer && attr->ingress && (action_flags &
5294                                                         MLX5_FLOW_ACTION_ENCAP))
5295                         return rte_flow_error_set(error, ENOTSUP,
5296                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5297                                                   NULL, "encap is not supported"
5298                                                   " for ingress traffic");
5299         }
5300         return 0;
5301 }
5302
5303 /**
5304  * Internal preparation function. Allocates the DV flow size,
5305  * this size is constant.
5306  *
5307  * @param[in] dev
5308  *   Pointer to the rte_eth_dev structure.
5309  * @param[in] attr
5310  *   Pointer to the flow attributes.
5311  * @param[in] items
5312  *   Pointer to the list of items.
5313  * @param[in] actions
5314  *   Pointer to the list of actions.
5315  * @param[out] error
5316  *   Pointer to the error structure.
5317  *
5318  * @return
5319  *   Pointer to mlx5_flow object on success,
5320  *   otherwise NULL and rte_errno is set.
5321  */
5322 static struct mlx5_flow *
5323 flow_dv_prepare(struct rte_eth_dev *dev,
5324                 const struct rte_flow_attr *attr __rte_unused,
5325                 const struct rte_flow_item items[] __rte_unused,
5326                 const struct rte_flow_action actions[] __rte_unused,
5327                 struct rte_flow_error *error)
5328 {
5329         size_t size = sizeof(struct mlx5_flow_handle);
5330         struct mlx5_flow *dev_flow;
5331         struct mlx5_flow_handle *dev_handle;
5332         struct mlx5_priv *priv = dev->data->dev_private;
5333
5334         /* In case of corrupting the memory. */
5335         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5336                 rte_flow_error_set(error, ENOSPC,
5337                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5338                                    "not free temporary device flow");
5339                 return NULL;
5340         }
5341         dev_handle = rte_calloc(__func__, 1, size, 0);
5342         if (!dev_handle) {
5343                 rte_flow_error_set(error, ENOMEM,
5344                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5345                                    "not enough memory to create flow handle");
5346                 return NULL;
5347         }
5348         /* No multi-thread supporting. */
5349         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5350         dev_flow->handle = dev_handle;
5351         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5352         /*
5353          * The matching value needs to be cleared to 0 before using. In the
5354          * past, it will be automatically cleared when using rte_*alloc
5355          * API. The time consumption will be almost the same as before.
5356          */
5357         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5358         dev_flow->ingress = attr->ingress;
5359         dev_flow->dv.transfer = attr->transfer;
5360         return dev_flow;
5361 }
5362
5363 #ifdef RTE_LIBRTE_MLX5_DEBUG
5364 /**
5365  * Sanity check for match mask and value. Similar to check_valid_spec() in
5366  * kernel driver. If unmasked bit is present in value, it returns failure.
5367  *
5368  * @param match_mask
5369  *   pointer to match mask buffer.
5370  * @param match_value
5371  *   pointer to match value buffer.
5372  *
5373  * @return
5374  *   0 if valid, -EINVAL otherwise.
5375  */
5376 static int
5377 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5378 {
5379         uint8_t *m = match_mask;
5380         uint8_t *v = match_value;
5381         unsigned int i;
5382
5383         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5384                 if (v[i] & ~m[i]) {
5385                         DRV_LOG(ERR,
5386                                 "match_value differs from match_criteria"
5387                                 " %p[%u] != %p[%u]",
5388                                 match_value, i, match_mask, i);
5389                         return -EINVAL;
5390                 }
5391         }
5392         return 0;
5393 }
5394 #endif
5395
5396 /**
5397  * Add Ethernet item to matcher and to the value.
5398  *
5399  * @param[in, out] matcher
5400  *   Flow matcher.
5401  * @param[in, out] key
5402  *   Flow matcher value.
5403  * @param[in] item
5404  *   Flow pattern to translate.
5405  * @param[in] inner
5406  *   Item is inner pattern.
5407  */
5408 static void
5409 flow_dv_translate_item_eth(void *matcher, void *key,
5410                            const struct rte_flow_item *item, int inner)
5411 {
5412         const struct rte_flow_item_eth *eth_m = item->mask;
5413         const struct rte_flow_item_eth *eth_v = item->spec;
5414         const struct rte_flow_item_eth nic_mask = {
5415                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5416                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5417                 .type = RTE_BE16(0xffff),
5418         };
5419         void *headers_m;
5420         void *headers_v;
5421         char *l24_v;
5422         unsigned int i;
5423
5424         if (!eth_v)
5425                 return;
5426         if (!eth_m)
5427                 eth_m = &nic_mask;
5428         if (inner) {
5429                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5430                                          inner_headers);
5431                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5432         } else {
5433                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5434                                          outer_headers);
5435                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5436         }
5437         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5438                &eth_m->dst, sizeof(eth_m->dst));
5439         /* The value must be in the range of the mask. */
5440         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5441         for (i = 0; i < sizeof(eth_m->dst); ++i)
5442                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5443         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5444                &eth_m->src, sizeof(eth_m->src));
5445         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5446         /* The value must be in the range of the mask. */
5447         for (i = 0; i < sizeof(eth_m->dst); ++i)
5448                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5449         if (eth_v->type) {
5450                 /* When ethertype is present set mask for tagged VLAN. */
5451                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5452                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5453                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5454                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5455                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5456                                  1);
5457                         /* Return here to avoid setting match on ethertype. */
5458                         return;
5459                 }
5460         }
5461         /*
5462          * HW supports match on one Ethertype, the Ethertype following the last
5463          * VLAN tag of the packet (see PRM).
5464          * Set match on ethertype only if ETH header is not followed by VLAN.
5465          */
5466         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5467                  rte_be_to_cpu_16(eth_m->type));
5468         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5469         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5470 }
5471
5472 /**
5473  * Add VLAN item to matcher and to the value.
5474  *
5475  * @param[in, out] dev_flow
5476  *   Flow descriptor.
5477  * @param[in, out] matcher
5478  *   Flow matcher.
5479  * @param[in, out] key
5480  *   Flow matcher value.
5481  * @param[in] item
5482  *   Flow pattern to translate.
5483  * @param[in] inner
5484  *   Item is inner pattern.
5485  */
5486 static void
5487 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5488                             void *matcher, void *key,
5489                             const struct rte_flow_item *item,
5490                             int inner)
5491 {
5492         const struct rte_flow_item_vlan *vlan_m = item->mask;
5493         const struct rte_flow_item_vlan *vlan_v = item->spec;
5494         void *headers_m;
5495         void *headers_v;
5496         uint16_t tci_m;
5497         uint16_t tci_v;
5498
5499         if (!vlan_v)
5500                 return;
5501         if (!vlan_m)
5502                 vlan_m = &rte_flow_item_vlan_mask;
5503         if (inner) {
5504                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5505                                          inner_headers);
5506                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5507         } else {
5508                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5509                                          outer_headers);
5510                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5511                 /*
5512                  * This is workaround, masks are not supported,
5513                  * and pre-validated.
5514                  */
5515                 dev_flow->handle->vf_vlan.tag =
5516                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5517         }
5518         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5519         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5520         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5521         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5522         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5523         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5524         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5525         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5526         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5527         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5528         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5529                  rte_be_to_cpu_16(vlan_m->inner_type));
5530         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5531                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5532 }
5533
5534 /**
5535  * Add IPV4 item to matcher and to the value.
5536  *
5537  * @param[in, out] matcher
5538  *   Flow matcher.
5539  * @param[in, out] key
5540  *   Flow matcher value.
5541  * @param[in] item
5542  *   Flow pattern to translate.
5543  * @param[in] item_flags
5544  *   Bit-fields that holds the items detected until now.
5545  * @param[in] inner
5546  *   Item is inner pattern.
5547  * @param[in] group
5548  *   The group to insert the rule.
5549  */
5550 static void
5551 flow_dv_translate_item_ipv4(void *matcher, void *key,
5552                             const struct rte_flow_item *item,
5553                             const uint64_t item_flags,
5554                             int inner, uint32_t group)
5555 {
5556         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5557         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5558         const struct rte_flow_item_ipv4 nic_mask = {
5559                 .hdr = {
5560                         .src_addr = RTE_BE32(0xffffffff),
5561                         .dst_addr = RTE_BE32(0xffffffff),
5562                         .type_of_service = 0xff,
5563                         .next_proto_id = 0xff,
5564                         .time_to_live = 0xff,
5565                 },
5566         };
5567         void *headers_m;
5568         void *headers_v;
5569         char *l24_m;
5570         char *l24_v;
5571         uint8_t tos;
5572
5573         if (inner) {
5574                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5575                                          inner_headers);
5576                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5577         } else {
5578                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5579                                          outer_headers);
5580                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5581         }
5582         if (group == 0)
5583                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5584         else
5585                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5586         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5587         /*
5588          * On outer header (which must contains L2), or inner header with L2,
5589          * set cvlan_tag mask bit to mark this packet as untagged.
5590          * This should be done even if item->spec is empty.
5591          */
5592         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5593                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5594         if (!ipv4_v)
5595                 return;
5596         if (!ipv4_m)
5597                 ipv4_m = &nic_mask;
5598         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5599                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5600         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5601                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5602         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5603         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5604         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5605                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5606         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5607                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5608         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5609         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5610         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5611         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5612                  ipv4_m->hdr.type_of_service);
5613         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5614         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5615                  ipv4_m->hdr.type_of_service >> 2);
5616         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5617         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5618                  ipv4_m->hdr.next_proto_id);
5619         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5620                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5621         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5622                  ipv4_m->hdr.time_to_live);
5623         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5624                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5625 }
5626
5627 /**
5628  * Add IPV6 item to matcher and to the value.
5629  *
5630  * @param[in, out] matcher
5631  *   Flow matcher.
5632  * @param[in, out] key
5633  *   Flow matcher value.
5634  * @param[in] item
5635  *   Flow pattern to translate.
5636  * @param[in] item_flags
5637  *   Bit-fields that holds the items detected until now.
5638  * @param[in] inner
5639  *   Item is inner pattern.
5640  * @param[in] group
5641  *   The group to insert the rule.
5642  */
5643 static void
5644 flow_dv_translate_item_ipv6(void *matcher, void *key,
5645                             const struct rte_flow_item *item,
5646                             const uint64_t item_flags,
5647                             int inner, uint32_t group)
5648 {
5649         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5650         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5651         const struct rte_flow_item_ipv6 nic_mask = {
5652                 .hdr = {
5653                         .src_addr =
5654                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5655                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5656                         .dst_addr =
5657                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5658                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5659                         .vtc_flow = RTE_BE32(0xffffffff),
5660                         .proto = 0xff,
5661                         .hop_limits = 0xff,
5662                 },
5663         };
5664         void *headers_m;
5665         void *headers_v;
5666         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5667         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5668         char *l24_m;
5669         char *l24_v;
5670         uint32_t vtc_m;
5671         uint32_t vtc_v;
5672         int i;
5673         int size;
5674
5675         if (inner) {
5676                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5677                                          inner_headers);
5678                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5679         } else {
5680                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5681                                          outer_headers);
5682                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5683         }
5684         if (group == 0)
5685                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5686         else
5687                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5689         /*
5690          * On outer header (which must contains L2), or inner header with L2,
5691          * set cvlan_tag mask bit to mark this packet as untagged.
5692          * This should be done even if item->spec is empty.
5693          */
5694         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5695                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5696         if (!ipv6_v)
5697                 return;
5698         if (!ipv6_m)
5699                 ipv6_m = &nic_mask;
5700         size = sizeof(ipv6_m->hdr.dst_addr);
5701         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5702                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5703         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5704                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5705         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5706         for (i = 0; i < size; ++i)
5707                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5708         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5709                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5710         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5711                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5712         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5713         for (i = 0; i < size; ++i)
5714                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5715         /* TOS. */
5716         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5717         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5718         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5719         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5720         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5721         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5722         /* Label. */
5723         if (inner) {
5724                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5725                          vtc_m);
5726                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5727                          vtc_v);
5728         } else {
5729                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5730                          vtc_m);
5731                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5732                          vtc_v);
5733         }
5734         /* Protocol. */
5735         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5736                  ipv6_m->hdr.proto);
5737         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5738                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5739         /* Hop limit. */
5740         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5741                  ipv6_m->hdr.hop_limits);
5742         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5743                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5744 }
5745
5746 /**
5747  * Add TCP item to matcher and to the value.
5748  *
5749  * @param[in, out] matcher
5750  *   Flow matcher.
5751  * @param[in, out] key
5752  *   Flow matcher value.
5753  * @param[in] item
5754  *   Flow pattern to translate.
5755  * @param[in] inner
5756  *   Item is inner pattern.
5757  */
5758 static void
5759 flow_dv_translate_item_tcp(void *matcher, void *key,
5760                            const struct rte_flow_item *item,
5761                            int inner)
5762 {
5763         const struct rte_flow_item_tcp *tcp_m = item->mask;
5764         const struct rte_flow_item_tcp *tcp_v = item->spec;
5765         void *headers_m;
5766         void *headers_v;
5767
5768         if (inner) {
5769                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5770                                          inner_headers);
5771                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5772         } else {
5773                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5774                                          outer_headers);
5775                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5776         }
5777         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5778         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5779         if (!tcp_v)
5780                 return;
5781         if (!tcp_m)
5782                 tcp_m = &rte_flow_item_tcp_mask;
5783         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5784                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5785         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5786                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5787         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5788                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5789         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5790                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5791         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5792                  tcp_m->hdr.tcp_flags);
5793         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5794                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5795 }
5796
5797 /**
5798  * Add UDP item to matcher and to the value.
5799  *
5800  * @param[in, out] matcher
5801  *   Flow matcher.
5802  * @param[in, out] key
5803  *   Flow matcher value.
5804  * @param[in] item
5805  *   Flow pattern to translate.
5806  * @param[in] inner
5807  *   Item is inner pattern.
5808  */
5809 static void
5810 flow_dv_translate_item_udp(void *matcher, void *key,
5811                            const struct rte_flow_item *item,
5812                            int inner)
5813 {
5814         const struct rte_flow_item_udp *udp_m = item->mask;
5815         const struct rte_flow_item_udp *udp_v = item->spec;
5816         void *headers_m;
5817         void *headers_v;
5818
5819         if (inner) {
5820                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5821                                          inner_headers);
5822                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5823         } else {
5824                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5825                                          outer_headers);
5826                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5827         }
5828         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5829         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5830         if (!udp_v)
5831                 return;
5832         if (!udp_m)
5833                 udp_m = &rte_flow_item_udp_mask;
5834         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5835                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5836         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5837                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5838         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5839                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5840         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5841                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5842 }
5843
5844 /**
5845  * Add GRE optional Key item to matcher and to the value.
5846  *
5847  * @param[in, out] matcher
5848  *   Flow matcher.
5849  * @param[in, out] key
5850  *   Flow matcher value.
5851  * @param[in] item
5852  *   Flow pattern to translate.
5853  * @param[in] inner
5854  *   Item is inner pattern.
5855  */
5856 static void
5857 flow_dv_translate_item_gre_key(void *matcher, void *key,
5858                                    const struct rte_flow_item *item)
5859 {
5860         const rte_be32_t *key_m = item->mask;
5861         const rte_be32_t *key_v = item->spec;
5862         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5863         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5864         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5865
5866         /* GRE K bit must be on and should already be validated */
5867         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5868         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5869         if (!key_v)
5870                 return;
5871         if (!key_m)
5872                 key_m = &gre_key_default_mask;
5873         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5874                  rte_be_to_cpu_32(*key_m) >> 8);
5875         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5876                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5877         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5878                  rte_be_to_cpu_32(*key_m) & 0xFF);
5879         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5880                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5881 }
5882
5883 /**
5884  * Add GRE item to matcher and to the value.
5885  *
5886  * @param[in, out] matcher
5887  *   Flow matcher.
5888  * @param[in, out] key
5889  *   Flow matcher value.
5890  * @param[in] item
5891  *   Flow pattern to translate.
5892  * @param[in] inner
5893  *   Item is inner pattern.
5894  */
5895 static void
5896 flow_dv_translate_item_gre(void *matcher, void *key,
5897                            const struct rte_flow_item *item,
5898                            int inner)
5899 {
5900         const struct rte_flow_item_gre *gre_m = item->mask;
5901         const struct rte_flow_item_gre *gre_v = item->spec;
5902         void *headers_m;
5903         void *headers_v;
5904         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5905         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5906         struct {
5907                 union {
5908                         __extension__
5909                         struct {
5910                                 uint16_t version:3;
5911                                 uint16_t rsvd0:9;
5912                                 uint16_t s_present:1;
5913                                 uint16_t k_present:1;
5914                                 uint16_t rsvd_bit1:1;
5915                                 uint16_t c_present:1;
5916                         };
5917                         uint16_t value;
5918                 };
5919         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5920
5921         if (inner) {
5922                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5923                                          inner_headers);
5924                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5925         } else {
5926                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5927                                          outer_headers);
5928                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5929         }
5930         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5931         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5932         if (!gre_v)
5933                 return;
5934         if (!gre_m)
5935                 gre_m = &rte_flow_item_gre_mask;
5936         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5937                  rte_be_to_cpu_16(gre_m->protocol));
5938         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5939                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5940         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5941         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5942         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5943                  gre_crks_rsvd0_ver_m.c_present);
5944         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5945                  gre_crks_rsvd0_ver_v.c_present &
5946                  gre_crks_rsvd0_ver_m.c_present);
5947         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5948                  gre_crks_rsvd0_ver_m.k_present);
5949         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5950                  gre_crks_rsvd0_ver_v.k_present &
5951                  gre_crks_rsvd0_ver_m.k_present);
5952         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5953                  gre_crks_rsvd0_ver_m.s_present);
5954         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5955                  gre_crks_rsvd0_ver_v.s_present &
5956                  gre_crks_rsvd0_ver_m.s_present);
5957 }
5958
5959 /**
5960  * Add NVGRE item to matcher and to the value.
5961  *
5962  * @param[in, out] matcher
5963  *   Flow matcher.
5964  * @param[in, out] key
5965  *   Flow matcher value.
5966  * @param[in] item
5967  *   Flow pattern to translate.
5968  * @param[in] inner
5969  *   Item is inner pattern.
5970  */
5971 static void
5972 flow_dv_translate_item_nvgre(void *matcher, void *key,
5973                              const struct rte_flow_item *item,
5974                              int inner)
5975 {
5976         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5977         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5978         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5979         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5980         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5981         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5982         char *gre_key_m;
5983         char *gre_key_v;
5984         int size;
5985         int i;
5986
5987         /* For NVGRE, GRE header fields must be set with defined values. */
5988         const struct rte_flow_item_gre gre_spec = {
5989                 .c_rsvd0_ver = RTE_BE16(0x2000),
5990                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5991         };
5992         const struct rte_flow_item_gre gre_mask = {
5993                 .c_rsvd0_ver = RTE_BE16(0xB000),
5994                 .protocol = RTE_BE16(UINT16_MAX),
5995         };
5996         const struct rte_flow_item gre_item = {
5997                 .spec = &gre_spec,
5998                 .mask = &gre_mask,
5999                 .last = NULL,
6000         };
6001         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6002         if (!nvgre_v)
6003                 return;
6004         if (!nvgre_m)
6005                 nvgre_m = &rte_flow_item_nvgre_mask;
6006         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6007         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6008         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6009         memcpy(gre_key_m, tni_flow_id_m, size);
6010         for (i = 0; i < size; ++i)
6011                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6012 }
6013
6014 /**
6015  * Add VXLAN item to matcher and to the value.
6016  *
6017  * @param[in, out] matcher
6018  *   Flow matcher.
6019  * @param[in, out] key
6020  *   Flow matcher value.
6021  * @param[in] item
6022  *   Flow pattern to translate.
6023  * @param[in] inner
6024  *   Item is inner pattern.
6025  */
6026 static void
6027 flow_dv_translate_item_vxlan(void *matcher, void *key,
6028                              const struct rte_flow_item *item,
6029                              int inner)
6030 {
6031         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6032         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6033         void *headers_m;
6034         void *headers_v;
6035         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6036         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6037         char *vni_m;
6038         char *vni_v;
6039         uint16_t dport;
6040         int size;
6041         int i;
6042
6043         if (inner) {
6044                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6045                                          inner_headers);
6046                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6047         } else {
6048                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6049                                          outer_headers);
6050                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6051         }
6052         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6053                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6054         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6055                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6056                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6057         }
6058         if (!vxlan_v)
6059                 return;
6060         if (!vxlan_m)
6061                 vxlan_m = &rte_flow_item_vxlan_mask;
6062         size = sizeof(vxlan_m->vni);
6063         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6064         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6065         memcpy(vni_m, vxlan_m->vni, size);
6066         for (i = 0; i < size; ++i)
6067                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6068 }
6069
6070 /**
6071  * Add VXLAN-GPE item to matcher and to the value.
6072  *
6073  * @param[in, out] matcher
6074  *   Flow matcher.
6075  * @param[in, out] key
6076  *   Flow matcher value.
6077  * @param[in] item
6078  *   Flow pattern to translate.
6079  * @param[in] inner
6080  *   Item is inner pattern.
6081  */
6082
6083 static void
6084 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6085                                  const struct rte_flow_item *item, int inner)
6086 {
6087         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6088         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6089         void *headers_m;
6090         void *headers_v;
6091         void *misc_m =
6092                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6093         void *misc_v =
6094                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6095         char *vni_m;
6096         char *vni_v;
6097         uint16_t dport;
6098         int size;
6099         int i;
6100         uint8_t flags_m = 0xff;
6101         uint8_t flags_v = 0xc;
6102
6103         if (inner) {
6104                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6105                                          inner_headers);
6106                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6107         } else {
6108                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6109                                          outer_headers);
6110                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6111         }
6112         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6113                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6114         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6115                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6116                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6117         }
6118         if (!vxlan_v)
6119                 return;
6120         if (!vxlan_m)
6121                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6122         size = sizeof(vxlan_m->vni);
6123         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6124         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6125         memcpy(vni_m, vxlan_m->vni, size);
6126         for (i = 0; i < size; ++i)
6127                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6128         if (vxlan_m->flags) {
6129                 flags_m = vxlan_m->flags;
6130                 flags_v = vxlan_v->flags;
6131         }
6132         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6133         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6134         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6135                  vxlan_m->protocol);
6136         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6137                  vxlan_v->protocol);
6138 }
6139
6140 /**
6141  * Add Geneve item to matcher and to the value.
6142  *
6143  * @param[in, out] matcher
6144  *   Flow matcher.
6145  * @param[in, out] key
6146  *   Flow matcher value.
6147  * @param[in] item
6148  *   Flow pattern to translate.
6149  * @param[in] inner
6150  *   Item is inner pattern.
6151  */
6152
6153 static void
6154 flow_dv_translate_item_geneve(void *matcher, void *key,
6155                               const struct rte_flow_item *item, int inner)
6156 {
6157         const struct rte_flow_item_geneve *geneve_m = item->mask;
6158         const struct rte_flow_item_geneve *geneve_v = item->spec;
6159         void *headers_m;
6160         void *headers_v;
6161         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6162         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6163         uint16_t dport;
6164         uint16_t gbhdr_m;
6165         uint16_t gbhdr_v;
6166         char *vni_m;
6167         char *vni_v;
6168         size_t size, i;
6169
6170         if (inner) {
6171                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6172                                          inner_headers);
6173                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6174         } else {
6175                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6176                                          outer_headers);
6177                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6178         }
6179         dport = MLX5_UDP_PORT_GENEVE;
6180         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6181                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6182                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6183         }
6184         if (!geneve_v)
6185                 return;
6186         if (!geneve_m)
6187                 geneve_m = &rte_flow_item_geneve_mask;
6188         size = sizeof(geneve_m->vni);
6189         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6190         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6191         memcpy(vni_m, geneve_m->vni, size);
6192         for (i = 0; i < size; ++i)
6193                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6194         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6195                  rte_be_to_cpu_16(geneve_m->protocol));
6196         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6197                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6198         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6199         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6200         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6201                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6202         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6203                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6204         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6205                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6206         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6207                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6208                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6209 }
6210
6211 /**
6212  * Add MPLS item to matcher and to the value.
6213  *
6214  * @param[in, out] matcher
6215  *   Flow matcher.
6216  * @param[in, out] key
6217  *   Flow matcher value.
6218  * @param[in] item
6219  *   Flow pattern to translate.
6220  * @param[in] prev_layer
6221  *   The protocol layer indicated in previous item.
6222  * @param[in] inner
6223  *   Item is inner pattern.
6224  */
6225 static void
6226 flow_dv_translate_item_mpls(void *matcher, void *key,
6227                             const struct rte_flow_item *item,
6228                             uint64_t prev_layer,
6229                             int inner)
6230 {
6231         const uint32_t *in_mpls_m = item->mask;
6232         const uint32_t *in_mpls_v = item->spec;
6233         uint32_t *out_mpls_m = 0;
6234         uint32_t *out_mpls_v = 0;
6235         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6236         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6237         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6238                                      misc_parameters_2);
6239         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6240         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6241         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6242
6243         switch (prev_layer) {
6244         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6245                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6246                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6247                          MLX5_UDP_PORT_MPLS);
6248                 break;
6249         case MLX5_FLOW_LAYER_GRE:
6250                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6251                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6252                          RTE_ETHER_TYPE_MPLS);
6253                 break;
6254         default:
6255                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6257                          IPPROTO_MPLS);
6258                 break;
6259         }
6260         if (!in_mpls_v)
6261                 return;
6262         if (!in_mpls_m)
6263                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6264         switch (prev_layer) {
6265         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6266                 out_mpls_m =
6267                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6268                                                  outer_first_mpls_over_udp);
6269                 out_mpls_v =
6270                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6271                                                  outer_first_mpls_over_udp);
6272                 break;
6273         case MLX5_FLOW_LAYER_GRE:
6274                 out_mpls_m =
6275                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6276                                                  outer_first_mpls_over_gre);
6277                 out_mpls_v =
6278                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6279                                                  outer_first_mpls_over_gre);
6280                 break;
6281         default:
6282                 /* Inner MPLS not over GRE is not supported. */
6283                 if (!inner) {
6284                         out_mpls_m =
6285                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6286                                                          misc2_m,
6287                                                          outer_first_mpls);
6288                         out_mpls_v =
6289                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6290                                                          misc2_v,
6291                                                          outer_first_mpls);
6292                 }
6293                 break;
6294         }
6295         if (out_mpls_m && out_mpls_v) {
6296                 *out_mpls_m = *in_mpls_m;
6297                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6298         }
6299 }
6300
6301 /**
6302  * Add metadata register item to matcher
6303  *
6304  * @param[in, out] matcher
6305  *   Flow matcher.
6306  * @param[in, out] key
6307  *   Flow matcher value.
6308  * @param[in] reg_type
6309  *   Type of device metadata register
6310  * @param[in] value
6311  *   Register value
6312  * @param[in] mask
6313  *   Register mask
6314  */
6315 static void
6316 flow_dv_match_meta_reg(void *matcher, void *key,
6317                        enum modify_reg reg_type,
6318                        uint32_t data, uint32_t mask)
6319 {
6320         void *misc2_m =
6321                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6322         void *misc2_v =
6323                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6324         uint32_t temp;
6325
6326         data &= mask;
6327         switch (reg_type) {
6328         case REG_A:
6329                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6330                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6331                 break;
6332         case REG_B:
6333                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6334                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6335                 break;
6336         case REG_C_0:
6337                 /*
6338                  * The metadata register C0 field might be divided into
6339                  * source vport index and META item value, we should set
6340                  * this field according to specified mask, not as whole one.
6341                  */
6342                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6343                 temp |= mask;
6344                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6345                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6346                 temp &= ~mask;
6347                 temp |= data;
6348                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6349                 break;
6350         case REG_C_1:
6351                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6352                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6353                 break;
6354         case REG_C_2:
6355                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6356                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6357                 break;
6358         case REG_C_3:
6359                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6360                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6361                 break;
6362         case REG_C_4:
6363                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6364                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6365                 break;
6366         case REG_C_5:
6367                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6368                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6369                 break;
6370         case REG_C_6:
6371                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6372                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6373                 break;
6374         case REG_C_7:
6375                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6376                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6377                 break;
6378         default:
6379                 MLX5_ASSERT(false);
6380                 break;
6381         }
6382 }
6383
6384 /**
6385  * Add MARK item to matcher
6386  *
6387  * @param[in] dev
6388  *   The device to configure through.
6389  * @param[in, out] matcher
6390  *   Flow matcher.
6391  * @param[in, out] key
6392  *   Flow matcher value.
6393  * @param[in] item
6394  *   Flow pattern to translate.
6395  */
6396 static void
6397 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6398                             void *matcher, void *key,
6399                             const struct rte_flow_item *item)
6400 {
6401         struct mlx5_priv *priv = dev->data->dev_private;
6402         const struct rte_flow_item_mark *mark;
6403         uint32_t value;
6404         uint32_t mask;
6405
6406         mark = item->mask ? (const void *)item->mask :
6407                             &rte_flow_item_mark_mask;
6408         mask = mark->id & priv->sh->dv_mark_mask;
6409         mark = (const void *)item->spec;
6410         MLX5_ASSERT(mark);
6411         value = mark->id & priv->sh->dv_mark_mask & mask;
6412         if (mask) {
6413                 enum modify_reg reg;
6414
6415                 /* Get the metadata register index for the mark. */
6416                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6417                 MLX5_ASSERT(reg > 0);
6418                 if (reg == REG_C_0) {
6419                         struct mlx5_priv *priv = dev->data->dev_private;
6420                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6421                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6422
6423                         mask &= msk_c0;
6424                         mask <<= shl_c0;
6425                         value <<= shl_c0;
6426                 }
6427                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6428         }
6429 }
6430
6431 /**
6432  * Add META item to matcher
6433  *
6434  * @param[in] dev
6435  *   The devich to configure through.
6436  * @param[in, out] matcher
6437  *   Flow matcher.
6438  * @param[in, out] key
6439  *   Flow matcher value.
6440  * @param[in] attr
6441  *   Attributes of flow that includes this item.
6442  * @param[in] item
6443  *   Flow pattern to translate.
6444  */
6445 static void
6446 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6447                             void *matcher, void *key,
6448                             const struct rte_flow_attr *attr,
6449                             const struct rte_flow_item *item)
6450 {
6451         const struct rte_flow_item_meta *meta_m;
6452         const struct rte_flow_item_meta *meta_v;
6453
6454         meta_m = (const void *)item->mask;
6455         if (!meta_m)
6456                 meta_m = &rte_flow_item_meta_mask;
6457         meta_v = (const void *)item->spec;
6458         if (meta_v) {
6459                 int reg;
6460                 uint32_t value = meta_v->data;
6461                 uint32_t mask = meta_m->data;
6462
6463                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6464                 if (reg < 0)
6465                         return;
6466                 /*
6467                  * In datapath code there is no endianness
6468                  * coversions for perfromance reasons, all
6469                  * pattern conversions are done in rte_flow.
6470                  */
6471                 value = rte_cpu_to_be_32(value);
6472                 mask = rte_cpu_to_be_32(mask);
6473                 if (reg == REG_C_0) {
6474                         struct mlx5_priv *priv = dev->data->dev_private;
6475                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6476                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6477 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6478                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6479
6480                         value >>= shr_c0;
6481                         mask >>= shr_c0;
6482 #endif
6483                         value <<= shl_c0;
6484                         mask <<= shl_c0;
6485                         MLX5_ASSERT(msk_c0);
6486                         MLX5_ASSERT(!(~msk_c0 & mask));
6487                 }
6488                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6489         }
6490 }
6491
6492 /**
6493  * Add vport metadata Reg C0 item to matcher
6494  *
6495  * @param[in, out] matcher
6496  *   Flow matcher.
6497  * @param[in, out] key
6498  *   Flow matcher value.
6499  * @param[in] reg
6500  *   Flow pattern to translate.
6501  */
6502 static void
6503 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6504                                   uint32_t value, uint32_t mask)
6505 {
6506         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6507 }
6508
6509 /**
6510  * Add tag item to matcher
6511  *
6512  * @param[in] dev
6513  *   The devich to configure through.
6514  * @param[in, out] matcher
6515  *   Flow matcher.
6516  * @param[in, out] key
6517  *   Flow matcher value.
6518  * @param[in] item
6519  *   Flow pattern to translate.
6520  */
6521 static void
6522 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6523                                 void *matcher, void *key,
6524                                 const struct rte_flow_item *item)
6525 {
6526         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6527         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6528         uint32_t mask, value;
6529
6530         MLX5_ASSERT(tag_v);
6531         value = tag_v->data;
6532         mask = tag_m ? tag_m->data : UINT32_MAX;
6533         if (tag_v->id == REG_C_0) {
6534                 struct mlx5_priv *priv = dev->data->dev_private;
6535                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6536                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6537
6538                 mask &= msk_c0;
6539                 mask <<= shl_c0;
6540                 value <<= shl_c0;
6541         }
6542         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6543 }
6544
6545 /**
6546  * Add TAG item to matcher
6547  *
6548  * @param[in] dev
6549  *   The devich to configure through.
6550  * @param[in, out] matcher
6551  *   Flow matcher.
6552  * @param[in, out] key
6553  *   Flow matcher value.
6554  * @param[in] item
6555  *   Flow pattern to translate.
6556  */
6557 static void
6558 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6559                            void *matcher, void *key,
6560                            const struct rte_flow_item *item)
6561 {
6562         const struct rte_flow_item_tag *tag_v = item->spec;
6563         const struct rte_flow_item_tag *tag_m = item->mask;
6564         enum modify_reg reg;
6565
6566         MLX5_ASSERT(tag_v);
6567         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6568         /* Get the metadata register index for the tag. */
6569         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6570         MLX5_ASSERT(reg > 0);
6571         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6572 }
6573
6574 /**
6575  * Add source vport match to the specified matcher.
6576  *
6577  * @param[in, out] matcher
6578  *   Flow matcher.
6579  * @param[in, out] key
6580  *   Flow matcher value.
6581  * @param[in] port
6582  *   Source vport value to match
6583  * @param[in] mask
6584  *   Mask
6585  */
6586 static void
6587 flow_dv_translate_item_source_vport(void *matcher, void *key,
6588                                     int16_t port, uint16_t mask)
6589 {
6590         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6591         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6592
6593         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6594         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6595 }
6596
6597 /**
6598  * Translate port-id item to eswitch match on  port-id.
6599  *
6600  * @param[in] dev
6601  *   The devich to configure through.
6602  * @param[in, out] matcher
6603  *   Flow matcher.
6604  * @param[in, out] key
6605  *   Flow matcher value.
6606  * @param[in] item
6607  *   Flow pattern to translate.
6608  *
6609  * @return
6610  *   0 on success, a negative errno value otherwise.
6611  */
6612 static int
6613 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6614                                void *key, const struct rte_flow_item *item)
6615 {
6616         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6617         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6618         struct mlx5_priv *priv;
6619         uint16_t mask, id;
6620
6621         mask = pid_m ? pid_m->id : 0xffff;
6622         id = pid_v ? pid_v->id : dev->data->port_id;
6623         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6624         if (!priv)
6625                 return -rte_errno;
6626         /* Translate to vport field or to metadata, depending on mode. */
6627         if (priv->vport_meta_mask)
6628                 flow_dv_translate_item_meta_vport(matcher, key,
6629                                                   priv->vport_meta_tag,
6630                                                   priv->vport_meta_mask);
6631         else
6632                 flow_dv_translate_item_source_vport(matcher, key,
6633                                                     priv->vport_id, mask);
6634         return 0;
6635 }
6636
6637 /**
6638  * Add ICMP6 item to matcher and to the value.
6639  *
6640  * @param[in, out] matcher
6641  *   Flow matcher.
6642  * @param[in, out] key
6643  *   Flow matcher value.
6644  * @param[in] item
6645  *   Flow pattern to translate.
6646  * @param[in] inner
6647  *   Item is inner pattern.
6648  */
6649 static void
6650 flow_dv_translate_item_icmp6(void *matcher, void *key,
6651                               const struct rte_flow_item *item,
6652                               int inner)
6653 {
6654         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6655         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6656         void *headers_m;
6657         void *headers_v;
6658         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6659                                      misc_parameters_3);
6660         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6661         if (inner) {
6662                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6663                                          inner_headers);
6664                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6665         } else {
6666                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667                                          outer_headers);
6668                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6669         }
6670         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6671         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6672         if (!icmp6_v)
6673                 return;
6674         if (!icmp6_m)
6675                 icmp6_m = &rte_flow_item_icmp6_mask;
6676         /*
6677          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6678          * If only the protocol is specified, no need to match the frag.
6679          */
6680         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6681         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6682         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6683         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6684                  icmp6_v->type & icmp6_m->type);
6685         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6686         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6687                  icmp6_v->code & icmp6_m->code);
6688 }
6689
6690 /**
6691  * Add ICMP item to matcher and to the value.
6692  *
6693  * @param[in, out] matcher
6694  *   Flow matcher.
6695  * @param[in, out] key
6696  *   Flow matcher value.
6697  * @param[in] item
6698  *   Flow pattern to translate.
6699  * @param[in] inner
6700  *   Item is inner pattern.
6701  */
6702 static void
6703 flow_dv_translate_item_icmp(void *matcher, void *key,
6704                             const struct rte_flow_item *item,
6705                             int inner)
6706 {
6707         const struct rte_flow_item_icmp *icmp_m = item->mask;
6708         const struct rte_flow_item_icmp *icmp_v = item->spec;
6709         void *headers_m;
6710         void *headers_v;
6711         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6712                                      misc_parameters_3);
6713         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6714         if (inner) {
6715                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6716                                          inner_headers);
6717                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6718         } else {
6719                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6720                                          outer_headers);
6721                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6722         }
6723         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6724         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6725         if (!icmp_v)
6726                 return;
6727         if (!icmp_m)
6728                 icmp_m = &rte_flow_item_icmp_mask;
6729         /*
6730          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6731          * If only the protocol is specified, no need to match the frag.
6732          */
6733         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6734         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6735         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6736                  icmp_m->hdr.icmp_type);
6737         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6738                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6739         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6740                  icmp_m->hdr.icmp_code);
6741         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6742                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6743 }
6744
6745 /**
6746  * Add GTP item to matcher and to the value.
6747  *
6748  * @param[in, out] matcher
6749  *   Flow matcher.
6750  * @param[in, out] key
6751  *   Flow matcher value.
6752  * @param[in] item
6753  *   Flow pattern to translate.
6754  * @param[in] inner
6755  *   Item is inner pattern.
6756  */
6757 static void
6758 flow_dv_translate_item_gtp(void *matcher, void *key,
6759                            const struct rte_flow_item *item, int inner)
6760 {
6761         const struct rte_flow_item_gtp *gtp_m = item->mask;
6762         const struct rte_flow_item_gtp *gtp_v = item->spec;
6763         void *headers_m;
6764         void *headers_v;
6765         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6766                                      misc_parameters_3);
6767         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6768         uint16_t dport = RTE_GTPU_UDP_PORT;
6769
6770         if (inner) {
6771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6772                                          inner_headers);
6773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6774         } else {
6775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6776                                          outer_headers);
6777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6778         }
6779         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6780                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6781                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6782         }
6783         if (!gtp_v)
6784                 return;
6785         if (!gtp_m)
6786                 gtp_m = &rte_flow_item_gtp_mask;
6787         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6788         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6789                  gtp_v->msg_type & gtp_m->msg_type);
6790         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6791                  rte_be_to_cpu_32(gtp_m->teid));
6792         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6793                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6794 }
6795
6796 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6797
6798 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6799         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6800                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6801
6802 /**
6803  * Calculate flow matcher enable bitmap.
6804  *
6805  * @param match_criteria
6806  *   Pointer to flow matcher criteria.
6807  *
6808  * @return
6809  *   Bitmap of enabled fields.
6810  */
6811 static uint8_t
6812 flow_dv_matcher_enable(uint32_t *match_criteria)
6813 {
6814         uint8_t match_criteria_enable;
6815
6816         match_criteria_enable =
6817                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6818                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6819         match_criteria_enable |=
6820                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6821                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6822         match_criteria_enable |=
6823                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6824                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6825         match_criteria_enable |=
6826                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6827                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6828         match_criteria_enable |=
6829                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6830                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6831         return match_criteria_enable;
6832 }
6833
6834
6835 /**
6836  * Get a flow table.
6837  *
6838  * @param[in, out] dev
6839  *   Pointer to rte_eth_dev structure.
6840  * @param[in] table_id
6841  *   Table id to use.
6842  * @param[in] egress
6843  *   Direction of the table.
6844  * @param[in] transfer
6845  *   E-Switch or NIC flow.
6846  * @param[out] error
6847  *   pointer to error structure.
6848  *
6849  * @return
6850  *   Returns tables resource based on the index, NULL in case of failed.
6851  */
6852 static struct mlx5_flow_tbl_resource *
6853 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6854                          uint32_t table_id, uint8_t egress,
6855                          uint8_t transfer,
6856                          struct rte_flow_error *error)
6857 {
6858         struct mlx5_priv *priv = dev->data->dev_private;
6859         struct mlx5_ibv_shared *sh = priv->sh;
6860         struct mlx5_flow_tbl_resource *tbl;
6861         union mlx5_flow_tbl_key table_key = {
6862                 {
6863                         .table_id = table_id,
6864                         .reserved = 0,
6865                         .domain = !!transfer,
6866                         .direction = !!egress,
6867                 }
6868         };
6869         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6870                                                          table_key.v64);
6871         struct mlx5_flow_tbl_data_entry *tbl_data;
6872         int ret;
6873         void *domain;
6874
6875         if (pos) {
6876                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6877                                         entry);
6878                 tbl = &tbl_data->tbl;
6879                 rte_atomic32_inc(&tbl->refcnt);
6880                 return tbl;
6881         }
6882         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6883         if (!tbl_data) {
6884                 rte_flow_error_set(error, ENOMEM,
6885                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6886                                    NULL,
6887                                    "cannot allocate flow table data entry");
6888                 return NULL;
6889         }
6890         tbl = &tbl_data->tbl;
6891         pos = &tbl_data->entry;
6892         if (transfer)
6893                 domain = sh->fdb_domain;
6894         else if (egress)
6895                 domain = sh->tx_domain;
6896         else
6897                 domain = sh->rx_domain;
6898         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6899         if (!tbl->obj) {
6900                 rte_flow_error_set(error, ENOMEM,
6901                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6902                                    NULL, "cannot create flow table object");
6903                 rte_free(tbl_data);
6904                 return NULL;
6905         }
6906         /*
6907          * No multi-threads now, but still better to initialize the reference
6908          * count before insert it into the hash list.
6909          */
6910         rte_atomic32_init(&tbl->refcnt);
6911         /* Jump action reference count is initialized here. */
6912         rte_atomic32_init(&tbl_data->jump.refcnt);
6913         pos->key = table_key.v64;
6914         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6915         if (ret < 0) {
6916                 rte_flow_error_set(error, -ret,
6917                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6918                                    "cannot insert flow table data entry");
6919                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6920                 rte_free(tbl_data);
6921         }
6922         rte_atomic32_inc(&tbl->refcnt);
6923         return tbl;
6924 }
6925
6926 /**
6927  * Release a flow table.
6928  *
6929  * @param[in] dev
6930  *   Pointer to rte_eth_dev structure.
6931  * @param[in] tbl
6932  *   Table resource to be released.
6933  *
6934  * @return
6935  *   Returns 0 if table was released, else return 1;
6936  */
6937 static int
6938 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6939                              struct mlx5_flow_tbl_resource *tbl)
6940 {
6941         struct mlx5_priv *priv = dev->data->dev_private;
6942         struct mlx5_ibv_shared *sh = priv->sh;
6943         struct mlx5_flow_tbl_data_entry *tbl_data =
6944                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6945
6946         if (!tbl)
6947                 return 0;
6948         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6949                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6950
6951                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6952                 tbl->obj = NULL;
6953                 /* remove the entry from the hash list and free memory. */
6954                 mlx5_hlist_remove(sh->flow_tbls, pos);
6955                 rte_free(tbl_data);
6956                 return 0;
6957         }
6958         return 1;
6959 }
6960
6961 /**
6962  * Register the flow matcher.
6963  *
6964  * @param[in, out] dev
6965  *   Pointer to rte_eth_dev structure.
6966  * @param[in, out] matcher
6967  *   Pointer to flow matcher.
6968  * @param[in, out] key
6969  *   Pointer to flow table key.
6970  * @parm[in, out] dev_flow
6971  *   Pointer to the dev_flow.
6972  * @param[out] error
6973  *   pointer to error structure.
6974  *
6975  * @return
6976  *   0 on success otherwise -errno and errno is set.
6977  */
6978 static int
6979 flow_dv_matcher_register(struct rte_eth_dev *dev,
6980                          struct mlx5_flow_dv_matcher *matcher,
6981                          union mlx5_flow_tbl_key *key,
6982                          struct mlx5_flow *dev_flow,
6983                          struct rte_flow_error *error)
6984 {
6985         struct mlx5_priv *priv = dev->data->dev_private;
6986         struct mlx5_ibv_shared *sh = priv->sh;
6987         struct mlx5_flow_dv_matcher *cache_matcher;
6988         struct mlx5dv_flow_matcher_attr dv_attr = {
6989                 .type = IBV_FLOW_ATTR_NORMAL,
6990                 .match_mask = (void *)&matcher->mask,
6991         };
6992         struct mlx5_flow_tbl_resource *tbl;
6993         struct mlx5_flow_tbl_data_entry *tbl_data;
6994
6995         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6996                                        key->domain, error);
6997         if (!tbl)
6998                 return -rte_errno;      /* No need to refill the error info */
6999         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7000         /* Lookup from cache. */
7001         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7002                 if (matcher->crc == cache_matcher->crc &&
7003                     matcher->priority == cache_matcher->priority &&
7004                     !memcmp((const void *)matcher->mask.buf,
7005                             (const void *)cache_matcher->mask.buf,
7006                             cache_matcher->mask.size)) {
7007                         DRV_LOG(DEBUG,
7008                                 "%s group %u priority %hd use %s "
7009                                 "matcher %p: refcnt %d++",
7010                                 key->domain ? "FDB" : "NIC", key->table_id,
7011                                 cache_matcher->priority,
7012                                 key->direction ? "tx" : "rx",
7013                                 (void *)cache_matcher,
7014                                 rte_atomic32_read(&cache_matcher->refcnt));
7015                         rte_atomic32_inc(&cache_matcher->refcnt);
7016                         dev_flow->handle->dvh.matcher = cache_matcher;
7017                         /* old matcher should not make the table ref++. */
7018                         flow_dv_tbl_resource_release(dev, tbl);
7019                         return 0;
7020                 }
7021         }
7022         /* Register new matcher. */
7023         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7024         if (!cache_matcher) {
7025                 flow_dv_tbl_resource_release(dev, tbl);
7026                 return rte_flow_error_set(error, ENOMEM,
7027                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7028                                           "cannot allocate matcher memory");
7029         }
7030         *cache_matcher = *matcher;
7031         dv_attr.match_criteria_enable =
7032                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7033         dv_attr.priority = matcher->priority;
7034         if (key->direction)
7035                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7036         cache_matcher->matcher_object =
7037                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7038         if (!cache_matcher->matcher_object) {
7039                 rte_free(cache_matcher);
7040 #ifdef HAVE_MLX5DV_DR
7041                 flow_dv_tbl_resource_release(dev, tbl);
7042 #endif
7043                 return rte_flow_error_set(error, ENOMEM,
7044                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7045                                           NULL, "cannot create matcher");
7046         }
7047         /* Save the table information */
7048         cache_matcher->tbl = tbl;
7049         rte_atomic32_init(&cache_matcher->refcnt);
7050         /* only matcher ref++, table ref++ already done above in get API. */
7051         rte_atomic32_inc(&cache_matcher->refcnt);
7052         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7053         dev_flow->handle->dvh.matcher = cache_matcher;
7054         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7055                 key->domain ? "FDB" : "NIC", key->table_id,
7056                 cache_matcher->priority,
7057                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7058                 rte_atomic32_read(&cache_matcher->refcnt));
7059         return 0;
7060 }
7061
7062 /**
7063  * Find existing tag resource or create and register a new one.
7064  *
7065  * @param dev[in, out]
7066  *   Pointer to rte_eth_dev structure.
7067  * @param[in, out] tag_be24
7068  *   Tag value in big endian then R-shift 8.
7069  * @parm[in, out] dev_flow
7070  *   Pointer to the dev_flow.
7071  * @param[out] error
7072  *   pointer to error structure.
7073  *
7074  * @return
7075  *   0 on success otherwise -errno and errno is set.
7076  */
7077 static int
7078 flow_dv_tag_resource_register
7079                         (struct rte_eth_dev *dev,
7080                          uint32_t tag_be24,
7081                          struct mlx5_flow *dev_flow,
7082                          struct rte_flow_error *error)
7083 {
7084         struct mlx5_priv *priv = dev->data->dev_private;
7085         struct mlx5_ibv_shared *sh = priv->sh;
7086         struct mlx5_flow_dv_tag_resource *cache_resource;
7087         struct mlx5_hlist_entry *entry;
7088
7089         /* Lookup a matching resource from cache. */
7090         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7091         if (entry) {
7092                 cache_resource = container_of
7093                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7094                 rte_atomic32_inc(&cache_resource->refcnt);
7095                 dev_flow->handle->dvh.tag_resource = cache_resource->idx;
7096                 dev_flow->dv.tag_resource = cache_resource;
7097                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7098                         (void *)cache_resource,
7099                         rte_atomic32_read(&cache_resource->refcnt));
7100                 return 0;
7101         }
7102         /* Register new resource. */
7103         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7104                                        &dev_flow->handle->dvh.tag_resource);
7105         if (!cache_resource)
7106                 return rte_flow_error_set(error, ENOMEM,
7107                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7108                                           "cannot allocate resource memory");
7109         cache_resource->entry.key = (uint64_t)tag_be24;
7110         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7111         if (!cache_resource->action) {
7112                 rte_free(cache_resource);
7113                 return rte_flow_error_set(error, ENOMEM,
7114                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7115                                           NULL, "cannot create action");
7116         }
7117         rte_atomic32_init(&cache_resource->refcnt);
7118         rte_atomic32_inc(&cache_resource->refcnt);
7119         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7120                 mlx5_glue->destroy_flow_action(cache_resource->action);
7121                 rte_free(cache_resource);
7122                 return rte_flow_error_set(error, EEXIST,
7123                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7124                                           NULL, "cannot insert tag");
7125         }
7126         dev_flow->dv.tag_resource = cache_resource;
7127         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7128                 (void *)cache_resource,
7129                 rte_atomic32_read(&cache_resource->refcnt));
7130         return 0;
7131 }
7132
7133 /**
7134  * Release the tag.
7135  *
7136  * @param dev
7137  *   Pointer to Ethernet device.
7138  * @param tag_idx
7139  *   Tag index.
7140  *
7141  * @return
7142  *   1 while a reference on it exists, 0 when freed.
7143  */
7144 static int
7145 flow_dv_tag_release(struct rte_eth_dev *dev,
7146                     uint32_t tag_idx)
7147 {
7148         struct mlx5_priv *priv = dev->data->dev_private;
7149         struct mlx5_ibv_shared *sh = priv->sh;
7150         struct mlx5_flow_dv_tag_resource *tag;
7151
7152         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7153         if (!tag)
7154                 return 0;
7155         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7156                 dev->data->port_id, (void *)tag,
7157                 rte_atomic32_read(&tag->refcnt));
7158         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7159                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7160                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7161                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7162                         dev->data->port_id, (void *)tag);
7163                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7164                 return 0;
7165         }
7166         return 1;
7167 }
7168
7169 /**
7170  * Translate port ID action to vport.
7171  *
7172  * @param[in] dev
7173  *   Pointer to rte_eth_dev structure.
7174  * @param[in] action
7175  *   Pointer to the port ID action.
7176  * @param[out] dst_port_id
7177  *   The target port ID.
7178  * @param[out] error
7179  *   Pointer to the error structure.
7180  *
7181  * @return
7182  *   0 on success, a negative errno value otherwise and rte_errno is set.
7183  */
7184 static int
7185 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7186                                  const struct rte_flow_action *action,
7187                                  uint32_t *dst_port_id,
7188                                  struct rte_flow_error *error)
7189 {
7190         uint32_t port;
7191         struct mlx5_priv *priv;
7192         const struct rte_flow_action_port_id *conf =
7193                         (const struct rte_flow_action_port_id *)action->conf;
7194
7195         port = conf->original ? dev->data->port_id : conf->id;
7196         priv = mlx5_port_to_eswitch_info(port, false);
7197         if (!priv)
7198                 return rte_flow_error_set(error, -rte_errno,
7199                                           RTE_FLOW_ERROR_TYPE_ACTION,
7200                                           NULL,
7201                                           "No eswitch info was found for port");
7202 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7203         /*
7204          * This parameter is transferred to
7205          * mlx5dv_dr_action_create_dest_ib_port().
7206          */
7207         *dst_port_id = priv->ibv_port;
7208 #else
7209         /*
7210          * Legacy mode, no LAG configurations is supported.
7211          * This parameter is transferred to
7212          * mlx5dv_dr_action_create_dest_vport().
7213          */
7214         *dst_port_id = priv->vport_id;
7215 #endif
7216         return 0;
7217 }
7218
7219 /**
7220  * Add Tx queue matcher
7221  *
7222  * @param[in] dev
7223  *   Pointer to the dev struct.
7224  * @param[in, out] matcher
7225  *   Flow matcher.
7226  * @param[in, out] key
7227  *   Flow matcher value.
7228  * @param[in] item
7229  *   Flow pattern to translate.
7230  * @param[in] inner
7231  *   Item is inner pattern.
7232  */
7233 static void
7234 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7235                                 void *matcher, void *key,
7236                                 const struct rte_flow_item *item)
7237 {
7238         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7239         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7240         void *misc_m =
7241                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7242         void *misc_v =
7243                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7244         struct mlx5_txq_ctrl *txq;
7245         uint32_t queue;
7246
7247
7248         queue_m = (const void *)item->mask;
7249         if (!queue_m)
7250                 return;
7251         queue_v = (const void *)item->spec;
7252         if (!queue_v)
7253                 return;
7254         txq = mlx5_txq_get(dev, queue_v->queue);
7255         if (!txq)
7256                 return;
7257         queue = txq->obj->sq->id;
7258         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7259         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7260                  queue & queue_m->queue);
7261         mlx5_txq_release(dev, queue_v->queue);
7262 }
7263
7264 /**
7265  * Set the hash fields according to the @p flow information.
7266  *
7267  * @param[in] dev_flow
7268  *   Pointer to the mlx5_flow.
7269  */
7270 static void
7271 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7272 {
7273         struct rte_flow *flow = dev_flow->flow;
7274         uint64_t items = dev_flow->handle->layers;
7275         int rss_inner = 0;
7276         uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7277
7278         dev_flow->hash_fields = 0;
7279 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7280         if (flow->rss.level >= 2) {
7281                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7282                 rss_inner = 1;
7283         }
7284 #endif
7285         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7286             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7287                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7288                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7289                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7290                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7291                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7292                         else
7293                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7294                 }
7295         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7296                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7297                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7298                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7299                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7300                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7301                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7302                         else
7303                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7304                 }
7305         }
7306         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7307             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7308                 if (rss_types & ETH_RSS_UDP) {
7309                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7310                                 dev_flow->hash_fields |=
7311                                                 IBV_RX_HASH_SRC_PORT_UDP;
7312                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7313                                 dev_flow->hash_fields |=
7314                                                 IBV_RX_HASH_DST_PORT_UDP;
7315                         else
7316                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7317                 }
7318         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7319                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7320                 if (rss_types & ETH_RSS_TCP) {
7321                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7322                                 dev_flow->hash_fields |=
7323                                                 IBV_RX_HASH_SRC_PORT_TCP;
7324                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7325                                 dev_flow->hash_fields |=
7326                                                 IBV_RX_HASH_DST_PORT_TCP;
7327                         else
7328                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7329                 }
7330         }
7331 }
7332
7333 /**
7334  * Fill the flow with DV spec, lock free
7335  * (mutex should be acquired by caller).
7336  *
7337  * @param[in] dev
7338  *   Pointer to rte_eth_dev structure.
7339  * @param[in, out] dev_flow
7340  *   Pointer to the sub flow.
7341  * @param[in] attr
7342  *   Pointer to the flow attributes.
7343  * @param[in] items
7344  *   Pointer to the list of items.
7345  * @param[in] actions
7346  *   Pointer to the list of actions.
7347  * @param[out] error
7348  *   Pointer to the error structure.
7349  *
7350  * @return
7351  *   0 on success, a negative errno value otherwise and rte_errno is set.
7352  */
7353 static int
7354 __flow_dv_translate(struct rte_eth_dev *dev,
7355                     struct mlx5_flow *dev_flow,
7356                     const struct rte_flow_attr *attr,
7357                     const struct rte_flow_item items[],
7358                     const struct rte_flow_action actions[],
7359                     struct rte_flow_error *error)
7360 {
7361         struct mlx5_priv *priv = dev->data->dev_private;
7362         struct mlx5_dev_config *dev_conf = &priv->config;
7363         struct rte_flow *flow = dev_flow->flow;
7364         struct mlx5_flow_handle *handle = dev_flow->handle;
7365         uint64_t item_flags = 0;
7366         uint64_t last_item = 0;
7367         uint64_t action_flags = 0;
7368         uint64_t priority = attr->priority;
7369         struct mlx5_flow_dv_matcher matcher = {
7370                 .mask = {
7371                         .size = sizeof(matcher.mask.buf),
7372                 },
7373         };
7374         int actions_n = 0;
7375         bool actions_end = false;
7376         union {
7377                 struct mlx5_flow_dv_modify_hdr_resource res;
7378                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7379                             sizeof(struct mlx5_modification_cmd) *
7380                             (MLX5_MAX_MODIFY_NUM + 1)];
7381         } mhdr_dummy;
7382         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7383         union flow_dv_attr flow_attr = { .attr = 0 };
7384         uint32_t tag_be;
7385         union mlx5_flow_tbl_key tbl_key;
7386         uint32_t modify_action_position = UINT32_MAX;
7387         void *match_mask = matcher.mask.buf;
7388         void *match_value = dev_flow->dv.value.buf;
7389         uint8_t next_protocol = 0xff;
7390         struct rte_vlan_hdr vlan = { 0 };
7391         uint32_t table;
7392         int ret = 0;
7393
7394         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7395                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7396         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7397                                        !!priv->fdb_def_rule, &table, error);
7398         if (ret)
7399                 return ret;
7400         dev_flow->dv.group = table;
7401         if (attr->transfer)
7402                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7403         if (priority == MLX5_FLOW_PRIO_RSVD)
7404                 priority = dev_conf->flow_prio - 1;
7405         /* number of actions must be set to 0 in case of dirty stack. */
7406         mhdr_res->actions_num = 0;
7407         for (; !actions_end ; actions++) {
7408                 const struct rte_flow_action_queue *queue;
7409                 const struct rte_flow_action_rss *rss;
7410                 const struct rte_flow_action *action = actions;
7411                 const struct rte_flow_action_count *count = action->conf;
7412                 const uint8_t *rss_key;
7413                 const struct rte_flow_action_jump *jump_data;
7414                 const struct rte_flow_action_meter *mtr;
7415                 struct mlx5_flow_tbl_resource *tbl;
7416                 uint32_t port_id = 0;
7417                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7418                 int action_type = actions->type;
7419                 const struct rte_flow_action *found_action = NULL;
7420
7421                 switch (action_type) {
7422                 case RTE_FLOW_ACTION_TYPE_VOID:
7423                         break;
7424                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7425                         if (flow_dv_translate_action_port_id(dev, action,
7426                                                              &port_id, error))
7427                                 return -rte_errno;
7428                         port_id_resource.port_id = port_id;
7429                         if (flow_dv_port_id_action_resource_register
7430                             (dev, &port_id_resource, dev_flow, error))
7431                                 return -rte_errno;
7432                         dev_flow->dv.actions[actions_n++] =
7433                                         handle->dvh.port_id_action->action;
7434                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7435                         break;
7436                 case RTE_FLOW_ACTION_TYPE_FLAG:
7437                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7438                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7439                                 struct rte_flow_action_mark mark = {
7440                                         .id = MLX5_FLOW_MARK_DEFAULT,
7441                                 };
7442
7443                                 if (flow_dv_convert_action_mark(dev, &mark,
7444                                                                 mhdr_res,
7445                                                                 error))
7446                                         return -rte_errno;
7447                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7448                                 break;
7449                         }
7450                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7451                         /*
7452                          * Only one FLAG or MARK is supported per device flow
7453                          * right now. So the pointer to the tag resource must be
7454                          * zero before the register process.
7455                          */
7456                         MLX5_ASSERT(!handle->dvh.tag_resource);
7457                         if (flow_dv_tag_resource_register(dev, tag_be,
7458                                                           dev_flow, error))
7459                                 return -rte_errno;
7460                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7461                         dev_flow->dv.actions[actions_n++] =
7462                                         dev_flow->dv.tag_resource->action;
7463                         break;
7464                 case RTE_FLOW_ACTION_TYPE_MARK:
7465                         action_flags |= MLX5_FLOW_ACTION_MARK;
7466                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7467                                 const struct rte_flow_action_mark *mark =
7468                                         (const struct rte_flow_action_mark *)
7469                                                 actions->conf;
7470
7471                                 if (flow_dv_convert_action_mark(dev, mark,
7472                                                                 mhdr_res,
7473                                                                 error))
7474                                         return -rte_errno;
7475                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7476                                 break;
7477                         }
7478                         /* Fall-through */
7479                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7480                         /* Legacy (non-extensive) MARK action. */
7481                         tag_be = mlx5_flow_mark_set
7482                               (((const struct rte_flow_action_mark *)
7483                                (actions->conf))->id);
7484                         MLX5_ASSERT(!handle->dvh.tag_resource);
7485                         if (flow_dv_tag_resource_register(dev, tag_be,
7486                                                           dev_flow, error))
7487                                 return -rte_errno;
7488                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7489                         dev_flow->dv.actions[actions_n++] =
7490                                         dev_flow->dv.tag_resource->action;
7491                         break;
7492                 case RTE_FLOW_ACTION_TYPE_SET_META:
7493                         if (flow_dv_convert_action_set_meta
7494                                 (dev, mhdr_res, attr,
7495                                  (const struct rte_flow_action_set_meta *)
7496                                   actions->conf, error))
7497                                 return -rte_errno;
7498                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7499                         break;
7500                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7501                         if (flow_dv_convert_action_set_tag
7502                                 (dev, mhdr_res,
7503                                  (const struct rte_flow_action_set_tag *)
7504                                   actions->conf, error))
7505                                 return -rte_errno;
7506                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7507                         break;
7508                 case RTE_FLOW_ACTION_TYPE_DROP:
7509                         action_flags |= MLX5_FLOW_ACTION_DROP;
7510                         break;
7511                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7512                         MLX5_ASSERT(flow->rss.queue);
7513                         queue = actions->conf;
7514                         flow->rss.queue_num = 1;
7515                         (*flow->rss.queue)[0] = queue->index;
7516                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7517                         break;
7518                 case RTE_FLOW_ACTION_TYPE_RSS:
7519                         MLX5_ASSERT(flow->rss.queue);
7520                         rss = actions->conf;
7521                         if (flow->rss.queue)
7522                                 memcpy((*flow->rss.queue), rss->queue,
7523                                        rss->queue_num * sizeof(uint16_t));
7524                         flow->rss.queue_num = rss->queue_num;
7525                         /* NULL RSS key indicates default RSS key. */
7526                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7527                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7528                         /*
7529                          * rss->level and rss.types should be set in advance
7530                          * when expanding items for RSS.
7531                          */
7532                         action_flags |= MLX5_FLOW_ACTION_RSS;
7533                         break;
7534                 case RTE_FLOW_ACTION_TYPE_COUNT:
7535                         if (!dev_conf->devx) {
7536                                 rte_errno = ENOTSUP;
7537                                 goto cnt_err;
7538                         }
7539                         flow->counter = flow_dv_counter_alloc(dev,
7540                                                         count->shared,
7541                                                         count->id,
7542                                                         dev_flow->dv.group);
7543                         if (!flow->counter)
7544                                 goto cnt_err;
7545                         dev_flow->dv.actions[actions_n++] =
7546                                   (flow_dv_counter_get_by_idx(dev,
7547                                   flow->counter, NULL))->action;
7548                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7549                         break;
7550 cnt_err:
7551                         if (rte_errno == ENOTSUP)
7552                                 return rte_flow_error_set
7553                                               (error, ENOTSUP,
7554                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7555                                                NULL,
7556                                                "count action not supported");
7557                         else
7558                                 return rte_flow_error_set
7559                                                 (error, rte_errno,
7560                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7561                                                  action,
7562                                                  "cannot create counter"
7563                                                   " object.");
7564                         break;
7565                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7566                         dev_flow->dv.actions[actions_n++] =
7567                                                 priv->sh->pop_vlan_action;
7568                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7569                         break;
7570                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7571                         if (!(action_flags &
7572                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7573                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7574                         vlan.eth_proto = rte_be_to_cpu_16
7575                              ((((const struct rte_flow_action_of_push_vlan *)
7576                                                    actions->conf)->ethertype));
7577                         found_action = mlx5_flow_find_action
7578                                         (actions + 1,
7579                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7580                         if (found_action)
7581                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7582                         found_action = mlx5_flow_find_action
7583                                         (actions + 1,
7584                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7585                         if (found_action)
7586                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7587                         if (flow_dv_create_action_push_vlan
7588                                             (dev, attr, &vlan, dev_flow, error))
7589                                 return -rte_errno;
7590                         dev_flow->dv.actions[actions_n++] =
7591                                         dev_flow->dv.push_vlan_res->action;
7592                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7593                         break;
7594                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7595                         /* of_vlan_push action handled this action */
7596                         MLX5_ASSERT(action_flags &
7597                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7598                         break;
7599                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7600                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7601                                 break;
7602                         flow_dev_get_vlan_info_from_items(items, &vlan);
7603                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7604                         /* If no VLAN push - this is a modify header action */
7605                         if (flow_dv_convert_action_modify_vlan_vid
7606                                                 (mhdr_res, actions, error))
7607                                 return -rte_errno;
7608                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7609                         break;
7610                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7611                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7612                         if (flow_dv_create_action_l2_encap(dev, actions,
7613                                                            dev_flow,
7614                                                            attr->transfer,
7615                                                            error))
7616                                 return -rte_errno;
7617                         dev_flow->dv.actions[actions_n++] =
7618                                         dev_flow->dv.encap_decap->verbs_action;
7619                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7620                         break;
7621                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7622                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7623                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7624                                                            attr->transfer,
7625                                                            error))
7626                                 return -rte_errno;
7627                         dev_flow->dv.actions[actions_n++] =
7628                                         dev_flow->dv.encap_decap->verbs_action;
7629                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7630                         break;
7631                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7632                         /* Handle encap with preceding decap. */
7633                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7634                                 if (flow_dv_create_action_raw_encap
7635                                         (dev, actions, dev_flow, attr, error))
7636                                         return -rte_errno;
7637                                 dev_flow->dv.actions[actions_n++] =
7638                                         dev_flow->dv.encap_decap->verbs_action;
7639                         } else {
7640                                 /* Handle encap without preceding decap. */
7641                                 if (flow_dv_create_action_l2_encap
7642                                     (dev, actions, dev_flow, attr->transfer,
7643                                      error))
7644                                         return -rte_errno;
7645                                 dev_flow->dv.actions[actions_n++] =
7646                                         dev_flow->dv.encap_decap->verbs_action;
7647                         }
7648                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7649                         break;
7650                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7651                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7652                                 ;
7653                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7654                                 if (flow_dv_create_action_l2_decap
7655                                     (dev, dev_flow, attr->transfer, error))
7656                                         return -rte_errno;
7657                                 dev_flow->dv.actions[actions_n++] =
7658                                         dev_flow->dv.encap_decap->verbs_action;
7659                         }
7660                         /* If decap is followed by encap, handle it at encap. */
7661                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7662                         break;
7663                 case RTE_FLOW_ACTION_TYPE_JUMP:
7664                         jump_data = action->conf;
7665                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7666                                                        jump_data->group,
7667                                                        !!priv->fdb_def_rule,
7668                                                        &table, error);
7669                         if (ret)
7670                                 return ret;
7671                         tbl = flow_dv_tbl_resource_get(dev, table,
7672                                                        attr->egress,
7673                                                        attr->transfer, error);
7674                         if (!tbl)
7675                                 return rte_flow_error_set
7676                                                 (error, errno,
7677                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7678                                                  NULL,
7679                                                  "cannot create jump action.");
7680                         if (flow_dv_jump_tbl_resource_register
7681                             (dev, tbl, dev_flow, error)) {
7682                                 flow_dv_tbl_resource_release(dev, tbl);
7683                                 return rte_flow_error_set
7684                                                 (error, errno,
7685                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7686                                                  NULL,
7687                                                  "cannot create jump action.");
7688                         }
7689                         dev_flow->dv.actions[actions_n++] =
7690                                         handle->dvh.jump->action;
7691                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7692                         break;
7693                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7694                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7695                         if (flow_dv_convert_action_modify_mac
7696                                         (mhdr_res, actions, error))
7697                                 return -rte_errno;
7698                         action_flags |= actions->type ==
7699                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7700                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7701                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7702                         break;
7703                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7704                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7705                         if (flow_dv_convert_action_modify_ipv4
7706                                         (mhdr_res, actions, error))
7707                                 return -rte_errno;
7708                         action_flags |= actions->type ==
7709                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7710                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7711                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7712                         break;
7713                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7714                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7715                         if (flow_dv_convert_action_modify_ipv6
7716                                         (mhdr_res, actions, error))
7717                                 return -rte_errno;
7718                         action_flags |= actions->type ==
7719                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7720                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7721                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7722                         break;
7723                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7724                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7725                         if (flow_dv_convert_action_modify_tp
7726                                         (mhdr_res, actions, items,
7727                                          &flow_attr, dev_flow, !!(action_flags &
7728                                          MLX5_FLOW_ACTION_DECAP), error))
7729                                 return -rte_errno;
7730                         action_flags |= actions->type ==
7731                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7732                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7733                                         MLX5_FLOW_ACTION_SET_TP_DST;
7734                         break;
7735                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7736                         if (flow_dv_convert_action_modify_dec_ttl
7737                                         (mhdr_res, items, &flow_attr, dev_flow,
7738                                          !!(action_flags &
7739                                          MLX5_FLOW_ACTION_DECAP), error))
7740                                 return -rte_errno;
7741                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7742                         break;
7743                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7744                         if (flow_dv_convert_action_modify_ttl
7745                                         (mhdr_res, actions, items, &flow_attr,
7746                                          dev_flow, !!(action_flags &
7747                                          MLX5_FLOW_ACTION_DECAP), error))
7748                                 return -rte_errno;
7749                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7750                         break;
7751                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7752                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7753                         if (flow_dv_convert_action_modify_tcp_seq
7754                                         (mhdr_res, actions, error))
7755                                 return -rte_errno;
7756                         action_flags |= actions->type ==
7757                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7758                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7759                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7760                         break;
7761
7762                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7763                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7764                         if (flow_dv_convert_action_modify_tcp_ack
7765                                         (mhdr_res, actions, error))
7766                                 return -rte_errno;
7767                         action_flags |= actions->type ==
7768                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7769                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7770                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7771                         break;
7772                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7773                         if (flow_dv_convert_action_set_reg
7774                                         (mhdr_res, actions, error))
7775                                 return -rte_errno;
7776                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7777                         break;
7778                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7779                         if (flow_dv_convert_action_copy_mreg
7780                                         (dev, mhdr_res, actions, error))
7781                                 return -rte_errno;
7782                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7783                         break;
7784                 case RTE_FLOW_ACTION_TYPE_METER:
7785                         mtr = actions->conf;
7786                         if (!flow->meter) {
7787                                 flow->meter = mlx5_flow_meter_attach(priv,
7788                                                         mtr->mtr_id, attr,
7789                                                         error);
7790                                 if (!flow->meter)
7791                                         return rte_flow_error_set(error,
7792                                                 rte_errno,
7793                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7794                                                 NULL,
7795                                                 "meter not found "
7796                                                 "or invalid parameters");
7797                         }
7798                         /* Set the meter action. */
7799                         dev_flow->dv.actions[actions_n++] =
7800                                 flow->meter->mfts->meter_action;
7801                         action_flags |= MLX5_FLOW_ACTION_METER;
7802                         break;
7803                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7804                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7805                                                               actions, error))
7806                                 return -rte_errno;
7807                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7808                         break;
7809                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7810                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7811                                                               actions, error))
7812                                 return -rte_errno;
7813                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7814                         break;
7815                 case RTE_FLOW_ACTION_TYPE_END:
7816                         actions_end = true;
7817                         if (mhdr_res->actions_num) {
7818                                 /* create modify action if needed. */
7819                                 if (flow_dv_modify_hdr_resource_register
7820                                         (dev, mhdr_res, dev_flow, error))
7821                                         return -rte_errno;
7822                                 dev_flow->dv.actions[modify_action_position] =
7823                                         handle->dvh.modify_hdr->verbs_action;
7824                         }
7825                         break;
7826                 default:
7827                         break;
7828                 }
7829                 if (mhdr_res->actions_num &&
7830                     modify_action_position == UINT32_MAX)
7831                         modify_action_position = actions_n++;
7832         }
7833         dev_flow->dv.actions_n = actions_n;
7834         handle->act_flags = action_flags;
7835         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7836                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7837                 int item_type = items->type;
7838
7839                 switch (item_type) {
7840                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7841                         flow_dv_translate_item_port_id(dev, match_mask,
7842                                                        match_value, items);
7843                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7844                         break;
7845                 case RTE_FLOW_ITEM_TYPE_ETH:
7846                         flow_dv_translate_item_eth(match_mask, match_value,
7847                                                    items, tunnel);
7848                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7849                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7850                                              MLX5_FLOW_LAYER_OUTER_L2;
7851                         break;
7852                 case RTE_FLOW_ITEM_TYPE_VLAN:
7853                         flow_dv_translate_item_vlan(dev_flow,
7854                                                     match_mask, match_value,
7855                                                     items, tunnel);
7856                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7857                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7858                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7859                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7860                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7861                         break;
7862                 case RTE_FLOW_ITEM_TYPE_IPV4:
7863                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7864                                                   &item_flags, &tunnel);
7865                         flow_dv_translate_item_ipv4(match_mask, match_value,
7866                                                     items, item_flags, tunnel,
7867                                                     dev_flow->dv.group);
7868                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7869                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7870                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7871                         if (items->mask != NULL &&
7872                             ((const struct rte_flow_item_ipv4 *)
7873                              items->mask)->hdr.next_proto_id) {
7874                                 next_protocol =
7875                                         ((const struct rte_flow_item_ipv4 *)
7876                                          (items->spec))->hdr.next_proto_id;
7877                                 next_protocol &=
7878                                         ((const struct rte_flow_item_ipv4 *)
7879                                          (items->mask))->hdr.next_proto_id;
7880                         } else {
7881                                 /* Reset for inner layer. */
7882                                 next_protocol = 0xff;
7883                         }
7884                         break;
7885                 case RTE_FLOW_ITEM_TYPE_IPV6:
7886                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7887                                                   &item_flags, &tunnel);
7888                         flow_dv_translate_item_ipv6(match_mask, match_value,
7889                                                     items, item_flags, tunnel,
7890                                                     dev_flow->dv.group);
7891                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7892                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7893                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7894                         if (items->mask != NULL &&
7895                             ((const struct rte_flow_item_ipv6 *)
7896                              items->mask)->hdr.proto) {
7897                                 next_protocol =
7898                                         ((const struct rte_flow_item_ipv6 *)
7899                                          items->spec)->hdr.proto;
7900                                 next_protocol &=
7901                                         ((const struct rte_flow_item_ipv6 *)
7902                                          items->mask)->hdr.proto;
7903                         } else {
7904                                 /* Reset for inner layer. */
7905                                 next_protocol = 0xff;
7906                         }
7907                         break;
7908                 case RTE_FLOW_ITEM_TYPE_TCP:
7909                         flow_dv_translate_item_tcp(match_mask, match_value,
7910                                                    items, tunnel);
7911                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7912                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7913                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7914                         break;
7915                 case RTE_FLOW_ITEM_TYPE_UDP:
7916                         flow_dv_translate_item_udp(match_mask, match_value,
7917                                                    items, tunnel);
7918                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7919                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7920                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7921                         break;
7922                 case RTE_FLOW_ITEM_TYPE_GRE:
7923                         flow_dv_translate_item_gre(match_mask, match_value,
7924                                                    items, tunnel);
7925                         matcher.priority = flow->rss.level >= 2 ?
7926                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7927                         last_item = MLX5_FLOW_LAYER_GRE;
7928                         break;
7929                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7930                         flow_dv_translate_item_gre_key(match_mask,
7931                                                        match_value, items);
7932                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7933                         break;
7934                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7935                         flow_dv_translate_item_nvgre(match_mask, match_value,
7936                                                      items, tunnel);
7937                         matcher.priority = flow->rss.level >= 2 ?
7938                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7939                         last_item = MLX5_FLOW_LAYER_GRE;
7940                         break;
7941                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7942                         flow_dv_translate_item_vxlan(match_mask, match_value,
7943                                                      items, tunnel);
7944                         matcher.priority = flow->rss.level >= 2 ?
7945                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7946                         last_item = MLX5_FLOW_LAYER_VXLAN;
7947                         break;
7948                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7949                         flow_dv_translate_item_vxlan_gpe(match_mask,
7950                                                          match_value, items,
7951                                                          tunnel);
7952                         matcher.priority = flow->rss.level >= 2 ?
7953                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7954                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7955                         break;
7956                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7957                         flow_dv_translate_item_geneve(match_mask, match_value,
7958                                                       items, tunnel);
7959                         matcher.priority = flow->rss.level >= 2 ?
7960                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7961                         last_item = MLX5_FLOW_LAYER_GENEVE;
7962                         break;
7963                 case RTE_FLOW_ITEM_TYPE_MPLS:
7964                         flow_dv_translate_item_mpls(match_mask, match_value,
7965                                                     items, last_item, tunnel);
7966                         matcher.priority = flow->rss.level >= 2 ?
7967                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7968                         last_item = MLX5_FLOW_LAYER_MPLS;
7969                         break;
7970                 case RTE_FLOW_ITEM_TYPE_MARK:
7971                         flow_dv_translate_item_mark(dev, match_mask,
7972                                                     match_value, items);
7973                         last_item = MLX5_FLOW_ITEM_MARK;
7974                         break;
7975                 case RTE_FLOW_ITEM_TYPE_META:
7976                         flow_dv_translate_item_meta(dev, match_mask,
7977                                                     match_value, attr, items);
7978                         last_item = MLX5_FLOW_ITEM_METADATA;
7979                         break;
7980                 case RTE_FLOW_ITEM_TYPE_ICMP:
7981                         flow_dv_translate_item_icmp(match_mask, match_value,
7982                                                     items, tunnel);
7983                         last_item = MLX5_FLOW_LAYER_ICMP;
7984                         break;
7985                 case RTE_FLOW_ITEM_TYPE_ICMP6:
7986                         flow_dv_translate_item_icmp6(match_mask, match_value,
7987                                                       items, tunnel);
7988                         last_item = MLX5_FLOW_LAYER_ICMP6;
7989                         break;
7990                 case RTE_FLOW_ITEM_TYPE_TAG:
7991                         flow_dv_translate_item_tag(dev, match_mask,
7992                                                    match_value, items);
7993                         last_item = MLX5_FLOW_ITEM_TAG;
7994                         break;
7995                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7996                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
7997                                                         match_value, items);
7998                         last_item = MLX5_FLOW_ITEM_TAG;
7999                         break;
8000                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8001                         flow_dv_translate_item_tx_queue(dev, match_mask,
8002                                                         match_value,
8003                                                         items);
8004                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8005                         break;
8006                 case RTE_FLOW_ITEM_TYPE_GTP:
8007                         flow_dv_translate_item_gtp(match_mask, match_value,
8008                                                    items, tunnel);
8009                         matcher.priority = flow->rss.level >= 2 ?
8010                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8011                         last_item = MLX5_FLOW_LAYER_GTP;
8012                         break;
8013                 default:
8014                         break;
8015                 }
8016                 item_flags |= last_item;
8017         }
8018         /*
8019          * When E-Switch mode is enabled, we have two cases where we need to
8020          * set the source port manually.
8021          * The first one, is in case of Nic steering rule, and the second is
8022          * E-Switch rule where no port_id item was found. In both cases
8023          * the source port is set according the current port in use.
8024          */
8025         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8026             (priv->representor || priv->master)) {
8027                 if (flow_dv_translate_item_port_id(dev, match_mask,
8028                                                    match_value, NULL))
8029                         return -rte_errno;
8030         }
8031 #ifdef RTE_LIBRTE_MLX5_DEBUG
8032         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8033                                               dev_flow->dv.value.buf));
8034 #endif
8035         /*
8036          * Layers may be already initialized from prefix flow if this dev_flow
8037          * is the suffix flow.
8038          */
8039         handle->layers |= item_flags;
8040         if (action_flags & MLX5_FLOW_ACTION_RSS)
8041                 flow_dv_hashfields_set(dev_flow);
8042         /* Register matcher. */
8043         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8044                                     matcher.mask.size);
8045         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8046                                                      matcher.priority);
8047         /* reserved field no needs to be set to 0 here. */
8048         tbl_key.domain = attr->transfer;
8049         tbl_key.direction = attr->egress;
8050         tbl_key.table_id = dev_flow->dv.group;
8051         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8052                 return -rte_errno;
8053         return 0;
8054 }
8055
8056 /**
8057  * Apply the flow to the NIC, lock free,
8058  * (mutex should be acquired by caller).
8059  *
8060  * @param[in] dev
8061  *   Pointer to the Ethernet device structure.
8062  * @param[in, out] flow
8063  *   Pointer to flow structure.
8064  * @param[out] error
8065  *   Pointer to error structure.
8066  *
8067  * @return
8068  *   0 on success, a negative errno value otherwise and rte_errno is set.
8069  */
8070 static int
8071 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8072                 struct rte_flow_error *error)
8073 {
8074         struct mlx5_flow_dv_workspace *dv;
8075         struct mlx5_flow_handle *dh;
8076         struct mlx5_flow_handle_dv *dv_h;
8077         struct mlx5_flow *dev_flow;
8078         struct mlx5_priv *priv = dev->data->dev_private;
8079         int n;
8080         int err;
8081         int idx;
8082
8083         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8084                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8085                 dv = &dev_flow->dv;
8086                 dh = dev_flow->handle;
8087                 dv_h = &dh->dvh;
8088                 n = dv->actions_n;
8089                 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8090                         if (dv->transfer) {
8091                                 dv->actions[n++] = priv->sh->esw_drop_action;
8092                         } else {
8093                                 dh->hrxq = mlx5_hrxq_drop_new(dev);
8094                                 if (!dh->hrxq) {
8095                                         rte_flow_error_set
8096                                                 (error, errno,
8097                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8098                                                  NULL,
8099                                                  "cannot get drop hash queue");
8100                                         goto error;
8101                                 }
8102                                 dv->actions[n++] = dh->hrxq->action;
8103                         }
8104                 } else if (dh->act_flags &
8105                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8106                         struct mlx5_hrxq *hrxq;
8107
8108                         MLX5_ASSERT(flow->rss.queue);
8109                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8110                                              MLX5_RSS_HASH_KEY_LEN,
8111                                              dev_flow->hash_fields,
8112                                              (*flow->rss.queue),
8113                                              flow->rss.queue_num);
8114                         if (!hrxq) {
8115                                 hrxq = mlx5_hrxq_new
8116                                         (dev, flow->rss.key,
8117                                          MLX5_RSS_HASH_KEY_LEN,
8118                                          dev_flow->hash_fields,
8119                                          (*flow->rss.queue),
8120                                          flow->rss.queue_num,
8121                                          !!(dh->layers &
8122                                             MLX5_FLOW_LAYER_TUNNEL));
8123                         }
8124                         if (!hrxq) {
8125                                 rte_flow_error_set
8126                                         (error, rte_errno,
8127                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8128                                          "cannot get hash queue");
8129                                 goto error;
8130                         }
8131                         dh->hrxq = hrxq;
8132                         dv->actions[n++] = dh->hrxq->action;
8133                 }
8134                 dh->ib_flow =
8135                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8136                                                   (void *)&dv->value, n,
8137                                                   dv->actions);
8138                 if (!dh->ib_flow) {
8139                         rte_flow_error_set(error, errno,
8140                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8141                                            NULL,
8142                                            "hardware refuses to create flow");
8143                         goto error;
8144                 }
8145                 if (priv->vmwa_context &&
8146                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8147                         /*
8148                          * The rule contains the VLAN pattern.
8149                          * For VF we are going to create VLAN
8150                          * interface to make hypervisor set correct
8151                          * e-Switch vport context.
8152                          */
8153                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8154                 }
8155         }
8156         return 0;
8157 error:
8158         err = rte_errno; /* Save rte_errno before cleanup. */
8159         LIST_FOREACH(dh, &flow->dev_handles, next) {
8160                 if (dh->hrxq) {
8161                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8162                                 mlx5_hrxq_drop_release(dev);
8163                         else
8164                                 mlx5_hrxq_release(dev, dh->hrxq);
8165                         dh->hrxq = NULL;
8166                 }
8167                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8168                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8169         }
8170         rte_errno = err; /* Restore rte_errno. */
8171         return -rte_errno;
8172 }
8173
8174 /**
8175  * Release the flow matcher.
8176  *
8177  * @param dev
8178  *   Pointer to Ethernet device.
8179  * @param handle
8180  *   Pointer to mlx5_flow_handle.
8181  *
8182  * @return
8183  *   1 while a reference on it exists, 0 when freed.
8184  */
8185 static int
8186 flow_dv_matcher_release(struct rte_eth_dev *dev,
8187                         struct mlx5_flow_handle *handle)
8188 {
8189         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8190
8191         MLX5_ASSERT(matcher->matcher_object);
8192         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8193                 dev->data->port_id, (void *)matcher,
8194                 rte_atomic32_read(&matcher->refcnt));
8195         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8196                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8197                            (matcher->matcher_object));
8198                 LIST_REMOVE(matcher, next);
8199                 /* table ref-- in release interface. */
8200                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8201                 rte_free(matcher);
8202                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8203                         dev->data->port_id, (void *)matcher);
8204                 return 0;
8205         }
8206         return 1;
8207 }
8208
8209 /**
8210  * Release an encap/decap resource.
8211  *
8212  * @param dev
8213  *   Pointer to Ethernet device.
8214  * @param handle
8215  *   Pointer to mlx5_flow_handle.
8216  *
8217  * @return
8218  *   1 while a reference on it exists, 0 when freed.
8219  */
8220 static int
8221 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8222                                      struct mlx5_flow_handle *handle)
8223 {
8224         struct mlx5_priv *priv = dev->data->dev_private;
8225         uint32_t idx = handle->dvh.encap_decap;
8226         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8227
8228         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8229                          idx);
8230         if (!cache_resource)
8231                 return 0;
8232         MLX5_ASSERT(cache_resource->verbs_action);
8233         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8234                 (void *)cache_resource,
8235                 rte_atomic32_read(&cache_resource->refcnt));
8236         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8237                 claim_zero(mlx5_glue->destroy_flow_action
8238                                 (cache_resource->verbs_action));
8239                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8240                              &priv->sh->encaps_decaps, idx,
8241                              cache_resource, next);
8242                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8243                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8244                         (void *)cache_resource);
8245                 return 0;
8246         }
8247         return 1;
8248 }
8249
8250 /**
8251  * Release an jump to table action resource.
8252  *
8253  * @param dev
8254  *   Pointer to Ethernet device.
8255  * @param handle
8256  *   Pointer to mlx5_flow_handle.
8257  *
8258  * @return
8259  *   1 while a reference on it exists, 0 when freed.
8260  */
8261 static int
8262 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8263                                   struct mlx5_flow_handle *handle)
8264 {
8265         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8266                                                         handle->dvh.jump;
8267         struct mlx5_flow_tbl_data_entry *tbl_data =
8268                         container_of(cache_resource,
8269                                      struct mlx5_flow_tbl_data_entry, jump);
8270
8271         MLX5_ASSERT(cache_resource->action);
8272         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8273                 (void *)cache_resource,
8274                 rte_atomic32_read(&cache_resource->refcnt));
8275         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8276                 claim_zero(mlx5_glue->destroy_flow_action
8277                                 (cache_resource->action));
8278                 /* jump action memory free is inside the table release. */
8279                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8280                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8281                         (void *)cache_resource);
8282                 return 0;
8283         }
8284         return 1;
8285 }
8286
8287 /**
8288  * Release a modify-header resource.
8289  *
8290  * @param handle
8291  *   Pointer to mlx5_flow_handle.
8292  *
8293  * @return
8294  *   1 while a reference on it exists, 0 when freed.
8295  */
8296 static int
8297 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8298 {
8299         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8300                                                         handle->dvh.modify_hdr;
8301
8302         MLX5_ASSERT(cache_resource->verbs_action);
8303         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8304                 (void *)cache_resource,
8305                 rte_atomic32_read(&cache_resource->refcnt));
8306         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8307                 claim_zero(mlx5_glue->destroy_flow_action
8308                                 (cache_resource->verbs_action));
8309                 LIST_REMOVE(cache_resource, next);
8310                 rte_free(cache_resource);
8311                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8312                         (void *)cache_resource);
8313                 return 0;
8314         }
8315         return 1;
8316 }
8317
8318 /**
8319  * Release port ID action resource.
8320  *
8321  * @param handle
8322  *   Pointer to mlx5_flow_handle.
8323  *
8324  * @return
8325  *   1 while a reference on it exists, 0 when freed.
8326  */
8327 static int
8328 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8329 {
8330         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8331                                                 handle->dvh.port_id_action;
8332
8333         MLX5_ASSERT(cache_resource->action);
8334         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8335                 (void *)cache_resource,
8336                 rte_atomic32_read(&cache_resource->refcnt));
8337         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8338                 claim_zero(mlx5_glue->destroy_flow_action
8339                                 (cache_resource->action));
8340                 LIST_REMOVE(cache_resource, next);
8341                 rte_free(cache_resource);
8342                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8343                         (void *)cache_resource);
8344                 return 0;
8345         }
8346         return 1;
8347 }
8348
8349 /**
8350  * Release push vlan action resource.
8351  *
8352  * @param dev
8353  *   Pointer to Ethernet device.
8354  * @param handle
8355  *   Pointer to mlx5_flow_handle.
8356  *
8357  * @return
8358  *   1 while a reference on it exists, 0 when freed.
8359  */
8360 static int
8361 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8362                                           struct mlx5_flow_handle *handle)
8363 {
8364         struct mlx5_priv *priv = dev->data->dev_private;
8365         uint32_t idx = handle->dvh.push_vlan_res;
8366         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8367
8368         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8369                                         idx);
8370         if (!cache_resource)
8371                 return 0;
8372         MLX5_ASSERT(cache_resource->action);
8373         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8374                 (void *)cache_resource,
8375                 rte_atomic32_read(&cache_resource->refcnt));
8376         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8377                 claim_zero(mlx5_glue->destroy_flow_action
8378                                 (cache_resource->action));
8379                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8380                              &priv->sh->push_vlan_action_list, idx,
8381                              cache_resource, next);
8382                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8383                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8384                         (void *)cache_resource);
8385                 return 0;
8386         }
8387         return 1;
8388 }
8389
8390 /**
8391  * Remove the flow from the NIC but keeps it in memory.
8392  * Lock free, (mutex should be acquired by caller).
8393  *
8394  * @param[in] dev
8395  *   Pointer to Ethernet device.
8396  * @param[in, out] flow
8397  *   Pointer to flow structure.
8398  */
8399 static void
8400 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8401 {
8402         struct mlx5_flow_handle *dh;
8403
8404         if (!flow)
8405                 return;
8406         LIST_FOREACH(dh, &flow->dev_handles, next) {
8407                 if (dh->ib_flow) {
8408                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8409                         dh->ib_flow = NULL;
8410                 }
8411                 if (dh->hrxq) {
8412                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8413                                 mlx5_hrxq_drop_release(dev);
8414                         else
8415                                 mlx5_hrxq_release(dev, dh->hrxq);
8416                         dh->hrxq = NULL;
8417                 }
8418                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8419                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8420         }
8421 }
8422
8423 /**
8424  * Remove the flow from the NIC and the memory.
8425  * Lock free, (mutex should be acquired by caller).
8426  *
8427  * @param[in] dev
8428  *   Pointer to the Ethernet device structure.
8429  * @param[in, out] flow
8430  *   Pointer to flow structure.
8431  */
8432 static void
8433 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8434 {
8435         struct mlx5_flow_handle *dev_handle;
8436
8437         if (!flow)
8438                 return;
8439         __flow_dv_remove(dev, flow);
8440         if (flow->counter) {
8441                 flow_dv_counter_release(dev, flow->counter);
8442                 flow->counter = 0;
8443         }
8444         if (flow->meter) {
8445                 mlx5_flow_meter_detach(flow->meter);
8446                 flow->meter = NULL;
8447         }
8448         while (!LIST_EMPTY(&flow->dev_handles)) {
8449                 dev_handle = LIST_FIRST(&flow->dev_handles);
8450                 LIST_REMOVE(dev_handle, next);
8451                 if (dev_handle->dvh.matcher)
8452                         flow_dv_matcher_release(dev, dev_handle);
8453                 if (dev_handle->dvh.encap_decap)
8454                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8455                 if (dev_handle->dvh.modify_hdr)
8456                         flow_dv_modify_hdr_resource_release(dev_handle);
8457                 if (dev_handle->dvh.jump)
8458                         flow_dv_jump_tbl_resource_release(dev, dev_handle);
8459                 if (dev_handle->dvh.port_id_action)
8460                         flow_dv_port_id_action_resource_release(dev_handle);
8461                 if (dev_handle->dvh.push_vlan_res)
8462                         flow_dv_push_vlan_action_resource_release(dev,
8463                                                                   dev_handle);
8464                 if (dev_handle->dvh.tag_resource)
8465                         flow_dv_tag_release(dev,
8466                                             dev_handle->dvh.tag_resource);
8467                 rte_free(dev_handle);
8468         }
8469 }
8470
8471 /**
8472  * Query a dv flow  rule for its statistics via devx.
8473  *
8474  * @param[in] dev
8475  *   Pointer to Ethernet device.
8476  * @param[in] flow
8477  *   Pointer to the sub flow.
8478  * @param[out] data
8479  *   data retrieved by the query.
8480  * @param[out] error
8481  *   Perform verbose error reporting if not NULL.
8482  *
8483  * @return
8484  *   0 on success, a negative errno value otherwise and rte_errno is set.
8485  */
8486 static int
8487 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8488                     void *data, struct rte_flow_error *error)
8489 {
8490         struct mlx5_priv *priv = dev->data->dev_private;
8491         struct rte_flow_query_count *qc = data;
8492
8493         if (!priv->config.devx)
8494                 return rte_flow_error_set(error, ENOTSUP,
8495                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8496                                           NULL,
8497                                           "counters are not supported");
8498         if (flow->counter) {
8499                 uint64_t pkts, bytes;
8500                 struct mlx5_flow_counter *cnt;
8501
8502                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8503                                                  NULL);
8504                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8505                                                &bytes);
8506
8507                 if (err)
8508                         return rte_flow_error_set(error, -err,
8509                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8510                                         NULL, "cannot read counters");
8511                 qc->hits_set = 1;
8512                 qc->bytes_set = 1;
8513                 qc->hits = pkts - cnt->hits;
8514                 qc->bytes = bytes - cnt->bytes;
8515                 if (qc->reset) {
8516                         cnt->hits = pkts;
8517                         cnt->bytes = bytes;
8518                 }
8519                 return 0;
8520         }
8521         return rte_flow_error_set(error, EINVAL,
8522                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8523                                   NULL,
8524                                   "counters are not available");
8525 }
8526
8527 /**
8528  * Query a flow.
8529  *
8530  * @see rte_flow_query()
8531  * @see rte_flow_ops
8532  */
8533 static int
8534 flow_dv_query(struct rte_eth_dev *dev,
8535               struct rte_flow *flow __rte_unused,
8536               const struct rte_flow_action *actions __rte_unused,
8537               void *data __rte_unused,
8538               struct rte_flow_error *error __rte_unused)
8539 {
8540         int ret = -EINVAL;
8541
8542         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8543                 switch (actions->type) {
8544                 case RTE_FLOW_ACTION_TYPE_VOID:
8545                         break;
8546                 case RTE_FLOW_ACTION_TYPE_COUNT:
8547                         ret = flow_dv_query_count(dev, flow, data, error);
8548                         break;
8549                 default:
8550                         return rte_flow_error_set(error, ENOTSUP,
8551                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8552                                                   actions,
8553                                                   "action not supported");
8554                 }
8555         }
8556         return ret;
8557 }
8558
8559 /**
8560  * Destroy the meter table set.
8561  * Lock free, (mutex should be acquired by caller).
8562  *
8563  * @param[in] dev
8564  *   Pointer to Ethernet device.
8565  * @param[in] tbl
8566  *   Pointer to the meter table set.
8567  *
8568  * @return
8569  *   Always 0.
8570  */
8571 static int
8572 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8573                         struct mlx5_meter_domains_infos *tbl)
8574 {
8575         struct mlx5_priv *priv = dev->data->dev_private;
8576         struct mlx5_meter_domains_infos *mtd =
8577                                 (struct mlx5_meter_domains_infos *)tbl;
8578
8579         if (!mtd || !priv->config.dv_flow_en)
8580                 return 0;
8581         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8582                 claim_zero(mlx5_glue->dv_destroy_flow
8583                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8584         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8585                 claim_zero(mlx5_glue->dv_destroy_flow
8586                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8587         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8588                 claim_zero(mlx5_glue->dv_destroy_flow
8589                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8590         if (mtd->egress.color_matcher)
8591                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8592                           (mtd->egress.color_matcher));
8593         if (mtd->egress.any_matcher)
8594                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8595                           (mtd->egress.any_matcher));
8596         if (mtd->egress.tbl)
8597                 claim_zero(flow_dv_tbl_resource_release(dev,
8598                                                         mtd->egress.tbl));
8599         if (mtd->egress.sfx_tbl)
8600                 claim_zero(flow_dv_tbl_resource_release(dev,
8601                                                         mtd->egress.sfx_tbl));
8602         if (mtd->ingress.color_matcher)
8603                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8604                           (mtd->ingress.color_matcher));
8605         if (mtd->ingress.any_matcher)
8606                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8607                           (mtd->ingress.any_matcher));
8608         if (mtd->ingress.tbl)
8609                 claim_zero(flow_dv_tbl_resource_release(dev,
8610                                                         mtd->ingress.tbl));
8611         if (mtd->ingress.sfx_tbl)
8612                 claim_zero(flow_dv_tbl_resource_release(dev,
8613                                                         mtd->ingress.sfx_tbl));
8614         if (mtd->transfer.color_matcher)
8615                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8616                           (mtd->transfer.color_matcher));
8617         if (mtd->transfer.any_matcher)
8618                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8619                           (mtd->transfer.any_matcher));
8620         if (mtd->transfer.tbl)
8621                 claim_zero(flow_dv_tbl_resource_release(dev,
8622                                                         mtd->transfer.tbl));
8623         if (mtd->transfer.sfx_tbl)
8624                 claim_zero(flow_dv_tbl_resource_release(dev,
8625                                                         mtd->transfer.sfx_tbl));
8626         if (mtd->drop_actn)
8627                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8628         rte_free(mtd);
8629         return 0;
8630 }
8631
8632 /* Number of meter flow actions, count and jump or count and drop. */
8633 #define METER_ACTIONS 2
8634
8635 /**
8636  * Create specify domain meter table and suffix table.
8637  *
8638  * @param[in] dev
8639  *   Pointer to Ethernet device.
8640  * @param[in,out] mtb
8641  *   Pointer to DV meter table set.
8642  * @param[in] egress
8643  *   Table attribute.
8644  * @param[in] transfer
8645  *   Table attribute.
8646  * @param[in] color_reg_c_idx
8647  *   Reg C index for color match.
8648  *
8649  * @return
8650  *   0 on success, -1 otherwise and rte_errno is set.
8651  */
8652 static int
8653 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8654                            struct mlx5_meter_domains_infos *mtb,
8655                            uint8_t egress, uint8_t transfer,
8656                            uint32_t color_reg_c_idx)
8657 {
8658         struct mlx5_priv *priv = dev->data->dev_private;
8659         struct mlx5_ibv_shared *sh = priv->sh;
8660         struct mlx5_flow_dv_match_params mask = {
8661                 .size = sizeof(mask.buf),
8662         };
8663         struct mlx5_flow_dv_match_params value = {
8664                 .size = sizeof(value.buf),
8665         };
8666         struct mlx5dv_flow_matcher_attr dv_attr = {
8667                 .type = IBV_FLOW_ATTR_NORMAL,
8668                 .priority = 0,
8669                 .match_criteria_enable = 0,
8670                 .match_mask = (void *)&mask,
8671         };
8672         void *actions[METER_ACTIONS];
8673         struct mlx5_meter_domain_info *dtb;
8674         struct rte_flow_error error;
8675         int i = 0;
8676
8677         if (transfer)
8678                 dtb = &mtb->transfer;
8679         else if (egress)
8680                 dtb = &mtb->egress;
8681         else
8682                 dtb = &mtb->ingress;
8683         /* Create the meter table with METER level. */
8684         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8685                                             egress, transfer, &error);
8686         if (!dtb->tbl) {
8687                 DRV_LOG(ERR, "Failed to create meter policer table.");
8688                 return -1;
8689         }
8690         /* Create the meter suffix table with SUFFIX level. */
8691         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8692                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8693                                             egress, transfer, &error);
8694         if (!dtb->sfx_tbl) {
8695                 DRV_LOG(ERR, "Failed to create meter suffix table.");
8696                 return -1;
8697         }
8698         /* Create matchers, Any and Color. */
8699         dv_attr.priority = 3;
8700         dv_attr.match_criteria_enable = 0;
8701         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8702                                                              &dv_attr,
8703                                                              dtb->tbl->obj);
8704         if (!dtb->any_matcher) {
8705                 DRV_LOG(ERR, "Failed to create meter"
8706                              " policer default matcher.");
8707                 goto error_exit;
8708         }
8709         dv_attr.priority = 0;
8710         dv_attr.match_criteria_enable =
8711                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8712         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8713                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8714         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8715                                                                &dv_attr,
8716                                                                dtb->tbl->obj);
8717         if (!dtb->color_matcher) {
8718                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8719                 goto error_exit;
8720         }
8721         if (mtb->count_actns[RTE_MTR_DROPPED])
8722                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8723         actions[i++] = mtb->drop_actn;
8724         /* Default rule: lowest priority, match any, actions: drop. */
8725         dtb->policer_rules[RTE_MTR_DROPPED] =
8726                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8727                                                  (void *)&value, i, actions);
8728         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8729                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8730                 goto error_exit;
8731         }
8732         return 0;
8733 error_exit:
8734         return -1;
8735 }
8736
8737 /**
8738  * Create the needed meter and suffix tables.
8739  * Lock free, (mutex should be acquired by caller).
8740  *
8741  * @param[in] dev
8742  *   Pointer to Ethernet device.
8743  * @param[in] fm
8744  *   Pointer to the flow meter.
8745  *
8746  * @return
8747  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8748  */
8749 static struct mlx5_meter_domains_infos *
8750 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8751                        const struct mlx5_flow_meter *fm)
8752 {
8753         struct mlx5_priv *priv = dev->data->dev_private;
8754         struct mlx5_meter_domains_infos *mtb;
8755         int ret;
8756         int i;
8757
8758         if (!priv->mtr_en) {
8759                 rte_errno = ENOTSUP;
8760                 return NULL;
8761         }
8762         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8763         if (!mtb) {
8764                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8765                 return NULL;
8766         }
8767         /* Create meter count actions */
8768         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8769                 struct mlx5_flow_counter *cnt;
8770                 if (!fm->policer_stats.cnt[i])
8771                         continue;
8772                 cnt = flow_dv_counter_get_by_idx(dev,
8773                       fm->policer_stats.cnt[i], NULL);
8774                 mtb->count_actns[i] = cnt->action;
8775         }
8776         /* Create drop action. */
8777         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8778         if (!mtb->drop_actn) {
8779                 DRV_LOG(ERR, "Failed to create drop action.");
8780                 goto error_exit;
8781         }
8782         /* Egress meter table. */
8783         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8784         if (ret) {
8785                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8786                 goto error_exit;
8787         }
8788         /* Ingress meter table. */
8789         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8790         if (ret) {
8791                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8792                 goto error_exit;
8793         }
8794         /* FDB meter table. */
8795         if (priv->config.dv_esw_en) {
8796                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8797                                                  priv->mtr_color_reg);
8798                 if (ret) {
8799                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8800                         goto error_exit;
8801                 }
8802         }
8803         return mtb;
8804 error_exit:
8805         flow_dv_destroy_mtr_tbl(dev, mtb);
8806         return NULL;
8807 }
8808
8809 /**
8810  * Destroy domain policer rule.
8811  *
8812  * @param[in] dt
8813  *   Pointer to domain table.
8814  */
8815 static void
8816 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8817 {
8818         int i;
8819
8820         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8821                 if (dt->policer_rules[i]) {
8822                         claim_zero(mlx5_glue->dv_destroy_flow
8823                                   (dt->policer_rules[i]));
8824                         dt->policer_rules[i] = NULL;
8825                 }
8826         }
8827         if (dt->jump_actn) {
8828                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8829                 dt->jump_actn = NULL;
8830         }
8831 }
8832
8833 /**
8834  * Destroy policer rules.
8835  *
8836  * @param[in] dev
8837  *   Pointer to Ethernet device.
8838  * @param[in] fm
8839  *   Pointer to flow meter structure.
8840  * @param[in] attr
8841  *   Pointer to flow attributes.
8842  *
8843  * @return
8844  *   Always 0.
8845  */
8846 static int
8847 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8848                               const struct mlx5_flow_meter *fm,
8849                               const struct rte_flow_attr *attr)
8850 {
8851         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8852
8853         if (!mtb)
8854                 return 0;
8855         if (attr->egress)
8856                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8857         if (attr->ingress)
8858                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8859         if (attr->transfer)
8860                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8861         return 0;
8862 }
8863
8864 /**
8865  * Create specify domain meter policer rule.
8866  *
8867  * @param[in] fm
8868  *   Pointer to flow meter structure.
8869  * @param[in] mtb
8870  *   Pointer to DV meter table set.
8871  * @param[in] mtr_reg_c
8872  *   Color match REG_C.
8873  *
8874  * @return
8875  *   0 on success, -1 otherwise.
8876  */
8877 static int
8878 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8879                                     struct mlx5_meter_domain_info *dtb,
8880                                     uint8_t mtr_reg_c)
8881 {
8882         struct mlx5_flow_dv_match_params matcher = {
8883                 .size = sizeof(matcher.buf),
8884         };
8885         struct mlx5_flow_dv_match_params value = {
8886                 .size = sizeof(value.buf),
8887         };
8888         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8889         void *actions[METER_ACTIONS];
8890         int i;
8891
8892         /* Create jump action. */
8893         if (!dtb->jump_actn)
8894                 dtb->jump_actn =
8895                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
8896                                                         (dtb->sfx_tbl->obj);
8897         if (!dtb->jump_actn) {
8898                 DRV_LOG(ERR, "Failed to create policer jump action.");
8899                 goto error;
8900         }
8901         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8902                 int j = 0;
8903
8904                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8905                                        rte_col_2_mlx5_col(i), UINT8_MAX);
8906                 if (mtb->count_actns[i])
8907                         actions[j++] = mtb->count_actns[i];
8908                 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8909                         actions[j++] = mtb->drop_actn;
8910                 else
8911                         actions[j++] = dtb->jump_actn;
8912                 dtb->policer_rules[i] =
8913                         mlx5_glue->dv_create_flow(dtb->color_matcher,
8914                                                  (void *)&value,
8915                                                   j, actions);
8916                 if (!dtb->policer_rules[i]) {
8917                         DRV_LOG(ERR, "Failed to create policer rule.");
8918                         goto error;
8919                 }
8920         }
8921         return 0;
8922 error:
8923         rte_errno = errno;
8924         return -1;
8925 }
8926
8927 /**
8928  * Create policer rules.
8929  *
8930  * @param[in] dev
8931  *   Pointer to Ethernet device.
8932  * @param[in] fm
8933  *   Pointer to flow meter structure.
8934  * @param[in] attr
8935  *   Pointer to flow attributes.
8936  *
8937  * @return
8938  *   0 on success, -1 otherwise.
8939  */
8940 static int
8941 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8942                              struct mlx5_flow_meter *fm,
8943                              const struct rte_flow_attr *attr)
8944 {
8945         struct mlx5_priv *priv = dev->data->dev_private;
8946         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8947         int ret;
8948
8949         if (attr->egress) {
8950                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8951                                                 priv->mtr_color_reg);
8952                 if (ret) {
8953                         DRV_LOG(ERR, "Failed to create egress policer.");
8954                         goto error;
8955                 }
8956         }
8957         if (attr->ingress) {
8958                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8959                                                 priv->mtr_color_reg);
8960                 if (ret) {
8961                         DRV_LOG(ERR, "Failed to create ingress policer.");
8962                         goto error;
8963                 }
8964         }
8965         if (attr->transfer) {
8966                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8967                                                 priv->mtr_color_reg);
8968                 if (ret) {
8969                         DRV_LOG(ERR, "Failed to create transfer policer.");
8970                         goto error;
8971                 }
8972         }
8973         return 0;
8974 error:
8975         flow_dv_destroy_policer_rules(dev, fm, attr);
8976         return -1;
8977 }
8978
8979 /**
8980  * Query a devx counter.
8981  *
8982  * @param[in] dev
8983  *   Pointer to the Ethernet device structure.
8984  * @param[in] cnt
8985  *   Index to the flow counter.
8986  * @param[in] clear
8987  *   Set to clear the counter statistics.
8988  * @param[out] pkts
8989  *   The statistics value of packets.
8990  * @param[out] bytes
8991  *   The statistics value of bytes.
8992  *
8993  * @return
8994  *   0 on success, otherwise return -1.
8995  */
8996 static int
8997 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
8998                       uint64_t *pkts, uint64_t *bytes)
8999 {
9000         struct mlx5_priv *priv = dev->data->dev_private;
9001         struct mlx5_flow_counter *cnt;
9002         uint64_t inn_pkts, inn_bytes;
9003         int ret;
9004
9005         if (!priv->config.devx)
9006                 return -1;
9007
9008         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9009         if (ret)
9010                 return -1;
9011         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9012         *pkts = inn_pkts - cnt->hits;
9013         *bytes = inn_bytes - cnt->bytes;
9014         if (clear) {
9015                 cnt->hits = inn_pkts;
9016                 cnt->bytes = inn_bytes;
9017         }
9018         return 0;
9019 }
9020
9021 /*
9022  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9023  */
9024 static int
9025 flow_dv_translate(struct rte_eth_dev *dev,
9026                   struct mlx5_flow *dev_flow,
9027                   const struct rte_flow_attr *attr,
9028                   const struct rte_flow_item items[],
9029                   const struct rte_flow_action actions[],
9030                   struct rte_flow_error *error)
9031 {
9032         int ret;
9033
9034         flow_dv_shared_lock(dev);
9035         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9036         flow_dv_shared_unlock(dev);
9037         return ret;
9038 }
9039
9040 /*
9041  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9042  */
9043 static int
9044 flow_dv_apply(struct rte_eth_dev *dev,
9045               struct rte_flow *flow,
9046               struct rte_flow_error *error)
9047 {
9048         int ret;
9049
9050         flow_dv_shared_lock(dev);
9051         ret = __flow_dv_apply(dev, flow, error);
9052         flow_dv_shared_unlock(dev);
9053         return ret;
9054 }
9055
9056 /*
9057  * Mutex-protected thunk to lock-free __flow_dv_remove().
9058  */
9059 static void
9060 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9061 {
9062         flow_dv_shared_lock(dev);
9063         __flow_dv_remove(dev, flow);
9064         flow_dv_shared_unlock(dev);
9065 }
9066
9067 /*
9068  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9069  */
9070 static void
9071 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9072 {
9073         flow_dv_shared_lock(dev);
9074         __flow_dv_destroy(dev, flow);
9075         flow_dv_shared_unlock(dev);
9076 }
9077
9078 /*
9079  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9080  */
9081 static uint32_t
9082 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9083 {
9084         uint32_t cnt;
9085
9086         flow_dv_shared_lock(dev);
9087         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9088         flow_dv_shared_unlock(dev);
9089         return cnt;
9090 }
9091
9092 /*
9093  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9094  */
9095 static void
9096 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9097 {
9098         flow_dv_shared_lock(dev);
9099         flow_dv_counter_release(dev, cnt);
9100         flow_dv_shared_unlock(dev);
9101 }
9102
9103 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9104         .validate = flow_dv_validate,
9105         .prepare = flow_dv_prepare,
9106         .translate = flow_dv_translate,
9107         .apply = flow_dv_apply,
9108         .remove = flow_dv_remove,
9109         .destroy = flow_dv_destroy,
9110         .query = flow_dv_query,
9111         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9112         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9113         .create_policer_rules = flow_dv_create_policer_rules,
9114         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9115         .counter_alloc = flow_dv_counter_allocate,
9116         .counter_free = flow_dv_counter_free,
9117         .counter_query = flow_dv_counter_query,
9118 };
9119
9120 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */