drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static int
  77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  78                              struct mlx5_flow_tbl_resource *tbl);
  79
  80 /**
  81  * Initialize flow attributes structure according to flow items' types.
  82  *
  83  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  84  * mode. For tunnel mode, the items to be modified are the outermost ones.
  85  *
  86  * @param[in] item
  87  *   Pointer to item specification.
  88  * @param[out] attr
  89  *   Pointer to flow attributes structure.
  90  * @param[in] dev_flow
  91  *   Pointer to the sub flow.
  92  * @param[in] tunnel_decap
  93  *   Whether action is after tunnel decapsulation.
  94  */
  95 static void
  96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  97                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  98 {
  99         uint64_t layers = dev_flow->handle->layers;
 100
 101         /*
 102          * If layers is already initialized, it means this dev_flow is the
 103          * suffix flow, the layers flags is set by the prefix flow. Need to
 104          * use the layer flags from prefix flow as the suffix flow may not
 105          * have the user defined items as the flow is split.
 106          */
 107         if (layers) {
 108                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 109                         attr->ipv4 = 1;
 110                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 111                         attr->ipv6 = 1;
 112                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 113                         attr->tcp = 1;
 114                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 115                         attr->udp = 1;
 116                 attr->valid = 1;
 117                 return;
 118         }
 119         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 120                 uint8_t next_protocol = 0xff;
 121                 switch (item->type) {
 122                 case RTE_FLOW_ITEM_TYPE_GRE:
 123                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 126                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 127                 case RTE_FLOW_ITEM_TYPE_MPLS:
 128                         if (tunnel_decap)
 129                                 attr->attr = 0;
 130                         break;
 131                 case RTE_FLOW_ITEM_TYPE_IPV4:
 132                         if (!attr->ipv6)
 133                                 attr->ipv4 = 1;
 134                         if (item->mask != NULL &&
 135                             ((const struct rte_flow_item_ipv4 *)
 136                             item->mask)->hdr.next_proto_id)
 137                                 next_protocol =
 138                                     ((const struct rte_flow_item_ipv4 *)
 139                                       (item->spec))->hdr.next_proto_id &
 140                                     ((const struct rte_flow_item_ipv4 *)
 141                                       (item->mask))->hdr.next_proto_id;
 142                         if ((next_protocol == IPPROTO_IPIP ||
 143                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 144                                 attr->attr = 0;
 145                         break;
 146                 case RTE_FLOW_ITEM_TYPE_IPV6:
 147                         if (!attr->ipv4)
 148                                 attr->ipv6 = 1;
 149                         if (item->mask != NULL &&
 150                             ((const struct rte_flow_item_ipv6 *)
 151                             item->mask)->hdr.proto)
 152                                 next_protocol =
 153                                     ((const struct rte_flow_item_ipv6 *)
 154                                       (item->spec))->hdr.proto &
 155                                     ((const struct rte_flow_item_ipv6 *)
 156                                       (item->mask))->hdr.proto;
 157                         if ((next_protocol == IPPROTO_IPIP ||
 158                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 159                                 attr->attr = 0;
 160                         break;
 161                 case RTE_FLOW_ITEM_TYPE_UDP:
 162                         if (!attr->tcp)
 163                                 attr->udp = 1;
 164                         break;
 165                 case RTE_FLOW_ITEM_TYPE_TCP:
 166                         if (!attr->udp)
 167                                 attr->tcp = 1;
 168                         break;
 169                 default:
 170                         break;
 171                 }
 172         }
 173         attr->valid = 1;
 174 }
 175
 176 /**
 177  * Convert rte_mtr_color to mlx5 color.
 178  *
 179  * @param[in] rcol
 180  *   rte_mtr_color.
 181  *
 182  * @return
 183  *   mlx5 color.
 184  */
 185 static int
 186 rte_col_2_mlx5_col(enum rte_color rcol)
 187 {
 188         switch (rcol) {
 189         case RTE_COLOR_GREEN:
 190                 return MLX5_FLOW_COLOR_GREEN;
 191         case RTE_COLOR_YELLOW:
 192                 return MLX5_FLOW_COLOR_YELLOW;
 193         case RTE_COLOR_RED:
 194                 return MLX5_FLOW_COLOR_RED;
 195         default:
 196                 break;
 197         }
 198         return MLX5_FLOW_COLOR_UNDEFINED;
 199 }
 200
 201 struct field_modify_info {
 202         uint32_t size; /* Size of field in protocol header, in bytes. */
 203         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 204         enum mlx5_modification_field id;
 205 };
 206
 207 struct field_modify_info modify_eth[] = {
 208         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 209         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 210         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 211         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 212         {0, 0, 0},
 213 };
 214
 215 struct field_modify_info modify_vlan_out_first_vid[] = {
 216         /* Size in bits !!! */
 217         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 218         {0, 0, 0},
 219 };
 220
 221 struct field_modify_info modify_ipv4[] = {
 222         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 223         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 224         {4, 12, MLX5_MODI_OUT_SIPV4},
 225         {4, 16, MLX5_MODI_OUT_DIPV4},
 226         {0, 0, 0},
 227 };
 228
 229 struct field_modify_info modify_ipv6[] = {
 230         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 231         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 232         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 233         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 234         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 235         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 236         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 237         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 238         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 239         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 240         {0, 0, 0},
 241 };
 242
 243 struct field_modify_info modify_udp[] = {
 244         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 245         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 246         {0, 0, 0},
 247 };
 248
 249 struct field_modify_info modify_tcp[] = {
 250         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 251         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 252         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 253         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 254         {0, 0, 0},
 255 };
 256
 257 static void
 258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 259                           uint8_t next_protocol, uint64_t *item_flags,
 260                           int *tunnel)
 261 {
 262         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 263                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 264         if (next_protocol == IPPROTO_IPIP) {
 265                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 266                 *tunnel = 1;
 267         }
 268         if (next_protocol == IPPROTO_IPV6) {
 269                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 270                 *tunnel = 1;
 271         }
 272 }
 273
 274 /**
 275  * Acquire the synchronizing object to protect multithreaded access
 276  * to shared dv context. Lock occurs only if context is actually
 277  * shared, i.e. we have multiport IB device and representors are
 278  * created.
 279  *
 280  * @param[in] dev
 281  *   Pointer to the rte_eth_dev structure.
 282  */
 283 static void
 284 flow_dv_shared_lock(struct rte_eth_dev *dev)
 285 {
 286         struct mlx5_priv *priv = dev->data->dev_private;
 287         struct mlx5_ibv_shared *sh = priv->sh;
 288
 289         if (sh->dv_refcnt > 1) {
 290                 int ret;
 291
 292                 ret = pthread_mutex_lock(&sh->dv_mutex);
 293                 MLX5_ASSERT(!ret);
 294                 (void)ret;
 295         }
 296 }
 297
 298 static void
 299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 300 {
 301         struct mlx5_priv *priv = dev->data->dev_private;
 302         struct mlx5_ibv_shared *sh = priv->sh;
 303
 304         if (sh->dv_refcnt > 1) {
 305                 int ret;
 306
 307                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 308                 MLX5_ASSERT(!ret);
 309                 (void)ret;
 310         }
 311 }
 312
 313 /* Update VLAN's VID/PCP based on input rte_flow_action.
 314  *
 315  * @param[in] action
 316  *   Pointer to struct rte_flow_action.
 317  * @param[out] vlan
 318  *   Pointer to struct rte_vlan_hdr.
 319  */
 320 static void
 321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 322                          struct rte_vlan_hdr *vlan)
 323 {
 324         uint16_t vlan_tci;
 325         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 326                 vlan_tci =
 327                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 328                                                action->conf)->vlan_pcp;
 329                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 330                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 331                 vlan->vlan_tci |= vlan_tci;
 332         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 334                 vlan->vlan_tci |= rte_be_to_cpu_16
 335                     (((const struct rte_flow_action_of_set_vlan_vid *)
 336                                              action->conf)->vlan_vid);
 337         }
 338 }
 339
 340 /**
 341  * Fetch 1, 2, 3 or 4 byte field from the byte array
 342  * and return as unsigned integer in host-endian format.
 343  *
 344  * @param[in] data
 345  *   Pointer to data array.
 346  * @param[in] size
 347  *   Size of field to extract.
 348  *
 349  * @return
 350  *   converted field in host endian format.
 351  */
 352 static inline uint32_t
 353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 354 {
 355         uint32_t ret;
 356
 357         switch (size) {
 358         case 1:
 359                 ret = *data;
 360                 break;
 361         case 2:
 362                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 363                 break;
 364         case 3:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 367                 break;
 368         case 4:
 369                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 370                 break;
 371         default:
 372                 MLX5_ASSERT(false);
 373                 ret = 0;
 374                 break;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Convert modify-header action to DV specification.
 381  *
 382  * Data length of each action is determined by provided field description
 383  * and the item mask. Data bit offset and width of each action is determined
 384  * by provided item mask.
 385  *
 386  * @param[in] item
 387  *   Pointer to item specification.
 388  * @param[in] field
 389  *   Pointer to field modification information.
 390  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 393  * @param[in] dcopy
 394  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 395  *   Negative offset value sets the same offset as source offset.
 396  *   size field is ignored, value is taken from source field.
 397  * @param[in,out] resource
 398  *   Pointer to the modify-header resource.
 399  * @param[in] type
 400  *   Type of modification.
 401  * @param[out] error
 402  *   Pointer to the error structure.
 403  *
 404  * @return
 405  *   0 on success, a negative errno value otherwise and rte_errno is set.
 406  */
 407 static int
 408 flow_dv_convert_modify_action(struct rte_flow_item *item,
 409                               struct field_modify_info *field,
 410                               struct field_modify_info *dcopy,
 411                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 412                               uint32_t type, struct rte_flow_error *error)
 413 {
 414         uint32_t i = resource->actions_num;
 415         struct mlx5_modification_cmd *actions = resource->actions;
 416
 417         /*
 418          * The item and mask are provided in big-endian format.
 419          * The fields should be presented as in big-endian format either.
 420          * Mask must be always present, it defines the actual field width.
 421          */
 422         MLX5_ASSERT(item->mask);
 423         MLX5_ASSERT(field->size);
 424         do {
 425                 unsigned int size_b;
 426                 unsigned int off_b;
 427                 uint32_t mask;
 428                 uint32_t data;
 429
 430                 if (i >= MLX5_MAX_MODIFY_NUM)
 431                         return rte_flow_error_set(error, EINVAL,
 432                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 433                                  "too many items to modify");
 434                 /* Fetch variable byte size mask from the array. */
 435                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 436                                            field->offset, field->size);
 437                 if (!mask) {
 438                         ++field;
 439                         continue;
 440                 }
 441                 /* Deduce actual data width in bits from mask value. */
 442                 off_b = rte_bsf32(mask);
 443                 size_b = sizeof(uint32_t) * CHAR_BIT -
 444                          off_b - __builtin_clz(mask);
 445                 MLX5_ASSERT(size_b);
 446                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 447                 actions[i] = (struct mlx5_modification_cmd) {
 448                         .action_type = type,
 449                         .field = field->id,
 450                         .offset = off_b,
 451                         .length = size_b,
 452                 };
 453                 /* Convert entire record to expected big-endian format. */
 454                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 455                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 456                         MLX5_ASSERT(dcopy);
 457                         actions[i].dst_field = dcopy->id;
 458                         actions[i].dst_offset =
 459                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 460                         /* Convert entire record to big-endian format. */
 461                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 462                 } else {
 463                         MLX5_ASSERT(item->spec);
 464                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 465                                                    field->offset, field->size);
 466                         /* Shift out the trailing masked bits from data. */
 467                         data = (data & mask) >> off_b;
 468                         actions[i].data1 = rte_cpu_to_be_32(data);
 469                 }
 470                 ++i;
 471                 ++field;
 472         } while (field->size);
 473         if (resource->actions_num == i)
 474                 return rte_flow_error_set(error, EINVAL,
 475                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 476                                           "invalid modification flow item");
 477         resource->actions_num = i;
 478         return 0;
 479 }
 480
 481 /**
 482  * Convert modify-header set IPv4 address action to DV specification.
 483  *
 484  * @param[in,out] resource
 485  *   Pointer to the modify-header resource.
 486  * @param[in] action
 487  *   Pointer to action specification.
 488  * @param[out] error
 489  *   Pointer to the error structure.
 490  *
 491  * @return
 492  *   0 on success, a negative errno value otherwise and rte_errno is set.
 493  */
 494 static int
 495 flow_dv_convert_action_modify_ipv4
 496                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 497                          const struct rte_flow_action *action,
 498                          struct rte_flow_error *error)
 499 {
 500         const struct rte_flow_action_set_ipv4 *conf =
 501                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 502         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 503         struct rte_flow_item_ipv4 ipv4;
 504         struct rte_flow_item_ipv4 ipv4_mask;
 505
 506         memset(&ipv4, 0, sizeof(ipv4));
 507         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 508         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 509                 ipv4.hdr.src_addr = conf->ipv4_addr;
 510                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 511         } else {
 512                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 514         }
 515         item.spec = &ipv4;
 516         item.mask = &ipv4_mask;
 517         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 518                                              MLX5_MODIFICATION_TYPE_SET, error);
 519 }
 520
 521 /**
 522  * Convert modify-header set IPv6 address action to DV specification.
 523  *
 524  * @param[in,out] resource
 525  *   Pointer to the modify-header resource.
 526  * @param[in] action
 527  *   Pointer to action specification.
 528  * @param[out] error
 529  *   Pointer to the error structure.
 530  *
 531  * @return
 532  *   0 on success, a negative errno value otherwise and rte_errno is set.
 533  */
 534 static int
 535 flow_dv_convert_action_modify_ipv6
 536                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 537                          const struct rte_flow_action *action,
 538                          struct rte_flow_error *error)
 539 {
 540         const struct rte_flow_action_set_ipv6 *conf =
 541                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 542         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 543         struct rte_flow_item_ipv6 ipv6;
 544         struct rte_flow_item_ipv6 ipv6_mask;
 545
 546         memset(&ipv6, 0, sizeof(ipv6));
 547         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 548         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 549                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 550                        sizeof(ipv6.hdr.src_addr));
 551                 memcpy(&ipv6_mask.hdr.src_addr,
 552                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554         } else {
 555                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 556                        sizeof(ipv6.hdr.dst_addr));
 557                 memcpy(&ipv6_mask.hdr.dst_addr,
 558                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560         }
 561         item.spec = &ipv6;
 562         item.mask = &ipv6_mask;
 563         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 564                                              MLX5_MODIFICATION_TYPE_SET, error);
 565 }
 566
 567 /**
 568  * Convert modify-header set MAC address action to DV specification.
 569  *
 570  * @param[in,out] resource
 571  *   Pointer to the modify-header resource.
 572  * @param[in] action
 573  *   Pointer to action specification.
 574  * @param[out] error
 575  *   Pointer to the error structure.
 576  *
 577  * @return
 578  *   0 on success, a negative errno value otherwise and rte_errno is set.
 579  */
 580 static int
 581 flow_dv_convert_action_modify_mac
 582                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 583                          const struct rte_flow_action *action,
 584                          struct rte_flow_error *error)
 585 {
 586         const struct rte_flow_action_set_mac *conf =
 587                 (const struct rte_flow_action_set_mac *)(action->conf);
 588         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 589         struct rte_flow_item_eth eth;
 590         struct rte_flow_item_eth eth_mask;
 591
 592         memset(&eth, 0, sizeof(eth));
 593         memset(&eth_mask, 0, sizeof(eth_mask));
 594         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 595                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 596                        sizeof(eth.src.addr_bytes));
 597                 memcpy(&eth_mask.src.addr_bytes,
 598                        &rte_flow_item_eth_mask.src.addr_bytes,
 599                        sizeof(eth_mask.src.addr_bytes));
 600         } else {
 601                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 602                        sizeof(eth.dst.addr_bytes));
 603                 memcpy(&eth_mask.dst.addr_bytes,
 604                        &rte_flow_item_eth_mask.dst.addr_bytes,
 605                        sizeof(eth_mask.dst.addr_bytes));
 606         }
 607         item.spec = &eth;
 608         item.mask = &eth_mask;
 609         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 610                                              MLX5_MODIFICATION_TYPE_SET, error);
 611 }
 612
 613 /**
 614  * Convert modify-header set VLAN VID action to DV specification.
 615  *
 616  * @param[in,out] resource
 617  *   Pointer to the modify-header resource.
 618  * @param[in] action
 619  *   Pointer to action specification.
 620  * @param[out] error
 621  *   Pointer to the error structure.
 622  *
 623  * @return
 624  *   0 on success, a negative errno value otherwise and rte_errno is set.
 625  */
 626 static int
 627 flow_dv_convert_action_modify_vlan_vid
 628                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 629                          const struct rte_flow_action *action,
 630                          struct rte_flow_error *error)
 631 {
 632         const struct rte_flow_action_of_set_vlan_vid *conf =
 633                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 634         int i = resource->actions_num;
 635         struct mlx5_modification_cmd *actions = resource->actions;
 636         struct field_modify_info *field = modify_vlan_out_first_vid;
 637
 638         if (i >= MLX5_MAX_MODIFY_NUM)
 639                 return rte_flow_error_set(error, EINVAL,
 640                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 641                          "too many items to modify");
 642         actions[i] = (struct mlx5_modification_cmd) {
 643                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 644                 .field = field->id,
 645                 .length = field->size,
 646                 .offset = field->offset,
 647         };
 648         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 649         actions[i].data1 = conf->vlan_vid;
 650         actions[i].data1 = actions[i].data1 << 16;
 651         resource->actions_num = ++i;
 652         return 0;
 653 }
 654
 655 /**
 656  * Convert modify-header set TP action to DV specification.
 657  *
 658  * @param[in,out] resource
 659  *   Pointer to the modify-header resource.
 660  * @param[in] action
 661  *   Pointer to action specification.
 662  * @param[in] items
 663  *   Pointer to rte_flow_item objects list.
 664  * @param[in] attr
 665  *   Pointer to flow attributes structure.
 666  * @param[in] dev_flow
 667  *   Pointer to the sub flow.
 668  * @param[in] tunnel_decap
 669  *   Whether action is after tunnel decapsulation.
 670  * @param[out] error
 671  *   Pointer to the error structure.
 672  *
 673  * @return
 674  *   0 on success, a negative errno value otherwise and rte_errno is set.
 675  */
 676 static int
 677 flow_dv_convert_action_modify_tp
 678                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 679                          const struct rte_flow_action *action,
 680                          const struct rte_flow_item *items,
 681                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 682                          bool tunnel_decap, struct rte_flow_error *error)
 683 {
 684         const struct rte_flow_action_set_tp *conf =
 685                 (const struct rte_flow_action_set_tp *)(action->conf);
 686         struct rte_flow_item item;
 687         struct rte_flow_item_udp udp;
 688         struct rte_flow_item_udp udp_mask;
 689         struct rte_flow_item_tcp tcp;
 690         struct rte_flow_item_tcp tcp_mask;
 691         struct field_modify_info *field;
 692
 693         if (!attr->valid)
 694                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 695         if (attr->udp) {
 696                 memset(&udp, 0, sizeof(udp));
 697                 memset(&udp_mask, 0, sizeof(udp_mask));
 698                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 699                         udp.hdr.src_port = conf->port;
 700                         udp_mask.hdr.src_port =
 701                                         rte_flow_item_udp_mask.hdr.src_port;
 702                 } else {
 703                         udp.hdr.dst_port = conf->port;
 704                         udp_mask.hdr.dst_port =
 705                                         rte_flow_item_udp_mask.hdr.dst_port;
 706                 }
 707                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 708                 item.spec = &udp;
 709                 item.mask = &udp_mask;
 710                 field = modify_udp;
 711         } else {
 712                 MLX5_ASSERT(attr->tcp);
 713                 memset(&tcp, 0, sizeof(tcp));
 714                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 715                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 716                         tcp.hdr.src_port = conf->port;
 717                         tcp_mask.hdr.src_port =
 718                                         rte_flow_item_tcp_mask.hdr.src_port;
 719                 } else {
 720                         tcp.hdr.dst_port = conf->port;
 721                         tcp_mask.hdr.dst_port =
 722                                         rte_flow_item_tcp_mask.hdr.dst_port;
 723                 }
 724                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 725                 item.spec = &tcp;
 726                 item.mask = &tcp_mask;
 727                 field = modify_tcp;
 728         }
 729         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 730                                              MLX5_MODIFICATION_TYPE_SET, error);
 731 }
 732
 733 /**
 734  * Convert modify-header set TTL action to DV specification.
 735  *
 736  * @param[in,out] resource
 737  *   Pointer to the modify-header resource.
 738  * @param[in] action
 739  *   Pointer to action specification.
 740  * @param[in] items
 741  *   Pointer to rte_flow_item objects list.
 742  * @param[in] attr
 743  *   Pointer to flow attributes structure.
 744  * @param[in] dev_flow
 745  *   Pointer to the sub flow.
 746  * @param[in] tunnel_decap
 747  *   Whether action is after tunnel decapsulation.
 748  * @param[out] error
 749  *   Pointer to the error structure.
 750  *
 751  * @return
 752  *   0 on success, a negative errno value otherwise and rte_errno is set.
 753  */
 754 static int
 755 flow_dv_convert_action_modify_ttl
 756                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 757                          const struct rte_flow_action *action,
 758                          const struct rte_flow_item *items,
 759                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 760                          bool tunnel_decap, struct rte_flow_error *error)
 761 {
 762         const struct rte_flow_action_set_ttl *conf =
 763                 (const struct rte_flow_action_set_ttl *)(action->conf);
 764         struct rte_flow_item item;
 765         struct rte_flow_item_ipv4 ipv4;
 766         struct rte_flow_item_ipv4 ipv4_mask;
 767         struct rte_flow_item_ipv6 ipv6;
 768         struct rte_flow_item_ipv6 ipv6_mask;
 769         struct field_modify_info *field;
 770
 771         if (!attr->valid)
 772                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 773         if (attr->ipv4) {
 774                 memset(&ipv4, 0, sizeof(ipv4));
 775                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 776                 ipv4.hdr.time_to_live = conf->ttl_value;
 777                 ipv4_mask.hdr.time_to_live = 0xFF;
 778                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 779                 item.spec = &ipv4;
 780                 item.mask = &ipv4_mask;
 781                 field = modify_ipv4;
 782         } else {
 783                 MLX5_ASSERT(attr->ipv6);
 784                 memset(&ipv6, 0, sizeof(ipv6));
 785                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 786                 ipv6.hdr.hop_limits = conf->ttl_value;
 787                 ipv6_mask.hdr.hop_limits = 0xFF;
 788                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 789                 item.spec = &ipv6;
 790                 item.mask = &ipv6_mask;
 791                 field = modify_ipv6;
 792         }
 793         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 794                                              MLX5_MODIFICATION_TYPE_SET, error);
 795 }
 796
 797 /**
 798  * Convert modify-header decrement TTL action to DV specification.
 799  *
 800  * @param[in,out] resource
 801  *   Pointer to the modify-header resource.
 802  * @param[in] action
 803  *   Pointer to action specification.
 804  * @param[in] items
 805  *   Pointer to rte_flow_item objects list.
 806  * @param[in] attr
 807  *   Pointer to flow attributes structure.
 808  * @param[in] dev_flow
 809  *   Pointer to the sub flow.
 810  * @param[in] tunnel_decap
 811  *   Whether action is after tunnel decapsulation.
 812  * @param[out] error
 813  *   Pointer to the error structure.
 814  *
 815  * @return
 816  *   0 on success, a negative errno value otherwise and rte_errno is set.
 817  */
 818 static int
 819 flow_dv_convert_action_modify_dec_ttl
 820                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 821                          const struct rte_flow_item *items,
 822                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 823                          bool tunnel_decap, struct rte_flow_error *error)
 824 {
 825         struct rte_flow_item item;
 826         struct rte_flow_item_ipv4 ipv4;
 827         struct rte_flow_item_ipv4 ipv4_mask;
 828         struct rte_flow_item_ipv6 ipv6;
 829         struct rte_flow_item_ipv6 ipv6_mask;
 830         struct field_modify_info *field;
 831
 832         if (!attr->valid)
 833                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 834         if (attr->ipv4) {
 835                 memset(&ipv4, 0, sizeof(ipv4));
 836                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 837                 ipv4.hdr.time_to_live = 0xFF;
 838                 ipv4_mask.hdr.time_to_live = 0xFF;
 839                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 840                 item.spec = &ipv4;
 841                 item.mask = &ipv4_mask;
 842                 field = modify_ipv4;
 843         } else {
 844                 MLX5_ASSERT(attr->ipv6);
 845                 memset(&ipv6, 0, sizeof(ipv6));
 846                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 847                 ipv6.hdr.hop_limits = 0xFF;
 848                 ipv6_mask.hdr.hop_limits = 0xFF;
 849                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 850                 item.spec = &ipv6;
 851                 item.mask = &ipv6_mask;
 852                 field = modify_ipv6;
 853         }
 854         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 855                                              MLX5_MODIFICATION_TYPE_ADD, error);
 856 }
 857
 858 /**
 859  * Convert modify-header increment/decrement TCP Sequence number
 860  * to DV specification.
 861  *
 862  * @param[in,out] resource
 863  *   Pointer to the modify-header resource.
 864  * @param[in] action
 865  *   Pointer to action specification.
 866  * @param[out] error
 867  *   Pointer to the error structure.
 868  *
 869  * @return
 870  *   0 on success, a negative errno value otherwise and rte_errno is set.
 871  */
 872 static int
 873 flow_dv_convert_action_modify_tcp_seq
 874                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 875                          const struct rte_flow_action *action,
 876                          struct rte_flow_error *error)
 877 {
 878         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 879         uint64_t value = rte_be_to_cpu_32(*conf);
 880         struct rte_flow_item item;
 881         struct rte_flow_item_tcp tcp;
 882         struct rte_flow_item_tcp tcp_mask;
 883
 884         memset(&tcp, 0, sizeof(tcp));
 885         memset(&tcp_mask, 0, sizeof(tcp_mask));
 886         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 887                 /*
 888                  * The HW has no decrement operation, only increment operation.
 889                  * To simulate decrement X from Y using increment operation
 890                  * we need to add UINT32_MAX X times to Y.
 891                  * Each adding of UINT32_MAX decrements Y by 1.
 892                  */
 893                 value *= UINT32_MAX;
 894         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 895         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 896         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 897         item.spec = &tcp;
 898         item.mask = &tcp_mask;
 899         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 900                                              MLX5_MODIFICATION_TYPE_ADD, error);
 901 }
 902
 903 /**
 904  * Convert modify-header increment/decrement TCP Acknowledgment number
 905  * to DV specification.
 906  *
 907  * @param[in,out] resource
 908  *   Pointer to the modify-header resource.
 909  * @param[in] action
 910  *   Pointer to action specification.
 911  * @param[out] error
 912  *   Pointer to the error structure.
 913  *
 914  * @return
 915  *   0 on success, a negative errno value otherwise and rte_errno is set.
 916  */
 917 static int
 918 flow_dv_convert_action_modify_tcp_ack
 919                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 920                          const struct rte_flow_action *action,
 921                          struct rte_flow_error *error)
 922 {
 923         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 924         uint64_t value = rte_be_to_cpu_32(*conf);
 925         struct rte_flow_item item;
 926         struct rte_flow_item_tcp tcp;
 927         struct rte_flow_item_tcp tcp_mask;
 928
 929         memset(&tcp, 0, sizeof(tcp));
 930         memset(&tcp_mask, 0, sizeof(tcp_mask));
 931         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 932                 /*
 933                  * The HW has no decrement operation, only increment operation.
 934                  * To simulate decrement X from Y using increment operation
 935                  * we need to add UINT32_MAX X times to Y.
 936                  * Each adding of UINT32_MAX decrements Y by 1.
 937                  */
 938                 value *= UINT32_MAX;
 939         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 940         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 941         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 942         item.spec = &tcp;
 943         item.mask = &tcp_mask;
 944         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 945                                              MLX5_MODIFICATION_TYPE_ADD, error);
 946 }
 947
 948 static enum mlx5_modification_field reg_to_field[] = {
 949         [REG_NONE] = MLX5_MODI_OUT_NONE,
 950         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 951         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 952         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 953         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 954         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 955         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 956         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 957         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 958         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 959         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 960 };
 961
 962 /**
 963  * Convert register set to DV specification.
 964  *
 965  * @param[in,out] resource
 966  *   Pointer to the modify-header resource.
 967  * @param[in] action
 968  *   Pointer to action specification.
 969  * @param[out] error
 970  *   Pointer to the error structure.
 971  *
 972  * @return
 973  *   0 on success, a negative errno value otherwise and rte_errno is set.
 974  */
 975 static int
 976 flow_dv_convert_action_set_reg
 977                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 978                          const struct rte_flow_action *action,
 979                          struct rte_flow_error *error)
 980 {
 981         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 982         struct mlx5_modification_cmd *actions = resource->actions;
 983         uint32_t i = resource->actions_num;
 984
 985         if (i >= MLX5_MAX_MODIFY_NUM)
 986                 return rte_flow_error_set(error, EINVAL,
 987                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 988                                           "too many items to modify");
 989         MLX5_ASSERT(conf->id != REG_NONE);
 990         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 991         actions[i] = (struct mlx5_modification_cmd) {
 992                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 993                 .field = reg_to_field[conf->id],
 994         };
 995         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 996         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 997         ++i;
 998         resource->actions_num = i;
 999         return 0;
1000 }
1001
1002 /**
1003  * Convert SET_TAG action to DV specification.
1004  *
1005  * @param[in] dev
1006  *   Pointer to the rte_eth_dev structure.
1007  * @param[in,out] resource
1008  *   Pointer to the modify-header resource.
1009  * @param[in] conf
1010  *   Pointer to action specification.
1011  * @param[out] error
1012  *   Pointer to the error structure.
1013  *
1014  * @return
1015  *   0 on success, a negative errno value otherwise and rte_errno is set.
1016  */
1017 static int
1018 flow_dv_convert_action_set_tag
1019                         (struct rte_eth_dev *dev,
1020                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1021                          const struct rte_flow_action_set_tag *conf,
1022                          struct rte_flow_error *error)
1023 {
1024         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026         struct rte_flow_item item = {
1027                 .spec = &data,
1028                 .mask = &mask,
1029         };
1030         struct field_modify_info reg_c_x[] = {
1031                 [1] = {0, 0, 0},
1032         };
1033         enum mlx5_modification_field reg_type;
1034         int ret;
1035
1036         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1037         if (ret < 0)
1038                 return ret;
1039         MLX5_ASSERT(ret != REG_NONE);
1040         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041         reg_type = reg_to_field[ret];
1042         MLX5_ASSERT(reg_type > 0);
1043         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045                                              MLX5_MODIFICATION_TYPE_SET, error);
1046 }
1047
1048 /**
1049  * Convert internal COPY_REG action to DV specification.
1050  *
1051  * @param[in] dev
1052  *   Pointer to the rte_eth_dev structure.
1053  * @param[in,out] res
1054  *   Pointer to the modify-header resource.
1055  * @param[in] action
1056  *   Pointer to action specification.
1057  * @param[out] error
1058  *   Pointer to the error structure.
1059  *
1060  * @return
1061  *   0 on success, a negative errno value otherwise and rte_errno is set.
1062  */
1063 static int
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1066                                  const struct rte_flow_action *action,
1067                                  struct rte_flow_error *error)
1068 {
1069         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071         struct rte_flow_item item = {
1072                 .spec = NULL,
1073                 .mask = &mask,
1074         };
1075         struct field_modify_info reg_src[] = {
1076                 {4, 0, reg_to_field[conf->src]},
1077                 {0, 0, 0},
1078         };
1079         struct field_modify_info reg_dst = {
1080                 .offset = 0,
1081                 .id = reg_to_field[conf->dst],
1082         };
1083         /* Adjust reg_c[0] usage according to reported mask. */
1084         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085                 struct mlx5_priv *priv = dev->data->dev_private;
1086                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087
1088                 MLX5_ASSERT(reg_c0);
1089                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090                 if (conf->dst == REG_C_0) {
1091                         /* Copy to reg_c[0], within mask only. */
1092                         reg_dst.offset = rte_bsf32(reg_c0);
1093                         /*
1094                          * Mask is ignoring the enianness, because
1095                          * there is no conversion in datapath.
1096                          */
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098                         /* Copy from destination lower bits to reg_c[0]. */
1099                         mask = reg_c0 >> reg_dst.offset;
1100 #else
1101                         /* Copy from destination upper bits to reg_c[0]. */
1102                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103                                           rte_fls_u32(reg_c0));
1104 #endif
1105                 } else {
1106                         mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108                         /* Copy from reg_c[0] to destination lower bits. */
1109                         reg_dst.offset = 0;
1110 #else
1111                         /* Copy from reg_c[0] to destination upper bits. */
1112                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113                                          (rte_fls_u32(reg_c0) -
1114                                           rte_bsf32(reg_c0));
1115 #endif
1116                 }
1117         }
1118         return flow_dv_convert_modify_action(&item,
1119                                              reg_src, &reg_dst, res,
1120                                              MLX5_MODIFICATION_TYPE_COPY,
1121                                              error);
1122 }
1123
1124 /**
1125  * Convert MARK action to DV specification. This routine is used
1126  * in extensive metadata only and requires metadata register to be
1127  * handled. In legacy mode hardware tag resource is engaged.
1128  *
1129  * @param[in] dev
1130  *   Pointer to the rte_eth_dev structure.
1131  * @param[in] conf
1132  *   Pointer to MARK action specification.
1133  * @param[in,out] resource
1134  *   Pointer to the modify-header resource.
1135  * @param[out] error
1136  *   Pointer to the error structure.
1137  *
1138  * @return
1139  *   0 on success, a negative errno value otherwise and rte_errno is set.
1140  */
1141 static int
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143                             const struct rte_flow_action_mark *conf,
1144                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1145                             struct rte_flow_error *error)
1146 {
1147         struct mlx5_priv *priv = dev->data->dev_private;
1148         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149                                            priv->sh->dv_mark_mask);
1150         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151         struct rte_flow_item item = {
1152                 .spec = &data,
1153                 .mask = &mask,
1154         };
1155         struct field_modify_info reg_c_x[] = {
1156                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1157                 {0, 0, 0},
1158         };
1159         int reg;
1160
1161         if (!mask)
1162                 return rte_flow_error_set(error, EINVAL,
1163                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164                                           NULL, "zero mark action mask");
1165         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1166         if (reg < 0)
1167                 return reg;
1168         MLX5_ASSERT(reg > 0);
1169         if (reg == REG_C_0) {
1170                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172
1173                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175                 mask = rte_cpu_to_be_32(mask << shl_c0);
1176         }
1177         reg_c_x[0].id = reg_to_field[reg];
1178         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179                                              MLX5_MODIFICATION_TYPE_SET, error);
1180 }
1181
1182 /**
1183  * Get metadata register index for specified steering domain.
1184  *
1185  * @param[in] dev
1186  *   Pointer to the rte_eth_dev structure.
1187  * @param[in] attr
1188  *   Attributes of flow to determine steering domain.
1189  * @param[out] error
1190  *   Pointer to the error structure.
1191  *
1192  * @return
1193  *   positive index on success, a negative errno value otherwise
1194  *   and rte_errno is set.
1195  */
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198                          const struct rte_flow_attr *attr,
1199                          struct rte_flow_error *error)
1200 {
1201         int reg =
1202                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1203                                           MLX5_METADATA_FDB :
1204                                             attr->egress ?
1205                                             MLX5_METADATA_TX :
1206                                             MLX5_METADATA_RX, 0, error);
1207         if (reg < 0)
1208                 return rte_flow_error_set(error,
1209                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210                                           NULL, "unavailable "
1211                                           "metadata register");
1212         return reg;
1213 }
1214
1215 /**
1216  * Convert SET_META action to DV specification.
1217  *
1218  * @param[in] dev
1219  *   Pointer to the rte_eth_dev structure.
1220  * @param[in,out] resource
1221  *   Pointer to the modify-header resource.
1222  * @param[in] attr
1223  *   Attributes of flow that includes this item.
1224  * @param[in] conf
1225  *   Pointer to action specification.
1226  * @param[out] error
1227  *   Pointer to the error structure.
1228  *
1229  * @return
1230  *   0 on success, a negative errno value otherwise and rte_errno is set.
1231  */
1232 static int
1233 flow_dv_convert_action_set_meta
1234                         (struct rte_eth_dev *dev,
1235                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1236                          const struct rte_flow_attr *attr,
1237                          const struct rte_flow_action_set_meta *conf,
1238                          struct rte_flow_error *error)
1239 {
1240         uint32_t data = conf->data;
1241         uint32_t mask = conf->mask;
1242         struct rte_flow_item item = {
1243                 .spec = &data,
1244                 .mask = &mask,
1245         };
1246         struct field_modify_info reg_c_x[] = {
1247                 [1] = {0, 0, 0},
1248         };
1249         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250
1251         if (reg < 0)
1252                 return reg;
1253         /*
1254          * In datapath code there is no endianness
1255          * coversions for perfromance reasons, all
1256          * pattern conversions are done in rte_flow.
1257          */
1258         if (reg == REG_C_0) {
1259                 struct mlx5_priv *priv = dev->data->dev_private;
1260                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1261                 uint32_t shl_c0;
1262
1263                 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265                 shl_c0 = rte_bsf32(msk_c0);
1266 #else
1267                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1268 #endif
1269                 mask <<= shl_c0;
1270                 data <<= shl_c0;
1271                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272         }
1273         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274         /* The routine expects parameters in memory as big-endian ones. */
1275         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276                                              MLX5_MODIFICATION_TYPE_SET, error);
1277 }
1278
1279 /**
1280  * Convert modify-header set IPv4 DSCP action to DV specification.
1281  *
1282  * @param[in,out] resource
1283  *   Pointer to the modify-header resource.
1284  * @param[in] action
1285  *   Pointer to action specification.
1286  * @param[out] error
1287  *   Pointer to the error structure.
1288  *
1289  * @return
1290  *   0 on success, a negative errno value otherwise and rte_errno is set.
1291  */
1292 static int
1293 flow_dv_convert_action_modify_ipv4_dscp
1294                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295                          const struct rte_flow_action *action,
1296                          struct rte_flow_error *error)
1297 {
1298         const struct rte_flow_action_set_dscp *conf =
1299                 (const struct rte_flow_action_set_dscp *)(action->conf);
1300         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301         struct rte_flow_item_ipv4 ipv4;
1302         struct rte_flow_item_ipv4 ipv4_mask;
1303
1304         memset(&ipv4, 0, sizeof(ipv4));
1305         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306         ipv4.hdr.type_of_service = conf->dscp;
1307         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308         item.spec = &ipv4;
1309         item.mask = &ipv4_mask;
1310         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311                                              MLX5_MODIFICATION_TYPE_SET, error);
1312 }
1313
1314 /**
1315  * Convert modify-header set IPv6 DSCP action to DV specification.
1316  *
1317  * @param[in,out] resource
1318  *   Pointer to the modify-header resource.
1319  * @param[in] action
1320  *   Pointer to action specification.
1321  * @param[out] error
1322  *   Pointer to the error structure.
1323  *
1324  * @return
1325  *   0 on success, a negative errno value otherwise and rte_errno is set.
1326  */
1327 static int
1328 flow_dv_convert_action_modify_ipv6_dscp
1329                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330                          const struct rte_flow_action *action,
1331                          struct rte_flow_error *error)
1332 {
1333         const struct rte_flow_action_set_dscp *conf =
1334                 (const struct rte_flow_action_set_dscp *)(action->conf);
1335         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336         struct rte_flow_item_ipv6 ipv6;
1337         struct rte_flow_item_ipv6 ipv6_mask;
1338
1339         memset(&ipv6, 0, sizeof(ipv6));
1340         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341         /*
1342          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343          * rdma-core only accept the DSCP bits byte aligned start from
1344          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345          * bits in IPv6 case as rdma-core requires byte aligned value.
1346          */
1347         ipv6.hdr.vtc_flow = conf->dscp;
1348         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349         item.spec = &ipv6;
1350         item.mask = &ipv6_mask;
1351         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352                                              MLX5_MODIFICATION_TYPE_SET, error);
1353 }
1354
1355 /**
1356  * Validate MARK item.
1357  *
1358  * @param[in] dev
1359  *   Pointer to the rte_eth_dev structure.
1360  * @param[in] item
1361  *   Item specification.
1362  * @param[in] attr
1363  *   Attributes of flow that includes this item.
1364  * @param[out] error
1365  *   Pointer to error structure.
1366  *
1367  * @return
1368  *   0 on success, a negative errno value otherwise and rte_errno is set.
1369  */
1370 static int
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372                            const struct rte_flow_item *item,
1373                            const struct rte_flow_attr *attr __rte_unused,
1374                            struct rte_flow_error *error)
1375 {
1376         struct mlx5_priv *priv = dev->data->dev_private;
1377         struct mlx5_dev_config *config = &priv->config;
1378         const struct rte_flow_item_mark *spec = item->spec;
1379         const struct rte_flow_item_mark *mask = item->mask;
1380         const struct rte_flow_item_mark nic_mask = {
1381                 .id = priv->sh->dv_mark_mask,
1382         };
1383         int ret;
1384
1385         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386                 return rte_flow_error_set(error, ENOTSUP,
1387                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1388                                           "extended metadata feature"
1389                                           " isn't enabled");
1390         if (!mlx5_flow_ext_mreg_supported(dev))
1391                 return rte_flow_error_set(error, ENOTSUP,
1392                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1393                                           "extended metadata register"
1394                                           " isn't supported");
1395         if (!nic_mask.id)
1396                 return rte_flow_error_set(error, ENOTSUP,
1397                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1398                                           "extended metadata register"
1399                                           " isn't available");
1400         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1401         if (ret < 0)
1402                 return ret;
1403         if (!spec)
1404                 return rte_flow_error_set(error, EINVAL,
1405                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406                                           item->spec,
1407                                           "data cannot be empty");
1408         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409                 return rte_flow_error_set(error, EINVAL,
1410                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411                                           &spec->id,
1412                                           "mark id exceeds the limit");
1413         if (!mask)
1414                 mask = &nic_mask;
1415         if (!mask->id)
1416                 return rte_flow_error_set(error, EINVAL,
1417                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418                                         "mask cannot be zero");
1419
1420         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421                                         (const uint8_t *)&nic_mask,
1422                                         sizeof(struct rte_flow_item_mark),
1423                                         error);
1424         if (ret < 0)
1425                 return ret;
1426         return 0;
1427 }
1428
1429 /**
1430  * Validate META item.
1431  *
1432  * @param[in] dev
1433  *   Pointer to the rte_eth_dev structure.
1434  * @param[in] item
1435  *   Item specification.
1436  * @param[in] attr
1437  *   Attributes of flow that includes this item.
1438  * @param[out] error
1439  *   Pointer to error structure.
1440  *
1441  * @return
1442  *   0 on success, a negative errno value otherwise and rte_errno is set.
1443  */
1444 static int
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446                            const struct rte_flow_item *item,
1447                            const struct rte_flow_attr *attr,
1448                            struct rte_flow_error *error)
1449 {
1450         struct mlx5_priv *priv = dev->data->dev_private;
1451         struct mlx5_dev_config *config = &priv->config;
1452         const struct rte_flow_item_meta *spec = item->spec;
1453         const struct rte_flow_item_meta *mask = item->mask;
1454         struct rte_flow_item_meta nic_mask = {
1455                 .data = UINT32_MAX
1456         };
1457         int reg;
1458         int ret;
1459
1460         if (!spec)
1461                 return rte_flow_error_set(error, EINVAL,
1462                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463                                           item->spec,
1464                                           "data cannot be empty");
1465         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466                 if (!mlx5_flow_ext_mreg_supported(dev))
1467                         return rte_flow_error_set(error, ENOTSUP,
1468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1469                                           "extended metadata register"
1470                                           " isn't supported");
1471                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1472                 if (reg < 0)
1473                         return reg;
1474                 if (reg == REG_B)
1475                         return rte_flow_error_set(error, ENOTSUP,
1476                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1477                                           "match on reg_b "
1478                                           "isn't supported");
1479                 if (reg != REG_A)
1480                         nic_mask.data = priv->sh->dv_meta_mask;
1481         }
1482         if (!mask)
1483                 mask = &rte_flow_item_meta_mask;
1484         if (!mask->data)
1485                 return rte_flow_error_set(error, EINVAL,
1486                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487                                         "mask cannot be zero");
1488
1489         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490                                         (const uint8_t *)&nic_mask,
1491                                         sizeof(struct rte_flow_item_meta),
1492                                         error);
1493         return ret;
1494 }
1495
1496 /**
1497  * Validate TAG item.
1498  *
1499  * @param[in] dev
1500  *   Pointer to the rte_eth_dev structure.
1501  * @param[in] item
1502  *   Item specification.
1503  * @param[in] attr
1504  *   Attributes of flow that includes this item.
1505  * @param[out] error
1506  *   Pointer to error structure.
1507  *
1508  * @return
1509  *   0 on success, a negative errno value otherwise and rte_errno is set.
1510  */
1511 static int
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513                           const struct rte_flow_item *item,
1514                           const struct rte_flow_attr *attr __rte_unused,
1515                           struct rte_flow_error *error)
1516 {
1517         const struct rte_flow_item_tag *spec = item->spec;
1518         const struct rte_flow_item_tag *mask = item->mask;
1519         const struct rte_flow_item_tag nic_mask = {
1520                 .data = RTE_BE32(UINT32_MAX),
1521                 .index = 0xff,
1522         };
1523         int ret;
1524
1525         if (!mlx5_flow_ext_mreg_supported(dev))
1526                 return rte_flow_error_set(error, ENOTSUP,
1527                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1528                                           "extensive metadata register"
1529                                           " isn't supported");
1530         if (!spec)
1531                 return rte_flow_error_set(error, EINVAL,
1532                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1533                                           item->spec,
1534                                           "data cannot be empty");
1535         if (!mask)
1536                 mask = &rte_flow_item_tag_mask;
1537         if (!mask->data)
1538                 return rte_flow_error_set(error, EINVAL,
1539                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540                                         "mask cannot be zero");
1541
1542         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543                                         (const uint8_t *)&nic_mask,
1544                                         sizeof(struct rte_flow_item_tag),
1545                                         error);
1546         if (ret < 0)
1547                 return ret;
1548         if (mask->index != 0xff)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                           "partial mask for tag index"
1552                                           " is not supported");
1553         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1554         if (ret < 0)
1555                 return ret;
1556         MLX5_ASSERT(ret != REG_NONE);
1557         return 0;
1558 }
1559
1560 /**
1561  * Validate vport item.
1562  *
1563  * @param[in] dev
1564  *   Pointer to the rte_eth_dev structure.
1565  * @param[in] item
1566  *   Item specification.
1567  * @param[in] attr
1568  *   Attributes of flow that includes this item.
1569  * @param[in] item_flags
1570  *   Bit-fields that holds the items detected until now.
1571  * @param[out] error
1572  *   Pointer to error structure.
1573  *
1574  * @return
1575  *   0 on success, a negative errno value otherwise and rte_errno is set.
1576  */
1577 static int
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579                               const struct rte_flow_item *item,
1580                               const struct rte_flow_attr *attr,
1581                               uint64_t item_flags,
1582                               struct rte_flow_error *error)
1583 {
1584         const struct rte_flow_item_port_id *spec = item->spec;
1585         const struct rte_flow_item_port_id *mask = item->mask;
1586         const struct rte_flow_item_port_id switch_mask = {
1587                         .id = 0xffffffff,
1588         };
1589         struct mlx5_priv *esw_priv;
1590         struct mlx5_priv *dev_priv;
1591         int ret;
1592
1593         if (!attr->transfer)
1594                 return rte_flow_error_set(error, EINVAL,
1595                                           RTE_FLOW_ERROR_TYPE_ITEM,
1596                                           NULL,
1597                                           "match on port id is valid only"
1598                                           " when transfer flag is enabled");
1599         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600                 return rte_flow_error_set(error, ENOTSUP,
1601                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1602                                           "multiple source ports are not"
1603                                           " supported");
1604         if (!mask)
1605                 mask = &switch_mask;
1606         if (mask->id != 0xffffffff)
1607                 return rte_flow_error_set(error, ENOTSUP,
1608                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1609                                            mask,
1610                                            "no support for partial mask on"
1611                                            " \"id\" field");
1612         ret = mlx5_flow_item_acceptable
1613                                 (item, (const uint8_t *)mask,
1614                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1615                                  sizeof(struct rte_flow_item_port_id),
1616                                  error);
1617         if (ret)
1618                 return ret;
1619         if (!spec)
1620                 return 0;
1621         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1622         if (!esw_priv)
1623                 return rte_flow_error_set(error, rte_errno,
1624                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625                                           "failed to obtain E-Switch info for"
1626                                           " port");
1627         dev_priv = mlx5_dev_to_eswitch_info(dev);
1628         if (!dev_priv)
1629                 return rte_flow_error_set(error, rte_errno,
1630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1631                                           NULL,
1632                                           "failed to obtain E-Switch info");
1633         if (esw_priv->domain_id != dev_priv->domain_id)
1634                 return rte_flow_error_set(error, EINVAL,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "cannot match on a port from a"
1637                                           " different E-Switch");
1638         return 0;
1639 }
1640
1641 /**
1642  * Validate GTP item.
1643  *
1644  * @param[in] dev
1645  *   Pointer to the rte_eth_dev structure.
1646  * @param[in] item
1647  *   Item specification.
1648  * @param[in] item_flags
1649  *   Bit-fields that holds the items detected until now.
1650  * @param[out] error
1651  *   Pointer to error structure.
1652  *
1653  * @return
1654  *   0 on success, a negative errno value otherwise and rte_errno is set.
1655  */
1656 static int
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658                           const struct rte_flow_item *item,
1659                           uint64_t item_flags,
1660                           struct rte_flow_error *error)
1661 {
1662         struct mlx5_priv *priv = dev->data->dev_private;
1663         const struct rte_flow_item_gtp *mask = item->mask;
1664         const struct rte_flow_item_gtp nic_mask = {
1665                 .msg_type = 0xff,
1666                 .teid = RTE_BE32(0xffffffff),
1667         };
1668
1669         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670                 return rte_flow_error_set(error, ENOTSUP,
1671                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1672                                           "GTP support is not enabled");
1673         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674                 return rte_flow_error_set(error, ENOTSUP,
1675                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1676                                           "multiple tunnel layers not"
1677                                           " supported");
1678         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679                 return rte_flow_error_set(error, EINVAL,
1680                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1681                                           "no outer UDP layer found");
1682         if (!mask)
1683                 mask = &rte_flow_item_gtp_mask;
1684         return mlx5_flow_item_acceptable
1685                 (item, (const uint8_t *)mask,
1686                  (const uint8_t *)&nic_mask,
1687                  sizeof(struct rte_flow_item_gtp),
1688                  error);
1689 }
1690
1691 /**
1692  * Validate the pop VLAN action.
1693  *
1694  * @param[in] dev
1695  *   Pointer to the rte_eth_dev structure.
1696  * @param[in] action_flags
1697  *   Holds the actions detected until now.
1698  * @param[in] action
1699  *   Pointer to the pop vlan action.
1700  * @param[in] item_flags
1701  *   The items found in this flow rule.
1702  * @param[in] attr
1703  *   Pointer to flow attributes.
1704  * @param[out] error
1705  *   Pointer to error structure.
1706  *
1707  * @return
1708  *   0 on success, a negative errno value otherwise and rte_errno is set.
1709  */
1710 static int
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712                                  uint64_t action_flags,
1713                                  const struct rte_flow_action *action,
1714                                  uint64_t item_flags,
1715                                  const struct rte_flow_attr *attr,
1716                                  struct rte_flow_error *error)
1717 {
1718         const struct mlx5_priv *priv = dev->data->dev_private;
1719
1720         (void)action;
1721         (void)attr;
1722         if (!priv->sh->pop_vlan_action)
1723                 return rte_flow_error_set(error, ENOTSUP,
1724                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1725                                           NULL,
1726                                           "pop vlan action is not supported");
1727         if (attr->egress)
1728                 return rte_flow_error_set(error, ENOTSUP,
1729                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1730                                           NULL,
1731                                           "pop vlan action not supported for "
1732                                           "egress");
1733         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734                 return rte_flow_error_set(error, ENOTSUP,
1735                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1736                                           "no support for multiple VLAN "
1737                                           "actions");
1738         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739                 return rte_flow_error_set(error, ENOTSUP,
1740                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1741                                           NULL,
1742                                           "cannot pop vlan without a "
1743                                           "match on (outer) vlan in the flow");
1744         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745                 return rte_flow_error_set(error, EINVAL,
1746                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1747                                           "wrong action order, port_id should "
1748                                           "be after pop VLAN action");
1749         if (!attr->transfer && priv->representor)
1750                 return rte_flow_error_set(error, ENOTSUP,
1751                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752                                           "pop vlan action for VF representor "
1753                                           "not supported on NIC table");
1754         return 0;
1755 }
1756
1757 /**
1758  * Get VLAN default info from vlan match info.
1759  *
1760  * @param[in] items
1761  *   the list of item specifications.
1762  * @param[out] vlan
1763  *   pointer VLAN info to fill to.
1764  *
1765  * @return
1766  *   0 on success, a negative errno value otherwise and rte_errno is set.
1767  */
1768 static void
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770                                   struct rte_vlan_hdr *vlan)
1771 {
1772         const struct rte_flow_item_vlan nic_mask = {
1773                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774                                 MLX5DV_FLOW_VLAN_VID_MASK),
1775                 .inner_type = RTE_BE16(0xffff),
1776         };
1777
1778         if (items == NULL)
1779                 return;
1780         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781                 int type = items->type;
1782
1783                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1785                         break;
1786         }
1787         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1790
1791                 if (!vlan_m)
1792                         vlan_m = &nic_mask;
1793                 /* Only full match values are accepted */
1794                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1797                         vlan->vlan_tci |=
1798                                 rte_be_to_cpu_16(vlan_v->tci &
1799                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1800                 }
1801                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1804                         vlan->vlan_tci |=
1805                                 rte_be_to_cpu_16(vlan_v->tci &
1806                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1807                 }
1808                 if (vlan_m->inner_type == nic_mask.inner_type)
1809                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810                                                            vlan_m->inner_type);
1811         }
1812 }
1813
1814 /**
1815  * Validate the push VLAN action.
1816  *
1817  * @param[in] dev
1818  *   Pointer to the rte_eth_dev structure.
1819  * @param[in] action_flags
1820  *   Holds the actions detected until now.
1821  * @param[in] item_flags
1822  *   The items found in this flow rule.
1823  * @param[in] action
1824  *   Pointer to the action structure.
1825  * @param[in] attr
1826  *   Pointer to flow attributes
1827  * @param[out] error
1828  *   Pointer to error structure.
1829  *
1830  * @return
1831  *   0 on success, a negative errno value otherwise and rte_errno is set.
1832  */
1833 static int
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835                                   uint64_t action_flags,
1836                                   const struct rte_flow_item_vlan *vlan_m,
1837                                   const struct rte_flow_action *action,
1838                                   const struct rte_flow_attr *attr,
1839                                   struct rte_flow_error *error)
1840 {
1841         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842         const struct mlx5_priv *priv = dev->data->dev_private;
1843
1844         if (!attr->transfer && attr->ingress)
1845                 return rte_flow_error_set(error, ENOTSUP,
1846                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1847                                           NULL,
1848                                           "push VLAN action not supported for "
1849                                           "ingress");
1850         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1854                                           "invalid vlan ethertype");
1855         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856                 return rte_flow_error_set(error, ENOTSUP,
1857                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1858                                           "no support for multiple VLAN "
1859                                           "actions");
1860         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861                 return rte_flow_error_set(error, EINVAL,
1862                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1863                                           "wrong action order, port_id should "
1864                                           "be after push VLAN");
1865         if (!attr->transfer && priv->representor)
1866                 return rte_flow_error_set(error, ENOTSUP,
1867                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868                                           "push vlan action for VF representor "
1869                                           "not supported on NIC table");
1870         if (vlan_m &&
1871             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875             !(mlx5_flow_find_action
1876                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877                 return rte_flow_error_set(error, EINVAL,
1878                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1879                                           "not full match mask on VLAN PCP and "
1880                                           "there is no of_set_vlan_pcp action, "
1881                                           "push VLAN action cannot figure out "
1882                                           "PCP value");
1883         if (vlan_m &&
1884             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888             !(mlx5_flow_find_action
1889                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890                 return rte_flow_error_set(error, EINVAL,
1891                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1892                                           "not full match mask on VLAN VID and "
1893                                           "there is no of_set_vlan_vid action, "
1894                                           "push VLAN action cannot figure out "
1895                                           "VID value");
1896         (void)attr;
1897         return 0;
1898 }
1899
1900 /**
1901  * Validate the set VLAN PCP.
1902  *
1903  * @param[in] action_flags
1904  *   Holds the actions detected until now.
1905  * @param[in] actions
1906  *   Pointer to the list of actions remaining in the flow rule.
1907  * @param[out] error
1908  *   Pointer to error structure.
1909  *
1910  * @return
1911  *   0 on success, a negative errno value otherwise and rte_errno is set.
1912  */
1913 static int
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915                                      const struct rte_flow_action actions[],
1916                                      struct rte_flow_error *error)
1917 {
1918         const struct rte_flow_action *action = actions;
1919         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1920
1921         if (conf->vlan_pcp > 7)
1922                 return rte_flow_error_set(error, EINVAL,
1923                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1924                                           "VLAN PCP value is too big");
1925         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926                 return rte_flow_error_set(error, ENOTSUP,
1927                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1928                                           "set VLAN PCP action must follow "
1929                                           "the push VLAN action");
1930         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931                 return rte_flow_error_set(error, ENOTSUP,
1932                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1933                                           "Multiple VLAN PCP modification are "
1934                                           "not supported");
1935         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936                 return rte_flow_error_set(error, EINVAL,
1937                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1938                                           "wrong action order, port_id should "
1939                                           "be after set VLAN PCP");
1940         return 0;
1941 }
1942
1943 /**
1944  * Validate the set VLAN VID.
1945  *
1946  * @param[in] item_flags
1947  *   Holds the items detected in this rule.
1948  * @param[in] action_flags
1949  *   Holds the actions detected until now.
1950  * @param[in] actions
1951  *   Pointer to the list of actions remaining in the flow rule.
1952  * @param[out] error
1953  *   Pointer to error structure.
1954  *
1955  * @return
1956  *   0 on success, a negative errno value otherwise and rte_errno is set.
1957  */
1958 static int
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960                                      uint64_t action_flags,
1961                                      const struct rte_flow_action actions[],
1962                                      struct rte_flow_error *error)
1963 {
1964         const struct rte_flow_action *action = actions;
1965         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1966
1967         if (conf->vlan_vid > RTE_BE16(0xFFE))
1968                 return rte_flow_error_set(error, EINVAL,
1969                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1970                                           "VLAN VID value is too big");
1971         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973                 return rte_flow_error_set(error, ENOTSUP,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "set VLAN VID action must follow push"
1976                                           " VLAN action or match on VLAN item");
1977         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978                 return rte_flow_error_set(error, ENOTSUP,
1979                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1980                                           "Multiple VLAN VID modifications are "
1981                                           "not supported");
1982         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1985                                           "wrong action order, port_id should "
1986                                           "be after set VLAN VID");
1987         return 0;
1988 }
1989
1990 /*
1991  * Validate the FLAG action.
1992  *
1993  * @param[in] dev
1994  *   Pointer to the rte_eth_dev structure.
1995  * @param[in] action_flags
1996  *   Holds the actions detected until now.
1997  * @param[in] attr
1998  *   Pointer to flow attributes
1999  * @param[out] error
2000  *   Pointer to error structure.
2001  *
2002  * @return
2003  *   0 on success, a negative errno value otherwise and rte_errno is set.
2004  */
2005 static int
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007                              uint64_t action_flags,
2008                              const struct rte_flow_attr *attr,
2009                              struct rte_flow_error *error)
2010 {
2011         struct mlx5_priv *priv = dev->data->dev_private;
2012         struct mlx5_dev_config *config = &priv->config;
2013         int ret;
2014
2015         /* Fall back if no extended metadata register support. */
2016         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017                 return mlx5_flow_validate_action_flag(action_flags, attr,
2018                                                       error);
2019         /* Extensive metadata mode requires registers. */
2020         if (!mlx5_flow_ext_mreg_supported(dev))
2021                 return rte_flow_error_set(error, ENOTSUP,
2022                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023                                           "no metadata registers "
2024                                           "to support flag action");
2025         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026                 return rte_flow_error_set(error, ENOTSUP,
2027                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028                                           "extended metadata register"
2029                                           " isn't available");
2030         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2031         if (ret < 0)
2032                 return ret;
2033         MLX5_ASSERT(ret > 0);
2034         if (action_flags & MLX5_FLOW_ACTION_MARK)
2035                 return rte_flow_error_set(error, EINVAL,
2036                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037                                           "can't mark and flag in same flow");
2038         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039                 return rte_flow_error_set(error, EINVAL,
2040                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2041                                           "can't have 2 flag"
2042                                           " actions in same flow");
2043         return 0;
2044 }
2045
2046 /**
2047  * Validate MARK action.
2048  *
2049  * @param[in] dev
2050  *   Pointer to the rte_eth_dev structure.
2051  * @param[in] action
2052  *   Pointer to action.
2053  * @param[in] action_flags
2054  *   Holds the actions detected until now.
2055  * @param[in] attr
2056  *   Pointer to flow attributes
2057  * @param[out] error
2058  *   Pointer to error structure.
2059  *
2060  * @return
2061  *   0 on success, a negative errno value otherwise and rte_errno is set.
2062  */
2063 static int
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065                              const struct rte_flow_action *action,
2066                              uint64_t action_flags,
2067                              const struct rte_flow_attr *attr,
2068                              struct rte_flow_error *error)
2069 {
2070         struct mlx5_priv *priv = dev->data->dev_private;
2071         struct mlx5_dev_config *config = &priv->config;
2072         const struct rte_flow_action_mark *mark = action->conf;
2073         int ret;
2074
2075         /* Fall back if no extended metadata register support. */
2076         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077                 return mlx5_flow_validate_action_mark(action, action_flags,
2078                                                       attr, error);
2079         /* Extensive metadata mode requires registers. */
2080         if (!mlx5_flow_ext_mreg_supported(dev))
2081                 return rte_flow_error_set(error, ENOTSUP,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083                                           "no metadata registers "
2084                                           "to support mark action");
2085         if (!priv->sh->dv_mark_mask)
2086                 return rte_flow_error_set(error, ENOTSUP,
2087                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088                                           "extended metadata register"
2089                                           " isn't available");
2090         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2091         if (ret < 0)
2092                 return ret;
2093         MLX5_ASSERT(ret > 0);
2094         if (!mark)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2097                                           "configuration cannot be null");
2098         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099                 return rte_flow_error_set(error, EINVAL,
2100                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2101                                           &mark->id,
2102                                           "mark id exceeds the limit");
2103         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104                 return rte_flow_error_set(error, EINVAL,
2105                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106                                           "can't flag and mark in same flow");
2107         if (action_flags & MLX5_FLOW_ACTION_MARK)
2108                 return rte_flow_error_set(error, EINVAL,
2109                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110                                           "can't have 2 mark actions in same"
2111                                           " flow");
2112         return 0;
2113 }
2114
2115 /**
2116  * Validate SET_META action.
2117  *
2118  * @param[in] dev
2119  *   Pointer to the rte_eth_dev structure.
2120  * @param[in] action
2121  *   Pointer to the action structure.
2122  * @param[in] action_flags
2123  *   Holds the actions detected until now.
2124  * @param[in] attr
2125  *   Pointer to flow attributes
2126  * @param[out] error
2127  *   Pointer to error structure.
2128  *
2129  * @return
2130  *   0 on success, a negative errno value otherwise and rte_errno is set.
2131  */
2132 static int
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134                                  const struct rte_flow_action *action,
2135                                  uint64_t action_flags __rte_unused,
2136                                  const struct rte_flow_attr *attr,
2137                                  struct rte_flow_error *error)
2138 {
2139         const struct rte_flow_action_set_meta *conf;
2140         uint32_t nic_mask = UINT32_MAX;
2141         int reg;
2142
2143         if (!mlx5_flow_ext_mreg_supported(dev))
2144                 return rte_flow_error_set(error, ENOTSUP,
2145                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2146                                           "extended metadata register"
2147                                           " isn't supported");
2148         reg = flow_dv_get_metadata_reg(dev, attr, error);
2149         if (reg < 0)
2150                 return reg;
2151         if (reg != REG_A && reg != REG_B) {
2152                 struct mlx5_priv *priv = dev->data->dev_private;
2153
2154                 nic_mask = priv->sh->dv_meta_mask;
2155         }
2156         if (!(action->conf))
2157                 return rte_flow_error_set(error, EINVAL,
2158                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2159                                           "configuration cannot be null");
2160         conf = (const struct rte_flow_action_set_meta *)action->conf;
2161         if (!conf->mask)
2162                 return rte_flow_error_set(error, EINVAL,
2163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2164                                           "zero mask doesn't have any effect");
2165         if (conf->mask & ~nic_mask)
2166                 return rte_flow_error_set(error, EINVAL,
2167                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2168                                           "meta data must be within reg C0");
2169         return 0;
2170 }
2171
2172 /**
2173  * Validate SET_TAG action.
2174  *
2175  * @param[in] dev
2176  *   Pointer to the rte_eth_dev structure.
2177  * @param[in] action
2178  *   Pointer to the action structure.
2179  * @param[in] action_flags
2180  *   Holds the actions detected until now.
2181  * @param[in] attr
2182  *   Pointer to flow attributes
2183  * @param[out] error
2184  *   Pointer to error structure.
2185  *
2186  * @return
2187  *   0 on success, a negative errno value otherwise and rte_errno is set.
2188  */
2189 static int
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191                                 const struct rte_flow_action *action,
2192                                 uint64_t action_flags,
2193                                 const struct rte_flow_attr *attr,
2194                                 struct rte_flow_error *error)
2195 {
2196         const struct rte_flow_action_set_tag *conf;
2197         const uint64_t terminal_action_flags =
2198                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199                 MLX5_FLOW_ACTION_RSS;
2200         int ret;
2201
2202         if (!mlx5_flow_ext_mreg_supported(dev))
2203                 return rte_flow_error_set(error, ENOTSUP,
2204                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2205                                           "extensive metadata register"
2206                                           " isn't supported");
2207         if (!(action->conf))
2208                 return rte_flow_error_set(error, EINVAL,
2209                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2210                                           "configuration cannot be null");
2211         conf = (const struct rte_flow_action_set_tag *)action->conf;
2212         if (!conf->mask)
2213                 return rte_flow_error_set(error, EINVAL,
2214                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2215                                           "zero mask doesn't have any effect");
2216         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2217         if (ret < 0)
2218                 return ret;
2219         if (!attr->transfer && attr->ingress &&
2220             (action_flags & terminal_action_flags))
2221                 return rte_flow_error_set(error, EINVAL,
2222                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2223                                           "set_tag has no effect"
2224                                           " with terminal actions");
2225         return 0;
2226 }
2227
2228 /**
2229  * Validate count action.
2230  *
2231  * @param[in] dev
2232  *   Pointer to rte_eth_dev structure.
2233  * @param[out] error
2234  *   Pointer to error structure.
2235  *
2236  * @return
2237  *   0 on success, a negative errno value otherwise and rte_errno is set.
2238  */
2239 static int
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241                               struct rte_flow_error *error)
2242 {
2243         struct mlx5_priv *priv = dev->data->dev_private;
2244
2245         if (!priv->config.devx)
2246                 goto notsup_err;
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2248         return 0;
2249 #endif
2250 notsup_err:
2251         return rte_flow_error_set
2252                       (error, ENOTSUP,
2253                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2254                        NULL,
2255                        "count action not supported");
2256 }
2257
2258 /**
2259  * Validate the L2 encap action.
2260  *
2261  * @param[in] dev
2262  *   Pointer to the rte_eth_dev structure.
2263  * @param[in] action_flags
2264  *   Holds the actions detected until now.
2265  * @param[in] action
2266  *   Pointer to the action structure.
2267  * @param[in] attr
2268  *   Pointer to flow attributes.
2269  * @param[out] error
2270  *   Pointer to error structure.
2271  *
2272  * @return
2273  *   0 on success, a negative errno value otherwise and rte_errno is set.
2274  */
2275 static int
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277                                  uint64_t action_flags,
2278                                  const struct rte_flow_action *action,
2279                                  const struct rte_flow_attr *attr,
2280                                  struct rte_flow_error *error)
2281 {
2282         const struct mlx5_priv *priv = dev->data->dev_private;
2283
2284         if (!(action->conf))
2285                 return rte_flow_error_set(error, EINVAL,
2286                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2287                                           "configuration cannot be null");
2288         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289                 return rte_flow_error_set(error, EINVAL,
2290                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291                                           "can only have a single encap action "
2292                                           "in a flow");
2293         if (!attr->transfer && priv->representor)
2294                 return rte_flow_error_set(error, ENOTSUP,
2295                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296                                           "encap action for VF representor "
2297                                           "not supported on NIC table");
2298         return 0;
2299 }
2300
2301 /**
2302  * Validate a decap action.
2303  *
2304  * @param[in] dev
2305  *   Pointer to the rte_eth_dev structure.
2306  * @param[in] action_flags
2307  *   Holds the actions detected until now.
2308  * @param[in] attr
2309  *   Pointer to flow attributes
2310  * @param[out] error
2311  *   Pointer to error structure.
2312  *
2313  * @return
2314  *   0 on success, a negative errno value otherwise and rte_errno is set.
2315  */
2316 static int
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318                               uint64_t action_flags,
2319                               const struct rte_flow_attr *attr,
2320                               struct rte_flow_error *error)
2321 {
2322         const struct mlx5_priv *priv = dev->data->dev_private;
2323
2324         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325                 return rte_flow_error_set(error, ENOTSUP,
2326                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2327                                           action_flags &
2328                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2329                                           "have a single decap action" : "decap "
2330                                           "after encap is not supported");
2331         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332                 return rte_flow_error_set(error, EINVAL,
2333                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334                                           "can't have decap action after"
2335                                           " modify action");
2336         if (attr->egress)
2337                 return rte_flow_error_set(error, ENOTSUP,
2338                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2339                                           NULL,
2340                                           "decap action not supported for "
2341                                           "egress");
2342         if (!attr->transfer && priv->representor)
2343                 return rte_flow_error_set(error, ENOTSUP,
2344                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345                                           "decap action for VF representor "
2346                                           "not supported on NIC table");
2347         return 0;
2348 }
2349
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2351
2352 /**
2353  * Validate the raw encap and decap actions.
2354  *
2355  * @param[in] dev
2356  *   Pointer to the rte_eth_dev structure.
2357  * @param[in] decap
2358  *   Pointer to the decap action.
2359  * @param[in] encap
2360  *   Pointer to the encap action.
2361  * @param[in] attr
2362  *   Pointer to flow attributes
2363  * @param[in/out] action_flags
2364  *   Holds the actions detected until now.
2365  * @param[out] actions_n
2366  *   pointer to the number of actions counter.
2367  * @param[out] error
2368  *   Pointer to error structure.
2369  *
2370  * @return
2371  *   0 on success, a negative errno value otherwise and rte_errno is set.
2372  */
2373 static int
2374 flow_dv_validate_action_raw_encap_decap
2375         (struct rte_eth_dev *dev,
2376          const struct rte_flow_action_raw_decap *decap,
2377          const struct rte_flow_action_raw_encap *encap,
2378          const struct rte_flow_attr *attr, uint64_t *action_flags,
2379          int *actions_n, struct rte_flow_error *error)
2380 {
2381         const struct mlx5_priv *priv = dev->data->dev_private;
2382         int ret;
2383
2384         if (encap && (!encap->size || !encap->data))
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "raw encap data cannot be empty");
2388         if (decap && encap) {
2389                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2391                         /* L3 encap. */
2392                         decap = NULL;
2393                 else if (encap->size <=
2394                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2395                            decap->size >
2396                            MLX5_ENCAPSULATION_DECISION_SIZE)
2397                         /* L3 decap. */
2398                         encap = NULL;
2399                 else if (encap->size >
2400                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2401                            decap->size >
2402                            MLX5_ENCAPSULATION_DECISION_SIZE)
2403                         /* 2 L2 actions: encap and decap. */
2404                         ;
2405                 else
2406                         return rte_flow_error_set(error,
2407                                 ENOTSUP,
2408                                 RTE_FLOW_ERROR_TYPE_ACTION,
2409                                 NULL, "unsupported too small "
2410                                 "raw decap and too small raw "
2411                                 "encap combination");
2412         }
2413         if (decap) {
2414                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2415                                                     error);
2416                 if (ret < 0)
2417                         return ret;
2418                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2419                 ++(*actions_n);
2420         }
2421         if (encap) {
2422                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423                         return rte_flow_error_set(error, ENOTSUP,
2424                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2425                                                   NULL,
2426                                                   "small raw encap size");
2427                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428                         return rte_flow_error_set(error, EINVAL,
2429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2430                                                   NULL,
2431                                                   "more than one encap action");
2432                 if (!attr->transfer && priv->representor)
2433                         return rte_flow_error_set
2434                                         (error, ENOTSUP,
2435                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436                                          "encap action for VF representor "
2437                                          "not supported on NIC table");
2438                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2439                 ++(*actions_n);
2440         }
2441         return 0;
2442 }
2443
2444 /**
2445  * Find existing encap/decap resource or create and register a new one.
2446  *
2447  * @param[in, out] dev
2448  *   Pointer to rte_eth_dev structure.
2449  * @param[in, out] resource
2450  *   Pointer to encap/decap resource.
2451  * @parm[in, out] dev_flow
2452  *   Pointer to the dev_flow.
2453  * @param[out] error
2454  *   pointer to error structure.
2455  *
2456  * @return
2457  *   0 on success otherwise -errno and errno is set.
2458  */
2459 static int
2460 flow_dv_encap_decap_resource_register
2461                         (struct rte_eth_dev *dev,
2462                          struct mlx5_flow_dv_encap_decap_resource *resource,
2463                          struct mlx5_flow *dev_flow,
2464                          struct rte_flow_error *error)
2465 {
2466         struct mlx5_priv *priv = dev->data->dev_private;
2467         struct mlx5_ibv_shared *sh = priv->sh;
2468         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469         struct mlx5dv_dr_domain *domain;
2470         uint32_t idx = 0;
2471
2472         resource->flags = dev_flow->dv.group ? 0 : 1;
2473         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2474                 domain = sh->fdb_domain;
2475         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2476                 domain = sh->rx_domain;
2477         else
2478                 domain = sh->tx_domain;
2479         /* Lookup a matching resource from cache. */
2480         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2481                       cache_resource, next) {
2482                 if (resource->reformat_type == cache_resource->reformat_type &&
2483                     resource->ft_type == cache_resource->ft_type &&
2484                     resource->flags == cache_resource->flags &&
2485                     resource->size == cache_resource->size &&
2486                     !memcmp((const void *)resource->buf,
2487                             (const void *)cache_resource->buf,
2488                             resource->size)) {
2489                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2490                                 (void *)cache_resource,
2491                                 rte_atomic32_read(&cache_resource->refcnt));
2492                         rte_atomic32_inc(&cache_resource->refcnt);
2493                         dev_flow->handle->dvh.rix_encap_decap = idx;
2494                         dev_flow->dv.encap_decap = cache_resource;
2495                         return 0;
2496                 }
2497         }
2498         /* Register new encap/decap resource. */
2499         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2500                                        &dev_flow->handle->dvh.rix_encap_decap);
2501         if (!cache_resource)
2502                 return rte_flow_error_set(error, ENOMEM,
2503                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2504                                           "cannot allocate resource memory");
2505         *cache_resource = *resource;
2506         cache_resource->verbs_action =
2507                 mlx5_glue->dv_create_flow_action_packet_reformat
2508                         (sh->ctx, cache_resource->reformat_type,
2509                          cache_resource->ft_type, domain, cache_resource->flags,
2510                          cache_resource->size,
2511                          (cache_resource->size ? cache_resource->buf : NULL));
2512         if (!cache_resource->verbs_action) {
2513                 rte_free(cache_resource);
2514                 return rte_flow_error_set(error, ENOMEM,
2515                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2516                                           NULL, "cannot create action");
2517         }
2518         rte_atomic32_init(&cache_resource->refcnt);
2519         rte_atomic32_inc(&cache_resource->refcnt);
2520         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2521                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2522                      next);
2523         dev_flow->dv.encap_decap = cache_resource;
2524         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2525                 (void *)cache_resource,
2526                 rte_atomic32_read(&cache_resource->refcnt));
2527         return 0;
2528 }
2529
2530 /**
2531  * Find existing table jump resource or create and register a new one.
2532  *
2533  * @param[in, out] dev
2534  *   Pointer to rte_eth_dev structure.
2535  * @param[in, out] tbl
2536  *   Pointer to flow table resource.
2537  * @parm[in, out] dev_flow
2538  *   Pointer to the dev_flow.
2539  * @param[out] error
2540  *   pointer to error structure.
2541  *
2542  * @return
2543  *   0 on success otherwise -errno and errno is set.
2544  */
2545 static int
2546 flow_dv_jump_tbl_resource_register
2547                         (struct rte_eth_dev *dev __rte_unused,
2548                          struct mlx5_flow_tbl_resource *tbl,
2549                          struct mlx5_flow *dev_flow,
2550                          struct rte_flow_error *error)
2551 {
2552         struct mlx5_flow_tbl_data_entry *tbl_data =
2553                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2554         int cnt;
2555
2556         MLX5_ASSERT(tbl);
2557         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2558         if (!cnt) {
2559                 tbl_data->jump.action =
2560                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2561                         (tbl->obj);
2562                 if (!tbl_data->jump.action)
2563                         return rte_flow_error_set(error, ENOMEM,
2564                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2565                                         NULL, "cannot create jump action");
2566                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2567                         (void *)&tbl_data->jump, cnt);
2568         } else {
2569                 /* old jump should not make the table ref++. */
2570                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2571                 MLX5_ASSERT(tbl_data->jump.action);
2572                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2573                         (void *)&tbl_data->jump, cnt);
2574         }
2575         rte_atomic32_inc(&tbl_data->jump.refcnt);
2576         dev_flow->handle->rix_jump = tbl_data->idx;
2577         dev_flow->dv.jump = &tbl_data->jump;
2578         return 0;
2579 }
2580
2581 /**
2582  * Find existing table port ID resource or create and register a new one.
2583  *
2584  * @param[in, out] dev
2585  *   Pointer to rte_eth_dev structure.
2586  * @param[in, out] resource
2587  *   Pointer to port ID action resource.
2588  * @parm[in, out] dev_flow
2589  *   Pointer to the dev_flow.
2590  * @param[out] error
2591  *   pointer to error structure.
2592  *
2593  * @return
2594  *   0 on success otherwise -errno and errno is set.
2595  */
2596 static int
2597 flow_dv_port_id_action_resource_register
2598                         (struct rte_eth_dev *dev,
2599                          struct mlx5_flow_dv_port_id_action_resource *resource,
2600                          struct mlx5_flow *dev_flow,
2601                          struct rte_flow_error *error)
2602 {
2603         struct mlx5_priv *priv = dev->data->dev_private;
2604         struct mlx5_ibv_shared *sh = priv->sh;
2605         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2606         uint32_t idx = 0;
2607
2608         /* Lookup a matching resource from cache. */
2609         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2610                       idx, cache_resource, next) {
2611                 if (resource->port_id == cache_resource->port_id) {
2612                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2613                                 "refcnt %d++",
2614                                 (void *)cache_resource,
2615                                 rte_atomic32_read(&cache_resource->refcnt));
2616                         rte_atomic32_inc(&cache_resource->refcnt);
2617                         dev_flow->handle->rix_port_id_action = idx;
2618                         dev_flow->dv.port_id_action = cache_resource;
2619                         return 0;
2620                 }
2621         }
2622         /* Register new port id action resource. */
2623         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2624                                        &dev_flow->handle->rix_port_id_action);
2625         if (!cache_resource)
2626                 return rte_flow_error_set(error, ENOMEM,
2627                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2628                                           "cannot allocate resource memory");
2629         *cache_resource = *resource;
2630         /*
2631          * Depending on rdma_core version the glue routine calls
2632          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2633          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2634          */
2635         cache_resource->action =
2636                 mlx5_glue->dr_create_flow_action_dest_port
2637                         (priv->sh->fdb_domain, resource->port_id);
2638         if (!cache_resource->action) {
2639                 rte_free(cache_resource);
2640                 return rte_flow_error_set(error, ENOMEM,
2641                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2642                                           NULL, "cannot create action");
2643         }
2644         rte_atomic32_init(&cache_resource->refcnt);
2645         rte_atomic32_inc(&cache_resource->refcnt);
2646         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2647                      dev_flow->handle->rix_port_id_action, cache_resource,
2648                      next);
2649         dev_flow->dv.port_id_action = cache_resource;
2650         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2651                 (void *)cache_resource,
2652                 rte_atomic32_read(&cache_resource->refcnt));
2653         return 0;
2654 }
2655
2656 /**
2657  * Find existing push vlan resource or create and register a new one.
2658  *
2659  * @param [in, out] dev
2660  *   Pointer to rte_eth_dev structure.
2661  * @param[in, out] resource
2662  *   Pointer to port ID action resource.
2663  * @parm[in, out] dev_flow
2664  *   Pointer to the dev_flow.
2665  * @param[out] error
2666  *   pointer to error structure.
2667  *
2668  * @return
2669  *   0 on success otherwise -errno and errno is set.
2670  */
2671 static int
2672 flow_dv_push_vlan_action_resource_register
2673                        (struct rte_eth_dev *dev,
2674                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2675                         struct mlx5_flow *dev_flow,
2676                         struct rte_flow_error *error)
2677 {
2678         struct mlx5_priv *priv = dev->data->dev_private;
2679         struct mlx5_ibv_shared *sh = priv->sh;
2680         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2681         struct mlx5dv_dr_domain *domain;
2682         uint32_t idx = 0;
2683
2684         /* Lookup a matching resource from cache. */
2685         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2686                       sh->push_vlan_action_list, idx, cache_resource, next) {
2687                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2688                     resource->ft_type == cache_resource->ft_type) {
2689                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2690                                 "refcnt %d++",
2691                                 (void *)cache_resource,
2692                                 rte_atomic32_read(&cache_resource->refcnt));
2693                         rte_atomic32_inc(&cache_resource->refcnt);
2694                         dev_flow->handle->dvh.rix_push_vlan = idx;
2695                         dev_flow->dv.push_vlan_res = cache_resource;
2696                         return 0;
2697                 }
2698         }
2699         /* Register new push_vlan action resource. */
2700         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2701                                        &dev_flow->handle->dvh.rix_push_vlan);
2702         if (!cache_resource)
2703                 return rte_flow_error_set(error, ENOMEM,
2704                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2705                                           "cannot allocate resource memory");
2706         *cache_resource = *resource;
2707         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2708                 domain = sh->fdb_domain;
2709         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2710                 domain = sh->rx_domain;
2711         else
2712                 domain = sh->tx_domain;
2713         cache_resource->action =
2714                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2715                                                            resource->vlan_tag);
2716         if (!cache_resource->action) {
2717                 rte_free(cache_resource);
2718                 return rte_flow_error_set(error, ENOMEM,
2719                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2720                                           NULL, "cannot create action");
2721         }
2722         rte_atomic32_init(&cache_resource->refcnt);
2723         rte_atomic32_inc(&cache_resource->refcnt);
2724         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2725                      &sh->push_vlan_action_list,
2726                      dev_flow->handle->dvh.rix_push_vlan,
2727                      cache_resource, next);
2728         dev_flow->dv.push_vlan_res = cache_resource;
2729         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2730                 (void *)cache_resource,
2731                 rte_atomic32_read(&cache_resource->refcnt));
2732         return 0;
2733 }
2734 /**
2735  * Get the size of specific rte_flow_item_type
2736  *
2737  * @param[in] item_type
2738  *   Tested rte_flow_item_type.
2739  *
2740  * @return
2741  *   sizeof struct item_type, 0 if void or irrelevant.
2742  */
2743 static size_t
2744 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2745 {
2746         size_t retval;
2747
2748         switch (item_type) {
2749         case RTE_FLOW_ITEM_TYPE_ETH:
2750                 retval = sizeof(struct rte_flow_item_eth);
2751                 break;
2752         case RTE_FLOW_ITEM_TYPE_VLAN:
2753                 retval = sizeof(struct rte_flow_item_vlan);
2754                 break;
2755         case RTE_FLOW_ITEM_TYPE_IPV4:
2756                 retval = sizeof(struct rte_flow_item_ipv4);
2757                 break;
2758         case RTE_FLOW_ITEM_TYPE_IPV6:
2759                 retval = sizeof(struct rte_flow_item_ipv6);
2760                 break;
2761         case RTE_FLOW_ITEM_TYPE_UDP:
2762                 retval = sizeof(struct rte_flow_item_udp);
2763                 break;
2764         case RTE_FLOW_ITEM_TYPE_TCP:
2765                 retval = sizeof(struct rte_flow_item_tcp);
2766                 break;
2767         case RTE_FLOW_ITEM_TYPE_VXLAN:
2768                 retval = sizeof(struct rte_flow_item_vxlan);
2769                 break;
2770         case RTE_FLOW_ITEM_TYPE_GRE:
2771                 retval = sizeof(struct rte_flow_item_gre);
2772                 break;
2773         case RTE_FLOW_ITEM_TYPE_NVGRE:
2774                 retval = sizeof(struct rte_flow_item_nvgre);
2775                 break;
2776         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2777                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2778                 break;
2779         case RTE_FLOW_ITEM_TYPE_MPLS:
2780                 retval = sizeof(struct rte_flow_item_mpls);
2781                 break;
2782         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2783         default:
2784                 retval = 0;
2785                 break;
2786         }
2787         return retval;
2788 }
2789
2790 #define MLX5_ENCAP_IPV4_VERSION         0x40
2791 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2792 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2793 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2794 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2795 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2796 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2797
2798 /**
2799  * Convert the encap action data from list of rte_flow_item to raw buffer
2800  *
2801  * @param[in] items
2802  *   Pointer to rte_flow_item objects list.
2803  * @param[out] buf
2804  *   Pointer to the output buffer.
2805  * @param[out] size
2806  *   Pointer to the output buffer size.
2807  * @param[out] error
2808  *   Pointer to the error structure.
2809  *
2810  * @return
2811  *   0 on success, a negative errno value otherwise and rte_errno is set.
2812  */
2813 static int
2814 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2815                            size_t *size, struct rte_flow_error *error)
2816 {
2817         struct rte_ether_hdr *eth = NULL;
2818         struct rte_vlan_hdr *vlan = NULL;
2819         struct rte_ipv4_hdr *ipv4 = NULL;
2820         struct rte_ipv6_hdr *ipv6 = NULL;
2821         struct rte_udp_hdr *udp = NULL;
2822         struct rte_vxlan_hdr *vxlan = NULL;
2823         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2824         struct rte_gre_hdr *gre = NULL;
2825         size_t len;
2826         size_t temp_size = 0;
2827
2828         if (!items)
2829                 return rte_flow_error_set(error, EINVAL,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION,
2831                                           NULL, "invalid empty data");
2832         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2833                 len = flow_dv_get_item_len(items->type);
2834                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2835                         return rte_flow_error_set(error, EINVAL,
2836                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2837                                                   (void *)items->type,
2838                                                   "items total size is too big"
2839                                                   " for encap action");
2840                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2841                 switch (items->type) {
2842                 case RTE_FLOW_ITEM_TYPE_ETH:
2843                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2844                         break;
2845                 case RTE_FLOW_ITEM_TYPE_VLAN:
2846                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2847                         if (!eth)
2848                                 return rte_flow_error_set(error, EINVAL,
2849                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2850                                                 (void *)items->type,
2851                                                 "eth header not found");
2852                         if (!eth->ether_type)
2853                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2854                         break;
2855                 case RTE_FLOW_ITEM_TYPE_IPV4:
2856                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2857                         if (!vlan && !eth)
2858                                 return rte_flow_error_set(error, EINVAL,
2859                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2860                                                 (void *)items->type,
2861                                                 "neither eth nor vlan"
2862                                                 " header found");
2863                         if (vlan && !vlan->eth_proto)
2864                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2865                         else if (eth && !eth->ether_type)
2866                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2867                         if (!ipv4->version_ihl)
2868                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2869                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2870                         if (!ipv4->time_to_live)
2871                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2872                         break;
2873                 case RTE_FLOW_ITEM_TYPE_IPV6:
2874                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2875                         if (!vlan && !eth)
2876                                 return rte_flow_error_set(error, EINVAL,
2877                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2878                                                 (void *)items->type,
2879                                                 "neither eth nor vlan"
2880                                                 " header found");
2881                         if (vlan && !vlan->eth_proto)
2882                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2883                         else if (eth && !eth->ether_type)
2884                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2885                         if (!ipv6->vtc_flow)
2886                                 ipv6->vtc_flow =
2887                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2888                         if (!ipv6->hop_limits)
2889                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2890                         break;
2891                 case RTE_FLOW_ITEM_TYPE_UDP:
2892                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2893                         if (!ipv4 && !ipv6)
2894                                 return rte_flow_error_set(error, EINVAL,
2895                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2896                                                 (void *)items->type,
2897                                                 "ip header not found");
2898                         if (ipv4 && !ipv4->next_proto_id)
2899                                 ipv4->next_proto_id = IPPROTO_UDP;
2900                         else if (ipv6 && !ipv6->proto)
2901                                 ipv6->proto = IPPROTO_UDP;
2902                         break;
2903                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2904                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2905                         if (!udp)
2906                                 return rte_flow_error_set(error, EINVAL,
2907                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2908                                                 (void *)items->type,
2909                                                 "udp header not found");
2910                         if (!udp->dst_port)
2911                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2912                         if (!vxlan->vx_flags)
2913                                 vxlan->vx_flags =
2914                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2915                         break;
2916                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2917                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2918                         if (!udp)
2919                                 return rte_flow_error_set(error, EINVAL,
2920                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2921                                                 (void *)items->type,
2922                                                 "udp header not found");
2923                         if (!vxlan_gpe->proto)
2924                                 return rte_flow_error_set(error, EINVAL,
2925                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2926                                                 (void *)items->type,
2927                                                 "next protocol not found");
2928                         if (!udp->dst_port)
2929                                 udp->dst_port =
2930                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2931                         if (!vxlan_gpe->vx_flags)
2932                                 vxlan_gpe->vx_flags =
2933                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2934                         break;
2935                 case RTE_FLOW_ITEM_TYPE_GRE:
2936                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2937                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2938                         if (!gre->proto)
2939                                 return rte_flow_error_set(error, EINVAL,
2940                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2941                                                 (void *)items->type,
2942                                                 "next protocol not found");
2943                         if (!ipv4 && !ipv6)
2944                                 return rte_flow_error_set(error, EINVAL,
2945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2946                                                 (void *)items->type,
2947                                                 "ip header not found");
2948                         if (ipv4 && !ipv4->next_proto_id)
2949                                 ipv4->next_proto_id = IPPROTO_GRE;
2950                         else if (ipv6 && !ipv6->proto)
2951                                 ipv6->proto = IPPROTO_GRE;
2952                         break;
2953                 case RTE_FLOW_ITEM_TYPE_VOID:
2954                         break;
2955                 default:
2956                         return rte_flow_error_set(error, EINVAL,
2957                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2958                                                   (void *)items->type,
2959                                                   "unsupported item type");
2960                         break;
2961                 }
2962                 temp_size += len;
2963         }
2964         *size = temp_size;
2965         return 0;
2966 }
2967
2968 static int
2969 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2970 {
2971         struct rte_ether_hdr *eth = NULL;
2972         struct rte_vlan_hdr *vlan = NULL;
2973         struct rte_ipv6_hdr *ipv6 = NULL;
2974         struct rte_udp_hdr *udp = NULL;
2975         char *next_hdr;
2976         uint16_t proto;
2977
2978         eth = (struct rte_ether_hdr *)data;
2979         next_hdr = (char *)(eth + 1);
2980         proto = RTE_BE16(eth->ether_type);
2981
2982         /* VLAN skipping */
2983         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2984                 vlan = (struct rte_vlan_hdr *)next_hdr;
2985                 proto = RTE_BE16(vlan->eth_proto);
2986                 next_hdr += sizeof(struct rte_vlan_hdr);
2987         }
2988
2989         /* HW calculates IPv4 csum. no need to proceed */
2990         if (proto == RTE_ETHER_TYPE_IPV4)
2991                 return 0;
2992
2993         /* non IPv4/IPv6 header. not supported */
2994         if (proto != RTE_ETHER_TYPE_IPV6) {
2995                 return rte_flow_error_set(error, ENOTSUP,
2996                                           RTE_FLOW_ERROR_TYPE_ACTION,
2997                                           NULL, "Cannot offload non IPv4/IPv6");
2998         }
2999
3000         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3001
3002         /* ignore non UDP */
3003         if (ipv6->proto != IPPROTO_UDP)
3004                 return 0;
3005
3006         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3007         udp->dgram_cksum = 0;
3008
3009         return 0;
3010 }
3011
3012 /**
3013  * Convert L2 encap action to DV specification.
3014  *
3015  * @param[in] dev
3016  *   Pointer to rte_eth_dev structure.
3017  * @param[in] action
3018  *   Pointer to action structure.
3019  * @param[in, out] dev_flow
3020  *   Pointer to the mlx5_flow.
3021  * @param[in] transfer
3022  *   Mark if the flow is E-Switch flow.
3023  * @param[out] error
3024  *   Pointer to the error structure.
3025  *
3026  * @return
3027  *   0 on success, a negative errno value otherwise and rte_errno is set.
3028  */
3029 static int
3030 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3031                                const struct rte_flow_action *action,
3032                                struct mlx5_flow *dev_flow,
3033                                uint8_t transfer,
3034                                struct rte_flow_error *error)
3035 {
3036         const struct rte_flow_item *encap_data;
3037         const struct rte_flow_action_raw_encap *raw_encap_data;
3038         struct mlx5_flow_dv_encap_decap_resource res = {
3039                 .reformat_type =
3040                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3041                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3042                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3043         };
3044
3045         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3046                 raw_encap_data =
3047                         (const struct rte_flow_action_raw_encap *)action->conf;
3048                 res.size = raw_encap_data->size;
3049                 memcpy(res.buf, raw_encap_data->data, res.size);
3050         } else {
3051                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3052                         encap_data =
3053                                 ((const struct rte_flow_action_vxlan_encap *)
3054                                                 action->conf)->definition;
3055                 else
3056                         encap_data =
3057                                 ((const struct rte_flow_action_nvgre_encap *)
3058                                                 action->conf)->definition;
3059                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3060                                                &res.size, error))
3061                         return -rte_errno;
3062         }
3063         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3064                 return -rte_errno;
3065         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3066                 return rte_flow_error_set(error, EINVAL,
3067                                           RTE_FLOW_ERROR_TYPE_ACTION,
3068                                           NULL, "can't create L2 encap action");
3069         return 0;
3070 }
3071
3072 /**
3073  * Convert L2 decap action to DV specification.
3074  *
3075  * @param[in] dev
3076  *   Pointer to rte_eth_dev structure.
3077  * @param[in, out] dev_flow
3078  *   Pointer to the mlx5_flow.
3079  * @param[in] transfer
3080  *   Mark if the flow is E-Switch flow.
3081  * @param[out] error
3082  *   Pointer to the error structure.
3083  *
3084  * @return
3085  *   0 on success, a negative errno value otherwise and rte_errno is set.
3086  */
3087 static int
3088 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3089                                struct mlx5_flow *dev_flow,
3090                                uint8_t transfer,
3091                                struct rte_flow_error *error)
3092 {
3093         struct mlx5_flow_dv_encap_decap_resource res = {
3094                 .size = 0,
3095                 .reformat_type =
3096                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3097                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3098                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3099         };
3100
3101         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3102                 return rte_flow_error_set(error, EINVAL,
3103                                           RTE_FLOW_ERROR_TYPE_ACTION,
3104                                           NULL, "can't create L2 decap action");
3105         return 0;
3106 }
3107
3108 /**
3109  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] action
3114  *   Pointer to action structure.
3115  * @param[in, out] dev_flow
3116  *   Pointer to the mlx5_flow.
3117  * @param[in] attr
3118  *   Pointer to the flow attributes.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3127                                 const struct rte_flow_action *action,
3128                                 struct mlx5_flow *dev_flow,
3129                                 const struct rte_flow_attr *attr,
3130                                 struct rte_flow_error *error)
3131 {
3132         const struct rte_flow_action_raw_encap *encap_data;
3133         struct mlx5_flow_dv_encap_decap_resource res;
3134
3135         memset(&res, 0, sizeof(res));
3136         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3137         res.size = encap_data->size;
3138         memcpy(res.buf, encap_data->data, res.size);
3139         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3140                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3141                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3142         if (attr->transfer)
3143                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3144         else
3145                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3146                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3147         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3148                 return rte_flow_error_set(error, EINVAL,
3149                                           RTE_FLOW_ERROR_TYPE_ACTION,
3150                                           NULL, "can't create encap action");
3151         return 0;
3152 }
3153
3154 /**
3155  * Create action push VLAN.
3156  *
3157  * @param[in] dev
3158  *   Pointer to rte_eth_dev structure.
3159  * @param[in] attr
3160  *   Pointer to the flow attributes.
3161  * @param[in] vlan
3162  *   Pointer to the vlan to push to the Ethernet header.
3163  * @param[in, out] dev_flow
3164  *   Pointer to the mlx5_flow.
3165  * @param[out] error
3166  *   Pointer to the error structure.
3167  *
3168  * @return
3169  *   0 on success, a negative errno value otherwise and rte_errno is set.
3170  */
3171 static int
3172 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3173                                 const struct rte_flow_attr *attr,
3174                                 const struct rte_vlan_hdr *vlan,
3175                                 struct mlx5_flow *dev_flow,
3176                                 struct rte_flow_error *error)
3177 {
3178         struct mlx5_flow_dv_push_vlan_action_resource res;
3179
3180         memset(&res, 0, sizeof(res));
3181         res.vlan_tag =
3182                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3183                                  vlan->vlan_tci);
3184         if (attr->transfer)
3185                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3186         else
3187                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3188                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3189         return flow_dv_push_vlan_action_resource_register
3190                                             (dev, &res, dev_flow, error);
3191 }
3192
3193 /**
3194  * Validate the modify-header actions.
3195  *
3196  * @param[in] action_flags
3197  *   Holds the actions detected until now.
3198  * @param[in] action
3199  *   Pointer to the modify action.
3200  * @param[out] error
3201  *   Pointer to error structure.
3202  *
3203  * @return
3204  *   0 on success, a negative errno value otherwise and rte_errno is set.
3205  */
3206 static int
3207 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3208                                    const struct rte_flow_action *action,
3209                                    struct rte_flow_error *error)
3210 {
3211         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3212                 return rte_flow_error_set(error, EINVAL,
3213                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3214                                           NULL, "action configuration not set");
3215         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3216                 return rte_flow_error_set(error, EINVAL,
3217                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3218                                           "can't have encap action before"
3219                                           " modify action");
3220         return 0;
3221 }
3222
3223 /**
3224  * Validate the modify-header MAC address actions.
3225  *
3226  * @param[in] action_flags
3227  *   Holds the actions detected until now.
3228  * @param[in] action
3229  *   Pointer to the modify action.
3230  * @param[in] item_flags
3231  *   Holds the items detected.
3232  * @param[out] error
3233  *   Pointer to error structure.
3234  *
3235  * @return
3236  *   0 on success, a negative errno value otherwise and rte_errno is set.
3237  */
3238 static int
3239 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3240                                    const struct rte_flow_action *action,
3241                                    const uint64_t item_flags,
3242                                    struct rte_flow_error *error)
3243 {
3244         int ret = 0;
3245
3246         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3247         if (!ret) {
3248                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3249                         return rte_flow_error_set(error, EINVAL,
3250                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3251                                                   NULL,
3252                                                   "no L2 item in pattern");
3253         }
3254         return ret;
3255 }
3256
3257 /**
3258  * Validate the modify-header IPv4 address actions.
3259  *
3260  * @param[in] action_flags
3261  *   Holds the actions detected until now.
3262  * @param[in] action
3263  *   Pointer to the modify action.
3264  * @param[in] item_flags
3265  *   Holds the items detected.
3266  * @param[out] error
3267  *   Pointer to error structure.
3268  *
3269  * @return
3270  *   0 on success, a negative errno value otherwise and rte_errno is set.
3271  */
3272 static int
3273 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3274                                     const struct rte_flow_action *action,
3275                                     const uint64_t item_flags,
3276                                     struct rte_flow_error *error)
3277 {
3278         int ret = 0;
3279         uint64_t layer;
3280
3281         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3282         if (!ret) {
3283                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3284                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3285                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3286                 if (!(item_flags & layer))
3287                         return rte_flow_error_set(error, EINVAL,
3288                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3289                                                   NULL,
3290                                                   "no ipv4 item in pattern");
3291         }
3292         return ret;
3293 }
3294
3295 /**
3296  * Validate the modify-header IPv6 address actions.
3297  *
3298  * @param[in] action_flags
3299  *   Holds the actions detected until now.
3300  * @param[in] action
3301  *   Pointer to the modify action.
3302  * @param[in] item_flags
3303  *   Holds the items detected.
3304  * @param[out] error
3305  *   Pointer to error structure.
3306  *
3307  * @return
3308  *   0 on success, a negative errno value otherwise and rte_errno is set.
3309  */
3310 static int
3311 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3312                                     const struct rte_flow_action *action,
3313                                     const uint64_t item_flags,
3314                                     struct rte_flow_error *error)
3315 {
3316         int ret = 0;
3317         uint64_t layer;
3318
3319         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3320         if (!ret) {
3321                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3322                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3323                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3324                 if (!(item_flags & layer))
3325                         return rte_flow_error_set(error, EINVAL,
3326                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3327                                                   NULL,
3328                                                   "no ipv6 item in pattern");
3329         }
3330         return ret;
3331 }
3332
3333 /**
3334  * Validate the modify-header TP actions.
3335  *
3336  * @param[in] action_flags
3337  *   Holds the actions detected until now.
3338  * @param[in] action
3339  *   Pointer to the modify action.
3340  * @param[in] item_flags
3341  *   Holds the items detected.
3342  * @param[out] error
3343  *   Pointer to error structure.
3344  *
3345  * @return
3346  *   0 on success, a negative errno value otherwise and rte_errno is set.
3347  */
3348 static int
3349 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3350                                   const struct rte_flow_action *action,
3351                                   const uint64_t item_flags,
3352                                   struct rte_flow_error *error)
3353 {
3354         int ret = 0;
3355         uint64_t layer;
3356
3357         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3358         if (!ret) {
3359                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3360                                  MLX5_FLOW_LAYER_INNER_L4 :
3361                                  MLX5_FLOW_LAYER_OUTER_L4;
3362                 if (!(item_flags & layer))
3363                         return rte_flow_error_set(error, EINVAL,
3364                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3365                                                   NULL, "no transport layer "
3366                                                   "in pattern");
3367         }
3368         return ret;
3369 }
3370
3371 /**
3372  * Validate the modify-header actions of increment/decrement
3373  * TCP Sequence-number.
3374  *
3375  * @param[in] action_flags
3376  *   Holds the actions detected until now.
3377  * @param[in] action
3378  *   Pointer to the modify action.
3379  * @param[in] item_flags
3380  *   Holds the items detected.
3381  * @param[out] error
3382  *   Pointer to error structure.
3383  *
3384  * @return
3385  *   0 on success, a negative errno value otherwise and rte_errno is set.
3386  */
3387 static int
3388 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3389                                        const struct rte_flow_action *action,
3390                                        const uint64_t item_flags,
3391                                        struct rte_flow_error *error)
3392 {
3393         int ret = 0;
3394         uint64_t layer;
3395
3396         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3397         if (!ret) {
3398                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3399                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3400                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3401                 if (!(item_flags & layer))
3402                         return rte_flow_error_set(error, EINVAL,
3403                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3404                                                   NULL, "no TCP item in"
3405                                                   " pattern");
3406                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3407                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3408                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3409                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3410                         return rte_flow_error_set(error, EINVAL,
3411                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3412                                                   NULL,
3413                                                   "cannot decrease and increase"
3414                                                   " TCP sequence number"
3415                                                   " at the same time");
3416         }
3417         return ret;
3418 }
3419
3420 /**
3421  * Validate the modify-header actions of increment/decrement
3422  * TCP Acknowledgment number.
3423  *
3424  * @param[in] action_flags
3425  *   Holds the actions detected until now.
3426  * @param[in] action
3427  *   Pointer to the modify action.
3428  * @param[in] item_flags
3429  *   Holds the items detected.
3430  * @param[out] error
3431  *   Pointer to error structure.
3432  *
3433  * @return
3434  *   0 on success, a negative errno value otherwise and rte_errno is set.
3435  */
3436 static int
3437 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3438                                        const struct rte_flow_action *action,
3439                                        const uint64_t item_flags,
3440                                        struct rte_flow_error *error)
3441 {
3442         int ret = 0;
3443         uint64_t layer;
3444
3445         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3446         if (!ret) {
3447                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3448                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3449                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3450                 if (!(item_flags & layer))
3451                         return rte_flow_error_set(error, EINVAL,
3452                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3453                                                   NULL, "no TCP item in"
3454                                                   " pattern");
3455                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3456                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3457                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3458                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3459                         return rte_flow_error_set(error, EINVAL,
3460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3461                                                   NULL,
3462                                                   "cannot decrease and increase"
3463                                                   " TCP acknowledgment number"
3464                                                   " at the same time");
3465         }
3466         return ret;
3467 }
3468
3469 /**
3470  * Validate the modify-header TTL actions.
3471  *
3472  * @param[in] action_flags
3473  *   Holds the actions detected until now.
3474  * @param[in] action
3475  *   Pointer to the modify action.
3476  * @param[in] item_flags
3477  *   Holds the items detected.
3478  * @param[out] error
3479  *   Pointer to error structure.
3480  *
3481  * @return
3482  *   0 on success, a negative errno value otherwise and rte_errno is set.
3483  */
3484 static int
3485 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3486                                    const struct rte_flow_action *action,
3487                                    const uint64_t item_flags,
3488                                    struct rte_flow_error *error)
3489 {
3490         int ret = 0;
3491         uint64_t layer;
3492
3493         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3494         if (!ret) {
3495                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3496                                  MLX5_FLOW_LAYER_INNER_L3 :
3497                                  MLX5_FLOW_LAYER_OUTER_L3;
3498                 if (!(item_flags & layer))
3499                         return rte_flow_error_set(error, EINVAL,
3500                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3501                                                   NULL,
3502                                                   "no IP protocol in pattern");
3503         }
3504         return ret;
3505 }
3506
3507 /**
3508  * Validate jump action.
3509  *
3510  * @param[in] action
3511  *   Pointer to the jump action.
3512  * @param[in] action_flags
3513  *   Holds the actions detected until now.
3514  * @param[in] attributes
3515  *   Pointer to flow attributes
3516  * @param[in] external
3517  *   Action belongs to flow rule created by request external to PMD.
3518  * @param[out] error
3519  *   Pointer to error structure.
3520  *
3521  * @return
3522  *   0 on success, a negative errno value otherwise and rte_errno is set.
3523  */
3524 static int
3525 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3526                              uint64_t action_flags,
3527                              const struct rte_flow_attr *attributes,
3528                              bool external, struct rte_flow_error *error)
3529 {
3530         uint32_t target_group, table;
3531         int ret = 0;
3532
3533         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3534                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3535                 return rte_flow_error_set(error, EINVAL,
3536                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3537                                           "can't have 2 fate actions in"
3538                                           " same flow");
3539         if (action_flags & MLX5_FLOW_ACTION_METER)
3540                 return rte_flow_error_set(error, ENOTSUP,
3541                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3542                                           "jump with meter not support");
3543         if (!action->conf)
3544                 return rte_flow_error_set(error, EINVAL,
3545                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3546                                           NULL, "action configuration not set");
3547         target_group =
3548                 ((const struct rte_flow_action_jump *)action->conf)->group;
3549         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3550                                        true, &table, error);
3551         if (ret)
3552                 return ret;
3553         if (attributes->group == target_group)
3554                 return rte_flow_error_set(error, EINVAL,
3555                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3556                                           "target group must be other than"
3557                                           " the current flow group");
3558         return 0;
3559 }
3560
3561 /*
3562  * Validate the port_id action.
3563  *
3564  * @param[in] dev
3565  *   Pointer to rte_eth_dev structure.
3566  * @param[in] action_flags
3567  *   Bit-fields that holds the actions detected until now.
3568  * @param[in] action
3569  *   Port_id RTE action structure.
3570  * @param[in] attr
3571  *   Attributes of flow that includes this action.
3572  * @param[out] error
3573  *   Pointer to error structure.
3574  *
3575  * @return
3576  *   0 on success, a negative errno value otherwise and rte_errno is set.
3577  */
3578 static int
3579 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3580                                 uint64_t action_flags,
3581                                 const struct rte_flow_action *action,
3582                                 const struct rte_flow_attr *attr,
3583                                 struct rte_flow_error *error)
3584 {
3585         const struct rte_flow_action_port_id *port_id;
3586         struct mlx5_priv *act_priv;
3587         struct mlx5_priv *dev_priv;
3588         uint16_t port;
3589
3590         if (!attr->transfer)
3591                 return rte_flow_error_set(error, ENOTSUP,
3592                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3593                                           NULL,
3594                                           "port id action is valid in transfer"
3595                                           " mode only");
3596         if (!action || !action->conf)
3597                 return rte_flow_error_set(error, ENOTSUP,
3598                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3599                                           NULL,
3600                                           "port id action parameters must be"
3601                                           " specified");
3602         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3603                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3604                 return rte_flow_error_set(error, EINVAL,
3605                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3606                                           "can have only one fate actions in"
3607                                           " a flow");
3608         dev_priv = mlx5_dev_to_eswitch_info(dev);
3609         if (!dev_priv)
3610                 return rte_flow_error_set(error, rte_errno,
3611                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3612                                           NULL,
3613                                           "failed to obtain E-Switch info");
3614         port_id = action->conf;
3615         port = port_id->original ? dev->data->port_id : port_id->id;
3616         act_priv = mlx5_port_to_eswitch_info(port, false);
3617         if (!act_priv)
3618                 return rte_flow_error_set
3619                                 (error, rte_errno,
3620                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3621                                  "failed to obtain E-Switch port id for port");
3622         if (act_priv->domain_id != dev_priv->domain_id)
3623                 return rte_flow_error_set
3624                                 (error, EINVAL,
3625                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3626                                  "port does not belong to"
3627                                  " E-Switch being configured");
3628         return 0;
3629 }
3630
3631 /**
3632  * Get the maximum number of modify header actions.
3633  *
3634  * @param dev
3635  *   Pointer to rte_eth_dev structure.
3636  * @param flags
3637  *   Flags bits to check if root level.
3638  *
3639  * @return
3640  *   Max number of modify header actions device can support.
3641  */
3642 static unsigned int
3643 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3644 {
3645         /*
3646          * There's no way to directly query the max cap. Although it has to be
3647          * acquried by iterative trial, it is a safe assumption that more
3648          * actions are supported by FW if extensive metadata register is
3649          * supported. (Only in the root table)
3650          */
3651         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3652                 return MLX5_MAX_MODIFY_NUM;
3653         else
3654                 return mlx5_flow_ext_mreg_supported(dev) ?
3655                                         MLX5_ROOT_TBL_MODIFY_NUM :
3656                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3657 }
3658
3659 /**
3660  * Validate the meter action.
3661  *
3662  * @param[in] dev
3663  *   Pointer to rte_eth_dev structure.
3664  * @param[in] action_flags
3665  *   Bit-fields that holds the actions detected until now.
3666  * @param[in] action
3667  *   Pointer to the meter action.
3668  * @param[in] attr
3669  *   Attributes of flow that includes this action.
3670  * @param[out] error
3671  *   Pointer to error structure.
3672  *
3673  * @return
3674  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3675  */
3676 static int
3677 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3678                                 uint64_t action_flags,
3679                                 const struct rte_flow_action *action,
3680                                 const struct rte_flow_attr *attr,
3681                                 struct rte_flow_error *error)
3682 {
3683         struct mlx5_priv *priv = dev->data->dev_private;
3684         const struct rte_flow_action_meter *am = action->conf;
3685         struct mlx5_flow_meter *fm;
3686
3687         if (!am)
3688                 return rte_flow_error_set(error, EINVAL,
3689                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3690                                           "meter action conf is NULL");
3691
3692         if (action_flags & MLX5_FLOW_ACTION_METER)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3695                                           "meter chaining not support");
3696         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3697                 return rte_flow_error_set(error, ENOTSUP,
3698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699                                           "meter with jump not support");
3700         if (!priv->mtr_en)
3701                 return rte_flow_error_set(error, ENOTSUP,
3702                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3703                                           NULL,
3704                                           "meter action not supported");
3705         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3706         if (!fm)
3707                 return rte_flow_error_set(error, EINVAL,
3708                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3709                                           "Meter not found");
3710         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3711               (!fm->ingress && !attr->ingress && attr->egress) ||
3712               (!fm->egress && !attr->egress && attr->ingress))))
3713                 return rte_flow_error_set(error, EINVAL,
3714                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3715                                           "Flow attributes are either invalid "
3716                                           "or have a conflict with current "
3717                                           "meter attributes");
3718         return 0;
3719 }
3720
3721 /**
3722  * Validate the modify-header IPv4 DSCP actions.
3723  *
3724  * @param[in] action_flags
3725  *   Holds the actions detected until now.
3726  * @param[in] action
3727  *   Pointer to the modify action.
3728  * @param[in] item_flags
3729  *   Holds the items detected.
3730  * @param[out] error
3731  *   Pointer to error structure.
3732  *
3733  * @return
3734  *   0 on success, a negative errno value otherwise and rte_errno is set.
3735  */
3736 static int
3737 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3738                                          const struct rte_flow_action *action,
3739                                          const uint64_t item_flags,
3740                                          struct rte_flow_error *error)
3741 {
3742         int ret = 0;
3743
3744         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3745         if (!ret) {
3746                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3747                         return rte_flow_error_set(error, EINVAL,
3748                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3749                                                   NULL,
3750                                                   "no ipv4 item in pattern");
3751         }
3752         return ret;
3753 }
3754
3755 /**
3756  * Validate the modify-header IPv6 DSCP actions.
3757  *
3758  * @param[in] action_flags
3759  *   Holds the actions detected until now.
3760  * @param[in] action
3761  *   Pointer to the modify action.
3762  * @param[in] item_flags
3763  *   Holds the items detected.
3764  * @param[out] error
3765  *   Pointer to error structure.
3766  *
3767  * @return
3768  *   0 on success, a negative errno value otherwise and rte_errno is set.
3769  */
3770 static int
3771 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3772                                          const struct rte_flow_action *action,
3773                                          const uint64_t item_flags,
3774                                          struct rte_flow_error *error)
3775 {
3776         int ret = 0;
3777
3778         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3779         if (!ret) {
3780                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3781                         return rte_flow_error_set(error, EINVAL,
3782                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3783                                                   NULL,
3784                                                   "no ipv6 item in pattern");
3785         }
3786         return ret;
3787 }
3788
3789 /**
3790  * Find existing modify-header resource or create and register a new one.
3791  *
3792  * @param dev[in, out]
3793  *   Pointer to rte_eth_dev structure.
3794  * @param[in, out] resource
3795  *   Pointer to modify-header resource.
3796  * @parm[in, out] dev_flow
3797  *   Pointer to the dev_flow.
3798  * @param[out] error
3799  *   pointer to error structure.
3800  *
3801  * @return
3802  *   0 on success otherwise -errno and errno is set.
3803  */
3804 static int
3805 flow_dv_modify_hdr_resource_register
3806                         (struct rte_eth_dev *dev,
3807                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3808                          struct mlx5_flow *dev_flow,
3809                          struct rte_flow_error *error)
3810 {
3811         struct mlx5_priv *priv = dev->data->dev_private;
3812         struct mlx5_ibv_shared *sh = priv->sh;
3813         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3814         struct mlx5dv_dr_domain *ns;
3815         uint32_t actions_len;
3816
3817         resource->flags = dev_flow->dv.group ? 0 :
3818                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3819         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3820                                     resource->flags))
3821                 return rte_flow_error_set(error, EOVERFLOW,
3822                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823                                           "too many modify header items");
3824         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3825                 ns = sh->fdb_domain;
3826         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3827                 ns = sh->tx_domain;
3828         else
3829                 ns = sh->rx_domain;
3830         /* Lookup a matching resource from cache. */
3831         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3832         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3833                 if (resource->ft_type == cache_resource->ft_type &&
3834                     resource->actions_num == cache_resource->actions_num &&
3835                     resource->flags == cache_resource->flags &&
3836                     !memcmp((const void *)resource->actions,
3837                             (const void *)cache_resource->actions,
3838                             actions_len)) {
3839                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3840                                 (void *)cache_resource,
3841                                 rte_atomic32_read(&cache_resource->refcnt));
3842                         rte_atomic32_inc(&cache_resource->refcnt);
3843                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3844                         return 0;
3845                 }
3846         }
3847         /* Register new modify-header resource. */
3848         cache_resource = rte_calloc(__func__, 1,
3849                                     sizeof(*cache_resource) + actions_len, 0);
3850         if (!cache_resource)
3851                 return rte_flow_error_set(error, ENOMEM,
3852                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853                                           "cannot allocate resource memory");
3854         *cache_resource = *resource;
3855         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3856         cache_resource->verbs_action =
3857                 mlx5_glue->dv_create_flow_action_modify_header
3858                                         (sh->ctx, cache_resource->ft_type, ns,
3859                                          cache_resource->flags, actions_len,
3860                                          (uint64_t *)cache_resource->actions);
3861         if (!cache_resource->verbs_action) {
3862                 rte_free(cache_resource);
3863                 return rte_flow_error_set(error, ENOMEM,
3864                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3865                                           NULL, "cannot create action");
3866         }
3867         rte_atomic32_init(&cache_resource->refcnt);
3868         rte_atomic32_inc(&cache_resource->refcnt);
3869         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3870         dev_flow->handle->dvh.modify_hdr = cache_resource;
3871         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3872                 (void *)cache_resource,
3873                 rte_atomic32_read(&cache_resource->refcnt));
3874         return 0;
3875 }
3876
3877 /**
3878  * Get DV flow counter by index.
3879  *
3880  * @param[in] dev
3881  *   Pointer to the Ethernet device structure.
3882  * @param[in] idx
3883  *   mlx5 flow counter index in the container.
3884  * @param[out] ppool
3885  *   mlx5 flow counter pool in the container,
3886  *
3887  * @return
3888  *   Pointer to the counter, NULL otherwise.
3889  */
3890 static struct mlx5_flow_counter *
3891 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3892                            uint32_t idx,
3893                            struct mlx5_flow_counter_pool **ppool)
3894 {
3895         struct mlx5_priv *priv = dev->data->dev_private;
3896         struct mlx5_pools_container *cont;
3897         struct mlx5_flow_counter_pool *pool;
3898         uint32_t batch = 0;
3899
3900         idx--;
3901         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3902                 idx -= MLX5_CNT_BATCH_OFFSET;
3903                 batch = 1;
3904         }
3905         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3906         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3907         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3908         MLX5_ASSERT(pool);
3909         if (ppool)
3910                 *ppool = pool;
3911         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3912 }
3913
3914 /**
3915  * Get a pool by devx counter ID.
3916  *
3917  * @param[in] cont
3918  *   Pointer to the counter container.
3919  * @param[in] id
3920  *   The counter devx ID.
3921  *
3922  * @return
3923  *   The counter pool pointer if exists, NULL otherwise,
3924  */
3925 static struct mlx5_flow_counter_pool *
3926 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3927 {
3928         uint32_t i;
3929         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3930
3931         for (i = 0; i < n_valid; i++) {
3932                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3933                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3934                            MLX5_COUNTERS_PER_POOL;
3935
3936                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3937                         /*
3938                          * Move the pool to the head, as counter allocate
3939                          * always gets the first pool in the container.
3940                          */
3941                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3942                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3943                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3944                         }
3945                         return pool;
3946                 }
3947         }
3948         return NULL;
3949 }
3950
3951 /**
3952  * Allocate a new memory for the counter values wrapped by all the needed
3953  * management.
3954  *
3955  * @param[in] dev
3956  *   Pointer to the Ethernet device structure.
3957  * @param[in] raws_n
3958  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3959  *
3960  * @return
3961  *   The new memory management pointer on success, otherwise NULL and rte_errno
3962  *   is set.
3963  */
3964 static struct mlx5_counter_stats_mem_mng *
3965 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3966 {
3967         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3968                                         (dev->data->dev_private))->sh;
3969         struct mlx5_devx_mkey_attr mkey_attr;
3970         struct mlx5_counter_stats_mem_mng *mem_mng;
3971         volatile struct flow_counter_stats *raw_data;
3972         int size = (sizeof(struct flow_counter_stats) *
3973                         MLX5_COUNTERS_PER_POOL +
3974                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3975                         sizeof(struct mlx5_counter_stats_mem_mng);
3976         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3977         int i;
3978
3979         if (!mem) {
3980                 rte_errno = ENOMEM;
3981                 return NULL;
3982         }
3983         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3984         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3985         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3986                                                  IBV_ACCESS_LOCAL_WRITE);
3987         if (!mem_mng->umem) {
3988                 rte_errno = errno;
3989                 rte_free(mem);
3990                 return NULL;
3991         }
3992         mkey_attr.addr = (uintptr_t)mem;
3993         mkey_attr.size = size;
3994         mkey_attr.umem_id = mem_mng->umem->umem_id;
3995         mkey_attr.pd = sh->pdn;
3996         mkey_attr.log_entity_size = 0;
3997         mkey_attr.pg_access = 0;
3998         mkey_attr.klm_array = NULL;
3999         mkey_attr.klm_num = 0;
4000         mkey_attr.relaxed_ordering = 1;
4001         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4002         if (!mem_mng->dm) {
4003                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4004                 rte_errno = errno;
4005                 rte_free(mem);
4006                 return NULL;
4007         }
4008         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4009         raw_data = (volatile struct flow_counter_stats *)mem;
4010         for (i = 0; i < raws_n; ++i) {
4011                 mem_mng->raws[i].mem_mng = mem_mng;
4012                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4013         }
4014         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4015         return mem_mng;
4016 }
4017
4018 /**
4019  * Resize a counter container.
4020  *
4021  * @param[in] dev
4022  *   Pointer to the Ethernet device structure.
4023  * @param[in] batch
4024  *   Whether the pool is for counter that was allocated by batch command.
4025  *
4026  * @return
4027  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4028  */
4029 static struct mlx5_pools_container *
4030 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4031 {
4032         struct mlx5_priv *priv = dev->data->dev_private;
4033         struct mlx5_pools_container *cont =
4034                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4035         struct mlx5_pools_container *new_cont =
4036                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4037         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4038         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4039         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4040         int i;
4041
4042         /* Fallback mode has no background thread. Skip the check. */
4043         if (!priv->counter_fallback &&
4044             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4045                 /* The last resize still hasn't detected by the host thread. */
4046                 rte_errno = EAGAIN;
4047                 return NULL;
4048         }
4049         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4050         if (!new_cont->pools) {
4051                 rte_errno = ENOMEM;
4052                 return NULL;
4053         }
4054         if (cont->n)
4055                 memcpy(new_cont->pools, cont->pools, cont->n *
4056                        sizeof(struct mlx5_flow_counter_pool *));
4057         /*
4058          * Fallback mode query the counter directly, no background query
4059          * resources are needed.
4060          */
4061         if (!priv->counter_fallback) {
4062                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4063                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4064                 if (!mem_mng) {
4065                         rte_free(new_cont->pools);
4066                         return NULL;
4067                 }
4068                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4069                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4070                                          mem_mng->raws +
4071                                          MLX5_CNT_CONTAINER_RESIZE +
4072                                          i, next);
4073         } else {
4074                 /*
4075                  * Release the old container pools directly as no background
4076                  * thread helps that.
4077                  */
4078                 rte_free(cont->pools);
4079         }
4080         new_cont->n = resize;
4081         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4082         TAILQ_INIT(&new_cont->pool_list);
4083         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4084         new_cont->init_mem_mng = mem_mng;
4085         rte_cio_wmb();
4086          /* Flip the master container. */
4087         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4088         return new_cont;
4089 }
4090
4091 /**
4092  * Query a devx flow counter.
4093  *
4094  * @param[in] dev
4095  *   Pointer to the Ethernet device structure.
4096  * @param[in] cnt
4097  *   Index to the flow counter.
4098  * @param[out] pkts
4099  *   The statistics value of packets.
4100  * @param[out] bytes
4101  *   The statistics value of bytes.
4102  *
4103  * @return
4104  *   0 on success, otherwise a negative errno value and rte_errno is set.
4105  */
4106 static inline int
4107 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4108                      uint64_t *bytes)
4109 {
4110         struct mlx5_priv *priv = dev->data->dev_private;
4111         struct mlx5_flow_counter_pool *pool = NULL;
4112         struct mlx5_flow_counter *cnt;
4113         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4114         int offset;
4115
4116         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4117         MLX5_ASSERT(pool);
4118         if (counter < MLX5_CNT_BATCH_OFFSET) {
4119                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4120                 if (priv->counter_fallback)
4121                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4122                                         0, pkts, bytes, 0, NULL, NULL, 0);
4123         }
4124
4125         rte_spinlock_lock(&pool->sl);
4126         /*
4127          * The single counters allocation may allocate smaller ID than the
4128          * current allocated in parallel to the host reading.
4129          * In this case the new counter values must be reported as 0.
4130          */
4131         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4132                 *pkts = 0;
4133                 *bytes = 0;
4134         } else {
4135                 offset = cnt - &pool->counters_raw[0];
4136                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4137                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4138         }
4139         rte_spinlock_unlock(&pool->sl);
4140         return 0;
4141 }
4142
4143 /**
4144  * Create and initialize a new counter pool.
4145  *
4146  * @param[in] dev
4147  *   Pointer to the Ethernet device structure.
4148  * @param[out] dcs
4149  *   The devX counter handle.
4150  * @param[in] batch
4151  *   Whether the pool is for counter that was allocated by batch command.
4152  * @param[in/out] cont_cur
4153  *   Pointer to the container pointer, it will be update in pool resize.
4154  *
4155  * @return
4156  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4157  */
4158 static struct mlx5_pools_container *
4159 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4160                     uint32_t batch)
4161 {
4162         struct mlx5_priv *priv = dev->data->dev_private;
4163         struct mlx5_flow_counter_pool *pool;
4164         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4165                                                                0);
4166         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4167         uint32_t size;
4168
4169         if (cont->n == n_valid) {
4170                 cont = flow_dv_container_resize(dev, batch);
4171                 if (!cont)
4172                         return NULL;
4173         }
4174         size = sizeof(*pool);
4175         if (!batch)
4176                 size += MLX5_COUNTERS_PER_POOL *
4177                         sizeof(struct mlx5_flow_counter_ext);
4178         pool = rte_calloc(__func__, 1, size, 0);
4179         if (!pool) {
4180                 rte_errno = ENOMEM;
4181                 return NULL;
4182         }
4183         pool->min_dcs = dcs;
4184         if (!priv->counter_fallback)
4185                 pool->raw = cont->init_mem_mng->raws + n_valid %
4186                                                      MLX5_CNT_CONTAINER_RESIZE;
4187         pool->raw_hw = NULL;
4188         rte_spinlock_init(&pool->sl);
4189         /*
4190          * The generation of the new allocated counters in this pool is 0, 2 in
4191          * the pool generation makes all the counters valid for allocation.
4192          * The start and end query generation protect the counters be released
4193          * between the query and update gap period will not be reallocated
4194          * without the last query finished and stats updated to the memory.
4195          */
4196         rte_atomic64_set(&pool->start_query_gen, 0x2);
4197         /*
4198          * There's no background query thread for fallback mode, set the
4199          * end_query_gen to the maximum value since no need to wait for
4200          * statistics update.
4201          */
4202         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4203                          INT64_MAX : 0x2);
4204         TAILQ_INIT(&pool->counters);
4205         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4206         pool->index = n_valid;
4207         cont->pools[n_valid] = pool;
4208         /* Pool initialization must be updated before host thread access. */
4209         rte_cio_wmb();
4210         rte_atomic16_add(&cont->n_valid, 1);
4211         return cont;
4212 }
4213
4214 /**
4215  * Prepare a new counter and/or a new counter pool.
4216  *
4217  * @param[in] dev
4218  *   Pointer to the Ethernet device structure.
4219  * @param[out] cnt_free
4220  *   Where to put the pointer of a new counter.
4221  * @param[in] batch
4222  *   Whether the pool is for counter that was allocated by batch command.
4223  *
4224  * @return
4225  *   The counter container pointer and @p cnt_free is set on success,
4226  *   NULL otherwise and rte_errno is set.
4227  */
4228 static struct mlx5_pools_container *
4229 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4230                              struct mlx5_flow_counter **cnt_free,
4231                              uint32_t batch)
4232 {
4233         struct mlx5_priv *priv = dev->data->dev_private;
4234         struct mlx5_pools_container *cont;
4235         struct mlx5_flow_counter_pool *pool;
4236         struct mlx5_devx_obj *dcs = NULL;
4237         struct mlx5_flow_counter *cnt;
4238         uint32_t i;
4239
4240         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4241         if (!batch) {
4242                 /* bulk_bitmap must be 0 for single counter allocation. */
4243                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4244                 if (!dcs)
4245                         return NULL;
4246                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4247                 if (!pool) {
4248                         cont = flow_dv_pool_create(dev, dcs, batch);
4249                         if (!cont) {
4250                                 mlx5_devx_cmd_destroy(dcs);
4251                                 return NULL;
4252                         }
4253                         pool = TAILQ_FIRST(&cont->pool_list);
4254                 } else if (dcs->id < pool->min_dcs->id) {
4255                         rte_atomic64_set(&pool->a64_dcs,
4256                                          (int64_t)(uintptr_t)dcs);
4257                 }
4258                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4259                 cnt = &pool->counters_raw[i];
4260                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4261                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4262                 *cnt_free = cnt;
4263                 return cont;
4264         }
4265         /* bulk_bitmap is in 128 counters units. */
4266         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4267                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4268         if (!dcs) {
4269                 rte_errno = ENODATA;
4270                 return NULL;
4271         }
4272         cont = flow_dv_pool_create(dev, dcs, batch);
4273         if (!cont) {
4274                 mlx5_devx_cmd_destroy(dcs);
4275                 return NULL;
4276         }
4277         pool = TAILQ_FIRST(&cont->pool_list);
4278         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4279                 cnt = &pool->counters_raw[i];
4280                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4281         }
4282         *cnt_free = &pool->counters_raw[0];
4283         return cont;
4284 }
4285
4286 /**
4287  * Search for existed shared counter.
4288  *
4289  * @param[in] cont
4290  *   Pointer to the relevant counter pool container.
4291  * @param[in] id
4292  *   The shared counter ID to search.
4293  * @param[out] ppool
4294  *   mlx5 flow counter pool in the container,
4295  *
4296  * @return
4297  *   NULL if not existed, otherwise pointer to the shared extend counter.
4298  */
4299 static struct mlx5_flow_counter_ext *
4300 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4301                               struct mlx5_flow_counter_pool **ppool)
4302 {
4303         static struct mlx5_flow_counter_ext *cnt;
4304         struct mlx5_flow_counter_pool *pool;
4305         uint32_t i;
4306         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4307
4308         for (i = 0; i < n_valid; i++) {
4309                 pool = cont->pools[i];
4310                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4311                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4312                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4313                                 if (ppool)
4314                                         *ppool = cont->pools[i];
4315                                 return cnt;
4316                         }
4317                 }
4318         }
4319         return NULL;
4320 }
4321
4322 /**
4323  * Allocate a flow counter.
4324  *
4325  * @param[in] dev
4326  *   Pointer to the Ethernet device structure.
4327  * @param[in] shared
4328  *   Indicate if this counter is shared with other flows.
4329  * @param[in] id
4330  *   Counter identifier.
4331  * @param[in] group
4332  *   Counter flow group.
4333  *
4334  * @return
4335  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4336  */
4337 static uint32_t
4338 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4339                       uint16_t group)
4340 {
4341         struct mlx5_priv *priv = dev->data->dev_private;
4342         struct mlx5_flow_counter_pool *pool = NULL;
4343         struct mlx5_flow_counter *cnt_free = NULL;
4344         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4345         /*
4346          * Currently group 0 flow counter cannot be assigned to a flow if it is
4347          * not the first one in the batch counter allocation, so it is better
4348          * to allocate counters one by one for these flows in a separate
4349          * container.
4350          * A counter can be shared between different groups so need to take
4351          * shared counters from the single container.
4352          */
4353         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4354         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4355                                                                0);
4356         uint32_t cnt_idx;
4357
4358         if (!priv->config.devx) {
4359                 rte_errno = ENOTSUP;
4360                 return 0;
4361         }
4362         if (shared) {
4363                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4364                 if (cnt_ext) {
4365                         if (cnt_ext->ref_cnt + 1 == 0) {
4366                                 rte_errno = E2BIG;
4367                                 return 0;
4368                         }
4369                         cnt_ext->ref_cnt++;
4370                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4371                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4372                                   + 1;
4373                         return cnt_idx;
4374                 }
4375         }
4376         /* Pools which has a free counters are in the start. */
4377         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4378                 /*
4379                  * The free counter reset values must be updated between the
4380                  * counter release to the counter allocation, so, at least one
4381                  * query must be done in this time. ensure it by saving the
4382                  * query generation in the release time.
4383                  * The free list is sorted according to the generation - so if
4384                  * the first one is not updated, all the others are not
4385                  * updated too.
4386                  */
4387                 cnt_free = TAILQ_FIRST(&pool->counters);
4388                 if (cnt_free && cnt_free->query_gen <
4389                     rte_atomic64_read(&pool->end_query_gen))
4390                         break;
4391                 cnt_free = NULL;
4392         }
4393         if (!cnt_free) {
4394                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4395                 if (!cont)
4396                         return 0;
4397                 pool = TAILQ_FIRST(&cont->pool_list);
4398         }
4399         if (!batch)
4400                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4401         /* Create a DV counter action only in the first time usage. */
4402         if (!cnt_free->action) {
4403                 uint16_t offset;
4404                 struct mlx5_devx_obj *dcs;
4405
4406                 if (batch) {
4407                         offset = cnt_free - &pool->counters_raw[0];
4408                         dcs = pool->min_dcs;
4409                 } else {
4410                         offset = 0;
4411                         dcs = cnt_ext->dcs;
4412                 }
4413                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4414                                         (dcs->obj, offset);
4415                 if (!cnt_free->action) {
4416                         rte_errno = errno;
4417                         return 0;
4418                 }
4419         }
4420         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4421                                     (cnt_free - pool->counters_raw));
4422         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4423         /* Update the counter reset values. */
4424         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4425                                  &cnt_free->bytes))
4426                 return 0;
4427         if (cnt_ext) {
4428                 cnt_ext->shared = shared;
4429                 cnt_ext->ref_cnt = 1;
4430                 cnt_ext->id = id;
4431         }
4432         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4433                 /* Start the asynchronous batch query by the host thread. */
4434                 mlx5_set_query_alarm(priv->sh);
4435         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4436         if (TAILQ_EMPTY(&pool->counters)) {
4437                 /* Move the pool to the end of the container pool list. */
4438                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4439                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4440         }
4441         return cnt_idx;
4442 }
4443
4444 /**
4445  * Release a flow counter.
4446  *
4447  * @param[in] dev
4448  *   Pointer to the Ethernet device structure.
4449  * @param[in] counter
4450  *   Index to the counter handler.
4451  */
4452 static void
4453 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4454 {
4455         struct mlx5_flow_counter_pool *pool = NULL;
4456         struct mlx5_flow_counter *cnt;
4457         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4458
4459         if (!counter)
4460                 return;
4461         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4462         MLX5_ASSERT(pool);
4463         if (counter < MLX5_CNT_BATCH_OFFSET) {
4464                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4465                 if (cnt_ext && --cnt_ext->ref_cnt)
4466                         return;
4467         }
4468         /* Put the counter in the end - the last updated one. */
4469         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4470         /*
4471          * Counters released between query trigger and handler need
4472          * to wait the next round of query. Since the packets arrive
4473          * in the gap period will not be taken into account to the
4474          * old counter.
4475          */
4476         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4477 }
4478
4479 /**
4480  * Verify the @p attributes will be correctly understood by the NIC and store
4481  * them in the @p flow if everything is correct.
4482  *
4483  * @param[in] dev
4484  *   Pointer to dev struct.
4485  * @param[in] attributes
4486  *   Pointer to flow attributes
4487  * @param[in] external
4488  *   This flow rule is created by request external to PMD.
4489  * @param[out] error
4490  *   Pointer to error structure.
4491  *
4492  * @return
4493  *   0 on success, a negative errno value otherwise and rte_errno is set.
4494  */
4495 static int
4496 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4497                             const struct rte_flow_attr *attributes,
4498                             bool external __rte_unused,
4499                             struct rte_flow_error *error)
4500 {
4501         struct mlx5_priv *priv = dev->data->dev_private;
4502         uint32_t priority_max = priv->config.flow_prio - 1;
4503
4504 #ifndef HAVE_MLX5DV_DR
4505         if (attributes->group)
4506                 return rte_flow_error_set(error, ENOTSUP,
4507                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4508                                           NULL,
4509                                           "groups are not supported");
4510 #else
4511         uint32_t table;
4512         int ret;
4513
4514         ret = mlx5_flow_group_to_table(attributes, external,
4515                                        attributes->group, !!priv->fdb_def_rule,
4516                                        &table, error);
4517         if (ret)
4518                 return ret;
4519 #endif
4520         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4521             attributes->priority >= priority_max)
4522                 return rte_flow_error_set(error, ENOTSUP,
4523                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4524                                           NULL,
4525                                           "priority out of range");
4526         if (attributes->transfer) {
4527                 if (!priv->config.dv_esw_en)
4528                         return rte_flow_error_set
4529                                 (error, ENOTSUP,
4530                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4531                                  "E-Switch dr is not supported");
4532                 if (!(priv->representor || priv->master))
4533                         return rte_flow_error_set
4534                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4535                                  NULL, "E-Switch configuration can only be"
4536                                  " done by a master or a representor device");
4537                 if (attributes->egress)
4538                         return rte_flow_error_set
4539                                 (error, ENOTSUP,
4540                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4541                                  "egress is not supported");
4542         }
4543         if (!(attributes->egress ^ attributes->ingress))
4544                 return rte_flow_error_set(error, ENOTSUP,
4545                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4546                                           "must specify exactly one of "
4547                                           "ingress or egress");
4548         return 0;
4549 }
4550
4551 /**
4552  * Internal validation function. For validating both actions and items.
4553  *
4554  * @param[in] dev
4555  *   Pointer to the rte_eth_dev structure.
4556  * @param[in] attr
4557  *   Pointer to the flow attributes.
4558  * @param[in] items
4559  *   Pointer to the list of items.
4560  * @param[in] actions
4561  *   Pointer to the list of actions.
4562  * @param[in] external
4563  *   This flow rule is created by request external to PMD.
4564  * @param[out] error
4565  *   Pointer to the error structure.
4566  *
4567  * @return
4568  *   0 on success, a negative errno value otherwise and rte_errno is set.
4569  */
4570 static int
4571 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4572                  const struct rte_flow_item items[],
4573                  const struct rte_flow_action actions[],
4574                  bool external, struct rte_flow_error *error)
4575 {
4576         int ret;
4577         uint64_t action_flags = 0;
4578         uint64_t item_flags = 0;
4579         uint64_t last_item = 0;
4580         uint8_t next_protocol = 0xff;
4581         uint16_t ether_type = 0;
4582         int actions_n = 0;
4583         uint8_t item_ipv6_proto = 0;
4584         const struct rte_flow_item *gre_item = NULL;
4585         const struct rte_flow_action_raw_decap *decap;
4586         const struct rte_flow_action_raw_encap *encap;
4587         const struct rte_flow_action_rss *rss;
4588         const struct rte_flow_item_tcp nic_tcp_mask = {
4589                 .hdr = {
4590                         .tcp_flags = 0xFF,
4591                         .src_port = RTE_BE16(UINT16_MAX),
4592                         .dst_port = RTE_BE16(UINT16_MAX),
4593                 }
4594         };
4595         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4596                 .hdr = {
4597                         .src_addr = RTE_BE32(0xffffffff),
4598                         .dst_addr = RTE_BE32(0xffffffff),
4599                         .type_of_service = 0xff,
4600                         .next_proto_id = 0xff,
4601                         .time_to_live = 0xff,
4602                 },
4603         };
4604         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4605                 .hdr = {
4606                         .src_addr =
4607                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4608                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4609                         .dst_addr =
4610                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4611                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4612                         .vtc_flow = RTE_BE32(0xffffffff),
4613                         .proto = 0xff,
4614                         .hop_limits = 0xff,
4615                 },
4616         };
4617         struct mlx5_priv *priv = dev->data->dev_private;
4618         struct mlx5_dev_config *dev_conf = &priv->config;
4619         uint16_t queue_index = 0xFFFF;
4620         const struct rte_flow_item_vlan *vlan_m = NULL;
4621
4622         if (items == NULL)
4623                 return -1;
4624         ret = flow_dv_validate_attributes(dev, attr, external, error);
4625         if (ret < 0)
4626                 return ret;
4627         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4628                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4629                 int type = items->type;
4630
4631                 switch (type) {
4632                 case RTE_FLOW_ITEM_TYPE_VOID:
4633                         break;
4634                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4635                         ret = flow_dv_validate_item_port_id
4636                                         (dev, items, attr, item_flags, error);
4637                         if (ret < 0)
4638                                 return ret;
4639                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4640                         break;
4641                 case RTE_FLOW_ITEM_TYPE_ETH:
4642                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4643                                                           error);
4644                         if (ret < 0)
4645                                 return ret;
4646                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4647                                              MLX5_FLOW_LAYER_OUTER_L2;
4648                         if (items->mask != NULL && items->spec != NULL) {
4649                                 ether_type =
4650                                         ((const struct rte_flow_item_eth *)
4651                                          items->spec)->type;
4652                                 ether_type &=
4653                                         ((const struct rte_flow_item_eth *)
4654                                          items->mask)->type;
4655                                 ether_type = rte_be_to_cpu_16(ether_type);
4656                         } else {
4657                                 ether_type = 0;
4658                         }
4659                         break;
4660                 case RTE_FLOW_ITEM_TYPE_VLAN:
4661                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4662                                                            dev, error);
4663                         if (ret < 0)
4664                                 return ret;
4665                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4666                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4667                         if (items->mask != NULL && items->spec != NULL) {
4668                                 ether_type =
4669                                         ((const struct rte_flow_item_vlan *)
4670                                          items->spec)->inner_type;
4671                                 ether_type &=
4672                                         ((const struct rte_flow_item_vlan *)
4673                                          items->mask)->inner_type;
4674                                 ether_type = rte_be_to_cpu_16(ether_type);
4675                         } else {
4676                                 ether_type = 0;
4677                         }
4678                         /* Store outer VLAN mask for of_push_vlan action. */
4679                         if (!tunnel)
4680                                 vlan_m = items->mask;
4681                         break;
4682                 case RTE_FLOW_ITEM_TYPE_IPV4:
4683                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4684                                                   &item_flags, &tunnel);
4685                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4686                                                            last_item,
4687                                                            ether_type,
4688                                                            &nic_ipv4_mask,
4689                                                            error);
4690                         if (ret < 0)
4691                                 return ret;
4692                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4693                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4694                         if (items->mask != NULL &&
4695                             ((const struct rte_flow_item_ipv4 *)
4696                              items->mask)->hdr.next_proto_id) {
4697                                 next_protocol =
4698                                         ((const struct rte_flow_item_ipv4 *)
4699                                          (items->spec))->hdr.next_proto_id;
4700                                 next_protocol &=
4701                                         ((const struct rte_flow_item_ipv4 *)
4702                                          (items->mask))->hdr.next_proto_id;
4703                         } else {
4704                                 /* Reset for inner layer. */
4705                                 next_protocol = 0xff;
4706                         }
4707                         break;
4708                 case RTE_FLOW_ITEM_TYPE_IPV6:
4709                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4710                                                   &item_flags, &tunnel);
4711                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4712                                                            last_item,
4713                                                            ether_type,
4714                                                            &nic_ipv6_mask,
4715                                                            error);
4716                         if (ret < 0)
4717                                 return ret;
4718                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4719                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4720                         if (items->mask != NULL &&
4721                             ((const struct rte_flow_item_ipv6 *)
4722                              items->mask)->hdr.proto) {
4723                                 item_ipv6_proto =
4724                                         ((const struct rte_flow_item_ipv6 *)
4725                                          items->spec)->hdr.proto;
4726                                 next_protocol =
4727                                         ((const struct rte_flow_item_ipv6 *)
4728                                          items->spec)->hdr.proto;
4729                                 next_protocol &=
4730                                         ((const struct rte_flow_item_ipv6 *)
4731                                          items->mask)->hdr.proto;
4732                         } else {
4733                                 /* Reset for inner layer. */
4734                                 next_protocol = 0xff;
4735                         }
4736                         break;
4737                 case RTE_FLOW_ITEM_TYPE_TCP:
4738                         ret = mlx5_flow_validate_item_tcp
4739                                                 (items, item_flags,
4740                                                  next_protocol,
4741                                                  &nic_tcp_mask,
4742                                                  error);
4743                         if (ret < 0)
4744                                 return ret;
4745                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4746                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4747                         break;
4748                 case RTE_FLOW_ITEM_TYPE_UDP:
4749                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4750                                                           next_protocol,
4751                                                           error);
4752                         if (ret < 0)
4753                                 return ret;
4754                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4755                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4756                         break;
4757                 case RTE_FLOW_ITEM_TYPE_GRE:
4758                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4759                                                           next_protocol, error);
4760                         if (ret < 0)
4761                                 return ret;
4762                         gre_item = items;
4763                         last_item = MLX5_FLOW_LAYER_GRE;
4764                         break;
4765                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4766                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4767                                                             next_protocol,
4768                                                             error);
4769                         if (ret < 0)
4770                                 return ret;
4771                         last_item = MLX5_FLOW_LAYER_NVGRE;
4772                         break;
4773                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4774                         ret = mlx5_flow_validate_item_gre_key
4775                                 (items, item_flags, gre_item, error);
4776                         if (ret < 0)
4777                                 return ret;
4778                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4779                         break;
4780                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4781                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4782                                                             error);
4783                         if (ret < 0)
4784                                 return ret;
4785                         last_item = MLX5_FLOW_LAYER_VXLAN;
4786                         break;
4787                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4788                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4789                                                                 item_flags, dev,
4790                                                                 error);
4791                         if (ret < 0)
4792                                 return ret;
4793                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4794                         break;
4795                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4796                         ret = mlx5_flow_validate_item_geneve(items,
4797                                                              item_flags, dev,
4798                                                              error);
4799                         if (ret < 0)
4800                                 return ret;
4801                         last_item = MLX5_FLOW_LAYER_GENEVE;
4802                         break;
4803                 case RTE_FLOW_ITEM_TYPE_MPLS:
4804                         ret = mlx5_flow_validate_item_mpls(dev, items,
4805                                                            item_flags,
4806                                                            last_item, error);
4807                         if (ret < 0)
4808                                 return ret;
4809                         last_item = MLX5_FLOW_LAYER_MPLS;
4810                         break;
4811
4812                 case RTE_FLOW_ITEM_TYPE_MARK:
4813                         ret = flow_dv_validate_item_mark(dev, items, attr,
4814                                                          error);
4815                         if (ret < 0)
4816                                 return ret;
4817                         last_item = MLX5_FLOW_ITEM_MARK;
4818                         break;
4819                 case RTE_FLOW_ITEM_TYPE_META:
4820                         ret = flow_dv_validate_item_meta(dev, items, attr,
4821                                                          error);
4822                         if (ret < 0)
4823                                 return ret;
4824                         last_item = MLX5_FLOW_ITEM_METADATA;
4825                         break;
4826                 case RTE_FLOW_ITEM_TYPE_ICMP:
4827                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4828                                                            next_protocol,
4829                                                            error);
4830                         if (ret < 0)
4831                                 return ret;
4832                         last_item = MLX5_FLOW_LAYER_ICMP;
4833                         break;
4834                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4835                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4836                                                             next_protocol,
4837                                                             error);
4838                         if (ret < 0)
4839                                 return ret;
4840                         item_ipv6_proto = IPPROTO_ICMPV6;
4841                         last_item = MLX5_FLOW_LAYER_ICMP6;
4842                         break;
4843                 case RTE_FLOW_ITEM_TYPE_TAG:
4844                         ret = flow_dv_validate_item_tag(dev, items,
4845                                                         attr, error);
4846                         if (ret < 0)
4847                                 return ret;
4848                         last_item = MLX5_FLOW_ITEM_TAG;
4849                         break;
4850                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4851                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4852                         break;
4853                 case RTE_FLOW_ITEM_TYPE_GTP:
4854                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4855                                                         error);
4856                         if (ret < 0)
4857                                 return ret;
4858                         last_item = MLX5_FLOW_LAYER_GTP;
4859                         break;
4860                 default:
4861                         return rte_flow_error_set(error, ENOTSUP,
4862                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4863                                                   NULL, "item not supported");
4864                 }
4865                 item_flags |= last_item;
4866         }
4867         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4868                 int type = actions->type;
4869                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4870                         return rte_flow_error_set(error, ENOTSUP,
4871                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4872                                                   actions, "too many actions");
4873                 switch (type) {
4874                 case RTE_FLOW_ACTION_TYPE_VOID:
4875                         break;
4876                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4877                         ret = flow_dv_validate_action_port_id(dev,
4878                                                               action_flags,
4879                                                               actions,
4880                                                               attr,
4881                                                               error);
4882                         if (ret)
4883                                 return ret;
4884                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4885                         ++actions_n;
4886                         break;
4887                 case RTE_FLOW_ACTION_TYPE_FLAG:
4888                         ret = flow_dv_validate_action_flag(dev, action_flags,
4889                                                            attr, error);
4890                         if (ret < 0)
4891                                 return ret;
4892                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4893                                 /* Count all modify-header actions as one. */
4894                                 if (!(action_flags &
4895                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4896                                         ++actions_n;
4897                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4898                                                 MLX5_FLOW_ACTION_MARK_EXT;
4899                         } else {
4900                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4901                                 ++actions_n;
4902                         }
4903                         break;
4904                 case RTE_FLOW_ACTION_TYPE_MARK:
4905                         ret = flow_dv_validate_action_mark(dev, actions,
4906                                                            action_flags,
4907                                                            attr, error);
4908                         if (ret < 0)
4909                                 return ret;
4910                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4911                                 /* Count all modify-header actions as one. */
4912                                 if (!(action_flags &
4913                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4914                                         ++actions_n;
4915                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4916                                                 MLX5_FLOW_ACTION_MARK_EXT;
4917                         } else {
4918                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4919                                 ++actions_n;
4920                         }
4921                         break;
4922                 case RTE_FLOW_ACTION_TYPE_SET_META:
4923                         ret = flow_dv_validate_action_set_meta(dev, actions,
4924                                                                action_flags,
4925                                                                attr, error);
4926                         if (ret < 0)
4927                                 return ret;
4928                         /* Count all modify-header actions as one action. */
4929                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4930                                 ++actions_n;
4931                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4932                         break;
4933                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4934                         ret = flow_dv_validate_action_set_tag(dev, actions,
4935                                                               action_flags,
4936                                                               attr, error);
4937                         if (ret < 0)
4938                                 return ret;
4939                         /* Count all modify-header actions as one action. */
4940                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4941                                 ++actions_n;
4942                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4943                         break;
4944                 case RTE_FLOW_ACTION_TYPE_DROP:
4945                         ret = mlx5_flow_validate_action_drop(action_flags,
4946                                                              attr, error);
4947                         if (ret < 0)
4948                                 return ret;
4949                         action_flags |= MLX5_FLOW_ACTION_DROP;
4950                         ++actions_n;
4951                         break;
4952                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4953                         ret = mlx5_flow_validate_action_queue(actions,
4954                                                               action_flags, dev,
4955                                                               attr, error);
4956                         if (ret < 0)
4957                                 return ret;
4958                         queue_index = ((const struct rte_flow_action_queue *)
4959                                                         (actions->conf))->index;
4960                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4961                         ++actions_n;
4962                         break;
4963                 case RTE_FLOW_ACTION_TYPE_RSS:
4964                         rss = actions->conf;
4965                         ret = mlx5_flow_validate_action_rss(actions,
4966                                                             action_flags, dev,
4967                                                             attr, item_flags,
4968                                                             error);
4969                         if (ret < 0)
4970                                 return ret;
4971                         if (rss != NULL && rss->queue_num)
4972                                 queue_index = rss->queue[0];
4973                         action_flags |= MLX5_FLOW_ACTION_RSS;
4974                         ++actions_n;
4975                         break;
4976                 case RTE_FLOW_ACTION_TYPE_COUNT:
4977                         ret = flow_dv_validate_action_count(dev, error);
4978                         if (ret < 0)
4979                                 return ret;
4980                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4981                         ++actions_n;
4982                         break;
4983                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4984                         if (flow_dv_validate_action_pop_vlan(dev,
4985                                                              action_flags,
4986                                                              actions,
4987                                                              item_flags, attr,
4988                                                              error))
4989                                 return -rte_errno;
4990                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4991                         ++actions_n;
4992                         break;
4993                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4994                         ret = flow_dv_validate_action_push_vlan(dev,
4995                                                                 action_flags,
4996                                                                 vlan_m,
4997                                                                 actions, attr,
4998                                                                 error);
4999                         if (ret < 0)
5000                                 return ret;
5001                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5002                         ++actions_n;
5003                         break;
5004                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5005                         ret = flow_dv_validate_action_set_vlan_pcp
5006                                                 (action_flags, actions, error);
5007                         if (ret < 0)
5008                                 return ret;
5009                         /* Count PCP with push_vlan command. */
5010                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5011                         break;
5012                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5013                         ret = flow_dv_validate_action_set_vlan_vid
5014                                                 (item_flags, action_flags,
5015                                                  actions, error);
5016                         if (ret < 0)
5017                                 return ret;
5018                         /* Count VID with push_vlan command. */
5019                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5020                         break;
5021                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5022                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5023                         ret = flow_dv_validate_action_l2_encap(dev,
5024                                                                action_flags,
5025                                                                actions, attr,
5026                                                                error);
5027                         if (ret < 0)
5028                                 return ret;
5029                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5030                         ++actions_n;
5031                         break;
5032                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5033                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5034                         ret = flow_dv_validate_action_decap(dev, action_flags,
5035                                                             attr, error);
5036                         if (ret < 0)
5037                                 return ret;
5038                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5039                         ++actions_n;
5040                         break;
5041                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5042                         ret = flow_dv_validate_action_raw_encap_decap
5043                                 (dev, NULL, actions->conf, attr, &action_flags,
5044                                  &actions_n, error);
5045                         if (ret < 0)
5046                                 return ret;
5047                         break;
5048                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5049                         decap = actions->conf;
5050                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5051                                 ;
5052                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5053                                 encap = NULL;
5054                                 actions--;
5055                         } else {
5056                                 encap = actions->conf;
5057                         }
5058                         ret = flow_dv_validate_action_raw_encap_decap
5059                                            (dev,
5060                                             decap ? decap : &empty_decap, encap,
5061                                             attr, &action_flags, &actions_n,
5062                                             error);
5063                         if (ret < 0)
5064                                 return ret;
5065                         break;
5066                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5067                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5068                         ret = flow_dv_validate_action_modify_mac(action_flags,
5069                                                                  actions,
5070                                                                  item_flags,
5071                                                                  error);
5072                         if (ret < 0)
5073                                 return ret;
5074                         /* Count all modify-header actions as one action. */
5075                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5076                                 ++actions_n;
5077                         action_flags |= actions->type ==
5078                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5079                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5080                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5081                         break;
5082
5083                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5084                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5085                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5086                                                                   actions,
5087                                                                   item_flags,
5088                                                                   error);
5089                         if (ret < 0)
5090                                 return ret;
5091                         /* Count all modify-header actions as one action. */
5092                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5093                                 ++actions_n;
5094                         action_flags |= actions->type ==
5095                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5096                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5097                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5098                         break;
5099                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5100                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5101                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5102                                                                   actions,
5103                                                                   item_flags,
5104                                                                   error);
5105                         if (ret < 0)
5106                                 return ret;
5107                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5108                                 return rte_flow_error_set(error, ENOTSUP,
5109                                         RTE_FLOW_ERROR_TYPE_ACTION,
5110                                         actions,
5111                                         "Can't change header "
5112                                         "with ICMPv6 proto");
5113                         /* Count all modify-header actions as one action. */
5114                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5115                                 ++actions_n;
5116                         action_flags |= actions->type ==
5117                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5118                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5119                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5120                         break;
5121                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5122                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5123                         ret = flow_dv_validate_action_modify_tp(action_flags,
5124                                                                 actions,
5125                                                                 item_flags,
5126                                                                 error);
5127                         if (ret < 0)
5128                                 return ret;
5129                         /* Count all modify-header actions as one action. */
5130                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5131                                 ++actions_n;
5132                         action_flags |= actions->type ==
5133                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5134                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5135                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5136                         break;
5137                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5138                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5139                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5140                                                                  actions,
5141                                                                  item_flags,
5142                                                                  error);
5143                         if (ret < 0)
5144                                 return ret;
5145                         /* Count all modify-header actions as one action. */
5146                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5147                                 ++actions_n;
5148                         action_flags |= actions->type ==
5149                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5150                                                 MLX5_FLOW_ACTION_SET_TTL :
5151                                                 MLX5_FLOW_ACTION_DEC_TTL;
5152                         break;
5153                 case RTE_FLOW_ACTION_TYPE_JUMP:
5154                         ret = flow_dv_validate_action_jump(actions,
5155                                                            action_flags,
5156                                                            attr, external,
5157                                                            error);
5158                         if (ret)
5159                                 return ret;
5160                         ++actions_n;
5161                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5162                         break;
5163                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5164                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5165                         ret = flow_dv_validate_action_modify_tcp_seq
5166                                                                 (action_flags,
5167                                                                  actions,
5168                                                                  item_flags,
5169                                                                  error);
5170                         if (ret < 0)
5171                                 return ret;
5172                         /* Count all modify-header actions as one action. */
5173                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5174                                 ++actions_n;
5175                         action_flags |= actions->type ==
5176                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5177                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5178                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5179                         break;
5180                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5181                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5182                         ret = flow_dv_validate_action_modify_tcp_ack
5183                                                                 (action_flags,
5184                                                                  actions,
5185                                                                  item_flags,
5186                                                                  error);
5187                         if (ret < 0)
5188                                 return ret;
5189                         /* Count all modify-header actions as one action. */
5190                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5191                                 ++actions_n;
5192                         action_flags |= actions->type ==
5193                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5194                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5195                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5196                         break;
5197                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5198                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5199                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5200                         break;
5201                 case RTE_FLOW_ACTION_TYPE_METER:
5202                         ret = mlx5_flow_validate_action_meter(dev,
5203                                                               action_flags,
5204                                                               actions, attr,
5205                                                               error);
5206                         if (ret < 0)
5207                                 return ret;
5208                         action_flags |= MLX5_FLOW_ACTION_METER;
5209                         ++actions_n;
5210                         break;
5211                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5212                         ret = flow_dv_validate_action_modify_ipv4_dscp
5213                                                          (action_flags,
5214                                                           actions,
5215                                                           item_flags,
5216                                                           error);
5217                         if (ret < 0)
5218                                 return ret;
5219                         /* Count all modify-header actions as one action. */
5220                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5221                                 ++actions_n;
5222                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5223                         break;
5224                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5225                         ret = flow_dv_validate_action_modify_ipv6_dscp
5226                                                                 (action_flags,
5227                                                                  actions,
5228                                                                  item_flags,
5229                                                                  error);
5230                         if (ret < 0)
5231                                 return ret;
5232                         /* Count all modify-header actions as one action. */
5233                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5234                                 ++actions_n;
5235                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5236                         break;
5237                 default:
5238                         return rte_flow_error_set(error, ENOTSUP,
5239                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5240                                                   actions,
5241                                                   "action not supported");
5242                 }
5243         }
5244         /*
5245          * Validate the drop action mutual exclusion with other actions.
5246          * Drop action is mutually-exclusive with any other action, except for
5247          * Count action.
5248          */
5249         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5250             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5251                 return rte_flow_error_set(error, EINVAL,
5252                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5253                                           "Drop action is mutually-exclusive "
5254                                           "with any other action, except for "
5255                                           "Count action");
5256         /* Eswitch has few restrictions on using items and actions */
5257         if (attr->transfer) {
5258                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5259                     action_flags & MLX5_FLOW_ACTION_FLAG)
5260                         return rte_flow_error_set(error, ENOTSUP,
5261                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5262                                                   NULL,
5263                                                   "unsupported action FLAG");
5264                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5265                     action_flags & MLX5_FLOW_ACTION_MARK)
5266                         return rte_flow_error_set(error, ENOTSUP,
5267                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5268                                                   NULL,
5269                                                   "unsupported action MARK");
5270                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5271                         return rte_flow_error_set(error, ENOTSUP,
5272                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5273                                                   NULL,
5274                                                   "unsupported action QUEUE");
5275                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5276                         return rte_flow_error_set(error, ENOTSUP,
5277                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5278                                                   NULL,
5279                                                   "unsupported action RSS");
5280                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5281                         return rte_flow_error_set(error, EINVAL,
5282                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5283                                                   actions,
5284                                                   "no fate action is found");
5285         } else {
5286                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5287                         return rte_flow_error_set(error, EINVAL,
5288                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5289                                                   actions,
5290                                                   "no fate action is found");
5291         }
5292         /* Continue validation for Xcap actions.*/
5293         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5294             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5295                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5296                     MLX5_FLOW_XCAP_ACTIONS)
5297                         return rte_flow_error_set(error, ENOTSUP,
5298                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5299                                                   NULL, "encap and decap "
5300                                                   "combination aren't supported");
5301                 if (!attr->transfer && attr->ingress && (action_flags &
5302                                                         MLX5_FLOW_ACTION_ENCAP))
5303                         return rte_flow_error_set(error, ENOTSUP,
5304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5305                                                   NULL, "encap is not supported"
5306                                                   " for ingress traffic");
5307         }
5308         return 0;
5309 }
5310
5311 /**
5312  * Internal preparation function. Allocates the DV flow size,
5313  * this size is constant.
5314  *
5315  * @param[in] dev
5316  *   Pointer to the rte_eth_dev structure.
5317  * @param[in] attr
5318  *   Pointer to the flow attributes.
5319  * @param[in] items
5320  *   Pointer to the list of items.
5321  * @param[in] actions
5322  *   Pointer to the list of actions.
5323  * @param[out] error
5324  *   Pointer to the error structure.
5325  *
5326  * @return
5327  *   Pointer to mlx5_flow object on success,
5328  *   otherwise NULL and rte_errno is set.
5329  */
5330 static struct mlx5_flow *
5331 flow_dv_prepare(struct rte_eth_dev *dev,
5332                 const struct rte_flow_attr *attr __rte_unused,
5333                 const struct rte_flow_item items[] __rte_unused,
5334                 const struct rte_flow_action actions[] __rte_unused,
5335                 struct rte_flow_error *error)
5336 {
5337         uint32_t handle_idx = 0;
5338         struct mlx5_flow *dev_flow;
5339         struct mlx5_flow_handle *dev_handle;
5340         struct mlx5_priv *priv = dev->data->dev_private;
5341
5342         /* In case of corrupting the memory. */
5343         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5344                 rte_flow_error_set(error, ENOSPC,
5345                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5346                                    "not free temporary device flow");
5347                 return NULL;
5348         }
5349         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5350                                    &handle_idx);
5351         if (!dev_handle) {
5352                 rte_flow_error_set(error, ENOMEM,
5353                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5354                                    "not enough memory to create flow handle");
5355                 return NULL;
5356         }
5357         /* No multi-thread supporting. */
5358         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5359         dev_flow->handle = dev_handle;
5360         dev_flow->handle_idx = handle_idx;
5361         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5362         /*
5363          * The matching value needs to be cleared to 0 before using. In the
5364          * past, it will be automatically cleared when using rte_*alloc
5365          * API. The time consumption will be almost the same as before.
5366          */
5367         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5368         dev_flow->ingress = attr->ingress;
5369         dev_flow->dv.transfer = attr->transfer;
5370         return dev_flow;
5371 }
5372
5373 #ifdef RTE_LIBRTE_MLX5_DEBUG
5374 /**
5375  * Sanity check for match mask and value. Similar to check_valid_spec() in
5376  * kernel driver. If unmasked bit is present in value, it returns failure.
5377  *
5378  * @param match_mask
5379  *   pointer to match mask buffer.
5380  * @param match_value
5381  *   pointer to match value buffer.
5382  *
5383  * @return
5384  *   0 if valid, -EINVAL otherwise.
5385  */
5386 static int
5387 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5388 {
5389         uint8_t *m = match_mask;
5390         uint8_t *v = match_value;
5391         unsigned int i;
5392
5393         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5394                 if (v[i] & ~m[i]) {
5395                         DRV_LOG(ERR,
5396                                 "match_value differs from match_criteria"
5397                                 " %p[%u] != %p[%u]",
5398                                 match_value, i, match_mask, i);
5399                         return -EINVAL;
5400                 }
5401         }
5402         return 0;
5403 }
5404 #endif
5405
5406 /**
5407  * Add Ethernet item to matcher and to the value.
5408  *
5409  * @param[in, out] matcher
5410  *   Flow matcher.
5411  * @param[in, out] key
5412  *   Flow matcher value.
5413  * @param[in] item
5414  *   Flow pattern to translate.
5415  * @param[in] inner
5416  *   Item is inner pattern.
5417  */
5418 static void
5419 flow_dv_translate_item_eth(void *matcher, void *key,
5420                            const struct rte_flow_item *item, int inner)
5421 {
5422         const struct rte_flow_item_eth *eth_m = item->mask;
5423         const struct rte_flow_item_eth *eth_v = item->spec;
5424         const struct rte_flow_item_eth nic_mask = {
5425                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5426                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5427                 .type = RTE_BE16(0xffff),
5428         };
5429         void *headers_m;
5430         void *headers_v;
5431         char *l24_v;
5432         unsigned int i;
5433
5434         if (!eth_v)
5435                 return;
5436         if (!eth_m)
5437                 eth_m = &nic_mask;
5438         if (inner) {
5439                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5440                                          inner_headers);
5441                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5442         } else {
5443                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5444                                          outer_headers);
5445                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5446         }
5447         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5448                &eth_m->dst, sizeof(eth_m->dst));
5449         /* The value must be in the range of the mask. */
5450         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5451         for (i = 0; i < sizeof(eth_m->dst); ++i)
5452                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5453         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5454                &eth_m->src, sizeof(eth_m->src));
5455         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5456         /* The value must be in the range of the mask. */
5457         for (i = 0; i < sizeof(eth_m->dst); ++i)
5458                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5459         if (eth_v->type) {
5460                 /* When ethertype is present set mask for tagged VLAN. */
5461                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5462                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5463                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5464                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5465                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5466                                  1);
5467                         /* Return here to avoid setting match on ethertype. */
5468                         return;
5469                 }
5470         }
5471         /*
5472          * HW supports match on one Ethertype, the Ethertype following the last
5473          * VLAN tag of the packet (see PRM).
5474          * Set match on ethertype only if ETH header is not followed by VLAN.
5475          */
5476         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5477                  rte_be_to_cpu_16(eth_m->type));
5478         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5479         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5480 }
5481
5482 /**
5483  * Add VLAN item to matcher and to the value.
5484  *
5485  * @param[in, out] dev_flow
5486  *   Flow descriptor.
5487  * @param[in, out] matcher
5488  *   Flow matcher.
5489  * @param[in, out] key
5490  *   Flow matcher value.
5491  * @param[in] item
5492  *   Flow pattern to translate.
5493  * @param[in] inner
5494  *   Item is inner pattern.
5495  */
5496 static void
5497 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5498                             void *matcher, void *key,
5499                             const struct rte_flow_item *item,
5500                             int inner)
5501 {
5502         const struct rte_flow_item_vlan *vlan_m = item->mask;
5503         const struct rte_flow_item_vlan *vlan_v = item->spec;
5504         void *headers_m;
5505         void *headers_v;
5506         uint16_t tci_m;
5507         uint16_t tci_v;
5508
5509         if (!vlan_v)
5510                 return;
5511         if (!vlan_m)
5512                 vlan_m = &rte_flow_item_vlan_mask;
5513         if (inner) {
5514                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5515                                          inner_headers);
5516                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5517         } else {
5518                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5519                                          outer_headers);
5520                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5521                 /*
5522                  * This is workaround, masks are not supported,
5523                  * and pre-validated.
5524                  */
5525                 dev_flow->handle->vf_vlan.tag =
5526                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5527         }
5528         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5529         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5530         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5531         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5532         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5533         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5534         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5535         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5536         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5537         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5538         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5539                  rte_be_to_cpu_16(vlan_m->inner_type));
5540         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5541                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5542 }
5543
5544 /**
5545  * Add IPV4 item to matcher and to the value.
5546  *
5547  * @param[in, out] matcher
5548  *   Flow matcher.
5549  * @param[in, out] key
5550  *   Flow matcher value.
5551  * @param[in] item
5552  *   Flow pattern to translate.
5553  * @param[in] item_flags
5554  *   Bit-fields that holds the items detected until now.
5555  * @param[in] inner
5556  *   Item is inner pattern.
5557  * @param[in] group
5558  *   The group to insert the rule.
5559  */
5560 static void
5561 flow_dv_translate_item_ipv4(void *matcher, void *key,
5562                             const struct rte_flow_item *item,
5563                             const uint64_t item_flags,
5564                             int inner, uint32_t group)
5565 {
5566         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5567         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5568         const struct rte_flow_item_ipv4 nic_mask = {
5569                 .hdr = {
5570                         .src_addr = RTE_BE32(0xffffffff),
5571                         .dst_addr = RTE_BE32(0xffffffff),
5572                         .type_of_service = 0xff,
5573                         .next_proto_id = 0xff,
5574                         .time_to_live = 0xff,
5575                 },
5576         };
5577         void *headers_m;
5578         void *headers_v;
5579         char *l24_m;
5580         char *l24_v;
5581         uint8_t tos;
5582
5583         if (inner) {
5584                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5585                                          inner_headers);
5586                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5587         } else {
5588                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5589                                          outer_headers);
5590                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5591         }
5592         if (group == 0)
5593                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5594         else
5595                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5596         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5597         /*
5598          * On outer header (which must contains L2), or inner header with L2,
5599          * set cvlan_tag mask bit to mark this packet as untagged.
5600          * This should be done even if item->spec is empty.
5601          */
5602         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5603                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5604         if (!ipv4_v)
5605                 return;
5606         if (!ipv4_m)
5607                 ipv4_m = &nic_mask;
5608         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5609                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5610         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5611                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5612         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5613         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5614         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5615                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5616         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5617                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5618         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5619         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5620         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5621         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5622                  ipv4_m->hdr.type_of_service);
5623         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5624         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5625                  ipv4_m->hdr.type_of_service >> 2);
5626         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5627         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5628                  ipv4_m->hdr.next_proto_id);
5629         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5630                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5631         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5632                  ipv4_m->hdr.time_to_live);
5633         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5634                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5635 }
5636
5637 /**
5638  * Add IPV6 item to matcher and to the value.
5639  *
5640  * @param[in, out] matcher
5641  *   Flow matcher.
5642  * @param[in, out] key
5643  *   Flow matcher value.
5644  * @param[in] item
5645  *   Flow pattern to translate.
5646  * @param[in] item_flags
5647  *   Bit-fields that holds the items detected until now.
5648  * @param[in] inner
5649  *   Item is inner pattern.
5650  * @param[in] group
5651  *   The group to insert the rule.
5652  */
5653 static void
5654 flow_dv_translate_item_ipv6(void *matcher, void *key,
5655                             const struct rte_flow_item *item,
5656                             const uint64_t item_flags,
5657                             int inner, uint32_t group)
5658 {
5659         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5660         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5661         const struct rte_flow_item_ipv6 nic_mask = {
5662                 .hdr = {
5663                         .src_addr =
5664                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5665                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5666                         .dst_addr =
5667                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5668                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5669                         .vtc_flow = RTE_BE32(0xffffffff),
5670                         .proto = 0xff,
5671                         .hop_limits = 0xff,
5672                 },
5673         };
5674         void *headers_m;
5675         void *headers_v;
5676         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5677         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5678         char *l24_m;
5679         char *l24_v;
5680         uint32_t vtc_m;
5681         uint32_t vtc_v;
5682         int i;
5683         int size;
5684
5685         if (inner) {
5686                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5687                                          inner_headers);
5688                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5689         } else {
5690                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5691                                          outer_headers);
5692                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5693         }
5694         if (group == 0)
5695                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5696         else
5697                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5698         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5699         /*
5700          * On outer header (which must contains L2), or inner header with L2,
5701          * set cvlan_tag mask bit to mark this packet as untagged.
5702          * This should be done even if item->spec is empty.
5703          */
5704         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5705                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5706         if (!ipv6_v)
5707                 return;
5708         if (!ipv6_m)
5709                 ipv6_m = &nic_mask;
5710         size = sizeof(ipv6_m->hdr.dst_addr);
5711         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5712                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5713         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5714                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5715         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5716         for (i = 0; i < size; ++i)
5717                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5718         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5719                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5720         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5721                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5722         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5723         for (i = 0; i < size; ++i)
5724                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5725         /* TOS. */
5726         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5727         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5728         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5729         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5731         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5732         /* Label. */
5733         if (inner) {
5734                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5735                          vtc_m);
5736                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5737                          vtc_v);
5738         } else {
5739                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5740                          vtc_m);
5741                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5742                          vtc_v);
5743         }
5744         /* Protocol. */
5745         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5746                  ipv6_m->hdr.proto);
5747         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5748                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5749         /* Hop limit. */
5750         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5751                  ipv6_m->hdr.hop_limits);
5752         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5753                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5754 }
5755
5756 /**
5757  * Add TCP item to matcher and to the value.
5758  *
5759  * @param[in, out] matcher
5760  *   Flow matcher.
5761  * @param[in, out] key
5762  *   Flow matcher value.
5763  * @param[in] item
5764  *   Flow pattern to translate.
5765  * @param[in] inner
5766  *   Item is inner pattern.
5767  */
5768 static void
5769 flow_dv_translate_item_tcp(void *matcher, void *key,
5770                            const struct rte_flow_item *item,
5771                            int inner)
5772 {
5773         const struct rte_flow_item_tcp *tcp_m = item->mask;
5774         const struct rte_flow_item_tcp *tcp_v = item->spec;
5775         void *headers_m;
5776         void *headers_v;
5777
5778         if (inner) {
5779                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5780                                          inner_headers);
5781                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5782         } else {
5783                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5784                                          outer_headers);
5785                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5786         }
5787         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5788         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5789         if (!tcp_v)
5790                 return;
5791         if (!tcp_m)
5792                 tcp_m = &rte_flow_item_tcp_mask;
5793         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5794                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5795         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5796                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5797         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5798                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5799         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5800                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5801         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5802                  tcp_m->hdr.tcp_flags);
5803         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5804                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5805 }
5806
5807 /**
5808  * Add UDP item to matcher and to the value.
5809  *
5810  * @param[in, out] matcher
5811  *   Flow matcher.
5812  * @param[in, out] key
5813  *   Flow matcher value.
5814  * @param[in] item
5815  *   Flow pattern to translate.
5816  * @param[in] inner
5817  *   Item is inner pattern.
5818  */
5819 static void
5820 flow_dv_translate_item_udp(void *matcher, void *key,
5821                            const struct rte_flow_item *item,
5822                            int inner)
5823 {
5824         const struct rte_flow_item_udp *udp_m = item->mask;
5825         const struct rte_flow_item_udp *udp_v = item->spec;
5826         void *headers_m;
5827         void *headers_v;
5828
5829         if (inner) {
5830                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5831                                          inner_headers);
5832                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5833         } else {
5834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5835                                          outer_headers);
5836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5837         }
5838         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5839         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5840         if (!udp_v)
5841                 return;
5842         if (!udp_m)
5843                 udp_m = &rte_flow_item_udp_mask;
5844         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5845                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5846         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5847                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5848         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5849                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5850         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5851                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5852 }
5853
5854 /**
5855  * Add GRE optional Key item to matcher and to the value.
5856  *
5857  * @param[in, out] matcher
5858  *   Flow matcher.
5859  * @param[in, out] key
5860  *   Flow matcher value.
5861  * @param[in] item
5862  *   Flow pattern to translate.
5863  * @param[in] inner
5864  *   Item is inner pattern.
5865  */
5866 static void
5867 flow_dv_translate_item_gre_key(void *matcher, void *key,
5868                                    const struct rte_flow_item *item)
5869 {
5870         const rte_be32_t *key_m = item->mask;
5871         const rte_be32_t *key_v = item->spec;
5872         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5873         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5874         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5875
5876         /* GRE K bit must be on and should already be validated */
5877         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5878         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5879         if (!key_v)
5880                 return;
5881         if (!key_m)
5882                 key_m = &gre_key_default_mask;
5883         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5884                  rte_be_to_cpu_32(*key_m) >> 8);
5885         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5886                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5887         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5888                  rte_be_to_cpu_32(*key_m) & 0xFF);
5889         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5890                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5891 }
5892
5893 /**
5894  * Add GRE item to matcher and to the value.
5895  *
5896  * @param[in, out] matcher
5897  *   Flow matcher.
5898  * @param[in, out] key
5899  *   Flow matcher value.
5900  * @param[in] item
5901  *   Flow pattern to translate.
5902  * @param[in] inner
5903  *   Item is inner pattern.
5904  */
5905 static void
5906 flow_dv_translate_item_gre(void *matcher, void *key,
5907                            const struct rte_flow_item *item,
5908                            int inner)
5909 {
5910         const struct rte_flow_item_gre *gre_m = item->mask;
5911         const struct rte_flow_item_gre *gre_v = item->spec;
5912         void *headers_m;
5913         void *headers_v;
5914         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5915         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5916         struct {
5917                 union {
5918                         __extension__
5919                         struct {
5920                                 uint16_t version:3;
5921                                 uint16_t rsvd0:9;
5922                                 uint16_t s_present:1;
5923                                 uint16_t k_present:1;
5924                                 uint16_t rsvd_bit1:1;
5925                                 uint16_t c_present:1;
5926                         };
5927                         uint16_t value;
5928                 };
5929         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5930
5931         if (inner) {
5932                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5933                                          inner_headers);
5934                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5935         } else {
5936                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5937                                          outer_headers);
5938                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5939         }
5940         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5941         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5942         if (!gre_v)
5943                 return;
5944         if (!gre_m)
5945                 gre_m = &rte_flow_item_gre_mask;
5946         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5947                  rte_be_to_cpu_16(gre_m->protocol));
5948         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5949                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5950         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5951         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5952         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5953                  gre_crks_rsvd0_ver_m.c_present);
5954         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5955                  gre_crks_rsvd0_ver_v.c_present &
5956                  gre_crks_rsvd0_ver_m.c_present);
5957         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5958                  gre_crks_rsvd0_ver_m.k_present);
5959         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5960                  gre_crks_rsvd0_ver_v.k_present &
5961                  gre_crks_rsvd0_ver_m.k_present);
5962         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5963                  gre_crks_rsvd0_ver_m.s_present);
5964         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5965                  gre_crks_rsvd0_ver_v.s_present &
5966                  gre_crks_rsvd0_ver_m.s_present);
5967 }
5968
5969 /**
5970  * Add NVGRE item to matcher and to the value.
5971  *
5972  * @param[in, out] matcher
5973  *   Flow matcher.
5974  * @param[in, out] key
5975  *   Flow matcher value.
5976  * @param[in] item
5977  *   Flow pattern to translate.
5978  * @param[in] inner
5979  *   Item is inner pattern.
5980  */
5981 static void
5982 flow_dv_translate_item_nvgre(void *matcher, void *key,
5983                              const struct rte_flow_item *item,
5984                              int inner)
5985 {
5986         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5987         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5988         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5989         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5990         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5991         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5992         char *gre_key_m;
5993         char *gre_key_v;
5994         int size;
5995         int i;
5996
5997         /* For NVGRE, GRE header fields must be set with defined values. */
5998         const struct rte_flow_item_gre gre_spec = {
5999                 .c_rsvd0_ver = RTE_BE16(0x2000),
6000                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6001         };
6002         const struct rte_flow_item_gre gre_mask = {
6003                 .c_rsvd0_ver = RTE_BE16(0xB000),
6004                 .protocol = RTE_BE16(UINT16_MAX),
6005         };
6006         const struct rte_flow_item gre_item = {
6007                 .spec = &gre_spec,
6008                 .mask = &gre_mask,
6009                 .last = NULL,
6010         };
6011         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6012         if (!nvgre_v)
6013                 return;
6014         if (!nvgre_m)
6015                 nvgre_m = &rte_flow_item_nvgre_mask;
6016         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6017         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6018         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6019         memcpy(gre_key_m, tni_flow_id_m, size);
6020         for (i = 0; i < size; ++i)
6021                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6022 }
6023
6024 /**
6025  * Add VXLAN item to matcher and to the value.
6026  *
6027  * @param[in, out] matcher
6028  *   Flow matcher.
6029  * @param[in, out] key
6030  *   Flow matcher value.
6031  * @param[in] item
6032  *   Flow pattern to translate.
6033  * @param[in] inner
6034  *   Item is inner pattern.
6035  */
6036 static void
6037 flow_dv_translate_item_vxlan(void *matcher, void *key,
6038                              const struct rte_flow_item *item,
6039                              int inner)
6040 {
6041         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6042         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6043         void *headers_m;
6044         void *headers_v;
6045         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6046         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6047         char *vni_m;
6048         char *vni_v;
6049         uint16_t dport;
6050         int size;
6051         int i;
6052
6053         if (inner) {
6054                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6055                                          inner_headers);
6056                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6057         } else {
6058                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6059                                          outer_headers);
6060                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6061         }
6062         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6063                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6064         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6065                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6066                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6067         }
6068         if (!vxlan_v)
6069                 return;
6070         if (!vxlan_m)
6071                 vxlan_m = &rte_flow_item_vxlan_mask;
6072         size = sizeof(vxlan_m->vni);
6073         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6074         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6075         memcpy(vni_m, vxlan_m->vni, size);
6076         for (i = 0; i < size; ++i)
6077                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6078 }
6079
6080 /**
6081  * Add VXLAN-GPE item to matcher and to the value.
6082  *
6083  * @param[in, out] matcher
6084  *   Flow matcher.
6085  * @param[in, out] key
6086  *   Flow matcher value.
6087  * @param[in] item
6088  *   Flow pattern to translate.
6089  * @param[in] inner
6090  *   Item is inner pattern.
6091  */
6092
6093 static void
6094 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6095                                  const struct rte_flow_item *item, int inner)
6096 {
6097         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6098         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6099         void *headers_m;
6100         void *headers_v;
6101         void *misc_m =
6102                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6103         void *misc_v =
6104                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6105         char *vni_m;
6106         char *vni_v;
6107         uint16_t dport;
6108         int size;
6109         int i;
6110         uint8_t flags_m = 0xff;
6111         uint8_t flags_v = 0xc;
6112
6113         if (inner) {
6114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6115                                          inner_headers);
6116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6117         } else {
6118                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6119                                          outer_headers);
6120                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6121         }
6122         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6123                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6124         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6125                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6126                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6127         }
6128         if (!vxlan_v)
6129                 return;
6130         if (!vxlan_m)
6131                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6132         size = sizeof(vxlan_m->vni);
6133         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6134         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6135         memcpy(vni_m, vxlan_m->vni, size);
6136         for (i = 0; i < size; ++i)
6137                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6138         if (vxlan_m->flags) {
6139                 flags_m = vxlan_m->flags;
6140                 flags_v = vxlan_v->flags;
6141         }
6142         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6143         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6144         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6145                  vxlan_m->protocol);
6146         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6147                  vxlan_v->protocol);
6148 }
6149
6150 /**
6151  * Add Geneve item to matcher and to the value.
6152  *
6153  * @param[in, out] matcher
6154  *   Flow matcher.
6155  * @param[in, out] key
6156  *   Flow matcher value.
6157  * @param[in] item
6158  *   Flow pattern to translate.
6159  * @param[in] inner
6160  *   Item is inner pattern.
6161  */
6162
6163 static void
6164 flow_dv_translate_item_geneve(void *matcher, void *key,
6165                               const struct rte_flow_item *item, int inner)
6166 {
6167         const struct rte_flow_item_geneve *geneve_m = item->mask;
6168         const struct rte_flow_item_geneve *geneve_v = item->spec;
6169         void *headers_m;
6170         void *headers_v;
6171         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6172         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6173         uint16_t dport;
6174         uint16_t gbhdr_m;
6175         uint16_t gbhdr_v;
6176         char *vni_m;
6177         char *vni_v;
6178         size_t size, i;
6179
6180         if (inner) {
6181                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6182                                          inner_headers);
6183                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6184         } else {
6185                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6186                                          outer_headers);
6187                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6188         }
6189         dport = MLX5_UDP_PORT_GENEVE;
6190         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6191                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6192                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6193         }
6194         if (!geneve_v)
6195                 return;
6196         if (!geneve_m)
6197                 geneve_m = &rte_flow_item_geneve_mask;
6198         size = sizeof(geneve_m->vni);
6199         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6200         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6201         memcpy(vni_m, geneve_m->vni, size);
6202         for (i = 0; i < size; ++i)
6203                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6204         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6205                  rte_be_to_cpu_16(geneve_m->protocol));
6206         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6207                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6208         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6209         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6210         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6211                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6212         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6213                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6214         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6215                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6216         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6217                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6218                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6219 }
6220
6221 /**
6222  * Add MPLS item to matcher and to the value.
6223  *
6224  * @param[in, out] matcher
6225  *   Flow matcher.
6226  * @param[in, out] key
6227  *   Flow matcher value.
6228  * @param[in] item
6229  *   Flow pattern to translate.
6230  * @param[in] prev_layer
6231  *   The protocol layer indicated in previous item.
6232  * @param[in] inner
6233  *   Item is inner pattern.
6234  */
6235 static void
6236 flow_dv_translate_item_mpls(void *matcher, void *key,
6237                             const struct rte_flow_item *item,
6238                             uint64_t prev_layer,
6239                             int inner)
6240 {
6241         const uint32_t *in_mpls_m = item->mask;
6242         const uint32_t *in_mpls_v = item->spec;
6243         uint32_t *out_mpls_m = 0;
6244         uint32_t *out_mpls_v = 0;
6245         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6246         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6247         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6248                                      misc_parameters_2);
6249         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6250         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6251         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6252
6253         switch (prev_layer) {
6254         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6255                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6256                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6257                          MLX5_UDP_PORT_MPLS);
6258                 break;
6259         case MLX5_FLOW_LAYER_GRE:
6260                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6261                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6262                          RTE_ETHER_TYPE_MPLS);
6263                 break;
6264         default:
6265                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6266                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6267                          IPPROTO_MPLS);
6268                 break;
6269         }
6270         if (!in_mpls_v)
6271                 return;
6272         if (!in_mpls_m)
6273                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6274         switch (prev_layer) {
6275         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6276                 out_mpls_m =
6277                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6278                                                  outer_first_mpls_over_udp);
6279                 out_mpls_v =
6280                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6281                                                  outer_first_mpls_over_udp);
6282                 break;
6283         case MLX5_FLOW_LAYER_GRE:
6284                 out_mpls_m =
6285                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6286                                                  outer_first_mpls_over_gre);
6287                 out_mpls_v =
6288                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6289                                                  outer_first_mpls_over_gre);
6290                 break;
6291         default:
6292                 /* Inner MPLS not over GRE is not supported. */
6293                 if (!inner) {
6294                         out_mpls_m =
6295                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6296                                                          misc2_m,
6297                                                          outer_first_mpls);
6298                         out_mpls_v =
6299                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6300                                                          misc2_v,
6301                                                          outer_first_mpls);
6302                 }
6303                 break;
6304         }
6305         if (out_mpls_m && out_mpls_v) {
6306                 *out_mpls_m = *in_mpls_m;
6307                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6308         }
6309 }
6310
6311 /**
6312  * Add metadata register item to matcher
6313  *
6314  * @param[in, out] matcher
6315  *   Flow matcher.
6316  * @param[in, out] key
6317  *   Flow matcher value.
6318  * @param[in] reg_type
6319  *   Type of device metadata register
6320  * @param[in] value
6321  *   Register value
6322  * @param[in] mask
6323  *   Register mask
6324  */
6325 static void
6326 flow_dv_match_meta_reg(void *matcher, void *key,
6327                        enum modify_reg reg_type,
6328                        uint32_t data, uint32_t mask)
6329 {
6330         void *misc2_m =
6331                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6332         void *misc2_v =
6333                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6334         uint32_t temp;
6335
6336         data &= mask;
6337         switch (reg_type) {
6338         case REG_A:
6339                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6340                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6341                 break;
6342         case REG_B:
6343                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6344                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6345                 break;
6346         case REG_C_0:
6347                 /*
6348                  * The metadata register C0 field might be divided into
6349                  * source vport index and META item value, we should set
6350                  * this field according to specified mask, not as whole one.
6351                  */
6352                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6353                 temp |= mask;
6354                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6355                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6356                 temp &= ~mask;
6357                 temp |= data;
6358                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6359                 break;
6360         case REG_C_1:
6361                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6362                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6363                 break;
6364         case REG_C_2:
6365                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6366                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6367                 break;
6368         case REG_C_3:
6369                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6370                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6371                 break;
6372         case REG_C_4:
6373                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6374                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6375                 break;
6376         case REG_C_5:
6377                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6378                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6379                 break;
6380         case REG_C_6:
6381                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6382                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6383                 break;
6384         case REG_C_7:
6385                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6386                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6387                 break;
6388         default:
6389                 MLX5_ASSERT(false);
6390                 break;
6391         }
6392 }
6393
6394 /**
6395  * Add MARK item to matcher
6396  *
6397  * @param[in] dev
6398  *   The device to configure through.
6399  * @param[in, out] matcher
6400  *   Flow matcher.
6401  * @param[in, out] key
6402  *   Flow matcher value.
6403  * @param[in] item
6404  *   Flow pattern to translate.
6405  */
6406 static void
6407 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6408                             void *matcher, void *key,
6409                             const struct rte_flow_item *item)
6410 {
6411         struct mlx5_priv *priv = dev->data->dev_private;
6412         const struct rte_flow_item_mark *mark;
6413         uint32_t value;
6414         uint32_t mask;
6415
6416         mark = item->mask ? (const void *)item->mask :
6417                             &rte_flow_item_mark_mask;
6418         mask = mark->id & priv->sh->dv_mark_mask;
6419         mark = (const void *)item->spec;
6420         MLX5_ASSERT(mark);
6421         value = mark->id & priv->sh->dv_mark_mask & mask;
6422         if (mask) {
6423                 enum modify_reg reg;
6424
6425                 /* Get the metadata register index for the mark. */
6426                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6427                 MLX5_ASSERT(reg > 0);
6428                 if (reg == REG_C_0) {
6429                         struct mlx5_priv *priv = dev->data->dev_private;
6430                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6431                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6432
6433                         mask &= msk_c0;
6434                         mask <<= shl_c0;
6435                         value <<= shl_c0;
6436                 }
6437                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6438         }
6439 }
6440
6441 /**
6442  * Add META item to matcher
6443  *
6444  * @param[in] dev
6445  *   The devich to configure through.
6446  * @param[in, out] matcher
6447  *   Flow matcher.
6448  * @param[in, out] key
6449  *   Flow matcher value.
6450  * @param[in] attr
6451  *   Attributes of flow that includes this item.
6452  * @param[in] item
6453  *   Flow pattern to translate.
6454  */
6455 static void
6456 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6457                             void *matcher, void *key,
6458                             const struct rte_flow_attr *attr,
6459                             const struct rte_flow_item *item)
6460 {
6461         const struct rte_flow_item_meta *meta_m;
6462         const struct rte_flow_item_meta *meta_v;
6463
6464         meta_m = (const void *)item->mask;
6465         if (!meta_m)
6466                 meta_m = &rte_flow_item_meta_mask;
6467         meta_v = (const void *)item->spec;
6468         if (meta_v) {
6469                 int reg;
6470                 uint32_t value = meta_v->data;
6471                 uint32_t mask = meta_m->data;
6472
6473                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6474                 if (reg < 0)
6475                         return;
6476                 /*
6477                  * In datapath code there is no endianness
6478                  * coversions for perfromance reasons, all
6479                  * pattern conversions are done in rte_flow.
6480                  */
6481                 value = rte_cpu_to_be_32(value);
6482                 mask = rte_cpu_to_be_32(mask);
6483                 if (reg == REG_C_0) {
6484                         struct mlx5_priv *priv = dev->data->dev_private;
6485                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6486                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6487 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6488                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6489
6490                         value >>= shr_c0;
6491                         mask >>= shr_c0;
6492 #endif
6493                         value <<= shl_c0;
6494                         mask <<= shl_c0;
6495                         MLX5_ASSERT(msk_c0);
6496                         MLX5_ASSERT(!(~msk_c0 & mask));
6497                 }
6498                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6499         }
6500 }
6501
6502 /**
6503  * Add vport metadata Reg C0 item to matcher
6504  *
6505  * @param[in, out] matcher
6506  *   Flow matcher.
6507  * @param[in, out] key
6508  *   Flow matcher value.
6509  * @param[in] reg
6510  *   Flow pattern to translate.
6511  */
6512 static void
6513 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6514                                   uint32_t value, uint32_t mask)
6515 {
6516         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6517 }
6518
6519 /**
6520  * Add tag item to matcher
6521  *
6522  * @param[in] dev
6523  *   The devich to configure through.
6524  * @param[in, out] matcher
6525  *   Flow matcher.
6526  * @param[in, out] key
6527  *   Flow matcher value.
6528  * @param[in] item
6529  *   Flow pattern to translate.
6530  */
6531 static void
6532 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6533                                 void *matcher, void *key,
6534                                 const struct rte_flow_item *item)
6535 {
6536         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6537         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6538         uint32_t mask, value;
6539
6540         MLX5_ASSERT(tag_v);
6541         value = tag_v->data;
6542         mask = tag_m ? tag_m->data : UINT32_MAX;
6543         if (tag_v->id == REG_C_0) {
6544                 struct mlx5_priv *priv = dev->data->dev_private;
6545                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6546                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6547
6548                 mask &= msk_c0;
6549                 mask <<= shl_c0;
6550                 value <<= shl_c0;
6551         }
6552         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6553 }
6554
6555 /**
6556  * Add TAG item to matcher
6557  *
6558  * @param[in] dev
6559  *   The devich to configure through.
6560  * @param[in, out] matcher
6561  *   Flow matcher.
6562  * @param[in, out] key
6563  *   Flow matcher value.
6564  * @param[in] item
6565  *   Flow pattern to translate.
6566  */
6567 static void
6568 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6569                            void *matcher, void *key,
6570                            const struct rte_flow_item *item)
6571 {
6572         const struct rte_flow_item_tag *tag_v = item->spec;
6573         const struct rte_flow_item_tag *tag_m = item->mask;
6574         enum modify_reg reg;
6575
6576         MLX5_ASSERT(tag_v);
6577         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6578         /* Get the metadata register index for the tag. */
6579         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6580         MLX5_ASSERT(reg > 0);
6581         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6582 }
6583
6584 /**
6585  * Add source vport match to the specified matcher.
6586  *
6587  * @param[in, out] matcher
6588  *   Flow matcher.
6589  * @param[in, out] key
6590  *   Flow matcher value.
6591  * @param[in] port
6592  *   Source vport value to match
6593  * @param[in] mask
6594  *   Mask
6595  */
6596 static void
6597 flow_dv_translate_item_source_vport(void *matcher, void *key,
6598                                     int16_t port, uint16_t mask)
6599 {
6600         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6601         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6602
6603         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6604         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6605 }
6606
6607 /**
6608  * Translate port-id item to eswitch match on  port-id.
6609  *
6610  * @param[in] dev
6611  *   The devich to configure through.
6612  * @param[in, out] matcher
6613  *   Flow matcher.
6614  * @param[in, out] key
6615  *   Flow matcher value.
6616  * @param[in] item
6617  *   Flow pattern to translate.
6618  *
6619  * @return
6620  *   0 on success, a negative errno value otherwise.
6621  */
6622 static int
6623 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6624                                void *key, const struct rte_flow_item *item)
6625 {
6626         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6627         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6628         struct mlx5_priv *priv;
6629         uint16_t mask, id;
6630
6631         mask = pid_m ? pid_m->id : 0xffff;
6632         id = pid_v ? pid_v->id : dev->data->port_id;
6633         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6634         if (!priv)
6635                 return -rte_errno;
6636         /* Translate to vport field or to metadata, depending on mode. */
6637         if (priv->vport_meta_mask)
6638                 flow_dv_translate_item_meta_vport(matcher, key,
6639                                                   priv->vport_meta_tag,
6640                                                   priv->vport_meta_mask);
6641         else
6642                 flow_dv_translate_item_source_vport(matcher, key,
6643                                                     priv->vport_id, mask);
6644         return 0;
6645 }
6646
6647 /**
6648  * Add ICMP6 item to matcher and to the value.
6649  *
6650  * @param[in, out] matcher
6651  *   Flow matcher.
6652  * @param[in, out] key
6653  *   Flow matcher value.
6654  * @param[in] item
6655  *   Flow pattern to translate.
6656  * @param[in] inner
6657  *   Item is inner pattern.
6658  */
6659 static void
6660 flow_dv_translate_item_icmp6(void *matcher, void *key,
6661                               const struct rte_flow_item *item,
6662                               int inner)
6663 {
6664         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6665         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6666         void *headers_m;
6667         void *headers_v;
6668         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6669                                      misc_parameters_3);
6670         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6671         if (inner) {
6672                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6673                                          inner_headers);
6674                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6675         } else {
6676                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6677                                          outer_headers);
6678                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6679         }
6680         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6681         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6682         if (!icmp6_v)
6683                 return;
6684         if (!icmp6_m)
6685                 icmp6_m = &rte_flow_item_icmp6_mask;
6686         /*
6687          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6688          * If only the protocol is specified, no need to match the frag.
6689          */
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6691         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6692         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6693         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6694                  icmp6_v->type & icmp6_m->type);
6695         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6696         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6697                  icmp6_v->code & icmp6_m->code);
6698 }
6699
6700 /**
6701  * Add ICMP item to matcher and to the value.
6702  *
6703  * @param[in, out] matcher
6704  *   Flow matcher.
6705  * @param[in, out] key
6706  *   Flow matcher value.
6707  * @param[in] item
6708  *   Flow pattern to translate.
6709  * @param[in] inner
6710  *   Item is inner pattern.
6711  */
6712 static void
6713 flow_dv_translate_item_icmp(void *matcher, void *key,
6714                             const struct rte_flow_item *item,
6715                             int inner)
6716 {
6717         const struct rte_flow_item_icmp *icmp_m = item->mask;
6718         const struct rte_flow_item_icmp *icmp_v = item->spec;
6719         void *headers_m;
6720         void *headers_v;
6721         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6722                                      misc_parameters_3);
6723         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6724         if (inner) {
6725                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6726                                          inner_headers);
6727                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6728         } else {
6729                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6730                                          outer_headers);
6731                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6732         }
6733         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6734         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6735         if (!icmp_v)
6736                 return;
6737         if (!icmp_m)
6738                 icmp_m = &rte_flow_item_icmp_mask;
6739         /*
6740          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6741          * If only the protocol is specified, no need to match the frag.
6742          */
6743         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6744         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6745         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6746                  icmp_m->hdr.icmp_type);
6747         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6748                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6749         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6750                  icmp_m->hdr.icmp_code);
6751         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6752                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6753 }
6754
6755 /**
6756  * Add GTP item to matcher and to the value.
6757  *
6758  * @param[in, out] matcher
6759  *   Flow matcher.
6760  * @param[in, out] key
6761  *   Flow matcher value.
6762  * @param[in] item
6763  *   Flow pattern to translate.
6764  * @param[in] inner
6765  *   Item is inner pattern.
6766  */
6767 static void
6768 flow_dv_translate_item_gtp(void *matcher, void *key,
6769                            const struct rte_flow_item *item, int inner)
6770 {
6771         const struct rte_flow_item_gtp *gtp_m = item->mask;
6772         const struct rte_flow_item_gtp *gtp_v = item->spec;
6773         void *headers_m;
6774         void *headers_v;
6775         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6776                                      misc_parameters_3);
6777         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6778         uint16_t dport = RTE_GTPU_UDP_PORT;
6779
6780         if (inner) {
6781                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6782                                          inner_headers);
6783                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6784         } else {
6785                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6786                                          outer_headers);
6787                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6788         }
6789         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6790                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6791                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6792         }
6793         if (!gtp_v)
6794                 return;
6795         if (!gtp_m)
6796                 gtp_m = &rte_flow_item_gtp_mask;
6797         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6798         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6799                  gtp_v->msg_type & gtp_m->msg_type);
6800         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6801                  rte_be_to_cpu_32(gtp_m->teid));
6802         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6803                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6804 }
6805
6806 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6807
6808 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6809         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6810                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6811
6812 /**
6813  * Calculate flow matcher enable bitmap.
6814  *
6815  * @param match_criteria
6816  *   Pointer to flow matcher criteria.
6817  *
6818  * @return
6819  *   Bitmap of enabled fields.
6820  */
6821 static uint8_t
6822 flow_dv_matcher_enable(uint32_t *match_criteria)
6823 {
6824         uint8_t match_criteria_enable;
6825
6826         match_criteria_enable =
6827                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6828                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6829         match_criteria_enable |=
6830                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6831                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6832         match_criteria_enable |=
6833                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6834                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6835         match_criteria_enable |=
6836                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6837                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6838         match_criteria_enable |=
6839                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6840                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6841         return match_criteria_enable;
6842 }
6843
6844
6845 /**
6846  * Get a flow table.
6847  *
6848  * @param[in, out] dev
6849  *   Pointer to rte_eth_dev structure.
6850  * @param[in] table_id
6851  *   Table id to use.
6852  * @param[in] egress
6853  *   Direction of the table.
6854  * @param[in] transfer
6855  *   E-Switch or NIC flow.
6856  * @param[out] error
6857  *   pointer to error structure.
6858  *
6859  * @return
6860  *   Returns tables resource based on the index, NULL in case of failed.
6861  */
6862 static struct mlx5_flow_tbl_resource *
6863 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6864                          uint32_t table_id, uint8_t egress,
6865                          uint8_t transfer,
6866                          struct rte_flow_error *error)
6867 {
6868         struct mlx5_priv *priv = dev->data->dev_private;
6869         struct mlx5_ibv_shared *sh = priv->sh;
6870         struct mlx5_flow_tbl_resource *tbl;
6871         union mlx5_flow_tbl_key table_key = {
6872                 {
6873                         .table_id = table_id,
6874                         .reserved = 0,
6875                         .domain = !!transfer,
6876                         .direction = !!egress,
6877                 }
6878         };
6879         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6880                                                          table_key.v64);
6881         struct mlx5_flow_tbl_data_entry *tbl_data;
6882         uint32_t idx = 0;
6883         int ret;
6884         void *domain;
6885
6886         if (pos) {
6887                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6888                                         entry);
6889                 tbl = &tbl_data->tbl;
6890                 rte_atomic32_inc(&tbl->refcnt);
6891                 return tbl;
6892         }
6893         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
6894         if (!tbl_data) {
6895                 rte_flow_error_set(error, ENOMEM,
6896                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6897                                    NULL,
6898                                    "cannot allocate flow table data entry");
6899                 return NULL;
6900         }
6901         tbl_data->idx = idx;
6902         tbl = &tbl_data->tbl;
6903         pos = &tbl_data->entry;
6904         if (transfer)
6905                 domain = sh->fdb_domain;
6906         else if (egress)
6907                 domain = sh->tx_domain;
6908         else
6909                 domain = sh->rx_domain;
6910         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6911         if (!tbl->obj) {
6912                 rte_flow_error_set(error, ENOMEM,
6913                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6914                                    NULL, "cannot create flow table object");
6915                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6916                 return NULL;
6917         }
6918         /*
6919          * No multi-threads now, but still better to initialize the reference
6920          * count before insert it into the hash list.
6921          */
6922         rte_atomic32_init(&tbl->refcnt);
6923         /* Jump action reference count is initialized here. */
6924         rte_atomic32_init(&tbl_data->jump.refcnt);
6925         pos->key = table_key.v64;
6926         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6927         if (ret < 0) {
6928                 rte_flow_error_set(error, -ret,
6929                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6930                                    "cannot insert flow table data entry");
6931                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6932                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6933         }
6934         rte_atomic32_inc(&tbl->refcnt);
6935         return tbl;
6936 }
6937
6938 /**
6939  * Release a flow table.
6940  *
6941  * @param[in] dev
6942  *   Pointer to rte_eth_dev structure.
6943  * @param[in] tbl
6944  *   Table resource to be released.
6945  *
6946  * @return
6947  *   Returns 0 if table was released, else return 1;
6948  */
6949 static int
6950 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6951                              struct mlx5_flow_tbl_resource *tbl)
6952 {
6953         struct mlx5_priv *priv = dev->data->dev_private;
6954         struct mlx5_ibv_shared *sh = priv->sh;
6955         struct mlx5_flow_tbl_data_entry *tbl_data =
6956                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6957
6958         if (!tbl)
6959                 return 0;
6960         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6961                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6962
6963                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6964                 tbl->obj = NULL;
6965                 /* remove the entry from the hash list and free memory. */
6966                 mlx5_hlist_remove(sh->flow_tbls, pos);
6967                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
6968                                 tbl_data->idx);
6969                 return 0;
6970         }
6971         return 1;
6972 }
6973
6974 /**
6975  * Register the flow matcher.
6976  *
6977  * @param[in, out] dev
6978  *   Pointer to rte_eth_dev structure.
6979  * @param[in, out] matcher
6980  *   Pointer to flow matcher.
6981  * @param[in, out] key
6982  *   Pointer to flow table key.
6983  * @parm[in, out] dev_flow
6984  *   Pointer to the dev_flow.
6985  * @param[out] error
6986  *   pointer to error structure.
6987  *
6988  * @return
6989  *   0 on success otherwise -errno and errno is set.
6990  */
6991 static int
6992 flow_dv_matcher_register(struct rte_eth_dev *dev,
6993                          struct mlx5_flow_dv_matcher *matcher,
6994                          union mlx5_flow_tbl_key *key,
6995                          struct mlx5_flow *dev_flow,
6996                          struct rte_flow_error *error)
6997 {
6998         struct mlx5_priv *priv = dev->data->dev_private;
6999         struct mlx5_ibv_shared *sh = priv->sh;
7000         struct mlx5_flow_dv_matcher *cache_matcher;
7001         struct mlx5dv_flow_matcher_attr dv_attr = {
7002                 .type = IBV_FLOW_ATTR_NORMAL,
7003                 .match_mask = (void *)&matcher->mask,
7004         };
7005         struct mlx5_flow_tbl_resource *tbl;
7006         struct mlx5_flow_tbl_data_entry *tbl_data;
7007
7008         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7009                                        key->domain, error);
7010         if (!tbl)
7011                 return -rte_errno;      /* No need to refill the error info */
7012         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7013         /* Lookup from cache. */
7014         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7015                 if (matcher->crc == cache_matcher->crc &&
7016                     matcher->priority == cache_matcher->priority &&
7017                     !memcmp((const void *)matcher->mask.buf,
7018                             (const void *)cache_matcher->mask.buf,
7019                             cache_matcher->mask.size)) {
7020                         DRV_LOG(DEBUG,
7021                                 "%s group %u priority %hd use %s "
7022                                 "matcher %p: refcnt %d++",
7023                                 key->domain ? "FDB" : "NIC", key->table_id,
7024                                 cache_matcher->priority,
7025                                 key->direction ? "tx" : "rx",
7026                                 (void *)cache_matcher,
7027                                 rte_atomic32_read(&cache_matcher->refcnt));
7028                         rte_atomic32_inc(&cache_matcher->refcnt);
7029                         dev_flow->handle->dvh.matcher = cache_matcher;
7030                         /* old matcher should not make the table ref++. */
7031                         flow_dv_tbl_resource_release(dev, tbl);
7032                         return 0;
7033                 }
7034         }
7035         /* Register new matcher. */
7036         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7037         if (!cache_matcher) {
7038                 flow_dv_tbl_resource_release(dev, tbl);
7039                 return rte_flow_error_set(error, ENOMEM,
7040                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7041                                           "cannot allocate matcher memory");
7042         }
7043         *cache_matcher = *matcher;
7044         dv_attr.match_criteria_enable =
7045                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7046         dv_attr.priority = matcher->priority;
7047         if (key->direction)
7048                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7049         cache_matcher->matcher_object =
7050                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7051         if (!cache_matcher->matcher_object) {
7052                 rte_free(cache_matcher);
7053 #ifdef HAVE_MLX5DV_DR
7054                 flow_dv_tbl_resource_release(dev, tbl);
7055 #endif
7056                 return rte_flow_error_set(error, ENOMEM,
7057                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7058                                           NULL, "cannot create matcher");
7059         }
7060         /* Save the table information */
7061         cache_matcher->tbl = tbl;
7062         rte_atomic32_init(&cache_matcher->refcnt);
7063         /* only matcher ref++, table ref++ already done above in get API. */
7064         rte_atomic32_inc(&cache_matcher->refcnt);
7065         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7066         dev_flow->handle->dvh.matcher = cache_matcher;
7067         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7068                 key->domain ? "FDB" : "NIC", key->table_id,
7069                 cache_matcher->priority,
7070                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7071                 rte_atomic32_read(&cache_matcher->refcnt));
7072         return 0;
7073 }
7074
7075 /**
7076  * Find existing tag resource or create and register a new one.
7077  *
7078  * @param dev[in, out]
7079  *   Pointer to rte_eth_dev structure.
7080  * @param[in, out] tag_be24
7081  *   Tag value in big endian then R-shift 8.
7082  * @parm[in, out] dev_flow
7083  *   Pointer to the dev_flow.
7084  * @param[out] error
7085  *   pointer to error structure.
7086  *
7087  * @return
7088  *   0 on success otherwise -errno and errno is set.
7089  */
7090 static int
7091 flow_dv_tag_resource_register
7092                         (struct rte_eth_dev *dev,
7093                          uint32_t tag_be24,
7094                          struct mlx5_flow *dev_flow,
7095                          struct rte_flow_error *error)
7096 {
7097         struct mlx5_priv *priv = dev->data->dev_private;
7098         struct mlx5_ibv_shared *sh = priv->sh;
7099         struct mlx5_flow_dv_tag_resource *cache_resource;
7100         struct mlx5_hlist_entry *entry;
7101
7102         /* Lookup a matching resource from cache. */
7103         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7104         if (entry) {
7105                 cache_resource = container_of
7106                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7107                 rte_atomic32_inc(&cache_resource->refcnt);
7108                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7109                 dev_flow->dv.tag_resource = cache_resource;
7110                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7111                         (void *)cache_resource,
7112                         rte_atomic32_read(&cache_resource->refcnt));
7113                 return 0;
7114         }
7115         /* Register new resource. */
7116         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7117                                        &dev_flow->handle->dvh.rix_tag);
7118         if (!cache_resource)
7119                 return rte_flow_error_set(error, ENOMEM,
7120                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7121                                           "cannot allocate resource memory");
7122         cache_resource->entry.key = (uint64_t)tag_be24;
7123         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7124         if (!cache_resource->action) {
7125                 rte_free(cache_resource);
7126                 return rte_flow_error_set(error, ENOMEM,
7127                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7128                                           NULL, "cannot create action");
7129         }
7130         rte_atomic32_init(&cache_resource->refcnt);
7131         rte_atomic32_inc(&cache_resource->refcnt);
7132         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7133                 mlx5_glue->destroy_flow_action(cache_resource->action);
7134                 rte_free(cache_resource);
7135                 return rte_flow_error_set(error, EEXIST,
7136                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7137                                           NULL, "cannot insert tag");
7138         }
7139         dev_flow->dv.tag_resource = cache_resource;
7140         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7141                 (void *)cache_resource,
7142                 rte_atomic32_read(&cache_resource->refcnt));
7143         return 0;
7144 }
7145
7146 /**
7147  * Release the tag.
7148  *
7149  * @param dev
7150  *   Pointer to Ethernet device.
7151  * @param tag_idx
7152  *   Tag index.
7153  *
7154  * @return
7155  *   1 while a reference on it exists, 0 when freed.
7156  */
7157 static int
7158 flow_dv_tag_release(struct rte_eth_dev *dev,
7159                     uint32_t tag_idx)
7160 {
7161         struct mlx5_priv *priv = dev->data->dev_private;
7162         struct mlx5_ibv_shared *sh = priv->sh;
7163         struct mlx5_flow_dv_tag_resource *tag;
7164
7165         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7166         if (!tag)
7167                 return 0;
7168         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7169                 dev->data->port_id, (void *)tag,
7170                 rte_atomic32_read(&tag->refcnt));
7171         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7172                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7173                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7174                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7175                         dev->data->port_id, (void *)tag);
7176                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7177                 return 0;
7178         }
7179         return 1;
7180 }
7181
7182 /**
7183  * Translate port ID action to vport.
7184  *
7185  * @param[in] dev
7186  *   Pointer to rte_eth_dev structure.
7187  * @param[in] action
7188  *   Pointer to the port ID action.
7189  * @param[out] dst_port_id
7190  *   The target port ID.
7191  * @param[out] error
7192  *   Pointer to the error structure.
7193  *
7194  * @return
7195  *   0 on success, a negative errno value otherwise and rte_errno is set.
7196  */
7197 static int
7198 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7199                                  const struct rte_flow_action *action,
7200                                  uint32_t *dst_port_id,
7201                                  struct rte_flow_error *error)
7202 {
7203         uint32_t port;
7204         struct mlx5_priv *priv;
7205         const struct rte_flow_action_port_id *conf =
7206                         (const struct rte_flow_action_port_id *)action->conf;
7207
7208         port = conf->original ? dev->data->port_id : conf->id;
7209         priv = mlx5_port_to_eswitch_info(port, false);
7210         if (!priv)
7211                 return rte_flow_error_set(error, -rte_errno,
7212                                           RTE_FLOW_ERROR_TYPE_ACTION,
7213                                           NULL,
7214                                           "No eswitch info was found for port");
7215 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7216         /*
7217          * This parameter is transferred to
7218          * mlx5dv_dr_action_create_dest_ib_port().
7219          */
7220         *dst_port_id = priv->ibv_port;
7221 #else
7222         /*
7223          * Legacy mode, no LAG configurations is supported.
7224          * This parameter is transferred to
7225          * mlx5dv_dr_action_create_dest_vport().
7226          */
7227         *dst_port_id = priv->vport_id;
7228 #endif
7229         return 0;
7230 }
7231
7232 /**
7233  * Add Tx queue matcher
7234  *
7235  * @param[in] dev
7236  *   Pointer to the dev struct.
7237  * @param[in, out] matcher
7238  *   Flow matcher.
7239  * @param[in, out] key
7240  *   Flow matcher value.
7241  * @param[in] item
7242  *   Flow pattern to translate.
7243  * @param[in] inner
7244  *   Item is inner pattern.
7245  */
7246 static void
7247 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7248                                 void *matcher, void *key,
7249                                 const struct rte_flow_item *item)
7250 {
7251         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7252         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7253         void *misc_m =
7254                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7255         void *misc_v =
7256                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7257         struct mlx5_txq_ctrl *txq;
7258         uint32_t queue;
7259
7260
7261         queue_m = (const void *)item->mask;
7262         if (!queue_m)
7263                 return;
7264         queue_v = (const void *)item->spec;
7265         if (!queue_v)
7266                 return;
7267         txq = mlx5_txq_get(dev, queue_v->queue);
7268         if (!txq)
7269                 return;
7270         queue = txq->obj->sq->id;
7271         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7272         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7273                  queue & queue_m->queue);
7274         mlx5_txq_release(dev, queue_v->queue);
7275 }
7276
7277 /**
7278  * Set the hash fields according to the @p flow information.
7279  *
7280  * @param[in] dev_flow
7281  *   Pointer to the mlx5_flow.
7282  * @param[in] rss_desc
7283  *   Pointer to the mlx5_flow_rss_desc.
7284  */
7285 static void
7286 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7287                        struct mlx5_flow_rss_desc *rss_desc)
7288 {
7289         uint64_t items = dev_flow->handle->layers;
7290         int rss_inner = 0;
7291         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7292
7293         dev_flow->hash_fields = 0;
7294 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7295         if (rss_desc->level >= 2) {
7296                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7297                 rss_inner = 1;
7298         }
7299 #endif
7300         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7301             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7302                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7303                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7304                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7305                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7306                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7307                         else
7308                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7309                 }
7310         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7311                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7312                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7313                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7314                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7315                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7316                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7317                         else
7318                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7319                 }
7320         }
7321         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7322             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7323                 if (rss_types & ETH_RSS_UDP) {
7324                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7325                                 dev_flow->hash_fields |=
7326                                                 IBV_RX_HASH_SRC_PORT_UDP;
7327                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7328                                 dev_flow->hash_fields |=
7329                                                 IBV_RX_HASH_DST_PORT_UDP;
7330                         else
7331                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7332                 }
7333         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7334                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7335                 if (rss_types & ETH_RSS_TCP) {
7336                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7337                                 dev_flow->hash_fields |=
7338                                                 IBV_RX_HASH_SRC_PORT_TCP;
7339                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7340                                 dev_flow->hash_fields |=
7341                                                 IBV_RX_HASH_DST_PORT_TCP;
7342                         else
7343                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7344                 }
7345         }
7346 }
7347
7348 /**
7349  * Fill the flow with DV spec, lock free
7350  * (mutex should be acquired by caller).
7351  *
7352  * @param[in] dev
7353  *   Pointer to rte_eth_dev structure.
7354  * @param[in, out] dev_flow
7355  *   Pointer to the sub flow.
7356  * @param[in] attr
7357  *   Pointer to the flow attributes.
7358  * @param[in] items
7359  *   Pointer to the list of items.
7360  * @param[in] actions
7361  *   Pointer to the list of actions.
7362  * @param[out] error
7363  *   Pointer to the error structure.
7364  *
7365  * @return
7366  *   0 on success, a negative errno value otherwise and rte_errno is set.
7367  */
7368 static int
7369 __flow_dv_translate(struct rte_eth_dev *dev,
7370                     struct mlx5_flow *dev_flow,
7371                     const struct rte_flow_attr *attr,
7372                     const struct rte_flow_item items[],
7373                     const struct rte_flow_action actions[],
7374                     struct rte_flow_error *error)
7375 {
7376         struct mlx5_priv *priv = dev->data->dev_private;
7377         struct mlx5_dev_config *dev_conf = &priv->config;
7378         struct rte_flow *flow = dev_flow->flow;
7379         struct mlx5_flow_handle *handle = dev_flow->handle;
7380         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7381                                               priv->rss_desc)
7382                                               [!!priv->flow_nested_idx];
7383         uint64_t item_flags = 0;
7384         uint64_t last_item = 0;
7385         uint64_t action_flags = 0;
7386         uint64_t priority = attr->priority;
7387         struct mlx5_flow_dv_matcher matcher = {
7388                 .mask = {
7389                         .size = sizeof(matcher.mask.buf),
7390                 },
7391         };
7392         int actions_n = 0;
7393         bool actions_end = false;
7394         union {
7395                 struct mlx5_flow_dv_modify_hdr_resource res;
7396                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7397                             sizeof(struct mlx5_modification_cmd) *
7398                             (MLX5_MAX_MODIFY_NUM + 1)];
7399         } mhdr_dummy;
7400         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7401         union flow_dv_attr flow_attr = { .attr = 0 };
7402         uint32_t tag_be;
7403         union mlx5_flow_tbl_key tbl_key;
7404         uint32_t modify_action_position = UINT32_MAX;
7405         void *match_mask = matcher.mask.buf;
7406         void *match_value = dev_flow->dv.value.buf;
7407         uint8_t next_protocol = 0xff;
7408         struct rte_vlan_hdr vlan = { 0 };
7409         uint32_t table;
7410         int ret = 0;
7411
7412         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7413                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7414         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7415                                        !!priv->fdb_def_rule, &table, error);
7416         if (ret)
7417                 return ret;
7418         dev_flow->dv.group = table;
7419         if (attr->transfer)
7420                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7421         if (priority == MLX5_FLOW_PRIO_RSVD)
7422                 priority = dev_conf->flow_prio - 1;
7423         /* number of actions must be set to 0 in case of dirty stack. */
7424         mhdr_res->actions_num = 0;
7425         for (; !actions_end ; actions++) {
7426                 const struct rte_flow_action_queue *queue;
7427                 const struct rte_flow_action_rss *rss;
7428                 const struct rte_flow_action *action = actions;
7429                 const struct rte_flow_action_count *count = action->conf;
7430                 const uint8_t *rss_key;
7431                 const struct rte_flow_action_jump *jump_data;
7432                 const struct rte_flow_action_meter *mtr;
7433                 struct mlx5_flow_tbl_resource *tbl;
7434                 uint32_t port_id = 0;
7435                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7436                 int action_type = actions->type;
7437                 const struct rte_flow_action *found_action = NULL;
7438                 struct mlx5_flow_meter *fm = NULL;
7439
7440                 switch (action_type) {
7441                 case RTE_FLOW_ACTION_TYPE_VOID:
7442                         break;
7443                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7444                         if (flow_dv_translate_action_port_id(dev, action,
7445                                                              &port_id, error))
7446                                 return -rte_errno;
7447                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7448                         port_id_resource.port_id = port_id;
7449                         if (flow_dv_port_id_action_resource_register
7450                             (dev, &port_id_resource, dev_flow, error))
7451                                 return -rte_errno;
7452                         MLX5_ASSERT(!handle->rix_port_id_action);
7453                         dev_flow->dv.actions[actions_n++] =
7454                                         dev_flow->dv.port_id_action->action;
7455                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7456                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7457                         break;
7458                 case RTE_FLOW_ACTION_TYPE_FLAG:
7459                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7460                         dev_flow->handle->mark = 1;
7461                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7462                                 struct rte_flow_action_mark mark = {
7463                                         .id = MLX5_FLOW_MARK_DEFAULT,
7464                                 };
7465
7466                                 if (flow_dv_convert_action_mark(dev, &mark,
7467                                                                 mhdr_res,
7468                                                                 error))
7469                                         return -rte_errno;
7470                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7471                                 break;
7472                         }
7473                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7474                         /*
7475                          * Only one FLAG or MARK is supported per device flow
7476                          * right now. So the pointer to the tag resource must be
7477                          * zero before the register process.
7478                          */
7479                         MLX5_ASSERT(!handle->dvh.rix_tag);
7480                         if (flow_dv_tag_resource_register(dev, tag_be,
7481                                                           dev_flow, error))
7482                                 return -rte_errno;
7483                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7484                         dev_flow->dv.actions[actions_n++] =
7485                                         dev_flow->dv.tag_resource->action;
7486                         break;
7487                 case RTE_FLOW_ACTION_TYPE_MARK:
7488                         action_flags |= MLX5_FLOW_ACTION_MARK;
7489                         dev_flow->handle->mark = 1;
7490                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7491                                 const struct rte_flow_action_mark *mark =
7492                                         (const struct rte_flow_action_mark *)
7493                                                 actions->conf;
7494
7495                                 if (flow_dv_convert_action_mark(dev, mark,
7496                                                                 mhdr_res,
7497                                                                 error))
7498                                         return -rte_errno;
7499                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7500                                 break;
7501                         }
7502                         /* Fall-through */
7503                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7504                         /* Legacy (non-extensive) MARK action. */
7505                         tag_be = mlx5_flow_mark_set
7506                               (((const struct rte_flow_action_mark *)
7507                                (actions->conf))->id);
7508                         MLX5_ASSERT(!handle->dvh.rix_tag);
7509                         if (flow_dv_tag_resource_register(dev, tag_be,
7510                                                           dev_flow, error))
7511                                 return -rte_errno;
7512                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7513                         dev_flow->dv.actions[actions_n++] =
7514                                         dev_flow->dv.tag_resource->action;
7515                         break;
7516                 case RTE_FLOW_ACTION_TYPE_SET_META:
7517                         if (flow_dv_convert_action_set_meta
7518                                 (dev, mhdr_res, attr,
7519                                  (const struct rte_flow_action_set_meta *)
7520                                   actions->conf, error))
7521                                 return -rte_errno;
7522                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7523                         break;
7524                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7525                         if (flow_dv_convert_action_set_tag
7526                                 (dev, mhdr_res,
7527                                  (const struct rte_flow_action_set_tag *)
7528                                   actions->conf, error))
7529                                 return -rte_errno;
7530                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7531                         break;
7532                 case RTE_FLOW_ACTION_TYPE_DROP:
7533                         action_flags |= MLX5_FLOW_ACTION_DROP;
7534                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7535                         break;
7536                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7537                         queue = actions->conf;
7538                         rss_desc->queue_num = 1;
7539                         rss_desc->queue[0] = queue->index;
7540                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7541                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7542                         break;
7543                 case RTE_FLOW_ACTION_TYPE_RSS:
7544                         rss = actions->conf;
7545                         memcpy(rss_desc->queue, rss->queue,
7546                                rss->queue_num * sizeof(uint16_t));
7547                         rss_desc->queue_num = rss->queue_num;
7548                         /* NULL RSS key indicates default RSS key. */
7549                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7550                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7551                         /*
7552                          * rss->level and rss.types should be set in advance
7553                          * when expanding items for RSS.
7554                          */
7555                         action_flags |= MLX5_FLOW_ACTION_RSS;
7556                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7557                         break;
7558                 case RTE_FLOW_ACTION_TYPE_COUNT:
7559                         if (!dev_conf->devx) {
7560                                 rte_errno = ENOTSUP;
7561                                 goto cnt_err;
7562                         }
7563                         flow->counter = flow_dv_counter_alloc(dev,
7564                                                         count->shared,
7565                                                         count->id,
7566                                                         dev_flow->dv.group);
7567                         if (!flow->counter)
7568                                 goto cnt_err;
7569                         dev_flow->dv.actions[actions_n++] =
7570                                   (flow_dv_counter_get_by_idx(dev,
7571                                   flow->counter, NULL))->action;
7572                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7573                         break;
7574 cnt_err:
7575                         if (rte_errno == ENOTSUP)
7576                                 return rte_flow_error_set
7577                                               (error, ENOTSUP,
7578                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7579                                                NULL,
7580                                                "count action not supported");
7581                         else
7582                                 return rte_flow_error_set
7583                                                 (error, rte_errno,
7584                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7585                                                  action,
7586                                                  "cannot create counter"
7587                                                   " object.");
7588                         break;
7589                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7590                         dev_flow->dv.actions[actions_n++] =
7591                                                 priv->sh->pop_vlan_action;
7592                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7593                         break;
7594                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7595                         if (!(action_flags &
7596                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7597                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7598                         vlan.eth_proto = rte_be_to_cpu_16
7599                              ((((const struct rte_flow_action_of_push_vlan *)
7600                                                    actions->conf)->ethertype));
7601                         found_action = mlx5_flow_find_action
7602                                         (actions + 1,
7603                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7604                         if (found_action)
7605                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7606                         found_action = mlx5_flow_find_action
7607                                         (actions + 1,
7608                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7609                         if (found_action)
7610                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7611                         if (flow_dv_create_action_push_vlan
7612                                             (dev, attr, &vlan, dev_flow, error))
7613                                 return -rte_errno;
7614                         dev_flow->dv.actions[actions_n++] =
7615                                         dev_flow->dv.push_vlan_res->action;
7616                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7617                         break;
7618                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7619                         /* of_vlan_push action handled this action */
7620                         MLX5_ASSERT(action_flags &
7621                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7622                         break;
7623                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7624                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7625                                 break;
7626                         flow_dev_get_vlan_info_from_items(items, &vlan);
7627                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7628                         /* If no VLAN push - this is a modify header action */
7629                         if (flow_dv_convert_action_modify_vlan_vid
7630                                                 (mhdr_res, actions, error))
7631                                 return -rte_errno;
7632                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7633                         break;
7634                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7635                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7636                         if (flow_dv_create_action_l2_encap(dev, actions,
7637                                                            dev_flow,
7638                                                            attr->transfer,
7639                                                            error))
7640                                 return -rte_errno;
7641                         dev_flow->dv.actions[actions_n++] =
7642                                         dev_flow->dv.encap_decap->verbs_action;
7643                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7644                         break;
7645                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7646                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7647                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7648                                                            attr->transfer,
7649                                                            error))
7650                                 return -rte_errno;
7651                         dev_flow->dv.actions[actions_n++] =
7652                                         dev_flow->dv.encap_decap->verbs_action;
7653                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7654                         break;
7655                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7656                         /* Handle encap with preceding decap. */
7657                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7658                                 if (flow_dv_create_action_raw_encap
7659                                         (dev, actions, dev_flow, attr, error))
7660                                         return -rte_errno;
7661                                 dev_flow->dv.actions[actions_n++] =
7662                                         dev_flow->dv.encap_decap->verbs_action;
7663                         } else {
7664                                 /* Handle encap without preceding decap. */
7665                                 if (flow_dv_create_action_l2_encap
7666                                     (dev, actions, dev_flow, attr->transfer,
7667                                      error))
7668                                         return -rte_errno;
7669                                 dev_flow->dv.actions[actions_n++] =
7670                                         dev_flow->dv.encap_decap->verbs_action;
7671                         }
7672                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7673                         break;
7674                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7675                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7676                                 ;
7677                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7678                                 if (flow_dv_create_action_l2_decap
7679                                     (dev, dev_flow, attr->transfer, error))
7680                                         return -rte_errno;
7681                                 dev_flow->dv.actions[actions_n++] =
7682                                         dev_flow->dv.encap_decap->verbs_action;
7683                         }
7684                         /* If decap is followed by encap, handle it at encap. */
7685                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7686                         break;
7687                 case RTE_FLOW_ACTION_TYPE_JUMP:
7688                         jump_data = action->conf;
7689                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7690                                                        jump_data->group,
7691                                                        !!priv->fdb_def_rule,
7692                                                        &table, error);
7693                         if (ret)
7694                                 return ret;
7695                         tbl = flow_dv_tbl_resource_get(dev, table,
7696                                                        attr->egress,
7697                                                        attr->transfer, error);
7698                         if (!tbl)
7699                                 return rte_flow_error_set
7700                                                 (error, errno,
7701                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7702                                                  NULL,
7703                                                  "cannot create jump action.");
7704                         if (flow_dv_jump_tbl_resource_register
7705                             (dev, tbl, dev_flow, error)) {
7706                                 flow_dv_tbl_resource_release(dev, tbl);
7707                                 return rte_flow_error_set
7708                                                 (error, errno,
7709                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7710                                                  NULL,
7711                                                  "cannot create jump action.");
7712                         }
7713                         dev_flow->dv.actions[actions_n++] =
7714                                         dev_flow->dv.jump->action;
7715                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7716                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
7717                         break;
7718                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7719                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7720                         if (flow_dv_convert_action_modify_mac
7721                                         (mhdr_res, actions, error))
7722                                 return -rte_errno;
7723                         action_flags |= actions->type ==
7724                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7725                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7726                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7727                         break;
7728                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7729                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7730                         if (flow_dv_convert_action_modify_ipv4
7731                                         (mhdr_res, actions, error))
7732                                 return -rte_errno;
7733                         action_flags |= actions->type ==
7734                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7735                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7736                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7737                         break;
7738                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7739                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7740                         if (flow_dv_convert_action_modify_ipv6
7741                                         (mhdr_res, actions, error))
7742                                 return -rte_errno;
7743                         action_flags |= actions->type ==
7744                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7745                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7746                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7747                         break;
7748                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7749                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7750                         if (flow_dv_convert_action_modify_tp
7751                                         (mhdr_res, actions, items,
7752                                          &flow_attr, dev_flow, !!(action_flags &
7753                                          MLX5_FLOW_ACTION_DECAP), error))
7754                                 return -rte_errno;
7755                         action_flags |= actions->type ==
7756                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7757                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7758                                         MLX5_FLOW_ACTION_SET_TP_DST;
7759                         break;
7760                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7761                         if (flow_dv_convert_action_modify_dec_ttl
7762                                         (mhdr_res, items, &flow_attr, dev_flow,
7763                                          !!(action_flags &
7764                                          MLX5_FLOW_ACTION_DECAP), error))
7765                                 return -rte_errno;
7766                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7767                         break;
7768                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7769                         if (flow_dv_convert_action_modify_ttl
7770                                         (mhdr_res, actions, items, &flow_attr,
7771                                          dev_flow, !!(action_flags &
7772                                          MLX5_FLOW_ACTION_DECAP), error))
7773                                 return -rte_errno;
7774                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7775                         break;
7776                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7777                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7778                         if (flow_dv_convert_action_modify_tcp_seq
7779                                         (mhdr_res, actions, error))
7780                                 return -rte_errno;
7781                         action_flags |= actions->type ==
7782                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7783                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7784                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7785                         break;
7786
7787                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7788                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7789                         if (flow_dv_convert_action_modify_tcp_ack
7790                                         (mhdr_res, actions, error))
7791                                 return -rte_errno;
7792                         action_flags |= actions->type ==
7793                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7794                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7795                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7796                         break;
7797                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7798                         if (flow_dv_convert_action_set_reg
7799                                         (mhdr_res, actions, error))
7800                                 return -rte_errno;
7801                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7802                         break;
7803                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7804                         if (flow_dv_convert_action_copy_mreg
7805                                         (dev, mhdr_res, actions, error))
7806                                 return -rte_errno;
7807                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7808                         break;
7809                 case RTE_FLOW_ACTION_TYPE_METER:
7810                         mtr = actions->conf;
7811                         if (!flow->meter) {
7812                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
7813                                                             attr, error);
7814                                 if (!fm)
7815                                         return rte_flow_error_set(error,
7816                                                 rte_errno,
7817                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7818                                                 NULL,
7819                                                 "meter not found "
7820                                                 "or invalid parameters");
7821                                 flow->meter = fm->meter_id;
7822                         }
7823                         /* Set the meter action. */
7824                         if (!fm) {
7825                                 fm = mlx5_flow_meter_find(priv, flow->meter);
7826                                 if (!fm)
7827                                         return rte_flow_error_set(error,
7828                                                 rte_errno,
7829                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7830                                                 NULL,
7831                                                 "meter not found "
7832                                                 "or invalid parameters");
7833                         }
7834                         dev_flow->dv.actions[actions_n++] =
7835                                 fm->mfts->meter_action;
7836                         action_flags |= MLX5_FLOW_ACTION_METER;
7837                         break;
7838                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7839                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7840                                                               actions, error))
7841                                 return -rte_errno;
7842                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7843                         break;
7844                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7845                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7846                                                               actions, error))
7847                                 return -rte_errno;
7848                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7849                         break;
7850                 case RTE_FLOW_ACTION_TYPE_END:
7851                         actions_end = true;
7852                         if (mhdr_res->actions_num) {
7853                                 /* create modify action if needed. */
7854                                 if (flow_dv_modify_hdr_resource_register
7855                                         (dev, mhdr_res, dev_flow, error))
7856                                         return -rte_errno;
7857                                 dev_flow->dv.actions[modify_action_position] =
7858                                         handle->dvh.modify_hdr->verbs_action;
7859                         }
7860                         break;
7861                 default:
7862                         break;
7863                 }
7864                 if (mhdr_res->actions_num &&
7865                     modify_action_position == UINT32_MAX)
7866                         modify_action_position = actions_n++;
7867         }
7868         dev_flow->dv.actions_n = actions_n;
7869         dev_flow->act_flags = action_flags;
7870         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7871                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7872                 int item_type = items->type;
7873
7874                 switch (item_type) {
7875                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7876                         flow_dv_translate_item_port_id(dev, match_mask,
7877                                                        match_value, items);
7878                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7879                         break;
7880                 case RTE_FLOW_ITEM_TYPE_ETH:
7881                         flow_dv_translate_item_eth(match_mask, match_value,
7882                                                    items, tunnel);
7883                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7884                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7885                                              MLX5_FLOW_LAYER_OUTER_L2;
7886                         break;
7887                 case RTE_FLOW_ITEM_TYPE_VLAN:
7888                         flow_dv_translate_item_vlan(dev_flow,
7889                                                     match_mask, match_value,
7890                                                     items, tunnel);
7891                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7892                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7893                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7894                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7895                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7896                         break;
7897                 case RTE_FLOW_ITEM_TYPE_IPV4:
7898                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7899                                                   &item_flags, &tunnel);
7900                         flow_dv_translate_item_ipv4(match_mask, match_value,
7901                                                     items, item_flags, tunnel,
7902                                                     dev_flow->dv.group);
7903                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7904                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7905                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7906                         if (items->mask != NULL &&
7907                             ((const struct rte_flow_item_ipv4 *)
7908                              items->mask)->hdr.next_proto_id) {
7909                                 next_protocol =
7910                                         ((const struct rte_flow_item_ipv4 *)
7911                                          (items->spec))->hdr.next_proto_id;
7912                                 next_protocol &=
7913                                         ((const struct rte_flow_item_ipv4 *)
7914                                          (items->mask))->hdr.next_proto_id;
7915                         } else {
7916                                 /* Reset for inner layer. */
7917                                 next_protocol = 0xff;
7918                         }
7919                         break;
7920                 case RTE_FLOW_ITEM_TYPE_IPV6:
7921                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7922                                                   &item_flags, &tunnel);
7923                         flow_dv_translate_item_ipv6(match_mask, match_value,
7924                                                     items, item_flags, tunnel,
7925                                                     dev_flow->dv.group);
7926                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7927                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7928                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7929                         if (items->mask != NULL &&
7930                             ((const struct rte_flow_item_ipv6 *)
7931                              items->mask)->hdr.proto) {
7932                                 next_protocol =
7933                                         ((const struct rte_flow_item_ipv6 *)
7934                                          items->spec)->hdr.proto;
7935                                 next_protocol &=
7936                                         ((const struct rte_flow_item_ipv6 *)
7937                                          items->mask)->hdr.proto;
7938                         } else {
7939                                 /* Reset for inner layer. */
7940                                 next_protocol = 0xff;
7941                         }
7942                         break;
7943                 case RTE_FLOW_ITEM_TYPE_TCP:
7944                         flow_dv_translate_item_tcp(match_mask, match_value,
7945                                                    items, tunnel);
7946                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7947                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7948                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7949                         break;
7950                 case RTE_FLOW_ITEM_TYPE_UDP:
7951                         flow_dv_translate_item_udp(match_mask, match_value,
7952                                                    items, tunnel);
7953                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7954                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7955                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7956                         break;
7957                 case RTE_FLOW_ITEM_TYPE_GRE:
7958                         flow_dv_translate_item_gre(match_mask, match_value,
7959                                                    items, tunnel);
7960                         matcher.priority = rss_desc->level >= 2 ?
7961                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7962                         last_item = MLX5_FLOW_LAYER_GRE;
7963                         break;
7964                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7965                         flow_dv_translate_item_gre_key(match_mask,
7966                                                        match_value, items);
7967                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7968                         break;
7969                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7970                         flow_dv_translate_item_nvgre(match_mask, match_value,
7971                                                      items, tunnel);
7972                         matcher.priority = rss_desc->level >= 2 ?
7973                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7974                         last_item = MLX5_FLOW_LAYER_GRE;
7975                         break;
7976                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7977                         flow_dv_translate_item_vxlan(match_mask, match_value,
7978                                                      items, tunnel);
7979                         matcher.priority = rss_desc->level >= 2 ?
7980                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7981                         last_item = MLX5_FLOW_LAYER_VXLAN;
7982                         break;
7983                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7984                         flow_dv_translate_item_vxlan_gpe(match_mask,
7985                                                          match_value, items,
7986                                                          tunnel);
7987                         matcher.priority = rss_desc->level >= 2 ?
7988                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7989                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7990                         break;
7991                 case RTE_FLOW_ITEM_TYPE_GENEVE:
7992                         flow_dv_translate_item_geneve(match_mask, match_value,
7993                                                       items, tunnel);
7994                         matcher.priority = rss_desc->level >= 2 ?
7995                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7996                         last_item = MLX5_FLOW_LAYER_GENEVE;
7997                         break;
7998                 case RTE_FLOW_ITEM_TYPE_MPLS:
7999                         flow_dv_translate_item_mpls(match_mask, match_value,
8000                                                     items, last_item, tunnel);
8001                         matcher.priority = rss_desc->level >= 2 ?
8002                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8003                         last_item = MLX5_FLOW_LAYER_MPLS;
8004                         break;
8005                 case RTE_FLOW_ITEM_TYPE_MARK:
8006                         flow_dv_translate_item_mark(dev, match_mask,
8007                                                     match_value, items);
8008                         last_item = MLX5_FLOW_ITEM_MARK;
8009                         break;
8010                 case RTE_FLOW_ITEM_TYPE_META:
8011                         flow_dv_translate_item_meta(dev, match_mask,
8012                                                     match_value, attr, items);
8013                         last_item = MLX5_FLOW_ITEM_METADATA;
8014                         break;
8015                 case RTE_FLOW_ITEM_TYPE_ICMP:
8016                         flow_dv_translate_item_icmp(match_mask, match_value,
8017                                                     items, tunnel);
8018                         last_item = MLX5_FLOW_LAYER_ICMP;
8019                         break;
8020                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8021                         flow_dv_translate_item_icmp6(match_mask, match_value,
8022                                                       items, tunnel);
8023                         last_item = MLX5_FLOW_LAYER_ICMP6;
8024                         break;
8025                 case RTE_FLOW_ITEM_TYPE_TAG:
8026                         flow_dv_translate_item_tag(dev, match_mask,
8027                                                    match_value, items);
8028                         last_item = MLX5_FLOW_ITEM_TAG;
8029                         break;
8030                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8031                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8032                                                         match_value, items);
8033                         last_item = MLX5_FLOW_ITEM_TAG;
8034                         break;
8035                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8036                         flow_dv_translate_item_tx_queue(dev, match_mask,
8037                                                         match_value,
8038                                                         items);
8039                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8040                         break;
8041                 case RTE_FLOW_ITEM_TYPE_GTP:
8042                         flow_dv_translate_item_gtp(match_mask, match_value,
8043                                                    items, tunnel);
8044                         matcher.priority = rss_desc->level >= 2 ?
8045                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8046                         last_item = MLX5_FLOW_LAYER_GTP;
8047                         break;
8048                 default:
8049                         break;
8050                 }
8051                 item_flags |= last_item;
8052         }
8053         /*
8054          * When E-Switch mode is enabled, we have two cases where we need to
8055          * set the source port manually.
8056          * The first one, is in case of Nic steering rule, and the second is
8057          * E-Switch rule where no port_id item was found. In both cases
8058          * the source port is set according the current port in use.
8059          */
8060         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8061             (priv->representor || priv->master)) {
8062                 if (flow_dv_translate_item_port_id(dev, match_mask,
8063                                                    match_value, NULL))
8064                         return -rte_errno;
8065         }
8066 #ifdef RTE_LIBRTE_MLX5_DEBUG
8067         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8068                                               dev_flow->dv.value.buf));
8069 #endif
8070         /*
8071          * Layers may be already initialized from prefix flow if this dev_flow
8072          * is the suffix flow.
8073          */
8074         handle->layers |= item_flags;
8075         if (action_flags & MLX5_FLOW_ACTION_RSS)
8076                 flow_dv_hashfields_set(dev_flow, rss_desc);
8077         /* Register matcher. */
8078         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8079                                     matcher.mask.size);
8080         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8081                                                      matcher.priority);
8082         /* reserved field no needs to be set to 0 here. */
8083         tbl_key.domain = attr->transfer;
8084         tbl_key.direction = attr->egress;
8085         tbl_key.table_id = dev_flow->dv.group;
8086         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8087                 return -rte_errno;
8088         return 0;
8089 }
8090
8091 /**
8092  * Apply the flow to the NIC, lock free,
8093  * (mutex should be acquired by caller).
8094  *
8095  * @param[in] dev
8096  *   Pointer to the Ethernet device structure.
8097  * @param[in, out] flow
8098  *   Pointer to flow structure.
8099  * @param[out] error
8100  *   Pointer to error structure.
8101  *
8102  * @return
8103  *   0 on success, a negative errno value otherwise and rte_errno is set.
8104  */
8105 static int
8106 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8107                 struct rte_flow_error *error)
8108 {
8109         struct mlx5_flow_dv_workspace *dv;
8110         struct mlx5_flow_handle *dh;
8111         struct mlx5_flow_handle_dv *dv_h;
8112         struct mlx5_flow *dev_flow;
8113         struct mlx5_priv *priv = dev->data->dev_private;
8114         uint32_t handle_idx;
8115         int n;
8116         int err;
8117         int idx;
8118
8119         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8120                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8121                 dv = &dev_flow->dv;
8122                 dh = dev_flow->handle;
8123                 dv_h = &dh->dvh;
8124                 n = dv->actions_n;
8125                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8126                         if (dv->transfer) {
8127                                 dv->actions[n++] = priv->sh->esw_drop_action;
8128                         } else {
8129                                 struct mlx5_hrxq *drop_hrxq;
8130                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8131                                 if (!drop_hrxq) {
8132                                         rte_flow_error_set
8133                                                 (error, errno,
8134                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8135                                                  NULL,
8136                                                  "cannot get drop hash queue");
8137                                         goto error;
8138                                 }
8139                                 /*
8140                                  * Drop queues will be released by the specify
8141                                  * mlx5_hrxq_drop_release() function. Assign
8142                                  * the special index to hrxq to mark the queue
8143                                  * has been allocated.
8144                                  */
8145                                 dh->rix_hrxq = UINT32_MAX;
8146                                 dv->actions[n++] = drop_hrxq->action;
8147                         }
8148                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8149                         struct mlx5_hrxq *hrxq;
8150                         uint32_t hrxq_idx;
8151                         struct mlx5_flow_rss_desc *rss_desc =
8152                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8153                                 [!!priv->flow_nested_idx];
8154
8155                         MLX5_ASSERT(rss_desc->queue_num);
8156                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8157                                                  MLX5_RSS_HASH_KEY_LEN,
8158                                                  dev_flow->hash_fields,
8159                                                  rss_desc->queue,
8160                                                  rss_desc->queue_num);
8161                         if (!hrxq_idx) {
8162                                 hrxq_idx = mlx5_hrxq_new
8163                                                 (dev, rss_desc->key,
8164                                                 MLX5_RSS_HASH_KEY_LEN,
8165                                                 dev_flow->hash_fields,
8166                                                 rss_desc->queue,
8167                                                 rss_desc->queue_num,
8168                                                 !!(dh->layers &
8169                                                 MLX5_FLOW_LAYER_TUNNEL));
8170                         }
8171                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8172                                               hrxq_idx);
8173                         if (!hrxq) {
8174                                 rte_flow_error_set
8175                                         (error, rte_errno,
8176                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8177                                          "cannot get hash queue");
8178                                 goto error;
8179                         }
8180                         dh->rix_hrxq = hrxq_idx;
8181                         dv->actions[n++] = hrxq->action;
8182                 }
8183                 dh->ib_flow =
8184                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8185                                                   (void *)&dv->value, n,
8186                                                   dv->actions);
8187                 if (!dh->ib_flow) {
8188                         rte_flow_error_set(error, errno,
8189                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8190                                            NULL,
8191                                            "hardware refuses to create flow");
8192                         goto error;
8193                 }
8194                 if (priv->vmwa_context &&
8195                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8196                         /*
8197                          * The rule contains the VLAN pattern.
8198                          * For VF we are going to create VLAN
8199                          * interface to make hypervisor set correct
8200                          * e-Switch vport context.
8201                          */
8202                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8203                 }
8204         }
8205         return 0;
8206 error:
8207         err = rte_errno; /* Save rte_errno before cleanup. */
8208         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8209                        handle_idx, dh, next) {
8210                 /* hrxq is union, don't clear it if the flag is not set. */
8211                 if (dh->rix_hrxq) {
8212                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8213                                 mlx5_hrxq_drop_release(dev);
8214                                 dh->rix_hrxq = 0;
8215                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8216                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8217                                 dh->rix_hrxq = 0;
8218                         }
8219                 }
8220                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8221                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8222         }
8223         rte_errno = err; /* Restore rte_errno. */
8224         return -rte_errno;
8225 }
8226
8227 /**
8228  * Release the flow matcher.
8229  *
8230  * @param dev
8231  *   Pointer to Ethernet device.
8232  * @param handle
8233  *   Pointer to mlx5_flow_handle.
8234  *
8235  * @return
8236  *   1 while a reference on it exists, 0 when freed.
8237  */
8238 static int
8239 flow_dv_matcher_release(struct rte_eth_dev *dev,
8240                         struct mlx5_flow_handle *handle)
8241 {
8242         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8243
8244         MLX5_ASSERT(matcher->matcher_object);
8245         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8246                 dev->data->port_id, (void *)matcher,
8247                 rte_atomic32_read(&matcher->refcnt));
8248         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8249                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8250                            (matcher->matcher_object));
8251                 LIST_REMOVE(matcher, next);
8252                 /* table ref-- in release interface. */
8253                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8254                 rte_free(matcher);
8255                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8256                         dev->data->port_id, (void *)matcher);
8257                 return 0;
8258         }
8259         return 1;
8260 }
8261
8262 /**
8263  * Release an encap/decap resource.
8264  *
8265  * @param dev
8266  *   Pointer to Ethernet device.
8267  * @param handle
8268  *   Pointer to mlx5_flow_handle.
8269  *
8270  * @return
8271  *   1 while a reference on it exists, 0 when freed.
8272  */
8273 static int
8274 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8275                                      struct mlx5_flow_handle *handle)
8276 {
8277         struct mlx5_priv *priv = dev->data->dev_private;
8278         uint32_t idx = handle->dvh.rix_encap_decap;
8279         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8280
8281         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8282                          idx);
8283         if (!cache_resource)
8284                 return 0;
8285         MLX5_ASSERT(cache_resource->verbs_action);
8286         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8287                 (void *)cache_resource,
8288                 rte_atomic32_read(&cache_resource->refcnt));
8289         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8290                 claim_zero(mlx5_glue->destroy_flow_action
8291                                 (cache_resource->verbs_action));
8292                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8293                              &priv->sh->encaps_decaps, idx,
8294                              cache_resource, next);
8295                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8296                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8297                         (void *)cache_resource);
8298                 return 0;
8299         }
8300         return 1;
8301 }
8302
8303 /**
8304  * Release an jump to table action resource.
8305  *
8306  * @param dev
8307  *   Pointer to Ethernet device.
8308  * @param handle
8309  *   Pointer to mlx5_flow_handle.
8310  *
8311  * @return
8312  *   1 while a reference on it exists, 0 when freed.
8313  */
8314 static int
8315 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8316                                   struct mlx5_flow_handle *handle)
8317 {
8318         struct mlx5_priv *priv = dev->data->dev_private;
8319         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8320         struct mlx5_flow_tbl_data_entry *tbl_data;
8321
8322         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8323                              handle->rix_jump);
8324         if (!tbl_data)
8325                 return 0;
8326         cache_resource = &tbl_data->jump;
8327         MLX5_ASSERT(cache_resource->action);
8328         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8329                 (void *)cache_resource,
8330                 rte_atomic32_read(&cache_resource->refcnt));
8331         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8332                 claim_zero(mlx5_glue->destroy_flow_action
8333                                 (cache_resource->action));
8334                 /* jump action memory free is inside the table release. */
8335                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8336                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8337                         (void *)cache_resource);
8338                 return 0;
8339         }
8340         return 1;
8341 }
8342
8343 /**
8344  * Release a modify-header resource.
8345  *
8346  * @param handle
8347  *   Pointer to mlx5_flow_handle.
8348  *
8349  * @return
8350  *   1 while a reference on it exists, 0 when freed.
8351  */
8352 static int
8353 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8354 {
8355         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8356                                                         handle->dvh.modify_hdr;
8357
8358         MLX5_ASSERT(cache_resource->verbs_action);
8359         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8360                 (void *)cache_resource,
8361                 rte_atomic32_read(&cache_resource->refcnt));
8362         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8363                 claim_zero(mlx5_glue->destroy_flow_action
8364                                 (cache_resource->verbs_action));
8365                 LIST_REMOVE(cache_resource, next);
8366                 rte_free(cache_resource);
8367                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8368                         (void *)cache_resource);
8369                 return 0;
8370         }
8371         return 1;
8372 }
8373
8374 /**
8375  * Release port ID action resource.
8376  *
8377  * @param dev
8378  *   Pointer to Ethernet device.
8379  * @param handle
8380  *   Pointer to mlx5_flow_handle.
8381  *
8382  * @return
8383  *   1 while a reference on it exists, 0 when freed.
8384  */
8385 static int
8386 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8387                                         struct mlx5_flow_handle *handle)
8388 {
8389         struct mlx5_priv *priv = dev->data->dev_private;
8390         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8391         uint32_t idx = handle->rix_port_id_action;
8392
8393         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8394                                         idx);
8395         if (!cache_resource)
8396                 return 0;
8397         MLX5_ASSERT(cache_resource->action);
8398         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8399                 (void *)cache_resource,
8400                 rte_atomic32_read(&cache_resource->refcnt));
8401         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8402                 claim_zero(mlx5_glue->destroy_flow_action
8403                                 (cache_resource->action));
8404                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8405                              &priv->sh->port_id_action_list, idx,
8406                              cache_resource, next);
8407                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8408                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8409                         (void *)cache_resource);
8410                 return 0;
8411         }
8412         return 1;
8413 }
8414
8415 /**
8416  * Release push vlan action resource.
8417  *
8418  * @param dev
8419  *   Pointer to Ethernet device.
8420  * @param handle
8421  *   Pointer to mlx5_flow_handle.
8422  *
8423  * @return
8424  *   1 while a reference on it exists, 0 when freed.
8425  */
8426 static int
8427 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8428                                           struct mlx5_flow_handle *handle)
8429 {
8430         struct mlx5_priv *priv = dev->data->dev_private;
8431         uint32_t idx = handle->dvh.rix_push_vlan;
8432         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8433
8434         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8435                                         idx);
8436         if (!cache_resource)
8437                 return 0;
8438         MLX5_ASSERT(cache_resource->action);
8439         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8440                 (void *)cache_resource,
8441                 rte_atomic32_read(&cache_resource->refcnt));
8442         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8443                 claim_zero(mlx5_glue->destroy_flow_action
8444                                 (cache_resource->action));
8445                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8446                              &priv->sh->push_vlan_action_list, idx,
8447                              cache_resource, next);
8448                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8449                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8450                         (void *)cache_resource);
8451                 return 0;
8452         }
8453         return 1;
8454 }
8455
8456 /**
8457  * Release the fate resource.
8458  *
8459  * @param dev
8460  *   Pointer to Ethernet device.
8461  * @param handle
8462  *   Pointer to mlx5_flow_handle.
8463  */
8464 static void
8465 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8466                                struct mlx5_flow_handle *handle)
8467 {
8468         if (!handle->rix_fate)
8469                 return;
8470         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8471                 mlx5_hrxq_drop_release(dev);
8472         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8473                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8474         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8475                 flow_dv_jump_tbl_resource_release(dev, handle);
8476         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8477                 flow_dv_port_id_action_resource_release(dev, handle);
8478         else
8479                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8480         handle->rix_fate = 0;
8481 }
8482
8483 /**
8484  * Remove the flow from the NIC but keeps it in memory.
8485  * Lock free, (mutex should be acquired by caller).
8486  *
8487  * @param[in] dev
8488  *   Pointer to Ethernet device.
8489  * @param[in, out] flow
8490  *   Pointer to flow structure.
8491  */
8492 static void
8493 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8494 {
8495         struct mlx5_flow_handle *dh;
8496         uint32_t handle_idx;
8497         struct mlx5_priv *priv = dev->data->dev_private;
8498
8499         if (!flow)
8500                 return;
8501         handle_idx = flow->dev_handles;
8502         while (handle_idx) {
8503                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8504                                     handle_idx);
8505                 if (!dh)
8506                         return;
8507                 if (dh->ib_flow) {
8508                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8509                         dh->ib_flow = NULL;
8510                 }
8511                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8512                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8513                         flow_dv_fate_resource_release(dev, dh);
8514                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8515                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8516                 handle_idx = dh->next.next;
8517         }
8518 }
8519
8520 /**
8521  * Remove the flow from the NIC and the memory.
8522  * Lock free, (mutex should be acquired by caller).
8523  *
8524  * @param[in] dev
8525  *   Pointer to the Ethernet device structure.
8526  * @param[in, out] flow
8527  *   Pointer to flow structure.
8528  */
8529 static void
8530 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8531 {
8532         struct mlx5_flow_handle *dev_handle;
8533         struct mlx5_priv *priv = dev->data->dev_private;
8534
8535         if (!flow)
8536                 return;
8537         __flow_dv_remove(dev, flow);
8538         if (flow->counter) {
8539                 flow_dv_counter_release(dev, flow->counter);
8540                 flow->counter = 0;
8541         }
8542         if (flow->meter) {
8543                 struct mlx5_flow_meter *fm;
8544
8545                 fm  = mlx5_flow_meter_find(priv, flow->meter);
8546                 if (fm)
8547                         mlx5_flow_meter_detach(fm);
8548                 flow->meter = 0;
8549         }
8550         while (flow->dev_handles) {
8551                 uint32_t tmp_idx = flow->dev_handles;
8552
8553                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8554                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8555                 if (!dev_handle)
8556                         return;
8557                 flow->dev_handles = dev_handle->next.next;
8558                 if (dev_handle->dvh.matcher)
8559                         flow_dv_matcher_release(dev, dev_handle);
8560                 if (dev_handle->dvh.rix_encap_decap)
8561                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8562                 if (dev_handle->dvh.modify_hdr)
8563                         flow_dv_modify_hdr_resource_release(dev_handle);
8564                 if (dev_handle->dvh.rix_push_vlan)
8565                         flow_dv_push_vlan_action_resource_release(dev,
8566                                                                   dev_handle);
8567                 if (dev_handle->dvh.rix_tag)
8568                         flow_dv_tag_release(dev,
8569                                             dev_handle->dvh.rix_tag);
8570                 flow_dv_fate_resource_release(dev, dev_handle);
8571                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8572                            tmp_idx);
8573         }
8574 }
8575
8576 /**
8577  * Query a dv flow  rule for its statistics via devx.
8578  *
8579  * @param[in] dev
8580  *   Pointer to Ethernet device.
8581  * @param[in] flow
8582  *   Pointer to the sub flow.
8583  * @param[out] data
8584  *   data retrieved by the query.
8585  * @param[out] error
8586  *   Perform verbose error reporting if not NULL.
8587  *
8588  * @return
8589  *   0 on success, a negative errno value otherwise and rte_errno is set.
8590  */
8591 static int
8592 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8593                     void *data, struct rte_flow_error *error)
8594 {
8595         struct mlx5_priv *priv = dev->data->dev_private;
8596         struct rte_flow_query_count *qc = data;
8597
8598         if (!priv->config.devx)
8599                 return rte_flow_error_set(error, ENOTSUP,
8600                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8601                                           NULL,
8602                                           "counters are not supported");
8603         if (flow->counter) {
8604                 uint64_t pkts, bytes;
8605                 struct mlx5_flow_counter *cnt;
8606
8607                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8608                                                  NULL);
8609                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8610                                                &bytes);
8611
8612                 if (err)
8613                         return rte_flow_error_set(error, -err,
8614                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8615                                         NULL, "cannot read counters");
8616                 qc->hits_set = 1;
8617                 qc->bytes_set = 1;
8618                 qc->hits = pkts - cnt->hits;
8619                 qc->bytes = bytes - cnt->bytes;
8620                 if (qc->reset) {
8621                         cnt->hits = pkts;
8622                         cnt->bytes = bytes;
8623                 }
8624                 return 0;
8625         }
8626         return rte_flow_error_set(error, EINVAL,
8627                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8628                                   NULL,
8629                                   "counters are not available");
8630 }
8631
8632 /**
8633  * Query a flow.
8634  *
8635  * @see rte_flow_query()
8636  * @see rte_flow_ops
8637  */
8638 static int
8639 flow_dv_query(struct rte_eth_dev *dev,
8640               struct rte_flow *flow __rte_unused,
8641               const struct rte_flow_action *actions __rte_unused,
8642               void *data __rte_unused,
8643               struct rte_flow_error *error __rte_unused)
8644 {
8645         int ret = -EINVAL;
8646
8647         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8648                 switch (actions->type) {
8649                 case RTE_FLOW_ACTION_TYPE_VOID:
8650                         break;
8651                 case RTE_FLOW_ACTION_TYPE_COUNT:
8652                         ret = flow_dv_query_count(dev, flow, data, error);
8653                         break;
8654                 default:
8655                         return rte_flow_error_set(error, ENOTSUP,
8656                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8657                                                   actions,
8658                                                   "action not supported");
8659                 }
8660         }
8661         return ret;
8662 }
8663
8664 /**
8665  * Destroy the meter table set.
8666  * Lock free, (mutex should be acquired by caller).
8667  *
8668  * @param[in] dev
8669  *   Pointer to Ethernet device.
8670  * @param[in] tbl
8671  *   Pointer to the meter table set.
8672  *
8673  * @return
8674  *   Always 0.
8675  */
8676 static int
8677 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8678                         struct mlx5_meter_domains_infos *tbl)
8679 {
8680         struct mlx5_priv *priv = dev->data->dev_private;
8681         struct mlx5_meter_domains_infos *mtd =
8682                                 (struct mlx5_meter_domains_infos *)tbl;
8683
8684         if (!mtd || !priv->config.dv_flow_en)
8685                 return 0;
8686         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8687                 claim_zero(mlx5_glue->dv_destroy_flow
8688                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8689         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8690                 claim_zero(mlx5_glue->dv_destroy_flow
8691                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8692         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8693                 claim_zero(mlx5_glue->dv_destroy_flow
8694                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8695         if (mtd->egress.color_matcher)
8696                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8697                           (mtd->egress.color_matcher));
8698         if (mtd->egress.any_matcher)
8699                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8700                           (mtd->egress.any_matcher));
8701         if (mtd->egress.tbl)
8702                 claim_zero(flow_dv_tbl_resource_release(dev,
8703                                                         mtd->egress.tbl));
8704         if (mtd->egress.sfx_tbl)
8705                 claim_zero(flow_dv_tbl_resource_release(dev,
8706                                                         mtd->egress.sfx_tbl));
8707         if (mtd->ingress.color_matcher)
8708                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8709                           (mtd->ingress.color_matcher));
8710         if (mtd->ingress.any_matcher)
8711                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8712                           (mtd->ingress.any_matcher));
8713         if (mtd->ingress.tbl)
8714                 claim_zero(flow_dv_tbl_resource_release(dev,
8715                                                         mtd->ingress.tbl));
8716         if (mtd->ingress.sfx_tbl)
8717                 claim_zero(flow_dv_tbl_resource_release(dev,
8718                                                         mtd->ingress.sfx_tbl));
8719         if (mtd->transfer.color_matcher)
8720                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8721                           (mtd->transfer.color_matcher));
8722         if (mtd->transfer.any_matcher)
8723                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8724                           (mtd->transfer.any_matcher));
8725         if (mtd->transfer.tbl)
8726                 claim_zero(flow_dv_tbl_resource_release(dev,
8727                                                         mtd->transfer.tbl));
8728         if (mtd->transfer.sfx_tbl)
8729                 claim_zero(flow_dv_tbl_resource_release(dev,
8730                                                         mtd->transfer.sfx_tbl));
8731         if (mtd->drop_actn)
8732                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8733         rte_free(mtd);
8734         return 0;
8735 }
8736
8737 /* Number of meter flow actions, count and jump or count and drop. */
8738 #define METER_ACTIONS 2
8739
8740 /**
8741  * Create specify domain meter table and suffix table.
8742  *
8743  * @param[in] dev
8744  *   Pointer to Ethernet device.
8745  * @param[in,out] mtb
8746  *   Pointer to DV meter table set.
8747  * @param[in] egress
8748  *   Table attribute.
8749  * @param[in] transfer
8750  *   Table attribute.
8751  * @param[in] color_reg_c_idx
8752  *   Reg C index for color match.
8753  *
8754  * @return
8755  *   0 on success, -1 otherwise and rte_errno is set.
8756  */
8757 static int
8758 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8759                            struct mlx5_meter_domains_infos *mtb,
8760                            uint8_t egress, uint8_t transfer,
8761                            uint32_t color_reg_c_idx)
8762 {
8763         struct mlx5_priv *priv = dev->data->dev_private;
8764         struct mlx5_ibv_shared *sh = priv->sh;
8765         struct mlx5_flow_dv_match_params mask = {
8766                 .size = sizeof(mask.buf),
8767         };
8768         struct mlx5_flow_dv_match_params value = {
8769                 .size = sizeof(value.buf),
8770         };
8771         struct mlx5dv_flow_matcher_attr dv_attr = {
8772                 .type = IBV_FLOW_ATTR_NORMAL,
8773                 .priority = 0,
8774                 .match_criteria_enable = 0,
8775                 .match_mask = (void *)&mask,
8776         };
8777         void *actions[METER_ACTIONS];
8778         struct mlx5_meter_domain_info *dtb;
8779         struct rte_flow_error error;
8780         int i = 0;
8781
8782         if (transfer)
8783                 dtb = &mtb->transfer;
8784         else if (egress)
8785                 dtb = &mtb->egress;
8786         else
8787                 dtb = &mtb->ingress;
8788         /* Create the meter table with METER level. */
8789         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8790                                             egress, transfer, &error);
8791         if (!dtb->tbl) {
8792                 DRV_LOG(ERR, "Failed to create meter policer table.");
8793                 return -1;
8794         }
8795         /* Create the meter suffix table with SUFFIX level. */
8796         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8797                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8798                                             egress, transfer, &error);
8799         if (!dtb->sfx_tbl) {
8800                 DRV_LOG(ERR, "Failed to create meter suffix table.");
8801                 return -1;
8802         }
8803         /* Create matchers, Any and Color. */
8804         dv_attr.priority = 3;
8805         dv_attr.match_criteria_enable = 0;
8806         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8807                                                              &dv_attr,
8808                                                              dtb->tbl->obj);
8809         if (!dtb->any_matcher) {
8810                 DRV_LOG(ERR, "Failed to create meter"
8811                              " policer default matcher.");
8812                 goto error_exit;
8813         }
8814         dv_attr.priority = 0;
8815         dv_attr.match_criteria_enable =
8816                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8817         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8818                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8819         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8820                                                                &dv_attr,
8821                                                                dtb->tbl->obj);
8822         if (!dtb->color_matcher) {
8823                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8824                 goto error_exit;
8825         }
8826         if (mtb->count_actns[RTE_MTR_DROPPED])
8827                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8828         actions[i++] = mtb->drop_actn;
8829         /* Default rule: lowest priority, match any, actions: drop. */
8830         dtb->policer_rules[RTE_MTR_DROPPED] =
8831                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8832                                                  (void *)&value, i, actions);
8833         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8834                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8835                 goto error_exit;
8836         }
8837         return 0;
8838 error_exit:
8839         return -1;
8840 }
8841
8842 /**
8843  * Create the needed meter and suffix tables.
8844  * Lock free, (mutex should be acquired by caller).
8845  *
8846  * @param[in] dev
8847  *   Pointer to Ethernet device.
8848  * @param[in] fm
8849  *   Pointer to the flow meter.
8850  *
8851  * @return
8852  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8853  */
8854 static struct mlx5_meter_domains_infos *
8855 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8856                        const struct mlx5_flow_meter *fm)
8857 {
8858         struct mlx5_priv *priv = dev->data->dev_private;
8859         struct mlx5_meter_domains_infos *mtb;
8860         int ret;
8861         int i;
8862
8863         if (!priv->mtr_en) {
8864                 rte_errno = ENOTSUP;
8865                 return NULL;
8866         }
8867         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8868         if (!mtb) {
8869                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8870                 return NULL;
8871         }
8872         /* Create meter count actions */
8873         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8874                 struct mlx5_flow_counter *cnt;
8875                 if (!fm->policer_stats.cnt[i])
8876                         continue;
8877                 cnt = flow_dv_counter_get_by_idx(dev,
8878                       fm->policer_stats.cnt[i], NULL);
8879                 mtb->count_actns[i] = cnt->action;
8880         }
8881         /* Create drop action. */
8882         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8883         if (!mtb->drop_actn) {
8884                 DRV_LOG(ERR, "Failed to create drop action.");
8885                 goto error_exit;
8886         }
8887         /* Egress meter table. */
8888         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8889         if (ret) {
8890                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8891                 goto error_exit;
8892         }
8893         /* Ingress meter table. */
8894         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8895         if (ret) {
8896                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8897                 goto error_exit;
8898         }
8899         /* FDB meter table. */
8900         if (priv->config.dv_esw_en) {
8901                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8902                                                  priv->mtr_color_reg);
8903                 if (ret) {
8904                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8905                         goto error_exit;
8906                 }
8907         }
8908         return mtb;
8909 error_exit:
8910         flow_dv_destroy_mtr_tbl(dev, mtb);
8911         return NULL;
8912 }
8913
8914 /**
8915  * Destroy domain policer rule.
8916  *
8917  * @param[in] dt
8918  *   Pointer to domain table.
8919  */
8920 static void
8921 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8922 {
8923         int i;
8924
8925         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8926                 if (dt->policer_rules[i]) {
8927                         claim_zero(mlx5_glue->dv_destroy_flow
8928                                   (dt->policer_rules[i]));
8929                         dt->policer_rules[i] = NULL;
8930                 }
8931         }
8932         if (dt->jump_actn) {
8933                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8934                 dt->jump_actn = NULL;
8935         }
8936 }
8937
8938 /**
8939  * Destroy policer rules.
8940  *
8941  * @param[in] dev
8942  *   Pointer to Ethernet device.
8943  * @param[in] fm
8944  *   Pointer to flow meter structure.
8945  * @param[in] attr
8946  *   Pointer to flow attributes.
8947  *
8948  * @return
8949  *   Always 0.
8950  */
8951 static int
8952 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8953                               const struct mlx5_flow_meter *fm,
8954                               const struct rte_flow_attr *attr)
8955 {
8956         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8957
8958         if (!mtb)
8959                 return 0;
8960         if (attr->egress)
8961                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8962         if (attr->ingress)
8963                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8964         if (attr->transfer)
8965                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8966         return 0;
8967 }
8968
8969 /**
8970  * Create specify domain meter policer rule.
8971  *
8972  * @param[in] fm
8973  *   Pointer to flow meter structure.
8974  * @param[in] mtb
8975  *   Pointer to DV meter table set.
8976  * @param[in] mtr_reg_c
8977  *   Color match REG_C.
8978  *
8979  * @return
8980  *   0 on success, -1 otherwise.
8981  */
8982 static int
8983 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8984                                     struct mlx5_meter_domain_info *dtb,
8985                                     uint8_t mtr_reg_c)
8986 {
8987         struct mlx5_flow_dv_match_params matcher = {
8988                 .size = sizeof(matcher.buf),
8989         };
8990         struct mlx5_flow_dv_match_params value = {
8991                 .size = sizeof(value.buf),
8992         };
8993         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8994         void *actions[METER_ACTIONS];
8995         int i;
8996
8997         /* Create jump action. */
8998         if (!dtb->jump_actn)
8999                 dtb->jump_actn =
9000                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9001                                                         (dtb->sfx_tbl->obj);
9002         if (!dtb->jump_actn) {
9003                 DRV_LOG(ERR, "Failed to create policer jump action.");
9004                 goto error;
9005         }
9006         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9007                 int j = 0;
9008
9009                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9010                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9011                 if (mtb->count_actns[i])
9012                         actions[j++] = mtb->count_actns[i];
9013                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9014                         actions[j++] = mtb->drop_actn;
9015                 else
9016                         actions[j++] = dtb->jump_actn;
9017                 dtb->policer_rules[i] =
9018                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9019                                                  (void *)&value,
9020                                                   j, actions);
9021                 if (!dtb->policer_rules[i]) {
9022                         DRV_LOG(ERR, "Failed to create policer rule.");
9023                         goto error;
9024                 }
9025         }
9026         return 0;
9027 error:
9028         rte_errno = errno;
9029         return -1;
9030 }
9031
9032 /**
9033  * Create policer rules.
9034  *
9035  * @param[in] dev
9036  *   Pointer to Ethernet device.
9037  * @param[in] fm
9038  *   Pointer to flow meter structure.
9039  * @param[in] attr
9040  *   Pointer to flow attributes.
9041  *
9042  * @return
9043  *   0 on success, -1 otherwise.
9044  */
9045 static int
9046 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9047                              struct mlx5_flow_meter *fm,
9048                              const struct rte_flow_attr *attr)
9049 {
9050         struct mlx5_priv *priv = dev->data->dev_private;
9051         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9052         int ret;
9053
9054         if (attr->egress) {
9055                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9056                                                 priv->mtr_color_reg);
9057                 if (ret) {
9058                         DRV_LOG(ERR, "Failed to create egress policer.");
9059                         goto error;
9060                 }
9061         }
9062         if (attr->ingress) {
9063                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9064                                                 priv->mtr_color_reg);
9065                 if (ret) {
9066                         DRV_LOG(ERR, "Failed to create ingress policer.");
9067                         goto error;
9068                 }
9069         }
9070         if (attr->transfer) {
9071                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9072                                                 priv->mtr_color_reg);
9073                 if (ret) {
9074                         DRV_LOG(ERR, "Failed to create transfer policer.");
9075                         goto error;
9076                 }
9077         }
9078         return 0;
9079 error:
9080         flow_dv_destroy_policer_rules(dev, fm, attr);
9081         return -1;
9082 }
9083
9084 /**
9085  * Query a devx counter.
9086  *
9087  * @param[in] dev
9088  *   Pointer to the Ethernet device structure.
9089  * @param[in] cnt
9090  *   Index to the flow counter.
9091  * @param[in] clear
9092  *   Set to clear the counter statistics.
9093  * @param[out] pkts
9094  *   The statistics value of packets.
9095  * @param[out] bytes
9096  *   The statistics value of bytes.
9097  *
9098  * @return
9099  *   0 on success, otherwise return -1.
9100  */
9101 static int
9102 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9103                       uint64_t *pkts, uint64_t *bytes)
9104 {
9105         struct mlx5_priv *priv = dev->data->dev_private;
9106         struct mlx5_flow_counter *cnt;
9107         uint64_t inn_pkts, inn_bytes;
9108         int ret;
9109
9110         if (!priv->config.devx)
9111                 return -1;
9112
9113         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9114         if (ret)
9115                 return -1;
9116         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9117         *pkts = inn_pkts - cnt->hits;
9118         *bytes = inn_bytes - cnt->bytes;
9119         if (clear) {
9120                 cnt->hits = inn_pkts;
9121                 cnt->bytes = inn_bytes;
9122         }
9123         return 0;
9124 }
9125
9126 /*
9127  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9128  */
9129 static int
9130 flow_dv_translate(struct rte_eth_dev *dev,
9131                   struct mlx5_flow *dev_flow,
9132                   const struct rte_flow_attr *attr,
9133                   const struct rte_flow_item items[],
9134                   const struct rte_flow_action actions[],
9135                   struct rte_flow_error *error)
9136 {
9137         int ret;
9138
9139         flow_dv_shared_lock(dev);
9140         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9141         flow_dv_shared_unlock(dev);
9142         return ret;
9143 }
9144
9145 /*
9146  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9147  */
9148 static int
9149 flow_dv_apply(struct rte_eth_dev *dev,
9150               struct rte_flow *flow,
9151               struct rte_flow_error *error)
9152 {
9153         int ret;
9154
9155         flow_dv_shared_lock(dev);
9156         ret = __flow_dv_apply(dev, flow, error);
9157         flow_dv_shared_unlock(dev);
9158         return ret;
9159 }
9160
9161 /*
9162  * Mutex-protected thunk to lock-free __flow_dv_remove().
9163  */
9164 static void
9165 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9166 {
9167         flow_dv_shared_lock(dev);
9168         __flow_dv_remove(dev, flow);
9169         flow_dv_shared_unlock(dev);
9170 }
9171
9172 /*
9173  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9174  */
9175 static void
9176 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9177 {
9178         flow_dv_shared_lock(dev);
9179         __flow_dv_destroy(dev, flow);
9180         flow_dv_shared_unlock(dev);
9181 }
9182
9183 /*
9184  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9185  */
9186 static uint32_t
9187 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9188 {
9189         uint32_t cnt;
9190
9191         flow_dv_shared_lock(dev);
9192         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9193         flow_dv_shared_unlock(dev);
9194         return cnt;
9195 }
9196
9197 /*
9198  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9199  */
9200 static void
9201 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9202 {
9203         flow_dv_shared_lock(dev);
9204         flow_dv_counter_release(dev, cnt);
9205         flow_dv_shared_unlock(dev);
9206 }
9207
9208 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9209         .validate = flow_dv_validate,
9210         .prepare = flow_dv_prepare,
9211         .translate = flow_dv_translate,
9212         .apply = flow_dv_apply,
9213         .remove = flow_dv_remove,
9214         .destroy = flow_dv_destroy,
9215         .query = flow_dv_query,
9216         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9217         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9218         .create_policer_rules = flow_dv_create_policer_rules,
9219         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9220         .counter_alloc = flow_dv_counter_allocate,
9221         .counter_free = flow_dv_counter_free,
9222         .counter_query = flow_dv_counter_query,
9223 };
9224
9225 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */