1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
95 uint64_t layers = dev_flow->handle->layers;
98 * If layers is already initialized, it means this dev_flow is the
99 * suffix flow, the layers flags is set by the prefix flow. Need to
100 * use the layer flags from prefix flow as the suffix flow may not
101 * have the user defined items as the flow is split.
104 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
106 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
108 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
115 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
116 uint8_t next_protocol = 0xff;
117 switch (item->type) {
118 case RTE_FLOW_ITEM_TYPE_GRE:
119 case RTE_FLOW_ITEM_TYPE_NVGRE:
120 case RTE_FLOW_ITEM_TYPE_VXLAN:
121 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
122 case RTE_FLOW_ITEM_TYPE_GENEVE:
123 case RTE_FLOW_ITEM_TYPE_MPLS:
127 case RTE_FLOW_ITEM_TYPE_IPV4:
130 if (item->mask != NULL &&
131 ((const struct rte_flow_item_ipv4 *)
132 item->mask)->hdr.next_proto_id)
134 ((const struct rte_flow_item_ipv4 *)
135 (item->spec))->hdr.next_proto_id &
136 ((const struct rte_flow_item_ipv4 *)
137 (item->mask))->hdr.next_proto_id;
138 if ((next_protocol == IPPROTO_IPIP ||
139 next_protocol == IPPROTO_IPV6) && tunnel_decap)
142 case RTE_FLOW_ITEM_TYPE_IPV6:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv6 *)
147 item->mask)->hdr.proto)
149 ((const struct rte_flow_item_ipv6 *)
150 (item->spec))->hdr.proto &
151 ((const struct rte_flow_item_ipv6 *)
152 (item->mask))->hdr.proto;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_UDP:
161 case RTE_FLOW_ITEM_TYPE_TCP:
173 * Convert rte_mtr_color to mlx5 color.
182 rte_col_2_mlx5_col(enum rte_color rcol)
185 case RTE_COLOR_GREEN:
186 return MLX5_FLOW_COLOR_GREEN;
187 case RTE_COLOR_YELLOW:
188 return MLX5_FLOW_COLOR_YELLOW;
190 return MLX5_FLOW_COLOR_RED;
194 return MLX5_FLOW_COLOR_UNDEFINED;
197 struct field_modify_info {
198 uint32_t size; /* Size of field in protocol header, in bytes. */
199 uint32_t offset; /* Offset of field in protocol header, in bytes. */
200 enum mlx5_modification_field id;
203 struct field_modify_info modify_eth[] = {
204 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
205 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
206 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
207 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
211 struct field_modify_info modify_vlan_out_first_vid[] = {
212 /* Size in bits !!! */
213 {12, 0, MLX5_MODI_OUT_FIRST_VID},
217 struct field_modify_info modify_ipv4[] = {
218 {1, 1, MLX5_MODI_OUT_IP_DSCP},
219 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
220 {4, 12, MLX5_MODI_OUT_SIPV4},
221 {4, 16, MLX5_MODI_OUT_DIPV4},
225 struct field_modify_info modify_ipv6[] = {
226 {1, 0, MLX5_MODI_OUT_IP_DSCP},
227 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
228 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
229 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
230 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
231 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
232 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
233 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
234 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
235 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
239 struct field_modify_info modify_udp[] = {
240 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
241 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
245 struct field_modify_info modify_tcp[] = {
246 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
247 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
248 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
249 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
254 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
255 uint8_t next_protocol, uint64_t *item_flags,
258 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
259 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
260 if (next_protocol == IPPROTO_IPIP) {
261 *item_flags |= MLX5_FLOW_LAYER_IPIP;
264 if (next_protocol == IPPROTO_IPV6) {
265 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
271 * Acquire the synchronizing object to protect multithreaded access
272 * to shared dv context. Lock occurs only if context is actually
273 * shared, i.e. we have multiport IB device and representors are
277 * Pointer to the rte_eth_dev structure.
280 flow_dv_shared_lock(struct rte_eth_dev *dev)
282 struct mlx5_priv *priv = dev->data->dev_private;
283 struct mlx5_ibv_shared *sh = priv->sh;
285 if (sh->dv_refcnt > 1) {
288 ret = pthread_mutex_lock(&sh->dv_mutex);
295 flow_dv_shared_unlock(struct rte_eth_dev *dev)
297 struct mlx5_priv *priv = dev->data->dev_private;
298 struct mlx5_ibv_shared *sh = priv->sh;
300 if (sh->dv_refcnt > 1) {
303 ret = pthread_mutex_unlock(&sh->dv_mutex);
309 /* Update VLAN's VID/PCP based on input rte_flow_action.
312 * Pointer to struct rte_flow_action.
314 * Pointer to struct rte_vlan_hdr.
317 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
318 struct rte_vlan_hdr *vlan)
321 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
323 ((const struct rte_flow_action_of_set_vlan_pcp *)
324 action->conf)->vlan_pcp;
325 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
326 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
327 vlan->vlan_tci |= vlan_tci;
328 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
330 vlan->vlan_tci |= rte_be_to_cpu_16
331 (((const struct rte_flow_action_of_set_vlan_vid *)
332 action->conf)->vlan_vid);
337 * Fetch 1, 2, 3 or 4 byte field from the byte array
338 * and return as unsigned integer in host-endian format.
341 * Pointer to data array.
343 * Size of field to extract.
346 * converted field in host endian format.
348 static inline uint32_t
349 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
358 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
362 ret = (ret << 8) | *(data + sizeof(uint16_t));
365 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
376 * Convert modify-header action to DV specification.
378 * Data length of each action is determined by provided field description
379 * and the item mask. Data bit offset and width of each action is determined
380 * by provided item mask.
383 * Pointer to item specification.
385 * Pointer to field modification information.
386 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
387 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
388 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
390 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
391 * Negative offset value sets the same offset as source offset.
392 * size field is ignored, value is taken from source field.
393 * @param[in,out] resource
394 * Pointer to the modify-header resource.
396 * Type of modification.
398 * Pointer to the error structure.
401 * 0 on success, a negative errno value otherwise and rte_errno is set.
404 flow_dv_convert_modify_action(struct rte_flow_item *item,
405 struct field_modify_info *field,
406 struct field_modify_info *dcopy,
407 struct mlx5_flow_dv_modify_hdr_resource *resource,
408 uint32_t type, struct rte_flow_error *error)
410 uint32_t i = resource->actions_num;
411 struct mlx5_modification_cmd *actions = resource->actions;
414 * The item and mask are provided in big-endian format.
415 * The fields should be presented as in big-endian format either.
416 * Mask must be always present, it defines the actual field width.
418 MLX5_ASSERT(item->mask);
419 MLX5_ASSERT(field->size);
426 if (i >= MLX5_MAX_MODIFY_NUM)
427 return rte_flow_error_set(error, EINVAL,
428 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
429 "too many items to modify");
430 /* Fetch variable byte size mask from the array. */
431 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
432 field->offset, field->size);
437 /* Deduce actual data width in bits from mask value. */
438 off_b = rte_bsf32(mask);
439 size_b = sizeof(uint32_t) * CHAR_BIT -
440 off_b - __builtin_clz(mask);
442 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
443 actions[i] = (struct mlx5_modification_cmd) {
449 /* Convert entire record to expected big-endian format. */
450 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
451 if (type == MLX5_MODIFICATION_TYPE_COPY) {
453 actions[i].dst_field = dcopy->id;
454 actions[i].dst_offset =
455 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
456 /* Convert entire record to big-endian format. */
457 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
459 MLX5_ASSERT(item->spec);
460 data = flow_dv_fetch_field((const uint8_t *)item->spec +
461 field->offset, field->size);
462 /* Shift out the trailing masked bits from data. */
463 data = (data & mask) >> off_b;
464 actions[i].data1 = rte_cpu_to_be_32(data);
468 } while (field->size);
469 if (resource->actions_num == i)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "invalid modification flow item");
473 resource->actions_num = i;
478 * Convert modify-header set IPv4 address action to DV specification.
480 * @param[in,out] resource
481 * Pointer to the modify-header resource.
483 * Pointer to action specification.
485 * Pointer to the error structure.
488 * 0 on success, a negative errno value otherwise and rte_errno is set.
491 flow_dv_convert_action_modify_ipv4
492 (struct mlx5_flow_dv_modify_hdr_resource *resource,
493 const struct rte_flow_action *action,
494 struct rte_flow_error *error)
496 const struct rte_flow_action_set_ipv4 *conf =
497 (const struct rte_flow_action_set_ipv4 *)(action->conf);
498 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
499 struct rte_flow_item_ipv4 ipv4;
500 struct rte_flow_item_ipv4 ipv4_mask;
502 memset(&ipv4, 0, sizeof(ipv4));
503 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
504 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
505 ipv4.hdr.src_addr = conf->ipv4_addr;
506 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
508 ipv4.hdr.dst_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
512 item.mask = &ipv4_mask;
513 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
514 MLX5_MODIFICATION_TYPE_SET, error);
518 * Convert modify-header set IPv6 address action to DV specification.
520 * @param[in,out] resource
521 * Pointer to the modify-header resource.
523 * Pointer to action specification.
525 * Pointer to the error structure.
528 * 0 on success, a negative errno value otherwise and rte_errno is set.
531 flow_dv_convert_action_modify_ipv6
532 (struct mlx5_flow_dv_modify_hdr_resource *resource,
533 const struct rte_flow_action *action,
534 struct rte_flow_error *error)
536 const struct rte_flow_action_set_ipv6 *conf =
537 (const struct rte_flow_action_set_ipv6 *)(action->conf);
538 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
539 struct rte_flow_item_ipv6 ipv6;
540 struct rte_flow_item_ipv6 ipv6_mask;
542 memset(&ipv6, 0, sizeof(ipv6));
543 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
544 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
545 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
546 sizeof(ipv6.hdr.src_addr));
547 memcpy(&ipv6_mask.hdr.src_addr,
548 &rte_flow_item_ipv6_mask.hdr.src_addr,
549 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
552 sizeof(ipv6.hdr.dst_addr));
553 memcpy(&ipv6_mask.hdr.dst_addr,
554 &rte_flow_item_ipv6_mask.hdr.dst_addr,
555 sizeof(ipv6.hdr.dst_addr));
558 item.mask = &ipv6_mask;
559 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
560 MLX5_MODIFICATION_TYPE_SET, error);
564 * Convert modify-header set MAC address action to DV specification.
566 * @param[in,out] resource
567 * Pointer to the modify-header resource.
569 * Pointer to action specification.
571 * Pointer to the error structure.
574 * 0 on success, a negative errno value otherwise and rte_errno is set.
577 flow_dv_convert_action_modify_mac
578 (struct mlx5_flow_dv_modify_hdr_resource *resource,
579 const struct rte_flow_action *action,
580 struct rte_flow_error *error)
582 const struct rte_flow_action_set_mac *conf =
583 (const struct rte_flow_action_set_mac *)(action->conf);
584 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
585 struct rte_flow_item_eth eth;
586 struct rte_flow_item_eth eth_mask;
588 memset(ð, 0, sizeof(eth));
589 memset(ð_mask, 0, sizeof(eth_mask));
590 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
591 memcpy(ð.src.addr_bytes, &conf->mac_addr,
592 sizeof(eth.src.addr_bytes));
593 memcpy(ð_mask.src.addr_bytes,
594 &rte_flow_item_eth_mask.src.addr_bytes,
595 sizeof(eth_mask.src.addr_bytes));
597 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
598 sizeof(eth.dst.addr_bytes));
599 memcpy(ð_mask.dst.addr_bytes,
600 &rte_flow_item_eth_mask.dst.addr_bytes,
601 sizeof(eth_mask.dst.addr_bytes));
604 item.mask = ð_mask;
605 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
606 MLX5_MODIFICATION_TYPE_SET, error);
610 * Convert modify-header set VLAN VID action to DV specification.
612 * @param[in,out] resource
613 * Pointer to the modify-header resource.
615 * Pointer to action specification.
617 * Pointer to the error structure.
620 * 0 on success, a negative errno value otherwise and rte_errno is set.
623 flow_dv_convert_action_modify_vlan_vid
624 (struct mlx5_flow_dv_modify_hdr_resource *resource,
625 const struct rte_flow_action *action,
626 struct rte_flow_error *error)
628 const struct rte_flow_action_of_set_vlan_vid *conf =
629 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
630 int i = resource->actions_num;
631 struct mlx5_modification_cmd *actions = resource->actions;
632 struct field_modify_info *field = modify_vlan_out_first_vid;
634 if (i >= MLX5_MAX_MODIFY_NUM)
635 return rte_flow_error_set(error, EINVAL,
636 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
637 "too many items to modify");
638 actions[i] = (struct mlx5_modification_cmd) {
639 .action_type = MLX5_MODIFICATION_TYPE_SET,
641 .length = field->size,
642 .offset = field->offset,
644 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
645 actions[i].data1 = conf->vlan_vid;
646 actions[i].data1 = actions[i].data1 << 16;
647 resource->actions_num = ++i;
652 * Convert modify-header set TP action to DV specification.
654 * @param[in,out] resource
655 * Pointer to the modify-header resource.
657 * Pointer to action specification.
659 * Pointer to rte_flow_item objects list.
661 * Pointer to flow attributes structure.
662 * @param[in] dev_flow
663 * Pointer to the sub flow.
664 * @param[in] tunnel_decap
665 * Whether action is after tunnel decapsulation.
667 * Pointer to the error structure.
670 * 0 on success, a negative errno value otherwise and rte_errno is set.
673 flow_dv_convert_action_modify_tp
674 (struct mlx5_flow_dv_modify_hdr_resource *resource,
675 const struct rte_flow_action *action,
676 const struct rte_flow_item *items,
677 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
678 bool tunnel_decap, struct rte_flow_error *error)
680 const struct rte_flow_action_set_tp *conf =
681 (const struct rte_flow_action_set_tp *)(action->conf);
682 struct rte_flow_item item;
683 struct rte_flow_item_udp udp;
684 struct rte_flow_item_udp udp_mask;
685 struct rte_flow_item_tcp tcp;
686 struct rte_flow_item_tcp tcp_mask;
687 struct field_modify_info *field;
690 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
692 memset(&udp, 0, sizeof(udp));
693 memset(&udp_mask, 0, sizeof(udp_mask));
694 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
695 udp.hdr.src_port = conf->port;
696 udp_mask.hdr.src_port =
697 rte_flow_item_udp_mask.hdr.src_port;
699 udp.hdr.dst_port = conf->port;
700 udp_mask.hdr.dst_port =
701 rte_flow_item_udp_mask.hdr.dst_port;
703 item.type = RTE_FLOW_ITEM_TYPE_UDP;
705 item.mask = &udp_mask;
708 MLX5_ASSERT(attr->tcp);
709 memset(&tcp, 0, sizeof(tcp));
710 memset(&tcp_mask, 0, sizeof(tcp_mask));
711 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
712 tcp.hdr.src_port = conf->port;
713 tcp_mask.hdr.src_port =
714 rte_flow_item_tcp_mask.hdr.src_port;
716 tcp.hdr.dst_port = conf->port;
717 tcp_mask.hdr.dst_port =
718 rte_flow_item_tcp_mask.hdr.dst_port;
720 item.type = RTE_FLOW_ITEM_TYPE_TCP;
722 item.mask = &tcp_mask;
725 return flow_dv_convert_modify_action(&item, field, NULL, resource,
726 MLX5_MODIFICATION_TYPE_SET, error);
730 * Convert modify-header set TTL action to DV specification.
732 * @param[in,out] resource
733 * Pointer to the modify-header resource.
735 * Pointer to action specification.
737 * Pointer to rte_flow_item objects list.
739 * Pointer to flow attributes structure.
740 * @param[in] dev_flow
741 * Pointer to the sub flow.
742 * @param[in] tunnel_decap
743 * Whether action is after tunnel decapsulation.
745 * Pointer to the error structure.
748 * 0 on success, a negative errno value otherwise and rte_errno is set.
751 flow_dv_convert_action_modify_ttl
752 (struct mlx5_flow_dv_modify_hdr_resource *resource,
753 const struct rte_flow_action *action,
754 const struct rte_flow_item *items,
755 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
756 bool tunnel_decap, struct rte_flow_error *error)
758 const struct rte_flow_action_set_ttl *conf =
759 (const struct rte_flow_action_set_ttl *)(action->conf);
760 struct rte_flow_item item;
761 struct rte_flow_item_ipv4 ipv4;
762 struct rte_flow_item_ipv4 ipv4_mask;
763 struct rte_flow_item_ipv6 ipv6;
764 struct rte_flow_item_ipv6 ipv6_mask;
765 struct field_modify_info *field;
768 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
770 memset(&ipv4, 0, sizeof(ipv4));
771 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
772 ipv4.hdr.time_to_live = conf->ttl_value;
773 ipv4_mask.hdr.time_to_live = 0xFF;
774 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
776 item.mask = &ipv4_mask;
779 MLX5_ASSERT(attr->ipv6);
780 memset(&ipv6, 0, sizeof(ipv6));
781 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
782 ipv6.hdr.hop_limits = conf->ttl_value;
783 ipv6_mask.hdr.hop_limits = 0xFF;
784 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
786 item.mask = &ipv6_mask;
789 return flow_dv_convert_modify_action(&item, field, NULL, resource,
790 MLX5_MODIFICATION_TYPE_SET, error);
794 * Convert modify-header decrement TTL action to DV specification.
796 * @param[in,out] resource
797 * Pointer to the modify-header resource.
799 * Pointer to action specification.
801 * Pointer to rte_flow_item objects list.
803 * Pointer to flow attributes structure.
804 * @param[in] dev_flow
805 * Pointer to the sub flow.
806 * @param[in] tunnel_decap
807 * Whether action is after tunnel decapsulation.
809 * Pointer to the error structure.
812 * 0 on success, a negative errno value otherwise and rte_errno is set.
815 flow_dv_convert_action_modify_dec_ttl
816 (struct mlx5_flow_dv_modify_hdr_resource *resource,
817 const struct rte_flow_item *items,
818 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
819 bool tunnel_decap, struct rte_flow_error *error)
821 struct rte_flow_item item;
822 struct rte_flow_item_ipv4 ipv4;
823 struct rte_flow_item_ipv4 ipv4_mask;
824 struct rte_flow_item_ipv6 ipv6;
825 struct rte_flow_item_ipv6 ipv6_mask;
826 struct field_modify_info *field;
829 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
831 memset(&ipv4, 0, sizeof(ipv4));
832 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
833 ipv4.hdr.time_to_live = 0xFF;
834 ipv4_mask.hdr.time_to_live = 0xFF;
835 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
837 item.mask = &ipv4_mask;
840 MLX5_ASSERT(attr->ipv6);
841 memset(&ipv6, 0, sizeof(ipv6));
842 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
843 ipv6.hdr.hop_limits = 0xFF;
844 ipv6_mask.hdr.hop_limits = 0xFF;
845 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
847 item.mask = &ipv6_mask;
850 return flow_dv_convert_modify_action(&item, field, NULL, resource,
851 MLX5_MODIFICATION_TYPE_ADD, error);
855 * Convert modify-header increment/decrement TCP Sequence number
856 * to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to the error structure.
866 * 0 on success, a negative errno value otherwise and rte_errno is set.
869 flow_dv_convert_action_modify_tcp_seq
870 (struct mlx5_flow_dv_modify_hdr_resource *resource,
871 const struct rte_flow_action *action,
872 struct rte_flow_error *error)
874 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
875 uint64_t value = rte_be_to_cpu_32(*conf);
876 struct rte_flow_item item;
877 struct rte_flow_item_tcp tcp;
878 struct rte_flow_item_tcp tcp_mask;
880 memset(&tcp, 0, sizeof(tcp));
881 memset(&tcp_mask, 0, sizeof(tcp_mask));
882 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
884 * The HW has no decrement operation, only increment operation.
885 * To simulate decrement X from Y using increment operation
886 * we need to add UINT32_MAX X times to Y.
887 * Each adding of UINT32_MAX decrements Y by 1.
890 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
891 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
892 item.type = RTE_FLOW_ITEM_TYPE_TCP;
894 item.mask = &tcp_mask;
895 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
896 MLX5_MODIFICATION_TYPE_ADD, error);
900 * Convert modify-header increment/decrement TCP Acknowledgment number
901 * to DV specification.
903 * @param[in,out] resource
904 * Pointer to the modify-header resource.
906 * Pointer to action specification.
908 * Pointer to the error structure.
911 * 0 on success, a negative errno value otherwise and rte_errno is set.
914 flow_dv_convert_action_modify_tcp_ack
915 (struct mlx5_flow_dv_modify_hdr_resource *resource,
916 const struct rte_flow_action *action,
917 struct rte_flow_error *error)
919 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
920 uint64_t value = rte_be_to_cpu_32(*conf);
921 struct rte_flow_item item;
922 struct rte_flow_item_tcp tcp;
923 struct rte_flow_item_tcp tcp_mask;
925 memset(&tcp, 0, sizeof(tcp));
926 memset(&tcp_mask, 0, sizeof(tcp_mask));
927 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
929 * The HW has no decrement operation, only increment operation.
930 * To simulate decrement X from Y using increment operation
931 * we need to add UINT32_MAX X times to Y.
932 * Each adding of UINT32_MAX decrements Y by 1.
935 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
936 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
937 item.type = RTE_FLOW_ITEM_TYPE_TCP;
939 item.mask = &tcp_mask;
940 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
941 MLX5_MODIFICATION_TYPE_ADD, error);
944 static enum mlx5_modification_field reg_to_field[] = {
945 [REG_NONE] = MLX5_MODI_OUT_NONE,
946 [REG_A] = MLX5_MODI_META_DATA_REG_A,
947 [REG_B] = MLX5_MODI_META_DATA_REG_B,
948 [REG_C_0] = MLX5_MODI_META_REG_C_0,
949 [REG_C_1] = MLX5_MODI_META_REG_C_1,
950 [REG_C_2] = MLX5_MODI_META_REG_C_2,
951 [REG_C_3] = MLX5_MODI_META_REG_C_3,
952 [REG_C_4] = MLX5_MODI_META_REG_C_4,
953 [REG_C_5] = MLX5_MODI_META_REG_C_5,
954 [REG_C_6] = MLX5_MODI_META_REG_C_6,
955 [REG_C_7] = MLX5_MODI_META_REG_C_7,
959 * Convert register set to DV specification.
961 * @param[in,out] resource
962 * Pointer to the modify-header resource.
964 * Pointer to action specification.
966 * Pointer to the error structure.
969 * 0 on success, a negative errno value otherwise and rte_errno is set.
972 flow_dv_convert_action_set_reg
973 (struct mlx5_flow_dv_modify_hdr_resource *resource,
974 const struct rte_flow_action *action,
975 struct rte_flow_error *error)
977 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
978 struct mlx5_modification_cmd *actions = resource->actions;
979 uint32_t i = resource->actions_num;
981 if (i >= MLX5_MAX_MODIFY_NUM)
982 return rte_flow_error_set(error, EINVAL,
983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
984 "too many items to modify");
985 MLX5_ASSERT(conf->id != REG_NONE);
986 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
987 actions[i] = (struct mlx5_modification_cmd) {
988 .action_type = MLX5_MODIFICATION_TYPE_SET,
989 .field = reg_to_field[conf->id],
991 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
992 actions[i].data1 = rte_cpu_to_be_32(conf->data);
994 resource->actions_num = i;
999 * Convert SET_TAG action to DV specification.
1002 * Pointer to the rte_eth_dev structure.
1003 * @param[in,out] resource
1004 * Pointer to the modify-header resource.
1006 * Pointer to action specification.
1008 * Pointer to the error structure.
1011 * 0 on success, a negative errno value otherwise and rte_errno is set.
1014 flow_dv_convert_action_set_tag
1015 (struct rte_eth_dev *dev,
1016 struct mlx5_flow_dv_modify_hdr_resource *resource,
1017 const struct rte_flow_action_set_tag *conf,
1018 struct rte_flow_error *error)
1020 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1021 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1022 struct rte_flow_item item = {
1026 struct field_modify_info reg_c_x[] = {
1029 enum mlx5_modification_field reg_type;
1032 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1035 MLX5_ASSERT(ret != REG_NONE);
1036 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1037 reg_type = reg_to_field[ret];
1038 MLX5_ASSERT(reg_type > 0);
1039 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1040 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1041 MLX5_MODIFICATION_TYPE_SET, error);
1045 * Convert internal COPY_REG action to DV specification.
1048 * Pointer to the rte_eth_dev structure.
1049 * @param[in,out] res
1050 * Pointer to the modify-header resource.
1052 * Pointer to action specification.
1054 * Pointer to the error structure.
1057 * 0 on success, a negative errno value otherwise and rte_errno is set.
1060 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1061 struct mlx5_flow_dv_modify_hdr_resource *res,
1062 const struct rte_flow_action *action,
1063 struct rte_flow_error *error)
1065 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1066 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1067 struct rte_flow_item item = {
1071 struct field_modify_info reg_src[] = {
1072 {4, 0, reg_to_field[conf->src]},
1075 struct field_modify_info reg_dst = {
1077 .id = reg_to_field[conf->dst],
1079 /* Adjust reg_c[0] usage according to reported mask. */
1080 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1081 struct mlx5_priv *priv = dev->data->dev_private;
1082 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1084 MLX5_ASSERT(reg_c0);
1085 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1086 if (conf->dst == REG_C_0) {
1087 /* Copy to reg_c[0], within mask only. */
1088 reg_dst.offset = rte_bsf32(reg_c0);
1090 * Mask is ignoring the enianness, because
1091 * there is no conversion in datapath.
1093 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1094 /* Copy from destination lower bits to reg_c[0]. */
1095 mask = reg_c0 >> reg_dst.offset;
1097 /* Copy from destination upper bits to reg_c[0]. */
1098 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1099 rte_fls_u32(reg_c0));
1102 mask = rte_cpu_to_be_32(reg_c0);
1103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1104 /* Copy from reg_c[0] to destination lower bits. */
1107 /* Copy from reg_c[0] to destination upper bits. */
1108 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1109 (rte_fls_u32(reg_c0) -
1114 return flow_dv_convert_modify_action(&item,
1115 reg_src, ®_dst, res,
1116 MLX5_MODIFICATION_TYPE_COPY,
1121 * Convert MARK action to DV specification. This routine is used
1122 * in extensive metadata only and requires metadata register to be
1123 * handled. In legacy mode hardware tag resource is engaged.
1126 * Pointer to the rte_eth_dev structure.
1128 * Pointer to MARK action specification.
1129 * @param[in,out] resource
1130 * Pointer to the modify-header resource.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1139 const struct rte_flow_action_mark *conf,
1140 struct mlx5_flow_dv_modify_hdr_resource *resource,
1141 struct rte_flow_error *error)
1143 struct mlx5_priv *priv = dev->data->dev_private;
1144 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1145 priv->sh->dv_mark_mask);
1146 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1147 struct rte_flow_item item = {
1151 struct field_modify_info reg_c_x[] = {
1152 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158 return rte_flow_error_set(error, EINVAL,
1159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1160 NULL, "zero mark action mask");
1161 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1164 MLX5_ASSERT(reg > 0);
1165 if (reg == REG_C_0) {
1166 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1167 uint32_t shl_c0 = rte_bsf32(msk_c0);
1169 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1170 mask = rte_cpu_to_be_32(mask) & msk_c0;
1171 mask = rte_cpu_to_be_32(mask << shl_c0);
1173 reg_c_x[0].id = reg_to_field[reg];
1174 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1175 MLX5_MODIFICATION_TYPE_SET, error);
1179 * Get metadata register index for specified steering domain.
1182 * Pointer to the rte_eth_dev structure.
1184 * Attributes of flow to determine steering domain.
1186 * Pointer to the error structure.
1189 * positive index on success, a negative errno value otherwise
1190 * and rte_errno is set.
1192 static enum modify_reg
1193 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1194 const struct rte_flow_attr *attr,
1195 struct rte_flow_error *error)
1198 mlx5_flow_get_reg_id(dev, attr->transfer ?
1202 MLX5_METADATA_RX, 0, error);
1204 return rte_flow_error_set(error,
1205 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1206 NULL, "unavailable "
1207 "metadata register");
1212 * Convert SET_META action to DV specification.
1215 * Pointer to the rte_eth_dev structure.
1216 * @param[in,out] resource
1217 * Pointer to the modify-header resource.
1219 * Attributes of flow that includes this item.
1221 * Pointer to action specification.
1223 * Pointer to the error structure.
1226 * 0 on success, a negative errno value otherwise and rte_errno is set.
1229 flow_dv_convert_action_set_meta
1230 (struct rte_eth_dev *dev,
1231 struct mlx5_flow_dv_modify_hdr_resource *resource,
1232 const struct rte_flow_attr *attr,
1233 const struct rte_flow_action_set_meta *conf,
1234 struct rte_flow_error *error)
1236 uint32_t data = conf->data;
1237 uint32_t mask = conf->mask;
1238 struct rte_flow_item item = {
1242 struct field_modify_info reg_c_x[] = {
1245 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250 * In datapath code there is no endianness
1251 * coversions for perfromance reasons, all
1252 * pattern conversions are done in rte_flow.
1254 if (reg == REG_C_0) {
1255 struct mlx5_priv *priv = dev->data->dev_private;
1256 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1259 MLX5_ASSERT(msk_c0);
1260 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1261 shl_c0 = rte_bsf32(msk_c0);
1263 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1267 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1269 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1270 /* The routine expects parameters in memory as big-endian ones. */
1271 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1272 MLX5_MODIFICATION_TYPE_SET, error);
1276 * Convert modify-header set IPv4 DSCP action to DV specification.
1278 * @param[in,out] resource
1279 * Pointer to the modify-header resource.
1281 * Pointer to action specification.
1283 * Pointer to the error structure.
1286 * 0 on success, a negative errno value otherwise and rte_errno is set.
1289 flow_dv_convert_action_modify_ipv4_dscp
1290 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1291 const struct rte_flow_action *action,
1292 struct rte_flow_error *error)
1294 const struct rte_flow_action_set_dscp *conf =
1295 (const struct rte_flow_action_set_dscp *)(action->conf);
1296 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1297 struct rte_flow_item_ipv4 ipv4;
1298 struct rte_flow_item_ipv4 ipv4_mask;
1300 memset(&ipv4, 0, sizeof(ipv4));
1301 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1302 ipv4.hdr.type_of_service = conf->dscp;
1303 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1305 item.mask = &ipv4_mask;
1306 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1307 MLX5_MODIFICATION_TYPE_SET, error);
1311 * Convert modify-header set IPv6 DSCP action to DV specification.
1313 * @param[in,out] resource
1314 * Pointer to the modify-header resource.
1316 * Pointer to action specification.
1318 * Pointer to the error structure.
1321 * 0 on success, a negative errno value otherwise and rte_errno is set.
1324 flow_dv_convert_action_modify_ipv6_dscp
1325 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1326 const struct rte_flow_action *action,
1327 struct rte_flow_error *error)
1329 const struct rte_flow_action_set_dscp *conf =
1330 (const struct rte_flow_action_set_dscp *)(action->conf);
1331 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1332 struct rte_flow_item_ipv6 ipv6;
1333 struct rte_flow_item_ipv6 ipv6_mask;
1335 memset(&ipv6, 0, sizeof(ipv6));
1336 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1338 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1339 * rdma-core only accept the DSCP bits byte aligned start from
1340 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1341 * bits in IPv6 case as rdma-core requires byte aligned value.
1343 ipv6.hdr.vtc_flow = conf->dscp;
1344 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1346 item.mask = &ipv6_mask;
1347 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1348 MLX5_MODIFICATION_TYPE_SET, error);
1352 * Validate MARK item.
1355 * Pointer to the rte_eth_dev structure.
1357 * Item specification.
1359 * Attributes of flow that includes this item.
1361 * Pointer to error structure.
1364 * 0 on success, a negative errno value otherwise and rte_errno is set.
1367 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1368 const struct rte_flow_item *item,
1369 const struct rte_flow_attr *attr __rte_unused,
1370 struct rte_flow_error *error)
1372 struct mlx5_priv *priv = dev->data->dev_private;
1373 struct mlx5_dev_config *config = &priv->config;
1374 const struct rte_flow_item_mark *spec = item->spec;
1375 const struct rte_flow_item_mark *mask = item->mask;
1376 const struct rte_flow_item_mark nic_mask = {
1377 .id = priv->sh->dv_mark_mask,
1381 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1382 return rte_flow_error_set(error, ENOTSUP,
1383 RTE_FLOW_ERROR_TYPE_ITEM, item,
1384 "extended metadata feature"
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't available");
1396 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1400 return rte_flow_error_set(error, EINVAL,
1401 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1403 "data cannot be empty");
1404 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1408 "mark id exceeds the limit");
1412 return rte_flow_error_set(error, EINVAL,
1413 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1414 "mask cannot be zero");
1416 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1417 (const uint8_t *)&nic_mask,
1418 sizeof(struct rte_flow_item_mark),
1426 * Validate META item.
1429 * Pointer to the rte_eth_dev structure.
1431 * Item specification.
1433 * Attributes of flow that includes this item.
1435 * Pointer to error structure.
1438 * 0 on success, a negative errno value otherwise and rte_errno is set.
1441 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1442 const struct rte_flow_item *item,
1443 const struct rte_flow_attr *attr,
1444 struct rte_flow_error *error)
1446 struct mlx5_priv *priv = dev->data->dev_private;
1447 struct mlx5_dev_config *config = &priv->config;
1448 const struct rte_flow_item_meta *spec = item->spec;
1449 const struct rte_flow_item_meta *mask = item->mask;
1450 struct rte_flow_item_meta nic_mask = {
1457 return rte_flow_error_set(error, EINVAL,
1458 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1460 "data cannot be empty");
1461 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1462 if (!mlx5_flow_ext_mreg_supported(dev))
1463 return rte_flow_error_set(error, ENOTSUP,
1464 RTE_FLOW_ERROR_TYPE_ITEM, item,
1465 "extended metadata register"
1466 " isn't supported");
1467 reg = flow_dv_get_metadata_reg(dev, attr, error);
1471 return rte_flow_error_set(error, ENOTSUP,
1472 RTE_FLOW_ERROR_TYPE_ITEM, item,
1476 nic_mask.data = priv->sh->dv_meta_mask;
1479 mask = &rte_flow_item_meta_mask;
1481 return rte_flow_error_set(error, EINVAL,
1482 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1483 "mask cannot be zero");
1485 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1486 (const uint8_t *)&nic_mask,
1487 sizeof(struct rte_flow_item_meta),
1493 * Validate TAG item.
1496 * Pointer to the rte_eth_dev structure.
1498 * Item specification.
1500 * Attributes of flow that includes this item.
1502 * Pointer to error structure.
1505 * 0 on success, a negative errno value otherwise and rte_errno is set.
1508 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1509 const struct rte_flow_item *item,
1510 const struct rte_flow_attr *attr __rte_unused,
1511 struct rte_flow_error *error)
1513 const struct rte_flow_item_tag *spec = item->spec;
1514 const struct rte_flow_item_tag *mask = item->mask;
1515 const struct rte_flow_item_tag nic_mask = {
1516 .data = RTE_BE32(UINT32_MAX),
1521 if (!mlx5_flow_ext_mreg_supported(dev))
1522 return rte_flow_error_set(error, ENOTSUP,
1523 RTE_FLOW_ERROR_TYPE_ITEM, item,
1524 "extensive metadata register"
1525 " isn't supported");
1527 return rte_flow_error_set(error, EINVAL,
1528 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1530 "data cannot be empty");
1532 mask = &rte_flow_item_tag_mask;
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1536 "mask cannot be zero");
1538 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1539 (const uint8_t *)&nic_mask,
1540 sizeof(struct rte_flow_item_tag),
1544 if (mask->index != 0xff)
1545 return rte_flow_error_set(error, EINVAL,
1546 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1547 "partial mask for tag index"
1548 " is not supported");
1549 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1552 MLX5_ASSERT(ret != REG_NONE);
1557 * Validate vport item.
1560 * Pointer to the rte_eth_dev structure.
1562 * Item specification.
1564 * Attributes of flow that includes this item.
1565 * @param[in] item_flags
1566 * Bit-fields that holds the items detected until now.
1568 * Pointer to error structure.
1571 * 0 on success, a negative errno value otherwise and rte_errno is set.
1574 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1575 const struct rte_flow_item *item,
1576 const struct rte_flow_attr *attr,
1577 uint64_t item_flags,
1578 struct rte_flow_error *error)
1580 const struct rte_flow_item_port_id *spec = item->spec;
1581 const struct rte_flow_item_port_id *mask = item->mask;
1582 const struct rte_flow_item_port_id switch_mask = {
1585 struct mlx5_priv *esw_priv;
1586 struct mlx5_priv *dev_priv;
1589 if (!attr->transfer)
1590 return rte_flow_error_set(error, EINVAL,
1591 RTE_FLOW_ERROR_TYPE_ITEM,
1593 "match on port id is valid only"
1594 " when transfer flag is enabled");
1595 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1596 return rte_flow_error_set(error, ENOTSUP,
1597 RTE_FLOW_ERROR_TYPE_ITEM, item,
1598 "multiple source ports are not"
1601 mask = &switch_mask;
1602 if (mask->id != 0xffffffff)
1603 return rte_flow_error_set(error, ENOTSUP,
1604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1606 "no support for partial mask on"
1608 ret = mlx5_flow_item_acceptable
1609 (item, (const uint8_t *)mask,
1610 (const uint8_t *)&rte_flow_item_port_id_mask,
1611 sizeof(struct rte_flow_item_port_id),
1617 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1619 return rte_flow_error_set(error, rte_errno,
1620 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1621 "failed to obtain E-Switch info for"
1623 dev_priv = mlx5_dev_to_eswitch_info(dev);
1625 return rte_flow_error_set(error, rte_errno,
1626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1628 "failed to obtain E-Switch info");
1629 if (esw_priv->domain_id != dev_priv->domain_id)
1630 return rte_flow_error_set(error, EINVAL,
1631 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1632 "cannot match on a port from a"
1633 " different E-Switch");
1638 * Validate GTP item.
1641 * Pointer to the rte_eth_dev structure.
1643 * Item specification.
1644 * @param[in] item_flags
1645 * Bit-fields that holds the items detected until now.
1647 * Pointer to error structure.
1650 * 0 on success, a negative errno value otherwise and rte_errno is set.
1653 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1654 const struct rte_flow_item *item,
1655 uint64_t item_flags,
1656 struct rte_flow_error *error)
1658 struct mlx5_priv *priv = dev->data->dev_private;
1659 const struct rte_flow_item_gtp *mask = item->mask;
1660 const struct rte_flow_item_gtp nic_mask = {
1662 .teid = RTE_BE32(0xffffffff),
1665 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1666 return rte_flow_error_set(error, ENOTSUP,
1667 RTE_FLOW_ERROR_TYPE_ITEM, item,
1668 "GTP support is not enabled");
1669 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "multiple tunnel layers not"
1674 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1675 return rte_flow_error_set(error, EINVAL,
1676 RTE_FLOW_ERROR_TYPE_ITEM, item,
1677 "no outer UDP layer found");
1679 mask = &rte_flow_item_gtp_mask;
1680 return mlx5_flow_item_acceptable
1681 (item, (const uint8_t *)mask,
1682 (const uint8_t *)&nic_mask,
1683 sizeof(struct rte_flow_item_gtp),
1688 * Validate the pop VLAN action.
1691 * Pointer to the rte_eth_dev structure.
1692 * @param[in] action_flags
1693 * Holds the actions detected until now.
1695 * Pointer to the pop vlan action.
1696 * @param[in] item_flags
1697 * The items found in this flow rule.
1699 * Pointer to flow attributes.
1701 * Pointer to error structure.
1704 * 0 on success, a negative errno value otherwise and rte_errno is set.
1707 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1708 uint64_t action_flags,
1709 const struct rte_flow_action *action,
1710 uint64_t item_flags,
1711 const struct rte_flow_attr *attr,
1712 struct rte_flow_error *error)
1714 const struct mlx5_priv *priv = dev->data->dev_private;
1718 if (!priv->sh->pop_vlan_action)
1719 return rte_flow_error_set(error, ENOTSUP,
1720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1722 "pop vlan action is not supported");
1724 return rte_flow_error_set(error, ENOTSUP,
1725 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1727 "pop vlan action not supported for "
1729 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1730 return rte_flow_error_set(error, ENOTSUP,
1731 RTE_FLOW_ERROR_TYPE_ACTION, action,
1732 "no support for multiple VLAN "
1734 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1735 return rte_flow_error_set(error, ENOTSUP,
1736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1738 "cannot pop vlan without a "
1739 "match on (outer) vlan in the flow");
1740 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1741 return rte_flow_error_set(error, EINVAL,
1742 RTE_FLOW_ERROR_TYPE_ACTION, action,
1743 "wrong action order, port_id should "
1744 "be after pop VLAN action");
1745 if (!attr->transfer && priv->representor)
1746 return rte_flow_error_set(error, ENOTSUP,
1747 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1748 "pop vlan action for VF representor "
1749 "not supported on NIC table");
1754 * Get VLAN default info from vlan match info.
1757 * the list of item specifications.
1759 * pointer VLAN info to fill to.
1762 * 0 on success, a negative errno value otherwise and rte_errno is set.
1765 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1766 struct rte_vlan_hdr *vlan)
1768 const struct rte_flow_item_vlan nic_mask = {
1769 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1770 MLX5DV_FLOW_VLAN_VID_MASK),
1771 .inner_type = RTE_BE16(0xffff),
1776 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1777 int type = items->type;
1779 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1780 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1783 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1784 const struct rte_flow_item_vlan *vlan_m = items->mask;
1785 const struct rte_flow_item_vlan *vlan_v = items->spec;
1789 /* Only full match values are accepted */
1790 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1791 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1792 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1794 rte_be_to_cpu_16(vlan_v->tci &
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1797 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1798 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1799 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1801 rte_be_to_cpu_16(vlan_v->tci &
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1804 if (vlan_m->inner_type == nic_mask.inner_type)
1805 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1806 vlan_m->inner_type);
1811 * Validate the push VLAN action.
1814 * Pointer to the rte_eth_dev structure.
1815 * @param[in] action_flags
1816 * Holds the actions detected until now.
1817 * @param[in] item_flags
1818 * The items found in this flow rule.
1820 * Pointer to the action structure.
1822 * Pointer to flow attributes
1824 * Pointer to error structure.
1827 * 0 on success, a negative errno value otherwise and rte_errno is set.
1830 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1831 uint64_t action_flags,
1832 uint64_t item_flags __rte_unused,
1833 const struct rte_flow_action *action,
1834 const struct rte_flow_attr *attr,
1835 struct rte_flow_error *error)
1837 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1838 const struct mlx5_priv *priv = dev->data->dev_private;
1840 if (!attr->transfer && attr->ingress)
1841 return rte_flow_error_set(error, ENOTSUP,
1842 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1844 "push VLAN action not supported for "
1846 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1847 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1848 return rte_flow_error_set(error, EINVAL,
1849 RTE_FLOW_ERROR_TYPE_ACTION, action,
1850 "invalid vlan ethertype");
1851 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "no support for multiple VLAN "
1856 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "wrong action order, port_id should "
1860 "be after push VLAN");
1861 if (!attr->transfer && priv->representor)
1862 return rte_flow_error_set(error, ENOTSUP,
1863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1864 "push vlan action for VF representor "
1865 "not supported on NIC table");
1871 * Validate the set VLAN PCP.
1873 * @param[in] action_flags
1874 * Holds the actions detected until now.
1875 * @param[in] actions
1876 * Pointer to the list of actions remaining in the flow rule.
1878 * Pointer to error structure.
1881 * 0 on success, a negative errno value otherwise and rte_errno is set.
1884 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1885 const struct rte_flow_action actions[],
1886 struct rte_flow_error *error)
1888 const struct rte_flow_action *action = actions;
1889 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1891 if (conf->vlan_pcp > 7)
1892 return rte_flow_error_set(error, EINVAL,
1893 RTE_FLOW_ERROR_TYPE_ACTION, action,
1894 "VLAN PCP value is too big");
1895 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1896 return rte_flow_error_set(error, ENOTSUP,
1897 RTE_FLOW_ERROR_TYPE_ACTION, action,
1898 "set VLAN PCP action must follow "
1899 "the push VLAN action");
1900 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1901 return rte_flow_error_set(error, ENOTSUP,
1902 RTE_FLOW_ERROR_TYPE_ACTION, action,
1903 "Multiple VLAN PCP modification are "
1905 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1906 return rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ACTION, action,
1908 "wrong action order, port_id should "
1909 "be after set VLAN PCP");
1914 * Validate the set VLAN VID.
1916 * @param[in] item_flags
1917 * Holds the items detected in this rule.
1918 * @param[in] action_flags
1919 * Holds the actions detected until now.
1920 * @param[in] actions
1921 * Pointer to the list of actions remaining in the flow rule.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1930 uint64_t action_flags,
1931 const struct rte_flow_action actions[],
1932 struct rte_flow_error *error)
1934 const struct rte_flow_action *action = actions;
1935 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1937 if (conf->vlan_vid > RTE_BE16(0xFFE))
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION, action,
1940 "VLAN VID value is too big");
1941 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1942 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1943 return rte_flow_error_set(error, ENOTSUP,
1944 RTE_FLOW_ERROR_TYPE_ACTION, action,
1945 "set VLAN VID action must follow push"
1946 " VLAN action or match on VLAN item");
1947 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1948 return rte_flow_error_set(error, ENOTSUP,
1949 RTE_FLOW_ERROR_TYPE_ACTION, action,
1950 "Multiple VLAN VID modifications are "
1952 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1953 return rte_flow_error_set(error, EINVAL,
1954 RTE_FLOW_ERROR_TYPE_ACTION, action,
1955 "wrong action order, port_id should "
1956 "be after set VLAN VID");
1961 * Validate the FLAG action.
1964 * Pointer to the rte_eth_dev structure.
1965 * @param[in] action_flags
1966 * Holds the actions detected until now.
1968 * Pointer to flow attributes
1970 * Pointer to error structure.
1973 * 0 on success, a negative errno value otherwise and rte_errno is set.
1976 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1977 uint64_t action_flags,
1978 const struct rte_flow_attr *attr,
1979 struct rte_flow_error *error)
1981 struct mlx5_priv *priv = dev->data->dev_private;
1982 struct mlx5_dev_config *config = &priv->config;
1985 /* Fall back if no extended metadata register support. */
1986 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1987 return mlx5_flow_validate_action_flag(action_flags, attr,
1989 /* Extensive metadata mode requires registers. */
1990 if (!mlx5_flow_ext_mreg_supported(dev))
1991 return rte_flow_error_set(error, ENOTSUP,
1992 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1993 "no metadata registers "
1994 "to support flag action");
1995 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1998 "extended metadata register"
1999 " isn't available");
2000 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2003 MLX5_ASSERT(ret > 0);
2004 if (action_flags & MLX5_FLOW_ACTION_MARK)
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2007 "can't mark and flag in same flow");
2008 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2009 return rte_flow_error_set(error, EINVAL,
2010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2012 " actions in same flow");
2017 * Validate MARK action.
2020 * Pointer to the rte_eth_dev structure.
2022 * Pointer to action.
2023 * @param[in] action_flags
2024 * Holds the actions detected until now.
2026 * Pointer to flow attributes
2028 * Pointer to error structure.
2031 * 0 on success, a negative errno value otherwise and rte_errno is set.
2034 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2035 const struct rte_flow_action *action,
2036 uint64_t action_flags,
2037 const struct rte_flow_attr *attr,
2038 struct rte_flow_error *error)
2040 struct mlx5_priv *priv = dev->data->dev_private;
2041 struct mlx5_dev_config *config = &priv->config;
2042 const struct rte_flow_action_mark *mark = action->conf;
2045 /* Fall back if no extended metadata register support. */
2046 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2047 return mlx5_flow_validate_action_mark(action, action_flags,
2049 /* Extensive metadata mode requires registers. */
2050 if (!mlx5_flow_ext_mreg_supported(dev))
2051 return rte_flow_error_set(error, ENOTSUP,
2052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2053 "no metadata registers "
2054 "to support mark action");
2055 if (!priv->sh->dv_mark_mask)
2056 return rte_flow_error_set(error, ENOTSUP,
2057 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2058 "extended metadata register"
2059 " isn't available");
2060 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2063 MLX5_ASSERT(ret > 0);
2065 return rte_flow_error_set(error, EINVAL,
2066 RTE_FLOW_ERROR_TYPE_ACTION, action,
2067 "configuration cannot be null");
2068 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2072 "mark id exceeds the limit");
2073 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2074 return rte_flow_error_set(error, EINVAL,
2075 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2076 "can't flag and mark in same flow");
2077 if (action_flags & MLX5_FLOW_ACTION_MARK)
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2080 "can't have 2 mark actions in same"
2086 * Validate SET_META action.
2089 * Pointer to the rte_eth_dev structure.
2091 * Pointer to the action structure.
2092 * @param[in] action_flags
2093 * Holds the actions detected until now.
2095 * Pointer to flow attributes
2097 * Pointer to error structure.
2100 * 0 on success, a negative errno value otherwise and rte_errno is set.
2103 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2104 const struct rte_flow_action *action,
2105 uint64_t action_flags __rte_unused,
2106 const struct rte_flow_attr *attr,
2107 struct rte_flow_error *error)
2109 const struct rte_flow_action_set_meta *conf;
2110 uint32_t nic_mask = UINT32_MAX;
2113 if (!mlx5_flow_ext_mreg_supported(dev))
2114 return rte_flow_error_set(error, ENOTSUP,
2115 RTE_FLOW_ERROR_TYPE_ACTION, action,
2116 "extended metadata register"
2117 " isn't supported");
2118 reg = flow_dv_get_metadata_reg(dev, attr, error);
2121 if (reg != REG_A && reg != REG_B) {
2122 struct mlx5_priv *priv = dev->data->dev_private;
2124 nic_mask = priv->sh->dv_meta_mask;
2126 if (!(action->conf))
2127 return rte_flow_error_set(error, EINVAL,
2128 RTE_FLOW_ERROR_TYPE_ACTION, action,
2129 "configuration cannot be null");
2130 conf = (const struct rte_flow_action_set_meta *)action->conf;
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ACTION, action,
2134 "zero mask doesn't have any effect");
2135 if (conf->mask & ~nic_mask)
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION, action,
2138 "meta data must be within reg C0");
2143 * Validate SET_TAG action.
2146 * Pointer to the rte_eth_dev structure.
2148 * Pointer to the action structure.
2149 * @param[in] action_flags
2150 * Holds the actions detected until now.
2152 * Pointer to flow attributes
2154 * Pointer to error structure.
2157 * 0 on success, a negative errno value otherwise and rte_errno is set.
2160 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2161 const struct rte_flow_action *action,
2162 uint64_t action_flags,
2163 const struct rte_flow_attr *attr,
2164 struct rte_flow_error *error)
2166 const struct rte_flow_action_set_tag *conf;
2167 const uint64_t terminal_action_flags =
2168 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2169 MLX5_FLOW_ACTION_RSS;
2172 if (!mlx5_flow_ext_mreg_supported(dev))
2173 return rte_flow_error_set(error, ENOTSUP,
2174 RTE_FLOW_ERROR_TYPE_ACTION, action,
2175 "extensive metadata register"
2176 " isn't supported");
2177 if (!(action->conf))
2178 return rte_flow_error_set(error, EINVAL,
2179 RTE_FLOW_ERROR_TYPE_ACTION, action,
2180 "configuration cannot be null");
2181 conf = (const struct rte_flow_action_set_tag *)action->conf;
2183 return rte_flow_error_set(error, EINVAL,
2184 RTE_FLOW_ERROR_TYPE_ACTION, action,
2185 "zero mask doesn't have any effect");
2186 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2189 if (!attr->transfer && attr->ingress &&
2190 (action_flags & terminal_action_flags))
2191 return rte_flow_error_set(error, EINVAL,
2192 RTE_FLOW_ERROR_TYPE_ACTION, action,
2193 "set_tag has no effect"
2194 " with terminal actions");
2199 * Validate count action.
2202 * Pointer to rte_eth_dev structure.
2204 * Pointer to error structure.
2207 * 0 on success, a negative errno value otherwise and rte_errno is set.
2210 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2211 struct rte_flow_error *error)
2213 struct mlx5_priv *priv = dev->data->dev_private;
2215 if (!priv->config.devx)
2217 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2221 return rte_flow_error_set
2223 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2225 "count action not supported");
2229 * Validate the L2 encap action.
2232 * Pointer to the rte_eth_dev structure.
2233 * @param[in] action_flags
2234 * Holds the actions detected until now.
2236 * Pointer to the action structure.
2238 * Pointer to flow attributes.
2240 * Pointer to error structure.
2243 * 0 on success, a negative errno value otherwise and rte_errno is set.
2246 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2247 uint64_t action_flags,
2248 const struct rte_flow_action *action,
2249 const struct rte_flow_attr *attr,
2250 struct rte_flow_error *error)
2252 const struct mlx5_priv *priv = dev->data->dev_private;
2254 if (!(action->conf))
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "configuration cannot be null");
2258 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2261 "can only have a single encap action "
2263 if (!attr->transfer && priv->representor)
2264 return rte_flow_error_set(error, ENOTSUP,
2265 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2266 "encap action for VF representor "
2267 "not supported on NIC table");
2272 * Validate a decap action.
2275 * Pointer to the rte_eth_dev structure.
2276 * @param[in] action_flags
2277 * Holds the actions detected until now.
2279 * Pointer to flow attributes
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2288 uint64_t action_flags,
2289 const struct rte_flow_attr *attr,
2290 struct rte_flow_error *error)
2292 const struct mlx5_priv *priv = dev->data->dev_private;
2294 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2295 return rte_flow_error_set(error, ENOTSUP,
2296 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2298 MLX5_FLOW_ACTION_DECAP ? "can only "
2299 "have a single decap action" : "decap "
2300 "after encap is not supported");
2301 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2302 return rte_flow_error_set(error, EINVAL,
2303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304 "can't have decap action after"
2307 return rte_flow_error_set(error, ENOTSUP,
2308 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2310 "decap action not supported for "
2312 if (!attr->transfer && priv->representor)
2313 return rte_flow_error_set(error, ENOTSUP,
2314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2315 "decap action for VF representor "
2316 "not supported on NIC table");
2320 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2323 * Validate the raw encap and decap actions.
2326 * Pointer to the rte_eth_dev structure.
2328 * Pointer to the decap action.
2330 * Pointer to the encap action.
2332 * Pointer to flow attributes
2333 * @param[in/out] action_flags
2334 * Holds the actions detected until now.
2335 * @param[out] actions_n
2336 * pointer to the number of actions counter.
2338 * Pointer to error structure.
2341 * 0 on success, a negative errno value otherwise and rte_errno is set.
2344 flow_dv_validate_action_raw_encap_decap
2345 (struct rte_eth_dev *dev,
2346 const struct rte_flow_action_raw_decap *decap,
2347 const struct rte_flow_action_raw_encap *encap,
2348 const struct rte_flow_attr *attr, uint64_t *action_flags,
2349 int *actions_n, struct rte_flow_error *error)
2351 const struct mlx5_priv *priv = dev->data->dev_private;
2354 if (encap && (!encap->size || !encap->data))
2355 return rte_flow_error_set(error, EINVAL,
2356 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2357 "raw encap data cannot be empty");
2358 if (decap && encap) {
2359 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2360 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2363 else if (encap->size <=
2364 MLX5_ENCAPSULATION_DECISION_SIZE &&
2366 MLX5_ENCAPSULATION_DECISION_SIZE)
2369 else if (encap->size >
2370 MLX5_ENCAPSULATION_DECISION_SIZE &&
2372 MLX5_ENCAPSULATION_DECISION_SIZE)
2373 /* 2 L2 actions: encap and decap. */
2376 return rte_flow_error_set(error,
2378 RTE_FLOW_ERROR_TYPE_ACTION,
2379 NULL, "unsupported too small "
2380 "raw decap and too small raw "
2381 "encap combination");
2384 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2388 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2392 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2393 return rte_flow_error_set(error, ENOTSUP,
2394 RTE_FLOW_ERROR_TYPE_ACTION,
2396 "small raw encap size");
2397 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2398 return rte_flow_error_set(error, EINVAL,
2399 RTE_FLOW_ERROR_TYPE_ACTION,
2401 "more than one encap action");
2402 if (!attr->transfer && priv->representor)
2403 return rte_flow_error_set
2405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2406 "encap action for VF representor "
2407 "not supported on NIC table");
2408 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2415 * Find existing encap/decap resource or create and register a new one.
2417 * @param[in, out] dev
2418 * Pointer to rte_eth_dev structure.
2419 * @param[in, out] resource
2420 * Pointer to encap/decap resource.
2421 * @parm[in, out] dev_flow
2422 * Pointer to the dev_flow.
2424 * pointer to error structure.
2427 * 0 on success otherwise -errno and errno is set.
2430 flow_dv_encap_decap_resource_register
2431 (struct rte_eth_dev *dev,
2432 struct mlx5_flow_dv_encap_decap_resource *resource,
2433 struct mlx5_flow *dev_flow,
2434 struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_ibv_shared *sh = priv->sh;
2438 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2439 struct mlx5dv_dr_domain *domain;
2441 resource->flags = dev_flow->dv.group ? 0 : 1;
2442 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2443 domain = sh->fdb_domain;
2444 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2445 domain = sh->rx_domain;
2447 domain = sh->tx_domain;
2448 /* Lookup a matching resource from cache. */
2449 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2450 if (resource->reformat_type == cache_resource->reformat_type &&
2451 resource->ft_type == cache_resource->ft_type &&
2452 resource->flags == cache_resource->flags &&
2453 resource->size == cache_resource->size &&
2454 !memcmp((const void *)resource->buf,
2455 (const void *)cache_resource->buf,
2457 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2458 (void *)cache_resource,
2459 rte_atomic32_read(&cache_resource->refcnt));
2460 rte_atomic32_inc(&cache_resource->refcnt);
2461 dev_flow->handle->dvh.encap_decap = cache_resource;
2465 /* Register new encap/decap resource. */
2466 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2467 if (!cache_resource)
2468 return rte_flow_error_set(error, ENOMEM,
2469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2470 "cannot allocate resource memory");
2471 *cache_resource = *resource;
2472 cache_resource->verbs_action =
2473 mlx5_glue->dv_create_flow_action_packet_reformat
2474 (sh->ctx, cache_resource->reformat_type,
2475 cache_resource->ft_type, domain, cache_resource->flags,
2476 cache_resource->size,
2477 (cache_resource->size ? cache_resource->buf : NULL));
2478 if (!cache_resource->verbs_action) {
2479 rte_free(cache_resource);
2480 return rte_flow_error_set(error, ENOMEM,
2481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2482 NULL, "cannot create action");
2484 rte_atomic32_init(&cache_resource->refcnt);
2485 rte_atomic32_inc(&cache_resource->refcnt);
2486 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2487 dev_flow->handle->dvh.encap_decap = cache_resource;
2488 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2489 (void *)cache_resource,
2490 rte_atomic32_read(&cache_resource->refcnt));
2495 * Find existing table jump resource or create and register a new one.
2497 * @param[in, out] dev
2498 * Pointer to rte_eth_dev structure.
2499 * @param[in, out] tbl
2500 * Pointer to flow table resource.
2501 * @parm[in, out] dev_flow
2502 * Pointer to the dev_flow.
2504 * pointer to error structure.
2507 * 0 on success otherwise -errno and errno is set.
2510 flow_dv_jump_tbl_resource_register
2511 (struct rte_eth_dev *dev __rte_unused,
2512 struct mlx5_flow_tbl_resource *tbl,
2513 struct mlx5_flow *dev_flow,
2514 struct rte_flow_error *error)
2516 struct mlx5_flow_tbl_data_entry *tbl_data =
2517 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2521 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2523 tbl_data->jump.action =
2524 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2526 if (!tbl_data->jump.action)
2527 return rte_flow_error_set(error, ENOMEM,
2528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2529 NULL, "cannot create jump action");
2530 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2531 (void *)&tbl_data->jump, cnt);
2533 MLX5_ASSERT(tbl_data->jump.action);
2534 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2535 (void *)&tbl_data->jump, cnt);
2537 rte_atomic32_inc(&tbl_data->jump.refcnt);
2538 dev_flow->handle->dvh.jump = &tbl_data->jump;
2543 * Find existing table port ID resource or create and register a new one.
2545 * @param[in, out] dev
2546 * Pointer to rte_eth_dev structure.
2547 * @param[in, out] resource
2548 * Pointer to port ID action resource.
2549 * @parm[in, out] dev_flow
2550 * Pointer to the dev_flow.
2552 * pointer to error structure.
2555 * 0 on success otherwise -errno and errno is set.
2558 flow_dv_port_id_action_resource_register
2559 (struct rte_eth_dev *dev,
2560 struct mlx5_flow_dv_port_id_action_resource *resource,
2561 struct mlx5_flow *dev_flow,
2562 struct rte_flow_error *error)
2564 struct mlx5_priv *priv = dev->data->dev_private;
2565 struct mlx5_ibv_shared *sh = priv->sh;
2566 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2568 /* Lookup a matching resource from cache. */
2569 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2570 if (resource->port_id == cache_resource->port_id) {
2571 DRV_LOG(DEBUG, "port id action resource resource %p: "
2573 (void *)cache_resource,
2574 rte_atomic32_read(&cache_resource->refcnt));
2575 rte_atomic32_inc(&cache_resource->refcnt);
2576 dev_flow->handle->dvh.port_id_action = cache_resource;
2580 /* Register new port id action resource. */
2581 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2582 if (!cache_resource)
2583 return rte_flow_error_set(error, ENOMEM,
2584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2585 "cannot allocate resource memory");
2586 *cache_resource = *resource;
2588 * Depending on rdma_core version the glue routine calls
2589 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2590 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2592 cache_resource->action =
2593 mlx5_glue->dr_create_flow_action_dest_port
2594 (priv->sh->fdb_domain, resource->port_id);
2595 if (!cache_resource->action) {
2596 rte_free(cache_resource);
2597 return rte_flow_error_set(error, ENOMEM,
2598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2599 NULL, "cannot create action");
2601 rte_atomic32_init(&cache_resource->refcnt);
2602 rte_atomic32_inc(&cache_resource->refcnt);
2603 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2604 dev_flow->handle->dvh.port_id_action = cache_resource;
2605 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2606 (void *)cache_resource,
2607 rte_atomic32_read(&cache_resource->refcnt));
2612 * Find existing push vlan resource or create and register a new one.
2614 * @param [in, out] dev
2615 * Pointer to rte_eth_dev structure.
2616 * @param[in, out] resource
2617 * Pointer to port ID action resource.
2618 * @parm[in, out] dev_flow
2619 * Pointer to the dev_flow.
2621 * pointer to error structure.
2624 * 0 on success otherwise -errno and errno is set.
2627 flow_dv_push_vlan_action_resource_register
2628 (struct rte_eth_dev *dev,
2629 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2630 struct mlx5_flow *dev_flow,
2631 struct rte_flow_error *error)
2633 struct mlx5_priv *priv = dev->data->dev_private;
2634 struct mlx5_ibv_shared *sh = priv->sh;
2635 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2636 struct mlx5dv_dr_domain *domain;
2638 /* Lookup a matching resource from cache. */
2639 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2640 if (resource->vlan_tag == cache_resource->vlan_tag &&
2641 resource->ft_type == cache_resource->ft_type) {
2642 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2644 (void *)cache_resource,
2645 rte_atomic32_read(&cache_resource->refcnt));
2646 rte_atomic32_inc(&cache_resource->refcnt);
2647 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2651 /* Register new push_vlan action resource. */
2652 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2653 if (!cache_resource)
2654 return rte_flow_error_set(error, ENOMEM,
2655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2656 "cannot allocate resource memory");
2657 *cache_resource = *resource;
2658 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2659 domain = sh->fdb_domain;
2660 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2661 domain = sh->rx_domain;
2663 domain = sh->tx_domain;
2664 cache_resource->action =
2665 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2666 resource->vlan_tag);
2667 if (!cache_resource->action) {
2668 rte_free(cache_resource);
2669 return rte_flow_error_set(error, ENOMEM,
2670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2671 NULL, "cannot create action");
2673 rte_atomic32_init(&cache_resource->refcnt);
2674 rte_atomic32_inc(&cache_resource->refcnt);
2675 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2676 dev_flow->handle->dvh.push_vlan_res = cache_resource;
2677 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2678 (void *)cache_resource,
2679 rte_atomic32_read(&cache_resource->refcnt));
2683 * Get the size of specific rte_flow_item_type
2685 * @param[in] item_type
2686 * Tested rte_flow_item_type.
2689 * sizeof struct item_type, 0 if void or irrelevant.
2692 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2696 switch (item_type) {
2697 case RTE_FLOW_ITEM_TYPE_ETH:
2698 retval = sizeof(struct rte_flow_item_eth);
2700 case RTE_FLOW_ITEM_TYPE_VLAN:
2701 retval = sizeof(struct rte_flow_item_vlan);
2703 case RTE_FLOW_ITEM_TYPE_IPV4:
2704 retval = sizeof(struct rte_flow_item_ipv4);
2706 case RTE_FLOW_ITEM_TYPE_IPV6:
2707 retval = sizeof(struct rte_flow_item_ipv6);
2709 case RTE_FLOW_ITEM_TYPE_UDP:
2710 retval = sizeof(struct rte_flow_item_udp);
2712 case RTE_FLOW_ITEM_TYPE_TCP:
2713 retval = sizeof(struct rte_flow_item_tcp);
2715 case RTE_FLOW_ITEM_TYPE_VXLAN:
2716 retval = sizeof(struct rte_flow_item_vxlan);
2718 case RTE_FLOW_ITEM_TYPE_GRE:
2719 retval = sizeof(struct rte_flow_item_gre);
2721 case RTE_FLOW_ITEM_TYPE_NVGRE:
2722 retval = sizeof(struct rte_flow_item_nvgre);
2724 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2725 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2727 case RTE_FLOW_ITEM_TYPE_MPLS:
2728 retval = sizeof(struct rte_flow_item_mpls);
2730 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2738 #define MLX5_ENCAP_IPV4_VERSION 0x40
2739 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2740 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2741 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2742 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2743 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2744 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2747 * Convert the encap action data from list of rte_flow_item to raw buffer
2750 * Pointer to rte_flow_item objects list.
2752 * Pointer to the output buffer.
2754 * Pointer to the output buffer size.
2756 * Pointer to the error structure.
2759 * 0 on success, a negative errno value otherwise and rte_errno is set.
2762 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2763 size_t *size, struct rte_flow_error *error)
2765 struct rte_ether_hdr *eth = NULL;
2766 struct rte_vlan_hdr *vlan = NULL;
2767 struct rte_ipv4_hdr *ipv4 = NULL;
2768 struct rte_ipv6_hdr *ipv6 = NULL;
2769 struct rte_udp_hdr *udp = NULL;
2770 struct rte_vxlan_hdr *vxlan = NULL;
2771 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2772 struct rte_gre_hdr *gre = NULL;
2774 size_t temp_size = 0;
2777 return rte_flow_error_set(error, EINVAL,
2778 RTE_FLOW_ERROR_TYPE_ACTION,
2779 NULL, "invalid empty data");
2780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2781 len = flow_dv_get_item_len(items->type);
2782 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION,
2785 (void *)items->type,
2786 "items total size is too big"
2787 " for encap action");
2788 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2789 switch (items->type) {
2790 case RTE_FLOW_ITEM_TYPE_ETH:
2791 eth = (struct rte_ether_hdr *)&buf[temp_size];
2793 case RTE_FLOW_ITEM_TYPE_VLAN:
2794 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2796 return rte_flow_error_set(error, EINVAL,
2797 RTE_FLOW_ERROR_TYPE_ACTION,
2798 (void *)items->type,
2799 "eth header not found");
2800 if (!eth->ether_type)
2801 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2803 case RTE_FLOW_ITEM_TYPE_IPV4:
2804 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2806 return rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ACTION,
2808 (void *)items->type,
2809 "neither eth nor vlan"
2811 if (vlan && !vlan->eth_proto)
2812 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2813 else if (eth && !eth->ether_type)
2814 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2815 if (!ipv4->version_ihl)
2816 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2817 MLX5_ENCAP_IPV4_IHL_MIN;
2818 if (!ipv4->time_to_live)
2819 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2821 case RTE_FLOW_ITEM_TYPE_IPV6:
2822 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2824 return rte_flow_error_set(error, EINVAL,
2825 RTE_FLOW_ERROR_TYPE_ACTION,
2826 (void *)items->type,
2827 "neither eth nor vlan"
2829 if (vlan && !vlan->eth_proto)
2830 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2831 else if (eth && !eth->ether_type)
2832 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2833 if (!ipv6->vtc_flow)
2835 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2836 if (!ipv6->hop_limits)
2837 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2839 case RTE_FLOW_ITEM_TYPE_UDP:
2840 udp = (struct rte_udp_hdr *)&buf[temp_size];
2842 return rte_flow_error_set(error, EINVAL,
2843 RTE_FLOW_ERROR_TYPE_ACTION,
2844 (void *)items->type,
2845 "ip header not found");
2846 if (ipv4 && !ipv4->next_proto_id)
2847 ipv4->next_proto_id = IPPROTO_UDP;
2848 else if (ipv6 && !ipv6->proto)
2849 ipv6->proto = IPPROTO_UDP;
2851 case RTE_FLOW_ITEM_TYPE_VXLAN:
2852 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2854 return rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ACTION,
2856 (void *)items->type,
2857 "udp header not found");
2859 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2860 if (!vxlan->vx_flags)
2862 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2864 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2865 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2867 return rte_flow_error_set(error, EINVAL,
2868 RTE_FLOW_ERROR_TYPE_ACTION,
2869 (void *)items->type,
2870 "udp header not found");
2871 if (!vxlan_gpe->proto)
2872 return rte_flow_error_set(error, EINVAL,
2873 RTE_FLOW_ERROR_TYPE_ACTION,
2874 (void *)items->type,
2875 "next protocol not found");
2878 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2879 if (!vxlan_gpe->vx_flags)
2880 vxlan_gpe->vx_flags =
2881 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2883 case RTE_FLOW_ITEM_TYPE_GRE:
2884 case RTE_FLOW_ITEM_TYPE_NVGRE:
2885 gre = (struct rte_gre_hdr *)&buf[temp_size];
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION,
2889 (void *)items->type,
2890 "next protocol not found");
2892 return rte_flow_error_set(error, EINVAL,
2893 RTE_FLOW_ERROR_TYPE_ACTION,
2894 (void *)items->type,
2895 "ip header not found");
2896 if (ipv4 && !ipv4->next_proto_id)
2897 ipv4->next_proto_id = IPPROTO_GRE;
2898 else if (ipv6 && !ipv6->proto)
2899 ipv6->proto = IPPROTO_GRE;
2901 case RTE_FLOW_ITEM_TYPE_VOID:
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 (void *)items->type,
2907 "unsupported item type");
2917 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2919 struct rte_ether_hdr *eth = NULL;
2920 struct rte_vlan_hdr *vlan = NULL;
2921 struct rte_ipv6_hdr *ipv6 = NULL;
2922 struct rte_udp_hdr *udp = NULL;
2926 eth = (struct rte_ether_hdr *)data;
2927 next_hdr = (char *)(eth + 1);
2928 proto = RTE_BE16(eth->ether_type);
2931 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2932 vlan = (struct rte_vlan_hdr *)next_hdr;
2933 proto = RTE_BE16(vlan->eth_proto);
2934 next_hdr += sizeof(struct rte_vlan_hdr);
2937 /* HW calculates IPv4 csum. no need to proceed */
2938 if (proto == RTE_ETHER_TYPE_IPV4)
2941 /* non IPv4/IPv6 header. not supported */
2942 if (proto != RTE_ETHER_TYPE_IPV6) {
2943 return rte_flow_error_set(error, ENOTSUP,
2944 RTE_FLOW_ERROR_TYPE_ACTION,
2945 NULL, "Cannot offload non IPv4/IPv6");
2948 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2950 /* ignore non UDP */
2951 if (ipv6->proto != IPPROTO_UDP)
2954 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2955 udp->dgram_cksum = 0;
2961 * Convert L2 encap action to DV specification.
2964 * Pointer to rte_eth_dev structure.
2966 * Pointer to action structure.
2967 * @param[in, out] dev_flow
2968 * Pointer to the mlx5_flow.
2969 * @param[in] transfer
2970 * Mark if the flow is E-Switch flow.
2972 * Pointer to the error structure.
2975 * 0 on success, a negative errno value otherwise and rte_errno is set.
2978 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2979 const struct rte_flow_action *action,
2980 struct mlx5_flow *dev_flow,
2982 struct rte_flow_error *error)
2984 const struct rte_flow_item *encap_data;
2985 const struct rte_flow_action_raw_encap *raw_encap_data;
2986 struct mlx5_flow_dv_encap_decap_resource res = {
2988 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2989 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2990 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2993 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2995 (const struct rte_flow_action_raw_encap *)action->conf;
2996 res.size = raw_encap_data->size;
2997 memcpy(res.buf, raw_encap_data->data, res.size);
2999 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3001 ((const struct rte_flow_action_vxlan_encap *)
3002 action->conf)->definition;
3005 ((const struct rte_flow_action_nvgre_encap *)
3006 action->conf)->definition;
3007 if (flow_dv_convert_encap_data(encap_data, res.buf,
3011 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3013 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION,
3016 NULL, "can't create L2 encap action");
3021 * Convert L2 decap action to DV specification.
3024 * Pointer to rte_eth_dev structure.
3025 * @param[in, out] dev_flow
3026 * Pointer to the mlx5_flow.
3027 * @param[in] transfer
3028 * Mark if the flow is E-Switch flow.
3030 * Pointer to the error structure.
3033 * 0 on success, a negative errno value otherwise and rte_errno is set.
3036 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3037 struct mlx5_flow *dev_flow,
3039 struct rte_flow_error *error)
3041 struct mlx5_flow_dv_encap_decap_resource res = {
3044 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3045 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3046 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3049 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 NULL, "can't create L2 decap action");
3057 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3060 * Pointer to rte_eth_dev structure.
3062 * Pointer to action structure.
3063 * @param[in, out] dev_flow
3064 * Pointer to the mlx5_flow.
3066 * Pointer to the flow attributes.
3068 * Pointer to the error structure.
3071 * 0 on success, a negative errno value otherwise and rte_errno is set.
3074 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3075 const struct rte_flow_action *action,
3076 struct mlx5_flow *dev_flow,
3077 const struct rte_flow_attr *attr,
3078 struct rte_flow_error *error)
3080 const struct rte_flow_action_raw_encap *encap_data;
3081 struct mlx5_flow_dv_encap_decap_resource res;
3083 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3084 res.size = encap_data->size;
3085 memcpy(res.buf, encap_data->data, res.size);
3086 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3087 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3088 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3090 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3092 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3093 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3094 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3095 return rte_flow_error_set(error, EINVAL,
3096 RTE_FLOW_ERROR_TYPE_ACTION,
3097 NULL, "can't create encap action");
3102 * Create action push VLAN.
3105 * Pointer to rte_eth_dev structure.
3107 * Pointer to the flow attributes.
3109 * Pointer to the vlan to push to the Ethernet header.
3110 * @param[in, out] dev_flow
3111 * Pointer to the mlx5_flow.
3113 * Pointer to the error structure.
3116 * 0 on success, a negative errno value otherwise and rte_errno is set.
3119 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3120 const struct rte_flow_attr *attr,
3121 const struct rte_vlan_hdr *vlan,
3122 struct mlx5_flow *dev_flow,
3123 struct rte_flow_error *error)
3125 struct mlx5_flow_dv_push_vlan_action_resource res;
3128 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3131 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3133 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3134 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3135 return flow_dv_push_vlan_action_resource_register
3136 (dev, &res, dev_flow, error);
3140 * Validate the modify-header actions.
3142 * @param[in] action_flags
3143 * Holds the actions detected until now.
3145 * Pointer to the modify action.
3147 * Pointer to error structure.
3150 * 0 on success, a negative errno value otherwise and rte_errno is set.
3153 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3154 const struct rte_flow_action *action,
3155 struct rte_flow_error *error)
3157 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3158 return rte_flow_error_set(error, EINVAL,
3159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3160 NULL, "action configuration not set");
3161 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3162 return rte_flow_error_set(error, EINVAL,
3163 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3164 "can't have encap action before"
3170 * Validate the modify-header MAC address actions.
3172 * @param[in] action_flags
3173 * Holds the actions detected until now.
3175 * Pointer to the modify action.
3176 * @param[in] item_flags
3177 * Holds the items detected.
3179 * Pointer to error structure.
3182 * 0 on success, a negative errno value otherwise and rte_errno is set.
3185 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3186 const struct rte_flow_action *action,
3187 const uint64_t item_flags,
3188 struct rte_flow_error *error)
3192 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3194 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3195 return rte_flow_error_set(error, EINVAL,
3196 RTE_FLOW_ERROR_TYPE_ACTION,
3198 "no L2 item in pattern");
3204 * Validate the modify-header IPv4 address actions.
3206 * @param[in] action_flags
3207 * Holds the actions detected until now.
3209 * Pointer to the modify action.
3210 * @param[in] item_flags
3211 * Holds the items detected.
3213 * Pointer to error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3220 const struct rte_flow_action *action,
3221 const uint64_t item_flags,
3222 struct rte_flow_error *error)
3227 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3229 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3230 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3231 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3232 if (!(item_flags & layer))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3236 "no ipv4 item in pattern");
3242 * Validate the modify-header IPv6 address actions.
3244 * @param[in] action_flags
3245 * Holds the actions detected until now.
3247 * Pointer to the modify action.
3248 * @param[in] item_flags
3249 * Holds the items detected.
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const uint64_t item_flags,
3260 struct rte_flow_error *error)
3265 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3267 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3268 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3269 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3270 if (!(item_flags & layer))
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION,
3274 "no ipv6 item in pattern");
3280 * Validate the modify-header TP actions.
3282 * @param[in] action_flags
3283 * Holds the actions detected until now.
3285 * Pointer to the modify action.
3286 * @param[in] item_flags
3287 * Holds the items detected.
3289 * Pointer to error structure.
3292 * 0 on success, a negative errno value otherwise and rte_errno is set.
3295 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3296 const struct rte_flow_action *action,
3297 const uint64_t item_flags,
3298 struct rte_flow_error *error)
3303 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3305 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3306 MLX5_FLOW_LAYER_INNER_L4 :
3307 MLX5_FLOW_LAYER_OUTER_L4;
3308 if (!(item_flags & layer))
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION,
3311 NULL, "no transport layer "
3318 * Validate the modify-header actions of increment/decrement
3319 * TCP Sequence-number.
3321 * @param[in] action_flags
3322 * Holds the actions detected until now.
3324 * Pointer to the modify action.
3325 * @param[in] item_flags
3326 * Holds the items detected.
3328 * Pointer to error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3335 const struct rte_flow_action *action,
3336 const uint64_t item_flags,
3337 struct rte_flow_error *error)
3342 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3344 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3345 MLX5_FLOW_LAYER_INNER_L4_TCP :
3346 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3347 if (!(item_flags & layer))
3348 return rte_flow_error_set(error, EINVAL,
3349 RTE_FLOW_ERROR_TYPE_ACTION,
3350 NULL, "no TCP item in"
3352 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3353 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3354 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3355 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3356 return rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3359 "cannot decrease and increase"
3360 " TCP sequence number"
3361 " at the same time");
3367 * Validate the modify-header actions of increment/decrement
3368 * TCP Acknowledgment number.
3370 * @param[in] action_flags
3371 * Holds the actions detected until now.
3373 * Pointer to the modify action.
3374 * @param[in] item_flags
3375 * Holds the items detected.
3377 * Pointer to error structure.
3380 * 0 on success, a negative errno value otherwise and rte_errno is set.
3383 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3384 const struct rte_flow_action *action,
3385 const uint64_t item_flags,
3386 struct rte_flow_error *error)
3391 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3393 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3394 MLX5_FLOW_LAYER_INNER_L4_TCP :
3395 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3396 if (!(item_flags & layer))
3397 return rte_flow_error_set(error, EINVAL,
3398 RTE_FLOW_ERROR_TYPE_ACTION,
3399 NULL, "no TCP item in"
3401 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3402 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3403 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3404 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3405 return rte_flow_error_set(error, EINVAL,
3406 RTE_FLOW_ERROR_TYPE_ACTION,
3408 "cannot decrease and increase"
3409 " TCP acknowledgment number"
3410 " at the same time");
3416 * Validate the modify-header TTL actions.
3418 * @param[in] action_flags
3419 * Holds the actions detected until now.
3421 * Pointer to the modify action.
3422 * @param[in] item_flags
3423 * Holds the items detected.
3425 * Pointer to error structure.
3428 * 0 on success, a negative errno value otherwise and rte_errno is set.
3431 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3432 const struct rte_flow_action *action,
3433 const uint64_t item_flags,
3434 struct rte_flow_error *error)
3439 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3441 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3442 MLX5_FLOW_LAYER_INNER_L3 :
3443 MLX5_FLOW_LAYER_OUTER_L3;
3444 if (!(item_flags & layer))
3445 return rte_flow_error_set(error, EINVAL,
3446 RTE_FLOW_ERROR_TYPE_ACTION,
3448 "no IP protocol in pattern");
3454 * Validate jump action.
3457 * Pointer to the jump action.
3458 * @param[in] action_flags
3459 * Holds the actions detected until now.
3460 * @param[in] attributes
3461 * Pointer to flow attributes
3462 * @param[in] external
3463 * Action belongs to flow rule created by request external to PMD.
3465 * Pointer to error structure.
3468 * 0 on success, a negative errno value otherwise and rte_errno is set.
3471 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3472 uint64_t action_flags,
3473 const struct rte_flow_attr *attributes,
3474 bool external, struct rte_flow_error *error)
3476 uint32_t target_group, table;
3479 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3480 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3481 return rte_flow_error_set(error, EINVAL,
3482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3483 "can't have 2 fate actions in"
3485 if (action_flags & MLX5_FLOW_ACTION_METER)
3486 return rte_flow_error_set(error, ENOTSUP,
3487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3488 "jump with meter not support");
3490 return rte_flow_error_set(error, EINVAL,
3491 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3492 NULL, "action configuration not set");
3494 ((const struct rte_flow_action_jump *)action->conf)->group;
3495 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3496 true, &table, error);
3499 if (attributes->group == target_group)
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3502 "target group must be other than"
3503 " the current flow group");
3508 * Validate the port_id action.
3511 * Pointer to rte_eth_dev structure.
3512 * @param[in] action_flags
3513 * Bit-fields that holds the actions detected until now.
3515 * Port_id RTE action structure.
3517 * Attributes of flow that includes this action.
3519 * Pointer to error structure.
3522 * 0 on success, a negative errno value otherwise and rte_errno is set.
3525 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3526 uint64_t action_flags,
3527 const struct rte_flow_action *action,
3528 const struct rte_flow_attr *attr,
3529 struct rte_flow_error *error)
3531 const struct rte_flow_action_port_id *port_id;
3532 struct mlx5_priv *act_priv;
3533 struct mlx5_priv *dev_priv;
3536 if (!attr->transfer)
3537 return rte_flow_error_set(error, ENOTSUP,
3538 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3540 "port id action is valid in transfer"
3542 if (!action || !action->conf)
3543 return rte_flow_error_set(error, ENOTSUP,
3544 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3546 "port id action parameters must be"
3548 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3549 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3550 return rte_flow_error_set(error, EINVAL,
3551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3552 "can have only one fate actions in"
3554 dev_priv = mlx5_dev_to_eswitch_info(dev);
3556 return rte_flow_error_set(error, rte_errno,
3557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3559 "failed to obtain E-Switch info");
3560 port_id = action->conf;
3561 port = port_id->original ? dev->data->port_id : port_id->id;
3562 act_priv = mlx5_port_to_eswitch_info(port, false);
3564 return rte_flow_error_set
3566 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3567 "failed to obtain E-Switch port id for port");
3568 if (act_priv->domain_id != dev_priv->domain_id)
3569 return rte_flow_error_set
3571 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3572 "port does not belong to"
3573 " E-Switch being configured");
3578 * Get the maximum number of modify header actions.
3581 * Pointer to rte_eth_dev structure.
3583 * Flags bits to check if root level.
3586 * Max number of modify header actions device can support.
3589 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3592 * There's no way to directly query the max cap. Although it has to be
3593 * acquried by iterative trial, it is a safe assumption that more
3594 * actions are supported by FW if extensive metadata register is
3595 * supported. (Only in the root table)
3597 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3598 return MLX5_MAX_MODIFY_NUM;
3600 return mlx5_flow_ext_mreg_supported(dev) ?
3601 MLX5_ROOT_TBL_MODIFY_NUM :
3602 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3606 * Validate the meter action.
3609 * Pointer to rte_eth_dev structure.
3610 * @param[in] action_flags
3611 * Bit-fields that holds the actions detected until now.
3613 * Pointer to the meter action.
3615 * Attributes of flow that includes this action.
3617 * Pointer to error structure.
3620 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3623 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3624 uint64_t action_flags,
3625 const struct rte_flow_action *action,
3626 const struct rte_flow_attr *attr,
3627 struct rte_flow_error *error)
3629 struct mlx5_priv *priv = dev->data->dev_private;
3630 const struct rte_flow_action_meter *am = action->conf;
3631 struct mlx5_flow_meter *fm;
3634 return rte_flow_error_set(error, EINVAL,
3635 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3636 "meter action conf is NULL");
3638 if (action_flags & MLX5_FLOW_ACTION_METER)
3639 return rte_flow_error_set(error, ENOTSUP,
3640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3641 "meter chaining not support");
3642 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3643 return rte_flow_error_set(error, ENOTSUP,
3644 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3645 "meter with jump not support");
3647 return rte_flow_error_set(error, ENOTSUP,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3650 "meter action not supported");
3651 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3653 return rte_flow_error_set(error, EINVAL,
3654 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3656 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3657 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3658 (!fm->attr.egress && !attr->egress && attr->ingress))))
3659 return rte_flow_error_set(error, EINVAL,
3660 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3661 "Flow attributes are either invalid "
3662 "or have a conflict with current "
3663 "meter attributes");
3668 * Validate the modify-header IPv4 DSCP actions.
3670 * @param[in] action_flags
3671 * Holds the actions detected until now.
3673 * Pointer to the modify action.
3674 * @param[in] item_flags
3675 * Holds the items detected.
3677 * Pointer to error structure.
3680 * 0 on success, a negative errno value otherwise and rte_errno is set.
3683 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3684 const struct rte_flow_action *action,
3685 const uint64_t item_flags,
3686 struct rte_flow_error *error)
3690 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3692 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3693 return rte_flow_error_set(error, EINVAL,
3694 RTE_FLOW_ERROR_TYPE_ACTION,
3696 "no ipv4 item in pattern");
3702 * Validate the modify-header IPv6 DSCP actions.
3704 * @param[in] action_flags
3705 * Holds the actions detected until now.
3707 * Pointer to the modify action.
3708 * @param[in] item_flags
3709 * Holds the items detected.
3711 * Pointer to error structure.
3714 * 0 on success, a negative errno value otherwise and rte_errno is set.
3717 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3718 const struct rte_flow_action *action,
3719 const uint64_t item_flags,
3720 struct rte_flow_error *error)
3724 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3726 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3727 return rte_flow_error_set(error, EINVAL,
3728 RTE_FLOW_ERROR_TYPE_ACTION,
3730 "no ipv6 item in pattern");
3736 * Find existing modify-header resource or create and register a new one.
3738 * @param dev[in, out]
3739 * Pointer to rte_eth_dev structure.
3740 * @param[in, out] resource
3741 * Pointer to modify-header resource.
3742 * @parm[in, out] dev_flow
3743 * Pointer to the dev_flow.
3745 * pointer to error structure.
3748 * 0 on success otherwise -errno and errno is set.
3751 flow_dv_modify_hdr_resource_register
3752 (struct rte_eth_dev *dev,
3753 struct mlx5_flow_dv_modify_hdr_resource *resource,
3754 struct mlx5_flow *dev_flow,
3755 struct rte_flow_error *error)
3757 struct mlx5_priv *priv = dev->data->dev_private;
3758 struct mlx5_ibv_shared *sh = priv->sh;
3759 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3760 struct mlx5dv_dr_domain *ns;
3761 uint32_t actions_len;
3763 resource->flags = dev_flow->dv.group ? 0 :
3764 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3765 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3767 return rte_flow_error_set(error, EOVERFLOW,
3768 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3769 "too many modify header items");
3770 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3771 ns = sh->fdb_domain;
3772 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3776 /* Lookup a matching resource from cache. */
3777 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3778 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3779 if (resource->ft_type == cache_resource->ft_type &&
3780 resource->actions_num == cache_resource->actions_num &&
3781 resource->flags == cache_resource->flags &&
3782 !memcmp((const void *)resource->actions,
3783 (const void *)cache_resource->actions,
3785 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3786 (void *)cache_resource,
3787 rte_atomic32_read(&cache_resource->refcnt));
3788 rte_atomic32_inc(&cache_resource->refcnt);
3789 dev_flow->handle->dvh.modify_hdr = cache_resource;
3793 /* Register new modify-header resource. */
3794 cache_resource = rte_calloc(__func__, 1,
3795 sizeof(*cache_resource) + actions_len, 0);
3796 if (!cache_resource)
3797 return rte_flow_error_set(error, ENOMEM,
3798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3799 "cannot allocate resource memory");
3800 *cache_resource = *resource;
3801 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3802 cache_resource->verbs_action =
3803 mlx5_glue->dv_create_flow_action_modify_header
3804 (sh->ctx, cache_resource->ft_type, ns,
3805 cache_resource->flags, actions_len,
3806 (uint64_t *)cache_resource->actions);
3807 if (!cache_resource->verbs_action) {
3808 rte_free(cache_resource);
3809 return rte_flow_error_set(error, ENOMEM,
3810 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3811 NULL, "cannot create action");
3813 rte_atomic32_init(&cache_resource->refcnt);
3814 rte_atomic32_inc(&cache_resource->refcnt);
3815 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3816 dev_flow->handle->dvh.modify_hdr = cache_resource;
3817 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3818 (void *)cache_resource,
3819 rte_atomic32_read(&cache_resource->refcnt));
3823 #define MLX5_CNT_CONTAINER_RESIZE 64
3826 * Get or create a flow counter.
3829 * Pointer to the Ethernet device structure.
3831 * Indicate if this counter is shared with other flows.
3833 * Counter identifier.
3836 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3838 static struct mlx5_flow_counter *
3839 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3842 struct mlx5_priv *priv = dev->data->dev_private;
3843 struct mlx5_flow_counter *cnt = NULL;
3844 struct mlx5_devx_obj *dcs = NULL;
3846 if (!priv->config.devx) {
3847 rte_errno = ENOTSUP;
3851 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3852 if (cnt->shared && cnt->id == id) {
3858 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3861 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3863 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3867 struct mlx5_flow_counter tmpl = {
3873 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3875 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3881 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3886 * Release a flow counter.
3889 * Pointer to the Ethernet device structure.
3890 * @param[in] counter
3891 * Pointer to the counter handler.
3894 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3895 struct mlx5_flow_counter *counter)
3897 struct mlx5_priv *priv = dev->data->dev_private;
3901 if (--counter->ref_cnt == 0) {
3902 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3903 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3909 * Query a devx flow counter.
3912 * Pointer to the Ethernet device structure.
3914 * Pointer to the flow counter.
3916 * The statistics value of packets.
3918 * The statistics value of bytes.
3921 * 0 on success, otherwise a negative errno value and rte_errno is set.
3924 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3925 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3928 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3933 * Get a pool by a counter.
3936 * Pointer to the counter.
3941 static struct mlx5_flow_counter_pool *
3942 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3945 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3946 return (struct mlx5_flow_counter_pool *)cnt - 1;
3952 * Get a pool by devx counter ID.
3955 * Pointer to the counter container.
3957 * The counter devx ID.
3960 * The counter pool pointer if exists, NULL otherwise,
3962 static struct mlx5_flow_counter_pool *
3963 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3965 struct mlx5_flow_counter_pool *pool;
3967 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3968 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3969 MLX5_COUNTERS_PER_POOL;
3971 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3978 * Allocate a new memory for the counter values wrapped by all the needed
3982 * Pointer to the Ethernet device structure.
3984 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3987 * The new memory management pointer on success, otherwise NULL and rte_errno
3990 static struct mlx5_counter_stats_mem_mng *
3991 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3993 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3994 (dev->data->dev_private))->sh;
3995 struct mlx5_devx_mkey_attr mkey_attr;
3996 struct mlx5_counter_stats_mem_mng *mem_mng;
3997 volatile struct flow_counter_stats *raw_data;
3998 int size = (sizeof(struct flow_counter_stats) *
3999 MLX5_COUNTERS_PER_POOL +
4000 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4001 sizeof(struct mlx5_counter_stats_mem_mng);
4002 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4009 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4010 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4011 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4012 IBV_ACCESS_LOCAL_WRITE);
4013 if (!mem_mng->umem) {
4018 mkey_attr.addr = (uintptr_t)mem;
4019 mkey_attr.size = size;
4020 mkey_attr.umem_id = mem_mng->umem->umem_id;
4021 mkey_attr.pd = sh->pdn;
4022 mkey_attr.log_entity_size = 0;
4023 mkey_attr.pg_access = 0;
4024 mkey_attr.klm_array = NULL;
4025 mkey_attr.klm_num = 0;
4026 mkey_attr.relaxed_ordering = 1;
4027 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4029 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4034 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4035 raw_data = (volatile struct flow_counter_stats *)mem;
4036 for (i = 0; i < raws_n; ++i) {
4037 mem_mng->raws[i].mem_mng = mem_mng;
4038 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4040 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4045 * Resize a counter container.
4048 * Pointer to the Ethernet device structure.
4050 * Whether the pool is for counter that was allocated by batch command.
4053 * The new container pointer on success, otherwise NULL and rte_errno is set.
4055 static struct mlx5_pools_container *
4056 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4058 struct mlx5_priv *priv = dev->data->dev_private;
4059 struct mlx5_pools_container *cont =
4060 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4061 struct mlx5_pools_container *new_cont =
4062 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4063 struct mlx5_counter_stats_mem_mng *mem_mng;
4064 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4065 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4068 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4069 /* The last resize still hasn't detected by the host thread. */
4073 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4074 if (!new_cont->pools) {
4079 memcpy(new_cont->pools, cont->pools, cont->n *
4080 sizeof(struct mlx5_flow_counter_pool *));
4081 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4082 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4084 rte_free(new_cont->pools);
4087 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4088 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4089 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4091 new_cont->n = resize;
4092 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4093 TAILQ_INIT(&new_cont->pool_list);
4094 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4095 new_cont->init_mem_mng = mem_mng;
4097 /* Flip the master container. */
4098 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4103 * Query a devx flow counter.
4106 * Pointer to the Ethernet device structure.
4108 * Pointer to the flow counter.
4110 * The statistics value of packets.
4112 * The statistics value of bytes.
4115 * 0 on success, otherwise a negative errno value and rte_errno is set.
4118 _flow_dv_query_count(struct rte_eth_dev *dev,
4119 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4122 struct mlx5_priv *priv = dev->data->dev_private;
4123 struct mlx5_flow_counter_pool *pool =
4124 flow_dv_counter_pool_get(cnt);
4125 int offset = cnt - &pool->counters_raw[0];
4127 if (priv->counter_fallback)
4128 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4130 rte_spinlock_lock(&pool->sl);
4132 * The single counters allocation may allocate smaller ID than the
4133 * current allocated in parallel to the host reading.
4134 * In this case the new counter values must be reported as 0.
4136 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4140 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4141 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4143 rte_spinlock_unlock(&pool->sl);
4148 * Create and initialize a new counter pool.
4151 * Pointer to the Ethernet device structure.
4153 * The devX counter handle.
4155 * Whether the pool is for counter that was allocated by batch command.
4156 * @param[in/out] cont_cur
4157 * Pointer to the container pointer, it will be update in pool resize.
4160 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4162 static struct mlx5_pools_container *
4163 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4166 struct mlx5_priv *priv = dev->data->dev_private;
4167 struct mlx5_flow_counter_pool *pool;
4168 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4170 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4173 if (cont->n == n_valid) {
4174 cont = flow_dv_container_resize(dev, batch);
4178 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4179 sizeof(struct mlx5_flow_counter);
4180 pool = rte_calloc(__func__, 1, size, 0);
4185 pool->min_dcs = dcs;
4186 pool->raw = cont->init_mem_mng->raws + n_valid %
4187 MLX5_CNT_CONTAINER_RESIZE;
4188 pool->raw_hw = NULL;
4189 rte_spinlock_init(&pool->sl);
4191 * The generation of the new allocated counters in this pool is 0, 2 in
4192 * the pool generation makes all the counters valid for allocation.
4194 rte_atomic64_set(&pool->query_gen, 0x2);
4195 TAILQ_INIT(&pool->counters);
4196 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4197 cont->pools[n_valid] = pool;
4198 /* Pool initialization must be updated before host thread access. */
4200 rte_atomic16_add(&cont->n_valid, 1);
4205 * Prepare a new counter and/or a new counter pool.
4208 * Pointer to the Ethernet device structure.
4209 * @param[out] cnt_free
4210 * Where to put the pointer of a new counter.
4212 * Whether the pool is for counter that was allocated by batch command.
4215 * The counter container pointer and @p cnt_free is set on success,
4216 * NULL otherwise and rte_errno is set.
4218 static struct mlx5_pools_container *
4219 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4220 struct mlx5_flow_counter **cnt_free,
4223 struct mlx5_priv *priv = dev->data->dev_private;
4224 struct mlx5_pools_container *cont;
4225 struct mlx5_flow_counter_pool *pool;
4226 struct mlx5_devx_obj *dcs = NULL;
4227 struct mlx5_flow_counter *cnt;
4230 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4232 /* bulk_bitmap must be 0 for single counter allocation. */
4233 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4236 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4238 cont = flow_dv_pool_create(dev, dcs, batch);
4240 mlx5_devx_cmd_destroy(dcs);
4243 pool = TAILQ_FIRST(&cont->pool_list);
4244 } else if (dcs->id < pool->min_dcs->id) {
4245 rte_atomic64_set(&pool->a64_dcs,
4246 (int64_t)(uintptr_t)dcs);
4248 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4249 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4254 /* bulk_bitmap is in 128 counters units. */
4255 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4256 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4258 rte_errno = ENODATA;
4261 cont = flow_dv_pool_create(dev, dcs, batch);
4263 mlx5_devx_cmd_destroy(dcs);
4266 pool = TAILQ_FIRST(&cont->pool_list);
4267 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4268 cnt = &pool->counters_raw[i];
4270 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4272 *cnt_free = &pool->counters_raw[0];
4277 * Search for existed shared counter.
4280 * Pointer to the relevant counter pool container.
4282 * The shared counter ID to search.
4285 * NULL if not existed, otherwise pointer to the shared counter.
4287 static struct mlx5_flow_counter *
4288 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4291 static struct mlx5_flow_counter *cnt;
4292 struct mlx5_flow_counter_pool *pool;
4295 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4296 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4297 cnt = &pool->counters_raw[i];
4298 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4306 * Allocate a flow counter.
4309 * Pointer to the Ethernet device structure.
4311 * Indicate if this counter is shared with other flows.
4313 * Counter identifier.
4315 * Counter flow group.
4318 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4320 static struct mlx5_flow_counter *
4321 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4324 struct mlx5_priv *priv = dev->data->dev_private;
4325 struct mlx5_flow_counter_pool *pool = NULL;
4326 struct mlx5_flow_counter *cnt_free = NULL;
4328 * Currently group 0 flow counter cannot be assigned to a flow if it is
4329 * not the first one in the batch counter allocation, so it is better
4330 * to allocate counters one by one for these flows in a separate
4332 * A counter can be shared between different groups so need to take
4333 * shared counters from the single container.
4335 uint32_t batch = (group && !shared) ? 1 : 0;
4336 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4339 if (priv->counter_fallback)
4340 return flow_dv_counter_alloc_fallback(dev, shared, id);
4341 if (!priv->config.devx) {
4342 rte_errno = ENOTSUP;
4346 cnt_free = flow_dv_counter_shared_search(cont, id);
4348 if (cnt_free->ref_cnt + 1 == 0) {
4352 cnt_free->ref_cnt++;
4356 /* Pools which has a free counters are in the start. */
4357 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4359 * The free counter reset values must be updated between the
4360 * counter release to the counter allocation, so, at least one
4361 * query must be done in this time. ensure it by saving the
4362 * query generation in the release time.
4363 * The free list is sorted according to the generation - so if
4364 * the first one is not updated, all the others are not
4367 cnt_free = TAILQ_FIRST(&pool->counters);
4368 if (cnt_free && cnt_free->query_gen + 1 <
4369 rte_atomic64_read(&pool->query_gen))
4374 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4377 pool = TAILQ_FIRST(&cont->pool_list);
4379 cnt_free->batch = batch;
4380 /* Create a DV counter action only in the first time usage. */
4381 if (!cnt_free->action) {
4383 struct mlx5_devx_obj *dcs;
4386 offset = cnt_free - &pool->counters_raw[0];
4387 dcs = pool->min_dcs;
4390 dcs = cnt_free->dcs;
4392 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4394 if (!cnt_free->action) {
4399 /* Update the counter reset values. */
4400 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4403 cnt_free->shared = shared;
4404 cnt_free->ref_cnt = 1;
4406 if (!priv->sh->cmng.query_thread_on)
4407 /* Start the asynchronous batch query by the host thread. */
4408 mlx5_set_query_alarm(priv->sh);
4409 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4410 if (TAILQ_EMPTY(&pool->counters)) {
4411 /* Move the pool to the end of the container pool list. */
4412 TAILQ_REMOVE(&cont->pool_list, pool, next);
4413 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4419 * Release a flow counter.
4422 * Pointer to the Ethernet device structure.
4423 * @param[in] counter
4424 * Pointer to the counter handler.
4427 flow_dv_counter_release(struct rte_eth_dev *dev,
4428 struct mlx5_flow_counter *counter)
4430 struct mlx5_priv *priv = dev->data->dev_private;
4434 if (priv->counter_fallback) {
4435 flow_dv_counter_release_fallback(dev, counter);
4438 if (--counter->ref_cnt == 0) {
4439 struct mlx5_flow_counter_pool *pool =
4440 flow_dv_counter_pool_get(counter);
4442 /* Put the counter in the end - the last updated one. */
4443 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4444 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4449 * Verify the @p attributes will be correctly understood by the NIC and store
4450 * them in the @p flow if everything is correct.
4453 * Pointer to dev struct.
4454 * @param[in] attributes
4455 * Pointer to flow attributes
4456 * @param[in] external
4457 * This flow rule is created by request external to PMD.
4459 * Pointer to error structure.
4462 * 0 on success, a negative errno value otherwise and rte_errno is set.
4465 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4466 const struct rte_flow_attr *attributes,
4467 bool external __rte_unused,
4468 struct rte_flow_error *error)
4470 struct mlx5_priv *priv = dev->data->dev_private;
4471 uint32_t priority_max = priv->config.flow_prio - 1;
4473 #ifndef HAVE_MLX5DV_DR
4474 if (attributes->group)
4475 return rte_flow_error_set(error, ENOTSUP,
4476 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4478 "groups are not supported");
4483 ret = mlx5_flow_group_to_table(attributes, external,
4484 attributes->group, !!priv->fdb_def_rule,
4489 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4490 attributes->priority >= priority_max)
4491 return rte_flow_error_set(error, ENOTSUP,
4492 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4494 "priority out of range");
4495 if (attributes->transfer) {
4496 if (!priv->config.dv_esw_en)
4497 return rte_flow_error_set
4499 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4500 "E-Switch dr is not supported");
4501 if (!(priv->representor || priv->master))
4502 return rte_flow_error_set
4503 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4504 NULL, "E-Switch configuration can only be"
4505 " done by a master or a representor device");
4506 if (attributes->egress)
4507 return rte_flow_error_set
4509 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4510 "egress is not supported");
4512 if (!(attributes->egress ^ attributes->ingress))
4513 return rte_flow_error_set(error, ENOTSUP,
4514 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4515 "must specify exactly one of "
4516 "ingress or egress");
4521 * Internal validation function. For validating both actions and items.
4524 * Pointer to the rte_eth_dev structure.
4526 * Pointer to the flow attributes.
4528 * Pointer to the list of items.
4529 * @param[in] actions
4530 * Pointer to the list of actions.
4531 * @param[in] external
4532 * This flow rule is created by request external to PMD.
4534 * Pointer to the error structure.
4537 * 0 on success, a negative errno value otherwise and rte_errno is set.
4540 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4541 const struct rte_flow_item items[],
4542 const struct rte_flow_action actions[],
4543 bool external, struct rte_flow_error *error)
4546 uint64_t action_flags = 0;
4547 uint64_t item_flags = 0;
4548 uint64_t last_item = 0;
4549 uint8_t next_protocol = 0xff;
4550 uint16_t ether_type = 0;
4552 uint8_t item_ipv6_proto = 0;
4553 const struct rte_flow_item *gre_item = NULL;
4554 const struct rte_flow_action_raw_decap *decap;
4555 const struct rte_flow_action_raw_encap *encap;
4556 const struct rte_flow_action_rss *rss;
4557 const struct rte_flow_item_tcp nic_tcp_mask = {
4560 .src_port = RTE_BE16(UINT16_MAX),
4561 .dst_port = RTE_BE16(UINT16_MAX),
4564 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4566 .src_addr = RTE_BE32(0xffffffff),
4567 .dst_addr = RTE_BE32(0xffffffff),
4568 .type_of_service = 0xff,
4569 .next_proto_id = 0xff,
4570 .time_to_live = 0xff,
4573 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4576 "\xff\xff\xff\xff\xff\xff\xff\xff"
4577 "\xff\xff\xff\xff\xff\xff\xff\xff",
4579 "\xff\xff\xff\xff\xff\xff\xff\xff"
4580 "\xff\xff\xff\xff\xff\xff\xff\xff",
4581 .vtc_flow = RTE_BE32(0xffffffff),
4586 struct mlx5_priv *priv = dev->data->dev_private;
4587 struct mlx5_dev_config *dev_conf = &priv->config;
4588 uint16_t queue_index = 0xFFFF;
4592 ret = flow_dv_validate_attributes(dev, attr, external, error);
4595 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4596 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4597 int type = items->type;
4600 case RTE_FLOW_ITEM_TYPE_VOID:
4602 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4603 ret = flow_dv_validate_item_port_id
4604 (dev, items, attr, item_flags, error);
4607 last_item = MLX5_FLOW_ITEM_PORT_ID;
4609 case RTE_FLOW_ITEM_TYPE_ETH:
4610 ret = mlx5_flow_validate_item_eth(items, item_flags,
4614 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4615 MLX5_FLOW_LAYER_OUTER_L2;
4616 if (items->mask != NULL && items->spec != NULL) {
4618 ((const struct rte_flow_item_eth *)
4621 ((const struct rte_flow_item_eth *)
4623 ether_type = rte_be_to_cpu_16(ether_type);
4628 case RTE_FLOW_ITEM_TYPE_VLAN:
4629 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4633 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4634 MLX5_FLOW_LAYER_OUTER_VLAN;
4635 if (items->mask != NULL && items->spec != NULL) {
4637 ((const struct rte_flow_item_vlan *)
4638 items->spec)->inner_type;
4640 ((const struct rte_flow_item_vlan *)
4641 items->mask)->inner_type;
4642 ether_type = rte_be_to_cpu_16(ether_type);
4647 case RTE_FLOW_ITEM_TYPE_IPV4:
4648 mlx5_flow_tunnel_ip_check(items, next_protocol,
4649 &item_flags, &tunnel);
4650 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4657 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4658 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4659 if (items->mask != NULL &&
4660 ((const struct rte_flow_item_ipv4 *)
4661 items->mask)->hdr.next_proto_id) {
4663 ((const struct rte_flow_item_ipv4 *)
4664 (items->spec))->hdr.next_proto_id;
4666 ((const struct rte_flow_item_ipv4 *)
4667 (items->mask))->hdr.next_proto_id;
4669 /* Reset for inner layer. */
4670 next_protocol = 0xff;
4673 case RTE_FLOW_ITEM_TYPE_IPV6:
4674 mlx5_flow_tunnel_ip_check(items, next_protocol,
4675 &item_flags, &tunnel);
4676 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4683 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4684 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4685 if (items->mask != NULL &&
4686 ((const struct rte_flow_item_ipv6 *)
4687 items->mask)->hdr.proto) {
4689 ((const struct rte_flow_item_ipv6 *)
4690 items->spec)->hdr.proto;
4692 ((const struct rte_flow_item_ipv6 *)
4693 items->spec)->hdr.proto;
4695 ((const struct rte_flow_item_ipv6 *)
4696 items->mask)->hdr.proto;
4698 /* Reset for inner layer. */
4699 next_protocol = 0xff;
4702 case RTE_FLOW_ITEM_TYPE_TCP:
4703 ret = mlx5_flow_validate_item_tcp
4710 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4711 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4713 case RTE_FLOW_ITEM_TYPE_UDP:
4714 ret = mlx5_flow_validate_item_udp(items, item_flags,
4719 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4720 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4722 case RTE_FLOW_ITEM_TYPE_GRE:
4723 ret = mlx5_flow_validate_item_gre(items, item_flags,
4724 next_protocol, error);
4728 last_item = MLX5_FLOW_LAYER_GRE;
4730 case RTE_FLOW_ITEM_TYPE_NVGRE:
4731 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4736 last_item = MLX5_FLOW_LAYER_NVGRE;
4738 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4739 ret = mlx5_flow_validate_item_gre_key
4740 (items, item_flags, gre_item, error);
4743 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4745 case RTE_FLOW_ITEM_TYPE_VXLAN:
4746 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4750 last_item = MLX5_FLOW_LAYER_VXLAN;
4752 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4753 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4758 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4760 case RTE_FLOW_ITEM_TYPE_GENEVE:
4761 ret = mlx5_flow_validate_item_geneve(items,
4766 last_item = MLX5_FLOW_LAYER_GENEVE;
4768 case RTE_FLOW_ITEM_TYPE_MPLS:
4769 ret = mlx5_flow_validate_item_mpls(dev, items,
4774 last_item = MLX5_FLOW_LAYER_MPLS;
4777 case RTE_FLOW_ITEM_TYPE_MARK:
4778 ret = flow_dv_validate_item_mark(dev, items, attr,
4782 last_item = MLX5_FLOW_ITEM_MARK;
4784 case RTE_FLOW_ITEM_TYPE_META:
4785 ret = flow_dv_validate_item_meta(dev, items, attr,
4789 last_item = MLX5_FLOW_ITEM_METADATA;
4791 case RTE_FLOW_ITEM_TYPE_ICMP:
4792 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4797 last_item = MLX5_FLOW_LAYER_ICMP;
4799 case RTE_FLOW_ITEM_TYPE_ICMP6:
4800 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4805 item_ipv6_proto = IPPROTO_ICMPV6;
4806 last_item = MLX5_FLOW_LAYER_ICMP6;
4808 case RTE_FLOW_ITEM_TYPE_TAG:
4809 ret = flow_dv_validate_item_tag(dev, items,
4813 last_item = MLX5_FLOW_ITEM_TAG;
4815 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4816 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4818 case RTE_FLOW_ITEM_TYPE_GTP:
4819 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4823 last_item = MLX5_FLOW_LAYER_GTP;
4826 return rte_flow_error_set(error, ENOTSUP,
4827 RTE_FLOW_ERROR_TYPE_ITEM,
4828 NULL, "item not supported");
4830 item_flags |= last_item;
4832 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4833 int type = actions->type;
4834 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4835 return rte_flow_error_set(error, ENOTSUP,
4836 RTE_FLOW_ERROR_TYPE_ACTION,
4837 actions, "too many actions");
4839 case RTE_FLOW_ACTION_TYPE_VOID:
4841 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4842 ret = flow_dv_validate_action_port_id(dev,
4849 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4852 case RTE_FLOW_ACTION_TYPE_FLAG:
4853 ret = flow_dv_validate_action_flag(dev, action_flags,
4857 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4858 /* Count all modify-header actions as one. */
4859 if (!(action_flags &
4860 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4862 action_flags |= MLX5_FLOW_ACTION_FLAG |
4863 MLX5_FLOW_ACTION_MARK_EXT;
4865 action_flags |= MLX5_FLOW_ACTION_FLAG;
4869 case RTE_FLOW_ACTION_TYPE_MARK:
4870 ret = flow_dv_validate_action_mark(dev, actions,
4875 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4876 /* Count all modify-header actions as one. */
4877 if (!(action_flags &
4878 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4880 action_flags |= MLX5_FLOW_ACTION_MARK |
4881 MLX5_FLOW_ACTION_MARK_EXT;
4883 action_flags |= MLX5_FLOW_ACTION_MARK;
4887 case RTE_FLOW_ACTION_TYPE_SET_META:
4888 ret = flow_dv_validate_action_set_meta(dev, actions,
4893 /* Count all modify-header actions as one action. */
4894 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4896 action_flags |= MLX5_FLOW_ACTION_SET_META;
4898 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4899 ret = flow_dv_validate_action_set_tag(dev, actions,
4904 /* Count all modify-header actions as one action. */
4905 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4907 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4909 case RTE_FLOW_ACTION_TYPE_DROP:
4910 ret = mlx5_flow_validate_action_drop(action_flags,
4914 action_flags |= MLX5_FLOW_ACTION_DROP;
4917 case RTE_FLOW_ACTION_TYPE_QUEUE:
4918 ret = mlx5_flow_validate_action_queue(actions,
4923 queue_index = ((const struct rte_flow_action_queue *)
4924 (actions->conf))->index;
4925 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4928 case RTE_FLOW_ACTION_TYPE_RSS:
4929 rss = actions->conf;
4930 ret = mlx5_flow_validate_action_rss(actions,
4936 if (rss != NULL && rss->queue_num)
4937 queue_index = rss->queue[0];
4938 action_flags |= MLX5_FLOW_ACTION_RSS;
4941 case RTE_FLOW_ACTION_TYPE_COUNT:
4942 ret = flow_dv_validate_action_count(dev, error);
4945 action_flags |= MLX5_FLOW_ACTION_COUNT;
4948 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4949 if (flow_dv_validate_action_pop_vlan(dev,
4955 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4958 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4959 ret = flow_dv_validate_action_push_vlan(dev,
4966 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4969 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4970 ret = flow_dv_validate_action_set_vlan_pcp
4971 (action_flags, actions, error);
4974 /* Count PCP with push_vlan command. */
4975 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4977 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4978 ret = flow_dv_validate_action_set_vlan_vid
4979 (item_flags, action_flags,
4983 /* Count VID with push_vlan command. */
4984 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4986 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4987 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4988 ret = flow_dv_validate_action_l2_encap(dev,
4994 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4997 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4998 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4999 ret = flow_dv_validate_action_decap(dev, action_flags,
5003 action_flags |= MLX5_FLOW_ACTION_DECAP;
5006 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5007 ret = flow_dv_validate_action_raw_encap_decap
5008 (dev, NULL, actions->conf, attr, &action_flags,
5013 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5014 decap = actions->conf;
5015 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5017 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5021 encap = actions->conf;
5023 ret = flow_dv_validate_action_raw_encap_decap
5025 decap ? decap : &empty_decap, encap,
5026 attr, &action_flags, &actions_n,
5031 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5032 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5033 ret = flow_dv_validate_action_modify_mac(action_flags,
5039 /* Count all modify-header actions as one action. */
5040 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5042 action_flags |= actions->type ==
5043 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5044 MLX5_FLOW_ACTION_SET_MAC_SRC :
5045 MLX5_FLOW_ACTION_SET_MAC_DST;
5048 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5049 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5050 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5056 /* Count all modify-header actions as one action. */
5057 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5059 action_flags |= actions->type ==
5060 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5061 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5062 MLX5_FLOW_ACTION_SET_IPV4_DST;
5064 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5065 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5066 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5072 if (item_ipv6_proto == IPPROTO_ICMPV6)
5073 return rte_flow_error_set(error, ENOTSUP,
5074 RTE_FLOW_ERROR_TYPE_ACTION,
5076 "Can't change header "
5077 "with ICMPv6 proto");
5078 /* Count all modify-header actions as one action. */
5079 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5081 action_flags |= actions->type ==
5082 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5083 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5084 MLX5_FLOW_ACTION_SET_IPV6_DST;
5086 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5087 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5088 ret = flow_dv_validate_action_modify_tp(action_flags,
5094 /* Count all modify-header actions as one action. */
5095 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5097 action_flags |= actions->type ==
5098 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5099 MLX5_FLOW_ACTION_SET_TP_SRC :
5100 MLX5_FLOW_ACTION_SET_TP_DST;
5102 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5103 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5104 ret = flow_dv_validate_action_modify_ttl(action_flags,
5110 /* Count all modify-header actions as one action. */
5111 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5113 action_flags |= actions->type ==
5114 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5115 MLX5_FLOW_ACTION_SET_TTL :
5116 MLX5_FLOW_ACTION_DEC_TTL;
5118 case RTE_FLOW_ACTION_TYPE_JUMP:
5119 ret = flow_dv_validate_action_jump(actions,
5126 action_flags |= MLX5_FLOW_ACTION_JUMP;
5128 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5129 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5130 ret = flow_dv_validate_action_modify_tcp_seq
5137 /* Count all modify-header actions as one action. */
5138 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5140 action_flags |= actions->type ==
5141 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5142 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5143 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5145 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5146 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5147 ret = flow_dv_validate_action_modify_tcp_ack
5154 /* Count all modify-header actions as one action. */
5155 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5157 action_flags |= actions->type ==
5158 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5159 MLX5_FLOW_ACTION_INC_TCP_ACK :
5160 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5162 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5163 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5164 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5166 case RTE_FLOW_ACTION_TYPE_METER:
5167 ret = mlx5_flow_validate_action_meter(dev,
5173 action_flags |= MLX5_FLOW_ACTION_METER;
5176 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5177 ret = flow_dv_validate_action_modify_ipv4_dscp
5184 /* Count all modify-header actions as one action. */
5185 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5187 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5189 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5190 ret = flow_dv_validate_action_modify_ipv6_dscp
5197 /* Count all modify-header actions as one action. */
5198 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5200 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5203 return rte_flow_error_set(error, ENOTSUP,
5204 RTE_FLOW_ERROR_TYPE_ACTION,
5206 "action not supported");
5210 * Validate the drop action mutual exclusion with other actions.
5211 * Drop action is mutually-exclusive with any other action, except for
5214 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5215 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5216 return rte_flow_error_set(error, EINVAL,
5217 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5218 "Drop action is mutually-exclusive "
5219 "with any other action, except for "
5221 /* Eswitch has few restrictions on using items and actions */
5222 if (attr->transfer) {
5223 if (!mlx5_flow_ext_mreg_supported(dev) &&
5224 action_flags & MLX5_FLOW_ACTION_FLAG)
5225 return rte_flow_error_set(error, ENOTSUP,
5226 RTE_FLOW_ERROR_TYPE_ACTION,
5228 "unsupported action FLAG");
5229 if (!mlx5_flow_ext_mreg_supported(dev) &&
5230 action_flags & MLX5_FLOW_ACTION_MARK)
5231 return rte_flow_error_set(error, ENOTSUP,
5232 RTE_FLOW_ERROR_TYPE_ACTION,
5234 "unsupported action MARK");
5235 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5236 return rte_flow_error_set(error, ENOTSUP,
5237 RTE_FLOW_ERROR_TYPE_ACTION,
5239 "unsupported action QUEUE");
5240 if (action_flags & MLX5_FLOW_ACTION_RSS)
5241 return rte_flow_error_set(error, ENOTSUP,
5242 RTE_FLOW_ERROR_TYPE_ACTION,
5244 "unsupported action RSS");
5245 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5246 return rte_flow_error_set(error, EINVAL,
5247 RTE_FLOW_ERROR_TYPE_ACTION,
5249 "no fate action is found");
5251 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5252 return rte_flow_error_set(error, EINVAL,
5253 RTE_FLOW_ERROR_TYPE_ACTION,
5255 "no fate action is found");
5257 /* Continue validation for Xcap actions.*/
5258 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5259 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5260 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5261 MLX5_FLOW_XCAP_ACTIONS)
5262 return rte_flow_error_set(error, ENOTSUP,
5263 RTE_FLOW_ERROR_TYPE_ACTION,
5264 NULL, "encap and decap "
5265 "combination aren't supported");
5266 if (!attr->transfer && attr->ingress && (action_flags &
5267 MLX5_FLOW_ACTION_ENCAP))
5268 return rte_flow_error_set(error, ENOTSUP,
5269 RTE_FLOW_ERROR_TYPE_ACTION,
5270 NULL, "encap is not supported"
5271 " for ingress traffic");
5277 * Internal preparation function. Allocates the DV flow size,
5278 * this size is constant.
5281 * Pointer to the rte_eth_dev structure.
5283 * Pointer to the flow attributes.
5285 * Pointer to the list of items.
5286 * @param[in] actions
5287 * Pointer to the list of actions.
5289 * Pointer to the error structure.
5292 * Pointer to mlx5_flow object on success,
5293 * otherwise NULL and rte_errno is set.
5295 static struct mlx5_flow *
5296 flow_dv_prepare(struct rte_eth_dev *dev,
5297 const struct rte_flow_attr *attr __rte_unused,
5298 const struct rte_flow_item items[] __rte_unused,
5299 const struct rte_flow_action actions[] __rte_unused,
5300 struct rte_flow_error *error)
5302 size_t size = sizeof(struct mlx5_flow_handle);
5303 struct mlx5_flow *dev_flow;
5304 struct mlx5_flow_handle *dev_handle;
5305 struct mlx5_priv *priv = dev->data->dev_private;
5307 /* In case of corrupting the memory. */
5308 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5309 rte_flow_error_set(error, ENOSPC,
5310 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5311 "not free temporary device flow");
5314 dev_handle = rte_calloc(__func__, 1, size, 0);
5316 rte_flow_error_set(error, ENOMEM,
5317 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5318 "not enough memory to create flow handle");
5321 /* No multi-thread supporting. */
5322 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5323 dev_flow->handle = dev_handle;
5324 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5326 * The matching value needs to be cleared to 0 before using. In the
5327 * past, it will be automatically cleared when using rte_*alloc
5328 * API. The time consumption will be almost the same as before.
5330 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5331 dev_flow->ingress = attr->ingress;
5332 dev_flow->dv.transfer = attr->transfer;
5336 #ifdef RTE_LIBRTE_MLX5_DEBUG
5338 * Sanity check for match mask and value. Similar to check_valid_spec() in
5339 * kernel driver. If unmasked bit is present in value, it returns failure.
5342 * pointer to match mask buffer.
5343 * @param match_value
5344 * pointer to match value buffer.
5347 * 0 if valid, -EINVAL otherwise.
5350 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5352 uint8_t *m = match_mask;
5353 uint8_t *v = match_value;
5356 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5359 "match_value differs from match_criteria"
5360 " %p[%u] != %p[%u]",
5361 match_value, i, match_mask, i);
5370 * Add Ethernet item to matcher and to the value.
5372 * @param[in, out] matcher
5374 * @param[in, out] key
5375 * Flow matcher value.
5377 * Flow pattern to translate.
5379 * Item is inner pattern.
5382 flow_dv_translate_item_eth(void *matcher, void *key,
5383 const struct rte_flow_item *item, int inner)
5385 const struct rte_flow_item_eth *eth_m = item->mask;
5386 const struct rte_flow_item_eth *eth_v = item->spec;
5387 const struct rte_flow_item_eth nic_mask = {
5388 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5389 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5390 .type = RTE_BE16(0xffff),
5402 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5404 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5406 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5408 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5410 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5411 ð_m->dst, sizeof(eth_m->dst));
5412 /* The value must be in the range of the mask. */
5413 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5414 for (i = 0; i < sizeof(eth_m->dst); ++i)
5415 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5416 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5417 ð_m->src, sizeof(eth_m->src));
5418 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5419 /* The value must be in the range of the mask. */
5420 for (i = 0; i < sizeof(eth_m->dst); ++i)
5421 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5423 /* When ethertype is present set mask for tagged VLAN. */
5424 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5425 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5426 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5427 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5428 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5430 /* Return here to avoid setting match on ethertype. */
5435 * HW supports match on one Ethertype, the Ethertype following the last
5436 * VLAN tag of the packet (see PRM).
5437 * Set match on ethertype only if ETH header is not followed by VLAN.
5439 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5440 rte_be_to_cpu_16(eth_m->type));
5441 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5442 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5446 * Add VLAN item to matcher and to the value.
5448 * @param[in, out] dev_flow
5450 * @param[in, out] matcher
5452 * @param[in, out] key
5453 * Flow matcher value.
5455 * Flow pattern to translate.
5457 * Item is inner pattern.
5460 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5461 void *matcher, void *key,
5462 const struct rte_flow_item *item,
5465 const struct rte_flow_item_vlan *vlan_m = item->mask;
5466 const struct rte_flow_item_vlan *vlan_v = item->spec;
5475 vlan_m = &rte_flow_item_vlan_mask;
5477 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5479 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5481 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5483 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5485 * This is workaround, masks are not supported,
5486 * and pre-validated.
5488 dev_flow->handle->vf_vlan.tag =
5489 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5491 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5492 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5493 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5495 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5497 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5499 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5501 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5502 rte_be_to_cpu_16(vlan_m->inner_type));
5503 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5504 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5508 * Add IPV4 item to matcher and to the value.
5510 * @param[in, out] matcher
5512 * @param[in, out] key
5513 * Flow matcher value.
5515 * Flow pattern to translate.
5516 * @param[in] item_flags
5517 * Bit-fields that holds the items detected until now.
5519 * Item is inner pattern.
5521 * The group to insert the rule.
5524 flow_dv_translate_item_ipv4(void *matcher, void *key,
5525 const struct rte_flow_item *item,
5526 const uint64_t item_flags,
5527 int inner, uint32_t group)
5529 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5530 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5531 const struct rte_flow_item_ipv4 nic_mask = {
5533 .src_addr = RTE_BE32(0xffffffff),
5534 .dst_addr = RTE_BE32(0xffffffff),
5535 .type_of_service = 0xff,
5536 .next_proto_id = 0xff,
5537 .time_to_live = 0xff,
5547 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5549 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5551 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5553 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5556 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5558 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5559 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5561 * On outer header (which must contains L2), or inner header with L2,
5562 * set cvlan_tag mask bit to mark this packet as untagged.
5563 * This should be done even if item->spec is empty.
5565 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5566 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5571 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5572 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5573 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5574 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5575 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5576 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5577 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5578 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5579 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5580 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5581 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5582 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5583 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5584 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5585 ipv4_m->hdr.type_of_service);
5586 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5587 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5588 ipv4_m->hdr.type_of_service >> 2);
5589 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5590 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5591 ipv4_m->hdr.next_proto_id);
5592 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5593 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5594 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5595 ipv4_m->hdr.time_to_live);
5596 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5597 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5601 * Add IPV6 item to matcher and to the value.
5603 * @param[in, out] matcher
5605 * @param[in, out] key
5606 * Flow matcher value.
5608 * Flow pattern to translate.
5609 * @param[in] item_flags
5610 * Bit-fields that holds the items detected until now.
5612 * Item is inner pattern.
5614 * The group to insert the rule.
5617 flow_dv_translate_item_ipv6(void *matcher, void *key,
5618 const struct rte_flow_item *item,
5619 const uint64_t item_flags,
5620 int inner, uint32_t group)
5622 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5623 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5624 const struct rte_flow_item_ipv6 nic_mask = {
5627 "\xff\xff\xff\xff\xff\xff\xff\xff"
5628 "\xff\xff\xff\xff\xff\xff\xff\xff",
5630 "\xff\xff\xff\xff\xff\xff\xff\xff"
5631 "\xff\xff\xff\xff\xff\xff\xff\xff",
5632 .vtc_flow = RTE_BE32(0xffffffff),
5639 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5640 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5649 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5651 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5653 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5655 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5658 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5660 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5663 * On outer header (which must contains L2), or inner header with L2,
5664 * set cvlan_tag mask bit to mark this packet as untagged.
5665 * This should be done even if item->spec is empty.
5667 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5668 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5673 size = sizeof(ipv6_m->hdr.dst_addr);
5674 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5675 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5676 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5677 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5678 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5679 for (i = 0; i < size; ++i)
5680 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5681 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5682 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5683 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5684 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5685 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5686 for (i = 0; i < size; ++i)
5687 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5689 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5690 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5691 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5692 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5693 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5694 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5697 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5699 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5702 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5704 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5708 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5710 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5711 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5713 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5714 ipv6_m->hdr.hop_limits);
5715 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5716 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5720 * Add TCP item to matcher and to the value.
5722 * @param[in, out] matcher
5724 * @param[in, out] key
5725 * Flow matcher value.
5727 * Flow pattern to translate.
5729 * Item is inner pattern.
5732 flow_dv_translate_item_tcp(void *matcher, void *key,
5733 const struct rte_flow_item *item,
5736 const struct rte_flow_item_tcp *tcp_m = item->mask;
5737 const struct rte_flow_item_tcp *tcp_v = item->spec;
5742 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5744 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5746 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5748 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5750 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5751 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5755 tcp_m = &rte_flow_item_tcp_mask;
5756 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5757 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5758 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5759 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5760 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5761 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5762 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5763 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5764 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5765 tcp_m->hdr.tcp_flags);
5766 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5767 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5771 * Add UDP item to matcher and to the value.
5773 * @param[in, out] matcher
5775 * @param[in, out] key
5776 * Flow matcher value.
5778 * Flow pattern to translate.
5780 * Item is inner pattern.
5783 flow_dv_translate_item_udp(void *matcher, void *key,
5784 const struct rte_flow_item *item,
5787 const struct rte_flow_item_udp *udp_m = item->mask;
5788 const struct rte_flow_item_udp *udp_v = item->spec;
5793 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5795 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5797 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5799 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5801 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5802 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5806 udp_m = &rte_flow_item_udp_mask;
5807 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5808 rte_be_to_cpu_16(udp_m->hdr.src_port));
5809 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5810 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5811 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5812 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5813 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5814 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5818 * Add GRE optional Key item to matcher and to the value.
5820 * @param[in, out] matcher
5822 * @param[in, out] key
5823 * Flow matcher value.
5825 * Flow pattern to translate.
5827 * Item is inner pattern.
5830 flow_dv_translate_item_gre_key(void *matcher, void *key,
5831 const struct rte_flow_item *item)
5833 const rte_be32_t *key_m = item->mask;
5834 const rte_be32_t *key_v = item->spec;
5835 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5836 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5837 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5839 /* GRE K bit must be on and should already be validated */
5840 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5841 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5845 key_m = &gre_key_default_mask;
5846 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5847 rte_be_to_cpu_32(*key_m) >> 8);
5848 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5849 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5850 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5851 rte_be_to_cpu_32(*key_m) & 0xFF);
5852 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5853 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5857 * Add GRE item to matcher and to the value.
5859 * @param[in, out] matcher
5861 * @param[in, out] key
5862 * Flow matcher value.
5864 * Flow pattern to translate.
5866 * Item is inner pattern.
5869 flow_dv_translate_item_gre(void *matcher, void *key,
5870 const struct rte_flow_item *item,
5873 const struct rte_flow_item_gre *gre_m = item->mask;
5874 const struct rte_flow_item_gre *gre_v = item->spec;
5877 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5878 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5885 uint16_t s_present:1;
5886 uint16_t k_present:1;
5887 uint16_t rsvd_bit1:1;
5888 uint16_t c_present:1;
5892 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5895 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5897 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5899 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5901 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5903 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5904 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5908 gre_m = &rte_flow_item_gre_mask;
5909 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5910 rte_be_to_cpu_16(gre_m->protocol));
5911 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5912 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5913 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5914 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5915 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5916 gre_crks_rsvd0_ver_m.c_present);
5917 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5918 gre_crks_rsvd0_ver_v.c_present &
5919 gre_crks_rsvd0_ver_m.c_present);
5920 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5921 gre_crks_rsvd0_ver_m.k_present);
5922 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5923 gre_crks_rsvd0_ver_v.k_present &
5924 gre_crks_rsvd0_ver_m.k_present);
5925 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5926 gre_crks_rsvd0_ver_m.s_present);
5927 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5928 gre_crks_rsvd0_ver_v.s_present &
5929 gre_crks_rsvd0_ver_m.s_present);
5933 * Add NVGRE item to matcher and to the value.
5935 * @param[in, out] matcher
5937 * @param[in, out] key
5938 * Flow matcher value.
5940 * Flow pattern to translate.
5942 * Item is inner pattern.
5945 flow_dv_translate_item_nvgre(void *matcher, void *key,
5946 const struct rte_flow_item *item,
5949 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5950 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5951 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5952 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5953 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5954 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5960 /* For NVGRE, GRE header fields must be set with defined values. */
5961 const struct rte_flow_item_gre gre_spec = {
5962 .c_rsvd0_ver = RTE_BE16(0x2000),
5963 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5965 const struct rte_flow_item_gre gre_mask = {
5966 .c_rsvd0_ver = RTE_BE16(0xB000),
5967 .protocol = RTE_BE16(UINT16_MAX),
5969 const struct rte_flow_item gre_item = {
5974 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5978 nvgre_m = &rte_flow_item_nvgre_mask;
5979 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5980 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5981 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5982 memcpy(gre_key_m, tni_flow_id_m, size);
5983 for (i = 0; i < size; ++i)
5984 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5988 * Add VXLAN item to matcher and to the value.
5990 * @param[in, out] matcher
5992 * @param[in, out] key
5993 * Flow matcher value.
5995 * Flow pattern to translate.
5997 * Item is inner pattern.
6000 flow_dv_translate_item_vxlan(void *matcher, void *key,
6001 const struct rte_flow_item *item,
6004 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6005 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6008 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6009 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6017 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6019 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6021 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6023 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6025 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6026 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6027 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6028 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6029 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6034 vxlan_m = &rte_flow_item_vxlan_mask;
6035 size = sizeof(vxlan_m->vni);
6036 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6037 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6038 memcpy(vni_m, vxlan_m->vni, size);
6039 for (i = 0; i < size; ++i)
6040 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6044 * Add VXLAN-GPE item to matcher and to the value.
6046 * @param[in, out] matcher
6048 * @param[in, out] key
6049 * Flow matcher value.
6051 * Flow pattern to translate.
6053 * Item is inner pattern.
6057 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6058 const struct rte_flow_item *item, int inner)
6060 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6061 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6065 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6067 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6073 uint8_t flags_m = 0xff;
6074 uint8_t flags_v = 0xc;
6077 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6079 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6081 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6083 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6085 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6086 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6087 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6088 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6089 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6094 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6095 size = sizeof(vxlan_m->vni);
6096 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6097 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6098 memcpy(vni_m, vxlan_m->vni, size);
6099 for (i = 0; i < size; ++i)
6100 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6101 if (vxlan_m->flags) {
6102 flags_m = vxlan_m->flags;
6103 flags_v = vxlan_v->flags;
6105 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6106 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6107 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6109 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6114 * Add Geneve item to matcher and to the value.
6116 * @param[in, out] matcher
6118 * @param[in, out] key
6119 * Flow matcher value.
6121 * Flow pattern to translate.
6123 * Item is inner pattern.
6127 flow_dv_translate_item_geneve(void *matcher, void *key,
6128 const struct rte_flow_item *item, int inner)
6130 const struct rte_flow_item_geneve *geneve_m = item->mask;
6131 const struct rte_flow_item_geneve *geneve_v = item->spec;
6134 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6135 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6144 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6146 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6148 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6150 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6152 dport = MLX5_UDP_PORT_GENEVE;
6153 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6154 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6155 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6160 geneve_m = &rte_flow_item_geneve_mask;
6161 size = sizeof(geneve_m->vni);
6162 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6163 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6164 memcpy(vni_m, geneve_m->vni, size);
6165 for (i = 0; i < size; ++i)
6166 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6167 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6168 rte_be_to_cpu_16(geneve_m->protocol));
6169 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6170 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6171 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6172 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6173 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6174 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6175 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6176 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6177 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6178 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6179 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6180 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6181 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6185 * Add MPLS item to matcher and to the value.
6187 * @param[in, out] matcher
6189 * @param[in, out] key
6190 * Flow matcher value.
6192 * Flow pattern to translate.
6193 * @param[in] prev_layer
6194 * The protocol layer indicated in previous item.
6196 * Item is inner pattern.
6199 flow_dv_translate_item_mpls(void *matcher, void *key,
6200 const struct rte_flow_item *item,
6201 uint64_t prev_layer,
6204 const uint32_t *in_mpls_m = item->mask;
6205 const uint32_t *in_mpls_v = item->spec;
6206 uint32_t *out_mpls_m = 0;
6207 uint32_t *out_mpls_v = 0;
6208 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6209 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6210 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6212 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6213 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6214 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6216 switch (prev_layer) {
6217 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6218 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6219 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6220 MLX5_UDP_PORT_MPLS);
6222 case MLX5_FLOW_LAYER_GRE:
6223 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6224 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6225 RTE_ETHER_TYPE_MPLS);
6228 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6229 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6236 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6237 switch (prev_layer) {
6238 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6240 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6241 outer_first_mpls_over_udp);
6243 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6244 outer_first_mpls_over_udp);
6246 case MLX5_FLOW_LAYER_GRE:
6248 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6249 outer_first_mpls_over_gre);
6251 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6252 outer_first_mpls_over_gre);
6255 /* Inner MPLS not over GRE is not supported. */
6258 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6262 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6268 if (out_mpls_m && out_mpls_v) {
6269 *out_mpls_m = *in_mpls_m;
6270 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6275 * Add metadata register item to matcher
6277 * @param[in, out] matcher
6279 * @param[in, out] key
6280 * Flow matcher value.
6281 * @param[in] reg_type
6282 * Type of device metadata register
6289 flow_dv_match_meta_reg(void *matcher, void *key,
6290 enum modify_reg reg_type,
6291 uint32_t data, uint32_t mask)
6294 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6296 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6302 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6303 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6306 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6307 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6311 * The metadata register C0 field might be divided into
6312 * source vport index and META item value, we should set
6313 * this field according to specified mask, not as whole one.
6315 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6317 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6318 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6321 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6324 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6325 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6328 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6329 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6332 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6333 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6336 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6337 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6340 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6341 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6344 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6345 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6348 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6349 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6358 * Add MARK item to matcher
6361 * The device to configure through.
6362 * @param[in, out] matcher
6364 * @param[in, out] key
6365 * Flow matcher value.
6367 * Flow pattern to translate.
6370 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6371 void *matcher, void *key,
6372 const struct rte_flow_item *item)
6374 struct mlx5_priv *priv = dev->data->dev_private;
6375 const struct rte_flow_item_mark *mark;
6379 mark = item->mask ? (const void *)item->mask :
6380 &rte_flow_item_mark_mask;
6381 mask = mark->id & priv->sh->dv_mark_mask;
6382 mark = (const void *)item->spec;
6384 value = mark->id & priv->sh->dv_mark_mask & mask;
6386 enum modify_reg reg;
6388 /* Get the metadata register index for the mark. */
6389 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6390 MLX5_ASSERT(reg > 0);
6391 if (reg == REG_C_0) {
6392 struct mlx5_priv *priv = dev->data->dev_private;
6393 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6394 uint32_t shl_c0 = rte_bsf32(msk_c0);
6400 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6405 * Add META item to matcher
6408 * The devich to configure through.
6409 * @param[in, out] matcher
6411 * @param[in, out] key
6412 * Flow matcher value.
6414 * Attributes of flow that includes this item.
6416 * Flow pattern to translate.
6419 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6420 void *matcher, void *key,
6421 const struct rte_flow_attr *attr,
6422 const struct rte_flow_item *item)
6424 const struct rte_flow_item_meta *meta_m;
6425 const struct rte_flow_item_meta *meta_v;
6427 meta_m = (const void *)item->mask;
6429 meta_m = &rte_flow_item_meta_mask;
6430 meta_v = (const void *)item->spec;
6433 uint32_t value = meta_v->data;
6434 uint32_t mask = meta_m->data;
6436 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6440 * In datapath code there is no endianness
6441 * coversions for perfromance reasons, all
6442 * pattern conversions are done in rte_flow.
6444 value = rte_cpu_to_be_32(value);
6445 mask = rte_cpu_to_be_32(mask);
6446 if (reg == REG_C_0) {
6447 struct mlx5_priv *priv = dev->data->dev_private;
6448 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6449 uint32_t shl_c0 = rte_bsf32(msk_c0);
6450 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6451 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6458 MLX5_ASSERT(msk_c0);
6459 MLX5_ASSERT(!(~msk_c0 & mask));
6461 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6466 * Add vport metadata Reg C0 item to matcher
6468 * @param[in, out] matcher
6470 * @param[in, out] key
6471 * Flow matcher value.
6473 * Flow pattern to translate.
6476 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6477 uint32_t value, uint32_t mask)
6479 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6483 * Add tag item to matcher
6486 * The devich to configure through.
6487 * @param[in, out] matcher
6489 * @param[in, out] key
6490 * Flow matcher value.
6492 * Flow pattern to translate.
6495 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6496 void *matcher, void *key,
6497 const struct rte_flow_item *item)
6499 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6500 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6501 uint32_t mask, value;
6504 value = tag_v->data;
6505 mask = tag_m ? tag_m->data : UINT32_MAX;
6506 if (tag_v->id == REG_C_0) {
6507 struct mlx5_priv *priv = dev->data->dev_private;
6508 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6509 uint32_t shl_c0 = rte_bsf32(msk_c0);
6515 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6519 * Add TAG item to matcher
6522 * The devich to configure through.
6523 * @param[in, out] matcher
6525 * @param[in, out] key
6526 * Flow matcher value.
6528 * Flow pattern to translate.
6531 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6532 void *matcher, void *key,
6533 const struct rte_flow_item *item)
6535 const struct rte_flow_item_tag *tag_v = item->spec;
6536 const struct rte_flow_item_tag *tag_m = item->mask;
6537 enum modify_reg reg;
6540 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6541 /* Get the metadata register index for the tag. */
6542 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6543 MLX5_ASSERT(reg > 0);
6544 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6548 * Add source vport match to the specified matcher.
6550 * @param[in, out] matcher
6552 * @param[in, out] key
6553 * Flow matcher value.
6555 * Source vport value to match
6560 flow_dv_translate_item_source_vport(void *matcher, void *key,
6561 int16_t port, uint16_t mask)
6563 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6564 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6566 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6567 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6571 * Translate port-id item to eswitch match on port-id.
6574 * The devich to configure through.
6575 * @param[in, out] matcher
6577 * @param[in, out] key
6578 * Flow matcher value.
6580 * Flow pattern to translate.
6583 * 0 on success, a negative errno value otherwise.
6586 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6587 void *key, const struct rte_flow_item *item)
6589 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6590 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6591 struct mlx5_priv *priv;
6594 mask = pid_m ? pid_m->id : 0xffff;
6595 id = pid_v ? pid_v->id : dev->data->port_id;
6596 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6599 /* Translate to vport field or to metadata, depending on mode. */
6600 if (priv->vport_meta_mask)
6601 flow_dv_translate_item_meta_vport(matcher, key,
6602 priv->vport_meta_tag,
6603 priv->vport_meta_mask);
6605 flow_dv_translate_item_source_vport(matcher, key,
6606 priv->vport_id, mask);
6611 * Add ICMP6 item to matcher and to the value.
6613 * @param[in, out] matcher
6615 * @param[in, out] key
6616 * Flow matcher value.
6618 * Flow pattern to translate.
6620 * Item is inner pattern.
6623 flow_dv_translate_item_icmp6(void *matcher, void *key,
6624 const struct rte_flow_item *item,
6627 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6628 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6631 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6633 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6635 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6637 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6639 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6641 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6643 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6644 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6648 icmp6_m = &rte_flow_item_icmp6_mask;
6650 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6651 * If only the protocol is specified, no need to match the frag.
6653 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6654 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6655 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6656 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6657 icmp6_v->type & icmp6_m->type);
6658 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6659 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6660 icmp6_v->code & icmp6_m->code);
6664 * Add ICMP item to matcher and to the value.
6666 * @param[in, out] matcher
6668 * @param[in, out] key
6669 * Flow matcher value.
6671 * Flow pattern to translate.
6673 * Item is inner pattern.
6676 flow_dv_translate_item_icmp(void *matcher, void *key,
6677 const struct rte_flow_item *item,
6680 const struct rte_flow_item_icmp *icmp_m = item->mask;
6681 const struct rte_flow_item_icmp *icmp_v = item->spec;
6684 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6686 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6688 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6690 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6692 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6694 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6696 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6697 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6701 icmp_m = &rte_flow_item_icmp_mask;
6703 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6704 * If only the protocol is specified, no need to match the frag.
6706 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6707 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6708 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6709 icmp_m->hdr.icmp_type);
6710 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6711 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6712 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6713 icmp_m->hdr.icmp_code);
6714 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6715 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6719 * Add GTP item to matcher and to the value.
6721 * @param[in, out] matcher
6723 * @param[in, out] key
6724 * Flow matcher value.
6726 * Flow pattern to translate.
6728 * Item is inner pattern.
6731 flow_dv_translate_item_gtp(void *matcher, void *key,
6732 const struct rte_flow_item *item, int inner)
6734 const struct rte_flow_item_gtp *gtp_m = item->mask;
6735 const struct rte_flow_item_gtp *gtp_v = item->spec;
6738 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6740 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6741 uint16_t dport = RTE_GTPU_UDP_PORT;
6744 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6746 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6748 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6750 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6752 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6753 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6754 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6759 gtp_m = &rte_flow_item_gtp_mask;
6760 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6761 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6762 gtp_v->msg_type & gtp_m->msg_type);
6763 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6764 rte_be_to_cpu_32(gtp_m->teid));
6765 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6766 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6769 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6771 #define HEADER_IS_ZERO(match_criteria, headers) \
6772 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6773 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6776 * Calculate flow matcher enable bitmap.
6778 * @param match_criteria
6779 * Pointer to flow matcher criteria.
6782 * Bitmap of enabled fields.
6785 flow_dv_matcher_enable(uint32_t *match_criteria)
6787 uint8_t match_criteria_enable;
6789 match_criteria_enable =
6790 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6791 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6792 match_criteria_enable |=
6793 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6794 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6795 match_criteria_enable |=
6796 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6797 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6798 match_criteria_enable |=
6799 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6800 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6801 match_criteria_enable |=
6802 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6803 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6804 return match_criteria_enable;
6811 * @param[in, out] dev
6812 * Pointer to rte_eth_dev structure.
6813 * @param[in] table_id
6816 * Direction of the table.
6817 * @param[in] transfer
6818 * E-Switch or NIC flow.
6820 * pointer to error structure.
6823 * Returns tables resource based on the index, NULL in case of failed.
6825 static struct mlx5_flow_tbl_resource *
6826 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6827 uint32_t table_id, uint8_t egress,
6829 struct rte_flow_error *error)
6831 struct mlx5_priv *priv = dev->data->dev_private;
6832 struct mlx5_ibv_shared *sh = priv->sh;
6833 struct mlx5_flow_tbl_resource *tbl;
6834 union mlx5_flow_tbl_key table_key = {
6836 .table_id = table_id,
6838 .domain = !!transfer,
6839 .direction = !!egress,
6842 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6844 struct mlx5_flow_tbl_data_entry *tbl_data;
6849 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6851 tbl = &tbl_data->tbl;
6852 rte_atomic32_inc(&tbl->refcnt);
6855 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6857 rte_flow_error_set(error, ENOMEM,
6858 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6860 "cannot allocate flow table data entry");
6863 tbl = &tbl_data->tbl;
6864 pos = &tbl_data->entry;
6866 domain = sh->fdb_domain;
6868 domain = sh->tx_domain;
6870 domain = sh->rx_domain;
6871 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6873 rte_flow_error_set(error, ENOMEM,
6874 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6875 NULL, "cannot create flow table object");
6880 * No multi-threads now, but still better to initialize the reference
6881 * count before insert it into the hash list.
6883 rte_atomic32_init(&tbl->refcnt);
6884 /* Jump action reference count is initialized here. */
6885 rte_atomic32_init(&tbl_data->jump.refcnt);
6886 pos->key = table_key.v64;
6887 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6889 rte_flow_error_set(error, -ret,
6890 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6891 "cannot insert flow table data entry");
6892 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6895 rte_atomic32_inc(&tbl->refcnt);
6900 * Release a flow table.
6903 * Pointer to rte_eth_dev structure.
6905 * Table resource to be released.
6908 * Returns 0 if table was released, else return 1;
6911 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6912 struct mlx5_flow_tbl_resource *tbl)
6914 struct mlx5_priv *priv = dev->data->dev_private;
6915 struct mlx5_ibv_shared *sh = priv->sh;
6916 struct mlx5_flow_tbl_data_entry *tbl_data =
6917 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6921 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6922 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6924 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6926 /* remove the entry from the hash list and free memory. */
6927 mlx5_hlist_remove(sh->flow_tbls, pos);
6935 * Register the flow matcher.
6937 * @param[in, out] dev
6938 * Pointer to rte_eth_dev structure.
6939 * @param[in, out] matcher
6940 * Pointer to flow matcher.
6941 * @param[in, out] key
6942 * Pointer to flow table key.
6943 * @parm[in, out] dev_flow
6944 * Pointer to the dev_flow.
6946 * pointer to error structure.
6949 * 0 on success otherwise -errno and errno is set.
6952 flow_dv_matcher_register(struct rte_eth_dev *dev,
6953 struct mlx5_flow_dv_matcher *matcher,
6954 union mlx5_flow_tbl_key *key,
6955 struct mlx5_flow *dev_flow,
6956 struct rte_flow_error *error)
6958 struct mlx5_priv *priv = dev->data->dev_private;
6959 struct mlx5_ibv_shared *sh = priv->sh;
6960 struct mlx5_flow_dv_matcher *cache_matcher;
6961 struct mlx5dv_flow_matcher_attr dv_attr = {
6962 .type = IBV_FLOW_ATTR_NORMAL,
6963 .match_mask = (void *)&matcher->mask,
6965 struct mlx5_flow_tbl_resource *tbl;
6966 struct mlx5_flow_tbl_data_entry *tbl_data;
6968 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6969 key->domain, error);
6971 return -rte_errno; /* No need to refill the error info */
6972 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6973 /* Lookup from cache. */
6974 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6975 if (matcher->crc == cache_matcher->crc &&
6976 matcher->priority == cache_matcher->priority &&
6977 !memcmp((const void *)matcher->mask.buf,
6978 (const void *)cache_matcher->mask.buf,
6979 cache_matcher->mask.size)) {
6981 "%s group %u priority %hd use %s "
6982 "matcher %p: refcnt %d++",
6983 key->domain ? "FDB" : "NIC", key->table_id,
6984 cache_matcher->priority,
6985 key->direction ? "tx" : "rx",
6986 (void *)cache_matcher,
6987 rte_atomic32_read(&cache_matcher->refcnt));
6988 rte_atomic32_inc(&cache_matcher->refcnt);
6989 dev_flow->handle->dvh.matcher = cache_matcher;
6990 /* old matcher should not make the table ref++. */
6991 flow_dv_tbl_resource_release(dev, tbl);
6995 /* Register new matcher. */
6996 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6997 if (!cache_matcher) {
6998 flow_dv_tbl_resource_release(dev, tbl);
6999 return rte_flow_error_set(error, ENOMEM,
7000 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7001 "cannot allocate matcher memory");
7003 *cache_matcher = *matcher;
7004 dv_attr.match_criteria_enable =
7005 flow_dv_matcher_enable(cache_matcher->mask.buf);
7006 dv_attr.priority = matcher->priority;
7008 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7009 cache_matcher->matcher_object =
7010 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7011 if (!cache_matcher->matcher_object) {
7012 rte_free(cache_matcher);
7013 #ifdef HAVE_MLX5DV_DR
7014 flow_dv_tbl_resource_release(dev, tbl);
7016 return rte_flow_error_set(error, ENOMEM,
7017 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7018 NULL, "cannot create matcher");
7020 /* Save the table information */
7021 cache_matcher->tbl = tbl;
7022 rte_atomic32_init(&cache_matcher->refcnt);
7023 /* only matcher ref++, table ref++ already done above in get API. */
7024 rte_atomic32_inc(&cache_matcher->refcnt);
7025 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7026 dev_flow->handle->dvh.matcher = cache_matcher;
7027 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7028 key->domain ? "FDB" : "NIC", key->table_id,
7029 cache_matcher->priority,
7030 key->direction ? "tx" : "rx", (void *)cache_matcher,
7031 rte_atomic32_read(&cache_matcher->refcnt));
7036 * Find existing tag resource or create and register a new one.
7038 * @param dev[in, out]
7039 * Pointer to rte_eth_dev structure.
7040 * @param[in, out] tag_be24
7041 * Tag value in big endian then R-shift 8.
7042 * @parm[in, out] dev_flow
7043 * Pointer to the dev_flow.
7045 * pointer to error structure.
7048 * 0 on success otherwise -errno and errno is set.
7051 flow_dv_tag_resource_register
7052 (struct rte_eth_dev *dev,
7054 struct mlx5_flow *dev_flow,
7055 struct rte_flow_error *error)
7057 struct mlx5_priv *priv = dev->data->dev_private;
7058 struct mlx5_ibv_shared *sh = priv->sh;
7059 struct mlx5_flow_dv_tag_resource *cache_resource;
7060 struct mlx5_hlist_entry *entry;
7062 /* Lookup a matching resource from cache. */
7063 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7065 cache_resource = container_of
7066 (entry, struct mlx5_flow_dv_tag_resource, entry);
7067 rte_atomic32_inc(&cache_resource->refcnt);
7068 dev_flow->handle->dvh.tag_resource = cache_resource;
7069 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7070 (void *)cache_resource,
7071 rte_atomic32_read(&cache_resource->refcnt));
7074 /* Register new resource. */
7075 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7076 if (!cache_resource)
7077 return rte_flow_error_set(error, ENOMEM,
7078 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7079 "cannot allocate resource memory");
7080 cache_resource->entry.key = (uint64_t)tag_be24;
7081 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7082 if (!cache_resource->action) {
7083 rte_free(cache_resource);
7084 return rte_flow_error_set(error, ENOMEM,
7085 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7086 NULL, "cannot create action");
7088 rte_atomic32_init(&cache_resource->refcnt);
7089 rte_atomic32_inc(&cache_resource->refcnt);
7090 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7091 mlx5_glue->destroy_flow_action(cache_resource->action);
7092 rte_free(cache_resource);
7093 return rte_flow_error_set(error, EEXIST,
7094 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7095 NULL, "cannot insert tag");
7097 dev_flow->handle->dvh.tag_resource = cache_resource;
7098 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7099 (void *)cache_resource,
7100 rte_atomic32_read(&cache_resource->refcnt));
7108 * Pointer to Ethernet device.
7110 * Pointer to mlx5_flow.
7113 * 1 while a reference on it exists, 0 when freed.
7116 flow_dv_tag_release(struct rte_eth_dev *dev,
7117 struct mlx5_flow_dv_tag_resource *tag)
7119 struct mlx5_priv *priv = dev->data->dev_private;
7120 struct mlx5_ibv_shared *sh = priv->sh;
7123 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7124 dev->data->port_id, (void *)tag,
7125 rte_atomic32_read(&tag->refcnt));
7126 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7127 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7128 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7129 DRV_LOG(DEBUG, "port %u tag %p: removed",
7130 dev->data->port_id, (void *)tag);
7138 * Translate port ID action to vport.
7141 * Pointer to rte_eth_dev structure.
7143 * Pointer to the port ID action.
7144 * @param[out] dst_port_id
7145 * The target port ID.
7147 * Pointer to the error structure.
7150 * 0 on success, a negative errno value otherwise and rte_errno is set.
7153 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7154 const struct rte_flow_action *action,
7155 uint32_t *dst_port_id,
7156 struct rte_flow_error *error)
7159 struct mlx5_priv *priv;
7160 const struct rte_flow_action_port_id *conf =
7161 (const struct rte_flow_action_port_id *)action->conf;
7163 port = conf->original ? dev->data->port_id : conf->id;
7164 priv = mlx5_port_to_eswitch_info(port, false);
7166 return rte_flow_error_set(error, -rte_errno,
7167 RTE_FLOW_ERROR_TYPE_ACTION,
7169 "No eswitch info was found for port");
7170 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7172 * This parameter is transferred to
7173 * mlx5dv_dr_action_create_dest_ib_port().
7175 *dst_port_id = priv->ibv_port;
7178 * Legacy mode, no LAG configurations is supported.
7179 * This parameter is transferred to
7180 * mlx5dv_dr_action_create_dest_vport().
7182 *dst_port_id = priv->vport_id;
7188 * Add Tx queue matcher
7191 * Pointer to the dev struct.
7192 * @param[in, out] matcher
7194 * @param[in, out] key
7195 * Flow matcher value.
7197 * Flow pattern to translate.
7199 * Item is inner pattern.
7202 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7203 void *matcher, void *key,
7204 const struct rte_flow_item *item)
7206 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7207 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7209 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7211 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7212 struct mlx5_txq_ctrl *txq;
7216 queue_m = (const void *)item->mask;
7219 queue_v = (const void *)item->spec;
7222 txq = mlx5_txq_get(dev, queue_v->queue);
7225 queue = txq->obj->sq->id;
7226 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7227 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7228 queue & queue_m->queue);
7229 mlx5_txq_release(dev, queue_v->queue);
7233 * Set the hash fields according to the @p flow information.
7235 * @param[in] dev_flow
7236 * Pointer to the mlx5_flow.
7239 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7241 struct rte_flow *flow = dev_flow->flow;
7242 uint64_t items = dev_flow->handle->layers;
7244 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7246 dev_flow->hash_fields = 0;
7247 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7248 if (flow->rss.level >= 2) {
7249 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7253 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7254 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7255 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7256 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7257 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7258 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7259 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7261 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7263 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7264 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7265 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7266 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7267 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7268 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7269 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7271 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7274 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7275 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7276 if (rss_types & ETH_RSS_UDP) {
7277 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7278 dev_flow->hash_fields |=
7279 IBV_RX_HASH_SRC_PORT_UDP;
7280 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7281 dev_flow->hash_fields |=
7282 IBV_RX_HASH_DST_PORT_UDP;
7284 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7286 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7287 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7288 if (rss_types & ETH_RSS_TCP) {
7289 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7290 dev_flow->hash_fields |=
7291 IBV_RX_HASH_SRC_PORT_TCP;
7292 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7293 dev_flow->hash_fields |=
7294 IBV_RX_HASH_DST_PORT_TCP;
7296 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7302 * Fill the flow with DV spec, lock free
7303 * (mutex should be acquired by caller).
7306 * Pointer to rte_eth_dev structure.
7307 * @param[in, out] dev_flow
7308 * Pointer to the sub flow.
7310 * Pointer to the flow attributes.
7312 * Pointer to the list of items.
7313 * @param[in] actions
7314 * Pointer to the list of actions.
7316 * Pointer to the error structure.
7319 * 0 on success, a negative errno value otherwise and rte_errno is set.
7322 __flow_dv_translate(struct rte_eth_dev *dev,
7323 struct mlx5_flow *dev_flow,
7324 const struct rte_flow_attr *attr,
7325 const struct rte_flow_item items[],
7326 const struct rte_flow_action actions[],
7327 struct rte_flow_error *error)
7329 struct mlx5_priv *priv = dev->data->dev_private;
7330 struct mlx5_dev_config *dev_conf = &priv->config;
7331 struct rte_flow *flow = dev_flow->flow;
7332 struct mlx5_flow_handle *handle = dev_flow->handle;
7333 uint64_t item_flags = 0;
7334 uint64_t last_item = 0;
7335 uint64_t action_flags = 0;
7336 uint64_t priority = attr->priority;
7337 struct mlx5_flow_dv_matcher matcher = {
7339 .size = sizeof(matcher.mask.buf),
7343 bool actions_end = false;
7345 struct mlx5_flow_dv_modify_hdr_resource res;
7346 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7347 sizeof(struct mlx5_modification_cmd) *
7348 (MLX5_MAX_MODIFY_NUM + 1)];
7350 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7351 union flow_dv_attr flow_attr = { .attr = 0 };
7353 union mlx5_flow_tbl_key tbl_key;
7354 uint32_t modify_action_position = UINT32_MAX;
7355 void *match_mask = matcher.mask.buf;
7356 void *match_value = dev_flow->dv.value.buf;
7357 uint8_t next_protocol = 0xff;
7358 struct rte_vlan_hdr vlan = { 0 };
7362 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7363 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7364 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7365 !!priv->fdb_def_rule, &table, error);
7368 dev_flow->dv.group = table;
7370 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7371 if (priority == MLX5_FLOW_PRIO_RSVD)
7372 priority = dev_conf->flow_prio - 1;
7373 /* number of actions must be set to 0 in case of dirty stack. */
7374 mhdr_res->actions_num = 0;
7375 for (; !actions_end ; actions++) {
7376 const struct rte_flow_action_queue *queue;
7377 const struct rte_flow_action_rss *rss;
7378 const struct rte_flow_action *action = actions;
7379 const struct rte_flow_action_count *count = action->conf;
7380 const uint8_t *rss_key;
7381 const struct rte_flow_action_jump *jump_data;
7382 const struct rte_flow_action_meter *mtr;
7383 struct mlx5_flow_tbl_resource *tbl;
7384 uint32_t port_id = 0;
7385 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7386 int action_type = actions->type;
7387 const struct rte_flow_action *found_action = NULL;
7389 switch (action_type) {
7390 case RTE_FLOW_ACTION_TYPE_VOID:
7392 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7393 if (flow_dv_translate_action_port_id(dev, action,
7396 port_id_resource.port_id = port_id;
7397 if (flow_dv_port_id_action_resource_register
7398 (dev, &port_id_resource, dev_flow, error))
7400 dev_flow->dv.actions[actions_n++] =
7401 handle->dvh.port_id_action->action;
7402 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7404 case RTE_FLOW_ACTION_TYPE_FLAG:
7405 action_flags |= MLX5_FLOW_ACTION_FLAG;
7406 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7407 struct rte_flow_action_mark mark = {
7408 .id = MLX5_FLOW_MARK_DEFAULT,
7411 if (flow_dv_convert_action_mark(dev, &mark,
7415 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7418 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7420 * Only one FLAG or MARK is supported per device flow
7421 * right now. So the pointer to the tag resource must be
7422 * zero before the register process.
7424 MLX5_ASSERT(!handle->dvh.tag_resource);
7425 if (flow_dv_tag_resource_register(dev, tag_be,
7428 dev_flow->dv.actions[actions_n++] =
7429 handle->dvh.tag_resource->action;
7431 case RTE_FLOW_ACTION_TYPE_MARK:
7432 action_flags |= MLX5_FLOW_ACTION_MARK;
7433 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7434 const struct rte_flow_action_mark *mark =
7435 (const struct rte_flow_action_mark *)
7438 if (flow_dv_convert_action_mark(dev, mark,
7442 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7446 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7447 /* Legacy (non-extensive) MARK action. */
7448 tag_be = mlx5_flow_mark_set
7449 (((const struct rte_flow_action_mark *)
7450 (actions->conf))->id);
7451 MLX5_ASSERT(!handle->dvh.tag_resource);
7452 if (flow_dv_tag_resource_register(dev, tag_be,
7455 dev_flow->dv.actions[actions_n++] =
7456 handle->dvh.tag_resource->action;
7458 case RTE_FLOW_ACTION_TYPE_SET_META:
7459 if (flow_dv_convert_action_set_meta
7460 (dev, mhdr_res, attr,
7461 (const struct rte_flow_action_set_meta *)
7462 actions->conf, error))
7464 action_flags |= MLX5_FLOW_ACTION_SET_META;
7466 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7467 if (flow_dv_convert_action_set_tag
7469 (const struct rte_flow_action_set_tag *)
7470 actions->conf, error))
7472 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7474 case RTE_FLOW_ACTION_TYPE_DROP:
7475 action_flags |= MLX5_FLOW_ACTION_DROP;
7477 case RTE_FLOW_ACTION_TYPE_QUEUE:
7478 MLX5_ASSERT(flow->rss.queue);
7479 queue = actions->conf;
7480 flow->rss.queue_num = 1;
7481 (*flow->rss.queue)[0] = queue->index;
7482 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7484 case RTE_FLOW_ACTION_TYPE_RSS:
7485 MLX5_ASSERT(flow->rss.queue);
7486 rss = actions->conf;
7487 if (flow->rss.queue)
7488 memcpy((*flow->rss.queue), rss->queue,
7489 rss->queue_num * sizeof(uint16_t));
7490 flow->rss.queue_num = rss->queue_num;
7491 /* NULL RSS key indicates default RSS key. */
7492 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7493 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7495 * rss->level and rss.types should be set in advance
7496 * when expanding items for RSS.
7498 action_flags |= MLX5_FLOW_ACTION_RSS;
7500 case RTE_FLOW_ACTION_TYPE_COUNT:
7501 if (!dev_conf->devx) {
7502 rte_errno = ENOTSUP;
7505 flow->counter = flow_dv_counter_alloc(dev,
7508 dev_flow->dv.group);
7509 if (flow->counter == NULL)
7511 dev_flow->dv.actions[actions_n++] =
7512 flow->counter->action;
7513 action_flags |= MLX5_FLOW_ACTION_COUNT;
7516 if (rte_errno == ENOTSUP)
7517 return rte_flow_error_set
7519 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7521 "count action not supported");
7523 return rte_flow_error_set
7525 RTE_FLOW_ERROR_TYPE_ACTION,
7527 "cannot create counter"
7530 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7531 dev_flow->dv.actions[actions_n++] =
7532 priv->sh->pop_vlan_action;
7533 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7535 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7536 flow_dev_get_vlan_info_from_items(items, &vlan);
7537 vlan.eth_proto = rte_be_to_cpu_16
7538 ((((const struct rte_flow_action_of_push_vlan *)
7539 actions->conf)->ethertype));
7540 found_action = mlx5_flow_find_action
7542 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7544 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7545 found_action = mlx5_flow_find_action
7547 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7549 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7550 if (flow_dv_create_action_push_vlan
7551 (dev, attr, &vlan, dev_flow, error))
7553 dev_flow->dv.actions[actions_n++] =
7554 handle->dvh.push_vlan_res->action;
7555 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7557 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7558 /* of_vlan_push action handled this action */
7559 MLX5_ASSERT(action_flags &
7560 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7562 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7563 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7565 flow_dev_get_vlan_info_from_items(items, &vlan);
7566 mlx5_update_vlan_vid_pcp(actions, &vlan);
7567 /* If no VLAN push - this is a modify header action */
7568 if (flow_dv_convert_action_modify_vlan_vid
7569 (mhdr_res, actions, error))
7571 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7573 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7574 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7575 if (flow_dv_create_action_l2_encap(dev, actions,
7580 dev_flow->dv.actions[actions_n++] =
7581 handle->dvh.encap_decap->verbs_action;
7582 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7584 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7585 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7586 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7590 dev_flow->dv.actions[actions_n++] =
7591 handle->dvh.encap_decap->verbs_action;
7592 action_flags |= MLX5_FLOW_ACTION_DECAP;
7594 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7595 /* Handle encap with preceding decap. */
7596 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7597 if (flow_dv_create_action_raw_encap
7598 (dev, actions, dev_flow, attr, error))
7600 dev_flow->dv.actions[actions_n++] =
7601 handle->dvh.encap_decap->verbs_action;
7603 /* Handle encap without preceding decap. */
7604 if (flow_dv_create_action_l2_encap
7605 (dev, actions, dev_flow, attr->transfer,
7608 dev_flow->dv.actions[actions_n++] =
7609 handle->dvh.encap_decap->verbs_action;
7611 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7613 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7614 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7616 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7617 if (flow_dv_create_action_l2_decap
7618 (dev, dev_flow, attr->transfer, error))
7620 dev_flow->dv.actions[actions_n++] =
7621 handle->dvh.encap_decap->verbs_action;
7623 /* If decap is followed by encap, handle it at encap. */
7624 action_flags |= MLX5_FLOW_ACTION_DECAP;
7626 case RTE_FLOW_ACTION_TYPE_JUMP:
7627 jump_data = action->conf;
7628 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7630 !!priv->fdb_def_rule,
7634 tbl = flow_dv_tbl_resource_get(dev, table,
7636 attr->transfer, error);
7638 return rte_flow_error_set
7640 RTE_FLOW_ERROR_TYPE_ACTION,
7642 "cannot create jump action.");
7643 if (flow_dv_jump_tbl_resource_register
7644 (dev, tbl, dev_flow, error)) {
7645 flow_dv_tbl_resource_release(dev, tbl);
7646 return rte_flow_error_set
7648 RTE_FLOW_ERROR_TYPE_ACTION,
7650 "cannot create jump action.");
7652 dev_flow->dv.actions[actions_n++] =
7653 handle->dvh.jump->action;
7654 action_flags |= MLX5_FLOW_ACTION_JUMP;
7656 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7657 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7658 if (flow_dv_convert_action_modify_mac
7659 (mhdr_res, actions, error))
7661 action_flags |= actions->type ==
7662 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7663 MLX5_FLOW_ACTION_SET_MAC_SRC :
7664 MLX5_FLOW_ACTION_SET_MAC_DST;
7666 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7667 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7668 if (flow_dv_convert_action_modify_ipv4
7669 (mhdr_res, actions, error))
7671 action_flags |= actions->type ==
7672 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7673 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7674 MLX5_FLOW_ACTION_SET_IPV4_DST;
7676 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7677 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7678 if (flow_dv_convert_action_modify_ipv6
7679 (mhdr_res, actions, error))
7681 action_flags |= actions->type ==
7682 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7683 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7684 MLX5_FLOW_ACTION_SET_IPV6_DST;
7686 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7687 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7688 if (flow_dv_convert_action_modify_tp
7689 (mhdr_res, actions, items,
7690 &flow_attr, dev_flow, !!(action_flags &
7691 MLX5_FLOW_ACTION_DECAP), error))
7693 action_flags |= actions->type ==
7694 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7695 MLX5_FLOW_ACTION_SET_TP_SRC :
7696 MLX5_FLOW_ACTION_SET_TP_DST;
7698 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7699 if (flow_dv_convert_action_modify_dec_ttl
7700 (mhdr_res, items, &flow_attr, dev_flow,
7702 MLX5_FLOW_ACTION_DECAP), error))
7704 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7706 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7707 if (flow_dv_convert_action_modify_ttl
7708 (mhdr_res, actions, items, &flow_attr,
7709 dev_flow, !!(action_flags &
7710 MLX5_FLOW_ACTION_DECAP), error))
7712 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7714 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7715 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7716 if (flow_dv_convert_action_modify_tcp_seq
7717 (mhdr_res, actions, error))
7719 action_flags |= actions->type ==
7720 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7721 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7722 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7725 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7726 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7727 if (flow_dv_convert_action_modify_tcp_ack
7728 (mhdr_res, actions, error))
7730 action_flags |= actions->type ==
7731 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7732 MLX5_FLOW_ACTION_INC_TCP_ACK :
7733 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7735 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7736 if (flow_dv_convert_action_set_reg
7737 (mhdr_res, actions, error))
7739 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7741 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7742 if (flow_dv_convert_action_copy_mreg
7743 (dev, mhdr_res, actions, error))
7745 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7747 case RTE_FLOW_ACTION_TYPE_METER:
7748 mtr = actions->conf;
7750 flow->meter = mlx5_flow_meter_attach(priv,
7754 return rte_flow_error_set(error,
7756 RTE_FLOW_ERROR_TYPE_ACTION,
7759 "or invalid parameters");
7761 /* Set the meter action. */
7762 dev_flow->dv.actions[actions_n++] =
7763 flow->meter->mfts->meter_action;
7764 action_flags |= MLX5_FLOW_ACTION_METER;
7766 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7767 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7770 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7772 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7773 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7776 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7778 case RTE_FLOW_ACTION_TYPE_END:
7780 if (mhdr_res->actions_num) {
7781 /* create modify action if needed. */
7782 if (flow_dv_modify_hdr_resource_register
7783 (dev, mhdr_res, dev_flow, error))
7785 dev_flow->dv.actions[modify_action_position] =
7786 handle->dvh.modify_hdr->verbs_action;
7792 if (mhdr_res->actions_num &&
7793 modify_action_position == UINT32_MAX)
7794 modify_action_position = actions_n++;
7796 dev_flow->dv.actions_n = actions_n;
7797 handle->act_flags = action_flags;
7798 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7799 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7800 int item_type = items->type;
7802 switch (item_type) {
7803 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7804 flow_dv_translate_item_port_id(dev, match_mask,
7805 match_value, items);
7806 last_item = MLX5_FLOW_ITEM_PORT_ID;
7808 case RTE_FLOW_ITEM_TYPE_ETH:
7809 flow_dv_translate_item_eth(match_mask, match_value,
7811 matcher.priority = MLX5_PRIORITY_MAP_L2;
7812 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7813 MLX5_FLOW_LAYER_OUTER_L2;
7815 case RTE_FLOW_ITEM_TYPE_VLAN:
7816 flow_dv_translate_item_vlan(dev_flow,
7817 match_mask, match_value,
7819 matcher.priority = MLX5_PRIORITY_MAP_L2;
7820 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7821 MLX5_FLOW_LAYER_INNER_VLAN) :
7822 (MLX5_FLOW_LAYER_OUTER_L2 |
7823 MLX5_FLOW_LAYER_OUTER_VLAN);
7825 case RTE_FLOW_ITEM_TYPE_IPV4:
7826 mlx5_flow_tunnel_ip_check(items, next_protocol,
7827 &item_flags, &tunnel);
7828 flow_dv_translate_item_ipv4(match_mask, match_value,
7829 items, item_flags, tunnel,
7830 dev_flow->dv.group);
7831 matcher.priority = MLX5_PRIORITY_MAP_L3;
7832 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7833 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7834 if (items->mask != NULL &&
7835 ((const struct rte_flow_item_ipv4 *)
7836 items->mask)->hdr.next_proto_id) {
7838 ((const struct rte_flow_item_ipv4 *)
7839 (items->spec))->hdr.next_proto_id;
7841 ((const struct rte_flow_item_ipv4 *)
7842 (items->mask))->hdr.next_proto_id;
7844 /* Reset for inner layer. */
7845 next_protocol = 0xff;
7848 case RTE_FLOW_ITEM_TYPE_IPV6:
7849 mlx5_flow_tunnel_ip_check(items, next_protocol,
7850 &item_flags, &tunnel);
7851 flow_dv_translate_item_ipv6(match_mask, match_value,
7852 items, item_flags, tunnel,
7853 dev_flow->dv.group);
7854 matcher.priority = MLX5_PRIORITY_MAP_L3;
7855 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7856 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7857 if (items->mask != NULL &&
7858 ((const struct rte_flow_item_ipv6 *)
7859 items->mask)->hdr.proto) {
7861 ((const struct rte_flow_item_ipv6 *)
7862 items->spec)->hdr.proto;
7864 ((const struct rte_flow_item_ipv6 *)
7865 items->mask)->hdr.proto;
7867 /* Reset for inner layer. */
7868 next_protocol = 0xff;
7871 case RTE_FLOW_ITEM_TYPE_TCP:
7872 flow_dv_translate_item_tcp(match_mask, match_value,
7874 matcher.priority = MLX5_PRIORITY_MAP_L4;
7875 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7876 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7878 case RTE_FLOW_ITEM_TYPE_UDP:
7879 flow_dv_translate_item_udp(match_mask, match_value,
7881 matcher.priority = MLX5_PRIORITY_MAP_L4;
7882 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7883 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7885 case RTE_FLOW_ITEM_TYPE_GRE:
7886 flow_dv_translate_item_gre(match_mask, match_value,
7888 matcher.priority = flow->rss.level >= 2 ?
7889 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7890 last_item = MLX5_FLOW_LAYER_GRE;
7892 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7893 flow_dv_translate_item_gre_key(match_mask,
7894 match_value, items);
7895 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7897 case RTE_FLOW_ITEM_TYPE_NVGRE:
7898 flow_dv_translate_item_nvgre(match_mask, match_value,
7900 matcher.priority = flow->rss.level >= 2 ?
7901 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7902 last_item = MLX5_FLOW_LAYER_GRE;
7904 case RTE_FLOW_ITEM_TYPE_VXLAN:
7905 flow_dv_translate_item_vxlan(match_mask, match_value,
7907 matcher.priority = flow->rss.level >= 2 ?
7908 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7909 last_item = MLX5_FLOW_LAYER_VXLAN;
7911 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7912 flow_dv_translate_item_vxlan_gpe(match_mask,
7915 matcher.priority = flow->rss.level >= 2 ?
7916 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7917 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7919 case RTE_FLOW_ITEM_TYPE_GENEVE:
7920 flow_dv_translate_item_geneve(match_mask, match_value,
7922 matcher.priority = flow->rss.level >= 2 ?
7923 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7924 last_item = MLX5_FLOW_LAYER_GENEVE;
7926 case RTE_FLOW_ITEM_TYPE_MPLS:
7927 flow_dv_translate_item_mpls(match_mask, match_value,
7928 items, last_item, tunnel);
7929 matcher.priority = flow->rss.level >= 2 ?
7930 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7931 last_item = MLX5_FLOW_LAYER_MPLS;
7933 case RTE_FLOW_ITEM_TYPE_MARK:
7934 flow_dv_translate_item_mark(dev, match_mask,
7935 match_value, items);
7936 last_item = MLX5_FLOW_ITEM_MARK;
7938 case RTE_FLOW_ITEM_TYPE_META:
7939 flow_dv_translate_item_meta(dev, match_mask,
7940 match_value, attr, items);
7941 last_item = MLX5_FLOW_ITEM_METADATA;
7943 case RTE_FLOW_ITEM_TYPE_ICMP:
7944 flow_dv_translate_item_icmp(match_mask, match_value,
7946 last_item = MLX5_FLOW_LAYER_ICMP;
7948 case RTE_FLOW_ITEM_TYPE_ICMP6:
7949 flow_dv_translate_item_icmp6(match_mask, match_value,
7951 last_item = MLX5_FLOW_LAYER_ICMP6;
7953 case RTE_FLOW_ITEM_TYPE_TAG:
7954 flow_dv_translate_item_tag(dev, match_mask,
7955 match_value, items);
7956 last_item = MLX5_FLOW_ITEM_TAG;
7958 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7959 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7960 match_value, items);
7961 last_item = MLX5_FLOW_ITEM_TAG;
7963 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7964 flow_dv_translate_item_tx_queue(dev, match_mask,
7967 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7969 case RTE_FLOW_ITEM_TYPE_GTP:
7970 flow_dv_translate_item_gtp(match_mask, match_value,
7972 matcher.priority = flow->rss.level >= 2 ?
7973 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7974 last_item = MLX5_FLOW_LAYER_GTP;
7979 item_flags |= last_item;
7982 * When E-Switch mode is enabled, we have two cases where we need to
7983 * set the source port manually.
7984 * The first one, is in case of Nic steering rule, and the second is
7985 * E-Switch rule where no port_id item was found. In both cases
7986 * the source port is set according the current port in use.
7988 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7989 (priv->representor || priv->master)) {
7990 if (flow_dv_translate_item_port_id(dev, match_mask,
7994 #ifdef RTE_LIBRTE_MLX5_DEBUG
7995 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7996 dev_flow->dv.value.buf));
7999 * Layers may be already initialized from prefix flow if this dev_flow
8000 * is the suffix flow.
8002 handle->layers |= item_flags;
8003 if (action_flags & MLX5_FLOW_ACTION_RSS)
8004 flow_dv_hashfields_set(dev_flow);
8005 /* Register matcher. */
8006 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8008 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8010 /* reserved field no needs to be set to 0 here. */
8011 tbl_key.domain = attr->transfer;
8012 tbl_key.direction = attr->egress;
8013 tbl_key.table_id = dev_flow->dv.group;
8014 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8020 * Apply the flow to the NIC, lock free,
8021 * (mutex should be acquired by caller).
8024 * Pointer to the Ethernet device structure.
8025 * @param[in, out] flow
8026 * Pointer to flow structure.
8028 * Pointer to error structure.
8031 * 0 on success, a negative errno value otherwise and rte_errno is set.
8034 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8035 struct rte_flow_error *error)
8037 struct mlx5_flow_dv_workspace *dv;
8038 struct mlx5_flow_handle *dh;
8039 struct mlx5_flow_handle_dv *dv_h;
8040 struct mlx5_flow *dev_flow;
8041 struct mlx5_priv *priv = dev->data->dev_private;
8046 for (idx = priv->flow_idx - 1; idx >= 0; idx--) {
8047 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8049 dh = dev_flow->handle;
8052 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8054 dv->actions[n++] = priv->sh->esw_drop_action;
8056 dh->hrxq = mlx5_hrxq_drop_new(dev);
8060 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8062 "cannot get drop hash queue");
8065 dv->actions[n++] = dh->hrxq->action;
8067 } else if (dh->act_flags &
8068 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8069 struct mlx5_hrxq *hrxq;
8071 MLX5_ASSERT(flow->rss.queue);
8072 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8073 MLX5_RSS_HASH_KEY_LEN,
8074 dev_flow->hash_fields,
8076 flow->rss.queue_num);
8078 hrxq = mlx5_hrxq_new
8079 (dev, flow->rss.key,
8080 MLX5_RSS_HASH_KEY_LEN,
8081 dev_flow->hash_fields,
8083 flow->rss.queue_num,
8085 MLX5_FLOW_LAYER_TUNNEL));
8090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8091 "cannot get hash queue");
8095 dv->actions[n++] = dh->hrxq->action;
8098 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8099 (void *)&dv->value, n,
8102 rte_flow_error_set(error, errno,
8103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8105 "hardware refuses to create flow");
8108 if (priv->vmwa_context &&
8109 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8111 * The rule contains the VLAN pattern.
8112 * For VF we are going to create VLAN
8113 * interface to make hypervisor set correct
8114 * e-Switch vport context.
8116 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8121 err = rte_errno; /* Save rte_errno before cleanup. */
8122 LIST_FOREACH(dh, &flow->dev_handles, next) {
8124 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8125 mlx5_hrxq_drop_release(dev);
8127 mlx5_hrxq_release(dev, dh->hrxq);
8130 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8131 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8133 rte_errno = err; /* Restore rte_errno. */
8138 * Release the flow matcher.
8141 * Pointer to Ethernet device.
8143 * Pointer to mlx5_flow_handle.
8146 * 1 while a reference on it exists, 0 when freed.
8149 flow_dv_matcher_release(struct rte_eth_dev *dev,
8150 struct mlx5_flow_handle *handle)
8152 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8154 MLX5_ASSERT(matcher->matcher_object);
8155 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8156 dev->data->port_id, (void *)matcher,
8157 rte_atomic32_read(&matcher->refcnt));
8158 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8159 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8160 (matcher->matcher_object));
8161 LIST_REMOVE(matcher, next);
8162 /* table ref-- in release interface. */
8163 flow_dv_tbl_resource_release(dev, matcher->tbl);
8165 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8166 dev->data->port_id, (void *)matcher);
8173 * Release an encap/decap resource.
8176 * Pointer to mlx5_flow_handle.
8179 * 1 while a reference on it exists, 0 when freed.
8182 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8184 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8185 handle->dvh.encap_decap;
8187 MLX5_ASSERT(cache_resource->verbs_action);
8188 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8189 (void *)cache_resource,
8190 rte_atomic32_read(&cache_resource->refcnt));
8191 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8192 claim_zero(mlx5_glue->destroy_flow_action
8193 (cache_resource->verbs_action));
8194 LIST_REMOVE(cache_resource, next);
8195 rte_free(cache_resource);
8196 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8197 (void *)cache_resource);
8204 * Release an jump to table action resource.
8207 * Pointer to Ethernet device.
8209 * Pointer to mlx5_flow_handle.
8212 * 1 while a reference on it exists, 0 when freed.
8215 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8216 struct mlx5_flow_handle *handle)
8218 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8220 struct mlx5_flow_tbl_data_entry *tbl_data =
8221 container_of(cache_resource,
8222 struct mlx5_flow_tbl_data_entry, jump);
8224 MLX5_ASSERT(cache_resource->action);
8225 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8226 (void *)cache_resource,
8227 rte_atomic32_read(&cache_resource->refcnt));
8228 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8229 claim_zero(mlx5_glue->destroy_flow_action
8230 (cache_resource->action));
8231 /* jump action memory free is inside the table release. */
8232 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8233 DRV_LOG(DEBUG, "jump table resource %p: removed",
8234 (void *)cache_resource);
8241 * Release a modify-header resource.
8244 * Pointer to mlx5_flow_handle.
8247 * 1 while a reference on it exists, 0 when freed.
8250 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8252 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8253 handle->dvh.modify_hdr;
8255 MLX5_ASSERT(cache_resource->verbs_action);
8256 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8257 (void *)cache_resource,
8258 rte_atomic32_read(&cache_resource->refcnt));
8259 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8260 claim_zero(mlx5_glue->destroy_flow_action
8261 (cache_resource->verbs_action));
8262 LIST_REMOVE(cache_resource, next);
8263 rte_free(cache_resource);
8264 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8265 (void *)cache_resource);
8272 * Release port ID action resource.
8275 * Pointer to mlx5_flow_handle.
8278 * 1 while a reference on it exists, 0 when freed.
8281 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8283 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8284 handle->dvh.port_id_action;
8286 MLX5_ASSERT(cache_resource->action);
8287 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8288 (void *)cache_resource,
8289 rte_atomic32_read(&cache_resource->refcnt));
8290 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8291 claim_zero(mlx5_glue->destroy_flow_action
8292 (cache_resource->action));
8293 LIST_REMOVE(cache_resource, next);
8294 rte_free(cache_resource);
8295 DRV_LOG(DEBUG, "port id action resource %p: removed",
8296 (void *)cache_resource);
8303 * Release push vlan action resource.
8306 * Pointer to mlx5_flow_handle.
8309 * 1 while a reference on it exists, 0 when freed.
8312 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8314 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8315 handle->dvh.push_vlan_res;
8317 MLX5_ASSERT(cache_resource->action);
8318 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8319 (void *)cache_resource,
8320 rte_atomic32_read(&cache_resource->refcnt));
8321 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8322 claim_zero(mlx5_glue->destroy_flow_action
8323 (cache_resource->action));
8324 LIST_REMOVE(cache_resource, next);
8325 rte_free(cache_resource);
8326 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8327 (void *)cache_resource);
8334 * Remove the flow from the NIC but keeps it in memory.
8335 * Lock free, (mutex should be acquired by caller).
8338 * Pointer to Ethernet device.
8339 * @param[in, out] flow
8340 * Pointer to flow structure.
8343 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8345 struct mlx5_flow_handle *dh;
8349 LIST_FOREACH(dh, &flow->dev_handles, next) {
8351 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8355 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8356 mlx5_hrxq_drop_release(dev);
8358 mlx5_hrxq_release(dev, dh->hrxq);
8361 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8362 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8367 * Remove the flow from the NIC and the memory.
8368 * Lock free, (mutex should be acquired by caller).
8371 * Pointer to the Ethernet device structure.
8372 * @param[in, out] flow
8373 * Pointer to flow structure.
8376 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8378 struct mlx5_flow_handle *dev_handle;
8382 __flow_dv_remove(dev, flow);
8383 if (flow->counter) {
8384 flow_dv_counter_release(dev, flow->counter);
8385 flow->counter = NULL;
8388 mlx5_flow_meter_detach(flow->meter);
8391 while (!LIST_EMPTY(&flow->dev_handles)) {
8392 dev_handle = LIST_FIRST(&flow->dev_handles);
8393 LIST_REMOVE(dev_handle, next);
8394 if (dev_handle->dvh.matcher)
8395 flow_dv_matcher_release(dev, dev_handle);
8396 if (dev_handle->dvh.encap_decap)
8397 flow_dv_encap_decap_resource_release(dev_handle);
8398 if (dev_handle->dvh.modify_hdr)
8399 flow_dv_modify_hdr_resource_release(dev_handle);
8400 if (dev_handle->dvh.jump)
8401 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8402 if (dev_handle->dvh.port_id_action)
8403 flow_dv_port_id_action_resource_release(dev_handle);
8404 if (dev_handle->dvh.push_vlan_res)
8405 flow_dv_push_vlan_action_resource_release(dev_handle);
8406 if (dev_handle->dvh.tag_resource)
8407 flow_dv_tag_release(dev,
8408 dev_handle->dvh.tag_resource);
8409 rte_free(dev_handle);
8414 * Query a dv flow rule for its statistics via devx.
8417 * Pointer to Ethernet device.
8419 * Pointer to the sub flow.
8421 * data retrieved by the query.
8423 * Perform verbose error reporting if not NULL.
8426 * 0 on success, a negative errno value otherwise and rte_errno is set.
8429 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8430 void *data, struct rte_flow_error *error)
8432 struct mlx5_priv *priv = dev->data->dev_private;
8433 struct rte_flow_query_count *qc = data;
8435 if (!priv->config.devx)
8436 return rte_flow_error_set(error, ENOTSUP,
8437 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8439 "counters are not supported");
8440 if (flow->counter) {
8441 uint64_t pkts, bytes;
8442 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8446 return rte_flow_error_set(error, -err,
8447 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8448 NULL, "cannot read counters");
8451 qc->hits = pkts - flow->counter->hits;
8452 qc->bytes = bytes - flow->counter->bytes;
8454 flow->counter->hits = pkts;
8455 flow->counter->bytes = bytes;
8459 return rte_flow_error_set(error, EINVAL,
8460 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8462 "counters are not available");
8468 * @see rte_flow_query()
8472 flow_dv_query(struct rte_eth_dev *dev,
8473 struct rte_flow *flow __rte_unused,
8474 const struct rte_flow_action *actions __rte_unused,
8475 void *data __rte_unused,
8476 struct rte_flow_error *error __rte_unused)
8480 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8481 switch (actions->type) {
8482 case RTE_FLOW_ACTION_TYPE_VOID:
8484 case RTE_FLOW_ACTION_TYPE_COUNT:
8485 ret = flow_dv_query_count(dev, flow, data, error);
8488 return rte_flow_error_set(error, ENOTSUP,
8489 RTE_FLOW_ERROR_TYPE_ACTION,
8491 "action not supported");
8498 * Destroy the meter table set.
8499 * Lock free, (mutex should be acquired by caller).
8502 * Pointer to Ethernet device.
8504 * Pointer to the meter table set.
8510 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8511 struct mlx5_meter_domains_infos *tbl)
8513 struct mlx5_priv *priv = dev->data->dev_private;
8514 struct mlx5_meter_domains_infos *mtd =
8515 (struct mlx5_meter_domains_infos *)tbl;
8517 if (!mtd || !priv->config.dv_flow_en)
8519 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8520 claim_zero(mlx5_glue->dv_destroy_flow
8521 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8522 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8523 claim_zero(mlx5_glue->dv_destroy_flow
8524 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8525 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8526 claim_zero(mlx5_glue->dv_destroy_flow
8527 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8528 if (mtd->egress.color_matcher)
8529 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8530 (mtd->egress.color_matcher));
8531 if (mtd->egress.any_matcher)
8532 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8533 (mtd->egress.any_matcher));
8534 if (mtd->egress.tbl)
8535 claim_zero(flow_dv_tbl_resource_release(dev,
8537 if (mtd->ingress.color_matcher)
8538 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8539 (mtd->ingress.color_matcher));
8540 if (mtd->ingress.any_matcher)
8541 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8542 (mtd->ingress.any_matcher));
8543 if (mtd->ingress.tbl)
8544 claim_zero(flow_dv_tbl_resource_release(dev,
8546 if (mtd->transfer.color_matcher)
8547 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8548 (mtd->transfer.color_matcher));
8549 if (mtd->transfer.any_matcher)
8550 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8551 (mtd->transfer.any_matcher));
8552 if (mtd->transfer.tbl)
8553 claim_zero(flow_dv_tbl_resource_release(dev,
8554 mtd->transfer.tbl));
8556 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8561 /* Number of meter flow actions, count and jump or count and drop. */
8562 #define METER_ACTIONS 2
8565 * Create specify domain meter table and suffix table.
8568 * Pointer to Ethernet device.
8569 * @param[in,out] mtb
8570 * Pointer to DV meter table set.
8573 * @param[in] transfer
8575 * @param[in] color_reg_c_idx
8576 * Reg C index for color match.
8579 * 0 on success, -1 otherwise and rte_errno is set.
8582 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8583 struct mlx5_meter_domains_infos *mtb,
8584 uint8_t egress, uint8_t transfer,
8585 uint32_t color_reg_c_idx)
8587 struct mlx5_priv *priv = dev->data->dev_private;
8588 struct mlx5_ibv_shared *sh = priv->sh;
8589 struct mlx5_flow_dv_match_params mask = {
8590 .size = sizeof(mask.buf),
8592 struct mlx5_flow_dv_match_params value = {
8593 .size = sizeof(value.buf),
8595 struct mlx5dv_flow_matcher_attr dv_attr = {
8596 .type = IBV_FLOW_ATTR_NORMAL,
8598 .match_criteria_enable = 0,
8599 .match_mask = (void *)&mask,
8601 void *actions[METER_ACTIONS];
8602 struct mlx5_flow_tbl_resource **sfx_tbl;
8603 struct mlx5_meter_domain_info *dtb;
8604 struct rte_flow_error error;
8608 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8609 dtb = &mtb->transfer;
8610 } else if (egress) {
8611 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8614 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8615 dtb = &mtb->ingress;
8617 /* If the suffix table in missing, create it. */
8619 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8620 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8621 egress, transfer, &error);
8623 DRV_LOG(ERR, "Failed to create meter suffix table.");
8627 /* Create the meter table with METER level. */
8628 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8629 egress, transfer, &error);
8631 DRV_LOG(ERR, "Failed to create meter policer table.");
8634 /* Create matchers, Any and Color. */
8635 dv_attr.priority = 3;
8636 dv_attr.match_criteria_enable = 0;
8637 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8640 if (!dtb->any_matcher) {
8641 DRV_LOG(ERR, "Failed to create meter"
8642 " policer default matcher.");
8645 dv_attr.priority = 0;
8646 dv_attr.match_criteria_enable =
8647 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8648 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8649 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8650 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8653 if (!dtb->color_matcher) {
8654 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8657 if (mtb->count_actns[RTE_MTR_DROPPED])
8658 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8659 actions[i++] = mtb->drop_actn;
8660 /* Default rule: lowest priority, match any, actions: drop. */
8661 dtb->policer_rules[RTE_MTR_DROPPED] =
8662 mlx5_glue->dv_create_flow(dtb->any_matcher,
8663 (void *)&value, i, actions);
8664 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8665 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8674 * Create the needed meter and suffix tables.
8675 * Lock free, (mutex should be acquired by caller).
8678 * Pointer to Ethernet device.
8680 * Pointer to the flow meter.
8683 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8685 static struct mlx5_meter_domains_infos *
8686 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8687 const struct mlx5_flow_meter *fm)
8689 struct mlx5_priv *priv = dev->data->dev_private;
8690 struct mlx5_meter_domains_infos *mtb;
8694 if (!priv->mtr_en) {
8695 rte_errno = ENOTSUP;
8698 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8700 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8703 /* Create meter count actions */
8704 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8705 if (!fm->policer_stats.cnt[i])
8707 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8709 /* Create drop action. */
8710 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8711 if (!mtb->drop_actn) {
8712 DRV_LOG(ERR, "Failed to create drop action.");
8715 /* Egress meter table. */
8716 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8718 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8721 /* Ingress meter table. */
8722 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8724 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8727 /* FDB meter table. */
8728 if (priv->config.dv_esw_en) {
8729 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8730 priv->mtr_color_reg);
8732 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8738 flow_dv_destroy_mtr_tbl(dev, mtb);
8743 * Destroy domain policer rule.
8746 * Pointer to domain table.
8749 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8753 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8754 if (dt->policer_rules[i]) {
8755 claim_zero(mlx5_glue->dv_destroy_flow
8756 (dt->policer_rules[i]));
8757 dt->policer_rules[i] = NULL;
8760 if (dt->jump_actn) {
8761 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8762 dt->jump_actn = NULL;
8767 * Destroy policer rules.
8770 * Pointer to Ethernet device.
8772 * Pointer to flow meter structure.
8774 * Pointer to flow attributes.
8780 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8781 const struct mlx5_flow_meter *fm,
8782 const struct rte_flow_attr *attr)
8784 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8789 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8791 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8793 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8798 * Create specify domain meter policer rule.
8801 * Pointer to flow meter structure.
8803 * Pointer to DV meter table set.
8805 * Pointer to suffix table.
8806 * @param[in] mtr_reg_c
8807 * Color match REG_C.
8810 * 0 on success, -1 otherwise.
8813 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8814 struct mlx5_meter_domain_info *dtb,
8815 struct mlx5_flow_tbl_resource *sfx_tb,
8818 struct mlx5_flow_dv_match_params matcher = {
8819 .size = sizeof(matcher.buf),
8821 struct mlx5_flow_dv_match_params value = {
8822 .size = sizeof(value.buf),
8824 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8825 void *actions[METER_ACTIONS];
8828 /* Create jump action. */
8831 if (!dtb->jump_actn)
8833 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8835 if (!dtb->jump_actn) {
8836 DRV_LOG(ERR, "Failed to create policer jump action.");
8839 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8842 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8843 rte_col_2_mlx5_col(i), UINT8_MAX);
8844 if (mtb->count_actns[i])
8845 actions[j++] = mtb->count_actns[i];
8846 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8847 actions[j++] = mtb->drop_actn;
8849 actions[j++] = dtb->jump_actn;
8850 dtb->policer_rules[i] =
8851 mlx5_glue->dv_create_flow(dtb->color_matcher,
8854 if (!dtb->policer_rules[i]) {
8855 DRV_LOG(ERR, "Failed to create policer rule.");
8866 * Create policer rules.
8869 * Pointer to Ethernet device.
8871 * Pointer to flow meter structure.
8873 * Pointer to flow attributes.
8876 * 0 on success, -1 otherwise.
8879 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8880 struct mlx5_flow_meter *fm,
8881 const struct rte_flow_attr *attr)
8883 struct mlx5_priv *priv = dev->data->dev_private;
8884 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8888 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8889 priv->sh->tx_mtr_sfx_tbl,
8890 priv->mtr_color_reg);
8892 DRV_LOG(ERR, "Failed to create egress policer.");
8896 if (attr->ingress) {
8897 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8898 priv->sh->rx_mtr_sfx_tbl,
8899 priv->mtr_color_reg);
8901 DRV_LOG(ERR, "Failed to create ingress policer.");
8905 if (attr->transfer) {
8906 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8907 priv->sh->fdb_mtr_sfx_tbl,
8908 priv->mtr_color_reg);
8910 DRV_LOG(ERR, "Failed to create transfer policer.");
8916 flow_dv_destroy_policer_rules(dev, fm, attr);
8921 * Query a devx counter.
8924 * Pointer to the Ethernet device structure.
8926 * Pointer to the flow counter.
8928 * Set to clear the counter statistics.
8930 * The statistics value of packets.
8932 * The statistics value of bytes.
8935 * 0 on success, otherwise return -1.
8938 flow_dv_counter_query(struct rte_eth_dev *dev,
8939 struct mlx5_flow_counter *cnt, bool clear,
8940 uint64_t *pkts, uint64_t *bytes)
8942 struct mlx5_priv *priv = dev->data->dev_private;
8943 uint64_t inn_pkts, inn_bytes;
8946 if (!priv->config.devx)
8948 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8951 *pkts = inn_pkts - cnt->hits;
8952 *bytes = inn_bytes - cnt->bytes;
8954 cnt->hits = inn_pkts;
8955 cnt->bytes = inn_bytes;
8961 * Mutex-protected thunk to lock-free __flow_dv_translate().
8964 flow_dv_translate(struct rte_eth_dev *dev,
8965 struct mlx5_flow *dev_flow,
8966 const struct rte_flow_attr *attr,
8967 const struct rte_flow_item items[],
8968 const struct rte_flow_action actions[],
8969 struct rte_flow_error *error)
8973 flow_dv_shared_lock(dev);
8974 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8975 flow_dv_shared_unlock(dev);
8980 * Mutex-protected thunk to lock-free __flow_dv_apply().
8983 flow_dv_apply(struct rte_eth_dev *dev,
8984 struct rte_flow *flow,
8985 struct rte_flow_error *error)
8989 flow_dv_shared_lock(dev);
8990 ret = __flow_dv_apply(dev, flow, error);
8991 flow_dv_shared_unlock(dev);
8996 * Mutex-protected thunk to lock-free __flow_dv_remove().
8999 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9001 flow_dv_shared_lock(dev);
9002 __flow_dv_remove(dev, flow);
9003 flow_dv_shared_unlock(dev);
9007 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9010 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9012 flow_dv_shared_lock(dev);
9013 __flow_dv_destroy(dev, flow);
9014 flow_dv_shared_unlock(dev);
9018 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9020 static struct mlx5_flow_counter *
9021 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9023 struct mlx5_flow_counter *cnt;
9025 flow_dv_shared_lock(dev);
9026 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9027 flow_dv_shared_unlock(dev);
9032 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9035 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
9037 flow_dv_shared_lock(dev);
9038 flow_dv_counter_release(dev, cnt);
9039 flow_dv_shared_unlock(dev);
9042 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9043 .validate = flow_dv_validate,
9044 .prepare = flow_dv_prepare,
9045 .translate = flow_dv_translate,
9046 .apply = flow_dv_apply,
9047 .remove = flow_dv_remove,
9048 .destroy = flow_dv_destroy,
9049 .query = flow_dv_query,
9050 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9051 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9052 .create_policer_rules = flow_dv_create_policer_rules,
9053 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9054 .counter_alloc = flow_dv_counter_allocate,
9055 .counter_free = flow_dv_counter_free,
9056 .counter_query = flow_dv_counter_query,
9059 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */