drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9
  10 /* Verbs header. */
  11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  12 #ifdef PEDANTIC
  13 #pragma GCC diagnostic ignored "-Wpedantic"
  14 #endif
  15 #include <infiniband/verbs.h>
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic error "-Wpedantic"
  18 #endif
  19
  20 #include <rte_common.h>
  21 #include <rte_ether.h>
  22 #include <rte_eth_ctrl.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_defs.h"
  32 #include "mlx5_prm.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35
  36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  37
  38 /**
  39  * Validate META item.
  40  *
  41  * @param[in] dev
  42  *   Pointer to the rte_eth_dev structure.
  43  * @param[in] item
  44  *   Item specification.
  45  * @param[in] attr
  46  *   Attributes of flow that includes this item.
  47  * @param[out] error
  48  *   Pointer to error structure.
  49  *
  50  * @return
  51  *   0 on success, a negative errno value otherwise and rte_errno is set.
  52  */
  53 static int
  54 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
  55                            const struct rte_flow_item *item,
  56                            const struct rte_flow_attr *attr,
  57                            struct rte_flow_error *error)
  58 {
  59         const struct rte_flow_item_meta *spec = item->spec;
  60         const struct rte_flow_item_meta *mask = item->mask;
  61         const struct rte_flow_item_meta nic_mask = {
  62                 .data = RTE_BE32(UINT32_MAX)
  63         };
  64         int ret;
  65         uint64_t offloads = dev->data->dev_conf.txmode.offloads;
  66
  67         if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
  68                 return rte_flow_error_set(error, EPERM,
  69                                           RTE_FLOW_ERROR_TYPE_ITEM,
  70                                           NULL,
  71                                           "match on metadata offload "
  72                                           "configuration is off for this port");
  73         if (!spec)
  74                 return rte_flow_error_set(error, EINVAL,
  75                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  76                                           item->spec,
  77                                           "data cannot be empty");
  78         if (!spec->data)
  79                 return rte_flow_error_set(error, EINVAL,
  80                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  81                                           NULL,
  82                                           "data cannot be zero");
  83         if (!mask)
  84                 mask = &rte_flow_item_meta_mask;
  85         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
  86                                         (const uint8_t *)&nic_mask,
  87                                         sizeof(struct rte_flow_item_meta),
  88                                         error);
  89         if (ret < 0)
  90                 return ret;
  91         if (attr->ingress)
  92                 return rte_flow_error_set(error, ENOTSUP,
  93                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
  94                                           NULL,
  95                                           "pattern not supported for ingress");
  96         return 0;
  97 }
  98
  99 /**
 100  * Validate the L2 encap action.
 101  *
 102  * @param[in] action_flags
 103  *   Holds the actions detected until now.
 104  * @param[in] action
 105  *   Pointer to the encap action.
 106  * @param[in] attr
 107  *   Pointer to flow attributes
 108  * @param[out] error
 109  *   Pointer to error structure.
 110  *
 111  * @return
 112  *   0 on success, a negative errno value otherwise and rte_errno is set.
 113  */
 114 static int
 115 flow_dv_validate_action_l2_encap(uint64_t action_flags,
 116                                  const struct rte_flow_action *action,
 117                                  const struct rte_flow_attr *attr,
 118                                  struct rte_flow_error *error)
 119 {
 120         if (!(action->conf))
 121                 return rte_flow_error_set(error, EINVAL,
 122                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 123                                           "configuration cannot be null");
 124         if (action_flags & MLX5_FLOW_ACTION_DROP)
 125                 return rte_flow_error_set(error, EINVAL,
 126                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 127                                           "can't drop and encap in same flow");
 128         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 129                 return rte_flow_error_set(error, EINVAL,
 130                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 131                                           "can only have a single encap or"
 132                                           " decap action in a flow");
 133         if (attr->ingress)
 134                 return rte_flow_error_set(error, ENOTSUP,
 135                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 136                                           NULL,
 137                                           "encap action not supported for "
 138                                           "ingress");
 139         return 0;
 140 }
 141
 142 /**
 143  * Validate the L2 decap action.
 144  *
 145  * @param[in] action_flags
 146  *   Holds the actions detected until now.
 147  * @param[in] attr
 148  *   Pointer to flow attributes
 149  * @param[out] error
 150  *   Pointer to error structure.
 151  *
 152  * @return
 153  *   0 on success, a negative errno value otherwise and rte_errno is set.
 154  */
 155 static int
 156 flow_dv_validate_action_l2_decap(uint64_t action_flags,
 157                                  const struct rte_flow_attr *attr,
 158                                  struct rte_flow_error *error)
 159 {
 160         if (action_flags & MLX5_FLOW_ACTION_DROP)
 161                 return rte_flow_error_set(error, EINVAL,
 162                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 163                                           "can't drop and decap in same flow");
 164         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 165                 return rte_flow_error_set(error, EINVAL,
 166                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 167                                           "can only have a single encap or"
 168                                           " decap action in a flow");
 169         if (attr->egress)
 170                 return rte_flow_error_set(error, ENOTSUP,
 171                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 172                                           NULL,
 173                                           "decap action not supported for "
 174                                           "egress");
 175         return 0;
 176 }
 177
 178 /**
 179  * Validate the raw encap action.
 180  *
 181  * @param[in] action_flags
 182  *   Holds the actions detected until now.
 183  * @param[in] action
 184  *   Pointer to the encap action.
 185  * @param[in] attr
 186  *   Pointer to flow attributes
 187  * @param[out] error
 188  *   Pointer to error structure.
 189  *
 190  * @return
 191  *   0 on success, a negative errno value otherwise and rte_errno is set.
 192  */
 193 static int
 194 flow_dv_validate_action_raw_encap(uint64_t action_flags,
 195                                   const struct rte_flow_action *action,
 196                                   const struct rte_flow_attr *attr,
 197                                   struct rte_flow_error *error)
 198 {
 199         if (!(action->conf))
 200                 return rte_flow_error_set(error, EINVAL,
 201                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 202                                           "configuration cannot be null");
 203         if (action_flags & MLX5_FLOW_ACTION_DROP)
 204                 return rte_flow_error_set(error, EINVAL,
 205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 206                                           "can't drop and encap in same flow");
 207         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 208                 return rte_flow_error_set(error, EINVAL,
 209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 210                                           "can only have a single encap"
 211                                           " action in a flow");
 212         /* encap without preceding decap is not supported for ingress */
 213         if (attr->ingress && !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
 214                 return rte_flow_error_set(error, ENOTSUP,
 215                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 216                                           NULL,
 217                                           "encap action not supported for "
 218                                           "ingress");
 219         return 0;
 220 }
 221
 222 /**
 223  * Validate the raw decap action.
 224  *
 225  * @param[in] action_flags
 226  *   Holds the actions detected until now.
 227  * @param[in] action
 228  *   Pointer to the encap action.
 229  * @param[in] attr
 230  *   Pointer to flow attributes
 231  * @param[out] error
 232  *   Pointer to error structure.
 233  *
 234  * @return
 235  *   0 on success, a negative errno value otherwise and rte_errno is set.
 236  */
 237 static int
 238 flow_dv_validate_action_raw_decap(uint64_t action_flags,
 239                                   const struct rte_flow_action *action,
 240                                   const struct rte_flow_attr *attr,
 241                                   struct rte_flow_error *error)
 242 {
 243         if (action_flags & MLX5_FLOW_ACTION_DROP)
 244                 return rte_flow_error_set(error, EINVAL,
 245                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 246                                           "can't drop and decap in same flow");
 247         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 248                 return rte_flow_error_set(error, EINVAL,
 249                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 250                                           "can't have encap action before"
 251                                           " decap action");
 252         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
 253                 return rte_flow_error_set(error, EINVAL,
 254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 255                                           "can only have a single decap"
 256                                           " action in a flow");
 257         /* decap action is valid on egress only if it is followed by encap */
 258         if (attr->egress) {
 259                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
 260                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
 261                        action++) {
 262                 }
 263                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
 264                         return rte_flow_error_set
 265                                         (error, ENOTSUP,
 266                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 267                                          NULL, "decap action not supported"
 268                                          " for egress");
 269         }
 270         return 0;
 271 }
 272
 273
 274 /**
 275  * Find existing encap/decap resource or create and register a new one.
 276  *
 277  * @param dev[in, out]
 278  *   Pointer to rte_eth_dev structure.
 279  * @param[in, out] resource
 280  *   Pointer to encap/decap resource.
 281  * @parm[in, out] dev_flow
 282  *   Pointer to the dev_flow.
 283  * @param[out] error
 284  *   pointer to error structure.
 285  *
 286  * @return
 287  *   0 on success otherwise -errno and errno is set.
 288  */
 289 static int
 290 flow_dv_encap_decap_resource_register
 291                         (struct rte_eth_dev *dev,
 292                          struct mlx5_flow_dv_encap_decap_resource *resource,
 293                          struct mlx5_flow *dev_flow,
 294                          struct rte_flow_error *error)
 295 {
 296         struct priv *priv = dev->data->dev_private;
 297         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
 298
 299         /* Lookup a matching resource from cache. */
 300         LIST_FOREACH(cache_resource, &priv->encaps_decaps, next) {
 301                 if (resource->reformat_type == cache_resource->reformat_type &&
 302                     resource->ft_type == cache_resource->ft_type &&
 303                     resource->size == cache_resource->size &&
 304                     !memcmp((const void *)resource->buf,
 305                             (const void *)cache_resource->buf,
 306                             resource->size)) {
 307                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
 308                                 (void *)cache_resource,
 309                                 rte_atomic32_read(&cache_resource->refcnt));
 310                         rte_atomic32_inc(&cache_resource->refcnt);
 311                         dev_flow->dv.encap_decap = cache_resource;
 312                         return 0;
 313                 }
 314         }
 315         /* Register new encap/decap resource. */
 316         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
 317         if (!cache_resource)
 318                 return rte_flow_error_set(error, ENOMEM,
 319                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
 320                                           "cannot allocate resource memory");
 321         *cache_resource = *resource;
 322         cache_resource->verbs_action =
 323                 mlx5_glue->dv_create_flow_action_packet_reformat
 324                         (priv->ctx, cache_resource->size,
 325                          (cache_resource->size ? cache_resource->buf : NULL),
 326                          cache_resource->reformat_type,
 327                          cache_resource->ft_type);
 328         if (!cache_resource->verbs_action) {
 329                 rte_free(cache_resource);
 330                 return rte_flow_error_set(error, ENOMEM,
 331                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 332                                           NULL, "cannot create action");
 333         }
 334         rte_atomic32_init(&cache_resource->refcnt);
 335         rte_atomic32_inc(&cache_resource->refcnt);
 336         LIST_INSERT_HEAD(&priv->encaps_decaps, cache_resource, next);
 337         dev_flow->dv.encap_decap = cache_resource;
 338         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
 339                 (void *)cache_resource,
 340                 rte_atomic32_read(&cache_resource->refcnt));
 341         return 0;
 342 }
 343
 344 /**
 345  * Get the size of specific rte_flow_item_type
 346  *
 347  * @param[in] item_type
 348  *   Tested rte_flow_item_type.
 349  *
 350  * @return
 351  *   sizeof struct item_type, 0 if void or irrelevant.
 352  */
 353 static size_t
 354 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
 355 {
 356         size_t retval;
 357
 358         switch (item_type) {
 359         case RTE_FLOW_ITEM_TYPE_ETH:
 360                 retval = sizeof(struct rte_flow_item_eth);
 361                 break;
 362         case RTE_FLOW_ITEM_TYPE_VLAN:
 363                 retval = sizeof(struct rte_flow_item_vlan);
 364                 break;
 365         case RTE_FLOW_ITEM_TYPE_IPV4:
 366                 retval = sizeof(struct rte_flow_item_ipv4);
 367                 break;
 368         case RTE_FLOW_ITEM_TYPE_IPV6:
 369                 retval = sizeof(struct rte_flow_item_ipv6);
 370                 break;
 371         case RTE_FLOW_ITEM_TYPE_UDP:
 372                 retval = sizeof(struct rte_flow_item_udp);
 373                 break;
 374         case RTE_FLOW_ITEM_TYPE_TCP:
 375                 retval = sizeof(struct rte_flow_item_tcp);
 376                 break;
 377         case RTE_FLOW_ITEM_TYPE_VXLAN:
 378                 retval = sizeof(struct rte_flow_item_vxlan);
 379                 break;
 380         case RTE_FLOW_ITEM_TYPE_GRE:
 381                 retval = sizeof(struct rte_flow_item_gre);
 382                 break;
 383         case RTE_FLOW_ITEM_TYPE_NVGRE:
 384                 retval = sizeof(struct rte_flow_item_nvgre);
 385                 break;
 386         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 387                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
 388                 break;
 389         case RTE_FLOW_ITEM_TYPE_MPLS:
 390                 retval = sizeof(struct rte_flow_item_mpls);
 391                 break;
 392         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
 393         default:
 394                 retval = 0;
 395                 break;
 396         }
 397         return retval;
 398 }
 399
 400 #define MLX5_ENCAP_IPV4_VERSION         0x40
 401 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
 402 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
 403 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
 404 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
 405 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
 406 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
 407
 408 /**
 409  * Convert the encap action data from list of rte_flow_item to raw buffer
 410  *
 411  * @param[in] items
 412  *   Pointer to rte_flow_item objects list.
 413  * @param[out] buf
 414  *   Pointer to the output buffer.
 415  * @param[out] size
 416  *   Pointer to the output buffer size.
 417  * @param[out] error
 418  *   Pointer to the error structure.
 419  *
 420  * @return
 421  *   0 on success, a negative errno value otherwise and rte_errno is set.
 422  */
 423 static int
 424 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
 425                            size_t *size, struct rte_flow_error *error)
 426 {
 427         struct ether_hdr *eth = NULL;
 428         struct vlan_hdr *vlan = NULL;
 429         struct ipv4_hdr *ipv4 = NULL;
 430         struct ipv6_hdr *ipv6 = NULL;
 431         struct udp_hdr *udp = NULL;
 432         struct vxlan_hdr *vxlan = NULL;
 433         struct vxlan_gpe_hdr *vxlan_gpe = NULL;
 434         struct gre_hdr *gre = NULL;
 435         size_t len;
 436         size_t temp_size = 0;
 437
 438         if (!items)
 439                 return rte_flow_error_set(error, EINVAL,
 440                                           RTE_FLOW_ERROR_TYPE_ACTION,
 441                                           NULL, "invalid empty data");
 442         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 443                 len = flow_dv_get_item_len(items->type);
 444                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
 445                         return rte_flow_error_set(error, EINVAL,
 446                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 447                                                   (void *)items->type,
 448                                                   "items total size is too big"
 449                                                   " for encap action");
 450                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
 451                 switch (items->type) {
 452                 case RTE_FLOW_ITEM_TYPE_ETH:
 453                         eth = (struct ether_hdr *)&buf[temp_size];
 454                         break;
 455                 case RTE_FLOW_ITEM_TYPE_VLAN:
 456                         vlan = (struct vlan_hdr *)&buf[temp_size];
 457                         if (!eth)
 458                                 return rte_flow_error_set(error, EINVAL,
 459                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 460                                                 (void *)items->type,
 461                                                 "eth header not found");
 462                         if (!eth->ether_type)
 463                                 eth->ether_type = RTE_BE16(ETHER_TYPE_VLAN);
 464                         break;
 465                 case RTE_FLOW_ITEM_TYPE_IPV4:
 466                         ipv4 = (struct ipv4_hdr *)&buf[temp_size];
 467                         if (!vlan && !eth)
 468                                 return rte_flow_error_set(error, EINVAL,
 469                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 470                                                 (void *)items->type,
 471                                                 "neither eth nor vlan"
 472                                                 " header found");
 473                         if (vlan && !vlan->eth_proto)
 474                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv4);
 475                         else if (eth && !eth->ether_type)
 476                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv4);
 477                         if (!ipv4->version_ihl)
 478                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
 479                                                     MLX5_ENCAP_IPV4_IHL_MIN;
 480                         if (!ipv4->time_to_live)
 481                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
 482                         break;
 483                 case RTE_FLOW_ITEM_TYPE_IPV6:
 484                         ipv6 = (struct ipv6_hdr *)&buf[temp_size];
 485                         if (!vlan && !eth)
 486                                 return rte_flow_error_set(error, EINVAL,
 487                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 488                                                 (void *)items->type,
 489                                                 "neither eth nor vlan"
 490                                                 " header found");
 491                         if (vlan && !vlan->eth_proto)
 492                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv6);
 493                         else if (eth && !eth->ether_type)
 494                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv6);
 495                         if (!ipv6->vtc_flow)
 496                                 ipv6->vtc_flow =
 497                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
 498                         if (!ipv6->hop_limits)
 499                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
 500                         break;
 501                 case RTE_FLOW_ITEM_TYPE_UDP:
 502                         udp = (struct udp_hdr *)&buf[temp_size];
 503                         if (!ipv4 && !ipv6)
 504                                 return rte_flow_error_set(error, EINVAL,
 505                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 506                                                 (void *)items->type,
 507                                                 "ip header not found");
 508                         if (ipv4 && !ipv4->next_proto_id)
 509                                 ipv4->next_proto_id = IPPROTO_UDP;
 510                         else if (ipv6 && !ipv6->proto)
 511                                 ipv6->proto = IPPROTO_UDP;
 512                         break;
 513                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 514                         vxlan = (struct vxlan_hdr *)&buf[temp_size];
 515                         if (!udp)
 516                                 return rte_flow_error_set(error, EINVAL,
 517                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 518                                                 (void *)items->type,
 519                                                 "udp header not found");
 520                         if (!udp->dst_port)
 521                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
 522                         if (!vxlan->vx_flags)
 523                                 vxlan->vx_flags =
 524                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
 525                         break;
 526                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 527                         vxlan_gpe = (struct vxlan_gpe_hdr *)&buf[temp_size];
 528                         if (!udp)
 529                                 return rte_flow_error_set(error, EINVAL,
 530                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 531                                                 (void *)items->type,
 532                                                 "udp header not found");
 533                         if (!vxlan_gpe->proto)
 534                                 return rte_flow_error_set(error, EINVAL,
 535                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 536                                                 (void *)items->type,
 537                                                 "next protocol not found");
 538                         if (!udp->dst_port)
 539                                 udp->dst_port =
 540                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
 541                         if (!vxlan_gpe->vx_flags)
 542                                 vxlan_gpe->vx_flags =
 543                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
 544                         break;
 545                 case RTE_FLOW_ITEM_TYPE_GRE:
 546                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 547                         gre = (struct gre_hdr *)&buf[temp_size];
 548                         if (!gre->proto)
 549                                 return rte_flow_error_set(error, EINVAL,
 550                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 551                                                 (void *)items->type,
 552                                                 "next protocol not found");
 553                         if (!ipv4 && !ipv6)
 554                                 return rte_flow_error_set(error, EINVAL,
 555                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 556                                                 (void *)items->type,
 557                                                 "ip header not found");
 558                         if (ipv4 && !ipv4->next_proto_id)
 559                                 ipv4->next_proto_id = IPPROTO_GRE;
 560                         else if (ipv6 && !ipv6->proto)
 561                                 ipv6->proto = IPPROTO_GRE;
 562                         break;
 563                 case RTE_FLOW_ITEM_TYPE_VOID:
 564                         break;
 565                 default:
 566                         return rte_flow_error_set(error, EINVAL,
 567                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 568                                                   (void *)items->type,
 569                                                   "unsupported item type");
 570                         break;
 571                 }
 572                 temp_size += len;
 573         }
 574         *size = temp_size;
 575         return 0;
 576 }
 577
 578 /**
 579  * Convert L2 encap action to DV specification.
 580  *
 581  * @param[in] dev
 582  *   Pointer to rte_eth_dev structure.
 583  * @param[in] action
 584  *   Pointer to action structure.
 585  * @param[in, out] dev_flow
 586  *   Pointer to the mlx5_flow.
 587  * @param[out] error
 588  *   Pointer to the error structure.
 589  *
 590  * @return
 591  *   0 on success, a negative errno value otherwise and rte_errno is set.
 592  */
 593 static int
 594 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
 595                                const struct rte_flow_action *action,
 596                                struct mlx5_flow *dev_flow,
 597                                struct rte_flow_error *error)
 598 {
 599         const struct rte_flow_item *encap_data;
 600         const struct rte_flow_action_raw_encap *raw_encap_data;
 601         struct mlx5_flow_dv_encap_decap_resource res = {
 602                 .reformat_type =
 603                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
 604                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
 605         };
 606
 607         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
 608                 raw_encap_data =
 609                         (const struct rte_flow_action_raw_encap *)action->conf;
 610                 res.size = raw_encap_data->size;
 611                 memcpy(res.buf, raw_encap_data->data, res.size);
 612         } else {
 613                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
 614                         encap_data =
 615                                 ((const struct rte_flow_action_vxlan_encap *)
 616                                                 action->conf)->definition;
 617                 else
 618                         encap_data =
 619                                 ((const struct rte_flow_action_nvgre_encap *)
 620                                                 action->conf)->definition;
 621                 if (flow_dv_convert_encap_data(encap_data, res.buf,
 622                                                &res.size, error))
 623                         return -rte_errno;
 624         }
 625         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 626                 return rte_flow_error_set(error, EINVAL,
 627                                           RTE_FLOW_ERROR_TYPE_ACTION,
 628                                           NULL, "can't create L2 encap action");
 629         return 0;
 630 }
 631
 632 /**
 633  * Convert L2 decap action to DV specification.
 634  *
 635  * @param[in] dev
 636  *   Pointer to rte_eth_dev structure.
 637  * @param[in, out] dev_flow
 638  *   Pointer to the mlx5_flow.
 639  * @param[out] error
 640  *   Pointer to the error structure.
 641  *
 642  * @return
 643  *   0 on success, a negative errno value otherwise and rte_errno is set.
 644  */
 645 static int
 646 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
 647                                struct mlx5_flow *dev_flow,
 648                                struct rte_flow_error *error)
 649 {
 650         struct mlx5_flow_dv_encap_decap_resource res = {
 651                 .size = 0,
 652                 .reformat_type =
 653                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
 654                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
 655         };
 656
 657         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 658                 return rte_flow_error_set(error, EINVAL,
 659                                           RTE_FLOW_ERROR_TYPE_ACTION,
 660                                           NULL, "can't create L2 decap action");
 661         return 0;
 662 }
 663
 664 /**
 665  * Convert raw decap/encap (L3 tunnel) action to DV specification.
 666  *
 667  * @param[in] dev
 668  *   Pointer to rte_eth_dev structure.
 669  * @param[in] action
 670  *   Pointer to action structure.
 671  * @param[in, out] dev_flow
 672  *   Pointer to the mlx5_flow.
 673  * @param[in] attr
 674  *   Pointer to the flow attributes.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
 683                                 const struct rte_flow_action *action,
 684                                 struct mlx5_flow *dev_flow,
 685                                 const struct rte_flow_attr *attr,
 686                                 struct rte_flow_error *error)
 687 {
 688         const struct rte_flow_action_raw_encap *encap_data;
 689         struct mlx5_flow_dv_encap_decap_resource res;
 690
 691         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
 692         res.size = encap_data->size;
 693         memcpy(res.buf, encap_data->data, res.size);
 694         res.reformat_type = attr->egress ?
 695                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
 696                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
 697         res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
 698                                      MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
 699         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 700                 return rte_flow_error_set(error, EINVAL,
 701                                           RTE_FLOW_ERROR_TYPE_ACTION,
 702                                           NULL, "can't create encap action");
 703         return 0;
 704 }
 705
 706 /**
 707  * Verify the @p attributes will be correctly understood by the NIC and store
 708  * them in the @p flow if everything is correct.
 709  *
 710  * @param[in] dev
 711  *   Pointer to dev struct.
 712  * @param[in] attributes
 713  *   Pointer to flow attributes
 714  * @param[out] error
 715  *   Pointer to error structure.
 716  *
 717  * @return
 718  *   0 on success, a negative errno value otherwise and rte_errno is set.
 719  */
 720 static int
 721 flow_dv_validate_attributes(struct rte_eth_dev *dev,
 722                             const struct rte_flow_attr *attributes,
 723                             struct rte_flow_error *error)
 724 {
 725         struct priv *priv = dev->data->dev_private;
 726         uint32_t priority_max = priv->config.flow_prio - 1;
 727
 728         if (attributes->group)
 729                 return rte_flow_error_set(error, ENOTSUP,
 730                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
 731                                           NULL,
 732                                           "groups is not supported");
 733         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
 734             attributes->priority >= priority_max)
 735                 return rte_flow_error_set(error, ENOTSUP,
 736                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
 737                                           NULL,
 738                                           "priority out of range");
 739         if (attributes->transfer)
 740                 return rte_flow_error_set(error, ENOTSUP,
 741                                           RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
 742                                           NULL,
 743                                           "transfer is not supported");
 744         if (!(attributes->egress ^ attributes->ingress))
 745                 return rte_flow_error_set(error, ENOTSUP,
 746                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
 747                                           "must specify exactly one of "
 748                                           "ingress or egress");
 749         return 0;
 750 }
 751
 752 /**
 753  * Internal validation function. For validating both actions and items.
 754  *
 755  * @param[in] dev
 756  *   Pointer to the rte_eth_dev structure.
 757  * @param[in] attr
 758  *   Pointer to the flow attributes.
 759  * @param[in] items
 760  *   Pointer to the list of items.
 761  * @param[in] actions
 762  *   Pointer to the list of actions.
 763  * @param[out] error
 764  *   Pointer to the error structure.
 765  *
 766  * @return
 767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
 768  */
 769 static int
 770 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 771                  const struct rte_flow_item items[],
 772                  const struct rte_flow_action actions[],
 773                  struct rte_flow_error *error)
 774 {
 775         int ret;
 776         uint64_t action_flags = 0;
 777         uint64_t item_flags = 0;
 778         int tunnel = 0;
 779         uint8_t next_protocol = 0xff;
 780         int actions_n = 0;
 781
 782         if (items == NULL)
 783                 return -1;
 784         ret = flow_dv_validate_attributes(dev, attr, error);
 785         if (ret < 0)
 786                 return ret;
 787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 788                 tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
 789                 switch (items->type) {
 790                 case RTE_FLOW_ITEM_TYPE_VOID:
 791                         break;
 792                 case RTE_FLOW_ITEM_TYPE_ETH:
 793                         ret = mlx5_flow_validate_item_eth(items, item_flags,
 794                                                           error);
 795                         if (ret < 0)
 796                                 return ret;
 797                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
 798                                                MLX5_FLOW_LAYER_OUTER_L2;
 799                         break;
 800                 case RTE_FLOW_ITEM_TYPE_VLAN:
 801                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
 802                                                            error);
 803                         if (ret < 0)
 804                                 return ret;
 805                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
 806                                                MLX5_FLOW_LAYER_OUTER_VLAN;
 807                         break;
 808                 case RTE_FLOW_ITEM_TYPE_IPV4:
 809                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
 810                                                            error);
 811                         if (ret < 0)
 812                                 return ret;
 813                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
 814                                                MLX5_FLOW_LAYER_OUTER_L3_IPV4;
 815                         if (items->mask != NULL &&
 816                             ((const struct rte_flow_item_ipv4 *)
 817                              items->mask)->hdr.next_proto_id)
 818                                 next_protocol =
 819                                         ((const struct rte_flow_item_ipv4 *)
 820                                          (items->spec))->hdr.next_proto_id;
 821                         break;
 822                 case RTE_FLOW_ITEM_TYPE_IPV6:
 823                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
 824                                                            error);
 825                         if (ret < 0)
 826                                 return ret;
 827                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
 828                                                MLX5_FLOW_LAYER_OUTER_L3_IPV6;
 829                         if (items->mask != NULL &&
 830                             ((const struct rte_flow_item_ipv6 *)
 831                              items->mask)->hdr.proto)
 832                                 next_protocol =
 833                                         ((const struct rte_flow_item_ipv6 *)
 834                                          items->spec)->hdr.proto;
 835                         break;
 836                 case RTE_FLOW_ITEM_TYPE_TCP:
 837                         ret = mlx5_flow_validate_item_tcp
 838                                                 (items, item_flags,
 839                                                  next_protocol,
 840                                                  &rte_flow_item_tcp_mask,
 841                                                  error);
 842                         if (ret < 0)
 843                                 return ret;
 844                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
 845                                                MLX5_FLOW_LAYER_OUTER_L4_TCP;
 846                         break;
 847                 case RTE_FLOW_ITEM_TYPE_UDP:
 848                         ret = mlx5_flow_validate_item_udp(items, item_flags,
 849                                                           next_protocol,
 850                                                           error);
 851                         if (ret < 0)
 852                                 return ret;
 853                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
 854                                                MLX5_FLOW_LAYER_OUTER_L4_UDP;
 855                         break;
 856                 case RTE_FLOW_ITEM_TYPE_GRE:
 857                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 858                         ret = mlx5_flow_validate_item_gre(items, item_flags,
 859                                                           next_protocol, error);
 860                         if (ret < 0)
 861                                 return ret;
 862                         item_flags |= MLX5_FLOW_LAYER_GRE;
 863                         break;
 864                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 865                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 866                                                             error);
 867                         if (ret < 0)
 868                                 return ret;
 869                         item_flags |= MLX5_FLOW_LAYER_VXLAN;
 870                         break;
 871                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 872                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
 873                                                                 item_flags, dev,
 874                                                                 error);
 875                         if (ret < 0)
 876                                 return ret;
 877                         item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
 878                         break;
 879                 case RTE_FLOW_ITEM_TYPE_META:
 880                         ret = flow_dv_validate_item_meta(dev, items, attr,
 881                                                          error);
 882                         if (ret < 0)
 883                                 return ret;
 884                         item_flags |= MLX5_FLOW_ITEM_METADATA;
 885                         break;
 886                 default:
 887                         return rte_flow_error_set(error, ENOTSUP,
 888                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 889                                                   NULL, "item not supported");
 890                 }
 891         }
 892         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
 893                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
 894                         return rte_flow_error_set(error, ENOTSUP,
 895                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 896                                                   actions, "too many actions");
 897                 switch (actions->type) {
 898                 case RTE_FLOW_ACTION_TYPE_VOID:
 899                         break;
 900                 case RTE_FLOW_ACTION_TYPE_FLAG:
 901                         ret = mlx5_flow_validate_action_flag(action_flags,
 902                                                              attr, error);
 903                         if (ret < 0)
 904                                 return ret;
 905                         action_flags |= MLX5_FLOW_ACTION_FLAG;
 906                         ++actions_n;
 907                         break;
 908                 case RTE_FLOW_ACTION_TYPE_MARK:
 909                         ret = mlx5_flow_validate_action_mark(actions,
 910                                                              action_flags,
 911                                                              attr, error);
 912                         if (ret < 0)
 913                                 return ret;
 914                         action_flags |= MLX5_FLOW_ACTION_MARK;
 915                         ++actions_n;
 916                         break;
 917                 case RTE_FLOW_ACTION_TYPE_DROP:
 918                         ret = mlx5_flow_validate_action_drop(action_flags,
 919                                                              attr, error);
 920                         if (ret < 0)
 921                                 return ret;
 922                         action_flags |= MLX5_FLOW_ACTION_DROP;
 923                         ++actions_n;
 924                         break;
 925                 case RTE_FLOW_ACTION_TYPE_QUEUE:
 926                         ret = mlx5_flow_validate_action_queue(actions,
 927                                                               action_flags, dev,
 928                                                               attr, error);
 929                         if (ret < 0)
 930                                 return ret;
 931                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
 932                         ++actions_n;
 933                         break;
 934                 case RTE_FLOW_ACTION_TYPE_RSS:
 935                         ret = mlx5_flow_validate_action_rss(actions,
 936                                                             action_flags, dev,
 937                                                             attr, error);
 938                         if (ret < 0)
 939                                 return ret;
 940                         action_flags |= MLX5_FLOW_ACTION_RSS;
 941                         ++actions_n;
 942                         break;
 943                 case RTE_FLOW_ACTION_TYPE_COUNT:
 944                         ret = mlx5_flow_validate_action_count(dev, attr, error);
 945                         if (ret < 0)
 946                                 return ret;
 947                         action_flags |= MLX5_FLOW_ACTION_COUNT;
 948                         ++actions_n;
 949                         break;
 950                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
 951                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
 952                         ret = flow_dv_validate_action_l2_encap(action_flags,
 953                                                                actions, attr,
 954                                                                error);
 955                         if (ret < 0)
 956                                 return ret;
 957                         action_flags |= actions->type ==
 958                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
 959                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
 960                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
 961                         ++actions_n;
 962                         break;
 963                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
 964                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
 965                         ret = flow_dv_validate_action_l2_decap(action_flags,
 966                                                                attr, error);
 967                         if (ret < 0)
 968                                 return ret;
 969                         action_flags |= actions->type ==
 970                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
 971                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
 972                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
 973                         ++actions_n;
 974                         break;
 975                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
 976                         ret = flow_dv_validate_action_raw_encap(action_flags,
 977                                                                 actions, attr,
 978                                                                 error);
 979                         if (ret < 0)
 980                                 return ret;
 981                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
 982                         ++actions_n;
 983                         break;
 984                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
 985                         ret = flow_dv_validate_action_raw_decap(action_flags,
 986                                                                 actions, attr,
 987                                                                 error);
 988                         if (ret < 0)
 989                                 return ret;
 990                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
 991                         ++actions_n;
 992                         break;
 993                 default:
 994                         return rte_flow_error_set(error, ENOTSUP,
 995                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 996                                                   actions,
 997                                                   "action not supported");
 998                 }
 999         }
1000         if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
1001                 return rte_flow_error_set(error, EINVAL,
1002                                           RTE_FLOW_ERROR_TYPE_ACTION, actions,
1003                                           "no fate action is found");
1004         return 0;
1005 }
1006
1007 /**
1008  * Internal preparation function. Allocates the DV flow size,
1009  * this size is constant.
1010  *
1011  * @param[in] attr
1012  *   Pointer to the flow attributes.
1013  * @param[in] items
1014  *   Pointer to the list of items.
1015  * @param[in] actions
1016  *   Pointer to the list of actions.
1017  * @param[out] item_flags
1018  *   Pointer to bit mask of all items detected.
1019  * @param[out] action_flags
1020  *   Pointer to bit mask of all actions detected.
1021  * @param[out] error
1022  *   Pointer to the error structure.
1023  *
1024  * @return
1025  *   Pointer to mlx5_flow object on success,
1026  *   otherwise NULL and rte_ernno is set.
1027  */
1028 static struct mlx5_flow *
1029 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
1030                 const struct rte_flow_item items[] __rte_unused,
1031                 const struct rte_flow_action actions[] __rte_unused,
1032                 uint64_t *item_flags __rte_unused,
1033                 uint64_t *action_flags __rte_unused,
1034                 struct rte_flow_error *error)
1035 {
1036         uint32_t size = sizeof(struct mlx5_flow);
1037         struct mlx5_flow *flow;
1038
1039         flow = rte_calloc(__func__, 1, size, 0);
1040         if (!flow) {
1041                 rte_flow_error_set(error, ENOMEM,
1042                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1043                                    "not enough memory to create flow");
1044                 return NULL;
1045         }
1046         flow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);
1047         return flow;
1048 }
1049
1050 /**
1051  * Add Ethernet item to matcher and to the value.
1052  *
1053  * @param[in, out] matcher
1054  *   Flow matcher.
1055  * @param[in, out] key
1056  *   Flow matcher value.
1057  * @param[in] item
1058  *   Flow pattern to translate.
1059  * @param[in] inner
1060  *   Item is inner pattern.
1061  */
1062 static void
1063 flow_dv_translate_item_eth(void *matcher, void *key,
1064                            const struct rte_flow_item *item, int inner)
1065 {
1066         const struct rte_flow_item_eth *eth_m = item->mask;
1067         const struct rte_flow_item_eth *eth_v = item->spec;
1068         const struct rte_flow_item_eth nic_mask = {
1069                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1070                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1071                 .type = RTE_BE16(0xffff),
1072         };
1073         void *headers_m;
1074         void *headers_v;
1075         char *l24_v;
1076         unsigned int i;
1077
1078         if (!eth_v)
1079                 return;
1080         if (!eth_m)
1081                 eth_m = &nic_mask;
1082         if (inner) {
1083                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1084                                          inner_headers);
1085                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1086         } else {
1087                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1088                                          outer_headers);
1089                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1090         }
1091         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
1092                &eth_m->dst, sizeof(eth_m->dst));
1093         /* The value must be in the range of the mask. */
1094         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
1095         for (i = 0; i < sizeof(eth_m->dst); ++i)
1096                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
1097         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
1098                &eth_m->src, sizeof(eth_m->src));
1099         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
1100         /* The value must be in the range of the mask. */
1101         for (i = 0; i < sizeof(eth_m->dst); ++i)
1102                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
1103         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
1104                  rte_be_to_cpu_16(eth_m->type));
1105         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
1106         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
1107 }
1108
1109 /**
1110  * Add VLAN item to matcher and to the value.
1111  *
1112  * @param[in, out] matcher
1113  *   Flow matcher.
1114  * @param[in, out] key
1115  *   Flow matcher value.
1116  * @param[in] item
1117  *   Flow pattern to translate.
1118  * @param[in] inner
1119  *   Item is inner pattern.
1120  */
1121 static void
1122 flow_dv_translate_item_vlan(void *matcher, void *key,
1123                             const struct rte_flow_item *item,
1124                             int inner)
1125 {
1126         const struct rte_flow_item_vlan *vlan_m = item->mask;
1127         const struct rte_flow_item_vlan *vlan_v = item->spec;
1128         const struct rte_flow_item_vlan nic_mask = {
1129                 .tci = RTE_BE16(0x0fff),
1130                 .inner_type = RTE_BE16(0xffff),
1131         };
1132         void *headers_m;
1133         void *headers_v;
1134         uint16_t tci_m;
1135         uint16_t tci_v;
1136
1137         if (!vlan_v)
1138                 return;
1139         if (!vlan_m)
1140                 vlan_m = &nic_mask;
1141         if (inner) {
1142                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1143                                          inner_headers);
1144                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1145         } else {
1146                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1147                                          outer_headers);
1148                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1149         }
1150         tci_m = rte_be_to_cpu_16(vlan_m->tci);
1151         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
1152         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
1153         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
1154         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
1155         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
1156         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
1157         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
1158         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
1159         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
1160 }
1161
1162 /**
1163  * Add IPV4 item to matcher and to the value.
1164  *
1165  * @param[in, out] matcher
1166  *   Flow matcher.
1167  * @param[in, out] key
1168  *   Flow matcher value.
1169  * @param[in] item
1170  *   Flow pattern to translate.
1171  * @param[in] inner
1172  *   Item is inner pattern.
1173  */
1174 static void
1175 flow_dv_translate_item_ipv4(void *matcher, void *key,
1176                             const struct rte_flow_item *item,
1177                             int inner)
1178 {
1179         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
1180         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
1181         const struct rte_flow_item_ipv4 nic_mask = {
1182                 .hdr = {
1183                         .src_addr = RTE_BE32(0xffffffff),
1184                         .dst_addr = RTE_BE32(0xffffffff),
1185                         .type_of_service = 0xff,
1186                         .next_proto_id = 0xff,
1187                 },
1188         };
1189         void *headers_m;
1190         void *headers_v;
1191         char *l24_m;
1192         char *l24_v;
1193         uint8_t tos;
1194
1195         if (inner) {
1196                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1197                                          inner_headers);
1198                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1199         } else {
1200                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1201                                          outer_headers);
1202                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1203         }
1204         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1205         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
1206         if (!ipv4_v)
1207                 return;
1208         if (!ipv4_m)
1209                 ipv4_m = &nic_mask;
1210         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1211                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1212         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1213                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1214         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
1215         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
1216         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1217                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1218         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1219                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1220         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
1221         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
1222         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
1223         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
1224                  ipv4_m->hdr.type_of_service);
1225         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
1226         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
1227                  ipv4_m->hdr.type_of_service >> 2);
1228         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
1229         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1230                  ipv4_m->hdr.next_proto_id);
1231         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1232                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
1233 }
1234
1235 /**
1236  * Add IPV6 item to matcher and to the value.
1237  *
1238  * @param[in, out] matcher
1239  *   Flow matcher.
1240  * @param[in, out] key
1241  *   Flow matcher value.
1242  * @param[in] item
1243  *   Flow pattern to translate.
1244  * @param[in] inner
1245  *   Item is inner pattern.
1246  */
1247 static void
1248 flow_dv_translate_item_ipv6(void *matcher, void *key,
1249                             const struct rte_flow_item *item,
1250                             int inner)
1251 {
1252         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
1253         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
1254         const struct rte_flow_item_ipv6 nic_mask = {
1255                 .hdr = {
1256                         .src_addr =
1257                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1258                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1259                         .dst_addr =
1260                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1261                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1262                         .vtc_flow = RTE_BE32(0xffffffff),
1263                         .proto = 0xff,
1264                         .hop_limits = 0xff,
1265                 },
1266         };
1267         void *headers_m;
1268         void *headers_v;
1269         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1270         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1271         char *l24_m;
1272         char *l24_v;
1273         uint32_t vtc_m;
1274         uint32_t vtc_v;
1275         int i;
1276         int size;
1277
1278         if (inner) {
1279                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1280                                          inner_headers);
1281                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1282         } else {
1283                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1284                                          outer_headers);
1285                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1286         }
1287         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1288         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
1289         if (!ipv6_v)
1290                 return;
1291         if (!ipv6_m)
1292                 ipv6_m = &nic_mask;
1293         size = sizeof(ipv6_m->hdr.dst_addr);
1294         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1295                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1296         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1297                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1298         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
1299         for (i = 0; i < size; ++i)
1300                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
1301         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1302                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1303         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1304                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1305         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
1306         for (i = 0; i < size; ++i)
1307                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
1308         /* TOS. */
1309         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
1310         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
1311         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
1312         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
1313         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
1314         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
1315         /* Label. */
1316         if (inner) {
1317                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
1318                          vtc_m);
1319                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
1320                          vtc_v);
1321         } else {
1322                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
1323                          vtc_m);
1324                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
1325                          vtc_v);
1326         }
1327         /* Protocol. */
1328         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1329                  ipv6_m->hdr.proto);
1330         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1331                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
1332 }
1333
1334 /**
1335  * Add TCP item to matcher and to the value.
1336  *
1337  * @param[in, out] matcher
1338  *   Flow matcher.
1339  * @param[in, out] key
1340  *   Flow matcher value.
1341  * @param[in] item
1342  *   Flow pattern to translate.
1343  * @param[in] inner
1344  *   Item is inner pattern.
1345  */
1346 static void
1347 flow_dv_translate_item_tcp(void *matcher, void *key,
1348                            const struct rte_flow_item *item,
1349                            int inner)
1350 {
1351         const struct rte_flow_item_tcp *tcp_m = item->mask;
1352         const struct rte_flow_item_tcp *tcp_v = item->spec;
1353         void *headers_m;
1354         void *headers_v;
1355
1356         if (inner) {
1357                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1358                                          inner_headers);
1359                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1360         } else {
1361                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1362                                          outer_headers);
1363                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1364         }
1365         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1366         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
1367         if (!tcp_v)
1368                 return;
1369         if (!tcp_m)
1370                 tcp_m = &rte_flow_item_tcp_mask;
1371         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
1372                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
1373         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1374                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
1375         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
1376                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
1377         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1378                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
1379 }
1380
1381 /**
1382  * Add UDP item to matcher and to the value.
1383  *
1384  * @param[in, out] matcher
1385  *   Flow matcher.
1386  * @param[in, out] key
1387  *   Flow matcher value.
1388  * @param[in] item
1389  *   Flow pattern to translate.
1390  * @param[in] inner
1391  *   Item is inner pattern.
1392  */
1393 static void
1394 flow_dv_translate_item_udp(void *matcher, void *key,
1395                            const struct rte_flow_item *item,
1396                            int inner)
1397 {
1398         const struct rte_flow_item_udp *udp_m = item->mask;
1399         const struct rte_flow_item_udp *udp_v = item->spec;
1400         void *headers_m;
1401         void *headers_v;
1402
1403         if (inner) {
1404                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1405                                          inner_headers);
1406                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1407         } else {
1408                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1409                                          outer_headers);
1410                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1411         }
1412         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1413         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1414         if (!udp_v)
1415                 return;
1416         if (!udp_m)
1417                 udp_m = &rte_flow_item_udp_mask;
1418         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
1419                  rte_be_to_cpu_16(udp_m->hdr.src_port));
1420         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1421                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
1422         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
1423                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
1424         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1425                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
1426 }
1427
1428 /**
1429  * Add GRE item to matcher and to the value.
1430  *
1431  * @param[in, out] matcher
1432  *   Flow matcher.
1433  * @param[in, out] key
1434  *   Flow matcher value.
1435  * @param[in] item
1436  *   Flow pattern to translate.
1437  * @param[in] inner
1438  *   Item is inner pattern.
1439  */
1440 static void
1441 flow_dv_translate_item_gre(void *matcher, void *key,
1442                            const struct rte_flow_item *item,
1443                            int inner)
1444 {
1445         const struct rte_flow_item_gre *gre_m = item->mask;
1446         const struct rte_flow_item_gre *gre_v = item->spec;
1447         void *headers_m;
1448         void *headers_v;
1449         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1450         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1451
1452         if (inner) {
1453                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1454                                          inner_headers);
1455                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1456         } else {
1457                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1458                                          outer_headers);
1459                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1460         }
1461         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1462         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
1463         if (!gre_v)
1464                 return;
1465         if (!gre_m)
1466                 gre_m = &rte_flow_item_gre_mask;
1467         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
1468                  rte_be_to_cpu_16(gre_m->protocol));
1469         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
1470                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
1471 }
1472
1473 /**
1474  * Add NVGRE item to matcher and to the value.
1475  *
1476  * @param[in, out] matcher
1477  *   Flow matcher.
1478  * @param[in, out] key
1479  *   Flow matcher value.
1480  * @param[in] item
1481  *   Flow pattern to translate.
1482  * @param[in] inner
1483  *   Item is inner pattern.
1484  */
1485 static void
1486 flow_dv_translate_item_nvgre(void *matcher, void *key,
1487                              const struct rte_flow_item *item,
1488                              int inner)
1489 {
1490         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
1491         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
1492         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1493         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1494         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
1495         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
1496         char *gre_key_m;
1497         char *gre_key_v;
1498         int size;
1499         int i;
1500
1501         flow_dv_translate_item_gre(matcher, key, item, inner);
1502         if (!nvgre_v)
1503                 return;
1504         if (!nvgre_m)
1505                 nvgre_m = &rte_flow_item_nvgre_mask;
1506         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
1507         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
1508         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
1509         memcpy(gre_key_m, tni_flow_id_m, size);
1510         for (i = 0; i < size; ++i)
1511                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
1512 }
1513
1514 /**
1515  * Add VXLAN item to matcher and to the value.
1516  *
1517  * @param[in, out] matcher
1518  *   Flow matcher.
1519  * @param[in, out] key
1520  *   Flow matcher value.
1521  * @param[in] item
1522  *   Flow pattern to translate.
1523  * @param[in] inner
1524  *   Item is inner pattern.
1525  */
1526 static void
1527 flow_dv_translate_item_vxlan(void *matcher, void *key,
1528                              const struct rte_flow_item *item,
1529                              int inner)
1530 {
1531         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
1532         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
1533         void *headers_m;
1534         void *headers_v;
1535         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1536         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1537         char *vni_m;
1538         char *vni_v;
1539         uint16_t dport;
1540         int size;
1541         int i;
1542
1543         if (inner) {
1544                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1545                                          inner_headers);
1546                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1547         } else {
1548                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1549                                          outer_headers);
1550                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1551         }
1552         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
1553                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
1554         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
1555                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
1556                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
1557         }
1558         if (!vxlan_v)
1559                 return;
1560         if (!vxlan_m)
1561                 vxlan_m = &rte_flow_item_vxlan_mask;
1562         size = sizeof(vxlan_m->vni);
1563         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
1564         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
1565         memcpy(vni_m, vxlan_m->vni, size);
1566         for (i = 0; i < size; ++i)
1567                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
1568 }
1569
1570 /**
1571  * Add META item to matcher
1572  *
1573  * @param[in, out] matcher
1574  *   Flow matcher.
1575  * @param[in, out] key
1576  *   Flow matcher value.
1577  * @param[in] item
1578  *   Flow pattern to translate.
1579  * @param[in] inner
1580  *   Item is inner pattern.
1581  */
1582 static void
1583 flow_dv_translate_item_meta(void *matcher, void *key,
1584                             const struct rte_flow_item *item)
1585 {
1586         const struct rte_flow_item_meta *meta_m;
1587         const struct rte_flow_item_meta *meta_v;
1588         void *misc2_m =
1589                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
1590         void *misc2_v =
1591                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
1592
1593         meta_m = (const void *)item->mask;
1594         if (!meta_m)
1595                 meta_m = &rte_flow_item_meta_mask;
1596         meta_v = (const void *)item->spec;
1597         if (meta_v) {
1598                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
1599                          rte_be_to_cpu_32(meta_m->data));
1600                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
1601                          rte_be_to_cpu_32(meta_v->data & meta_m->data));
1602         }
1603 }
1604
1605 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
1606
1607 #define HEADER_IS_ZERO(match_criteria, headers)                              \
1608         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
1609                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1610
1611 /**
1612  * Calculate flow matcher enable bitmap.
1613  *
1614  * @param match_criteria
1615  *   Pointer to flow matcher criteria.
1616  *
1617  * @return
1618  *   Bitmap of enabled fields.
1619  */
1620 static uint8_t
1621 flow_dv_matcher_enable(uint32_t *match_criteria)
1622 {
1623         uint8_t match_criteria_enable;
1624
1625         match_criteria_enable =
1626                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1627                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
1628         match_criteria_enable |=
1629                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1630                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
1631         match_criteria_enable |=
1632                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1633                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
1634         match_criteria_enable |=
1635                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
1636                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
1637
1638         return match_criteria_enable;
1639 }
1640
1641 /**
1642  * Register the flow matcher.
1643  *
1644  * @param dev[in, out]
1645  *   Pointer to rte_eth_dev structure.
1646  * @param[in, out] matcher
1647  *   Pointer to flow matcher.
1648  * @parm[in, out] dev_flow
1649  *   Pointer to the dev_flow.
1650  * @param[out] error
1651  *   pointer to error structure.
1652  *
1653  * @return
1654  *   0 on success otherwise -errno and errno is set.
1655  */
1656 static int
1657 flow_dv_matcher_register(struct rte_eth_dev *dev,
1658                          struct mlx5_flow_dv_matcher *matcher,
1659                          struct mlx5_flow *dev_flow,
1660                          struct rte_flow_error *error)
1661 {
1662         struct priv *priv = dev->data->dev_private;
1663         struct mlx5_flow_dv_matcher *cache_matcher;
1664         struct mlx5dv_flow_matcher_attr dv_attr = {
1665                 .type = IBV_FLOW_ATTR_NORMAL,
1666                 .match_mask = (void *)&matcher->mask,
1667         };
1668
1669         /* Lookup from cache. */
1670         LIST_FOREACH(cache_matcher, &priv->matchers, next) {
1671                 if (matcher->crc == cache_matcher->crc &&
1672                     matcher->priority == cache_matcher->priority &&
1673                     matcher->egress == cache_matcher->egress &&
1674                     !memcmp((const void *)matcher->mask.buf,
1675                             (const void *)cache_matcher->mask.buf,
1676                             cache_matcher->mask.size)) {
1677                         DRV_LOG(DEBUG,
1678                                 "priority %hd use %s matcher %p: refcnt %d++",
1679                                 cache_matcher->priority,
1680                                 cache_matcher->egress ? "tx" : "rx",
1681                                 (void *)cache_matcher,
1682                                 rte_atomic32_read(&cache_matcher->refcnt));
1683                         rte_atomic32_inc(&cache_matcher->refcnt);
1684                         dev_flow->dv.matcher = cache_matcher;
1685                         return 0;
1686                 }
1687         }
1688         /* Register new matcher. */
1689         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
1690         if (!cache_matcher)
1691                 return rte_flow_error_set(error, ENOMEM,
1692                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1693                                           "cannot allocate matcher memory");
1694         *cache_matcher = *matcher;
1695         dv_attr.match_criteria_enable =
1696                 flow_dv_matcher_enable(cache_matcher->mask.buf);
1697         dv_attr.priority = matcher->priority;
1698         if (matcher->egress)
1699                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
1700         cache_matcher->matcher_object =
1701                 mlx5_glue->dv_create_flow_matcher(priv->ctx, &dv_attr);
1702         if (!cache_matcher->matcher_object) {
1703                 rte_free(cache_matcher);
1704                 return rte_flow_error_set(error, ENOMEM,
1705                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1706                                           NULL, "cannot create matcher");
1707         }
1708         rte_atomic32_inc(&cache_matcher->refcnt);
1709         LIST_INSERT_HEAD(&priv->matchers, cache_matcher, next);
1710         dev_flow->dv.matcher = cache_matcher;
1711         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
1712                 cache_matcher->priority,
1713                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
1714                 rte_atomic32_read(&cache_matcher->refcnt));
1715         return 0;
1716 }
1717
1718 /**
1719  * Fill the flow with DV spec.
1720  *
1721  * @param[in] dev
1722  *   Pointer to rte_eth_dev structure.
1723  * @param[in, out] dev_flow
1724  *   Pointer to the sub flow.
1725  * @param[in] attr
1726  *   Pointer to the flow attributes.
1727  * @param[in] items
1728  *   Pointer to the list of items.
1729  * @param[in] actions
1730  *   Pointer to the list of actions.
1731  * @param[out] error
1732  *   Pointer to the error structure.
1733  *
1734  * @return
1735  *   0 on success, a negative errno value otherwise and rte_ernno is set.
1736  */
1737 static int
1738 flow_dv_translate(struct rte_eth_dev *dev,
1739                   struct mlx5_flow *dev_flow,
1740                   const struct rte_flow_attr *attr,
1741                   const struct rte_flow_item items[],
1742                   const struct rte_flow_action actions[],
1743                   struct rte_flow_error *error)
1744 {
1745         struct priv *priv = dev->data->dev_private;
1746         struct rte_flow *flow = dev_flow->flow;
1747         uint64_t item_flags = 0;
1748         uint64_t action_flags = 0;
1749         uint64_t priority = attr->priority;
1750         struct mlx5_flow_dv_matcher matcher = {
1751                 .mask = {
1752                         .size = sizeof(matcher.mask.buf),
1753                 },
1754         };
1755         int actions_n = 0;
1756
1757         if (priority == MLX5_FLOW_PRIO_RSVD)
1758                 priority = priv->config.flow_prio - 1;
1759         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1760                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1761                 void *match_mask = matcher.mask.buf;
1762                 void *match_value = dev_flow->dv.value.buf;
1763
1764                 switch (items->type) {
1765                 case RTE_FLOW_ITEM_TYPE_ETH:
1766                         flow_dv_translate_item_eth(match_mask, match_value,
1767                                                    items, tunnel);
1768                         matcher.priority = MLX5_PRIORITY_MAP_L2;
1769                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
1770                                                MLX5_FLOW_LAYER_OUTER_L2;
1771                         break;
1772                 case RTE_FLOW_ITEM_TYPE_VLAN:
1773                         flow_dv_translate_item_vlan(match_mask, match_value,
1774                                                     items, tunnel);
1775                         matcher.priority = MLX5_PRIORITY_MAP_L2;
1776                         item_flags |= tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
1777                                                 MLX5_FLOW_LAYER_INNER_VLAN) :
1778                                                (MLX5_FLOW_LAYER_OUTER_L2 |
1779                                                 MLX5_FLOW_LAYER_OUTER_VLAN);
1780                         break;
1781                 case RTE_FLOW_ITEM_TYPE_IPV4:
1782                         flow_dv_translate_item_ipv4(match_mask, match_value,
1783                                                     items, tunnel);
1784                         matcher.priority = MLX5_PRIORITY_MAP_L3;
1785                         dev_flow->dv.hash_fields |=
1786                                 mlx5_flow_hashfields_adjust
1787                                         (dev_flow, tunnel,
1788                                          MLX5_IPV4_LAYER_TYPES,
1789                                          MLX5_IPV4_IBV_RX_HASH);
1790                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
1791                                                MLX5_FLOW_LAYER_OUTER_L3_IPV4;
1792                         break;
1793                 case RTE_FLOW_ITEM_TYPE_IPV6:
1794                         flow_dv_translate_item_ipv6(match_mask, match_value,
1795                                                     items, tunnel);
1796                         matcher.priority = MLX5_PRIORITY_MAP_L3;
1797                         dev_flow->dv.hash_fields |=
1798                                 mlx5_flow_hashfields_adjust
1799                                         (dev_flow, tunnel,
1800                                          MLX5_IPV6_LAYER_TYPES,
1801                                          MLX5_IPV6_IBV_RX_HASH);
1802                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
1803                                                MLX5_FLOW_LAYER_OUTER_L3_IPV6;
1804                         break;
1805                 case RTE_FLOW_ITEM_TYPE_TCP:
1806                         flow_dv_translate_item_tcp(match_mask, match_value,
1807                                                    items, tunnel);
1808                         matcher.priority = MLX5_PRIORITY_MAP_L4;
1809                         dev_flow->dv.hash_fields |=
1810                                 mlx5_flow_hashfields_adjust
1811                                         (dev_flow, tunnel, ETH_RSS_TCP,
1812                                          IBV_RX_HASH_SRC_PORT_TCP |
1813                                          IBV_RX_HASH_DST_PORT_TCP);
1814                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
1815                                                MLX5_FLOW_LAYER_OUTER_L4_TCP;
1816                         break;
1817                 case RTE_FLOW_ITEM_TYPE_UDP:
1818                         flow_dv_translate_item_udp(match_mask, match_value,
1819                                                    items, tunnel);
1820                         matcher.priority = MLX5_PRIORITY_MAP_L4;
1821                         dev_flow->verbs.hash_fields |=
1822                                 mlx5_flow_hashfields_adjust
1823                                         (dev_flow, tunnel, ETH_RSS_UDP,
1824                                          IBV_RX_HASH_SRC_PORT_UDP |
1825                                          IBV_RX_HASH_DST_PORT_UDP);
1826                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
1827                                                MLX5_FLOW_LAYER_OUTER_L4_UDP;
1828                         break;
1829                 case RTE_FLOW_ITEM_TYPE_GRE:
1830                         flow_dv_translate_item_gre(match_mask, match_value,
1831                                                    items, tunnel);
1832                         item_flags |= MLX5_FLOW_LAYER_GRE;
1833                         break;
1834                 case RTE_FLOW_ITEM_TYPE_NVGRE:
1835                         flow_dv_translate_item_nvgre(match_mask, match_value,
1836                                                      items, tunnel);
1837                         item_flags |= MLX5_FLOW_LAYER_GRE;
1838                         break;
1839                 case RTE_FLOW_ITEM_TYPE_VXLAN:
1840                         flow_dv_translate_item_vxlan(match_mask, match_value,
1841                                                      items, tunnel);
1842                         item_flags |= MLX5_FLOW_LAYER_VXLAN;
1843                         break;
1844                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1845                         flow_dv_translate_item_vxlan(match_mask, match_value,
1846                                                      items, tunnel);
1847                         item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
1848                         break;
1849                 case RTE_FLOW_ITEM_TYPE_META:
1850                         flow_dv_translate_item_meta(match_mask, match_value,
1851                                                     items);
1852                         item_flags |= MLX5_FLOW_ITEM_METADATA;
1853                         break;
1854                 default:
1855                         break;
1856                 }
1857         }
1858         dev_flow->layers = item_flags;
1859         /* Register matcher. */
1860         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
1861                                     matcher.mask.size);
1862         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
1863                                                      matcher.priority);
1864         matcher.egress = attr->egress;
1865         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
1866                 return -rte_errno;
1867         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
1868                 const struct rte_flow_action_queue *queue;
1869                 const struct rte_flow_action_rss *rss;
1870                 const struct rte_flow_action *action = actions;
1871                 const uint8_t *rss_key;
1872
1873                 switch (actions->type) {
1874                 case RTE_FLOW_ACTION_TYPE_VOID:
1875                         break;
1876                 case RTE_FLOW_ACTION_TYPE_FLAG:
1877                         dev_flow->dv.actions[actions_n].type =
1878                                 MLX5DV_FLOW_ACTION_TAG;
1879                         dev_flow->dv.actions[actions_n].tag_value =
1880                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
1881                         actions_n++;
1882                         action_flags |= MLX5_FLOW_ACTION_FLAG;
1883                         break;
1884                 case RTE_FLOW_ACTION_TYPE_MARK:
1885                         dev_flow->dv.actions[actions_n].type =
1886                                 MLX5DV_FLOW_ACTION_TAG;
1887                         dev_flow->dv.actions[actions_n].tag_value =
1888                                 mlx5_flow_mark_set
1889                                 (((const struct rte_flow_action_mark *)
1890                                   (actions->conf))->id);
1891                         actions_n++;
1892                         action_flags |= MLX5_FLOW_ACTION_MARK;
1893                         break;
1894                 case RTE_FLOW_ACTION_TYPE_DROP:
1895                         dev_flow->dv.actions[actions_n].type =
1896                                 MLX5DV_FLOW_ACTION_DROP;
1897                         action_flags |= MLX5_FLOW_ACTION_DROP;
1898                         break;
1899                 case RTE_FLOW_ACTION_TYPE_QUEUE:
1900                         queue = actions->conf;
1901                         flow->rss.queue_num = 1;
1902                         (*flow->queue)[0] = queue->index;
1903                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
1904                         break;
1905                 case RTE_FLOW_ACTION_TYPE_RSS:
1906                         rss = actions->conf;
1907                         if (flow->queue)
1908                                 memcpy((*flow->queue), rss->queue,
1909                                        rss->queue_num * sizeof(uint16_t));
1910                         flow->rss.queue_num = rss->queue_num;
1911                         /* NULL RSS key indicates default RSS key. */
1912                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
1913                         memcpy(flow->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
1914                         /* RSS type 0 indicates default RSS type ETH_RSS_IP. */
1915                         flow->rss.types = !rss->types ? ETH_RSS_IP : rss->types;
1916                         flow->rss.level = rss->level;
1917                         action_flags |= MLX5_FLOW_ACTION_RSS;
1918                         break;
1919                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
1920                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
1921                         if (flow_dv_create_action_l2_encap(dev, actions,
1922                                                            dev_flow, error))
1923                                 return -rte_errno;
1924                         dev_flow->dv.actions[actions_n].type =
1925                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1926                         dev_flow->dv.actions[actions_n].action =
1927                                 dev_flow->dv.encap_decap->verbs_action;
1928                         actions_n++;
1929                         action_flags |= actions->type ==
1930                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
1931                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
1932                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
1933                         break;
1934                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
1935                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
1936                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
1937                                                            error))
1938                                 return -rte_errno;
1939                         dev_flow->dv.actions[actions_n].type =
1940                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1941                         dev_flow->dv.actions[actions_n].action =
1942                                 dev_flow->dv.encap_decap->verbs_action;
1943                         actions_n++;
1944                         action_flags |= actions->type ==
1945                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
1946                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
1947                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
1948                         break;
1949                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
1950                         /* Handle encap with preceding decap. */
1951                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
1952                                 if (flow_dv_create_action_raw_encap
1953                                         (dev, actions, dev_flow, attr, error))
1954                                         return -rte_errno;
1955                                 dev_flow->dv.actions[actions_n].type =
1956                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1957                                 dev_flow->dv.actions[actions_n].action =
1958                                         dev_flow->dv.encap_decap->verbs_action;
1959                         } else {
1960                                 /* Handle encap without preceding decap. */
1961                                 if (flow_dv_create_action_l2_encap(dev, actions,
1962                                                                    dev_flow,
1963                                                                    error))
1964                                         return -rte_errno;
1965                                 dev_flow->dv.actions[actions_n].type =
1966                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1967                                 dev_flow->dv.actions[actions_n].action =
1968                                         dev_flow->dv.encap_decap->verbs_action;
1969                         }
1970                         actions_n++;
1971                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
1972                         break;
1973                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
1974                         /* Check if this decap is followed by encap. */
1975                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1976                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1977                                action++) {
1978                         }
1979                         /* Handle decap only if it isn't followed by encap. */
1980                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1981                                 if (flow_dv_create_action_l2_decap(dev,
1982                                                                    dev_flow,
1983                                                                    error))
1984                                         return -rte_errno;
1985                                 dev_flow->dv.actions[actions_n].type =
1986                                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1987                                 dev_flow->dv.actions[actions_n].action =
1988                                         dev_flow->dv.encap_decap->verbs_action;
1989                                 actions_n++;
1990                         }
1991                         /* If decap is followed by encap, handle it at encap. */
1992                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
1993                         break;
1994                 default:
1995                         break;
1996                 }
1997         }
1998         dev_flow->dv.actions_n = actions_n;
1999         flow->actions = action_flags;
2000         return 0;
2001 }
2002
2003 /**
2004  * Apply the flow to the NIC.
2005  *
2006  * @param[in] dev
2007  *   Pointer to the Ethernet device structure.
2008  * @param[in, out] flow
2009  *   Pointer to flow structure.
2010  * @param[out] error
2011  *   Pointer to error structure.
2012  *
2013  * @return
2014  *   0 on success, a negative errno value otherwise and rte_errno is set.
2015  */
2016 static int
2017 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
2018               struct rte_flow_error *error)
2019 {
2020         struct mlx5_flow_dv *dv;
2021         struct mlx5_flow *dev_flow;
2022         int n;
2023         int err;
2024
2025         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2026                 dv = &dev_flow->dv;
2027                 n = dv->actions_n;
2028                 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
2029                         dv->hrxq = mlx5_hrxq_drop_new(dev);
2030                         if (!dv->hrxq) {
2031                                 rte_flow_error_set
2032                                         (error, errno,
2033                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2034                                          "cannot get drop hash queue");
2035                                 goto error;
2036                         }
2037                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2038                         dv->actions[n].qp = dv->hrxq->qp;
2039                         n++;
2040                 } else if (flow->actions &
2041                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
2042                         struct mlx5_hrxq *hrxq;
2043                         hrxq = mlx5_hrxq_get(dev, flow->key,
2044                                              MLX5_RSS_HASH_KEY_LEN,
2045                                              dv->hash_fields,
2046                                              (*flow->queue),
2047                                              flow->rss.queue_num);
2048                         if (!hrxq)
2049                                 hrxq = mlx5_hrxq_new
2050                                         (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
2051                                          dv->hash_fields, (*flow->queue),
2052                                          flow->rss.queue_num,
2053                                          !!(dev_flow->layers &
2054                                             MLX5_FLOW_LAYER_TUNNEL));
2055                         if (!hrxq) {
2056                                 rte_flow_error_set
2057                                         (error, rte_errno,
2058                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2059                                          "cannot get hash queue");
2060                                 goto error;
2061                         }
2062                         dv->hrxq = hrxq;
2063                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2064                         dv->actions[n].qp = hrxq->qp;
2065                         n++;
2066                 }
2067                 dv->flow =
2068                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
2069                                                   (void *)&dv->value, n,
2070                                                   dv->actions);
2071                 if (!dv->flow) {
2072                         rte_flow_error_set(error, errno,
2073                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2074                                            NULL,
2075                                            "hardware refuses to create flow");
2076                         goto error;
2077                 }
2078         }
2079         return 0;
2080 error:
2081         err = rte_errno; /* Save rte_errno before cleanup. */
2082         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2083                 struct mlx5_flow_dv *dv = &dev_flow->dv;
2084                 if (dv->hrxq) {
2085                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2086                                 mlx5_hrxq_drop_release(dev);
2087                         else
2088                                 mlx5_hrxq_release(dev, dv->hrxq);
2089                         dv->hrxq = NULL;
2090                 }
2091         }
2092         rte_errno = err; /* Restore rte_errno. */
2093         return -rte_errno;
2094 }
2095
2096 /**
2097  * Release the flow matcher.
2098  *
2099  * @param dev
2100  *   Pointer to Ethernet device.
2101  * @param flow
2102  *   Pointer to mlx5_flow.
2103  *
2104  * @return
2105  *   1 while a reference on it exists, 0 when freed.
2106  */
2107 static int
2108 flow_dv_matcher_release(struct rte_eth_dev *dev,
2109                         struct mlx5_flow *flow)
2110 {
2111         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
2112
2113         assert(matcher->matcher_object);
2114         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
2115                 dev->data->port_id, (void *)matcher,
2116                 rte_atomic32_read(&matcher->refcnt));
2117         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
2118                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
2119                            (matcher->matcher_object));
2120                 LIST_REMOVE(matcher, next);
2121                 rte_free(matcher);
2122                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
2123                         dev->data->port_id, (void *)matcher);
2124                 return 0;
2125         }
2126         return 1;
2127 }
2128
2129 /**
2130  * Release an encap/decap resource.
2131  *
2132  * @param flow
2133  *   Pointer to mlx5_flow.
2134  *
2135  * @return
2136  *   1 while a reference on it exists, 0 when freed.
2137  */
2138 static int
2139 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
2140 {
2141         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
2142                                                 flow->dv.encap_decap;
2143
2144         assert(cache_resource->verbs_action);
2145         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
2146                 (void *)cache_resource,
2147                 rte_atomic32_read(&cache_resource->refcnt));
2148         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
2149                 claim_zero(mlx5_glue->destroy_flow_action
2150                                 (cache_resource->verbs_action));
2151                 LIST_REMOVE(cache_resource, next);
2152                 rte_free(cache_resource);
2153                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
2154                         (void *)cache_resource);
2155                 return 0;
2156         }
2157         return 1;
2158 }
2159
2160 /**
2161  * Remove the flow from the NIC but keeps it in memory.
2162  *
2163  * @param[in] dev
2164  *   Pointer to Ethernet device.
2165  * @param[in, out] flow
2166  *   Pointer to flow structure.
2167  */
2168 static void
2169 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
2170 {
2171         struct mlx5_flow_dv *dv;
2172         struct mlx5_flow *dev_flow;
2173
2174         if (!flow)
2175                 return;
2176         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2177                 dv = &dev_flow->dv;
2178                 if (dv->flow) {
2179                         claim_zero(mlx5_glue->destroy_flow(dv->flow));
2180                         dv->flow = NULL;
2181                 }
2182                 if (dv->hrxq) {
2183                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2184                                 mlx5_hrxq_drop_release(dev);
2185                         else
2186                                 mlx5_hrxq_release(dev, dv->hrxq);
2187                         dv->hrxq = NULL;
2188                 }
2189         }
2190         if (flow->counter)
2191                 flow->counter = NULL;
2192 }
2193
2194 /**
2195  * Remove the flow from the NIC and the memory.
2196  *
2197  * @param[in] dev
2198  *   Pointer to the Ethernet device structure.
2199  * @param[in, out] flow
2200  *   Pointer to flow structure.
2201  */
2202 static void
2203 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
2204 {
2205         struct mlx5_flow *dev_flow;
2206
2207         if (!flow)
2208                 return;
2209         flow_dv_remove(dev, flow);
2210         while (!LIST_EMPTY(&flow->dev_flows)) {
2211                 dev_flow = LIST_FIRST(&flow->dev_flows);
2212                 LIST_REMOVE(dev_flow, next);
2213                 if (dev_flow->dv.matcher)
2214                         flow_dv_matcher_release(dev, dev_flow);
2215                 if (dev_flow->dv.encap_decap)
2216                         flow_dv_encap_decap_resource_release(dev_flow);
2217                 rte_free(dev_flow);
2218         }
2219 }
2220
2221 /**
2222  * Query a flow.
2223  *
2224  * @see rte_flow_query()
2225  * @see rte_flow_ops
2226  */
2227 static int
2228 flow_dv_query(struct rte_eth_dev *dev __rte_unused,
2229               struct rte_flow *flow __rte_unused,
2230               const struct rte_flow_action *actions __rte_unused,
2231               void *data __rte_unused,
2232               struct rte_flow_error *error __rte_unused)
2233 {
2234         rte_errno = ENOTSUP;
2235         return -rte_errno;
2236 }
2237
2238
2239 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
2240         .validate = flow_dv_validate,
2241         .prepare = flow_dv_prepare,
2242         .translate = flow_dv_translate,
2243         .apply = flow_dv_apply,
2244         .remove = flow_dv_remove,
2245         .destroy = flow_dv_destroy,
2246         .query = flow_dv_query,
2247 };
2248
2249 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */