1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
87 * Pointer to the sub flow.
88 * @param[in] tunnel_decap
89 * Whether action is after tunnel decapsulation.
92 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
93 struct mlx5_flow *dev_flow, bool tunnel_decap)
95 uint64_t layers = dev_flow->handle.layers;
98 * If layers is already initialized, it means this dev_flow is the
99 * suffix flow, the layers flags is set by the prefix flow. Need to
100 * use the layer flags from prefix flow as the suffix flow may not
101 * have the user defined items as the flow is split.
104 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
106 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
108 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
115 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
116 uint8_t next_protocol = 0xff;
117 switch (item->type) {
118 case RTE_FLOW_ITEM_TYPE_GRE:
119 case RTE_FLOW_ITEM_TYPE_NVGRE:
120 case RTE_FLOW_ITEM_TYPE_VXLAN:
121 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
122 case RTE_FLOW_ITEM_TYPE_GENEVE:
123 case RTE_FLOW_ITEM_TYPE_MPLS:
127 case RTE_FLOW_ITEM_TYPE_IPV4:
130 if (item->mask != NULL &&
131 ((const struct rte_flow_item_ipv4 *)
132 item->mask)->hdr.next_proto_id)
134 ((const struct rte_flow_item_ipv4 *)
135 (item->spec))->hdr.next_proto_id &
136 ((const struct rte_flow_item_ipv4 *)
137 (item->mask))->hdr.next_proto_id;
138 if ((next_protocol == IPPROTO_IPIP ||
139 next_protocol == IPPROTO_IPV6) && tunnel_decap)
142 case RTE_FLOW_ITEM_TYPE_IPV6:
145 if (item->mask != NULL &&
146 ((const struct rte_flow_item_ipv6 *)
147 item->mask)->hdr.proto)
149 ((const struct rte_flow_item_ipv6 *)
150 (item->spec))->hdr.proto &
151 ((const struct rte_flow_item_ipv6 *)
152 (item->mask))->hdr.proto;
153 if ((next_protocol == IPPROTO_IPIP ||
154 next_protocol == IPPROTO_IPV6) && tunnel_decap)
157 case RTE_FLOW_ITEM_TYPE_UDP:
161 case RTE_FLOW_ITEM_TYPE_TCP:
173 * Convert rte_mtr_color to mlx5 color.
182 rte_col_2_mlx5_col(enum rte_color rcol)
185 case RTE_COLOR_GREEN:
186 return MLX5_FLOW_COLOR_GREEN;
187 case RTE_COLOR_YELLOW:
188 return MLX5_FLOW_COLOR_YELLOW;
190 return MLX5_FLOW_COLOR_RED;
194 return MLX5_FLOW_COLOR_UNDEFINED;
197 struct field_modify_info {
198 uint32_t size; /* Size of field in protocol header, in bytes. */
199 uint32_t offset; /* Offset of field in protocol header, in bytes. */
200 enum mlx5_modification_field id;
203 struct field_modify_info modify_eth[] = {
204 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
205 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
206 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
207 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
211 struct field_modify_info modify_vlan_out_first_vid[] = {
212 /* Size in bits !!! */
213 {12, 0, MLX5_MODI_OUT_FIRST_VID},
217 struct field_modify_info modify_ipv4[] = {
218 {1, 1, MLX5_MODI_OUT_IP_DSCP},
219 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
220 {4, 12, MLX5_MODI_OUT_SIPV4},
221 {4, 16, MLX5_MODI_OUT_DIPV4},
225 struct field_modify_info modify_ipv6[] = {
226 {1, 0, MLX5_MODI_OUT_IP_DSCP},
227 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
228 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
229 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
230 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
231 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
232 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
233 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
234 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
235 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
239 struct field_modify_info modify_udp[] = {
240 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
241 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
245 struct field_modify_info modify_tcp[] = {
246 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
247 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
248 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
249 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
254 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
255 uint8_t next_protocol, uint64_t *item_flags,
258 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
259 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
260 if (next_protocol == IPPROTO_IPIP) {
261 *item_flags |= MLX5_FLOW_LAYER_IPIP;
264 if (next_protocol == IPPROTO_IPV6) {
265 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
271 * Acquire the synchronizing object to protect multithreaded access
272 * to shared dv context. Lock occurs only if context is actually
273 * shared, i.e. we have multiport IB device and representors are
277 * Pointer to the rte_eth_dev structure.
280 flow_dv_shared_lock(struct rte_eth_dev *dev)
282 struct mlx5_priv *priv = dev->data->dev_private;
283 struct mlx5_ibv_shared *sh = priv->sh;
285 if (sh->dv_refcnt > 1) {
288 ret = pthread_mutex_lock(&sh->dv_mutex);
295 flow_dv_shared_unlock(struct rte_eth_dev *dev)
297 struct mlx5_priv *priv = dev->data->dev_private;
298 struct mlx5_ibv_shared *sh = priv->sh;
300 if (sh->dv_refcnt > 1) {
303 ret = pthread_mutex_unlock(&sh->dv_mutex);
309 /* Update VLAN's VID/PCP based on input rte_flow_action.
312 * Pointer to struct rte_flow_action.
314 * Pointer to struct rte_vlan_hdr.
317 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
318 struct rte_vlan_hdr *vlan)
321 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
323 ((const struct rte_flow_action_of_set_vlan_pcp *)
324 action->conf)->vlan_pcp;
325 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
326 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
327 vlan->vlan_tci |= vlan_tci;
328 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
330 vlan->vlan_tci |= rte_be_to_cpu_16
331 (((const struct rte_flow_action_of_set_vlan_vid *)
332 action->conf)->vlan_vid);
337 * Fetch 1, 2, 3 or 4 byte field from the byte array
338 * and return as unsigned integer in host-endian format.
341 * Pointer to data array.
343 * Size of field to extract.
346 * converted field in host endian format.
348 static inline uint32_t
349 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
358 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
362 ret = (ret << 8) | *(data + sizeof(uint16_t));
365 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
376 * Convert modify-header action to DV specification.
378 * Data length of each action is determined by provided field description
379 * and the item mask. Data bit offset and width of each action is determined
380 * by provided item mask.
383 * Pointer to item specification.
385 * Pointer to field modification information.
386 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
387 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
388 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
390 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
391 * Negative offset value sets the same offset as source offset.
392 * size field is ignored, value is taken from source field.
393 * @param[in,out] resource
394 * Pointer to the modify-header resource.
396 * Type of modification.
398 * Pointer to the error structure.
401 * 0 on success, a negative errno value otherwise and rte_errno is set.
404 flow_dv_convert_modify_action(struct rte_flow_item *item,
405 struct field_modify_info *field,
406 struct field_modify_info *dcopy,
407 struct mlx5_flow_dv_modify_hdr_resource *resource,
408 uint32_t type, struct rte_flow_error *error)
410 uint32_t i = resource->actions_num;
411 struct mlx5_modification_cmd *actions = resource->actions;
414 * The item and mask are provided in big-endian format.
415 * The fields should be presented as in big-endian format either.
416 * Mask must be always present, it defines the actual field width.
418 MLX5_ASSERT(item->mask);
419 MLX5_ASSERT(field->size);
426 if (i >= MLX5_MAX_MODIFY_NUM)
427 return rte_flow_error_set(error, EINVAL,
428 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
429 "too many items to modify");
430 /* Fetch variable byte size mask from the array. */
431 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
432 field->offset, field->size);
437 /* Deduce actual data width in bits from mask value. */
438 off_b = rte_bsf32(mask);
439 size_b = sizeof(uint32_t) * CHAR_BIT -
440 off_b - __builtin_clz(mask);
442 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
443 actions[i] = (struct mlx5_modification_cmd) {
449 /* Convert entire record to expected big-endian format. */
450 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
451 if (type == MLX5_MODIFICATION_TYPE_COPY) {
453 actions[i].dst_field = dcopy->id;
454 actions[i].dst_offset =
455 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
456 /* Convert entire record to big-endian format. */
457 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
459 MLX5_ASSERT(item->spec);
460 data = flow_dv_fetch_field((const uint8_t *)item->spec +
461 field->offset, field->size);
462 /* Shift out the trailing masked bits from data. */
463 data = (data & mask) >> off_b;
464 actions[i].data1 = rte_cpu_to_be_32(data);
468 } while (field->size);
469 if (resource->actions_num == i)
470 return rte_flow_error_set(error, EINVAL,
471 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
472 "invalid modification flow item");
473 resource->actions_num = i;
478 * Convert modify-header set IPv4 address action to DV specification.
480 * @param[in,out] resource
481 * Pointer to the modify-header resource.
483 * Pointer to action specification.
485 * Pointer to the error structure.
488 * 0 on success, a negative errno value otherwise and rte_errno is set.
491 flow_dv_convert_action_modify_ipv4
492 (struct mlx5_flow_dv_modify_hdr_resource *resource,
493 const struct rte_flow_action *action,
494 struct rte_flow_error *error)
496 const struct rte_flow_action_set_ipv4 *conf =
497 (const struct rte_flow_action_set_ipv4 *)(action->conf);
498 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
499 struct rte_flow_item_ipv4 ipv4;
500 struct rte_flow_item_ipv4 ipv4_mask;
502 memset(&ipv4, 0, sizeof(ipv4));
503 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
504 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
505 ipv4.hdr.src_addr = conf->ipv4_addr;
506 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
508 ipv4.hdr.dst_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
512 item.mask = &ipv4_mask;
513 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
514 MLX5_MODIFICATION_TYPE_SET, error);
518 * Convert modify-header set IPv6 address action to DV specification.
520 * @param[in,out] resource
521 * Pointer to the modify-header resource.
523 * Pointer to action specification.
525 * Pointer to the error structure.
528 * 0 on success, a negative errno value otherwise and rte_errno is set.
531 flow_dv_convert_action_modify_ipv6
532 (struct mlx5_flow_dv_modify_hdr_resource *resource,
533 const struct rte_flow_action *action,
534 struct rte_flow_error *error)
536 const struct rte_flow_action_set_ipv6 *conf =
537 (const struct rte_flow_action_set_ipv6 *)(action->conf);
538 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
539 struct rte_flow_item_ipv6 ipv6;
540 struct rte_flow_item_ipv6 ipv6_mask;
542 memset(&ipv6, 0, sizeof(ipv6));
543 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
544 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
545 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
546 sizeof(ipv6.hdr.src_addr));
547 memcpy(&ipv6_mask.hdr.src_addr,
548 &rte_flow_item_ipv6_mask.hdr.src_addr,
549 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
552 sizeof(ipv6.hdr.dst_addr));
553 memcpy(&ipv6_mask.hdr.dst_addr,
554 &rte_flow_item_ipv6_mask.hdr.dst_addr,
555 sizeof(ipv6.hdr.dst_addr));
558 item.mask = &ipv6_mask;
559 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
560 MLX5_MODIFICATION_TYPE_SET, error);
564 * Convert modify-header set MAC address action to DV specification.
566 * @param[in,out] resource
567 * Pointer to the modify-header resource.
569 * Pointer to action specification.
571 * Pointer to the error structure.
574 * 0 on success, a negative errno value otherwise and rte_errno is set.
577 flow_dv_convert_action_modify_mac
578 (struct mlx5_flow_dv_modify_hdr_resource *resource,
579 const struct rte_flow_action *action,
580 struct rte_flow_error *error)
582 const struct rte_flow_action_set_mac *conf =
583 (const struct rte_flow_action_set_mac *)(action->conf);
584 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
585 struct rte_flow_item_eth eth;
586 struct rte_flow_item_eth eth_mask;
588 memset(ð, 0, sizeof(eth));
589 memset(ð_mask, 0, sizeof(eth_mask));
590 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
591 memcpy(ð.src.addr_bytes, &conf->mac_addr,
592 sizeof(eth.src.addr_bytes));
593 memcpy(ð_mask.src.addr_bytes,
594 &rte_flow_item_eth_mask.src.addr_bytes,
595 sizeof(eth_mask.src.addr_bytes));
597 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
598 sizeof(eth.dst.addr_bytes));
599 memcpy(ð_mask.dst.addr_bytes,
600 &rte_flow_item_eth_mask.dst.addr_bytes,
601 sizeof(eth_mask.dst.addr_bytes));
604 item.mask = ð_mask;
605 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
606 MLX5_MODIFICATION_TYPE_SET, error);
610 * Convert modify-header set VLAN VID action to DV specification.
612 * @param[in,out] resource
613 * Pointer to the modify-header resource.
615 * Pointer to action specification.
617 * Pointer to the error structure.
620 * 0 on success, a negative errno value otherwise and rte_errno is set.
623 flow_dv_convert_action_modify_vlan_vid
624 (struct mlx5_flow_dv_modify_hdr_resource *resource,
625 const struct rte_flow_action *action,
626 struct rte_flow_error *error)
628 const struct rte_flow_action_of_set_vlan_vid *conf =
629 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
630 int i = resource->actions_num;
631 struct mlx5_modification_cmd *actions = resource->actions;
632 struct field_modify_info *field = modify_vlan_out_first_vid;
634 if (i >= MLX5_MAX_MODIFY_NUM)
635 return rte_flow_error_set(error, EINVAL,
636 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
637 "too many items to modify");
638 actions[i] = (struct mlx5_modification_cmd) {
639 .action_type = MLX5_MODIFICATION_TYPE_SET,
641 .length = field->size,
642 .offset = field->offset,
644 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
645 actions[i].data1 = conf->vlan_vid;
646 actions[i].data1 = actions[i].data1 << 16;
647 resource->actions_num = ++i;
652 * Convert modify-header set TP action to DV specification.
654 * @param[in,out] resource
655 * Pointer to the modify-header resource.
657 * Pointer to action specification.
659 * Pointer to rte_flow_item objects list.
661 * Pointer to flow attributes structure.
662 * @param[in] dev_flow
663 * Pointer to the sub flow.
664 * @param[in] tunnel_decap
665 * Whether action is after tunnel decapsulation.
667 * Pointer to the error structure.
670 * 0 on success, a negative errno value otherwise and rte_errno is set.
673 flow_dv_convert_action_modify_tp
674 (struct mlx5_flow_dv_modify_hdr_resource *resource,
675 const struct rte_flow_action *action,
676 const struct rte_flow_item *items,
677 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
678 bool tunnel_decap, struct rte_flow_error *error)
680 const struct rte_flow_action_set_tp *conf =
681 (const struct rte_flow_action_set_tp *)(action->conf);
682 struct rte_flow_item item;
683 struct rte_flow_item_udp udp;
684 struct rte_flow_item_udp udp_mask;
685 struct rte_flow_item_tcp tcp;
686 struct rte_flow_item_tcp tcp_mask;
687 struct field_modify_info *field;
690 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
692 memset(&udp, 0, sizeof(udp));
693 memset(&udp_mask, 0, sizeof(udp_mask));
694 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
695 udp.hdr.src_port = conf->port;
696 udp_mask.hdr.src_port =
697 rte_flow_item_udp_mask.hdr.src_port;
699 udp.hdr.dst_port = conf->port;
700 udp_mask.hdr.dst_port =
701 rte_flow_item_udp_mask.hdr.dst_port;
703 item.type = RTE_FLOW_ITEM_TYPE_UDP;
705 item.mask = &udp_mask;
708 MLX5_ASSERT(attr->tcp);
709 memset(&tcp, 0, sizeof(tcp));
710 memset(&tcp_mask, 0, sizeof(tcp_mask));
711 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
712 tcp.hdr.src_port = conf->port;
713 tcp_mask.hdr.src_port =
714 rte_flow_item_tcp_mask.hdr.src_port;
716 tcp.hdr.dst_port = conf->port;
717 tcp_mask.hdr.dst_port =
718 rte_flow_item_tcp_mask.hdr.dst_port;
720 item.type = RTE_FLOW_ITEM_TYPE_TCP;
722 item.mask = &tcp_mask;
725 return flow_dv_convert_modify_action(&item, field, NULL, resource,
726 MLX5_MODIFICATION_TYPE_SET, error);
730 * Convert modify-header set TTL action to DV specification.
732 * @param[in,out] resource
733 * Pointer to the modify-header resource.
735 * Pointer to action specification.
737 * Pointer to rte_flow_item objects list.
739 * Pointer to flow attributes structure.
740 * @param[in] dev_flow
741 * Pointer to the sub flow.
742 * @param[in] tunnel_decap
743 * Whether action is after tunnel decapsulation.
745 * Pointer to the error structure.
748 * 0 on success, a negative errno value otherwise and rte_errno is set.
751 flow_dv_convert_action_modify_ttl
752 (struct mlx5_flow_dv_modify_hdr_resource *resource,
753 const struct rte_flow_action *action,
754 const struct rte_flow_item *items,
755 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
756 bool tunnel_decap, struct rte_flow_error *error)
758 const struct rte_flow_action_set_ttl *conf =
759 (const struct rte_flow_action_set_ttl *)(action->conf);
760 struct rte_flow_item item;
761 struct rte_flow_item_ipv4 ipv4;
762 struct rte_flow_item_ipv4 ipv4_mask;
763 struct rte_flow_item_ipv6 ipv6;
764 struct rte_flow_item_ipv6 ipv6_mask;
765 struct field_modify_info *field;
768 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
770 memset(&ipv4, 0, sizeof(ipv4));
771 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
772 ipv4.hdr.time_to_live = conf->ttl_value;
773 ipv4_mask.hdr.time_to_live = 0xFF;
774 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
776 item.mask = &ipv4_mask;
779 MLX5_ASSERT(attr->ipv6);
780 memset(&ipv6, 0, sizeof(ipv6));
781 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
782 ipv6.hdr.hop_limits = conf->ttl_value;
783 ipv6_mask.hdr.hop_limits = 0xFF;
784 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
786 item.mask = &ipv6_mask;
789 return flow_dv_convert_modify_action(&item, field, NULL, resource,
790 MLX5_MODIFICATION_TYPE_SET, error);
794 * Convert modify-header decrement TTL action to DV specification.
796 * @param[in,out] resource
797 * Pointer to the modify-header resource.
799 * Pointer to action specification.
801 * Pointer to rte_flow_item objects list.
803 * Pointer to flow attributes structure.
804 * @param[in] dev_flow
805 * Pointer to the sub flow.
806 * @param[in] tunnel_decap
807 * Whether action is after tunnel decapsulation.
809 * Pointer to the error structure.
812 * 0 on success, a negative errno value otherwise and rte_errno is set.
815 flow_dv_convert_action_modify_dec_ttl
816 (struct mlx5_flow_dv_modify_hdr_resource *resource,
817 const struct rte_flow_item *items,
818 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
819 bool tunnel_decap, struct rte_flow_error *error)
821 struct rte_flow_item item;
822 struct rte_flow_item_ipv4 ipv4;
823 struct rte_flow_item_ipv4 ipv4_mask;
824 struct rte_flow_item_ipv6 ipv6;
825 struct rte_flow_item_ipv6 ipv6_mask;
826 struct field_modify_info *field;
829 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
831 memset(&ipv4, 0, sizeof(ipv4));
832 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
833 ipv4.hdr.time_to_live = 0xFF;
834 ipv4_mask.hdr.time_to_live = 0xFF;
835 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
837 item.mask = &ipv4_mask;
840 MLX5_ASSERT(attr->ipv6);
841 memset(&ipv6, 0, sizeof(ipv6));
842 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
843 ipv6.hdr.hop_limits = 0xFF;
844 ipv6_mask.hdr.hop_limits = 0xFF;
845 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
847 item.mask = &ipv6_mask;
850 return flow_dv_convert_modify_action(&item, field, NULL, resource,
851 MLX5_MODIFICATION_TYPE_ADD, error);
855 * Convert modify-header increment/decrement TCP Sequence number
856 * to DV specification.
858 * @param[in,out] resource
859 * Pointer to the modify-header resource.
861 * Pointer to action specification.
863 * Pointer to the error structure.
866 * 0 on success, a negative errno value otherwise and rte_errno is set.
869 flow_dv_convert_action_modify_tcp_seq
870 (struct mlx5_flow_dv_modify_hdr_resource *resource,
871 const struct rte_flow_action *action,
872 struct rte_flow_error *error)
874 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
875 uint64_t value = rte_be_to_cpu_32(*conf);
876 struct rte_flow_item item;
877 struct rte_flow_item_tcp tcp;
878 struct rte_flow_item_tcp tcp_mask;
880 memset(&tcp, 0, sizeof(tcp));
881 memset(&tcp_mask, 0, sizeof(tcp_mask));
882 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
884 * The HW has no decrement operation, only increment operation.
885 * To simulate decrement X from Y using increment operation
886 * we need to add UINT32_MAX X times to Y.
887 * Each adding of UINT32_MAX decrements Y by 1.
890 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
891 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
892 item.type = RTE_FLOW_ITEM_TYPE_TCP;
894 item.mask = &tcp_mask;
895 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
896 MLX5_MODIFICATION_TYPE_ADD, error);
900 * Convert modify-header increment/decrement TCP Acknowledgment number
901 * to DV specification.
903 * @param[in,out] resource
904 * Pointer to the modify-header resource.
906 * Pointer to action specification.
908 * Pointer to the error structure.
911 * 0 on success, a negative errno value otherwise and rte_errno is set.
914 flow_dv_convert_action_modify_tcp_ack
915 (struct mlx5_flow_dv_modify_hdr_resource *resource,
916 const struct rte_flow_action *action,
917 struct rte_flow_error *error)
919 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
920 uint64_t value = rte_be_to_cpu_32(*conf);
921 struct rte_flow_item item;
922 struct rte_flow_item_tcp tcp;
923 struct rte_flow_item_tcp tcp_mask;
925 memset(&tcp, 0, sizeof(tcp));
926 memset(&tcp_mask, 0, sizeof(tcp_mask));
927 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
929 * The HW has no decrement operation, only increment operation.
930 * To simulate decrement X from Y using increment operation
931 * we need to add UINT32_MAX X times to Y.
932 * Each adding of UINT32_MAX decrements Y by 1.
935 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
936 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
937 item.type = RTE_FLOW_ITEM_TYPE_TCP;
939 item.mask = &tcp_mask;
940 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
941 MLX5_MODIFICATION_TYPE_ADD, error);
944 static enum mlx5_modification_field reg_to_field[] = {
945 [REG_NONE] = MLX5_MODI_OUT_NONE,
946 [REG_A] = MLX5_MODI_META_DATA_REG_A,
947 [REG_B] = MLX5_MODI_META_DATA_REG_B,
948 [REG_C_0] = MLX5_MODI_META_REG_C_0,
949 [REG_C_1] = MLX5_MODI_META_REG_C_1,
950 [REG_C_2] = MLX5_MODI_META_REG_C_2,
951 [REG_C_3] = MLX5_MODI_META_REG_C_3,
952 [REG_C_4] = MLX5_MODI_META_REG_C_4,
953 [REG_C_5] = MLX5_MODI_META_REG_C_5,
954 [REG_C_6] = MLX5_MODI_META_REG_C_6,
955 [REG_C_7] = MLX5_MODI_META_REG_C_7,
959 * Convert register set to DV specification.
961 * @param[in,out] resource
962 * Pointer to the modify-header resource.
964 * Pointer to action specification.
966 * Pointer to the error structure.
969 * 0 on success, a negative errno value otherwise and rte_errno is set.
972 flow_dv_convert_action_set_reg
973 (struct mlx5_flow_dv_modify_hdr_resource *resource,
974 const struct rte_flow_action *action,
975 struct rte_flow_error *error)
977 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
978 struct mlx5_modification_cmd *actions = resource->actions;
979 uint32_t i = resource->actions_num;
981 if (i >= MLX5_MAX_MODIFY_NUM)
982 return rte_flow_error_set(error, EINVAL,
983 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
984 "too many items to modify");
985 MLX5_ASSERT(conf->id != REG_NONE);
986 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
987 actions[i] = (struct mlx5_modification_cmd) {
988 .action_type = MLX5_MODIFICATION_TYPE_SET,
989 .field = reg_to_field[conf->id],
991 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
992 actions[i].data1 = rte_cpu_to_be_32(conf->data);
994 resource->actions_num = i;
999 * Convert SET_TAG action to DV specification.
1002 * Pointer to the rte_eth_dev structure.
1003 * @param[in,out] resource
1004 * Pointer to the modify-header resource.
1006 * Pointer to action specification.
1008 * Pointer to the error structure.
1011 * 0 on success, a negative errno value otherwise and rte_errno is set.
1014 flow_dv_convert_action_set_tag
1015 (struct rte_eth_dev *dev,
1016 struct mlx5_flow_dv_modify_hdr_resource *resource,
1017 const struct rte_flow_action_set_tag *conf,
1018 struct rte_flow_error *error)
1020 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1021 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1022 struct rte_flow_item item = {
1026 struct field_modify_info reg_c_x[] = {
1029 enum mlx5_modification_field reg_type;
1032 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1035 MLX5_ASSERT(ret != REG_NONE);
1036 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1037 reg_type = reg_to_field[ret];
1038 MLX5_ASSERT(reg_type > 0);
1039 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1040 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1041 MLX5_MODIFICATION_TYPE_SET, error);
1045 * Convert internal COPY_REG action to DV specification.
1048 * Pointer to the rte_eth_dev structure.
1049 * @param[in,out] res
1050 * Pointer to the modify-header resource.
1052 * Pointer to action specification.
1054 * Pointer to the error structure.
1057 * 0 on success, a negative errno value otherwise and rte_errno is set.
1060 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1061 struct mlx5_flow_dv_modify_hdr_resource *res,
1062 const struct rte_flow_action *action,
1063 struct rte_flow_error *error)
1065 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1066 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1067 struct rte_flow_item item = {
1071 struct field_modify_info reg_src[] = {
1072 {4, 0, reg_to_field[conf->src]},
1075 struct field_modify_info reg_dst = {
1077 .id = reg_to_field[conf->dst],
1079 /* Adjust reg_c[0] usage according to reported mask. */
1080 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1081 struct mlx5_priv *priv = dev->data->dev_private;
1082 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1084 MLX5_ASSERT(reg_c0);
1085 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1086 if (conf->dst == REG_C_0) {
1087 /* Copy to reg_c[0], within mask only. */
1088 reg_dst.offset = rte_bsf32(reg_c0);
1090 * Mask is ignoring the enianness, because
1091 * there is no conversion in datapath.
1093 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1094 /* Copy from destination lower bits to reg_c[0]. */
1095 mask = reg_c0 >> reg_dst.offset;
1097 /* Copy from destination upper bits to reg_c[0]. */
1098 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1099 rte_fls_u32(reg_c0));
1102 mask = rte_cpu_to_be_32(reg_c0);
1103 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1104 /* Copy from reg_c[0] to destination lower bits. */
1107 /* Copy from reg_c[0] to destination upper bits. */
1108 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1109 (rte_fls_u32(reg_c0) -
1114 return flow_dv_convert_modify_action(&item,
1115 reg_src, ®_dst, res,
1116 MLX5_MODIFICATION_TYPE_COPY,
1121 * Convert MARK action to DV specification. This routine is used
1122 * in extensive metadata only and requires metadata register to be
1123 * handled. In legacy mode hardware tag resource is engaged.
1126 * Pointer to the rte_eth_dev structure.
1128 * Pointer to MARK action specification.
1129 * @param[in,out] resource
1130 * Pointer to the modify-header resource.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1139 const struct rte_flow_action_mark *conf,
1140 struct mlx5_flow_dv_modify_hdr_resource *resource,
1141 struct rte_flow_error *error)
1143 struct mlx5_priv *priv = dev->data->dev_private;
1144 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1145 priv->sh->dv_mark_mask);
1146 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1147 struct rte_flow_item item = {
1151 struct field_modify_info reg_c_x[] = {
1152 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158 return rte_flow_error_set(error, EINVAL,
1159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1160 NULL, "zero mark action mask");
1161 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1164 MLX5_ASSERT(reg > 0);
1165 if (reg == REG_C_0) {
1166 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1167 uint32_t shl_c0 = rte_bsf32(msk_c0);
1169 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1170 mask = rte_cpu_to_be_32(mask) & msk_c0;
1171 mask = rte_cpu_to_be_32(mask << shl_c0);
1173 reg_c_x[0].id = reg_to_field[reg];
1174 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1175 MLX5_MODIFICATION_TYPE_SET, error);
1179 * Get metadata register index for specified steering domain.
1182 * Pointer to the rte_eth_dev structure.
1184 * Attributes of flow to determine steering domain.
1186 * Pointer to the error structure.
1189 * positive index on success, a negative errno value otherwise
1190 * and rte_errno is set.
1192 static enum modify_reg
1193 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1194 const struct rte_flow_attr *attr,
1195 struct rte_flow_error *error)
1198 mlx5_flow_get_reg_id(dev, attr->transfer ?
1202 MLX5_METADATA_RX, 0, error);
1204 return rte_flow_error_set(error,
1205 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1206 NULL, "unavailable "
1207 "metadata register");
1212 * Convert SET_META action to DV specification.
1215 * Pointer to the rte_eth_dev structure.
1216 * @param[in,out] resource
1217 * Pointer to the modify-header resource.
1219 * Attributes of flow that includes this item.
1221 * Pointer to action specification.
1223 * Pointer to the error structure.
1226 * 0 on success, a negative errno value otherwise and rte_errno is set.
1229 flow_dv_convert_action_set_meta
1230 (struct rte_eth_dev *dev,
1231 struct mlx5_flow_dv_modify_hdr_resource *resource,
1232 const struct rte_flow_attr *attr,
1233 const struct rte_flow_action_set_meta *conf,
1234 struct rte_flow_error *error)
1236 uint32_t data = conf->data;
1237 uint32_t mask = conf->mask;
1238 struct rte_flow_item item = {
1242 struct field_modify_info reg_c_x[] = {
1245 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1250 * In datapath code there is no endianness
1251 * coversions for perfromance reasons, all
1252 * pattern conversions are done in rte_flow.
1254 if (reg == REG_C_0) {
1255 struct mlx5_priv *priv = dev->data->dev_private;
1256 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1259 MLX5_ASSERT(msk_c0);
1260 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1261 shl_c0 = rte_bsf32(msk_c0);
1263 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1267 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1269 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1270 /* The routine expects parameters in memory as big-endian ones. */
1271 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1272 MLX5_MODIFICATION_TYPE_SET, error);
1276 * Convert modify-header set IPv4 DSCP action to DV specification.
1278 * @param[in,out] resource
1279 * Pointer to the modify-header resource.
1281 * Pointer to action specification.
1283 * Pointer to the error structure.
1286 * 0 on success, a negative errno value otherwise and rte_errno is set.
1289 flow_dv_convert_action_modify_ipv4_dscp
1290 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1291 const struct rte_flow_action *action,
1292 struct rte_flow_error *error)
1294 const struct rte_flow_action_set_dscp *conf =
1295 (const struct rte_flow_action_set_dscp *)(action->conf);
1296 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1297 struct rte_flow_item_ipv4 ipv4;
1298 struct rte_flow_item_ipv4 ipv4_mask;
1300 memset(&ipv4, 0, sizeof(ipv4));
1301 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1302 ipv4.hdr.type_of_service = conf->dscp;
1303 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1305 item.mask = &ipv4_mask;
1306 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1307 MLX5_MODIFICATION_TYPE_SET, error);
1311 * Convert modify-header set IPv6 DSCP action to DV specification.
1313 * @param[in,out] resource
1314 * Pointer to the modify-header resource.
1316 * Pointer to action specification.
1318 * Pointer to the error structure.
1321 * 0 on success, a negative errno value otherwise and rte_errno is set.
1324 flow_dv_convert_action_modify_ipv6_dscp
1325 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1326 const struct rte_flow_action *action,
1327 struct rte_flow_error *error)
1329 const struct rte_flow_action_set_dscp *conf =
1330 (const struct rte_flow_action_set_dscp *)(action->conf);
1331 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1332 struct rte_flow_item_ipv6 ipv6;
1333 struct rte_flow_item_ipv6 ipv6_mask;
1335 memset(&ipv6, 0, sizeof(ipv6));
1336 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1338 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1339 * rdma-core only accept the DSCP bits byte aligned start from
1340 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1341 * bits in IPv6 case as rdma-core requires byte aligned value.
1343 ipv6.hdr.vtc_flow = conf->dscp;
1344 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1346 item.mask = &ipv6_mask;
1347 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1348 MLX5_MODIFICATION_TYPE_SET, error);
1352 * Validate MARK item.
1355 * Pointer to the rte_eth_dev structure.
1357 * Item specification.
1359 * Attributes of flow that includes this item.
1361 * Pointer to error structure.
1364 * 0 on success, a negative errno value otherwise and rte_errno is set.
1367 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1368 const struct rte_flow_item *item,
1369 const struct rte_flow_attr *attr __rte_unused,
1370 struct rte_flow_error *error)
1372 struct mlx5_priv *priv = dev->data->dev_private;
1373 struct mlx5_dev_config *config = &priv->config;
1374 const struct rte_flow_item_mark *spec = item->spec;
1375 const struct rte_flow_item_mark *mask = item->mask;
1376 const struct rte_flow_item_mark nic_mask = {
1377 .id = priv->sh->dv_mark_mask,
1381 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1382 return rte_flow_error_set(error, ENOTSUP,
1383 RTE_FLOW_ERROR_TYPE_ITEM, item,
1384 "extended metadata feature"
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1392 return rte_flow_error_set(error, ENOTSUP,
1393 RTE_FLOW_ERROR_TYPE_ITEM, item,
1394 "extended metadata register"
1395 " isn't available");
1396 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1400 return rte_flow_error_set(error, EINVAL,
1401 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1403 "data cannot be empty");
1404 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1405 return rte_flow_error_set(error, EINVAL,
1406 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1408 "mark id exceeds the limit");
1412 return rte_flow_error_set(error, EINVAL,
1413 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1414 "mask cannot be zero");
1416 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1417 (const uint8_t *)&nic_mask,
1418 sizeof(struct rte_flow_item_mark),
1426 * Validate META item.
1429 * Pointer to the rte_eth_dev structure.
1431 * Item specification.
1433 * Attributes of flow that includes this item.
1435 * Pointer to error structure.
1438 * 0 on success, a negative errno value otherwise and rte_errno is set.
1441 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1442 const struct rte_flow_item *item,
1443 const struct rte_flow_attr *attr,
1444 struct rte_flow_error *error)
1446 struct mlx5_priv *priv = dev->data->dev_private;
1447 struct mlx5_dev_config *config = &priv->config;
1448 const struct rte_flow_item_meta *spec = item->spec;
1449 const struct rte_flow_item_meta *mask = item->mask;
1450 struct rte_flow_item_meta nic_mask = {
1457 return rte_flow_error_set(error, EINVAL,
1458 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1460 "data cannot be empty");
1461 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1462 if (!mlx5_flow_ext_mreg_supported(dev))
1463 return rte_flow_error_set(error, ENOTSUP,
1464 RTE_FLOW_ERROR_TYPE_ITEM, item,
1465 "extended metadata register"
1466 " isn't supported");
1467 reg = flow_dv_get_metadata_reg(dev, attr, error);
1471 return rte_flow_error_set(error, ENOTSUP,
1472 RTE_FLOW_ERROR_TYPE_ITEM, item,
1476 nic_mask.data = priv->sh->dv_meta_mask;
1479 mask = &rte_flow_item_meta_mask;
1481 return rte_flow_error_set(error, EINVAL,
1482 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1483 "mask cannot be zero");
1485 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1486 (const uint8_t *)&nic_mask,
1487 sizeof(struct rte_flow_item_meta),
1493 * Validate TAG item.
1496 * Pointer to the rte_eth_dev structure.
1498 * Item specification.
1500 * Attributes of flow that includes this item.
1502 * Pointer to error structure.
1505 * 0 on success, a negative errno value otherwise and rte_errno is set.
1508 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1509 const struct rte_flow_item *item,
1510 const struct rte_flow_attr *attr __rte_unused,
1511 struct rte_flow_error *error)
1513 const struct rte_flow_item_tag *spec = item->spec;
1514 const struct rte_flow_item_tag *mask = item->mask;
1515 const struct rte_flow_item_tag nic_mask = {
1516 .data = RTE_BE32(UINT32_MAX),
1521 if (!mlx5_flow_ext_mreg_supported(dev))
1522 return rte_flow_error_set(error, ENOTSUP,
1523 RTE_FLOW_ERROR_TYPE_ITEM, item,
1524 "extensive metadata register"
1525 " isn't supported");
1527 return rte_flow_error_set(error, EINVAL,
1528 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1530 "data cannot be empty");
1532 mask = &rte_flow_item_tag_mask;
1534 return rte_flow_error_set(error, EINVAL,
1535 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1536 "mask cannot be zero");
1538 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1539 (const uint8_t *)&nic_mask,
1540 sizeof(struct rte_flow_item_tag),
1544 if (mask->index != 0xff)
1545 return rte_flow_error_set(error, EINVAL,
1546 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1547 "partial mask for tag index"
1548 " is not supported");
1549 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1552 MLX5_ASSERT(ret != REG_NONE);
1557 * Validate vport item.
1560 * Pointer to the rte_eth_dev structure.
1562 * Item specification.
1564 * Attributes of flow that includes this item.
1565 * @param[in] item_flags
1566 * Bit-fields that holds the items detected until now.
1568 * Pointer to error structure.
1571 * 0 on success, a negative errno value otherwise and rte_errno is set.
1574 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1575 const struct rte_flow_item *item,
1576 const struct rte_flow_attr *attr,
1577 uint64_t item_flags,
1578 struct rte_flow_error *error)
1580 const struct rte_flow_item_port_id *spec = item->spec;
1581 const struct rte_flow_item_port_id *mask = item->mask;
1582 const struct rte_flow_item_port_id switch_mask = {
1585 struct mlx5_priv *esw_priv;
1586 struct mlx5_priv *dev_priv;
1589 if (!attr->transfer)
1590 return rte_flow_error_set(error, EINVAL,
1591 RTE_FLOW_ERROR_TYPE_ITEM,
1593 "match on port id is valid only"
1594 " when transfer flag is enabled");
1595 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1596 return rte_flow_error_set(error, ENOTSUP,
1597 RTE_FLOW_ERROR_TYPE_ITEM, item,
1598 "multiple source ports are not"
1601 mask = &switch_mask;
1602 if (mask->id != 0xffffffff)
1603 return rte_flow_error_set(error, ENOTSUP,
1604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1606 "no support for partial mask on"
1608 ret = mlx5_flow_item_acceptable
1609 (item, (const uint8_t *)mask,
1610 (const uint8_t *)&rte_flow_item_port_id_mask,
1611 sizeof(struct rte_flow_item_port_id),
1617 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1619 return rte_flow_error_set(error, rte_errno,
1620 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1621 "failed to obtain E-Switch info for"
1623 dev_priv = mlx5_dev_to_eswitch_info(dev);
1625 return rte_flow_error_set(error, rte_errno,
1626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1628 "failed to obtain E-Switch info");
1629 if (esw_priv->domain_id != dev_priv->domain_id)
1630 return rte_flow_error_set(error, EINVAL,
1631 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1632 "cannot match on a port from a"
1633 " different E-Switch");
1638 * Validate GTP item.
1641 * Pointer to the rte_eth_dev structure.
1643 * Item specification.
1644 * @param[in] item_flags
1645 * Bit-fields that holds the items detected until now.
1647 * Pointer to error structure.
1650 * 0 on success, a negative errno value otherwise and rte_errno is set.
1653 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1654 const struct rte_flow_item *item,
1655 uint64_t item_flags,
1656 struct rte_flow_error *error)
1658 struct mlx5_priv *priv = dev->data->dev_private;
1659 const struct rte_flow_item_gtp *mask = item->mask;
1660 const struct rte_flow_item_gtp nic_mask = {
1662 .teid = RTE_BE32(0xffffffff),
1665 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1666 return rte_flow_error_set(error, ENOTSUP,
1667 RTE_FLOW_ERROR_TYPE_ITEM, item,
1668 "GTP support is not enabled");
1669 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "multiple tunnel layers not"
1674 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1675 return rte_flow_error_set(error, EINVAL,
1676 RTE_FLOW_ERROR_TYPE_ITEM, item,
1677 "no outer UDP layer found");
1679 mask = &rte_flow_item_gtp_mask;
1680 return mlx5_flow_item_acceptable
1681 (item, (const uint8_t *)mask,
1682 (const uint8_t *)&nic_mask,
1683 sizeof(struct rte_flow_item_gtp),
1688 * Validate the pop VLAN action.
1691 * Pointer to the rte_eth_dev structure.
1692 * @param[in] action_flags
1693 * Holds the actions detected until now.
1695 * Pointer to the pop vlan action.
1696 * @param[in] item_flags
1697 * The items found in this flow rule.
1699 * Pointer to flow attributes.
1701 * Pointer to error structure.
1704 * 0 on success, a negative errno value otherwise and rte_errno is set.
1707 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1708 uint64_t action_flags,
1709 const struct rte_flow_action *action,
1710 uint64_t item_flags,
1711 const struct rte_flow_attr *attr,
1712 struct rte_flow_error *error)
1714 const struct mlx5_priv *priv = dev->data->dev_private;
1718 if (!priv->sh->pop_vlan_action)
1719 return rte_flow_error_set(error, ENOTSUP,
1720 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1722 "pop vlan action is not supported");
1724 return rte_flow_error_set(error, ENOTSUP,
1725 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1727 "pop vlan action not supported for "
1729 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1730 return rte_flow_error_set(error, ENOTSUP,
1731 RTE_FLOW_ERROR_TYPE_ACTION, action,
1732 "no support for multiple VLAN "
1734 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1735 return rte_flow_error_set(error, ENOTSUP,
1736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1738 "cannot pop vlan without a "
1739 "match on (outer) vlan in the flow");
1740 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1741 return rte_flow_error_set(error, EINVAL,
1742 RTE_FLOW_ERROR_TYPE_ACTION, action,
1743 "wrong action order, port_id should "
1744 "be after pop VLAN action");
1745 if (!attr->transfer && priv->representor)
1746 return rte_flow_error_set(error, ENOTSUP,
1747 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1748 "pop vlan action for VF representor "
1749 "not supported on NIC table");
1754 * Get VLAN default info from vlan match info.
1757 * the list of item specifications.
1759 * pointer VLAN info to fill to.
1762 * 0 on success, a negative errno value otherwise and rte_errno is set.
1765 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1766 struct rte_vlan_hdr *vlan)
1768 const struct rte_flow_item_vlan nic_mask = {
1769 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1770 MLX5DV_FLOW_VLAN_VID_MASK),
1771 .inner_type = RTE_BE16(0xffff),
1776 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1777 int type = items->type;
1779 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1780 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1783 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1784 const struct rte_flow_item_vlan *vlan_m = items->mask;
1785 const struct rte_flow_item_vlan *vlan_v = items->spec;
1789 /* Only full match values are accepted */
1790 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1791 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1792 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1794 rte_be_to_cpu_16(vlan_v->tci &
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1797 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1798 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1799 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1801 rte_be_to_cpu_16(vlan_v->tci &
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1804 if (vlan_m->inner_type == nic_mask.inner_type)
1805 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1806 vlan_m->inner_type);
1811 * Validate the push VLAN action.
1814 * Pointer to the rte_eth_dev structure.
1815 * @param[in] action_flags
1816 * Holds the actions detected until now.
1817 * @param[in] item_flags
1818 * The items found in this flow rule.
1820 * Pointer to the action structure.
1822 * Pointer to flow attributes
1824 * Pointer to error structure.
1827 * 0 on success, a negative errno value otherwise and rte_errno is set.
1830 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1831 uint64_t action_flags,
1832 uint64_t item_flags __rte_unused,
1833 const struct rte_flow_action *action,
1834 const struct rte_flow_attr *attr,
1835 struct rte_flow_error *error)
1837 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1838 const struct mlx5_priv *priv = dev->data->dev_private;
1840 if (!attr->transfer && attr->ingress)
1841 return rte_flow_error_set(error, ENOTSUP,
1842 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1844 "push VLAN action not supported for "
1846 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1847 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1848 return rte_flow_error_set(error, EINVAL,
1849 RTE_FLOW_ERROR_TYPE_ACTION, action,
1850 "invalid vlan ethertype");
1851 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1852 return rte_flow_error_set(error, ENOTSUP,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "no support for multiple VLAN "
1856 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1857 return rte_flow_error_set(error, EINVAL,
1858 RTE_FLOW_ERROR_TYPE_ACTION, action,
1859 "wrong action order, port_id should "
1860 "be after push VLAN");
1861 if (!attr->transfer && priv->representor)
1862 return rte_flow_error_set(error, ENOTSUP,
1863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1864 "push vlan action for VF representor "
1865 "not supported on NIC table");
1871 * Validate the set VLAN PCP.
1873 * @param[in] action_flags
1874 * Holds the actions detected until now.
1875 * @param[in] actions
1876 * Pointer to the list of actions remaining in the flow rule.
1878 * Pointer to error structure.
1881 * 0 on success, a negative errno value otherwise and rte_errno is set.
1884 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1885 const struct rte_flow_action actions[],
1886 struct rte_flow_error *error)
1888 const struct rte_flow_action *action = actions;
1889 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1891 if (conf->vlan_pcp > 7)
1892 return rte_flow_error_set(error, EINVAL,
1893 RTE_FLOW_ERROR_TYPE_ACTION, action,
1894 "VLAN PCP value is too big");
1895 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1896 return rte_flow_error_set(error, ENOTSUP,
1897 RTE_FLOW_ERROR_TYPE_ACTION, action,
1898 "set VLAN PCP action must follow "
1899 "the push VLAN action");
1900 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1901 return rte_flow_error_set(error, ENOTSUP,
1902 RTE_FLOW_ERROR_TYPE_ACTION, action,
1903 "Multiple VLAN PCP modification are "
1905 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1906 return rte_flow_error_set(error, EINVAL,
1907 RTE_FLOW_ERROR_TYPE_ACTION, action,
1908 "wrong action order, port_id should "
1909 "be after set VLAN PCP");
1914 * Validate the set VLAN VID.
1916 * @param[in] item_flags
1917 * Holds the items detected in this rule.
1918 * @param[in] action_flags
1919 * Holds the actions detected until now.
1920 * @param[in] actions
1921 * Pointer to the list of actions remaining in the flow rule.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1930 uint64_t action_flags,
1931 const struct rte_flow_action actions[],
1932 struct rte_flow_error *error)
1934 const struct rte_flow_action *action = actions;
1935 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1937 if (conf->vlan_vid > RTE_BE16(0xFFE))
1938 return rte_flow_error_set(error, EINVAL,
1939 RTE_FLOW_ERROR_TYPE_ACTION, action,
1940 "VLAN VID value is too big");
1941 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1942 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1943 return rte_flow_error_set(error, ENOTSUP,
1944 RTE_FLOW_ERROR_TYPE_ACTION, action,
1945 "set VLAN VID action must follow push"
1946 " VLAN action or match on VLAN item");
1947 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1948 return rte_flow_error_set(error, ENOTSUP,
1949 RTE_FLOW_ERROR_TYPE_ACTION, action,
1950 "Multiple VLAN VID modifications are "
1952 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1953 return rte_flow_error_set(error, EINVAL,
1954 RTE_FLOW_ERROR_TYPE_ACTION, action,
1955 "wrong action order, port_id should "
1956 "be after set VLAN VID");
1961 * Validate the FLAG action.
1964 * Pointer to the rte_eth_dev structure.
1965 * @param[in] action_flags
1966 * Holds the actions detected until now.
1968 * Pointer to flow attributes
1970 * Pointer to error structure.
1973 * 0 on success, a negative errno value otherwise and rte_errno is set.
1976 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1977 uint64_t action_flags,
1978 const struct rte_flow_attr *attr,
1979 struct rte_flow_error *error)
1981 struct mlx5_priv *priv = dev->data->dev_private;
1982 struct mlx5_dev_config *config = &priv->config;
1985 /* Fall back if no extended metadata register support. */
1986 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1987 return mlx5_flow_validate_action_flag(action_flags, attr,
1989 /* Extensive metadata mode requires registers. */
1990 if (!mlx5_flow_ext_mreg_supported(dev))
1991 return rte_flow_error_set(error, ENOTSUP,
1992 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1993 "no metadata registers "
1994 "to support flag action");
1995 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1996 return rte_flow_error_set(error, ENOTSUP,
1997 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1998 "extended metadata register"
1999 " isn't available");
2000 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2003 MLX5_ASSERT(ret > 0);
2004 if (action_flags & MLX5_FLOW_ACTION_MARK)
2005 return rte_flow_error_set(error, EINVAL,
2006 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2007 "can't mark and flag in same flow");
2008 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2009 return rte_flow_error_set(error, EINVAL,
2010 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2012 " actions in same flow");
2017 * Validate MARK action.
2020 * Pointer to the rte_eth_dev structure.
2022 * Pointer to action.
2023 * @param[in] action_flags
2024 * Holds the actions detected until now.
2026 * Pointer to flow attributes
2028 * Pointer to error structure.
2031 * 0 on success, a negative errno value otherwise and rte_errno is set.
2034 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2035 const struct rte_flow_action *action,
2036 uint64_t action_flags,
2037 const struct rte_flow_attr *attr,
2038 struct rte_flow_error *error)
2040 struct mlx5_priv *priv = dev->data->dev_private;
2041 struct mlx5_dev_config *config = &priv->config;
2042 const struct rte_flow_action_mark *mark = action->conf;
2045 /* Fall back if no extended metadata register support. */
2046 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2047 return mlx5_flow_validate_action_mark(action, action_flags,
2049 /* Extensive metadata mode requires registers. */
2050 if (!mlx5_flow_ext_mreg_supported(dev))
2051 return rte_flow_error_set(error, ENOTSUP,
2052 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2053 "no metadata registers "
2054 "to support mark action");
2055 if (!priv->sh->dv_mark_mask)
2056 return rte_flow_error_set(error, ENOTSUP,
2057 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2058 "extended metadata register"
2059 " isn't available");
2060 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2063 MLX5_ASSERT(ret > 0);
2065 return rte_flow_error_set(error, EINVAL,
2066 RTE_FLOW_ERROR_TYPE_ACTION, action,
2067 "configuration cannot be null");
2068 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2069 return rte_flow_error_set(error, EINVAL,
2070 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2072 "mark id exceeds the limit");
2073 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2074 return rte_flow_error_set(error, EINVAL,
2075 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2076 "can't flag and mark in same flow");
2077 if (action_flags & MLX5_FLOW_ACTION_MARK)
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2080 "can't have 2 mark actions in same"
2086 * Validate SET_META action.
2089 * Pointer to the rte_eth_dev structure.
2091 * Pointer to the action structure.
2092 * @param[in] action_flags
2093 * Holds the actions detected until now.
2095 * Pointer to flow attributes
2097 * Pointer to error structure.
2100 * 0 on success, a negative errno value otherwise and rte_errno is set.
2103 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2104 const struct rte_flow_action *action,
2105 uint64_t action_flags __rte_unused,
2106 const struct rte_flow_attr *attr,
2107 struct rte_flow_error *error)
2109 const struct rte_flow_action_set_meta *conf;
2110 uint32_t nic_mask = UINT32_MAX;
2113 if (!mlx5_flow_ext_mreg_supported(dev))
2114 return rte_flow_error_set(error, ENOTSUP,
2115 RTE_FLOW_ERROR_TYPE_ACTION, action,
2116 "extended metadata register"
2117 " isn't supported");
2118 reg = flow_dv_get_metadata_reg(dev, attr, error);
2121 if (reg != REG_A && reg != REG_B) {
2122 struct mlx5_priv *priv = dev->data->dev_private;
2124 nic_mask = priv->sh->dv_meta_mask;
2126 if (!(action->conf))
2127 return rte_flow_error_set(error, EINVAL,
2128 RTE_FLOW_ERROR_TYPE_ACTION, action,
2129 "configuration cannot be null");
2130 conf = (const struct rte_flow_action_set_meta *)action->conf;
2132 return rte_flow_error_set(error, EINVAL,
2133 RTE_FLOW_ERROR_TYPE_ACTION, action,
2134 "zero mask doesn't have any effect");
2135 if (conf->mask & ~nic_mask)
2136 return rte_flow_error_set(error, EINVAL,
2137 RTE_FLOW_ERROR_TYPE_ACTION, action,
2138 "meta data must be within reg C0");
2143 * Validate SET_TAG action.
2146 * Pointer to the rte_eth_dev structure.
2148 * Pointer to the action structure.
2149 * @param[in] action_flags
2150 * Holds the actions detected until now.
2152 * Pointer to flow attributes
2154 * Pointer to error structure.
2157 * 0 on success, a negative errno value otherwise and rte_errno is set.
2160 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2161 const struct rte_flow_action *action,
2162 uint64_t action_flags,
2163 const struct rte_flow_attr *attr,
2164 struct rte_flow_error *error)
2166 const struct rte_flow_action_set_tag *conf;
2167 const uint64_t terminal_action_flags =
2168 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2169 MLX5_FLOW_ACTION_RSS;
2172 if (!mlx5_flow_ext_mreg_supported(dev))
2173 return rte_flow_error_set(error, ENOTSUP,
2174 RTE_FLOW_ERROR_TYPE_ACTION, action,
2175 "extensive metadata register"
2176 " isn't supported");
2177 if (!(action->conf))
2178 return rte_flow_error_set(error, EINVAL,
2179 RTE_FLOW_ERROR_TYPE_ACTION, action,
2180 "configuration cannot be null");
2181 conf = (const struct rte_flow_action_set_tag *)action->conf;
2183 return rte_flow_error_set(error, EINVAL,
2184 RTE_FLOW_ERROR_TYPE_ACTION, action,
2185 "zero mask doesn't have any effect");
2186 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2189 if (!attr->transfer && attr->ingress &&
2190 (action_flags & terminal_action_flags))
2191 return rte_flow_error_set(error, EINVAL,
2192 RTE_FLOW_ERROR_TYPE_ACTION, action,
2193 "set_tag has no effect"
2194 " with terminal actions");
2199 * Validate count action.
2202 * Pointer to rte_eth_dev structure.
2204 * Pointer to error structure.
2207 * 0 on success, a negative errno value otherwise and rte_errno is set.
2210 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2211 struct rte_flow_error *error)
2213 struct mlx5_priv *priv = dev->data->dev_private;
2215 if (!priv->config.devx)
2217 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2221 return rte_flow_error_set
2223 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2225 "count action not supported");
2229 * Validate the L2 encap action.
2232 * Pointer to the rte_eth_dev structure.
2233 * @param[in] action_flags
2234 * Holds the actions detected until now.
2236 * Pointer to the action structure.
2238 * Pointer to flow attributes.
2240 * Pointer to error structure.
2243 * 0 on success, a negative errno value otherwise and rte_errno is set.
2246 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2247 uint64_t action_flags,
2248 const struct rte_flow_action *action,
2249 const struct rte_flow_attr *attr,
2250 struct rte_flow_error *error)
2252 const struct mlx5_priv *priv = dev->data->dev_private;
2254 if (!(action->conf))
2255 return rte_flow_error_set(error, EINVAL,
2256 RTE_FLOW_ERROR_TYPE_ACTION, action,
2257 "configuration cannot be null");
2258 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2259 return rte_flow_error_set(error, EINVAL,
2260 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2261 "can only have a single encap action "
2263 if (!attr->transfer && priv->representor)
2264 return rte_flow_error_set(error, ENOTSUP,
2265 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2266 "encap action for VF representor "
2267 "not supported on NIC table");
2272 * Validate a decap action.
2275 * Pointer to the rte_eth_dev structure.
2276 * @param[in] action_flags
2277 * Holds the actions detected until now.
2279 * Pointer to flow attributes
2281 * Pointer to error structure.
2284 * 0 on success, a negative errno value otherwise and rte_errno is set.
2287 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2288 uint64_t action_flags,
2289 const struct rte_flow_attr *attr,
2290 struct rte_flow_error *error)
2292 const struct mlx5_priv *priv = dev->data->dev_private;
2294 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2295 return rte_flow_error_set(error, ENOTSUP,
2296 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2298 MLX5_FLOW_ACTION_DECAP ? "can only "
2299 "have a single decap action" : "decap "
2300 "after encap is not supported");
2301 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2302 return rte_flow_error_set(error, EINVAL,
2303 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304 "can't have decap action after"
2307 return rte_flow_error_set(error, ENOTSUP,
2308 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2310 "decap action not supported for "
2312 if (!attr->transfer && priv->representor)
2313 return rte_flow_error_set(error, ENOTSUP,
2314 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2315 "decap action for VF representor "
2316 "not supported on NIC table");
2320 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2323 * Validate the raw encap and decap actions.
2326 * Pointer to the rte_eth_dev structure.
2328 * Pointer to the decap action.
2330 * Pointer to the encap action.
2332 * Pointer to flow attributes
2333 * @param[in/out] action_flags
2334 * Holds the actions detected until now.
2335 * @param[out] actions_n
2336 * pointer to the number of actions counter.
2338 * Pointer to error structure.
2341 * 0 on success, a negative errno value otherwise and rte_errno is set.
2344 flow_dv_validate_action_raw_encap_decap
2345 (struct rte_eth_dev *dev,
2346 const struct rte_flow_action_raw_decap *decap,
2347 const struct rte_flow_action_raw_encap *encap,
2348 const struct rte_flow_attr *attr, uint64_t *action_flags,
2349 int *actions_n, struct rte_flow_error *error)
2351 const struct mlx5_priv *priv = dev->data->dev_private;
2354 if (encap && (!encap->size || !encap->data))
2355 return rte_flow_error_set(error, EINVAL,
2356 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2357 "raw encap data cannot be empty");
2358 if (decap && encap) {
2359 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2360 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2363 else if (encap->size <=
2364 MLX5_ENCAPSULATION_DECISION_SIZE &&
2366 MLX5_ENCAPSULATION_DECISION_SIZE)
2369 else if (encap->size >
2370 MLX5_ENCAPSULATION_DECISION_SIZE &&
2372 MLX5_ENCAPSULATION_DECISION_SIZE)
2373 /* 2 L2 actions: encap and decap. */
2376 return rte_flow_error_set(error,
2378 RTE_FLOW_ERROR_TYPE_ACTION,
2379 NULL, "unsupported too small "
2380 "raw decap and too small raw "
2381 "encap combination");
2384 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2388 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2392 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2393 return rte_flow_error_set(error, ENOTSUP,
2394 RTE_FLOW_ERROR_TYPE_ACTION,
2396 "small raw encap size");
2397 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2398 return rte_flow_error_set(error, EINVAL,
2399 RTE_FLOW_ERROR_TYPE_ACTION,
2401 "more than one encap action");
2402 if (!attr->transfer && priv->representor)
2403 return rte_flow_error_set
2405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2406 "encap action for VF representor "
2407 "not supported on NIC table");
2408 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2415 * Find existing encap/decap resource or create and register a new one.
2417 * @param[in, out] dev
2418 * Pointer to rte_eth_dev structure.
2419 * @param[in, out] resource
2420 * Pointer to encap/decap resource.
2421 * @parm[in, out] dev_flow
2422 * Pointer to the dev_flow.
2424 * pointer to error structure.
2427 * 0 on success otherwise -errno and errno is set.
2430 flow_dv_encap_decap_resource_register
2431 (struct rte_eth_dev *dev,
2432 struct mlx5_flow_dv_encap_decap_resource *resource,
2433 struct mlx5_flow *dev_flow,
2434 struct rte_flow_error *error)
2436 struct mlx5_priv *priv = dev->data->dev_private;
2437 struct mlx5_ibv_shared *sh = priv->sh;
2438 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2439 struct mlx5dv_dr_domain *domain;
2441 resource->flags = dev_flow->dv.group ? 0 : 1;
2442 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2443 domain = sh->fdb_domain;
2444 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2445 domain = sh->rx_domain;
2447 domain = sh->tx_domain;
2448 /* Lookup a matching resource from cache. */
2449 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2450 if (resource->reformat_type == cache_resource->reformat_type &&
2451 resource->ft_type == cache_resource->ft_type &&
2452 resource->flags == cache_resource->flags &&
2453 resource->size == cache_resource->size &&
2454 !memcmp((const void *)resource->buf,
2455 (const void *)cache_resource->buf,
2457 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2458 (void *)cache_resource,
2459 rte_atomic32_read(&cache_resource->refcnt));
2460 rte_atomic32_inc(&cache_resource->refcnt);
2461 dev_flow->handle.dvh.encap_decap = cache_resource;
2465 /* Register new encap/decap resource. */
2466 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2467 if (!cache_resource)
2468 return rte_flow_error_set(error, ENOMEM,
2469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2470 "cannot allocate resource memory");
2471 *cache_resource = *resource;
2472 cache_resource->verbs_action =
2473 mlx5_glue->dv_create_flow_action_packet_reformat
2474 (sh->ctx, cache_resource->reformat_type,
2475 cache_resource->ft_type, domain, cache_resource->flags,
2476 cache_resource->size,
2477 (cache_resource->size ? cache_resource->buf : NULL));
2478 if (!cache_resource->verbs_action) {
2479 rte_free(cache_resource);
2480 return rte_flow_error_set(error, ENOMEM,
2481 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2482 NULL, "cannot create action");
2484 rte_atomic32_init(&cache_resource->refcnt);
2485 rte_atomic32_inc(&cache_resource->refcnt);
2486 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2487 dev_flow->handle.dvh.encap_decap = cache_resource;
2488 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2489 (void *)cache_resource,
2490 rte_atomic32_read(&cache_resource->refcnt));
2495 * Find existing table jump resource or create and register a new one.
2497 * @param[in, out] dev
2498 * Pointer to rte_eth_dev structure.
2499 * @param[in, out] tbl
2500 * Pointer to flow table resource.
2501 * @parm[in, out] dev_flow
2502 * Pointer to the dev_flow.
2504 * pointer to error structure.
2507 * 0 on success otherwise -errno and errno is set.
2510 flow_dv_jump_tbl_resource_register
2511 (struct rte_eth_dev *dev __rte_unused,
2512 struct mlx5_flow_tbl_resource *tbl,
2513 struct mlx5_flow *dev_flow,
2514 struct rte_flow_error *error)
2516 struct mlx5_flow_tbl_data_entry *tbl_data =
2517 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2521 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2523 tbl_data->jump.action =
2524 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2526 if (!tbl_data->jump.action)
2527 return rte_flow_error_set(error, ENOMEM,
2528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2529 NULL, "cannot create jump action");
2530 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2531 (void *)&tbl_data->jump, cnt);
2533 MLX5_ASSERT(tbl_data->jump.action);
2534 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2535 (void *)&tbl_data->jump, cnt);
2537 rte_atomic32_inc(&tbl_data->jump.refcnt);
2538 dev_flow->handle.dvh.jump = &tbl_data->jump;
2543 * Find existing table port ID resource or create and register a new one.
2545 * @param[in, out] dev
2546 * Pointer to rte_eth_dev structure.
2547 * @param[in, out] resource
2548 * Pointer to port ID action resource.
2549 * @parm[in, out] dev_flow
2550 * Pointer to the dev_flow.
2552 * pointer to error structure.
2555 * 0 on success otherwise -errno and errno is set.
2558 flow_dv_port_id_action_resource_register
2559 (struct rte_eth_dev *dev,
2560 struct mlx5_flow_dv_port_id_action_resource *resource,
2561 struct mlx5_flow *dev_flow,
2562 struct rte_flow_error *error)
2564 struct mlx5_priv *priv = dev->data->dev_private;
2565 struct mlx5_ibv_shared *sh = priv->sh;
2566 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2568 /* Lookup a matching resource from cache. */
2569 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2570 if (resource->port_id == cache_resource->port_id) {
2571 DRV_LOG(DEBUG, "port id action resource resource %p: "
2573 (void *)cache_resource,
2574 rte_atomic32_read(&cache_resource->refcnt));
2575 rte_atomic32_inc(&cache_resource->refcnt);
2576 dev_flow->handle.dvh.port_id_action = cache_resource;
2580 /* Register new port id action resource. */
2581 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2582 if (!cache_resource)
2583 return rte_flow_error_set(error, ENOMEM,
2584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2585 "cannot allocate resource memory");
2586 *cache_resource = *resource;
2588 * Depending on rdma_core version the glue routine calls
2589 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2590 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2592 cache_resource->action =
2593 mlx5_glue->dr_create_flow_action_dest_port
2594 (priv->sh->fdb_domain, resource->port_id);
2595 if (!cache_resource->action) {
2596 rte_free(cache_resource);
2597 return rte_flow_error_set(error, ENOMEM,
2598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2599 NULL, "cannot create action");
2601 rte_atomic32_init(&cache_resource->refcnt);
2602 rte_atomic32_inc(&cache_resource->refcnt);
2603 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2604 dev_flow->handle.dvh.port_id_action = cache_resource;
2605 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2606 (void *)cache_resource,
2607 rte_atomic32_read(&cache_resource->refcnt));
2612 * Find existing push vlan resource or create and register a new one.
2614 * @param [in, out] dev
2615 * Pointer to rte_eth_dev structure.
2616 * @param[in, out] resource
2617 * Pointer to port ID action resource.
2618 * @parm[in, out] dev_flow
2619 * Pointer to the dev_flow.
2621 * pointer to error structure.
2624 * 0 on success otherwise -errno and errno is set.
2627 flow_dv_push_vlan_action_resource_register
2628 (struct rte_eth_dev *dev,
2629 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2630 struct mlx5_flow *dev_flow,
2631 struct rte_flow_error *error)
2633 struct mlx5_priv *priv = dev->data->dev_private;
2634 struct mlx5_ibv_shared *sh = priv->sh;
2635 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2636 struct mlx5dv_dr_domain *domain;
2638 /* Lookup a matching resource from cache. */
2639 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2640 if (resource->vlan_tag == cache_resource->vlan_tag &&
2641 resource->ft_type == cache_resource->ft_type) {
2642 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2644 (void *)cache_resource,
2645 rte_atomic32_read(&cache_resource->refcnt));
2646 rte_atomic32_inc(&cache_resource->refcnt);
2647 dev_flow->handle.dvh.push_vlan_res = cache_resource;
2651 /* Register new push_vlan action resource. */
2652 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2653 if (!cache_resource)
2654 return rte_flow_error_set(error, ENOMEM,
2655 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2656 "cannot allocate resource memory");
2657 *cache_resource = *resource;
2658 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2659 domain = sh->fdb_domain;
2660 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2661 domain = sh->rx_domain;
2663 domain = sh->tx_domain;
2664 cache_resource->action =
2665 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2666 resource->vlan_tag);
2667 if (!cache_resource->action) {
2668 rte_free(cache_resource);
2669 return rte_flow_error_set(error, ENOMEM,
2670 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2671 NULL, "cannot create action");
2673 rte_atomic32_init(&cache_resource->refcnt);
2674 rte_atomic32_inc(&cache_resource->refcnt);
2675 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2676 dev_flow->handle.dvh.push_vlan_res = cache_resource;
2677 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2678 (void *)cache_resource,
2679 rte_atomic32_read(&cache_resource->refcnt));
2683 * Get the size of specific rte_flow_item_type
2685 * @param[in] item_type
2686 * Tested rte_flow_item_type.
2689 * sizeof struct item_type, 0 if void or irrelevant.
2692 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2696 switch (item_type) {
2697 case RTE_FLOW_ITEM_TYPE_ETH:
2698 retval = sizeof(struct rte_flow_item_eth);
2700 case RTE_FLOW_ITEM_TYPE_VLAN:
2701 retval = sizeof(struct rte_flow_item_vlan);
2703 case RTE_FLOW_ITEM_TYPE_IPV4:
2704 retval = sizeof(struct rte_flow_item_ipv4);
2706 case RTE_FLOW_ITEM_TYPE_IPV6:
2707 retval = sizeof(struct rte_flow_item_ipv6);
2709 case RTE_FLOW_ITEM_TYPE_UDP:
2710 retval = sizeof(struct rte_flow_item_udp);
2712 case RTE_FLOW_ITEM_TYPE_TCP:
2713 retval = sizeof(struct rte_flow_item_tcp);
2715 case RTE_FLOW_ITEM_TYPE_VXLAN:
2716 retval = sizeof(struct rte_flow_item_vxlan);
2718 case RTE_FLOW_ITEM_TYPE_GRE:
2719 retval = sizeof(struct rte_flow_item_gre);
2721 case RTE_FLOW_ITEM_TYPE_NVGRE:
2722 retval = sizeof(struct rte_flow_item_nvgre);
2724 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2725 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2727 case RTE_FLOW_ITEM_TYPE_MPLS:
2728 retval = sizeof(struct rte_flow_item_mpls);
2730 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2738 #define MLX5_ENCAP_IPV4_VERSION 0x40
2739 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2740 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2741 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2742 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2743 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2744 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2747 * Convert the encap action data from list of rte_flow_item to raw buffer
2750 * Pointer to rte_flow_item objects list.
2752 * Pointer to the output buffer.
2754 * Pointer to the output buffer size.
2756 * Pointer to the error structure.
2759 * 0 on success, a negative errno value otherwise and rte_errno is set.
2762 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2763 size_t *size, struct rte_flow_error *error)
2765 struct rte_ether_hdr *eth = NULL;
2766 struct rte_vlan_hdr *vlan = NULL;
2767 struct rte_ipv4_hdr *ipv4 = NULL;
2768 struct rte_ipv6_hdr *ipv6 = NULL;
2769 struct rte_udp_hdr *udp = NULL;
2770 struct rte_vxlan_hdr *vxlan = NULL;
2771 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2772 struct rte_gre_hdr *gre = NULL;
2774 size_t temp_size = 0;
2777 return rte_flow_error_set(error, EINVAL,
2778 RTE_FLOW_ERROR_TYPE_ACTION,
2779 NULL, "invalid empty data");
2780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2781 len = flow_dv_get_item_len(items->type);
2782 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2783 return rte_flow_error_set(error, EINVAL,
2784 RTE_FLOW_ERROR_TYPE_ACTION,
2785 (void *)items->type,
2786 "items total size is too big"
2787 " for encap action");
2788 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2789 switch (items->type) {
2790 case RTE_FLOW_ITEM_TYPE_ETH:
2791 eth = (struct rte_ether_hdr *)&buf[temp_size];
2793 case RTE_FLOW_ITEM_TYPE_VLAN:
2794 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2796 return rte_flow_error_set(error, EINVAL,
2797 RTE_FLOW_ERROR_TYPE_ACTION,
2798 (void *)items->type,
2799 "eth header not found");
2800 if (!eth->ether_type)
2801 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2803 case RTE_FLOW_ITEM_TYPE_IPV4:
2804 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2806 return rte_flow_error_set(error, EINVAL,
2807 RTE_FLOW_ERROR_TYPE_ACTION,
2808 (void *)items->type,
2809 "neither eth nor vlan"
2811 if (vlan && !vlan->eth_proto)
2812 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2813 else if (eth && !eth->ether_type)
2814 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2815 if (!ipv4->version_ihl)
2816 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2817 MLX5_ENCAP_IPV4_IHL_MIN;
2818 if (!ipv4->time_to_live)
2819 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2821 case RTE_FLOW_ITEM_TYPE_IPV6:
2822 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2824 return rte_flow_error_set(error, EINVAL,
2825 RTE_FLOW_ERROR_TYPE_ACTION,
2826 (void *)items->type,
2827 "neither eth nor vlan"
2829 if (vlan && !vlan->eth_proto)
2830 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2831 else if (eth && !eth->ether_type)
2832 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2833 if (!ipv6->vtc_flow)
2835 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2836 if (!ipv6->hop_limits)
2837 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2839 case RTE_FLOW_ITEM_TYPE_UDP:
2840 udp = (struct rte_udp_hdr *)&buf[temp_size];
2842 return rte_flow_error_set(error, EINVAL,
2843 RTE_FLOW_ERROR_TYPE_ACTION,
2844 (void *)items->type,
2845 "ip header not found");
2846 if (ipv4 && !ipv4->next_proto_id)
2847 ipv4->next_proto_id = IPPROTO_UDP;
2848 else if (ipv6 && !ipv6->proto)
2849 ipv6->proto = IPPROTO_UDP;
2851 case RTE_FLOW_ITEM_TYPE_VXLAN:
2852 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2854 return rte_flow_error_set(error, EINVAL,
2855 RTE_FLOW_ERROR_TYPE_ACTION,
2856 (void *)items->type,
2857 "udp header not found");
2859 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2860 if (!vxlan->vx_flags)
2862 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2864 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2865 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2867 return rte_flow_error_set(error, EINVAL,
2868 RTE_FLOW_ERROR_TYPE_ACTION,
2869 (void *)items->type,
2870 "udp header not found");
2871 if (!vxlan_gpe->proto)
2872 return rte_flow_error_set(error, EINVAL,
2873 RTE_FLOW_ERROR_TYPE_ACTION,
2874 (void *)items->type,
2875 "next protocol not found");
2878 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2879 if (!vxlan_gpe->vx_flags)
2880 vxlan_gpe->vx_flags =
2881 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2883 case RTE_FLOW_ITEM_TYPE_GRE:
2884 case RTE_FLOW_ITEM_TYPE_NVGRE:
2885 gre = (struct rte_gre_hdr *)&buf[temp_size];
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION,
2889 (void *)items->type,
2890 "next protocol not found");
2892 return rte_flow_error_set(error, EINVAL,
2893 RTE_FLOW_ERROR_TYPE_ACTION,
2894 (void *)items->type,
2895 "ip header not found");
2896 if (ipv4 && !ipv4->next_proto_id)
2897 ipv4->next_proto_id = IPPROTO_GRE;
2898 else if (ipv6 && !ipv6->proto)
2899 ipv6->proto = IPPROTO_GRE;
2901 case RTE_FLOW_ITEM_TYPE_VOID:
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 (void *)items->type,
2907 "unsupported item type");
2917 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2919 struct rte_ether_hdr *eth = NULL;
2920 struct rte_vlan_hdr *vlan = NULL;
2921 struct rte_ipv6_hdr *ipv6 = NULL;
2922 struct rte_udp_hdr *udp = NULL;
2926 eth = (struct rte_ether_hdr *)data;
2927 next_hdr = (char *)(eth + 1);
2928 proto = RTE_BE16(eth->ether_type);
2931 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2932 vlan = (struct rte_vlan_hdr *)next_hdr;
2933 proto = RTE_BE16(vlan->eth_proto);
2934 next_hdr += sizeof(struct rte_vlan_hdr);
2937 /* HW calculates IPv4 csum. no need to proceed */
2938 if (proto == RTE_ETHER_TYPE_IPV4)
2941 /* non IPv4/IPv6 header. not supported */
2942 if (proto != RTE_ETHER_TYPE_IPV6) {
2943 return rte_flow_error_set(error, ENOTSUP,
2944 RTE_FLOW_ERROR_TYPE_ACTION,
2945 NULL, "Cannot offload non IPv4/IPv6");
2948 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2950 /* ignore non UDP */
2951 if (ipv6->proto != IPPROTO_UDP)
2954 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2955 udp->dgram_cksum = 0;
2961 * Convert L2 encap action to DV specification.
2964 * Pointer to rte_eth_dev structure.
2966 * Pointer to action structure.
2967 * @param[in, out] dev_flow
2968 * Pointer to the mlx5_flow.
2969 * @param[in] transfer
2970 * Mark if the flow is E-Switch flow.
2972 * Pointer to the error structure.
2975 * 0 on success, a negative errno value otherwise and rte_errno is set.
2978 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2979 const struct rte_flow_action *action,
2980 struct mlx5_flow *dev_flow,
2982 struct rte_flow_error *error)
2984 const struct rte_flow_item *encap_data;
2985 const struct rte_flow_action_raw_encap *raw_encap_data;
2986 struct mlx5_flow_dv_encap_decap_resource res = {
2988 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2989 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2990 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2993 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2995 (const struct rte_flow_action_raw_encap *)action->conf;
2996 res.size = raw_encap_data->size;
2997 memcpy(res.buf, raw_encap_data->data, res.size);
2999 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3001 ((const struct rte_flow_action_vxlan_encap *)
3002 action->conf)->definition;
3005 ((const struct rte_flow_action_nvgre_encap *)
3006 action->conf)->definition;
3007 if (flow_dv_convert_encap_data(encap_data, res.buf,
3011 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3013 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION,
3016 NULL, "can't create L2 encap action");
3021 * Convert L2 decap action to DV specification.
3024 * Pointer to rte_eth_dev structure.
3025 * @param[in, out] dev_flow
3026 * Pointer to the mlx5_flow.
3027 * @param[in] transfer
3028 * Mark if the flow is E-Switch flow.
3030 * Pointer to the error structure.
3033 * 0 on success, a negative errno value otherwise and rte_errno is set.
3036 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3037 struct mlx5_flow *dev_flow,
3039 struct rte_flow_error *error)
3041 struct mlx5_flow_dv_encap_decap_resource res = {
3044 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3045 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3046 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3049 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 NULL, "can't create L2 decap action");
3057 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3060 * Pointer to rte_eth_dev structure.
3062 * Pointer to action structure.
3063 * @param[in, out] dev_flow
3064 * Pointer to the mlx5_flow.
3066 * Pointer to the flow attributes.
3068 * Pointer to the error structure.
3071 * 0 on success, a negative errno value otherwise and rte_errno is set.
3074 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3075 const struct rte_flow_action *action,
3076 struct mlx5_flow *dev_flow,
3077 const struct rte_flow_attr *attr,
3078 struct rte_flow_error *error)
3080 const struct rte_flow_action_raw_encap *encap_data;
3081 struct mlx5_flow_dv_encap_decap_resource res;
3083 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3084 res.size = encap_data->size;
3085 memcpy(res.buf, encap_data->data, res.size);
3086 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3087 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3088 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3090 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3092 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3093 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3094 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3095 return rte_flow_error_set(error, EINVAL,
3096 RTE_FLOW_ERROR_TYPE_ACTION,
3097 NULL, "can't create encap action");
3102 * Create action push VLAN.
3105 * Pointer to rte_eth_dev structure.
3107 * Pointer to the flow attributes.
3109 * Pointer to the vlan to push to the Ethernet header.
3110 * @param[in, out] dev_flow
3111 * Pointer to the mlx5_flow.
3113 * Pointer to the error structure.
3116 * 0 on success, a negative errno value otherwise and rte_errno is set.
3119 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3120 const struct rte_flow_attr *attr,
3121 const struct rte_vlan_hdr *vlan,
3122 struct mlx5_flow *dev_flow,
3123 struct rte_flow_error *error)
3125 struct mlx5_flow_dv_push_vlan_action_resource res;
3128 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3131 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3133 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3134 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3135 return flow_dv_push_vlan_action_resource_register
3136 (dev, &res, dev_flow, error);
3140 * Validate the modify-header actions.
3142 * @param[in] action_flags
3143 * Holds the actions detected until now.
3145 * Pointer to the modify action.
3147 * Pointer to error structure.
3150 * 0 on success, a negative errno value otherwise and rte_errno is set.
3153 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3154 const struct rte_flow_action *action,
3155 struct rte_flow_error *error)
3157 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3158 return rte_flow_error_set(error, EINVAL,
3159 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3160 NULL, "action configuration not set");
3161 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3162 return rte_flow_error_set(error, EINVAL,
3163 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3164 "can't have encap action before"
3170 * Validate the modify-header MAC address actions.
3172 * @param[in] action_flags
3173 * Holds the actions detected until now.
3175 * Pointer to the modify action.
3176 * @param[in] item_flags
3177 * Holds the items detected.
3179 * Pointer to error structure.
3182 * 0 on success, a negative errno value otherwise and rte_errno is set.
3185 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3186 const struct rte_flow_action *action,
3187 const uint64_t item_flags,
3188 struct rte_flow_error *error)
3192 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3194 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3195 return rte_flow_error_set(error, EINVAL,
3196 RTE_FLOW_ERROR_TYPE_ACTION,
3198 "no L2 item in pattern");
3204 * Validate the modify-header IPv4 address actions.
3206 * @param[in] action_flags
3207 * Holds the actions detected until now.
3209 * Pointer to the modify action.
3210 * @param[in] item_flags
3211 * Holds the items detected.
3213 * Pointer to error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3220 const struct rte_flow_action *action,
3221 const uint64_t item_flags,
3222 struct rte_flow_error *error)
3227 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3229 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3230 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3231 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3232 if (!(item_flags & layer))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3236 "no ipv4 item in pattern");
3242 * Validate the modify-header IPv6 address actions.
3244 * @param[in] action_flags
3245 * Holds the actions detected until now.
3247 * Pointer to the modify action.
3248 * @param[in] item_flags
3249 * Holds the items detected.
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const uint64_t item_flags,
3260 struct rte_flow_error *error)
3265 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3267 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3268 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3269 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3270 if (!(item_flags & layer))
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION,
3274 "no ipv6 item in pattern");
3280 * Validate the modify-header TP actions.
3282 * @param[in] action_flags
3283 * Holds the actions detected until now.
3285 * Pointer to the modify action.
3286 * @param[in] item_flags
3287 * Holds the items detected.
3289 * Pointer to error structure.
3292 * 0 on success, a negative errno value otherwise and rte_errno is set.
3295 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3296 const struct rte_flow_action *action,
3297 const uint64_t item_flags,
3298 struct rte_flow_error *error)
3303 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3305 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3306 MLX5_FLOW_LAYER_INNER_L4 :
3307 MLX5_FLOW_LAYER_OUTER_L4;
3308 if (!(item_flags & layer))
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION,
3311 NULL, "no transport layer "
3318 * Validate the modify-header actions of increment/decrement
3319 * TCP Sequence-number.
3321 * @param[in] action_flags
3322 * Holds the actions detected until now.
3324 * Pointer to the modify action.
3325 * @param[in] item_flags
3326 * Holds the items detected.
3328 * Pointer to error structure.
3331 * 0 on success, a negative errno value otherwise and rte_errno is set.
3334 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3335 const struct rte_flow_action *action,
3336 const uint64_t item_flags,
3337 struct rte_flow_error *error)
3342 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3344 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3345 MLX5_FLOW_LAYER_INNER_L4_TCP :
3346 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3347 if (!(item_flags & layer))
3348 return rte_flow_error_set(error, EINVAL,
3349 RTE_FLOW_ERROR_TYPE_ACTION,
3350 NULL, "no TCP item in"
3352 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3353 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3354 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3355 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3356 return rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION,
3359 "cannot decrease and increase"
3360 " TCP sequence number"
3361 " at the same time");
3367 * Validate the modify-header actions of increment/decrement
3368 * TCP Acknowledgment number.
3370 * @param[in] action_flags
3371 * Holds the actions detected until now.
3373 * Pointer to the modify action.
3374 * @param[in] item_flags
3375 * Holds the items detected.
3377 * Pointer to error structure.
3380 * 0 on success, a negative errno value otherwise and rte_errno is set.
3383 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3384 const struct rte_flow_action *action,
3385 const uint64_t item_flags,
3386 struct rte_flow_error *error)
3391 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3393 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3394 MLX5_FLOW_LAYER_INNER_L4_TCP :
3395 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3396 if (!(item_flags & layer))
3397 return rte_flow_error_set(error, EINVAL,
3398 RTE_FLOW_ERROR_TYPE_ACTION,
3399 NULL, "no TCP item in"
3401 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3402 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3403 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3404 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3405 return rte_flow_error_set(error, EINVAL,
3406 RTE_FLOW_ERROR_TYPE_ACTION,
3408 "cannot decrease and increase"
3409 " TCP acknowledgment number"
3410 " at the same time");
3416 * Validate the modify-header TTL actions.
3418 * @param[in] action_flags
3419 * Holds the actions detected until now.
3421 * Pointer to the modify action.
3422 * @param[in] item_flags
3423 * Holds the items detected.
3425 * Pointer to error structure.
3428 * 0 on success, a negative errno value otherwise and rte_errno is set.
3431 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3432 const struct rte_flow_action *action,
3433 const uint64_t item_flags,
3434 struct rte_flow_error *error)
3439 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3441 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3442 MLX5_FLOW_LAYER_INNER_L3 :
3443 MLX5_FLOW_LAYER_OUTER_L3;
3444 if (!(item_flags & layer))
3445 return rte_flow_error_set(error, EINVAL,
3446 RTE_FLOW_ERROR_TYPE_ACTION,
3448 "no IP protocol in pattern");
3454 * Validate jump action.
3457 * Pointer to the jump action.
3458 * @param[in] action_flags
3459 * Holds the actions detected until now.
3460 * @param[in] attributes
3461 * Pointer to flow attributes
3462 * @param[in] external
3463 * Action belongs to flow rule created by request external to PMD.
3465 * Pointer to error structure.
3468 * 0 on success, a negative errno value otherwise and rte_errno is set.
3471 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3472 uint64_t action_flags,
3473 const struct rte_flow_attr *attributes,
3474 bool external, struct rte_flow_error *error)
3476 uint32_t target_group, table;
3479 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3480 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3481 return rte_flow_error_set(error, EINVAL,
3482 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3483 "can't have 2 fate actions in"
3485 if (action_flags & MLX5_FLOW_ACTION_METER)
3486 return rte_flow_error_set(error, ENOTSUP,
3487 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3488 "jump with meter not support");
3490 return rte_flow_error_set(error, EINVAL,
3491 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3492 NULL, "action configuration not set");
3494 ((const struct rte_flow_action_jump *)action->conf)->group;
3495 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3496 true, &table, error);
3499 if (attributes->group == target_group)
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3502 "target group must be other than"
3503 " the current flow group");
3508 * Validate the port_id action.
3511 * Pointer to rte_eth_dev structure.
3512 * @param[in] action_flags
3513 * Bit-fields that holds the actions detected until now.
3515 * Port_id RTE action structure.
3517 * Attributes of flow that includes this action.
3519 * Pointer to error structure.
3522 * 0 on success, a negative errno value otherwise and rte_errno is set.
3525 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3526 uint64_t action_flags,
3527 const struct rte_flow_action *action,
3528 const struct rte_flow_attr *attr,
3529 struct rte_flow_error *error)
3531 const struct rte_flow_action_port_id *port_id;
3532 struct mlx5_priv *act_priv;
3533 struct mlx5_priv *dev_priv;
3536 if (!attr->transfer)
3537 return rte_flow_error_set(error, ENOTSUP,
3538 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3540 "port id action is valid in transfer"
3542 if (!action || !action->conf)
3543 return rte_flow_error_set(error, ENOTSUP,
3544 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3546 "port id action parameters must be"
3548 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3549 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3550 return rte_flow_error_set(error, EINVAL,
3551 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3552 "can have only one fate actions in"
3554 dev_priv = mlx5_dev_to_eswitch_info(dev);
3556 return rte_flow_error_set(error, rte_errno,
3557 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3559 "failed to obtain E-Switch info");
3560 port_id = action->conf;
3561 port = port_id->original ? dev->data->port_id : port_id->id;
3562 act_priv = mlx5_port_to_eswitch_info(port, false);
3564 return rte_flow_error_set
3566 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3567 "failed to obtain E-Switch port id for port");
3568 if (act_priv->domain_id != dev_priv->domain_id)
3569 return rte_flow_error_set
3571 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3572 "port does not belong to"
3573 " E-Switch being configured");
3578 * Get the maximum number of modify header actions.
3581 * Pointer to rte_eth_dev structure.
3583 * Flags bits to check if root level.
3586 * Max number of modify header actions device can support.
3589 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3592 * There's no way to directly query the max cap. Although it has to be
3593 * acquried by iterative trial, it is a safe assumption that more
3594 * actions are supported by FW if extensive metadata register is
3595 * supported. (Only in the root table)
3597 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3598 return MLX5_MAX_MODIFY_NUM;
3600 return mlx5_flow_ext_mreg_supported(dev) ?
3601 MLX5_ROOT_TBL_MODIFY_NUM :
3602 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3606 * Validate the meter action.
3609 * Pointer to rte_eth_dev structure.
3610 * @param[in] action_flags
3611 * Bit-fields that holds the actions detected until now.
3613 * Pointer to the meter action.
3615 * Attributes of flow that includes this action.
3617 * Pointer to error structure.
3620 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3623 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3624 uint64_t action_flags,
3625 const struct rte_flow_action *action,
3626 const struct rte_flow_attr *attr,
3627 struct rte_flow_error *error)
3629 struct mlx5_priv *priv = dev->data->dev_private;
3630 const struct rte_flow_action_meter *am = action->conf;
3631 struct mlx5_flow_meter *fm;
3634 return rte_flow_error_set(error, EINVAL,
3635 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3636 "meter action conf is NULL");
3638 if (action_flags & MLX5_FLOW_ACTION_METER)
3639 return rte_flow_error_set(error, ENOTSUP,
3640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3641 "meter chaining not support");
3642 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3643 return rte_flow_error_set(error, ENOTSUP,
3644 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3645 "meter with jump not support");
3647 return rte_flow_error_set(error, ENOTSUP,
3648 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3650 "meter action not supported");
3651 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3653 return rte_flow_error_set(error, EINVAL,
3654 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3656 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3657 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3658 (!fm->attr.egress && !attr->egress && attr->ingress))))
3659 return rte_flow_error_set(error, EINVAL,
3660 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3661 "Flow attributes are either invalid "
3662 "or have a conflict with current "
3663 "meter attributes");
3668 * Validate the modify-header IPv4 DSCP actions.
3670 * @param[in] action_flags
3671 * Holds the actions detected until now.
3673 * Pointer to the modify action.
3674 * @param[in] item_flags
3675 * Holds the items detected.
3677 * Pointer to error structure.
3680 * 0 on success, a negative errno value otherwise and rte_errno is set.
3683 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3684 const struct rte_flow_action *action,
3685 const uint64_t item_flags,
3686 struct rte_flow_error *error)
3690 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3692 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3693 return rte_flow_error_set(error, EINVAL,
3694 RTE_FLOW_ERROR_TYPE_ACTION,
3696 "no ipv4 item in pattern");
3702 * Validate the modify-header IPv6 DSCP actions.
3704 * @param[in] action_flags
3705 * Holds the actions detected until now.
3707 * Pointer to the modify action.
3708 * @param[in] item_flags
3709 * Holds the items detected.
3711 * Pointer to error structure.
3714 * 0 on success, a negative errno value otherwise and rte_errno is set.
3717 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3718 const struct rte_flow_action *action,
3719 const uint64_t item_flags,
3720 struct rte_flow_error *error)
3724 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3726 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3727 return rte_flow_error_set(error, EINVAL,
3728 RTE_FLOW_ERROR_TYPE_ACTION,
3730 "no ipv6 item in pattern");
3736 * Find existing modify-header resource or create and register a new one.
3738 * @param dev[in, out]
3739 * Pointer to rte_eth_dev structure.
3740 * @param[in, out] resource
3741 * Pointer to modify-header resource.
3742 * @parm[in, out] dev_flow
3743 * Pointer to the dev_flow.
3745 * pointer to error structure.
3748 * 0 on success otherwise -errno and errno is set.
3751 flow_dv_modify_hdr_resource_register
3752 (struct rte_eth_dev *dev,
3753 struct mlx5_flow_dv_modify_hdr_resource *resource,
3754 struct mlx5_flow *dev_flow,
3755 struct rte_flow_error *error)
3757 struct mlx5_priv *priv = dev->data->dev_private;
3758 struct mlx5_ibv_shared *sh = priv->sh;
3759 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3760 struct mlx5dv_dr_domain *ns;
3761 uint32_t actions_len;
3763 resource->flags = dev_flow->dv.group ? 0 :
3764 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3765 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3767 return rte_flow_error_set(error, EOVERFLOW,
3768 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3769 "too many modify header items");
3770 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3771 ns = sh->fdb_domain;
3772 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3776 /* Lookup a matching resource from cache. */
3777 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3778 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3779 if (resource->ft_type == cache_resource->ft_type &&
3780 resource->actions_num == cache_resource->actions_num &&
3781 resource->flags == cache_resource->flags &&
3782 !memcmp((const void *)resource->actions,
3783 (const void *)cache_resource->actions,
3785 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3786 (void *)cache_resource,
3787 rte_atomic32_read(&cache_resource->refcnt));
3788 rte_atomic32_inc(&cache_resource->refcnt);
3789 dev_flow->handle.dvh.modify_hdr = cache_resource;
3793 /* Register new modify-header resource. */
3794 cache_resource = rte_calloc(__func__, 1,
3795 sizeof(*cache_resource) + actions_len, 0);
3796 if (!cache_resource)
3797 return rte_flow_error_set(error, ENOMEM,
3798 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3799 "cannot allocate resource memory");
3800 *cache_resource = *resource;
3801 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3802 cache_resource->verbs_action =
3803 mlx5_glue->dv_create_flow_action_modify_header
3804 (sh->ctx, cache_resource->ft_type, ns,
3805 cache_resource->flags, actions_len,
3806 (uint64_t *)cache_resource->actions);
3807 if (!cache_resource->verbs_action) {
3808 rte_free(cache_resource);
3809 return rte_flow_error_set(error, ENOMEM,
3810 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3811 NULL, "cannot create action");
3813 rte_atomic32_init(&cache_resource->refcnt);
3814 rte_atomic32_inc(&cache_resource->refcnt);
3815 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3816 dev_flow->handle.dvh.modify_hdr = cache_resource;
3817 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3818 (void *)cache_resource,
3819 rte_atomic32_read(&cache_resource->refcnt));
3823 #define MLX5_CNT_CONTAINER_RESIZE 64
3826 * Get or create a flow counter.
3829 * Pointer to the Ethernet device structure.
3831 * Indicate if this counter is shared with other flows.
3833 * Counter identifier.
3836 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3838 static struct mlx5_flow_counter *
3839 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3842 struct mlx5_priv *priv = dev->data->dev_private;
3843 struct mlx5_flow_counter *cnt = NULL;
3844 struct mlx5_devx_obj *dcs = NULL;
3846 if (!priv->config.devx) {
3847 rte_errno = ENOTSUP;
3851 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3852 if (cnt->shared && cnt->id == id) {
3858 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3861 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3863 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3867 struct mlx5_flow_counter tmpl = {
3873 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3875 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3881 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3886 * Release a flow counter.
3889 * Pointer to the Ethernet device structure.
3890 * @param[in] counter
3891 * Pointer to the counter handler.
3894 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3895 struct mlx5_flow_counter *counter)
3897 struct mlx5_priv *priv = dev->data->dev_private;
3901 if (--counter->ref_cnt == 0) {
3902 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3903 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3909 * Query a devx flow counter.
3912 * Pointer to the Ethernet device structure.
3914 * Pointer to the flow counter.
3916 * The statistics value of packets.
3918 * The statistics value of bytes.
3921 * 0 on success, otherwise a negative errno value and rte_errno is set.
3924 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3925 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3928 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3933 * Get a pool by a counter.
3936 * Pointer to the counter.
3941 static struct mlx5_flow_counter_pool *
3942 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3945 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3946 return (struct mlx5_flow_counter_pool *)cnt - 1;
3952 * Get a pool by devx counter ID.
3955 * Pointer to the counter container.
3957 * The counter devx ID.
3960 * The counter pool pointer if exists, NULL otherwise,
3962 static struct mlx5_flow_counter_pool *
3963 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3965 struct mlx5_flow_counter_pool *pool;
3967 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3968 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3969 MLX5_COUNTERS_PER_POOL;
3971 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3978 * Allocate a new memory for the counter values wrapped by all the needed
3982 * Pointer to the Ethernet device structure.
3984 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3987 * The new memory management pointer on success, otherwise NULL and rte_errno
3990 static struct mlx5_counter_stats_mem_mng *
3991 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3993 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3994 (dev->data->dev_private))->sh;
3995 struct mlx5_devx_mkey_attr mkey_attr;
3996 struct mlx5_counter_stats_mem_mng *mem_mng;
3997 volatile struct flow_counter_stats *raw_data;
3998 int size = (sizeof(struct flow_counter_stats) *
3999 MLX5_COUNTERS_PER_POOL +
4000 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4001 sizeof(struct mlx5_counter_stats_mem_mng);
4002 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4009 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4010 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4011 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4012 IBV_ACCESS_LOCAL_WRITE);
4013 if (!mem_mng->umem) {
4018 mkey_attr.addr = (uintptr_t)mem;
4019 mkey_attr.size = size;
4020 mkey_attr.umem_id = mem_mng->umem->umem_id;
4021 mkey_attr.pd = sh->pdn;
4022 mkey_attr.log_entity_size = 0;
4023 mkey_attr.pg_access = 0;
4024 mkey_attr.klm_array = NULL;
4025 mkey_attr.klm_num = 0;
4026 mkey_attr.relaxed_ordering = 1;
4027 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4029 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4034 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4035 raw_data = (volatile struct flow_counter_stats *)mem;
4036 for (i = 0; i < raws_n; ++i) {
4037 mem_mng->raws[i].mem_mng = mem_mng;
4038 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4040 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4045 * Resize a counter container.
4048 * Pointer to the Ethernet device structure.
4050 * Whether the pool is for counter that was allocated by batch command.
4053 * The new container pointer on success, otherwise NULL and rte_errno is set.
4055 static struct mlx5_pools_container *
4056 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4058 struct mlx5_priv *priv = dev->data->dev_private;
4059 struct mlx5_pools_container *cont =
4060 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4061 struct mlx5_pools_container *new_cont =
4062 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4063 struct mlx5_counter_stats_mem_mng *mem_mng;
4064 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4065 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4068 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4069 /* The last resize still hasn't detected by the host thread. */
4073 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4074 if (!new_cont->pools) {
4079 memcpy(new_cont->pools, cont->pools, cont->n *
4080 sizeof(struct mlx5_flow_counter_pool *));
4081 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4082 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4084 rte_free(new_cont->pools);
4087 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4088 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4089 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4091 new_cont->n = resize;
4092 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4093 TAILQ_INIT(&new_cont->pool_list);
4094 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4095 new_cont->init_mem_mng = mem_mng;
4097 /* Flip the master container. */
4098 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4103 * Query a devx flow counter.
4106 * Pointer to the Ethernet device structure.
4108 * Pointer to the flow counter.
4110 * The statistics value of packets.
4112 * The statistics value of bytes.
4115 * 0 on success, otherwise a negative errno value and rte_errno is set.
4118 _flow_dv_query_count(struct rte_eth_dev *dev,
4119 struct mlx5_flow_counter *cnt, uint64_t *pkts,
4122 struct mlx5_priv *priv = dev->data->dev_private;
4123 struct mlx5_flow_counter_pool *pool =
4124 flow_dv_counter_pool_get(cnt);
4125 int offset = cnt - &pool->counters_raw[0];
4127 if (priv->counter_fallback)
4128 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4130 rte_spinlock_lock(&pool->sl);
4132 * The single counters allocation may allocate smaller ID than the
4133 * current allocated in parallel to the host reading.
4134 * In this case the new counter values must be reported as 0.
4136 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4140 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4141 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4143 rte_spinlock_unlock(&pool->sl);
4148 * Create and initialize a new counter pool.
4151 * Pointer to the Ethernet device structure.
4153 * The devX counter handle.
4155 * Whether the pool is for counter that was allocated by batch command.
4158 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4160 static struct mlx5_flow_counter_pool *
4161 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4164 struct mlx5_priv *priv = dev->data->dev_private;
4165 struct mlx5_flow_counter_pool *pool;
4166 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4168 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4171 if (cont->n == n_valid) {
4172 cont = flow_dv_container_resize(dev, batch);
4176 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4177 sizeof(struct mlx5_flow_counter);
4178 pool = rte_calloc(__func__, 1, size, 0);
4183 pool->min_dcs = dcs;
4184 pool->raw = cont->init_mem_mng->raws + n_valid %
4185 MLX5_CNT_CONTAINER_RESIZE;
4186 pool->raw_hw = NULL;
4187 rte_spinlock_init(&pool->sl);
4189 * The generation of the new allocated counters in this pool is 0, 2 in
4190 * the pool generation makes all the counters valid for allocation.
4192 rte_atomic64_set(&pool->query_gen, 0x2);
4193 TAILQ_INIT(&pool->counters);
4194 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4195 cont->pools[n_valid] = pool;
4196 /* Pool initialization must be updated before host thread access. */
4198 rte_atomic16_add(&cont->n_valid, 1);
4203 * Prepare a new counter and/or a new counter pool.
4206 * Pointer to the Ethernet device structure.
4207 * @param[out] cnt_free
4208 * Where to put the pointer of a new counter.
4210 * Whether the pool is for counter that was allocated by batch command.
4213 * The free counter pool pointer and @p cnt_free is set on success,
4214 * NULL otherwise and rte_errno is set.
4216 static struct mlx5_flow_counter_pool *
4217 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4218 struct mlx5_flow_counter **cnt_free,
4221 struct mlx5_priv *priv = dev->data->dev_private;
4222 struct mlx5_flow_counter_pool *pool;
4223 struct mlx5_devx_obj *dcs = NULL;
4224 struct mlx5_flow_counter *cnt;
4228 /* bulk_bitmap must be 0 for single counter allocation. */
4229 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4232 pool = flow_dv_find_pool_by_id
4233 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4235 pool = flow_dv_pool_create(dev, dcs, batch);
4237 mlx5_devx_cmd_destroy(dcs);
4240 } else if (dcs->id < pool->min_dcs->id) {
4241 rte_atomic64_set(&pool->a64_dcs,
4242 (int64_t)(uintptr_t)dcs);
4244 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4245 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4250 /* bulk_bitmap is in 128 counters units. */
4251 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4252 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4254 rte_errno = ENODATA;
4257 pool = flow_dv_pool_create(dev, dcs, batch);
4259 mlx5_devx_cmd_destroy(dcs);
4262 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4263 cnt = &pool->counters_raw[i];
4265 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4267 *cnt_free = &pool->counters_raw[0];
4272 * Search for existed shared counter.
4275 * Pointer to the relevant counter pool container.
4277 * The shared counter ID to search.
4280 * NULL if not existed, otherwise pointer to the shared counter.
4282 static struct mlx5_flow_counter *
4283 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4286 static struct mlx5_flow_counter *cnt;
4287 struct mlx5_flow_counter_pool *pool;
4290 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4291 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4292 cnt = &pool->counters_raw[i];
4293 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4301 * Allocate a flow counter.
4304 * Pointer to the Ethernet device structure.
4306 * Indicate if this counter is shared with other flows.
4308 * Counter identifier.
4310 * Counter flow group.
4313 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4315 static struct mlx5_flow_counter *
4316 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4319 struct mlx5_priv *priv = dev->data->dev_private;
4320 struct mlx5_flow_counter_pool *pool = NULL;
4321 struct mlx5_flow_counter *cnt_free = NULL;
4323 * Currently group 0 flow counter cannot be assigned to a flow if it is
4324 * not the first one in the batch counter allocation, so it is better
4325 * to allocate counters one by one for these flows in a separate
4327 * A counter can be shared between different groups so need to take
4328 * shared counters from the single container.
4330 uint32_t batch = (group && !shared) ? 1 : 0;
4331 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4334 if (priv->counter_fallback)
4335 return flow_dv_counter_alloc_fallback(dev, shared, id);
4336 if (!priv->config.devx) {
4337 rte_errno = ENOTSUP;
4341 cnt_free = flow_dv_counter_shared_search(cont, id);
4343 if (cnt_free->ref_cnt + 1 == 0) {
4347 cnt_free->ref_cnt++;
4351 /* Pools which has a free counters are in the start. */
4352 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4354 * The free counter reset values must be updated between the
4355 * counter release to the counter allocation, so, at least one
4356 * query must be done in this time. ensure it by saving the
4357 * query generation in the release time.
4358 * The free list is sorted according to the generation - so if
4359 * the first one is not updated, all the others are not
4362 cnt_free = TAILQ_FIRST(&pool->counters);
4363 if (cnt_free && cnt_free->query_gen + 1 <
4364 rte_atomic64_read(&pool->query_gen))
4369 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4373 cnt_free->batch = batch;
4374 /* Create a DV counter action only in the first time usage. */
4375 if (!cnt_free->action) {
4377 struct mlx5_devx_obj *dcs;
4380 offset = cnt_free - &pool->counters_raw[0];
4381 dcs = pool->min_dcs;
4384 dcs = cnt_free->dcs;
4386 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4388 if (!cnt_free->action) {
4393 /* Update the counter reset values. */
4394 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4397 cnt_free->shared = shared;
4398 cnt_free->ref_cnt = 1;
4400 if (!priv->sh->cmng.query_thread_on)
4401 /* Start the asynchronous batch query by the host thread. */
4402 mlx5_set_query_alarm(priv->sh);
4403 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4404 if (TAILQ_EMPTY(&pool->counters)) {
4405 /* Move the pool to the end of the container pool list. */
4406 TAILQ_REMOVE(&cont->pool_list, pool, next);
4407 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4413 * Release a flow counter.
4416 * Pointer to the Ethernet device structure.
4417 * @param[in] counter
4418 * Pointer to the counter handler.
4421 flow_dv_counter_release(struct rte_eth_dev *dev,
4422 struct mlx5_flow_counter *counter)
4424 struct mlx5_priv *priv = dev->data->dev_private;
4428 if (priv->counter_fallback) {
4429 flow_dv_counter_release_fallback(dev, counter);
4432 if (--counter->ref_cnt == 0) {
4433 struct mlx5_flow_counter_pool *pool =
4434 flow_dv_counter_pool_get(counter);
4436 /* Put the counter in the end - the last updated one. */
4437 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4438 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4443 * Verify the @p attributes will be correctly understood by the NIC and store
4444 * them in the @p flow if everything is correct.
4447 * Pointer to dev struct.
4448 * @param[in] attributes
4449 * Pointer to flow attributes
4450 * @param[in] external
4451 * This flow rule is created by request external to PMD.
4453 * Pointer to error structure.
4456 * 0 on success, a negative errno value otherwise and rte_errno is set.
4459 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4460 const struct rte_flow_attr *attributes,
4461 bool external __rte_unused,
4462 struct rte_flow_error *error)
4464 struct mlx5_priv *priv = dev->data->dev_private;
4465 uint32_t priority_max = priv->config.flow_prio - 1;
4467 #ifndef HAVE_MLX5DV_DR
4468 if (attributes->group)
4469 return rte_flow_error_set(error, ENOTSUP,
4470 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4472 "groups are not supported");
4477 ret = mlx5_flow_group_to_table(attributes, external,
4478 attributes->group, !!priv->fdb_def_rule,
4483 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4484 attributes->priority >= priority_max)
4485 return rte_flow_error_set(error, ENOTSUP,
4486 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4488 "priority out of range");
4489 if (attributes->transfer) {
4490 if (!priv->config.dv_esw_en)
4491 return rte_flow_error_set
4493 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4494 "E-Switch dr is not supported");
4495 if (!(priv->representor || priv->master))
4496 return rte_flow_error_set
4497 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4498 NULL, "E-Switch configuration can only be"
4499 " done by a master or a representor device");
4500 if (attributes->egress)
4501 return rte_flow_error_set
4503 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4504 "egress is not supported");
4506 if (!(attributes->egress ^ attributes->ingress))
4507 return rte_flow_error_set(error, ENOTSUP,
4508 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4509 "must specify exactly one of "
4510 "ingress or egress");
4515 * Internal validation function. For validating both actions and items.
4518 * Pointer to the rte_eth_dev structure.
4520 * Pointer to the flow attributes.
4522 * Pointer to the list of items.
4523 * @param[in] actions
4524 * Pointer to the list of actions.
4525 * @param[in] external
4526 * This flow rule is created by request external to PMD.
4528 * Pointer to the error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4535 const struct rte_flow_item items[],
4536 const struct rte_flow_action actions[],
4537 bool external, struct rte_flow_error *error)
4540 uint64_t action_flags = 0;
4541 uint64_t item_flags = 0;
4542 uint64_t last_item = 0;
4543 uint8_t next_protocol = 0xff;
4544 uint16_t ether_type = 0;
4546 uint8_t item_ipv6_proto = 0;
4547 const struct rte_flow_item *gre_item = NULL;
4548 const struct rte_flow_action_raw_decap *decap;
4549 const struct rte_flow_action_raw_encap *encap;
4550 const struct rte_flow_action_rss *rss;
4551 const struct rte_flow_item_tcp nic_tcp_mask = {
4554 .src_port = RTE_BE16(UINT16_MAX),
4555 .dst_port = RTE_BE16(UINT16_MAX),
4558 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4560 .src_addr = RTE_BE32(0xffffffff),
4561 .dst_addr = RTE_BE32(0xffffffff),
4562 .type_of_service = 0xff,
4563 .next_proto_id = 0xff,
4564 .time_to_live = 0xff,
4567 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4570 "\xff\xff\xff\xff\xff\xff\xff\xff"
4571 "\xff\xff\xff\xff\xff\xff\xff\xff",
4573 "\xff\xff\xff\xff\xff\xff\xff\xff"
4574 "\xff\xff\xff\xff\xff\xff\xff\xff",
4575 .vtc_flow = RTE_BE32(0xffffffff),
4580 struct mlx5_priv *priv = dev->data->dev_private;
4581 struct mlx5_dev_config *dev_conf = &priv->config;
4582 uint16_t queue_index = 0xFFFF;
4586 ret = flow_dv_validate_attributes(dev, attr, external, error);
4589 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4590 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4591 int type = items->type;
4594 case RTE_FLOW_ITEM_TYPE_VOID:
4596 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4597 ret = flow_dv_validate_item_port_id
4598 (dev, items, attr, item_flags, error);
4601 last_item = MLX5_FLOW_ITEM_PORT_ID;
4603 case RTE_FLOW_ITEM_TYPE_ETH:
4604 ret = mlx5_flow_validate_item_eth(items, item_flags,
4608 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4609 MLX5_FLOW_LAYER_OUTER_L2;
4610 if (items->mask != NULL && items->spec != NULL) {
4612 ((const struct rte_flow_item_eth *)
4615 ((const struct rte_flow_item_eth *)
4617 ether_type = rte_be_to_cpu_16(ether_type);
4622 case RTE_FLOW_ITEM_TYPE_VLAN:
4623 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4627 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4628 MLX5_FLOW_LAYER_OUTER_VLAN;
4629 if (items->mask != NULL && items->spec != NULL) {
4631 ((const struct rte_flow_item_vlan *)
4632 items->spec)->inner_type;
4634 ((const struct rte_flow_item_vlan *)
4635 items->mask)->inner_type;
4636 ether_type = rte_be_to_cpu_16(ether_type);
4641 case RTE_FLOW_ITEM_TYPE_IPV4:
4642 mlx5_flow_tunnel_ip_check(items, next_protocol,
4643 &item_flags, &tunnel);
4644 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4651 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4652 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4653 if (items->mask != NULL &&
4654 ((const struct rte_flow_item_ipv4 *)
4655 items->mask)->hdr.next_proto_id) {
4657 ((const struct rte_flow_item_ipv4 *)
4658 (items->spec))->hdr.next_proto_id;
4660 ((const struct rte_flow_item_ipv4 *)
4661 (items->mask))->hdr.next_proto_id;
4663 /* Reset for inner layer. */
4664 next_protocol = 0xff;
4667 case RTE_FLOW_ITEM_TYPE_IPV6:
4668 mlx5_flow_tunnel_ip_check(items, next_protocol,
4669 &item_flags, &tunnel);
4670 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4677 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4678 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4679 if (items->mask != NULL &&
4680 ((const struct rte_flow_item_ipv6 *)
4681 items->mask)->hdr.proto) {
4683 ((const struct rte_flow_item_ipv6 *)
4684 items->spec)->hdr.proto;
4686 ((const struct rte_flow_item_ipv6 *)
4687 items->spec)->hdr.proto;
4689 ((const struct rte_flow_item_ipv6 *)
4690 items->mask)->hdr.proto;
4692 /* Reset for inner layer. */
4693 next_protocol = 0xff;
4696 case RTE_FLOW_ITEM_TYPE_TCP:
4697 ret = mlx5_flow_validate_item_tcp
4704 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4705 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4707 case RTE_FLOW_ITEM_TYPE_UDP:
4708 ret = mlx5_flow_validate_item_udp(items, item_flags,
4713 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4714 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4716 case RTE_FLOW_ITEM_TYPE_GRE:
4717 ret = mlx5_flow_validate_item_gre(items, item_flags,
4718 next_protocol, error);
4722 last_item = MLX5_FLOW_LAYER_GRE;
4724 case RTE_FLOW_ITEM_TYPE_NVGRE:
4725 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4730 last_item = MLX5_FLOW_LAYER_NVGRE;
4732 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4733 ret = mlx5_flow_validate_item_gre_key
4734 (items, item_flags, gre_item, error);
4737 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4739 case RTE_FLOW_ITEM_TYPE_VXLAN:
4740 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4744 last_item = MLX5_FLOW_LAYER_VXLAN;
4746 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4747 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4752 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4754 case RTE_FLOW_ITEM_TYPE_GENEVE:
4755 ret = mlx5_flow_validate_item_geneve(items,
4760 last_item = MLX5_FLOW_LAYER_GENEVE;
4762 case RTE_FLOW_ITEM_TYPE_MPLS:
4763 ret = mlx5_flow_validate_item_mpls(dev, items,
4768 last_item = MLX5_FLOW_LAYER_MPLS;
4771 case RTE_FLOW_ITEM_TYPE_MARK:
4772 ret = flow_dv_validate_item_mark(dev, items, attr,
4776 last_item = MLX5_FLOW_ITEM_MARK;
4778 case RTE_FLOW_ITEM_TYPE_META:
4779 ret = flow_dv_validate_item_meta(dev, items, attr,
4783 last_item = MLX5_FLOW_ITEM_METADATA;
4785 case RTE_FLOW_ITEM_TYPE_ICMP:
4786 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4791 last_item = MLX5_FLOW_LAYER_ICMP;
4793 case RTE_FLOW_ITEM_TYPE_ICMP6:
4794 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4799 item_ipv6_proto = IPPROTO_ICMPV6;
4800 last_item = MLX5_FLOW_LAYER_ICMP6;
4802 case RTE_FLOW_ITEM_TYPE_TAG:
4803 ret = flow_dv_validate_item_tag(dev, items,
4807 last_item = MLX5_FLOW_ITEM_TAG;
4809 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4810 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4812 case RTE_FLOW_ITEM_TYPE_GTP:
4813 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4817 last_item = MLX5_FLOW_LAYER_GTP;
4820 return rte_flow_error_set(error, ENOTSUP,
4821 RTE_FLOW_ERROR_TYPE_ITEM,
4822 NULL, "item not supported");
4824 item_flags |= last_item;
4826 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4827 int type = actions->type;
4828 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4829 return rte_flow_error_set(error, ENOTSUP,
4830 RTE_FLOW_ERROR_TYPE_ACTION,
4831 actions, "too many actions");
4833 case RTE_FLOW_ACTION_TYPE_VOID:
4835 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4836 ret = flow_dv_validate_action_port_id(dev,
4843 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4846 case RTE_FLOW_ACTION_TYPE_FLAG:
4847 ret = flow_dv_validate_action_flag(dev, action_flags,
4851 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4852 /* Count all modify-header actions as one. */
4853 if (!(action_flags &
4854 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4856 action_flags |= MLX5_FLOW_ACTION_FLAG |
4857 MLX5_FLOW_ACTION_MARK_EXT;
4859 action_flags |= MLX5_FLOW_ACTION_FLAG;
4863 case RTE_FLOW_ACTION_TYPE_MARK:
4864 ret = flow_dv_validate_action_mark(dev, actions,
4869 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4870 /* Count all modify-header actions as one. */
4871 if (!(action_flags &
4872 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4874 action_flags |= MLX5_FLOW_ACTION_MARK |
4875 MLX5_FLOW_ACTION_MARK_EXT;
4877 action_flags |= MLX5_FLOW_ACTION_MARK;
4881 case RTE_FLOW_ACTION_TYPE_SET_META:
4882 ret = flow_dv_validate_action_set_meta(dev, actions,
4887 /* Count all modify-header actions as one action. */
4888 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4890 action_flags |= MLX5_FLOW_ACTION_SET_META;
4892 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4893 ret = flow_dv_validate_action_set_tag(dev, actions,
4898 /* Count all modify-header actions as one action. */
4899 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4901 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4903 case RTE_FLOW_ACTION_TYPE_DROP:
4904 ret = mlx5_flow_validate_action_drop(action_flags,
4908 action_flags |= MLX5_FLOW_ACTION_DROP;
4911 case RTE_FLOW_ACTION_TYPE_QUEUE:
4912 ret = mlx5_flow_validate_action_queue(actions,
4917 queue_index = ((const struct rte_flow_action_queue *)
4918 (actions->conf))->index;
4919 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4922 case RTE_FLOW_ACTION_TYPE_RSS:
4923 rss = actions->conf;
4924 ret = mlx5_flow_validate_action_rss(actions,
4930 if (rss != NULL && rss->queue_num)
4931 queue_index = rss->queue[0];
4932 action_flags |= MLX5_FLOW_ACTION_RSS;
4935 case RTE_FLOW_ACTION_TYPE_COUNT:
4936 ret = flow_dv_validate_action_count(dev, error);
4939 action_flags |= MLX5_FLOW_ACTION_COUNT;
4942 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4943 if (flow_dv_validate_action_pop_vlan(dev,
4949 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4952 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4953 ret = flow_dv_validate_action_push_vlan(dev,
4960 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4963 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4964 ret = flow_dv_validate_action_set_vlan_pcp
4965 (action_flags, actions, error);
4968 /* Count PCP with push_vlan command. */
4969 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4971 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4972 ret = flow_dv_validate_action_set_vlan_vid
4973 (item_flags, action_flags,
4977 /* Count VID with push_vlan command. */
4978 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4980 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4981 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4982 ret = flow_dv_validate_action_l2_encap(dev,
4988 action_flags |= MLX5_FLOW_ACTION_ENCAP;
4991 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4992 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4993 ret = flow_dv_validate_action_decap(dev, action_flags,
4997 action_flags |= MLX5_FLOW_ACTION_DECAP;
5000 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5001 ret = flow_dv_validate_action_raw_encap_decap
5002 (dev, NULL, actions->conf, attr, &action_flags,
5007 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5008 decap = actions->conf;
5009 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5011 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5015 encap = actions->conf;
5017 ret = flow_dv_validate_action_raw_encap_decap
5019 decap ? decap : &empty_decap, encap,
5020 attr, &action_flags, &actions_n,
5025 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5026 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5027 ret = flow_dv_validate_action_modify_mac(action_flags,
5033 /* Count all modify-header actions as one action. */
5034 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5036 action_flags |= actions->type ==
5037 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5038 MLX5_FLOW_ACTION_SET_MAC_SRC :
5039 MLX5_FLOW_ACTION_SET_MAC_DST;
5042 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5043 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5044 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5050 /* Count all modify-header actions as one action. */
5051 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5053 action_flags |= actions->type ==
5054 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5055 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5056 MLX5_FLOW_ACTION_SET_IPV4_DST;
5058 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5059 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5060 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5066 if (item_ipv6_proto == IPPROTO_ICMPV6)
5067 return rte_flow_error_set(error, ENOTSUP,
5068 RTE_FLOW_ERROR_TYPE_ACTION,
5070 "Can't change header "
5071 "with ICMPv6 proto");
5072 /* Count all modify-header actions as one action. */
5073 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5075 action_flags |= actions->type ==
5076 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5077 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5078 MLX5_FLOW_ACTION_SET_IPV6_DST;
5080 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5081 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5082 ret = flow_dv_validate_action_modify_tp(action_flags,
5088 /* Count all modify-header actions as one action. */
5089 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5091 action_flags |= actions->type ==
5092 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5093 MLX5_FLOW_ACTION_SET_TP_SRC :
5094 MLX5_FLOW_ACTION_SET_TP_DST;
5096 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5097 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5098 ret = flow_dv_validate_action_modify_ttl(action_flags,
5104 /* Count all modify-header actions as one action. */
5105 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5107 action_flags |= actions->type ==
5108 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5109 MLX5_FLOW_ACTION_SET_TTL :
5110 MLX5_FLOW_ACTION_DEC_TTL;
5112 case RTE_FLOW_ACTION_TYPE_JUMP:
5113 ret = flow_dv_validate_action_jump(actions,
5120 action_flags |= MLX5_FLOW_ACTION_JUMP;
5122 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5123 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5124 ret = flow_dv_validate_action_modify_tcp_seq
5131 /* Count all modify-header actions as one action. */
5132 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5134 action_flags |= actions->type ==
5135 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5136 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5137 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5139 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5140 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5141 ret = flow_dv_validate_action_modify_tcp_ack
5148 /* Count all modify-header actions as one action. */
5149 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5151 action_flags |= actions->type ==
5152 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5153 MLX5_FLOW_ACTION_INC_TCP_ACK :
5154 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5156 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5157 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5158 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5160 case RTE_FLOW_ACTION_TYPE_METER:
5161 ret = mlx5_flow_validate_action_meter(dev,
5167 action_flags |= MLX5_FLOW_ACTION_METER;
5170 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5171 ret = flow_dv_validate_action_modify_ipv4_dscp
5178 /* Count all modify-header actions as one action. */
5179 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5181 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5183 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5184 ret = flow_dv_validate_action_modify_ipv6_dscp
5191 /* Count all modify-header actions as one action. */
5192 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5194 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5197 return rte_flow_error_set(error, ENOTSUP,
5198 RTE_FLOW_ERROR_TYPE_ACTION,
5200 "action not supported");
5204 * Validate the drop action mutual exclusion with other actions.
5205 * Drop action is mutually-exclusive with any other action, except for
5208 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5209 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5210 return rte_flow_error_set(error, EINVAL,
5211 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5212 "Drop action is mutually-exclusive "
5213 "with any other action, except for "
5215 /* Eswitch has few restrictions on using items and actions */
5216 if (attr->transfer) {
5217 if (!mlx5_flow_ext_mreg_supported(dev) &&
5218 action_flags & MLX5_FLOW_ACTION_FLAG)
5219 return rte_flow_error_set(error, ENOTSUP,
5220 RTE_FLOW_ERROR_TYPE_ACTION,
5222 "unsupported action FLAG");
5223 if (!mlx5_flow_ext_mreg_supported(dev) &&
5224 action_flags & MLX5_FLOW_ACTION_MARK)
5225 return rte_flow_error_set(error, ENOTSUP,
5226 RTE_FLOW_ERROR_TYPE_ACTION,
5228 "unsupported action MARK");
5229 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5230 return rte_flow_error_set(error, ENOTSUP,
5231 RTE_FLOW_ERROR_TYPE_ACTION,
5233 "unsupported action QUEUE");
5234 if (action_flags & MLX5_FLOW_ACTION_RSS)
5235 return rte_flow_error_set(error, ENOTSUP,
5236 RTE_FLOW_ERROR_TYPE_ACTION,
5238 "unsupported action RSS");
5239 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5240 return rte_flow_error_set(error, EINVAL,
5241 RTE_FLOW_ERROR_TYPE_ACTION,
5243 "no fate action is found");
5245 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5246 return rte_flow_error_set(error, EINVAL,
5247 RTE_FLOW_ERROR_TYPE_ACTION,
5249 "no fate action is found");
5251 /* Continue validation for Xcap actions.*/
5252 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5253 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5254 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5255 MLX5_FLOW_XCAP_ACTIONS)
5256 return rte_flow_error_set(error, ENOTSUP,
5257 RTE_FLOW_ERROR_TYPE_ACTION,
5258 NULL, "encap and decap "
5259 "combination aren't supported");
5260 if (!attr->transfer && attr->ingress && (action_flags &
5261 MLX5_FLOW_ACTION_ENCAP))
5262 return rte_flow_error_set(error, ENOTSUP,
5263 RTE_FLOW_ERROR_TYPE_ACTION,
5264 NULL, "encap is not supported"
5265 " for ingress traffic");
5271 * Internal preparation function. Allocates the DV flow size,
5272 * this size is constant.
5275 * Pointer to the flow attributes.
5277 * Pointer to the list of items.
5278 * @param[in] actions
5279 * Pointer to the list of actions.
5281 * Pointer to the error structure.
5284 * Pointer to mlx5_flow object on success,
5285 * otherwise NULL and rte_errno is set.
5287 static struct mlx5_flow *
5288 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5289 const struct rte_flow_item items[] __rte_unused,
5290 const struct rte_flow_action actions[] __rte_unused,
5291 struct rte_flow_error *error)
5293 size_t size = sizeof(struct mlx5_flow);
5294 struct mlx5_flow *dev_flow;
5296 dev_flow = rte_calloc(__func__, 1, size, 0);
5298 rte_flow_error_set(error, ENOMEM,
5299 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5300 "not enough memory to create flow");
5303 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5304 dev_flow->ingress = attr->ingress;
5305 dev_flow->dv.transfer = attr->transfer;
5309 #ifdef RTE_LIBRTE_MLX5_DEBUG
5311 * Sanity check for match mask and value. Similar to check_valid_spec() in
5312 * kernel driver. If unmasked bit is present in value, it returns failure.
5315 * pointer to match mask buffer.
5316 * @param match_value
5317 * pointer to match value buffer.
5320 * 0 if valid, -EINVAL otherwise.
5323 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5325 uint8_t *m = match_mask;
5326 uint8_t *v = match_value;
5329 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5332 "match_value differs from match_criteria"
5333 " %p[%u] != %p[%u]",
5334 match_value, i, match_mask, i);
5343 * Add Ethernet item to matcher and to the value.
5345 * @param[in, out] matcher
5347 * @param[in, out] key
5348 * Flow matcher value.
5350 * Flow pattern to translate.
5352 * Item is inner pattern.
5355 flow_dv_translate_item_eth(void *matcher, void *key,
5356 const struct rte_flow_item *item, int inner)
5358 const struct rte_flow_item_eth *eth_m = item->mask;
5359 const struct rte_flow_item_eth *eth_v = item->spec;
5360 const struct rte_flow_item_eth nic_mask = {
5361 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5362 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5363 .type = RTE_BE16(0xffff),
5375 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5377 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5379 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5381 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5383 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5384 ð_m->dst, sizeof(eth_m->dst));
5385 /* The value must be in the range of the mask. */
5386 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5387 for (i = 0; i < sizeof(eth_m->dst); ++i)
5388 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5389 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5390 ð_m->src, sizeof(eth_m->src));
5391 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5392 /* The value must be in the range of the mask. */
5393 for (i = 0; i < sizeof(eth_m->dst); ++i)
5394 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5396 /* When ethertype is present set mask for tagged VLAN. */
5397 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5398 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5399 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5400 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5401 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5403 /* Return here to avoid setting match on ethertype. */
5408 * HW supports match on one Ethertype, the Ethertype following the last
5409 * VLAN tag of the packet (see PRM).
5410 * Set match on ethertype only if ETH header is not followed by VLAN.
5412 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5413 rte_be_to_cpu_16(eth_m->type));
5414 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5415 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5419 * Add VLAN item to matcher and to the value.
5421 * @param[in, out] dev_flow
5423 * @param[in, out] matcher
5425 * @param[in, out] key
5426 * Flow matcher value.
5428 * Flow pattern to translate.
5430 * Item is inner pattern.
5433 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5434 void *matcher, void *key,
5435 const struct rte_flow_item *item,
5438 const struct rte_flow_item_vlan *vlan_m = item->mask;
5439 const struct rte_flow_item_vlan *vlan_v = item->spec;
5448 vlan_m = &rte_flow_item_vlan_mask;
5450 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5452 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5454 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5456 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5458 * This is workaround, masks are not supported,
5459 * and pre-validated.
5461 dev_flow->handle.vf_vlan.tag =
5462 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5464 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5465 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5466 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5467 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5468 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5469 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5470 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5471 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5472 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5473 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5474 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5475 rte_be_to_cpu_16(vlan_m->inner_type));
5476 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5477 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5481 * Add IPV4 item to matcher and to the value.
5483 * @param[in, out] matcher
5485 * @param[in, out] key
5486 * Flow matcher value.
5488 * Flow pattern to translate.
5489 * @param[in] item_flags
5490 * Bit-fields that holds the items detected until now.
5492 * Item is inner pattern.
5494 * The group to insert the rule.
5497 flow_dv_translate_item_ipv4(void *matcher, void *key,
5498 const struct rte_flow_item *item,
5499 const uint64_t item_flags,
5500 int inner, uint32_t group)
5502 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5503 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5504 const struct rte_flow_item_ipv4 nic_mask = {
5506 .src_addr = RTE_BE32(0xffffffff),
5507 .dst_addr = RTE_BE32(0xffffffff),
5508 .type_of_service = 0xff,
5509 .next_proto_id = 0xff,
5510 .time_to_live = 0xff,
5520 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5522 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5524 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5526 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5529 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5531 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5534 * On outer header (which must contains L2), or inner header with L2,
5535 * set cvlan_tag mask bit to mark this packet as untagged.
5536 * This should be done even if item->spec is empty.
5538 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5539 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5544 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5545 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5546 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5547 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5548 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5549 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5550 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5551 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5552 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5553 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5554 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5555 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5556 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5557 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5558 ipv4_m->hdr.type_of_service);
5559 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5560 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5561 ipv4_m->hdr.type_of_service >> 2);
5562 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5563 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5564 ipv4_m->hdr.next_proto_id);
5565 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5566 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5567 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5568 ipv4_m->hdr.time_to_live);
5569 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5570 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5574 * Add IPV6 item to matcher and to the value.
5576 * @param[in, out] matcher
5578 * @param[in, out] key
5579 * Flow matcher value.
5581 * Flow pattern to translate.
5582 * @param[in] item_flags
5583 * Bit-fields that holds the items detected until now.
5585 * Item is inner pattern.
5587 * The group to insert the rule.
5590 flow_dv_translate_item_ipv6(void *matcher, void *key,
5591 const struct rte_flow_item *item,
5592 const uint64_t item_flags,
5593 int inner, uint32_t group)
5595 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5596 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5597 const struct rte_flow_item_ipv6 nic_mask = {
5600 "\xff\xff\xff\xff\xff\xff\xff\xff"
5601 "\xff\xff\xff\xff\xff\xff\xff\xff",
5603 "\xff\xff\xff\xff\xff\xff\xff\xff"
5604 "\xff\xff\xff\xff\xff\xff\xff\xff",
5605 .vtc_flow = RTE_BE32(0xffffffff),
5612 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5613 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5622 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5624 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5626 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5628 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5631 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5633 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5634 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5636 * On outer header (which must contains L2), or inner header with L2,
5637 * set cvlan_tag mask bit to mark this packet as untagged.
5638 * This should be done even if item->spec is empty.
5640 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5646 size = sizeof(ipv6_m->hdr.dst_addr);
5647 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5648 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5649 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5650 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5651 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5652 for (i = 0; i < size; ++i)
5653 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5654 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5655 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5656 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5657 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5658 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5659 for (i = 0; i < size; ++i)
5660 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5662 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5663 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5664 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5665 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5666 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5667 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5670 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5672 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5675 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5677 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5681 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5684 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5686 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5687 ipv6_m->hdr.hop_limits);
5688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5689 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5693 * Add TCP item to matcher and to the value.
5695 * @param[in, out] matcher
5697 * @param[in, out] key
5698 * Flow matcher value.
5700 * Flow pattern to translate.
5702 * Item is inner pattern.
5705 flow_dv_translate_item_tcp(void *matcher, void *key,
5706 const struct rte_flow_item *item,
5709 const struct rte_flow_item_tcp *tcp_m = item->mask;
5710 const struct rte_flow_item_tcp *tcp_v = item->spec;
5715 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5717 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5719 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5721 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5723 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5724 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5728 tcp_m = &rte_flow_item_tcp_mask;
5729 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5730 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5732 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5733 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5734 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5736 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5737 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5738 tcp_m->hdr.tcp_flags);
5739 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5740 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5744 * Add UDP item to matcher and to the value.
5746 * @param[in, out] matcher
5748 * @param[in, out] key
5749 * Flow matcher value.
5751 * Flow pattern to translate.
5753 * Item is inner pattern.
5756 flow_dv_translate_item_udp(void *matcher, void *key,
5757 const struct rte_flow_item *item,
5760 const struct rte_flow_item_udp *udp_m = item->mask;
5761 const struct rte_flow_item_udp *udp_v = item->spec;
5766 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5768 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5770 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5772 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5774 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5775 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5779 udp_m = &rte_flow_item_udp_mask;
5780 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5781 rte_be_to_cpu_16(udp_m->hdr.src_port));
5782 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5783 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5785 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5786 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5787 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5791 * Add GRE optional Key item to matcher and to the value.
5793 * @param[in, out] matcher
5795 * @param[in, out] key
5796 * Flow matcher value.
5798 * Flow pattern to translate.
5800 * Item is inner pattern.
5803 flow_dv_translate_item_gre_key(void *matcher, void *key,
5804 const struct rte_flow_item *item)
5806 const rte_be32_t *key_m = item->mask;
5807 const rte_be32_t *key_v = item->spec;
5808 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5809 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5810 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5812 /* GRE K bit must be on and should already be validated */
5813 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5814 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5818 key_m = &gre_key_default_mask;
5819 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5820 rte_be_to_cpu_32(*key_m) >> 8);
5821 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5822 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5823 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5824 rte_be_to_cpu_32(*key_m) & 0xFF);
5825 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5826 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5830 * Add GRE item to matcher and to the value.
5832 * @param[in, out] matcher
5834 * @param[in, out] key
5835 * Flow matcher value.
5837 * Flow pattern to translate.
5839 * Item is inner pattern.
5842 flow_dv_translate_item_gre(void *matcher, void *key,
5843 const struct rte_flow_item *item,
5846 const struct rte_flow_item_gre *gre_m = item->mask;
5847 const struct rte_flow_item_gre *gre_v = item->spec;
5850 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5851 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5858 uint16_t s_present:1;
5859 uint16_t k_present:1;
5860 uint16_t rsvd_bit1:1;
5861 uint16_t c_present:1;
5865 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5868 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5870 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5872 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5874 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5876 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5877 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5881 gre_m = &rte_flow_item_gre_mask;
5882 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5883 rte_be_to_cpu_16(gre_m->protocol));
5884 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5885 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5886 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5887 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5888 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5889 gre_crks_rsvd0_ver_m.c_present);
5890 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5891 gre_crks_rsvd0_ver_v.c_present &
5892 gre_crks_rsvd0_ver_m.c_present);
5893 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5894 gre_crks_rsvd0_ver_m.k_present);
5895 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5896 gre_crks_rsvd0_ver_v.k_present &
5897 gre_crks_rsvd0_ver_m.k_present);
5898 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5899 gre_crks_rsvd0_ver_m.s_present);
5900 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5901 gre_crks_rsvd0_ver_v.s_present &
5902 gre_crks_rsvd0_ver_m.s_present);
5906 * Add NVGRE item to matcher and to the value.
5908 * @param[in, out] matcher
5910 * @param[in, out] key
5911 * Flow matcher value.
5913 * Flow pattern to translate.
5915 * Item is inner pattern.
5918 flow_dv_translate_item_nvgre(void *matcher, void *key,
5919 const struct rte_flow_item *item,
5922 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5923 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5924 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5925 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5926 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5927 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5933 /* For NVGRE, GRE header fields must be set with defined values. */
5934 const struct rte_flow_item_gre gre_spec = {
5935 .c_rsvd0_ver = RTE_BE16(0x2000),
5936 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5938 const struct rte_flow_item_gre gre_mask = {
5939 .c_rsvd0_ver = RTE_BE16(0xB000),
5940 .protocol = RTE_BE16(UINT16_MAX),
5942 const struct rte_flow_item gre_item = {
5947 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5951 nvgre_m = &rte_flow_item_nvgre_mask;
5952 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5953 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5954 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5955 memcpy(gre_key_m, tni_flow_id_m, size);
5956 for (i = 0; i < size; ++i)
5957 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5961 * Add VXLAN item to matcher and to the value.
5963 * @param[in, out] matcher
5965 * @param[in, out] key
5966 * Flow matcher value.
5968 * Flow pattern to translate.
5970 * Item is inner pattern.
5973 flow_dv_translate_item_vxlan(void *matcher, void *key,
5974 const struct rte_flow_item *item,
5977 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5978 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5981 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5982 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5990 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5992 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5994 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5996 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5998 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5999 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6000 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6001 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6002 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6007 vxlan_m = &rte_flow_item_vxlan_mask;
6008 size = sizeof(vxlan_m->vni);
6009 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6010 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6011 memcpy(vni_m, vxlan_m->vni, size);
6012 for (i = 0; i < size; ++i)
6013 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6017 * Add VXLAN-GPE item to matcher and to the value.
6019 * @param[in, out] matcher
6021 * @param[in, out] key
6022 * Flow matcher value.
6024 * Flow pattern to translate.
6026 * Item is inner pattern.
6030 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6031 const struct rte_flow_item *item, int inner)
6033 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6034 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6038 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6040 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6046 uint8_t flags_m = 0xff;
6047 uint8_t flags_v = 0xc;
6050 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6052 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6054 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6056 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6058 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6059 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6060 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6061 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6067 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6068 size = sizeof(vxlan_m->vni);
6069 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6070 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6071 memcpy(vni_m, vxlan_m->vni, size);
6072 for (i = 0; i < size; ++i)
6073 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6074 if (vxlan_m->flags) {
6075 flags_m = vxlan_m->flags;
6076 flags_v = vxlan_v->flags;
6078 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6079 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6080 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6082 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6087 * Add Geneve item to matcher and to the value.
6089 * @param[in, out] matcher
6091 * @param[in, out] key
6092 * Flow matcher value.
6094 * Flow pattern to translate.
6096 * Item is inner pattern.
6100 flow_dv_translate_item_geneve(void *matcher, void *key,
6101 const struct rte_flow_item *item, int inner)
6103 const struct rte_flow_item_geneve *geneve_m = item->mask;
6104 const struct rte_flow_item_geneve *geneve_v = item->spec;
6107 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6108 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6117 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6119 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6121 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6123 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6125 dport = MLX5_UDP_PORT_GENEVE;
6126 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6127 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6128 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6133 geneve_m = &rte_flow_item_geneve_mask;
6134 size = sizeof(geneve_m->vni);
6135 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6136 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6137 memcpy(vni_m, geneve_m->vni, size);
6138 for (i = 0; i < size; ++i)
6139 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6140 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6141 rte_be_to_cpu_16(geneve_m->protocol));
6142 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6143 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6144 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6145 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6146 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6147 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6148 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6149 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6150 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6151 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6152 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6153 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6154 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6158 * Add MPLS item to matcher and to the value.
6160 * @param[in, out] matcher
6162 * @param[in, out] key
6163 * Flow matcher value.
6165 * Flow pattern to translate.
6166 * @param[in] prev_layer
6167 * The protocol layer indicated in previous item.
6169 * Item is inner pattern.
6172 flow_dv_translate_item_mpls(void *matcher, void *key,
6173 const struct rte_flow_item *item,
6174 uint64_t prev_layer,
6177 const uint32_t *in_mpls_m = item->mask;
6178 const uint32_t *in_mpls_v = item->spec;
6179 uint32_t *out_mpls_m = 0;
6180 uint32_t *out_mpls_v = 0;
6181 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6182 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6183 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6185 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6186 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6187 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6189 switch (prev_layer) {
6190 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6191 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6192 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6193 MLX5_UDP_PORT_MPLS);
6195 case MLX5_FLOW_LAYER_GRE:
6196 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6197 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6198 RTE_ETHER_TYPE_MPLS);
6201 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6202 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6209 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6210 switch (prev_layer) {
6211 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6213 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6214 outer_first_mpls_over_udp);
6216 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6217 outer_first_mpls_over_udp);
6219 case MLX5_FLOW_LAYER_GRE:
6221 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6222 outer_first_mpls_over_gre);
6224 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6225 outer_first_mpls_over_gre);
6228 /* Inner MPLS not over GRE is not supported. */
6231 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6235 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6241 if (out_mpls_m && out_mpls_v) {
6242 *out_mpls_m = *in_mpls_m;
6243 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6248 * Add metadata register item to matcher
6250 * @param[in, out] matcher
6252 * @param[in, out] key
6253 * Flow matcher value.
6254 * @param[in] reg_type
6255 * Type of device metadata register
6262 flow_dv_match_meta_reg(void *matcher, void *key,
6263 enum modify_reg reg_type,
6264 uint32_t data, uint32_t mask)
6267 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6269 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6275 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6276 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6279 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6280 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6284 * The metadata register C0 field might be divided into
6285 * source vport index and META item value, we should set
6286 * this field according to specified mask, not as whole one.
6288 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6290 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6291 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6294 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6297 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6298 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6301 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6302 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6305 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6306 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6309 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6310 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6313 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6314 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6317 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6318 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6321 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6322 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6331 * Add MARK item to matcher
6334 * The device to configure through.
6335 * @param[in, out] matcher
6337 * @param[in, out] key
6338 * Flow matcher value.
6340 * Flow pattern to translate.
6343 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6344 void *matcher, void *key,
6345 const struct rte_flow_item *item)
6347 struct mlx5_priv *priv = dev->data->dev_private;
6348 const struct rte_flow_item_mark *mark;
6352 mark = item->mask ? (const void *)item->mask :
6353 &rte_flow_item_mark_mask;
6354 mask = mark->id & priv->sh->dv_mark_mask;
6355 mark = (const void *)item->spec;
6357 value = mark->id & priv->sh->dv_mark_mask & mask;
6359 enum modify_reg reg;
6361 /* Get the metadata register index for the mark. */
6362 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6363 MLX5_ASSERT(reg > 0);
6364 if (reg == REG_C_0) {
6365 struct mlx5_priv *priv = dev->data->dev_private;
6366 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6367 uint32_t shl_c0 = rte_bsf32(msk_c0);
6373 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6378 * Add META item to matcher
6381 * The devich to configure through.
6382 * @param[in, out] matcher
6384 * @param[in, out] key
6385 * Flow matcher value.
6387 * Attributes of flow that includes this item.
6389 * Flow pattern to translate.
6392 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6393 void *matcher, void *key,
6394 const struct rte_flow_attr *attr,
6395 const struct rte_flow_item *item)
6397 const struct rte_flow_item_meta *meta_m;
6398 const struct rte_flow_item_meta *meta_v;
6400 meta_m = (const void *)item->mask;
6402 meta_m = &rte_flow_item_meta_mask;
6403 meta_v = (const void *)item->spec;
6406 uint32_t value = meta_v->data;
6407 uint32_t mask = meta_m->data;
6409 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6413 * In datapath code there is no endianness
6414 * coversions for perfromance reasons, all
6415 * pattern conversions are done in rte_flow.
6417 value = rte_cpu_to_be_32(value);
6418 mask = rte_cpu_to_be_32(mask);
6419 if (reg == REG_C_0) {
6420 struct mlx5_priv *priv = dev->data->dev_private;
6421 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6422 uint32_t shl_c0 = rte_bsf32(msk_c0);
6423 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6424 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6431 MLX5_ASSERT(msk_c0);
6432 MLX5_ASSERT(!(~msk_c0 & mask));
6434 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6439 * Add vport metadata Reg C0 item to matcher
6441 * @param[in, out] matcher
6443 * @param[in, out] key
6444 * Flow matcher value.
6446 * Flow pattern to translate.
6449 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6450 uint32_t value, uint32_t mask)
6452 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6456 * Add tag item to matcher
6459 * The devich to configure through.
6460 * @param[in, out] matcher
6462 * @param[in, out] key
6463 * Flow matcher value.
6465 * Flow pattern to translate.
6468 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6469 void *matcher, void *key,
6470 const struct rte_flow_item *item)
6472 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6473 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6474 uint32_t mask, value;
6477 value = tag_v->data;
6478 mask = tag_m ? tag_m->data : UINT32_MAX;
6479 if (tag_v->id == REG_C_0) {
6480 struct mlx5_priv *priv = dev->data->dev_private;
6481 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6482 uint32_t shl_c0 = rte_bsf32(msk_c0);
6488 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6492 * Add TAG item to matcher
6495 * The devich to configure through.
6496 * @param[in, out] matcher
6498 * @param[in, out] key
6499 * Flow matcher value.
6501 * Flow pattern to translate.
6504 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6505 void *matcher, void *key,
6506 const struct rte_flow_item *item)
6508 const struct rte_flow_item_tag *tag_v = item->spec;
6509 const struct rte_flow_item_tag *tag_m = item->mask;
6510 enum modify_reg reg;
6513 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6514 /* Get the metadata register index for the tag. */
6515 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6516 MLX5_ASSERT(reg > 0);
6517 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6521 * Add source vport match to the specified matcher.
6523 * @param[in, out] matcher
6525 * @param[in, out] key
6526 * Flow matcher value.
6528 * Source vport value to match
6533 flow_dv_translate_item_source_vport(void *matcher, void *key,
6534 int16_t port, uint16_t mask)
6536 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6537 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6539 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6540 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6544 * Translate port-id item to eswitch match on port-id.
6547 * The devich to configure through.
6548 * @param[in, out] matcher
6550 * @param[in, out] key
6551 * Flow matcher value.
6553 * Flow pattern to translate.
6556 * 0 on success, a negative errno value otherwise.
6559 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6560 void *key, const struct rte_flow_item *item)
6562 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6563 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6564 struct mlx5_priv *priv;
6567 mask = pid_m ? pid_m->id : 0xffff;
6568 id = pid_v ? pid_v->id : dev->data->port_id;
6569 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6572 /* Translate to vport field or to metadata, depending on mode. */
6573 if (priv->vport_meta_mask)
6574 flow_dv_translate_item_meta_vport(matcher, key,
6575 priv->vport_meta_tag,
6576 priv->vport_meta_mask);
6578 flow_dv_translate_item_source_vport(matcher, key,
6579 priv->vport_id, mask);
6584 * Add ICMP6 item to matcher and to the value.
6586 * @param[in, out] matcher
6588 * @param[in, out] key
6589 * Flow matcher value.
6591 * Flow pattern to translate.
6593 * Item is inner pattern.
6596 flow_dv_translate_item_icmp6(void *matcher, void *key,
6597 const struct rte_flow_item *item,
6600 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6601 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6604 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6606 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6608 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6610 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6612 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6614 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6616 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6617 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6621 icmp6_m = &rte_flow_item_icmp6_mask;
6623 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6624 * If only the protocol is specified, no need to match the frag.
6626 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6627 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6628 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6629 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6630 icmp6_v->type & icmp6_m->type);
6631 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6632 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6633 icmp6_v->code & icmp6_m->code);
6637 * Add ICMP item to matcher and to the value.
6639 * @param[in, out] matcher
6641 * @param[in, out] key
6642 * Flow matcher value.
6644 * Flow pattern to translate.
6646 * Item is inner pattern.
6649 flow_dv_translate_item_icmp(void *matcher, void *key,
6650 const struct rte_flow_item *item,
6653 const struct rte_flow_item_icmp *icmp_m = item->mask;
6654 const struct rte_flow_item_icmp *icmp_v = item->spec;
6657 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6659 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6661 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6663 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6665 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6669 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6674 icmp_m = &rte_flow_item_icmp_mask;
6676 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6677 * If only the protocol is specified, no need to match the frag.
6679 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6680 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6681 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6682 icmp_m->hdr.icmp_type);
6683 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6684 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6685 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6686 icmp_m->hdr.icmp_code);
6687 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6688 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6692 * Add GTP item to matcher and to the value.
6694 * @param[in, out] matcher
6696 * @param[in, out] key
6697 * Flow matcher value.
6699 * Flow pattern to translate.
6701 * Item is inner pattern.
6704 flow_dv_translate_item_gtp(void *matcher, void *key,
6705 const struct rte_flow_item *item, int inner)
6707 const struct rte_flow_item_gtp *gtp_m = item->mask;
6708 const struct rte_flow_item_gtp *gtp_v = item->spec;
6711 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6713 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6714 uint16_t dport = RTE_GTPU_UDP_PORT;
6717 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6719 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6721 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6723 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6725 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6726 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6727 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6732 gtp_m = &rte_flow_item_gtp_mask;
6733 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6734 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6735 gtp_v->msg_type & gtp_m->msg_type);
6736 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6737 rte_be_to_cpu_32(gtp_m->teid));
6738 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6739 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6742 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6744 #define HEADER_IS_ZERO(match_criteria, headers) \
6745 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6746 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6749 * Calculate flow matcher enable bitmap.
6751 * @param match_criteria
6752 * Pointer to flow matcher criteria.
6755 * Bitmap of enabled fields.
6758 flow_dv_matcher_enable(uint32_t *match_criteria)
6760 uint8_t match_criteria_enable;
6762 match_criteria_enable =
6763 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6764 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6765 match_criteria_enable |=
6766 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6767 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6768 match_criteria_enable |=
6769 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6770 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6771 match_criteria_enable |=
6772 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6773 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6774 match_criteria_enable |=
6775 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6776 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6777 return match_criteria_enable;
6784 * @param[in, out] dev
6785 * Pointer to rte_eth_dev structure.
6786 * @param[in] table_id
6789 * Direction of the table.
6790 * @param[in] transfer
6791 * E-Switch or NIC flow.
6793 * pointer to error structure.
6796 * Returns tables resource based on the index, NULL in case of failed.
6798 static struct mlx5_flow_tbl_resource *
6799 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6800 uint32_t table_id, uint8_t egress,
6802 struct rte_flow_error *error)
6804 struct mlx5_priv *priv = dev->data->dev_private;
6805 struct mlx5_ibv_shared *sh = priv->sh;
6806 struct mlx5_flow_tbl_resource *tbl;
6807 union mlx5_flow_tbl_key table_key = {
6809 .table_id = table_id,
6811 .domain = !!transfer,
6812 .direction = !!egress,
6815 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6817 struct mlx5_flow_tbl_data_entry *tbl_data;
6822 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6824 tbl = &tbl_data->tbl;
6825 rte_atomic32_inc(&tbl->refcnt);
6828 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6830 rte_flow_error_set(error, ENOMEM,
6831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6833 "cannot allocate flow table data entry");
6836 tbl = &tbl_data->tbl;
6837 pos = &tbl_data->entry;
6839 domain = sh->fdb_domain;
6841 domain = sh->tx_domain;
6843 domain = sh->rx_domain;
6844 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6846 rte_flow_error_set(error, ENOMEM,
6847 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6848 NULL, "cannot create flow table object");
6853 * No multi-threads now, but still better to initialize the reference
6854 * count before insert it into the hash list.
6856 rte_atomic32_init(&tbl->refcnt);
6857 /* Jump action reference count is initialized here. */
6858 rte_atomic32_init(&tbl_data->jump.refcnt);
6859 pos->key = table_key.v64;
6860 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6862 rte_flow_error_set(error, -ret,
6863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6864 "cannot insert flow table data entry");
6865 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6868 rte_atomic32_inc(&tbl->refcnt);
6873 * Release a flow table.
6876 * Pointer to rte_eth_dev structure.
6878 * Table resource to be released.
6881 * Returns 0 if table was released, else return 1;
6884 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6885 struct mlx5_flow_tbl_resource *tbl)
6887 struct mlx5_priv *priv = dev->data->dev_private;
6888 struct mlx5_ibv_shared *sh = priv->sh;
6889 struct mlx5_flow_tbl_data_entry *tbl_data =
6890 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6894 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6895 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6897 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6899 /* remove the entry from the hash list and free memory. */
6900 mlx5_hlist_remove(sh->flow_tbls, pos);
6908 * Register the flow matcher.
6910 * @param[in, out] dev
6911 * Pointer to rte_eth_dev structure.
6912 * @param[in, out] matcher
6913 * Pointer to flow matcher.
6914 * @param[in, out] key
6915 * Pointer to flow table key.
6916 * @parm[in, out] dev_flow
6917 * Pointer to the dev_flow.
6919 * pointer to error structure.
6922 * 0 on success otherwise -errno and errno is set.
6925 flow_dv_matcher_register(struct rte_eth_dev *dev,
6926 struct mlx5_flow_dv_matcher *matcher,
6927 union mlx5_flow_tbl_key *key,
6928 struct mlx5_flow *dev_flow,
6929 struct rte_flow_error *error)
6931 struct mlx5_priv *priv = dev->data->dev_private;
6932 struct mlx5_ibv_shared *sh = priv->sh;
6933 struct mlx5_flow_dv_matcher *cache_matcher;
6934 struct mlx5dv_flow_matcher_attr dv_attr = {
6935 .type = IBV_FLOW_ATTR_NORMAL,
6936 .match_mask = (void *)&matcher->mask,
6938 struct mlx5_flow_tbl_resource *tbl;
6939 struct mlx5_flow_tbl_data_entry *tbl_data;
6941 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6942 key->domain, error);
6944 return -rte_errno; /* No need to refill the error info */
6945 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6946 /* Lookup from cache. */
6947 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6948 if (matcher->crc == cache_matcher->crc &&
6949 matcher->priority == cache_matcher->priority &&
6950 !memcmp((const void *)matcher->mask.buf,
6951 (const void *)cache_matcher->mask.buf,
6952 cache_matcher->mask.size)) {
6954 "%s group %u priority %hd use %s "
6955 "matcher %p: refcnt %d++",
6956 key->domain ? "FDB" : "NIC", key->table_id,
6957 cache_matcher->priority,
6958 key->direction ? "tx" : "rx",
6959 (void *)cache_matcher,
6960 rte_atomic32_read(&cache_matcher->refcnt));
6961 rte_atomic32_inc(&cache_matcher->refcnt);
6962 dev_flow->handle.dvh.matcher = cache_matcher;
6963 /* old matcher should not make the table ref++. */
6964 flow_dv_tbl_resource_release(dev, tbl);
6968 /* Register new matcher. */
6969 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6970 if (!cache_matcher) {
6971 flow_dv_tbl_resource_release(dev, tbl);
6972 return rte_flow_error_set(error, ENOMEM,
6973 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6974 "cannot allocate matcher memory");
6976 *cache_matcher = *matcher;
6977 dv_attr.match_criteria_enable =
6978 flow_dv_matcher_enable(cache_matcher->mask.buf);
6979 dv_attr.priority = matcher->priority;
6981 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6982 cache_matcher->matcher_object =
6983 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6984 if (!cache_matcher->matcher_object) {
6985 rte_free(cache_matcher);
6986 #ifdef HAVE_MLX5DV_DR
6987 flow_dv_tbl_resource_release(dev, tbl);
6989 return rte_flow_error_set(error, ENOMEM,
6990 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6991 NULL, "cannot create matcher");
6993 /* Save the table information */
6994 cache_matcher->tbl = tbl;
6995 rte_atomic32_init(&cache_matcher->refcnt);
6996 /* only matcher ref++, table ref++ already done above in get API. */
6997 rte_atomic32_inc(&cache_matcher->refcnt);
6998 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6999 dev_flow->handle.dvh.matcher = cache_matcher;
7000 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7001 key->domain ? "FDB" : "NIC", key->table_id,
7002 cache_matcher->priority,
7003 key->direction ? "tx" : "rx", (void *)cache_matcher,
7004 rte_atomic32_read(&cache_matcher->refcnt));
7009 * Find existing tag resource or create and register a new one.
7011 * @param dev[in, out]
7012 * Pointer to rte_eth_dev structure.
7013 * @param[in, out] tag_be24
7014 * Tag value in big endian then R-shift 8.
7015 * @parm[in, out] dev_flow
7016 * Pointer to the dev_flow.
7018 * pointer to error structure.
7021 * 0 on success otherwise -errno and errno is set.
7024 flow_dv_tag_resource_register
7025 (struct rte_eth_dev *dev,
7027 struct mlx5_flow *dev_flow,
7028 struct rte_flow_error *error)
7030 struct mlx5_priv *priv = dev->data->dev_private;
7031 struct mlx5_ibv_shared *sh = priv->sh;
7032 struct mlx5_flow_dv_tag_resource *cache_resource;
7033 struct mlx5_hlist_entry *entry;
7035 /* Lookup a matching resource from cache. */
7036 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7038 cache_resource = container_of
7039 (entry, struct mlx5_flow_dv_tag_resource, entry);
7040 rte_atomic32_inc(&cache_resource->refcnt);
7041 dev_flow->handle.dvh.tag_resource = cache_resource;
7042 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7043 (void *)cache_resource,
7044 rte_atomic32_read(&cache_resource->refcnt));
7047 /* Register new resource. */
7048 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7049 if (!cache_resource)
7050 return rte_flow_error_set(error, ENOMEM,
7051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7052 "cannot allocate resource memory");
7053 cache_resource->entry.key = (uint64_t)tag_be24;
7054 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7055 if (!cache_resource->action) {
7056 rte_free(cache_resource);
7057 return rte_flow_error_set(error, ENOMEM,
7058 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7059 NULL, "cannot create action");
7061 rte_atomic32_init(&cache_resource->refcnt);
7062 rte_atomic32_inc(&cache_resource->refcnt);
7063 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7064 mlx5_glue->destroy_flow_action(cache_resource->action);
7065 rte_free(cache_resource);
7066 return rte_flow_error_set(error, EEXIST,
7067 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7068 NULL, "cannot insert tag");
7070 dev_flow->handle.dvh.tag_resource = cache_resource;
7071 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7072 (void *)cache_resource,
7073 rte_atomic32_read(&cache_resource->refcnt));
7081 * Pointer to Ethernet device.
7083 * Pointer to mlx5_flow.
7086 * 1 while a reference on it exists, 0 when freed.
7089 flow_dv_tag_release(struct rte_eth_dev *dev,
7090 struct mlx5_flow_dv_tag_resource *tag)
7092 struct mlx5_priv *priv = dev->data->dev_private;
7093 struct mlx5_ibv_shared *sh = priv->sh;
7096 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7097 dev->data->port_id, (void *)tag,
7098 rte_atomic32_read(&tag->refcnt));
7099 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7100 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7101 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7102 DRV_LOG(DEBUG, "port %u tag %p: removed",
7103 dev->data->port_id, (void *)tag);
7111 * Translate port ID action to vport.
7114 * Pointer to rte_eth_dev structure.
7116 * Pointer to the port ID action.
7117 * @param[out] dst_port_id
7118 * The target port ID.
7120 * Pointer to the error structure.
7123 * 0 on success, a negative errno value otherwise and rte_errno is set.
7126 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7127 const struct rte_flow_action *action,
7128 uint32_t *dst_port_id,
7129 struct rte_flow_error *error)
7132 struct mlx5_priv *priv;
7133 const struct rte_flow_action_port_id *conf =
7134 (const struct rte_flow_action_port_id *)action->conf;
7136 port = conf->original ? dev->data->port_id : conf->id;
7137 priv = mlx5_port_to_eswitch_info(port, false);
7139 return rte_flow_error_set(error, -rte_errno,
7140 RTE_FLOW_ERROR_TYPE_ACTION,
7142 "No eswitch info was found for port");
7143 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7145 * This parameter is transferred to
7146 * mlx5dv_dr_action_create_dest_ib_port().
7148 *dst_port_id = priv->ibv_port;
7151 * Legacy mode, no LAG configurations is supported.
7152 * This parameter is transferred to
7153 * mlx5dv_dr_action_create_dest_vport().
7155 *dst_port_id = priv->vport_id;
7161 * Add Tx queue matcher
7164 * Pointer to the dev struct.
7165 * @param[in, out] matcher
7167 * @param[in, out] key
7168 * Flow matcher value.
7170 * Flow pattern to translate.
7172 * Item is inner pattern.
7175 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7176 void *matcher, void *key,
7177 const struct rte_flow_item *item)
7179 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7180 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7182 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7184 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7185 struct mlx5_txq_ctrl *txq;
7189 queue_m = (const void *)item->mask;
7192 queue_v = (const void *)item->spec;
7195 txq = mlx5_txq_get(dev, queue_v->queue);
7198 queue = txq->obj->sq->id;
7199 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7200 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7201 queue & queue_m->queue);
7202 mlx5_txq_release(dev, queue_v->queue);
7206 * Set the hash fields according to the @p flow information.
7208 * @param[in] dev_flow
7209 * Pointer to the mlx5_flow.
7212 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7214 struct rte_flow *flow = dev_flow->flow;
7215 uint64_t items = dev_flow->handle.layers;
7217 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7219 dev_flow->hash_fields = 0;
7220 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7221 if (flow->rss.level >= 2) {
7222 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7226 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7227 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7228 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7229 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7230 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7231 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7232 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7234 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7236 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7237 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7238 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7239 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7240 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7241 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7242 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7244 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7247 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7248 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7249 if (rss_types & ETH_RSS_UDP) {
7250 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7251 dev_flow->hash_fields |=
7252 IBV_RX_HASH_SRC_PORT_UDP;
7253 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7254 dev_flow->hash_fields |=
7255 IBV_RX_HASH_DST_PORT_UDP;
7257 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7259 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7260 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7261 if (rss_types & ETH_RSS_TCP) {
7262 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7263 dev_flow->hash_fields |=
7264 IBV_RX_HASH_SRC_PORT_TCP;
7265 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7266 dev_flow->hash_fields |=
7267 IBV_RX_HASH_DST_PORT_TCP;
7269 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7275 * Fill the flow with DV spec, lock free
7276 * (mutex should be acquired by caller).
7279 * Pointer to rte_eth_dev structure.
7280 * @param[in, out] dev_flow
7281 * Pointer to the sub flow.
7283 * Pointer to the flow attributes.
7285 * Pointer to the list of items.
7286 * @param[in] actions
7287 * Pointer to the list of actions.
7289 * Pointer to the error structure.
7292 * 0 on success, a negative errno value otherwise and rte_errno is set.
7295 __flow_dv_translate(struct rte_eth_dev *dev,
7296 struct mlx5_flow *dev_flow,
7297 const struct rte_flow_attr *attr,
7298 const struct rte_flow_item items[],
7299 const struct rte_flow_action actions[],
7300 struct rte_flow_error *error)
7302 struct mlx5_priv *priv = dev->data->dev_private;
7303 struct mlx5_dev_config *dev_conf = &priv->config;
7304 struct rte_flow *flow = dev_flow->flow;
7305 uint64_t item_flags = 0;
7306 uint64_t last_item = 0;
7307 uint64_t action_flags = 0;
7308 uint64_t priority = attr->priority;
7309 struct mlx5_flow_dv_matcher matcher = {
7311 .size = sizeof(matcher.mask.buf),
7315 bool actions_end = false;
7317 struct mlx5_flow_dv_modify_hdr_resource res;
7318 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7319 sizeof(struct mlx5_modification_cmd) *
7320 (MLX5_MAX_MODIFY_NUM + 1)];
7322 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7323 union flow_dv_attr flow_attr = { .attr = 0 };
7325 union mlx5_flow_tbl_key tbl_key;
7326 uint32_t modify_action_position = UINT32_MAX;
7327 void *match_mask = matcher.mask.buf;
7328 void *match_value = dev_flow->dv.value.buf;
7329 uint8_t next_protocol = 0xff;
7330 struct rte_vlan_hdr vlan = { 0 };
7334 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7335 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7336 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7337 !!priv->fdb_def_rule, &table, error);
7340 dev_flow->dv.group = table;
7342 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7343 if (priority == MLX5_FLOW_PRIO_RSVD)
7344 priority = dev_conf->flow_prio - 1;
7345 /* number of actions must be set to 0 in case of dirty stack. */
7346 mhdr_res->actions_num = 0;
7347 for (; !actions_end ; actions++) {
7348 const struct rte_flow_action_queue *queue;
7349 const struct rte_flow_action_rss *rss;
7350 const struct rte_flow_action *action = actions;
7351 const struct rte_flow_action_count *count = action->conf;
7352 const uint8_t *rss_key;
7353 const struct rte_flow_action_jump *jump_data;
7354 const struct rte_flow_action_meter *mtr;
7355 struct mlx5_flow_tbl_resource *tbl;
7356 uint32_t port_id = 0;
7357 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7358 int action_type = actions->type;
7359 const struct rte_flow_action *found_action = NULL;
7361 switch (action_type) {
7362 case RTE_FLOW_ACTION_TYPE_VOID:
7364 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7365 if (flow_dv_translate_action_port_id(dev, action,
7368 port_id_resource.port_id = port_id;
7369 if (flow_dv_port_id_action_resource_register
7370 (dev, &port_id_resource, dev_flow, error))
7372 dev_flow->dv.actions[actions_n++] =
7373 dev_flow->handle.dvh.port_id_action->action;
7374 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7376 case RTE_FLOW_ACTION_TYPE_FLAG:
7377 action_flags |= MLX5_FLOW_ACTION_FLAG;
7378 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7379 struct rte_flow_action_mark mark = {
7380 .id = MLX5_FLOW_MARK_DEFAULT,
7383 if (flow_dv_convert_action_mark(dev, &mark,
7387 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7390 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7391 if (!dev_flow->handle.dvh.tag_resource)
7392 if (flow_dv_tag_resource_register
7393 (dev, tag_be, dev_flow, error))
7395 dev_flow->dv.actions[actions_n++] =
7396 dev_flow->handle.dvh.tag_resource->action;
7398 case RTE_FLOW_ACTION_TYPE_MARK:
7399 action_flags |= MLX5_FLOW_ACTION_MARK;
7400 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7401 const struct rte_flow_action_mark *mark =
7402 (const struct rte_flow_action_mark *)
7405 if (flow_dv_convert_action_mark(dev, mark,
7409 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7413 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7414 /* Legacy (non-extensive) MARK action. */
7415 tag_be = mlx5_flow_mark_set
7416 (((const struct rte_flow_action_mark *)
7417 (actions->conf))->id);
7418 if (!dev_flow->handle.dvh.tag_resource)
7419 if (flow_dv_tag_resource_register
7420 (dev, tag_be, dev_flow, error))
7422 dev_flow->dv.actions[actions_n++] =
7423 dev_flow->handle.dvh.tag_resource->action;
7425 case RTE_FLOW_ACTION_TYPE_SET_META:
7426 if (flow_dv_convert_action_set_meta
7427 (dev, mhdr_res, attr,
7428 (const struct rte_flow_action_set_meta *)
7429 actions->conf, error))
7431 action_flags |= MLX5_FLOW_ACTION_SET_META;
7433 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7434 if (flow_dv_convert_action_set_tag
7436 (const struct rte_flow_action_set_tag *)
7437 actions->conf, error))
7439 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7441 case RTE_FLOW_ACTION_TYPE_DROP:
7442 action_flags |= MLX5_FLOW_ACTION_DROP;
7444 case RTE_FLOW_ACTION_TYPE_QUEUE:
7445 MLX5_ASSERT(flow->rss.queue);
7446 queue = actions->conf;
7447 flow->rss.queue_num = 1;
7448 (*flow->rss.queue)[0] = queue->index;
7449 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7451 case RTE_FLOW_ACTION_TYPE_RSS:
7452 MLX5_ASSERT(flow->rss.queue);
7453 rss = actions->conf;
7454 if (flow->rss.queue)
7455 memcpy((*flow->rss.queue), rss->queue,
7456 rss->queue_num * sizeof(uint16_t));
7457 flow->rss.queue_num = rss->queue_num;
7458 /* NULL RSS key indicates default RSS key. */
7459 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7460 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7462 * rss->level and rss.types should be set in advance
7463 * when expanding items for RSS.
7465 action_flags |= MLX5_FLOW_ACTION_RSS;
7467 case RTE_FLOW_ACTION_TYPE_COUNT:
7468 if (!dev_conf->devx) {
7469 rte_errno = ENOTSUP;
7472 flow->counter = flow_dv_counter_alloc(dev,
7475 dev_flow->dv.group);
7476 if (flow->counter == NULL)
7478 dev_flow->dv.actions[actions_n++] =
7479 flow->counter->action;
7480 action_flags |= MLX5_FLOW_ACTION_COUNT;
7483 if (rte_errno == ENOTSUP)
7484 return rte_flow_error_set
7486 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7488 "count action not supported");
7490 return rte_flow_error_set
7492 RTE_FLOW_ERROR_TYPE_ACTION,
7494 "cannot create counter"
7497 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7498 dev_flow->dv.actions[actions_n++] =
7499 priv->sh->pop_vlan_action;
7500 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7502 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7503 flow_dev_get_vlan_info_from_items(items, &vlan);
7504 vlan.eth_proto = rte_be_to_cpu_16
7505 ((((const struct rte_flow_action_of_push_vlan *)
7506 actions->conf)->ethertype));
7507 found_action = mlx5_flow_find_action
7509 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7511 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7512 found_action = mlx5_flow_find_action
7514 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7516 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7517 if (flow_dv_create_action_push_vlan
7518 (dev, attr, &vlan, dev_flow, error))
7520 dev_flow->dv.actions[actions_n++] =
7521 dev_flow->handle.dvh.push_vlan_res->action;
7522 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7524 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7525 /* of_vlan_push action handled this action */
7526 MLX5_ASSERT(action_flags &
7527 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7529 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7530 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7532 flow_dev_get_vlan_info_from_items(items, &vlan);
7533 mlx5_update_vlan_vid_pcp(actions, &vlan);
7534 /* If no VLAN push - this is a modify header action */
7535 if (flow_dv_convert_action_modify_vlan_vid
7536 (mhdr_res, actions, error))
7538 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7540 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7541 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7542 if (flow_dv_create_action_l2_encap(dev, actions,
7547 dev_flow->dv.actions[actions_n++] =
7548 dev_flow->handle.dvh.encap_decap->verbs_action;
7549 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7551 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7552 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7553 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7557 dev_flow->dv.actions[actions_n++] =
7558 dev_flow->handle.dvh.encap_decap->verbs_action;
7559 action_flags |= MLX5_FLOW_ACTION_DECAP;
7561 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7562 /* Handle encap with preceding decap. */
7563 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7564 if (flow_dv_create_action_raw_encap
7565 (dev, actions, dev_flow, attr, error))
7567 dev_flow->dv.actions[actions_n++] =
7568 dev_flow->handle.dvh.encap_decap->verbs_action;
7570 /* Handle encap without preceding decap. */
7571 if (flow_dv_create_action_l2_encap
7572 (dev, actions, dev_flow, attr->transfer,
7575 dev_flow->dv.actions[actions_n++] =
7576 dev_flow->handle.dvh.encap_decap->verbs_action;
7578 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7580 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7581 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7583 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7584 if (flow_dv_create_action_l2_decap
7585 (dev, dev_flow, attr->transfer, error))
7587 dev_flow->dv.actions[actions_n++] =
7588 dev_flow->handle.dvh.encap_decap->verbs_action;
7590 /* If decap is followed by encap, handle it at encap. */
7591 action_flags |= MLX5_FLOW_ACTION_DECAP;
7593 case RTE_FLOW_ACTION_TYPE_JUMP:
7594 jump_data = action->conf;
7595 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7597 !!priv->fdb_def_rule,
7601 tbl = flow_dv_tbl_resource_get(dev, table,
7603 attr->transfer, error);
7605 return rte_flow_error_set
7607 RTE_FLOW_ERROR_TYPE_ACTION,
7609 "cannot create jump action.");
7610 if (flow_dv_jump_tbl_resource_register
7611 (dev, tbl, dev_flow, error)) {
7612 flow_dv_tbl_resource_release(dev, tbl);
7613 return rte_flow_error_set
7615 RTE_FLOW_ERROR_TYPE_ACTION,
7617 "cannot create jump action.");
7619 dev_flow->dv.actions[actions_n++] =
7620 dev_flow->handle.dvh.jump->action;
7621 action_flags |= MLX5_FLOW_ACTION_JUMP;
7623 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7624 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7625 if (flow_dv_convert_action_modify_mac
7626 (mhdr_res, actions, error))
7628 action_flags |= actions->type ==
7629 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7630 MLX5_FLOW_ACTION_SET_MAC_SRC :
7631 MLX5_FLOW_ACTION_SET_MAC_DST;
7633 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7634 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7635 if (flow_dv_convert_action_modify_ipv4
7636 (mhdr_res, actions, error))
7638 action_flags |= actions->type ==
7639 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7640 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7641 MLX5_FLOW_ACTION_SET_IPV4_DST;
7643 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7644 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7645 if (flow_dv_convert_action_modify_ipv6
7646 (mhdr_res, actions, error))
7648 action_flags |= actions->type ==
7649 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7650 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7651 MLX5_FLOW_ACTION_SET_IPV6_DST;
7653 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7654 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7655 if (flow_dv_convert_action_modify_tp
7656 (mhdr_res, actions, items,
7657 &flow_attr, dev_flow, !!(action_flags &
7658 MLX5_FLOW_ACTION_DECAP), error))
7660 action_flags |= actions->type ==
7661 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7662 MLX5_FLOW_ACTION_SET_TP_SRC :
7663 MLX5_FLOW_ACTION_SET_TP_DST;
7665 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7666 if (flow_dv_convert_action_modify_dec_ttl
7667 (mhdr_res, items, &flow_attr, dev_flow,
7669 MLX5_FLOW_ACTION_DECAP), error))
7671 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7673 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7674 if (flow_dv_convert_action_modify_ttl
7675 (mhdr_res, actions, items, &flow_attr,
7676 dev_flow, !!(action_flags &
7677 MLX5_FLOW_ACTION_DECAP), error))
7679 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7681 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7682 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7683 if (flow_dv_convert_action_modify_tcp_seq
7684 (mhdr_res, actions, error))
7686 action_flags |= actions->type ==
7687 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7688 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7689 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7692 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7693 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7694 if (flow_dv_convert_action_modify_tcp_ack
7695 (mhdr_res, actions, error))
7697 action_flags |= actions->type ==
7698 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7699 MLX5_FLOW_ACTION_INC_TCP_ACK :
7700 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7702 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7703 if (flow_dv_convert_action_set_reg
7704 (mhdr_res, actions, error))
7706 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7708 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7709 if (flow_dv_convert_action_copy_mreg
7710 (dev, mhdr_res, actions, error))
7712 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7714 case RTE_FLOW_ACTION_TYPE_METER:
7715 mtr = actions->conf;
7717 flow->meter = mlx5_flow_meter_attach(priv,
7721 return rte_flow_error_set(error,
7723 RTE_FLOW_ERROR_TYPE_ACTION,
7726 "or invalid parameters");
7728 /* Set the meter action. */
7729 dev_flow->dv.actions[actions_n++] =
7730 flow->meter->mfts->meter_action;
7731 action_flags |= MLX5_FLOW_ACTION_METER;
7733 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7734 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7737 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7739 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7740 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7743 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7745 case RTE_FLOW_ACTION_TYPE_END:
7747 if (mhdr_res->actions_num) {
7748 /* create modify action if needed. */
7749 if (flow_dv_modify_hdr_resource_register
7750 (dev, mhdr_res, dev_flow, error))
7752 dev_flow->dv.actions[modify_action_position] =
7753 dev_flow->handle.dvh.modify_hdr->verbs_action;
7759 if (mhdr_res->actions_num &&
7760 modify_action_position == UINT32_MAX)
7761 modify_action_position = actions_n++;
7763 dev_flow->dv.actions_n = actions_n;
7764 dev_flow->handle.act_flags = action_flags;
7765 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7766 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7767 int item_type = items->type;
7769 switch (item_type) {
7770 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7771 flow_dv_translate_item_port_id(dev, match_mask,
7772 match_value, items);
7773 last_item = MLX5_FLOW_ITEM_PORT_ID;
7775 case RTE_FLOW_ITEM_TYPE_ETH:
7776 flow_dv_translate_item_eth(match_mask, match_value,
7778 matcher.priority = MLX5_PRIORITY_MAP_L2;
7779 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7780 MLX5_FLOW_LAYER_OUTER_L2;
7782 case RTE_FLOW_ITEM_TYPE_VLAN:
7783 flow_dv_translate_item_vlan(dev_flow,
7784 match_mask, match_value,
7786 matcher.priority = MLX5_PRIORITY_MAP_L2;
7787 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7788 MLX5_FLOW_LAYER_INNER_VLAN) :
7789 (MLX5_FLOW_LAYER_OUTER_L2 |
7790 MLX5_FLOW_LAYER_OUTER_VLAN);
7792 case RTE_FLOW_ITEM_TYPE_IPV4:
7793 mlx5_flow_tunnel_ip_check(items, next_protocol,
7794 &item_flags, &tunnel);
7795 flow_dv_translate_item_ipv4(match_mask, match_value,
7796 items, item_flags, tunnel,
7797 dev_flow->dv.group);
7798 matcher.priority = MLX5_PRIORITY_MAP_L3;
7799 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7800 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7801 if (items->mask != NULL &&
7802 ((const struct rte_flow_item_ipv4 *)
7803 items->mask)->hdr.next_proto_id) {
7805 ((const struct rte_flow_item_ipv4 *)
7806 (items->spec))->hdr.next_proto_id;
7808 ((const struct rte_flow_item_ipv4 *)
7809 (items->mask))->hdr.next_proto_id;
7811 /* Reset for inner layer. */
7812 next_protocol = 0xff;
7815 case RTE_FLOW_ITEM_TYPE_IPV6:
7816 mlx5_flow_tunnel_ip_check(items, next_protocol,
7817 &item_flags, &tunnel);
7818 flow_dv_translate_item_ipv6(match_mask, match_value,
7819 items, item_flags, tunnel,
7820 dev_flow->dv.group);
7821 matcher.priority = MLX5_PRIORITY_MAP_L3;
7822 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7823 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7824 if (items->mask != NULL &&
7825 ((const struct rte_flow_item_ipv6 *)
7826 items->mask)->hdr.proto) {
7828 ((const struct rte_flow_item_ipv6 *)
7829 items->spec)->hdr.proto;
7831 ((const struct rte_flow_item_ipv6 *)
7832 items->mask)->hdr.proto;
7834 /* Reset for inner layer. */
7835 next_protocol = 0xff;
7838 case RTE_FLOW_ITEM_TYPE_TCP:
7839 flow_dv_translate_item_tcp(match_mask, match_value,
7841 matcher.priority = MLX5_PRIORITY_MAP_L4;
7842 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7843 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7845 case RTE_FLOW_ITEM_TYPE_UDP:
7846 flow_dv_translate_item_udp(match_mask, match_value,
7848 matcher.priority = MLX5_PRIORITY_MAP_L4;
7849 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7850 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7852 case RTE_FLOW_ITEM_TYPE_GRE:
7853 flow_dv_translate_item_gre(match_mask, match_value,
7855 matcher.priority = flow->rss.level >= 2 ?
7856 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7857 last_item = MLX5_FLOW_LAYER_GRE;
7859 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7860 flow_dv_translate_item_gre_key(match_mask,
7861 match_value, items);
7862 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7864 case RTE_FLOW_ITEM_TYPE_NVGRE:
7865 flow_dv_translate_item_nvgre(match_mask, match_value,
7867 matcher.priority = flow->rss.level >= 2 ?
7868 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7869 last_item = MLX5_FLOW_LAYER_GRE;
7871 case RTE_FLOW_ITEM_TYPE_VXLAN:
7872 flow_dv_translate_item_vxlan(match_mask, match_value,
7874 matcher.priority = flow->rss.level >= 2 ?
7875 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7876 last_item = MLX5_FLOW_LAYER_VXLAN;
7878 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7879 flow_dv_translate_item_vxlan_gpe(match_mask,
7882 matcher.priority = flow->rss.level >= 2 ?
7883 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7884 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7886 case RTE_FLOW_ITEM_TYPE_GENEVE:
7887 flow_dv_translate_item_geneve(match_mask, match_value,
7889 matcher.priority = flow->rss.level >= 2 ?
7890 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7891 last_item = MLX5_FLOW_LAYER_GENEVE;
7893 case RTE_FLOW_ITEM_TYPE_MPLS:
7894 flow_dv_translate_item_mpls(match_mask, match_value,
7895 items, last_item, tunnel);
7896 matcher.priority = flow->rss.level >= 2 ?
7897 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7898 last_item = MLX5_FLOW_LAYER_MPLS;
7900 case RTE_FLOW_ITEM_TYPE_MARK:
7901 flow_dv_translate_item_mark(dev, match_mask,
7902 match_value, items);
7903 last_item = MLX5_FLOW_ITEM_MARK;
7905 case RTE_FLOW_ITEM_TYPE_META:
7906 flow_dv_translate_item_meta(dev, match_mask,
7907 match_value, attr, items);
7908 last_item = MLX5_FLOW_ITEM_METADATA;
7910 case RTE_FLOW_ITEM_TYPE_ICMP:
7911 flow_dv_translate_item_icmp(match_mask, match_value,
7913 last_item = MLX5_FLOW_LAYER_ICMP;
7915 case RTE_FLOW_ITEM_TYPE_ICMP6:
7916 flow_dv_translate_item_icmp6(match_mask, match_value,
7918 last_item = MLX5_FLOW_LAYER_ICMP6;
7920 case RTE_FLOW_ITEM_TYPE_TAG:
7921 flow_dv_translate_item_tag(dev, match_mask,
7922 match_value, items);
7923 last_item = MLX5_FLOW_ITEM_TAG;
7925 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7926 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7927 match_value, items);
7928 last_item = MLX5_FLOW_ITEM_TAG;
7930 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7931 flow_dv_translate_item_tx_queue(dev, match_mask,
7934 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7936 case RTE_FLOW_ITEM_TYPE_GTP:
7937 flow_dv_translate_item_gtp(match_mask, match_value,
7939 matcher.priority = flow->rss.level >= 2 ?
7940 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7941 last_item = MLX5_FLOW_LAYER_GTP;
7946 item_flags |= last_item;
7949 * When E-Switch mode is enabled, we have two cases where we need to
7950 * set the source port manually.
7951 * The first one, is in case of Nic steering rule, and the second is
7952 * E-Switch rule where no port_id item was found. In both cases
7953 * the source port is set according the current port in use.
7955 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7956 (priv->representor || priv->master)) {
7957 if (flow_dv_translate_item_port_id(dev, match_mask,
7961 #ifdef RTE_LIBRTE_MLX5_DEBUG
7962 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7963 dev_flow->dv.value.buf));
7966 * Layers may be already initialized from prefix flow if this dev_flow
7967 * is the suffix flow.
7969 dev_flow->handle.layers |= item_flags;
7970 if (action_flags & MLX5_FLOW_ACTION_RSS)
7971 flow_dv_hashfields_set(dev_flow);
7972 /* Register matcher. */
7973 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7975 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7977 /* reserved field no needs to be set to 0 here. */
7978 tbl_key.domain = attr->transfer;
7979 tbl_key.direction = attr->egress;
7980 tbl_key.table_id = dev_flow->dv.group;
7981 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7987 * Apply the flow to the NIC, lock free,
7988 * (mutex should be acquired by caller).
7991 * Pointer to the Ethernet device structure.
7992 * @param[in, out] flow
7993 * Pointer to flow structure.
7995 * Pointer to error structure.
7998 * 0 on success, a negative errno value otherwise and rte_errno is set.
8001 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8002 struct rte_flow_error *error)
8004 struct mlx5_flow_resource_dv *dv;
8005 struct mlx5_flow_handle *dh;
8006 struct mlx5_flow_handle_dv *dv_h;
8007 struct mlx5_flow *dev_flow;
8008 struct mlx5_priv *priv = dev->data->dev_private;
8012 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8013 dh = &dev_flow->handle;
8017 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8019 dv->actions[n++] = priv->sh->esw_drop_action;
8021 dh->hrxq = mlx5_hrxq_drop_new(dev);
8025 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8027 "cannot get drop hash queue");
8030 dv->actions[n++] = dh->hrxq->action;
8032 } else if (dh->act_flags &
8033 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8034 struct mlx5_hrxq *hrxq;
8036 MLX5_ASSERT(flow->rss.queue);
8037 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8038 MLX5_RSS_HASH_KEY_LEN,
8039 dev_flow->hash_fields,
8041 flow->rss.queue_num);
8043 hrxq = mlx5_hrxq_new
8044 (dev, flow->rss.key,
8045 MLX5_RSS_HASH_KEY_LEN,
8046 dev_flow->hash_fields,
8048 flow->rss.queue_num,
8049 !!(dev_flow->handle.layers &
8050 MLX5_FLOW_LAYER_TUNNEL));
8055 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8056 "cannot get hash queue");
8060 dv->actions[n++] = dh->hrxq->action;
8063 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8064 (void *)&dv->value, n,
8067 rte_flow_error_set(error, errno,
8068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8070 "hardware refuses to create flow");
8073 if (priv->vmwa_context &&
8074 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8076 * The rule contains the VLAN pattern.
8077 * For VF we are going to create VLAN
8078 * interface to make hypervisor set correct
8079 * e-Switch vport context.
8081 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8086 err = rte_errno; /* Save rte_errno before cleanup. */
8087 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8088 struct mlx5_flow_handle *dh_tmp = &dev_flow->handle;
8090 if (dh_tmp->act_flags & MLX5_FLOW_ACTION_DROP)
8091 mlx5_hrxq_drop_release(dev);
8093 mlx5_hrxq_release(dev, dh_tmp->hrxq);
8094 dh_tmp->hrxq = NULL;
8096 if (dh_tmp->vf_vlan.tag && dh_tmp->vf_vlan.created)
8097 mlx5_vlan_vmwa_release(dev, &dh_tmp->vf_vlan);
8099 rte_errno = err; /* Restore rte_errno. */
8104 * Release the flow matcher.
8107 * Pointer to Ethernet device.
8109 * Pointer to mlx5_flow.
8112 * 1 while a reference on it exists, 0 when freed.
8115 flow_dv_matcher_release(struct rte_eth_dev *dev,
8116 struct mlx5_flow *flow)
8118 struct mlx5_flow_dv_matcher *matcher = flow->handle.dvh.matcher;
8120 MLX5_ASSERT(matcher->matcher_object);
8121 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8122 dev->data->port_id, (void *)matcher,
8123 rte_atomic32_read(&matcher->refcnt));
8124 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8125 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8126 (matcher->matcher_object));
8127 LIST_REMOVE(matcher, next);
8128 /* table ref-- in release interface. */
8129 flow_dv_tbl_resource_release(dev, matcher->tbl);
8131 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8132 dev->data->port_id, (void *)matcher);
8139 * Release an encap/decap resource.
8142 * Pointer to mlx5_flow.
8145 * 1 while a reference on it exists, 0 when freed.
8148 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
8150 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8151 flow->handle.dvh.encap_decap;
8153 MLX5_ASSERT(cache_resource->verbs_action);
8154 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8155 (void *)cache_resource,
8156 rte_atomic32_read(&cache_resource->refcnt));
8157 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8158 claim_zero(mlx5_glue->destroy_flow_action
8159 (cache_resource->verbs_action));
8160 LIST_REMOVE(cache_resource, next);
8161 rte_free(cache_resource);
8162 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8163 (void *)cache_resource);
8170 * Release an jump to table action resource.
8173 * Pointer to Ethernet device.
8175 * Pointer to mlx5_flow.
8178 * 1 while a reference on it exists, 0 when freed.
8181 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8182 struct mlx5_flow *flow)
8184 struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8185 flow->handle.dvh.jump;
8186 struct mlx5_flow_tbl_data_entry *tbl_data =
8187 container_of(cache_resource,
8188 struct mlx5_flow_tbl_data_entry, jump);
8190 MLX5_ASSERT(cache_resource->action);
8191 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8192 (void *)cache_resource,
8193 rte_atomic32_read(&cache_resource->refcnt));
8194 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8195 claim_zero(mlx5_glue->destroy_flow_action
8196 (cache_resource->action));
8197 /* jump action memory free is inside the table release. */
8198 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8199 DRV_LOG(DEBUG, "jump table resource %p: removed",
8200 (void *)cache_resource);
8207 * Release a modify-header resource.
8210 * Pointer to mlx5_flow.
8213 * 1 while a reference on it exists, 0 when freed.
8216 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
8218 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8219 flow->handle.dvh.modify_hdr;
8221 MLX5_ASSERT(cache_resource->verbs_action);
8222 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8223 (void *)cache_resource,
8224 rte_atomic32_read(&cache_resource->refcnt));
8225 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8226 claim_zero(mlx5_glue->destroy_flow_action
8227 (cache_resource->verbs_action));
8228 LIST_REMOVE(cache_resource, next);
8229 rte_free(cache_resource);
8230 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8231 (void *)cache_resource);
8238 * Release port ID action resource.
8241 * Pointer to mlx5_flow.
8244 * 1 while a reference on it exists, 0 when freed.
8247 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
8249 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8250 flow->handle.dvh.port_id_action;
8252 MLX5_ASSERT(cache_resource->action);
8253 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8254 (void *)cache_resource,
8255 rte_atomic32_read(&cache_resource->refcnt));
8256 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8257 claim_zero(mlx5_glue->destroy_flow_action
8258 (cache_resource->action));
8259 LIST_REMOVE(cache_resource, next);
8260 rte_free(cache_resource);
8261 DRV_LOG(DEBUG, "port id action resource %p: removed",
8262 (void *)cache_resource);
8269 * Release push vlan action resource.
8272 * Pointer to mlx5_flow.
8275 * 1 while a reference on it exists, 0 when freed.
8278 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8280 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8281 flow->handle.dvh.push_vlan_res;
8283 MLX5_ASSERT(cache_resource->action);
8284 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8285 (void *)cache_resource,
8286 rte_atomic32_read(&cache_resource->refcnt));
8287 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8288 claim_zero(mlx5_glue->destroy_flow_action
8289 (cache_resource->action));
8290 LIST_REMOVE(cache_resource, next);
8291 rte_free(cache_resource);
8292 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8293 (void *)cache_resource);
8300 * Remove the flow from the NIC but keeps it in memory.
8301 * Lock free, (mutex should be acquired by caller).
8304 * Pointer to Ethernet device.
8305 * @param[in, out] flow
8306 * Pointer to flow structure.
8309 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8311 struct mlx5_flow_handle *dh;
8312 struct mlx5_flow *dev_flow;
8316 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8317 dh = &dev_flow->handle;
8319 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8323 if (dev_flow->handle.act_flags & MLX5_FLOW_ACTION_DROP)
8324 mlx5_hrxq_drop_release(dev);
8326 mlx5_hrxq_release(dev, dh->hrxq);
8329 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8330 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8335 * Remove the flow from the NIC and the memory.
8336 * Lock free, (mutex should be acquired by caller).
8339 * Pointer to the Ethernet device structure.
8340 * @param[in, out] flow
8341 * Pointer to flow structure.
8344 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8346 struct mlx5_flow *dev_flow;
8350 __flow_dv_remove(dev, flow);
8351 if (flow->counter) {
8352 flow_dv_counter_release(dev, flow->counter);
8353 flow->counter = NULL;
8356 mlx5_flow_meter_detach(flow->meter);
8359 while (!LIST_EMPTY(&flow->dev_flows)) {
8360 dev_flow = LIST_FIRST(&flow->dev_flows);
8361 LIST_REMOVE(dev_flow, next);
8362 if (dev_flow->handle.dvh.matcher)
8363 flow_dv_matcher_release(dev, dev_flow);
8364 if (dev_flow->handle.dvh.encap_decap)
8365 flow_dv_encap_decap_resource_release(dev_flow);
8366 if (dev_flow->handle.dvh.modify_hdr)
8367 flow_dv_modify_hdr_resource_release(dev_flow);
8368 if (dev_flow->handle.dvh.jump)
8369 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8370 if (dev_flow->handle.dvh.port_id_action)
8371 flow_dv_port_id_action_resource_release(dev_flow);
8372 if (dev_flow->handle.dvh.push_vlan_res)
8373 flow_dv_push_vlan_action_resource_release(dev_flow);
8374 if (dev_flow->handle.dvh.tag_resource)
8375 flow_dv_tag_release(dev,
8376 dev_flow->handle.dvh.tag_resource);
8382 * Query a dv flow rule for its statistics via devx.
8385 * Pointer to Ethernet device.
8387 * Pointer to the sub flow.
8389 * data retrieved by the query.
8391 * Perform verbose error reporting if not NULL.
8394 * 0 on success, a negative errno value otherwise and rte_errno is set.
8397 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8398 void *data, struct rte_flow_error *error)
8400 struct mlx5_priv *priv = dev->data->dev_private;
8401 struct rte_flow_query_count *qc = data;
8403 if (!priv->config.devx)
8404 return rte_flow_error_set(error, ENOTSUP,
8405 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8407 "counters are not supported");
8408 if (flow->counter) {
8409 uint64_t pkts, bytes;
8410 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8414 return rte_flow_error_set(error, -err,
8415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8416 NULL, "cannot read counters");
8419 qc->hits = pkts - flow->counter->hits;
8420 qc->bytes = bytes - flow->counter->bytes;
8422 flow->counter->hits = pkts;
8423 flow->counter->bytes = bytes;
8427 return rte_flow_error_set(error, EINVAL,
8428 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8430 "counters are not available");
8436 * @see rte_flow_query()
8440 flow_dv_query(struct rte_eth_dev *dev,
8441 struct rte_flow *flow __rte_unused,
8442 const struct rte_flow_action *actions __rte_unused,
8443 void *data __rte_unused,
8444 struct rte_flow_error *error __rte_unused)
8448 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8449 switch (actions->type) {
8450 case RTE_FLOW_ACTION_TYPE_VOID:
8452 case RTE_FLOW_ACTION_TYPE_COUNT:
8453 ret = flow_dv_query_count(dev, flow, data, error);
8456 return rte_flow_error_set(error, ENOTSUP,
8457 RTE_FLOW_ERROR_TYPE_ACTION,
8459 "action not supported");
8466 * Destroy the meter table set.
8467 * Lock free, (mutex should be acquired by caller).
8470 * Pointer to Ethernet device.
8472 * Pointer to the meter table set.
8478 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8479 struct mlx5_meter_domains_infos *tbl)
8481 struct mlx5_priv *priv = dev->data->dev_private;
8482 struct mlx5_meter_domains_infos *mtd =
8483 (struct mlx5_meter_domains_infos *)tbl;
8485 if (!mtd || !priv->config.dv_flow_en)
8487 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8488 claim_zero(mlx5_glue->dv_destroy_flow
8489 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8490 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8491 claim_zero(mlx5_glue->dv_destroy_flow
8492 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8493 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8494 claim_zero(mlx5_glue->dv_destroy_flow
8495 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8496 if (mtd->egress.color_matcher)
8497 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8498 (mtd->egress.color_matcher));
8499 if (mtd->egress.any_matcher)
8500 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8501 (mtd->egress.any_matcher));
8502 if (mtd->egress.tbl)
8503 claim_zero(flow_dv_tbl_resource_release(dev,
8505 if (mtd->ingress.color_matcher)
8506 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8507 (mtd->ingress.color_matcher));
8508 if (mtd->ingress.any_matcher)
8509 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8510 (mtd->ingress.any_matcher));
8511 if (mtd->ingress.tbl)
8512 claim_zero(flow_dv_tbl_resource_release(dev,
8514 if (mtd->transfer.color_matcher)
8515 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8516 (mtd->transfer.color_matcher));
8517 if (mtd->transfer.any_matcher)
8518 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8519 (mtd->transfer.any_matcher));
8520 if (mtd->transfer.tbl)
8521 claim_zero(flow_dv_tbl_resource_release(dev,
8522 mtd->transfer.tbl));
8524 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8529 /* Number of meter flow actions, count and jump or count and drop. */
8530 #define METER_ACTIONS 2
8533 * Create specify domain meter table and suffix table.
8536 * Pointer to Ethernet device.
8537 * @param[in,out] mtb
8538 * Pointer to DV meter table set.
8541 * @param[in] transfer
8543 * @param[in] color_reg_c_idx
8544 * Reg C index for color match.
8547 * 0 on success, -1 otherwise and rte_errno is set.
8550 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8551 struct mlx5_meter_domains_infos *mtb,
8552 uint8_t egress, uint8_t transfer,
8553 uint32_t color_reg_c_idx)
8555 struct mlx5_priv *priv = dev->data->dev_private;
8556 struct mlx5_ibv_shared *sh = priv->sh;
8557 struct mlx5_flow_dv_match_params mask = {
8558 .size = sizeof(mask.buf),
8560 struct mlx5_flow_dv_match_params value = {
8561 .size = sizeof(value.buf),
8563 struct mlx5dv_flow_matcher_attr dv_attr = {
8564 .type = IBV_FLOW_ATTR_NORMAL,
8566 .match_criteria_enable = 0,
8567 .match_mask = (void *)&mask,
8569 void *actions[METER_ACTIONS];
8570 struct mlx5_flow_tbl_resource **sfx_tbl;
8571 struct mlx5_meter_domain_info *dtb;
8572 struct rte_flow_error error;
8576 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8577 dtb = &mtb->transfer;
8578 } else if (egress) {
8579 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8582 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8583 dtb = &mtb->ingress;
8585 /* If the suffix table in missing, create it. */
8587 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8588 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8589 egress, transfer, &error);
8591 DRV_LOG(ERR, "Failed to create meter suffix table.");
8595 /* Create the meter table with METER level. */
8596 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8597 egress, transfer, &error);
8599 DRV_LOG(ERR, "Failed to create meter policer table.");
8602 /* Create matchers, Any and Color. */
8603 dv_attr.priority = 3;
8604 dv_attr.match_criteria_enable = 0;
8605 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8608 if (!dtb->any_matcher) {
8609 DRV_LOG(ERR, "Failed to create meter"
8610 " policer default matcher.");
8613 dv_attr.priority = 0;
8614 dv_attr.match_criteria_enable =
8615 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8616 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8617 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8618 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8621 if (!dtb->color_matcher) {
8622 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8625 if (mtb->count_actns[RTE_MTR_DROPPED])
8626 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8627 actions[i++] = mtb->drop_actn;
8628 /* Default rule: lowest priority, match any, actions: drop. */
8629 dtb->policer_rules[RTE_MTR_DROPPED] =
8630 mlx5_glue->dv_create_flow(dtb->any_matcher,
8631 (void *)&value, i, actions);
8632 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8633 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8642 * Create the needed meter and suffix tables.
8643 * Lock free, (mutex should be acquired by caller).
8646 * Pointer to Ethernet device.
8648 * Pointer to the flow meter.
8651 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8653 static struct mlx5_meter_domains_infos *
8654 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8655 const struct mlx5_flow_meter *fm)
8657 struct mlx5_priv *priv = dev->data->dev_private;
8658 struct mlx5_meter_domains_infos *mtb;
8662 if (!priv->mtr_en) {
8663 rte_errno = ENOTSUP;
8666 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8668 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8671 /* Create meter count actions */
8672 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8673 if (!fm->policer_stats.cnt[i])
8675 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8677 /* Create drop action. */
8678 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8679 if (!mtb->drop_actn) {
8680 DRV_LOG(ERR, "Failed to create drop action.");
8683 /* Egress meter table. */
8684 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8686 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8689 /* Ingress meter table. */
8690 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8692 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8695 /* FDB meter table. */
8696 if (priv->config.dv_esw_en) {
8697 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8698 priv->mtr_color_reg);
8700 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8706 flow_dv_destroy_mtr_tbl(dev, mtb);
8711 * Destroy domain policer rule.
8714 * Pointer to domain table.
8717 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8721 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8722 if (dt->policer_rules[i]) {
8723 claim_zero(mlx5_glue->dv_destroy_flow
8724 (dt->policer_rules[i]));
8725 dt->policer_rules[i] = NULL;
8728 if (dt->jump_actn) {
8729 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8730 dt->jump_actn = NULL;
8735 * Destroy policer rules.
8738 * Pointer to Ethernet device.
8740 * Pointer to flow meter structure.
8742 * Pointer to flow attributes.
8748 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8749 const struct mlx5_flow_meter *fm,
8750 const struct rte_flow_attr *attr)
8752 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8757 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8759 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8761 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8766 * Create specify domain meter policer rule.
8769 * Pointer to flow meter structure.
8771 * Pointer to DV meter table set.
8773 * Pointer to suffix table.
8774 * @param[in] mtr_reg_c
8775 * Color match REG_C.
8778 * 0 on success, -1 otherwise.
8781 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8782 struct mlx5_meter_domain_info *dtb,
8783 struct mlx5_flow_tbl_resource *sfx_tb,
8786 struct mlx5_flow_dv_match_params matcher = {
8787 .size = sizeof(matcher.buf),
8789 struct mlx5_flow_dv_match_params value = {
8790 .size = sizeof(value.buf),
8792 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8793 void *actions[METER_ACTIONS];
8796 /* Create jump action. */
8799 if (!dtb->jump_actn)
8801 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8803 if (!dtb->jump_actn) {
8804 DRV_LOG(ERR, "Failed to create policer jump action.");
8807 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8810 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8811 rte_col_2_mlx5_col(i), UINT8_MAX);
8812 if (mtb->count_actns[i])
8813 actions[j++] = mtb->count_actns[i];
8814 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8815 actions[j++] = mtb->drop_actn;
8817 actions[j++] = dtb->jump_actn;
8818 dtb->policer_rules[i] =
8819 mlx5_glue->dv_create_flow(dtb->color_matcher,
8822 if (!dtb->policer_rules[i]) {
8823 DRV_LOG(ERR, "Failed to create policer rule.");
8834 * Create policer rules.
8837 * Pointer to Ethernet device.
8839 * Pointer to flow meter structure.
8841 * Pointer to flow attributes.
8844 * 0 on success, -1 otherwise.
8847 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8848 struct mlx5_flow_meter *fm,
8849 const struct rte_flow_attr *attr)
8851 struct mlx5_priv *priv = dev->data->dev_private;
8852 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8856 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8857 priv->sh->tx_mtr_sfx_tbl,
8858 priv->mtr_color_reg);
8860 DRV_LOG(ERR, "Failed to create egress policer.");
8864 if (attr->ingress) {
8865 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8866 priv->sh->rx_mtr_sfx_tbl,
8867 priv->mtr_color_reg);
8869 DRV_LOG(ERR, "Failed to create ingress policer.");
8873 if (attr->transfer) {
8874 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8875 priv->sh->fdb_mtr_sfx_tbl,
8876 priv->mtr_color_reg);
8878 DRV_LOG(ERR, "Failed to create transfer policer.");
8884 flow_dv_destroy_policer_rules(dev, fm, attr);
8889 * Query a devx counter.
8892 * Pointer to the Ethernet device structure.
8894 * Pointer to the flow counter.
8896 * Set to clear the counter statistics.
8898 * The statistics value of packets.
8900 * The statistics value of bytes.
8903 * 0 on success, otherwise return -1.
8906 flow_dv_counter_query(struct rte_eth_dev *dev,
8907 struct mlx5_flow_counter *cnt, bool clear,
8908 uint64_t *pkts, uint64_t *bytes)
8910 struct mlx5_priv *priv = dev->data->dev_private;
8911 uint64_t inn_pkts, inn_bytes;
8914 if (!priv->config.devx)
8916 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8919 *pkts = inn_pkts - cnt->hits;
8920 *bytes = inn_bytes - cnt->bytes;
8922 cnt->hits = inn_pkts;
8923 cnt->bytes = inn_bytes;
8929 * Mutex-protected thunk to lock-free __flow_dv_translate().
8932 flow_dv_translate(struct rte_eth_dev *dev,
8933 struct mlx5_flow *dev_flow,
8934 const struct rte_flow_attr *attr,
8935 const struct rte_flow_item items[],
8936 const struct rte_flow_action actions[],
8937 struct rte_flow_error *error)
8941 flow_dv_shared_lock(dev);
8942 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8943 flow_dv_shared_unlock(dev);
8948 * Mutex-protected thunk to lock-free __flow_dv_apply().
8951 flow_dv_apply(struct rte_eth_dev *dev,
8952 struct rte_flow *flow,
8953 struct rte_flow_error *error)
8957 flow_dv_shared_lock(dev);
8958 ret = __flow_dv_apply(dev, flow, error);
8959 flow_dv_shared_unlock(dev);
8964 * Mutex-protected thunk to lock-free __flow_dv_remove().
8967 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8969 flow_dv_shared_lock(dev);
8970 __flow_dv_remove(dev, flow);
8971 flow_dv_shared_unlock(dev);
8975 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8978 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8980 flow_dv_shared_lock(dev);
8981 __flow_dv_destroy(dev, flow);
8982 flow_dv_shared_unlock(dev);
8986 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8988 static struct mlx5_flow_counter *
8989 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8991 struct mlx5_flow_counter *cnt;
8993 flow_dv_shared_lock(dev);
8994 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8995 flow_dv_shared_unlock(dev);
9000 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9003 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
9005 flow_dv_shared_lock(dev);
9006 flow_dv_counter_release(dev, cnt);
9007 flow_dv_shared_unlock(dev);
9010 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9011 .validate = flow_dv_validate,
9012 .prepare = flow_dv_prepare,
9013 .translate = flow_dv_translate,
9014 .apply = flow_dv_apply,
9015 .remove = flow_dv_remove,
9016 .destroy = flow_dv_destroy,
9017 .query = flow_dv_query,
9018 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9019 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9020 .create_policer_rules = flow_dv_create_policer_rules,
9021 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9022 .counter_alloc = flow_dv_counter_allocate,
9023 .counter_free = flow_dv_counter_free,
9024 .counter_query = flow_dv_counter_query,
9027 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */