drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  * MPRQ can be enabled explicitly, or implicitly by enabling LRO.
  97  *
  98  * @param dev
  99  *   Pointer to Ethernet device.
 100  *
 101  * @return
 102  *   0 if disabled, otherwise enabled.
 103  */
 104 inline int
 105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 106 {
 107         struct mlx5_priv *priv = dev->data->dev_private;
 108         uint16_t i;
 109         uint16_t n = 0;
 110
 111         if (mlx5_check_mprq_support(dev) < 0)
 112                 return 0;
 113         /* All the configured queues should be enabled. */
 114         for (i = 0; i < priv->rxqs_n; ++i) {
 115                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 116
 117                 if (!rxq)
 118                         continue;
 119                 if (mlx5_rxq_mprq_enabled(rxq))
 120                         ++n;
 121         }
 122         /* Multi-Packet RQ can't be partially configured. */
 123         assert(n == 0 || n == priv->rxqs_n);
 124         return n == priv->rxqs_n;
 125 }
 126
 127 /**
 128  * Check whether LRO is supported and enabled for the device.
 129  *
 130  * @param dev
 131  *   Pointer to Ethernet device.
 132  *
 133  * @return
 134  *   0 if disabled, 1 if enabled.
 135  */
 136 inline int
 137 mlx5_lro_on(struct rte_eth_dev *dev)
 138 {
 139         return (MLX5_LRO_SUPPORTED(dev) && MLX5_LRO_ENABLED(dev));
 140 }
 141
 142 /**
 143  * Allocate RX queue elements for Multi-Packet RQ.
 144  *
 145  * @param rxq_ctrl
 146  *   Pointer to RX queue structure.
 147  *
 148  * @return
 149  *   0 on success, a negative errno value otherwise and rte_errno is set.
 150  */
 151 static int
 152 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 153 {
 154         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 155         unsigned int wqe_n = 1 << rxq->elts_n;
 156         unsigned int i;
 157         int err;
 158
 159         /* Iterate on segments. */
 160         for (i = 0; i <= wqe_n; ++i) {
 161                 struct mlx5_mprq_buf *buf;
 162
 163                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 164                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 165                         rte_errno = ENOMEM;
 166                         goto error;
 167                 }
 168                 if (i < wqe_n)
 169                         (*rxq->mprq_bufs)[i] = buf;
 170                 else
 171                         rxq->mprq_repl = buf;
 172         }
 173         DRV_LOG(DEBUG,
 174                 "port %u Rx queue %u allocated and configured %u segments",
 175                 rxq->port_id, rxq->idx, wqe_n);
 176         return 0;
 177 error:
 178         err = rte_errno; /* Save rte_errno before cleanup. */
 179         wqe_n = i;
 180         for (i = 0; (i != wqe_n); ++i) {
 181                 if ((*rxq->mprq_bufs)[i] != NULL)
 182                         rte_mempool_put(rxq->mprq_mp,
 183                                         (*rxq->mprq_bufs)[i]);
 184                 (*rxq->mprq_bufs)[i] = NULL;
 185         }
 186         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 187                 rxq->port_id, rxq->idx);
 188         rte_errno = err; /* Restore rte_errno. */
 189         return -rte_errno;
 190 }
 191
 192 /**
 193  * Allocate RX queue elements for Single-Packet RQ.
 194  *
 195  * @param rxq_ctrl
 196  *   Pointer to RX queue structure.
 197  *
 198  * @return
 199  *   0 on success, errno value on failure.
 200  */
 201 static int
 202 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 203 {
 204         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 205         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 206         unsigned int i;
 207         int err;
 208
 209         /* Iterate on segments. */
 210         for (i = 0; (i != elts_n); ++i) {
 211                 struct rte_mbuf *buf;
 212
 213                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 214                 if (buf == NULL) {
 215                         DRV_LOG(ERR, "port %u empty mbuf pool",
 216                                 PORT_ID(rxq_ctrl->priv));
 217                         rte_errno = ENOMEM;
 218                         goto error;
 219                 }
 220                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 221                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 222                 /* Buffer is supposed to be empty. */
 223                 assert(rte_pktmbuf_data_len(buf) == 0);
 224                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 225                 assert(!buf->next);
 226                 /* Only the first segment keeps headroom. */
 227                 if (i % sges_n)
 228                         SET_DATA_OFF(buf, 0);
 229                 PORT(buf) = rxq_ctrl->rxq.port_id;
 230                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 231                 PKT_LEN(buf) = DATA_LEN(buf);
 232                 NB_SEGS(buf) = 1;
 233                 (*rxq_ctrl->rxq.elts)[i] = buf;
 234         }
 235         /* If Rx vector is activated. */
 236         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 237                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 238                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 239                 int j;
 240
 241                 /* Initialize default rearm_data for vPMD. */
 242                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 243                 rte_mbuf_refcnt_set(mbuf_init, 1);
 244                 mbuf_init->nb_segs = 1;
 245                 mbuf_init->port = rxq->port_id;
 246                 /*
 247                  * prevent compiler reordering:
 248                  * rearm_data covers previous fields.
 249                  */
 250                 rte_compiler_barrier();
 251                 rxq->mbuf_initializer =
 252                         *(uint64_t *)&mbuf_init->rearm_data;
 253                 /* Padding with a fake mbuf for vectorized Rx. */
 254                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 255                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 256         }
 257         DRV_LOG(DEBUG,
 258                 "port %u Rx queue %u allocated and configured %u segments"
 259                 " (max %u packets)",
 260                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 261                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 262         return 0;
 263 error:
 264         err = rte_errno; /* Save rte_errno before cleanup. */
 265         elts_n = i;
 266         for (i = 0; (i != elts_n); ++i) {
 267                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 268                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 269                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 270         }
 271         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 272                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 273         rte_errno = err; /* Restore rte_errno. */
 274         return -rte_errno;
 275 }
 276
 277 /**
 278  * Allocate RX queue elements.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  *
 283  * @return
 284  *   0 on success, errno value on failure.
 285  */
 286 int
 287 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 288 {
 289         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 290                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 291 }
 292
 293 /**
 294  * Free RX queue elements for Multi-Packet RQ.
 295  *
 296  * @param rxq_ctrl
 297  *   Pointer to RX queue structure.
 298  */
 299 static void
 300 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 301 {
 302         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 303         uint16_t i;
 304
 305         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 306                 rxq->port_id, rxq->idx);
 307         if (rxq->mprq_bufs == NULL)
 308                 return;
 309         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 310         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 311                 if ((*rxq->mprq_bufs)[i] != NULL)
 312                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 313                 (*rxq->mprq_bufs)[i] = NULL;
 314         }
 315         if (rxq->mprq_repl != NULL) {
 316                 mlx5_mprq_buf_free(rxq->mprq_repl);
 317                 rxq->mprq_repl = NULL;
 318         }
 319 }
 320
 321 /**
 322  * Free RX queue elements for Single-Packet RQ.
 323  *
 324  * @param rxq_ctrl
 325  *   Pointer to RX queue structure.
 326  */
 327 static void
 328 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 329 {
 330         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 331         const uint16_t q_n = (1 << rxq->elts_n);
 332         const uint16_t q_mask = q_n - 1;
 333         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 334         uint16_t i;
 335
 336         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 337                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 338         if (rxq->elts == NULL)
 339                 return;
 340         /**
 341          * Some mbuf in the Ring belongs to the application.  They cannot be
 342          * freed.
 343          */
 344         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 345                 for (i = 0; i < used; ++i)
 346                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 347                 rxq->rq_pi = rxq->rq_ci;
 348         }
 349         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 350                 if ((*rxq->elts)[i] != NULL)
 351                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 352                 (*rxq->elts)[i] = NULL;
 353         }
 354 }
 355
 356 /**
 357  * Free RX queue elements.
 358  *
 359  * @param rxq_ctrl
 360  *   Pointer to RX queue structure.
 361  */
 362 static void
 363 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 364 {
 365         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 366                 rxq_free_elts_mprq(rxq_ctrl);
 367         else
 368                 rxq_free_elts_sprq(rxq_ctrl);
 369 }
 370
 371 /**
 372  * Returns the per-queue supported offloads.
 373  *
 374  * @param dev
 375  *   Pointer to Ethernet device.
 376  *
 377  * @return
 378  *   Supported Rx offloads.
 379  */
 380 uint64_t
 381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 382 {
 383         struct mlx5_priv *priv = dev->data->dev_private;
 384         struct mlx5_dev_config *config = &priv->config;
 385         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 386                              DEV_RX_OFFLOAD_TIMESTAMP |
 387                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 388
 389         if (config->hw_fcs_strip)
 390                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 391
 392         if (config->hw_csum)
 393                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 394                              DEV_RX_OFFLOAD_UDP_CKSUM |
 395                              DEV_RX_OFFLOAD_TCP_CKSUM);
 396         if (config->hw_vlan_strip)
 397                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 398         return offloads;
 399 }
 400
 401
 402 /**
 403  * Returns the per-port supported offloads.
 404  *
 405  * @param dev
 406  *   Pointer to Ethernet device.
 407  *
 408  * @return
 409  *   Supported Rx offloads.
 410  */
 411 uint64_t
 412 mlx5_get_rx_port_offloads(struct rte_eth_dev *dev)
 413 {
 414         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 415
 416         if (MLX5_LRO_SUPPORTED(dev))
 417                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 418         return offloads;
 419 }
 420
 421 /**
 422  * Verify if the queue can be released.
 423  *
 424  * @param dev
 425  *   Pointer to Ethernet device.
 426  * @param idx
 427  *   RX queue index.
 428  *
 429  * @return
 430  *   1 if the queue can be released
 431  *   0 if the queue can not be released, there are references to it.
 432  *   Negative errno and rte_errno is set if queue doesn't exist.
 433  */
 434 static int
 435 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 436 {
 437         struct mlx5_priv *priv = dev->data->dev_private;
 438         struct mlx5_rxq_ctrl *rxq_ctrl;
 439
 440         if (!(*priv->rxqs)[idx]) {
 441                 rte_errno = EINVAL;
 442                 return -rte_errno;
 443         }
 444         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 445         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 446 }
 447
 448 /**
 449  *
 450  * @param dev
 451  *   Pointer to Ethernet device structure.
 452  * @param idx
 453  *   RX queue index.
 454  * @param desc
 455  *   Number of descriptors to configure in queue.
 456  * @param socket
 457  *   NUMA socket on which memory must be allocated.
 458  * @param[in] conf
 459  *   Thresholds parameters.
 460  * @param mp
 461  *   Memory pool for buffer allocations.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 int
 467 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 468                     unsigned int socket, const struct rte_eth_rxconf *conf,
 469                     struct rte_mempool *mp)
 470 {
 471         struct mlx5_priv *priv = dev->data->dev_private;
 472         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 473         struct mlx5_rxq_ctrl *rxq_ctrl =
 474                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 475
 476         if (!rte_is_power_of_2(desc)) {
 477                 desc = 1 << log2above(desc);
 478                 DRV_LOG(WARNING,
 479                         "port %u increased number of descriptors in Rx queue %u"
 480                         " to the next power of two (%d)",
 481                         dev->data->port_id, idx, desc);
 482         }
 483         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 484                 dev->data->port_id, idx, desc);
 485         if (idx >= priv->rxqs_n) {
 486                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 487                         dev->data->port_id, idx, priv->rxqs_n);
 488                 rte_errno = EOVERFLOW;
 489                 return -rte_errno;
 490         }
 491         if (!mlx5_rxq_releasable(dev, idx)) {
 492                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 493                         dev->data->port_id, idx);
 494                 rte_errno = EBUSY;
 495                 return -rte_errno;
 496         }
 497         mlx5_rxq_release(dev, idx);
 498         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 499         if (!rxq_ctrl) {
 500                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 501                         dev->data->port_id, idx);
 502                 rte_errno = ENOMEM;
 503                 return -rte_errno;
 504         }
 505         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 506                 dev->data->port_id, idx);
 507         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 508         return 0;
 509 }
 510
 511 /**
 512  * DPDK callback to release a RX queue.
 513  *
 514  * @param dpdk_rxq
 515  *   Generic RX queue pointer.
 516  */
 517 void
 518 mlx5_rx_queue_release(void *dpdk_rxq)
 519 {
 520         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 521         struct mlx5_rxq_ctrl *rxq_ctrl;
 522         struct mlx5_priv *priv;
 523
 524         if (rxq == NULL)
 525                 return;
 526         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 527         priv = rxq_ctrl->priv;
 528         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 529                 rte_panic("port %u Rx queue %u is still used by a flow and"
 530                           " cannot be removed\n",
 531                           PORT_ID(priv), rxq->idx);
 532         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 533 }
 534
 535 /**
 536  * Get an Rx queue Verbs/DevX object.
 537  *
 538  * @param dev
 539  *   Pointer to Ethernet device.
 540  * @param idx
 541  *   Queue index in DPDK Rx queue array
 542  *
 543  * @return
 544  *   The Verbs/DevX object if it exists.
 545  */
 546 static struct mlx5_rxq_obj *
 547 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 548 {
 549         struct mlx5_priv *priv = dev->data->dev_private;
 550         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 551         struct mlx5_rxq_ctrl *rxq_ctrl;
 552
 553         if (idx >= priv->rxqs_n)
 554                 return NULL;
 555         if (!rxq_data)
 556                 return NULL;
 557         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 558         if (rxq_ctrl->obj)
 559                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 560         return rxq_ctrl->obj;
 561 }
 562
 563 /**
 564  * Release the resources allocated for an RQ DevX object.
 565  *
 566  * @param rxq_ctrl
 567  *   DevX Rx queue object.
 568  */
 569 static void
 570 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 571 {
 572         if (rxq_ctrl->rxq.wqes) {
 573                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 574                 rxq_ctrl->rxq.wqes = NULL;
 575         }
 576         if (rxq_ctrl->wq_umem)
 577                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 578 }
 579
 580 /**
 581  * Release an Rx verbs/DevX queue object.
 582  *
 583  * @param rxq_obj
 584  *   Verbs/DevX Rx queue object.
 585  *
 586  * @return
 587  *   1 while a reference on it exists, 0 when freed.
 588  */
 589 static int
 590 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 591 {
 592         assert(rxq_obj);
 593         if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV)
 594                 assert(rxq_obj->wq);
 595         assert(rxq_obj->cq);
 596         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 597                 rxq_free_elts(rxq_obj->rxq_ctrl);
 598                 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
 599                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 600                 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
 601                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 602                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 603                 }
 604                 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 605                 if (rxq_obj->channel)
 606                         claim_zero(mlx5_glue->destroy_comp_channel
 607                                    (rxq_obj->channel));
 608                 LIST_REMOVE(rxq_obj, next);
 609                 rte_free(rxq_obj);
 610                 return 0;
 611         }
 612         return 1;
 613 }
 614
 615 /**
 616  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 617  *
 618  * @param dev
 619  *   Pointer to Ethernet device.
 620  *
 621  * @return
 622  *   0 on success, a negative errno value otherwise and rte_errno is set.
 623  */
 624 int
 625 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 626 {
 627         struct mlx5_priv *priv = dev->data->dev_private;
 628         unsigned int i;
 629         unsigned int rxqs_n = priv->rxqs_n;
 630         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 631         unsigned int count = 0;
 632         struct rte_intr_handle *intr_handle = dev->intr_handle;
 633
 634         if (!dev->data->dev_conf.intr_conf.rxq)
 635                 return 0;
 636         mlx5_rx_intr_vec_disable(dev);
 637         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 638         if (intr_handle->intr_vec == NULL) {
 639                 DRV_LOG(ERR,
 640                         "port %u failed to allocate memory for interrupt"
 641                         " vector, Rx interrupts will not be supported",
 642                         dev->data->port_id);
 643                 rte_errno = ENOMEM;
 644                 return -rte_errno;
 645         }
 646         intr_handle->type = RTE_INTR_HANDLE_EXT;
 647         for (i = 0; i != n; ++i) {
 648                 /* This rxq obj must not be released in this function. */
 649                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 650                 int fd;
 651                 int flags;
 652                 int rc;
 653
 654                 /* Skip queues that cannot request interrupts. */
 655                 if (!rxq_obj || !rxq_obj->channel) {
 656                         /* Use invalid intr_vec[] index to disable entry. */
 657                         intr_handle->intr_vec[i] =
 658                                 RTE_INTR_VEC_RXTX_OFFSET +
 659                                 RTE_MAX_RXTX_INTR_VEC_ID;
 660                         continue;
 661                 }
 662                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 663                         DRV_LOG(ERR,
 664                                 "port %u too many Rx queues for interrupt"
 665                                 " vector size (%d), Rx interrupts cannot be"
 666                                 " enabled",
 667                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 668                         mlx5_rx_intr_vec_disable(dev);
 669                         rte_errno = ENOMEM;
 670                         return -rte_errno;
 671                 }
 672                 fd = rxq_obj->channel->fd;
 673                 flags = fcntl(fd, F_GETFL);
 674                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 675                 if (rc < 0) {
 676                         rte_errno = errno;
 677                         DRV_LOG(ERR,
 678                                 "port %u failed to make Rx interrupt file"
 679                                 " descriptor %d non-blocking for queue index"
 680                                 " %d",
 681                                 dev->data->port_id, fd, i);
 682                         mlx5_rx_intr_vec_disable(dev);
 683                         return -rte_errno;
 684                 }
 685                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 686                 intr_handle->efds[count] = fd;
 687                 count++;
 688         }
 689         if (!count)
 690                 mlx5_rx_intr_vec_disable(dev);
 691         else
 692                 intr_handle->nb_efd = count;
 693         return 0;
 694 }
 695
 696 /**
 697  * Clean up Rx interrupts handler.
 698  *
 699  * @param dev
 700  *   Pointer to Ethernet device.
 701  */
 702 void
 703 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 704 {
 705         struct mlx5_priv *priv = dev->data->dev_private;
 706         struct rte_intr_handle *intr_handle = dev->intr_handle;
 707         unsigned int i;
 708         unsigned int rxqs_n = priv->rxqs_n;
 709         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 710
 711         if (!dev->data->dev_conf.intr_conf.rxq)
 712                 return;
 713         if (!intr_handle->intr_vec)
 714                 goto free;
 715         for (i = 0; i != n; ++i) {
 716                 struct mlx5_rxq_ctrl *rxq_ctrl;
 717                 struct mlx5_rxq_data *rxq_data;
 718
 719                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 720                     RTE_MAX_RXTX_INTR_VEC_ID)
 721                         continue;
 722                 /**
 723                  * Need to access directly the queue to release the reference
 724                  * kept in mlx5_rx_intr_vec_enable().
 725                  */
 726                 rxq_data = (*priv->rxqs)[i];
 727                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 728                 if (rxq_ctrl->obj)
 729                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 730         }
 731 free:
 732         rte_intr_free_epoll_fd(intr_handle);
 733         if (intr_handle->intr_vec)
 734                 free(intr_handle->intr_vec);
 735         intr_handle->nb_efd = 0;
 736         intr_handle->intr_vec = NULL;
 737 }
 738
 739 /**
 740  *  MLX5 CQ notification .
 741  *
 742  *  @param rxq
 743  *     Pointer to receive queue structure.
 744  *  @param sq_n_rxq
 745  *     Sequence number per receive queue .
 746  */
 747 static inline void
 748 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 749 {
 750         int sq_n = 0;
 751         uint32_t doorbell_hi;
 752         uint64_t doorbell;
 753         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 754
 755         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 756         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 757         doorbell = (uint64_t)doorbell_hi << 32;
 758         doorbell |=  rxq->cqn;
 759         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 760         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 761                          cq_db_reg, rxq->uar_lock_cq);
 762 }
 763
 764 /**
 765  * DPDK callback for Rx queue interrupt enable.
 766  *
 767  * @param dev
 768  *   Pointer to Ethernet device structure.
 769  * @param rx_queue_id
 770  *   Rx queue number.
 771  *
 772  * @return
 773  *   0 on success, a negative errno value otherwise and rte_errno is set.
 774  */
 775 int
 776 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 777 {
 778         struct mlx5_priv *priv = dev->data->dev_private;
 779         struct mlx5_rxq_data *rxq_data;
 780         struct mlx5_rxq_ctrl *rxq_ctrl;
 781
 782         rxq_data = (*priv->rxqs)[rx_queue_id];
 783         if (!rxq_data) {
 784                 rte_errno = EINVAL;
 785                 return -rte_errno;
 786         }
 787         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 788         if (rxq_ctrl->irq) {
 789                 struct mlx5_rxq_obj *rxq_obj;
 790
 791                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 792                 if (!rxq_obj) {
 793                         rte_errno = EINVAL;
 794                         return -rte_errno;
 795                 }
 796                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 797                 mlx5_rxq_obj_release(rxq_obj);
 798         }
 799         return 0;
 800 }
 801
 802 /**
 803  * DPDK callback for Rx queue interrupt disable.
 804  *
 805  * @param dev
 806  *   Pointer to Ethernet device structure.
 807  * @param rx_queue_id
 808  *   Rx queue number.
 809  *
 810  * @return
 811  *   0 on success, a negative errno value otherwise and rte_errno is set.
 812  */
 813 int
 814 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 815 {
 816         struct mlx5_priv *priv = dev->data->dev_private;
 817         struct mlx5_rxq_data *rxq_data;
 818         struct mlx5_rxq_ctrl *rxq_ctrl;
 819         struct mlx5_rxq_obj *rxq_obj = NULL;
 820         struct ibv_cq *ev_cq;
 821         void *ev_ctx;
 822         int ret;
 823
 824         rxq_data = (*priv->rxqs)[rx_queue_id];
 825         if (!rxq_data) {
 826                 rte_errno = EINVAL;
 827                 return -rte_errno;
 828         }
 829         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 830         if (!rxq_ctrl->irq)
 831                 return 0;
 832         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 833         if (!rxq_obj) {
 834                 rte_errno = EINVAL;
 835                 return -rte_errno;
 836         }
 837         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 838         if (ret || ev_cq != rxq_obj->cq) {
 839                 rte_errno = EINVAL;
 840                 goto exit;
 841         }
 842         rxq_data->cq_arm_sn++;
 843         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 844         mlx5_rxq_obj_release(rxq_obj);
 845         return 0;
 846 exit:
 847         ret = rte_errno; /* Save rte_errno before cleanup. */
 848         if (rxq_obj)
 849                 mlx5_rxq_obj_release(rxq_obj);
 850         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 851                 dev->data->port_id, rx_queue_id);
 852         rte_errno = ret; /* Restore rte_errno. */
 853         return -rte_errno;
 854 }
 855
 856 /**
 857  * Create a CQ Verbs object.
 858  *
 859  * @param dev
 860  *   Pointer to Ethernet device.
 861  * @param priv
 862  *   Pointer to device private data.
 863  * @param rxq_data
 864  *   Pointer to Rx queue data.
 865  * @param cqe_n
 866  *   Number of CQEs in CQ.
 867  * @param rxq_obj
 868  *   Pointer to Rx queue object data.
 869  *
 870  * @return
 871  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 872  */
 873 static struct ibv_cq *
 874 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 875                 struct mlx5_rxq_data *rxq_data,
 876                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 877 {
 878         struct {
 879                 struct ibv_cq_init_attr_ex ibv;
 880                 struct mlx5dv_cq_init_attr mlx5;
 881         } cq_attr;
 882
 883         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 884                 .cqe = cqe_n,
 885                 .channel = rxq_obj->channel,
 886                 .comp_mask = 0,
 887         };
 888         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 889                 .comp_mask = 0,
 890         };
 891         if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
 892                 cq_attr.mlx5.comp_mask |=
 893                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 894 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 895                 cq_attr.mlx5.cqe_comp_res_format =
 896                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 897                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 898                                 MLX5DV_CQE_RES_FORMAT_HASH;
 899 #else
 900                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 901 #endif
 902                 /*
 903                  * For vectorized Rx, it must not be doubled in order to
 904                  * make cq_ci and rq_ci aligned.
 905                  */
 906                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 907                         cq_attr.ibv.cqe *= 2;
 908         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
 909                 DRV_LOG(DEBUG,
 910                         "port %u Rx CQE compression is disabled for HW"
 911                         " timestamp",
 912                         dev->data->port_id);
 913         }
 914 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 915         if (priv->config.cqe_pad) {
 916                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 917                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 918         }
 919 #endif
 920         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
 921                                                               &cq_attr.ibv,
 922                                                               &cq_attr.mlx5));
 923 }
 924
 925 /**
 926  * Create a WQ Verbs object.
 927  *
 928  * @param dev
 929  *   Pointer to Ethernet device.
 930  * @param priv
 931  *   Pointer to device private data.
 932  * @param rxq_data
 933  *   Pointer to Rx queue data.
 934  * @param idx
 935  *   Queue index in DPDK Rx queue array
 936  * @param wqe_n
 937  *   Number of WQEs in WQ.
 938  * @param rxq_obj
 939  *   Pointer to Rx queue object data.
 940  *
 941  * @return
 942  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 943  */
 944 static struct ibv_wq *
 945 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 946                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
 947                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
 948 {
 949         struct {
 950                 struct ibv_wq_init_attr ibv;
 951 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 952                 struct mlx5dv_wq_init_attr mlx5;
 953 #endif
 954         } wq_attr;
 955
 956         wq_attr.ibv = (struct ibv_wq_init_attr){
 957                 .wq_context = NULL, /* Could be useful in the future. */
 958                 .wq_type = IBV_WQT_RQ,
 959                 /* Max number of outstanding WRs. */
 960                 .max_wr = wqe_n >> rxq_data->sges_n,
 961                 /* Max number of scatter/gather elements in a WR. */
 962                 .max_sge = 1 << rxq_data->sges_n,
 963                 .pd = priv->sh->pd,
 964                 .cq = rxq_obj->cq,
 965                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
 966                 .create_flags = (rxq_data->vlan_strip ?
 967                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
 968         };
 969         /* By default, FCS (CRC) is stripped by hardware. */
 970         if (rxq_data->crc_present) {
 971                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 972                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 973         }
 974         if (priv->config.hw_padding) {
 975 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 976                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 977                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 978 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 979                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 980                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 981 #endif
 982         }
 983 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 984         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
 985                 .comp_mask = 0,
 986         };
 987         if (mlx5_rxq_mprq_enabled(rxq_data)) {
 988                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 989                                                 &wq_attr.mlx5.striding_rq_attrs;
 990
 991                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 992                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 993                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 994                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 995                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 996                 };
 997         }
 998         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
 999                                               &wq_attr.mlx5);
1000 #else
1001         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1002 #endif
1003         if (rxq_obj->wq) {
1004                 /*
1005                  * Make sure number of WRs*SGEs match expectations since a queue
1006                  * cannot allocate more than "desc" buffers.
1007                  */
1008                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1009                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1010                         DRV_LOG(ERR,
1011                                 "port %u Rx queue %u requested %u*%u but got"
1012                                 " %u*%u WRs*SGEs",
1013                                 dev->data->port_id, idx,
1014                                 wqe_n >> rxq_data->sges_n,
1015                                 (1 << rxq_data->sges_n),
1016                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1017                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1018                         rxq_obj->wq = NULL;
1019                         rte_errno = EINVAL;
1020                 }
1021         }
1022         return rxq_obj->wq;
1023 }
1024
1025 /**
1026  * Fill common fields of create RQ attributes structure.
1027  *
1028  * @param rxq_data
1029  *   Pointer to Rx queue data.
1030  * @param cqn
1031  *   CQ number to use with this RQ.
1032  * @param rq_attr
1033  *   RQ attributes structure to fill..
1034  */
1035 static void
1036 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1037                               struct mlx5_devx_create_rq_attr *rq_attr)
1038 {
1039         rq_attr->state = MLX5_RQC_STATE_RST;
1040         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1041         rq_attr->cqn = cqn;
1042         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1043 }
1044
1045 /**
1046  * Fill common fields of DevX WQ attributes structure.
1047  *
1048  * @param priv
1049  *   Pointer to device private data.
1050  * @param rxq_ctrl
1051  *   Pointer to Rx queue control structure.
1052  * @param wq_attr
1053  *   WQ attributes structure to fill..
1054  */
1055 static void
1056 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1057                        struct mlx5_devx_wq_attr *wq_attr)
1058 {
1059         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1060                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1061                                         MLX5_WQ_END_PAD_MODE_NONE;
1062         wq_attr->pd = priv->sh->pdn;
1063         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1064         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1065         wq_attr->dbr_umem_valid = 1;
1066         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1067         wq_attr->wq_umem_valid = 1;
1068 }
1069
1070 /**
1071  * Create a RQ object using DevX.
1072  *
1073  * @param dev
1074  *   Pointer to Ethernet device.
1075  * @param idx
1076  *   Queue index in DPDK Rx queue array
1077  * @param cqn
1078  *   CQ number to use with this RQ.
1079  *
1080  * @return
1081  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1082  */
1083 static struct mlx5_devx_obj *
1084 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1085 {
1086         struct mlx5_priv *priv = dev->data->dev_private;
1087         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1088         struct mlx5_rxq_ctrl *rxq_ctrl =
1089                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1090         struct mlx5_devx_create_rq_attr rq_attr;
1091         uint32_t wqe_n = 1 << rxq_data->elts_n;
1092         uint32_t wq_size = 0;
1093         uint32_t wqe_size = 0;
1094         uint32_t log_wqe_size = 0;
1095         void *buf = NULL;
1096         struct mlx5_devx_obj *rq;
1097
1098         memset(&rq_attr, 0, sizeof(rq_attr));
1099         /* Fill RQ attributes. */
1100         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1101         rq_attr.flush_in_error_en = 1;
1102         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1103         /* Fill WQ attributes for this RQ. */
1104         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1105                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1106                 /*
1107                  * Number of strides in each WQE:
1108                  * 512*2^single_wqe_log_num_of_strides.
1109                  */
1110                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1111                                 rxq_data->strd_num_n -
1112                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1113                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1114                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1115                                 rxq_data->strd_sz_n -
1116                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1117                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1118         } else {
1119                 int max_sge = 0;
1120                 int num_scatter = 0;
1121
1122                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1123                 max_sge = 1 << rxq_data->sges_n;
1124                 num_scatter = RTE_MAX(max_sge, 1);
1125                 wqe_size = sizeof(struct mlx5_wqe_data_seg) * num_scatter;
1126         }
1127         log_wqe_size = log2above(wqe_size);
1128         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1129         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n;
1130         /* Calculate and allocate WQ memory space. */
1131         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1132         wq_size = wqe_n * wqe_size;
1133         buf = rte_calloc_socket(__func__, 1, wq_size, RTE_CACHE_LINE_SIZE,
1134                                 rxq_ctrl->socket);
1135         if (!buf)
1136                 return NULL;
1137         rxq_data->wqes = buf;
1138         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1139                                                      buf, wq_size, 0);
1140         if (!rxq_ctrl->wq_umem) {
1141                 rte_free(buf);
1142                 return NULL;
1143         }
1144         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1145         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1146         if (!rq)
1147                 rxq_release_rq_resources(rxq_ctrl);
1148         return rq;
1149 }
1150
1151 /**
1152  * Create the Rx queue Verbs/DevX object.
1153  *
1154  * @param dev
1155  *   Pointer to Ethernet device.
1156  * @param idx
1157  *   Queue index in DPDK Rx queue array
1158  * @param type
1159  *   Type of Rx queue object to create.
1160  *
1161  * @return
1162  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1163  */
1164 struct mlx5_rxq_obj *
1165 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1166                  enum mlx5_rxq_obj_type type)
1167 {
1168         struct mlx5_priv *priv = dev->data->dev_private;
1169         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1170         struct mlx5_rxq_ctrl *rxq_ctrl =
1171                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1172         struct ibv_wq_attr mod;
1173         unsigned int cqe_n;
1174         unsigned int wqe_n = 1 << rxq_data->elts_n;
1175         struct mlx5_rxq_obj *tmpl = NULL;
1176         struct mlx5dv_cq cq_info;
1177         struct mlx5dv_rwq rwq;
1178         int ret = 0;
1179         struct mlx5dv_obj obj;
1180
1181         assert(rxq_data);
1182         assert(!rxq_ctrl->obj);
1183         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1184         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1185         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1186                                  rxq_ctrl->socket);
1187         if (!tmpl) {
1188                 DRV_LOG(ERR,
1189                         "port %u Rx queue %u cannot allocate verbs resources",
1190                         dev->data->port_id, rxq_data->idx);
1191                 rte_errno = ENOMEM;
1192                 goto error;
1193         }
1194         tmpl->type = type;
1195         tmpl->rxq_ctrl = rxq_ctrl;
1196         if (rxq_ctrl->irq) {
1197                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1198                 if (!tmpl->channel) {
1199                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1200                                 dev->data->port_id);
1201                         rte_errno = ENOMEM;
1202                         goto error;
1203                 }
1204         }
1205         if (mlx5_rxq_mprq_enabled(rxq_data))
1206                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1207         else
1208                 cqe_n = wqe_n  - 1;
1209         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1210         if (!tmpl->cq) {
1211                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1212                         dev->data->port_id, idx);
1213                 rte_errno = ENOMEM;
1214                 goto error;
1215         }
1216         obj.cq.in = tmpl->cq;
1217         obj.cq.out = &cq_info;
1218         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1219         if (ret) {
1220                 rte_errno = ret;
1221                 goto error;
1222         }
1223         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1224                 DRV_LOG(ERR,
1225                         "port %u wrong MLX5_CQE_SIZE environment variable"
1226                         " value: it should be set to %u",
1227                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1228                 rte_errno = EINVAL;
1229                 goto error;
1230         }
1231         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1232                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1233         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1234                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1235         /* Allocate door-bell for types created with DevX. */
1236         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1237                 struct mlx5_devx_dbr_page *dbr_page;
1238                 int64_t dbr_offset;
1239
1240                 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1241                 if (dbr_offset < 0)
1242                         goto error;
1243                 rxq_ctrl->dbr_offset = dbr_offset;
1244                 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1245                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1246                                                (uintptr_t)rxq_ctrl->dbr_offset);
1247         }
1248         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1249                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1250                                            tmpl);
1251                 if (!tmpl->wq) {
1252                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1253                                 dev->data->port_id, idx);
1254                         rte_errno = ENOMEM;
1255                         goto error;
1256                 }
1257                 /* Change queue state to ready. */
1258                 mod = (struct ibv_wq_attr){
1259                         .attr_mask = IBV_WQ_ATTR_STATE,
1260                         .wq_state = IBV_WQS_RDY,
1261                 };
1262                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1263                 if (ret) {
1264                         DRV_LOG(ERR,
1265                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1266                                 " failed", dev->data->port_id, idx);
1267                         rte_errno = ret;
1268                         goto error;
1269                 }
1270                 obj.rwq.in = tmpl->wq;
1271                 obj.rwq.out = &rwq;
1272                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1273                 if (ret) {
1274                         rte_errno = ret;
1275                         goto error;
1276                 }
1277                 rxq_data->wqes = rwq.buf;
1278                 rxq_data->rq_db = rwq.dbrec;
1279         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1280                 struct mlx5_devx_modify_rq_attr rq_attr;
1281
1282                 memset(&rq_attr, 0, sizeof(rq_attr));
1283                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1284                 if (!tmpl->rq) {
1285                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1286                                 dev->data->port_id, idx);
1287                         rte_errno = ENOMEM;
1288                         goto error;
1289                 }
1290                 /* Change queue state to ready. */
1291                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1292                 rq_attr.state = MLX5_RQC_STATE_RDY;
1293                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1294                 if (ret)
1295                         goto error;
1296         }
1297         /* Fill the rings. */
1298         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1299         rxq_data->cq_db = cq_info.dbrec;
1300         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1301         rxq_data->cq_uar = cq_info.cq_uar;
1302         rxq_data->cqn = cq_info.cqn;
1303         rxq_data->cq_arm_sn = 0;
1304         mlx5_rxq_initialize(rxq_data);
1305         rxq_data->cq_ci = 0;
1306         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1307                 idx, (void *)&tmpl);
1308         rte_atomic32_inc(&tmpl->refcnt);
1309         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1310         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1311         return tmpl;
1312 error:
1313         if (tmpl) {
1314                 ret = rte_errno; /* Save rte_errno before cleanup. */
1315                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1316                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1317                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1318                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1319                 if (tmpl->cq)
1320                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1321                 if (tmpl->channel)
1322                         claim_zero(mlx5_glue->destroy_comp_channel
1323                                                         (tmpl->channel));
1324                 rte_free(tmpl);
1325                 rte_errno = ret; /* Restore rte_errno. */
1326         }
1327         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1328                 rxq_release_rq_resources(rxq_ctrl);
1329         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1330         return NULL;
1331 }
1332
1333 /**
1334  * Verify the Rx queue objects list is empty
1335  *
1336  * @param dev
1337  *   Pointer to Ethernet device.
1338  *
1339  * @return
1340  *   The number of objects not released.
1341  */
1342 int
1343 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1344 {
1345         struct mlx5_priv *priv = dev->data->dev_private;
1346         int ret = 0;
1347         struct mlx5_rxq_obj *rxq_obj;
1348
1349         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1350                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1351                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1352                 ++ret;
1353         }
1354         return ret;
1355 }
1356
1357 /**
1358  * Callback function to initialize mbufs for Multi-Packet RQ.
1359  */
1360 static inline void
1361 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1362                     void *_m, unsigned int i __rte_unused)
1363 {
1364         struct mlx5_mprq_buf *buf = _m;
1365
1366         memset(_m, 0, sizeof(*buf));
1367         buf->mp = mp;
1368         rte_atomic16_set(&buf->refcnt, 1);
1369 }
1370
1371 /**
1372  * Free mempool of Multi-Packet RQ.
1373  *
1374  * @param dev
1375  *   Pointer to Ethernet device.
1376  *
1377  * @return
1378  *   0 on success, negative errno value on failure.
1379  */
1380 int
1381 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1382 {
1383         struct mlx5_priv *priv = dev->data->dev_private;
1384         struct rte_mempool *mp = priv->mprq_mp;
1385         unsigned int i;
1386
1387         if (mp == NULL)
1388                 return 0;
1389         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1390                 dev->data->port_id, mp->name);
1391         /*
1392          * If a buffer in the pool has been externally attached to a mbuf and it
1393          * is still in use by application, destroying the Rx queue can spoil
1394          * the packet. It is unlikely to happen but if application dynamically
1395          * creates and destroys with holding Rx packets, this can happen.
1396          *
1397          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1398          * RQ isn't provided by application but managed by PMD.
1399          */
1400         if (!rte_mempool_full(mp)) {
1401                 DRV_LOG(ERR,
1402                         "port %u mempool for Multi-Packet RQ is still in use",
1403                         dev->data->port_id);
1404                 rte_errno = EBUSY;
1405                 return -rte_errno;
1406         }
1407         rte_mempool_free(mp);
1408         /* Unset mempool for each Rx queue. */
1409         for (i = 0; i != priv->rxqs_n; ++i) {
1410                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1411
1412                 if (rxq == NULL)
1413                         continue;
1414                 rxq->mprq_mp = NULL;
1415         }
1416         priv->mprq_mp = NULL;
1417         return 0;
1418 }
1419
1420 /**
1421  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1422  * mempool. If already allocated, reuse it if there're enough elements.
1423  * Otherwise, resize it.
1424  *
1425  * @param dev
1426  *   Pointer to Ethernet device.
1427  *
1428  * @return
1429  *   0 on success, negative errno value on failure.
1430  */
1431 int
1432 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1433 {
1434         struct mlx5_priv *priv = dev->data->dev_private;
1435         struct rte_mempool *mp = priv->mprq_mp;
1436         char name[RTE_MEMPOOL_NAMESIZE];
1437         unsigned int desc = 0;
1438         unsigned int buf_len;
1439         unsigned int obj_num;
1440         unsigned int obj_size;
1441         unsigned int strd_num_n = 0;
1442         unsigned int strd_sz_n = 0;
1443         unsigned int i;
1444
1445         if (!mlx5_mprq_enabled(dev))
1446                 return 0;
1447         /* Count the total number of descriptors configured. */
1448         for (i = 0; i != priv->rxqs_n; ++i) {
1449                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1450
1451                 if (rxq == NULL)
1452                         continue;
1453                 desc += 1 << rxq->elts_n;
1454                 /* Get the max number of strides. */
1455                 if (strd_num_n < rxq->strd_num_n)
1456                         strd_num_n = rxq->strd_num_n;
1457                 /* Get the max size of a stride. */
1458                 if (strd_sz_n < rxq->strd_sz_n)
1459                         strd_sz_n = rxq->strd_sz_n;
1460         }
1461         assert(strd_num_n && strd_sz_n);
1462         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1463         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1464         /*
1465          * Received packets can be either memcpy'd or externally referenced. In
1466          * case that the packet is attached to an mbuf as an external buffer, as
1467          * it isn't possible to predict how the buffers will be queued by
1468          * application, there's no option to exactly pre-allocate needed buffers
1469          * in advance but to speculatively prepares enough buffers.
1470          *
1471          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1472          * received packets to buffers provided by application (rxq->mp) until
1473          * this Mempool gets available again.
1474          */
1475         desc *= 4;
1476         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1477         /*
1478          * rte_mempool_create_empty() has sanity check to refuse large cache
1479          * size compared to the number of elements.
1480          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1481          * constant number 2 instead.
1482          */
1483         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1484         /* Check a mempool is already allocated and if it can be resued. */
1485         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1486                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1487                         dev->data->port_id, mp->name);
1488                 /* Reuse. */
1489                 goto exit;
1490         } else if (mp != NULL) {
1491                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1492                         dev->data->port_id, mp->name);
1493                 /*
1494                  * If failed to free, which means it may be still in use, no way
1495                  * but to keep using the existing one. On buffer underrun,
1496                  * packets will be memcpy'd instead of external buffer
1497                  * attachment.
1498                  */
1499                 if (mlx5_mprq_free_mp(dev)) {
1500                         if (mp->elt_size >= obj_size)
1501                                 goto exit;
1502                         else
1503                                 return -rte_errno;
1504                 }
1505         }
1506         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1507         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1508                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1509                                 dev->device->numa_node, 0);
1510         if (mp == NULL) {
1511                 DRV_LOG(ERR,
1512                         "port %u failed to allocate a mempool for"
1513                         " Multi-Packet RQ, count=%u, size=%u",
1514                         dev->data->port_id, obj_num, obj_size);
1515                 rte_errno = ENOMEM;
1516                 return -rte_errno;
1517         }
1518         priv->mprq_mp = mp;
1519 exit:
1520         /* Set mempool for each Rx queue. */
1521         for (i = 0; i != priv->rxqs_n; ++i) {
1522                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1523
1524                 if (rxq == NULL)
1525                         continue;
1526                 rxq->mprq_mp = mp;
1527         }
1528         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1529                 dev->data->port_id);
1530         return 0;
1531 }
1532
1533 /**
1534  * Create a DPDK Rx queue.
1535  *
1536  * @param dev
1537  *   Pointer to Ethernet device.
1538  * @param idx
1539  *   RX queue index.
1540  * @param desc
1541  *   Number of descriptors to configure in queue.
1542  * @param socket
1543  *   NUMA socket on which memory must be allocated.
1544  *
1545  * @return
1546  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1547  */
1548 struct mlx5_rxq_ctrl *
1549 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1550              unsigned int socket, const struct rte_eth_rxconf *conf,
1551              struct rte_mempool *mp)
1552 {
1553         struct mlx5_priv *priv = dev->data->dev_private;
1554         struct mlx5_rxq_ctrl *tmpl;
1555         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1556         unsigned int mprq_stride_size;
1557         struct mlx5_dev_config *config = &priv->config;
1558         /*
1559          * Always allocate extra slots, even if eventually
1560          * the vector Rx will not be used.
1561          */
1562         uint16_t desc_n =
1563                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1564         uint64_t offloads = conf->offloads |
1565                            dev->data->dev_conf.rxmode.offloads;
1566         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1567
1568         tmpl = rte_calloc_socket("RXQ", 1,
1569                                  sizeof(*tmpl) +
1570                                  desc_n * sizeof(struct rte_mbuf *),
1571                                  0, socket);
1572         if (!tmpl) {
1573                 rte_errno = ENOMEM;
1574                 return NULL;
1575         }
1576         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1577                                MLX5_MR_BTREE_CACHE_N, socket)) {
1578                 /* rte_errno is already set. */
1579                 goto error;
1580         }
1581         tmpl->socket = socket;
1582         if (dev->data->dev_conf.intr_conf.rxq)
1583                 tmpl->irq = 1;
1584         /*
1585          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1586          * following conditions are met:
1587          *  - MPRQ is enabled.
1588          *  - The number of descs is more than the number of strides.
1589          *  - max_rx_pkt_len plus overhead is less than the max size of a
1590          *    stride.
1591          *  Otherwise, enable Rx scatter if necessary.
1592          */
1593         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1594         mprq_stride_size =
1595                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1596                 sizeof(struct rte_mbuf_ext_shared_info) +
1597                 RTE_PKTMBUF_HEADROOM;
1598         if (mprq_en &&
1599             desc > (1U << config->mprq.stride_num_n) &&
1600             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1601                 /* TODO: Rx scatter isn't supported yet. */
1602                 tmpl->rxq.sges_n = 0;
1603                 /* Trim the number of descs needed. */
1604                 desc >>= config->mprq.stride_num_n;
1605                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1606                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1607                                               config->mprq.min_stride_size_n);
1608                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1609                 tmpl->rxq.mprq_max_memcpy_len =
1610                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1611                                 config->mprq.max_memcpy_len);
1612                 DRV_LOG(DEBUG,
1613                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1614                         " strd_num_n = %u, strd_sz_n = %u",
1615                         dev->data->port_id, idx,
1616                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1617         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1618                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1619                 tmpl->rxq.sges_n = 0;
1620         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1621                 unsigned int size =
1622                         RTE_PKTMBUF_HEADROOM +
1623                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1624                 unsigned int sges_n;
1625
1626                 /*
1627                  * Determine the number of SGEs needed for a full packet
1628                  * and round it to the next power of two.
1629                  */
1630                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1631                 tmpl->rxq.sges_n = sges_n;
1632                 /* Make sure rxq.sges_n did not overflow. */
1633                 size = mb_len * (1 << tmpl->rxq.sges_n);
1634                 size -= RTE_PKTMBUF_HEADROOM;
1635                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1636                         DRV_LOG(ERR,
1637                                 "port %u too many SGEs (%u) needed to handle"
1638                                 " requested maximum packet size %u",
1639                                 dev->data->port_id,
1640                                 1 << sges_n,
1641                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1642                         rte_errno = EOVERFLOW;
1643                         goto error;
1644                 }
1645         } else {
1646                 DRV_LOG(WARNING,
1647                         "port %u the requested maximum Rx packet size (%u) is"
1648                         " larger than a single mbuf (%u) and scattered mode has"
1649                         " not been requested",
1650                         dev->data->port_id,
1651                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1652                         mb_len - RTE_PKTMBUF_HEADROOM);
1653         }
1654         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1655                 DRV_LOG(WARNING,
1656                         "port %u MPRQ is requested but cannot be enabled"
1657                         " (requested: desc = %u, stride_sz = %u,"
1658                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1659                         dev->data->port_id, desc, mprq_stride_size,
1660                         (1 << config->mprq.stride_num_n),
1661                         (1 << config->mprq.max_stride_size_n));
1662         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1663                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1664         if (desc % (1 << tmpl->rxq.sges_n)) {
1665                 DRV_LOG(ERR,
1666                         "port %u number of Rx queue descriptors (%u) is not a"
1667                         " multiple of SGEs per packet (%u)",
1668                         dev->data->port_id,
1669                         desc,
1670                         1 << tmpl->rxq.sges_n);
1671                 rte_errno = EINVAL;
1672                 goto error;
1673         }
1674         /* Toggle RX checksum offload if hardware supports it. */
1675         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1676         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1677         /* Configure VLAN stripping. */
1678         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1679         /* By default, FCS (CRC) is stripped by hardware. */
1680         tmpl->rxq.crc_present = 0;
1681         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1682                 if (config->hw_fcs_strip) {
1683                         /*
1684                          * RQs used for LRO-enabled TIRs should not be
1685                          * configured to scatter the FCS.
1686                          */
1687                         if (mlx5_lro_on(dev))
1688                                 DRV_LOG(WARNING,
1689                                         "port %u CRC stripping has been "
1690                                         "disabled but will still be performed "
1691                                         "by hardware, because LRO is enabled",
1692                                         dev->data->port_id);
1693                         else
1694                                 tmpl->rxq.crc_present = 1;
1695                 } else {
1696                         DRV_LOG(WARNING,
1697                                 "port %u CRC stripping has been disabled but will"
1698                                 " still be performed by hardware, make sure MLNX_OFED"
1699                                 " and firmware are up to date",
1700                                 dev->data->port_id);
1701                 }
1702         }
1703         DRV_LOG(DEBUG,
1704                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1705                 " incoming frames to hide it",
1706                 dev->data->port_id,
1707                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1708                 tmpl->rxq.crc_present << 2);
1709         /* Save port ID. */
1710         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1711                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1712         tmpl->rxq.port_id = dev->data->port_id;
1713         tmpl->priv = priv;
1714         tmpl->rxq.mp = mp;
1715         tmpl->rxq.elts_n = log2above(desc);
1716         tmpl->rxq.rq_repl_thresh =
1717                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1718         tmpl->rxq.elts =
1719                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1720 #ifndef RTE_ARCH_64
1721         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1722 #endif
1723         tmpl->rxq.idx = idx;
1724         rte_atomic32_inc(&tmpl->refcnt);
1725         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1726         return tmpl;
1727 error:
1728         rte_free(tmpl);
1729         return NULL;
1730 }
1731
1732 /**
1733  * Get a Rx queue.
1734  *
1735  * @param dev
1736  *   Pointer to Ethernet device.
1737  * @param idx
1738  *   RX queue index.
1739  *
1740  * @return
1741  *   A pointer to the queue if it exists, NULL otherwise.
1742  */
1743 struct mlx5_rxq_ctrl *
1744 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1745 {
1746         struct mlx5_priv *priv = dev->data->dev_private;
1747         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1748
1749         if ((*priv->rxqs)[idx]) {
1750                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1751                                         struct mlx5_rxq_ctrl,
1752                                         rxq);
1753                 mlx5_rxq_obj_get(dev, idx);
1754                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1755         }
1756         return rxq_ctrl;
1757 }
1758
1759 /**
1760  * Release a Rx queue.
1761  *
1762  * @param dev
1763  *   Pointer to Ethernet device.
1764  * @param idx
1765  *   RX queue index.
1766  *
1767  * @return
1768  *   1 while a reference on it exists, 0 when freed.
1769  */
1770 int
1771 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1772 {
1773         struct mlx5_priv *priv = dev->data->dev_private;
1774         struct mlx5_rxq_ctrl *rxq_ctrl;
1775
1776         if (!(*priv->rxqs)[idx])
1777                 return 0;
1778         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1779         assert(rxq_ctrl->priv);
1780         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
1781                 rxq_ctrl->obj = NULL;
1782         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1783                 claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
1784                                             rxq_ctrl->dbr_offset));
1785                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1786                 LIST_REMOVE(rxq_ctrl, next);
1787                 rte_free(rxq_ctrl);
1788                 (*priv->rxqs)[idx] = NULL;
1789                 return 0;
1790         }
1791         return 1;
1792 }
1793
1794 /**
1795  * Verify the Rx Queue list is empty
1796  *
1797  * @param dev
1798  *   Pointer to Ethernet device.
1799  *
1800  * @return
1801  *   The number of object not released.
1802  */
1803 int
1804 mlx5_rxq_verify(struct rte_eth_dev *dev)
1805 {
1806         struct mlx5_priv *priv = dev->data->dev_private;
1807         struct mlx5_rxq_ctrl *rxq_ctrl;
1808         int ret = 0;
1809
1810         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1811                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1812                         dev->data->port_id, rxq_ctrl->rxq.idx);
1813                 ++ret;
1814         }
1815         return ret;
1816 }
1817
1818 /**
1819  * Create an indirection table.
1820  *
1821  * @param dev
1822  *   Pointer to Ethernet device.
1823  * @param queues
1824  *   Queues entering in the indirection table.
1825  * @param queues_n
1826  *   Number of queues in the array.
1827  *
1828  * @return
1829  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1830  */
1831 static struct mlx5_ind_table_obj *
1832 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1833                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
1834 {
1835         struct mlx5_priv *priv = dev->data->dev_private;
1836         struct mlx5_ind_table_obj *ind_tbl;
1837         unsigned int i = 0, j = 0, k = 0;
1838
1839         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1840                              queues_n * sizeof(uint16_t), 0);
1841         if (!ind_tbl) {
1842                 rte_errno = ENOMEM;
1843                 return NULL;
1844         }
1845         ind_tbl->type = type;
1846         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1847                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1848                         log2above(queues_n) :
1849                         log2above(priv->config.ind_table_max_size);
1850                 struct ibv_wq *wq[1 << wq_n];
1851
1852                 for (i = 0; i != queues_n; ++i) {
1853                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1854                                                                  queues[i]);
1855                         if (!rxq)
1856                                 goto error;
1857                         wq[i] = rxq->obj->wq;
1858                         ind_tbl->queues[i] = queues[i];
1859                 }
1860                 ind_tbl->queues_n = queues_n;
1861                 /* Finalise indirection table. */
1862                 k = i; /* Retain value of i for use in error case. */
1863                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1864                         wq[k] = wq[j];
1865                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1866                         (priv->sh->ctx,
1867                          &(struct ibv_rwq_ind_table_init_attr){
1868                                 .log_ind_tbl_size = wq_n,
1869                                 .ind_tbl = wq,
1870                                 .comp_mask = 0,
1871                         });
1872                 if (!ind_tbl->ind_table) {
1873                         rte_errno = errno;
1874                         goto error;
1875                 }
1876         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1877                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1878
1879                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
1880                                       queues_n * sizeof(uint16_t), 0);
1881                 if (!rqt_attr) {
1882                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1883                                 dev->data->port_id);
1884                         rte_errno = ENOMEM;
1885                         goto error;
1886                 }
1887                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1888                 rqt_attr->rqt_actual_size = queues_n;
1889                 for (i = 0; i != queues_n; ++i) {
1890                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1891                                                                  queues[i]);
1892                         if (!rxq)
1893                                 goto error;
1894                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
1895                         ind_tbl->queues[i] = queues[i];
1896                 }
1897                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1898                                                         rqt_attr);
1899                 rte_free(rqt_attr);
1900                 if (!ind_tbl->rqt) {
1901                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
1902                                 dev->data->port_id);
1903                         rte_errno = errno;
1904                         goto error;
1905                 }
1906                 ind_tbl->queues_n = queues_n;
1907         }
1908         rte_atomic32_inc(&ind_tbl->refcnt);
1909         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1910         return ind_tbl;
1911 error:
1912         for (j = 0; j < i; j++)
1913                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1914         rte_free(ind_tbl);
1915         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1916         return NULL;
1917 }
1918
1919 /**
1920  * Get an indirection table.
1921  *
1922  * @param dev
1923  *   Pointer to Ethernet device.
1924  * @param queues
1925  *   Queues entering in the indirection table.
1926  * @param queues_n
1927  *   Number of queues in the array.
1928  *
1929  * @return
1930  *   An indirection table if found.
1931  */
1932 static struct mlx5_ind_table_obj *
1933 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1934                        uint32_t queues_n)
1935 {
1936         struct mlx5_priv *priv = dev->data->dev_private;
1937         struct mlx5_ind_table_obj *ind_tbl;
1938
1939         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1940                 if ((ind_tbl->queues_n == queues_n) &&
1941                     (memcmp(ind_tbl->queues, queues,
1942                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1943                      == 0))
1944                         break;
1945         }
1946         if (ind_tbl) {
1947                 unsigned int i;
1948
1949                 rte_atomic32_inc(&ind_tbl->refcnt);
1950                 for (i = 0; i != ind_tbl->queues_n; ++i)
1951                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1952         }
1953         return ind_tbl;
1954 }
1955
1956 /**
1957  * Release an indirection table.
1958  *
1959  * @param dev
1960  *   Pointer to Ethernet device.
1961  * @param ind_table
1962  *   Indirection table to release.
1963  *
1964  * @return
1965  *   1 while a reference on it exists, 0 when freed.
1966  */
1967 static int
1968 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1969                            struct mlx5_ind_table_obj *ind_tbl)
1970 {
1971         unsigned int i;
1972
1973         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
1974                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
1975                         claim_zero(mlx5_glue->destroy_rwq_ind_table
1976                                                         (ind_tbl->ind_table));
1977                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
1978                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
1979         }
1980         for (i = 0; i != ind_tbl->queues_n; ++i)
1981                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1982         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1983                 LIST_REMOVE(ind_tbl, next);
1984                 rte_free(ind_tbl);
1985                 return 0;
1986         }
1987         return 1;
1988 }
1989
1990 /**
1991  * Verify the Rx Queue list is empty
1992  *
1993  * @param dev
1994  *   Pointer to Ethernet device.
1995  *
1996  * @return
1997  *   The number of object not released.
1998  */
1999 int
2000 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2001 {
2002         struct mlx5_priv *priv = dev->data->dev_private;
2003         struct mlx5_ind_table_obj *ind_tbl;
2004         int ret = 0;
2005
2006         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2007                 DRV_LOG(DEBUG,
2008                         "port %u indirection table obj %p still referenced",
2009                         dev->data->port_id, (void *)ind_tbl);
2010                 ++ret;
2011         }
2012         return ret;
2013 }
2014
2015 /**
2016  * Create an Rx Hash queue.
2017  *
2018  * @param dev
2019  *   Pointer to Ethernet device.
2020  * @param rss_key
2021  *   RSS key for the Rx hash queue.
2022  * @param rss_key_len
2023  *   RSS key length.
2024  * @param hash_fields
2025  *   Verbs protocol hash field to make the RSS on.
2026  * @param queues
2027  *   Queues entering in hash queue. In case of empty hash_fields only the
2028  *   first queue index will be taken for the indirection table.
2029  * @param queues_n
2030  *   Number of queues.
2031  * @param tunnel
2032  *   Tunnel type.
2033  *
2034  * @return
2035  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2036  */
2037 struct mlx5_hrxq *
2038 mlx5_hrxq_new(struct rte_eth_dev *dev,
2039               const uint8_t *rss_key, uint32_t rss_key_len,
2040               uint64_t hash_fields,
2041               const uint16_t *queues, uint32_t queues_n,
2042               int tunnel __rte_unused)
2043 {
2044         struct mlx5_priv *priv = dev->data->dev_private;
2045         struct mlx5_hrxq *hrxq;
2046         struct ibv_qp *qp = NULL;
2047         struct mlx5_ind_table_obj *ind_tbl;
2048         int err;
2049         struct mlx5_devx_obj *tir = NULL;
2050
2051         queues_n = hash_fields ? queues_n : 1;
2052         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2053         if (!ind_tbl) {
2054                 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2055                 struct mlx5_rxq_ctrl *rxq_ctrl =
2056                         container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2057                 enum mlx5_ind_tbl_type type;
2058
2059                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2060                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2061                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2062         }
2063         if (!ind_tbl) {
2064                 rte_errno = ENOMEM;
2065                 return NULL;
2066         }
2067         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2068 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2069                 struct mlx5dv_qp_init_attr qp_init_attr;
2070
2071                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2072                 if (tunnel) {
2073                         qp_init_attr.comp_mask =
2074                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2075                         qp_init_attr.create_flags =
2076                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2077                 }
2078 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2079                 if (dev->data->dev_conf.lpbk_mode) {
2080                         /*
2081                          * Allow packet sent from NIC loop back
2082                          * w/o source MAC check.
2083                          */
2084                         qp_init_attr.comp_mask |=
2085                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2086                         qp_init_attr.create_flags |=
2087                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2088                 }
2089 #endif
2090                 qp = mlx5_glue->dv_create_qp
2091                         (priv->sh->ctx,
2092                          &(struct ibv_qp_init_attr_ex){
2093                                 .qp_type = IBV_QPT_RAW_PACKET,
2094                                 .comp_mask =
2095                                         IBV_QP_INIT_ATTR_PD |
2096                                         IBV_QP_INIT_ATTR_IND_TABLE |
2097                                         IBV_QP_INIT_ATTR_RX_HASH,
2098                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2099                                         .rx_hash_function =
2100                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2101                                         .rx_hash_key_len = rss_key_len,
2102                                         .rx_hash_key =
2103                                                 (void *)(uintptr_t)rss_key,
2104                                         .rx_hash_fields_mask = hash_fields,
2105                                 },
2106                                 .rwq_ind_tbl = ind_tbl->ind_table,
2107                                 .pd = priv->sh->pd,
2108                           },
2109                           &qp_init_attr);
2110 #else
2111                 qp = mlx5_glue->create_qp_ex
2112                         (priv->sh->ctx,
2113                          &(struct ibv_qp_init_attr_ex){
2114                                 .qp_type = IBV_QPT_RAW_PACKET,
2115                                 .comp_mask =
2116                                         IBV_QP_INIT_ATTR_PD |
2117                                         IBV_QP_INIT_ATTR_IND_TABLE |
2118                                         IBV_QP_INIT_ATTR_RX_HASH,
2119                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2120                                         .rx_hash_function =
2121                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2122                                         .rx_hash_key_len = rss_key_len,
2123                                         .rx_hash_key =
2124                                                 (void *)(uintptr_t)rss_key,
2125                                         .rx_hash_fields_mask = hash_fields,
2126                                 },
2127                                 .rwq_ind_tbl = ind_tbl->ind_table,
2128                                 .pd = priv->sh->pd,
2129                          });
2130 #endif
2131                 if (!qp) {
2132                         rte_errno = errno;
2133                         goto error;
2134                 }
2135         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2136                 struct mlx5_devx_tir_attr tir_attr;
2137
2138                 memset(&tir_attr, 0, sizeof(tir_attr));
2139                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2140                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2141                 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2142                        sizeof(uint64_t));
2143                 tir_attr.transport_domain = priv->sh->tdn;
2144                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2145                 tir_attr.indirect_table = ind_tbl->rqt->id;
2146                 if (dev->data->dev_conf.lpbk_mode)
2147                         tir_attr.self_lb_block =
2148                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2149                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2150                 if (!tir) {
2151                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2152                                 dev->data->port_id);
2153                         rte_errno = errno;
2154                         goto error;
2155                 }
2156         }
2157         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2158         if (!hrxq)
2159                 goto error;
2160         hrxq->ind_table = ind_tbl;
2161         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2162                 hrxq->qp = qp;
2163 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2164                 hrxq->action =
2165                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2166                 if (!hrxq->action) {
2167                         rte_errno = errno;
2168                         goto error;
2169                 }
2170 #endif
2171         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2172                 hrxq->tir = tir;
2173 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2174                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2175                                                         (hrxq->tir->obj);
2176                 if (!hrxq->action) {
2177                         rte_errno = errno;
2178                         goto error;
2179                 }
2180 #endif
2181         }
2182         hrxq->rss_key_len = rss_key_len;
2183         hrxq->hash_fields = hash_fields;
2184         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2185         rte_atomic32_inc(&hrxq->refcnt);
2186         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2187         return hrxq;
2188 error:
2189         err = rte_errno; /* Save rte_errno before cleanup. */
2190         mlx5_ind_table_obj_release(dev, ind_tbl);
2191         if (qp)
2192                 claim_zero(mlx5_glue->destroy_qp(qp));
2193         else if (tir)
2194                 claim_zero(mlx5_devx_cmd_destroy(tir));
2195         rte_errno = err; /* Restore rte_errno. */
2196         return NULL;
2197 }
2198
2199 /**
2200  * Get an Rx Hash queue.
2201  *
2202  * @param dev
2203  *   Pointer to Ethernet device.
2204  * @param rss_conf
2205  *   RSS configuration for the Rx hash queue.
2206  * @param queues
2207  *   Queues entering in hash queue. In case of empty hash_fields only the
2208  *   first queue index will be taken for the indirection table.
2209  * @param queues_n
2210  *   Number of queues.
2211  *
2212  * @return
2213  *   An hash Rx queue on success.
2214  */
2215 struct mlx5_hrxq *
2216 mlx5_hrxq_get(struct rte_eth_dev *dev,
2217               const uint8_t *rss_key, uint32_t rss_key_len,
2218               uint64_t hash_fields,
2219               const uint16_t *queues, uint32_t queues_n)
2220 {
2221         struct mlx5_priv *priv = dev->data->dev_private;
2222         struct mlx5_hrxq *hrxq;
2223
2224         queues_n = hash_fields ? queues_n : 1;
2225         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2226                 struct mlx5_ind_table_obj *ind_tbl;
2227
2228                 if (hrxq->rss_key_len != rss_key_len)
2229                         continue;
2230                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2231                         continue;
2232                 if (hrxq->hash_fields != hash_fields)
2233                         continue;
2234                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2235                 if (!ind_tbl)
2236                         continue;
2237                 if (ind_tbl != hrxq->ind_table) {
2238                         mlx5_ind_table_obj_release(dev, ind_tbl);
2239                         continue;
2240                 }
2241                 rte_atomic32_inc(&hrxq->refcnt);
2242                 return hrxq;
2243         }
2244         return NULL;
2245 }
2246
2247 /**
2248  * Release the hash Rx queue.
2249  *
2250  * @param dev
2251  *   Pointer to Ethernet device.
2252  * @param hrxq
2253  *   Pointer to Hash Rx queue to release.
2254  *
2255  * @return
2256  *   1 while a reference on it exists, 0 when freed.
2257  */
2258 int
2259 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2260 {
2261         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2262 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2263                 mlx5_glue->destroy_flow_action(hrxq->action);
2264 #endif
2265                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2266                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2267                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2268                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2269                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2270                 LIST_REMOVE(hrxq, next);
2271                 rte_free(hrxq);
2272                 return 0;
2273         }
2274         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2275         return 1;
2276 }
2277
2278 /**
2279  * Verify the Rx Queue list is empty
2280  *
2281  * @param dev
2282  *   Pointer to Ethernet device.
2283  *
2284  * @return
2285  *   The number of object not released.
2286  */
2287 int
2288 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2289 {
2290         struct mlx5_priv *priv = dev->data->dev_private;
2291         struct mlx5_hrxq *hrxq;
2292         int ret = 0;
2293
2294         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2295                 DRV_LOG(DEBUG,
2296                         "port %u hash Rx queue %p still referenced",
2297                         dev->data->port_id, (void *)hrxq);
2298                 ++ret;
2299         }
2300         return ret;
2301 }
2302
2303 /**
2304  * Create a drop Rx queue Verbs/DevX object.
2305  *
2306  * @param dev
2307  *   Pointer to Ethernet device.
2308  *
2309  * @return
2310  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2311  */
2312 static struct mlx5_rxq_obj *
2313 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2314 {
2315         struct mlx5_priv *priv = dev->data->dev_private;
2316         struct ibv_context *ctx = priv->sh->ctx;
2317         struct ibv_cq *cq;
2318         struct ibv_wq *wq = NULL;
2319         struct mlx5_rxq_obj *rxq;
2320
2321         if (priv->drop_queue.rxq)
2322                 return priv->drop_queue.rxq;
2323         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2324         if (!cq) {
2325                 DEBUG("port %u cannot allocate CQ for drop queue",
2326                       dev->data->port_id);
2327                 rte_errno = errno;
2328                 goto error;
2329         }
2330         wq = mlx5_glue->create_wq(ctx,
2331                  &(struct ibv_wq_init_attr){
2332                         .wq_type = IBV_WQT_RQ,
2333                         .max_wr = 1,
2334                         .max_sge = 1,
2335                         .pd = priv->sh->pd,
2336                         .cq = cq,
2337                  });
2338         if (!wq) {
2339                 DEBUG("port %u cannot allocate WQ for drop queue",
2340                       dev->data->port_id);
2341                 rte_errno = errno;
2342                 goto error;
2343         }
2344         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2345         if (!rxq) {
2346                 DEBUG("port %u cannot allocate drop Rx queue memory",
2347                       dev->data->port_id);
2348                 rte_errno = ENOMEM;
2349                 goto error;
2350         }
2351         rxq->cq = cq;
2352         rxq->wq = wq;
2353         priv->drop_queue.rxq = rxq;
2354         return rxq;
2355 error:
2356         if (wq)
2357                 claim_zero(mlx5_glue->destroy_wq(wq));
2358         if (cq)
2359                 claim_zero(mlx5_glue->destroy_cq(cq));
2360         return NULL;
2361 }
2362
2363 /**
2364  * Release a drop Rx queue Verbs/DevX object.
2365  *
2366  * @param dev
2367  *   Pointer to Ethernet device.
2368  *
2369  * @return
2370  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2371  */
2372 static void
2373 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2374 {
2375         struct mlx5_priv *priv = dev->data->dev_private;
2376         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2377
2378         if (rxq->wq)
2379                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2380         if (rxq->cq)
2381                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2382         rte_free(rxq);
2383         priv->drop_queue.rxq = NULL;
2384 }
2385
2386 /**
2387  * Create a drop indirection table.
2388  *
2389  * @param dev
2390  *   Pointer to Ethernet device.
2391  *
2392  * @return
2393  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2394  */
2395 static struct mlx5_ind_table_obj *
2396 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2397 {
2398         struct mlx5_priv *priv = dev->data->dev_private;
2399         struct mlx5_ind_table_obj *ind_tbl;
2400         struct mlx5_rxq_obj *rxq;
2401         struct mlx5_ind_table_obj tmpl;
2402
2403         rxq = mlx5_rxq_obj_drop_new(dev);
2404         if (!rxq)
2405                 return NULL;
2406         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2407                 (priv->sh->ctx,
2408                  &(struct ibv_rwq_ind_table_init_attr){
2409                         .log_ind_tbl_size = 0,
2410                         .ind_tbl = &rxq->wq,
2411                         .comp_mask = 0,
2412                  });
2413         if (!tmpl.ind_table) {
2414                 DEBUG("port %u cannot allocate indirection table for drop"
2415                       " queue",
2416                       dev->data->port_id);
2417                 rte_errno = errno;
2418                 goto error;
2419         }
2420         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2421         if (!ind_tbl) {
2422                 rte_errno = ENOMEM;
2423                 goto error;
2424         }
2425         ind_tbl->ind_table = tmpl.ind_table;
2426         return ind_tbl;
2427 error:
2428         mlx5_rxq_obj_drop_release(dev);
2429         return NULL;
2430 }
2431
2432 /**
2433  * Release a drop indirection table.
2434  *
2435  * @param dev
2436  *   Pointer to Ethernet device.
2437  */
2438 static void
2439 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2440 {
2441         struct mlx5_priv *priv = dev->data->dev_private;
2442         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2443
2444         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2445         mlx5_rxq_obj_drop_release(dev);
2446         rte_free(ind_tbl);
2447         priv->drop_queue.hrxq->ind_table = NULL;
2448 }
2449
2450 /**
2451  * Create a drop Rx Hash queue.
2452  *
2453  * @param dev
2454  *   Pointer to Ethernet device.
2455  *
2456  * @return
2457  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2458  */
2459 struct mlx5_hrxq *
2460 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2461 {
2462         struct mlx5_priv *priv = dev->data->dev_private;
2463         struct mlx5_ind_table_obj *ind_tbl;
2464         struct ibv_qp *qp;
2465         struct mlx5_hrxq *hrxq;
2466
2467         if (priv->drop_queue.hrxq) {
2468                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2469                 return priv->drop_queue.hrxq;
2470         }
2471         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2472         if (!ind_tbl)
2473                 return NULL;
2474         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2475                  &(struct ibv_qp_init_attr_ex){
2476                         .qp_type = IBV_QPT_RAW_PACKET,
2477                         .comp_mask =
2478                                 IBV_QP_INIT_ATTR_PD |
2479                                 IBV_QP_INIT_ATTR_IND_TABLE |
2480                                 IBV_QP_INIT_ATTR_RX_HASH,
2481                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2482                                 .rx_hash_function =
2483                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2484                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2485                                 .rx_hash_key = rss_hash_default_key,
2486                                 .rx_hash_fields_mask = 0,
2487                                 },
2488                         .rwq_ind_tbl = ind_tbl->ind_table,
2489                         .pd = priv->sh->pd
2490                  });
2491         if (!qp) {
2492                 DEBUG("port %u cannot allocate QP for drop queue",
2493                       dev->data->port_id);
2494                 rte_errno = errno;
2495                 goto error;
2496         }
2497         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2498         if (!hrxq) {
2499                 DRV_LOG(WARNING,
2500                         "port %u cannot allocate memory for drop queue",
2501                         dev->data->port_id);
2502                 rte_errno = ENOMEM;
2503                 goto error;
2504         }
2505         hrxq->ind_table = ind_tbl;
2506         hrxq->qp = qp;
2507 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2508         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2509         if (!hrxq->action) {
2510                 rte_errno = errno;
2511                 goto error;
2512         }
2513 #endif
2514         priv->drop_queue.hrxq = hrxq;
2515         rte_atomic32_set(&hrxq->refcnt, 1);
2516         return hrxq;
2517 error:
2518         if (ind_tbl)
2519                 mlx5_ind_table_obj_drop_release(dev);
2520         return NULL;
2521 }
2522
2523 /**
2524  * Release a drop hash Rx queue.
2525  *
2526  * @param dev
2527  *   Pointer to Ethernet device.
2528  */
2529 void
2530 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2531 {
2532         struct mlx5_priv *priv = dev->data->dev_private;
2533         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2534
2535         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2536 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2537                 mlx5_glue->destroy_flow_action(hrxq->action);
2538 #endif
2539                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2540                 mlx5_ind_table_obj_drop_release(dev);
2541                 rte_free(hrxq);
2542                 priv->drop_queue.hrxq = NULL;
2543         }
2544 }