drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  *
  97  * @param dev
  98  *   Pointer to Ethernet device.
  99  *
 100  * @return
 101  *   0 if disabled, otherwise enabled.
 102  */
 103 inline int
 104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 105 {
 106         struct mlx5_priv *priv = dev->data->dev_private;
 107         uint16_t i;
 108         uint16_t n = 0;
 109
 110         if (mlx5_check_mprq_support(dev) < 0)
 111                 return 0;
 112         /* All the configured queues should be enabled. */
 113         for (i = 0; i < priv->rxqs_n; ++i) {
 114                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 115
 116                 if (!rxq)
 117                         continue;
 118                 if (mlx5_rxq_mprq_enabled(rxq))
 119                         ++n;
 120         }
 121         /* Multi-Packet RQ can't be partially configured. */
 122         assert(n == 0 || n == priv->rxqs_n);
 123         return n == priv->rxqs_n;
 124 }
 125
 126 /**
 127  * Allocate RX queue elements for Multi-Packet RQ.
 128  *
 129  * @param rxq_ctrl
 130  *   Pointer to RX queue structure.
 131  *
 132  * @return
 133  *   0 on success, a negative errno value otherwise and rte_errno is set.
 134  */
 135 static int
 136 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 137 {
 138         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 139         unsigned int wqe_n = 1 << rxq->elts_n;
 140         unsigned int i;
 141         int err;
 142
 143         /* Iterate on segments. */
 144         for (i = 0; i <= wqe_n; ++i) {
 145                 struct mlx5_mprq_buf *buf;
 146
 147                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 148                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 149                         rte_errno = ENOMEM;
 150                         goto error;
 151                 }
 152                 if (i < wqe_n)
 153                         (*rxq->mprq_bufs)[i] = buf;
 154                 else
 155                         rxq->mprq_repl = buf;
 156         }
 157         DRV_LOG(DEBUG,
 158                 "port %u Rx queue %u allocated and configured %u segments",
 159                 rxq->port_id, rxq->idx, wqe_n);
 160         return 0;
 161 error:
 162         err = rte_errno; /* Save rte_errno before cleanup. */
 163         wqe_n = i;
 164         for (i = 0; (i != wqe_n); ++i) {
 165                 if ((*rxq->mprq_bufs)[i] != NULL)
 166                         rte_mempool_put(rxq->mprq_mp,
 167                                         (*rxq->mprq_bufs)[i]);
 168                 (*rxq->mprq_bufs)[i] = NULL;
 169         }
 170         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 171                 rxq->port_id, rxq->idx);
 172         rte_errno = err; /* Restore rte_errno. */
 173         return -rte_errno;
 174 }
 175
 176 /**
 177  * Allocate RX queue elements for Single-Packet RQ.
 178  *
 179  * @param rxq_ctrl
 180  *   Pointer to RX queue structure.
 181  *
 182  * @return
 183  *   0 on success, errno value on failure.
 184  */
 185 static int
 186 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 187 {
 188         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 189         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 190         unsigned int i;
 191         int err;
 192
 193         /* Iterate on segments. */
 194         for (i = 0; (i != elts_n); ++i) {
 195                 struct rte_mbuf *buf;
 196
 197                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 198                 if (buf == NULL) {
 199                         DRV_LOG(ERR, "port %u empty mbuf pool",
 200                                 PORT_ID(rxq_ctrl->priv));
 201                         rte_errno = ENOMEM;
 202                         goto error;
 203                 }
 204                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 205                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 206                 /* Buffer is supposed to be empty. */
 207                 assert(rte_pktmbuf_data_len(buf) == 0);
 208                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 209                 assert(!buf->next);
 210                 /* Only the first segment keeps headroom. */
 211                 if (i % sges_n)
 212                         SET_DATA_OFF(buf, 0);
 213                 PORT(buf) = rxq_ctrl->rxq.port_id;
 214                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 215                 PKT_LEN(buf) = DATA_LEN(buf);
 216                 NB_SEGS(buf) = 1;
 217                 (*rxq_ctrl->rxq.elts)[i] = buf;
 218         }
 219         /* If Rx vector is activated. */
 220         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 221                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 222                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 223                 int j;
 224
 225                 /* Initialize default rearm_data for vPMD. */
 226                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 227                 rte_mbuf_refcnt_set(mbuf_init, 1);
 228                 mbuf_init->nb_segs = 1;
 229                 mbuf_init->port = rxq->port_id;
 230                 /*
 231                  * prevent compiler reordering:
 232                  * rearm_data covers previous fields.
 233                  */
 234                 rte_compiler_barrier();
 235                 rxq->mbuf_initializer =
 236                         *(uint64_t *)&mbuf_init->rearm_data;
 237                 /* Padding with a fake mbuf for vectorized Rx. */
 238                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 239                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 240         }
 241         DRV_LOG(DEBUG,
 242                 "port %u Rx queue %u allocated and configured %u segments"
 243                 " (max %u packets)",
 244                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 245                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 246         return 0;
 247 error:
 248         err = rte_errno; /* Save rte_errno before cleanup. */
 249         elts_n = i;
 250         for (i = 0; (i != elts_n); ++i) {
 251                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 252                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 253                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 254         }
 255         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 256                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 257         rte_errno = err; /* Restore rte_errno. */
 258         return -rte_errno;
 259 }
 260
 261 /**
 262  * Allocate RX queue elements.
 263  *
 264  * @param rxq_ctrl
 265  *   Pointer to RX queue structure.
 266  *
 267  * @return
 268  *   0 on success, errno value on failure.
 269  */
 270 int
 271 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 272 {
 273         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 274                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 275 }
 276
 277 /**
 278  * Free RX queue elements for Multi-Packet RQ.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  */
 283 static void
 284 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 285 {
 286         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 287         uint16_t i;
 288
 289         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 290                 rxq->port_id, rxq->idx);
 291         if (rxq->mprq_bufs == NULL)
 292                 return;
 293         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 294         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 295                 if ((*rxq->mprq_bufs)[i] != NULL)
 296                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 297                 (*rxq->mprq_bufs)[i] = NULL;
 298         }
 299         if (rxq->mprq_repl != NULL) {
 300                 mlx5_mprq_buf_free(rxq->mprq_repl);
 301                 rxq->mprq_repl = NULL;
 302         }
 303 }
 304
 305 /**
 306  * Free RX queue elements for Single-Packet RQ.
 307  *
 308  * @param rxq_ctrl
 309  *   Pointer to RX queue structure.
 310  */
 311 static void
 312 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 313 {
 314         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 315         const uint16_t q_n = (1 << rxq->elts_n);
 316         const uint16_t q_mask = q_n - 1;
 317         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 318         uint16_t i;
 319
 320         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 321                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 322         if (rxq->elts == NULL)
 323                 return;
 324         /**
 325          * Some mbuf in the Ring belongs to the application.  They cannot be
 326          * freed.
 327          */
 328         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 329                 for (i = 0; i < used; ++i)
 330                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 331                 rxq->rq_pi = rxq->rq_ci;
 332         }
 333         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 334                 if ((*rxq->elts)[i] != NULL)
 335                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 336                 (*rxq->elts)[i] = NULL;
 337         }
 338 }
 339
 340 /**
 341  * Free RX queue elements.
 342  *
 343  * @param rxq_ctrl
 344  *   Pointer to RX queue structure.
 345  */
 346 static void
 347 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 348 {
 349         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 350                 rxq_free_elts_mprq(rxq_ctrl);
 351         else
 352                 rxq_free_elts_sprq(rxq_ctrl);
 353 }
 354
 355 /**
 356  * Returns the per-queue supported offloads.
 357  *
 358  * @param dev
 359  *   Pointer to Ethernet device.
 360  *
 361  * @return
 362  *   Supported Rx offloads.
 363  */
 364 uint64_t
 365 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 366 {
 367         struct mlx5_priv *priv = dev->data->dev_private;
 368         struct mlx5_dev_config *config = &priv->config;
 369         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 370                              DEV_RX_OFFLOAD_TIMESTAMP |
 371                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 372
 373         if (config->hw_fcs_strip)
 374                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 375
 376         if (config->hw_csum)
 377                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 378                              DEV_RX_OFFLOAD_UDP_CKSUM |
 379                              DEV_RX_OFFLOAD_TCP_CKSUM);
 380         if (config->hw_vlan_strip)
 381                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 382         return offloads;
 383 }
 384
 385
 386 /**
 387  * Returns the per-port supported offloads.
 388  *
 389  * @return
 390  *   Supported Rx offloads.
 391  */
 392 uint64_t
 393 mlx5_get_rx_port_offloads(void)
 394 {
 395         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 396
 397         return offloads;
 398 }
 399
 400 /**
 401  * Verify if the queue can be released.
 402  *
 403  * @param dev
 404  *   Pointer to Ethernet device.
 405  * @param idx
 406  *   RX queue index.
 407  *
 408  * @return
 409  *   1 if the queue can be released
 410  *   0 if the queue can not be released, there are references to it.
 411  *   Negative errno and rte_errno is set if queue doesn't exist.
 412  */
 413 static int
 414 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 415 {
 416         struct mlx5_priv *priv = dev->data->dev_private;
 417         struct mlx5_rxq_ctrl *rxq_ctrl;
 418
 419         if (!(*priv->rxqs)[idx]) {
 420                 rte_errno = EINVAL;
 421                 return -rte_errno;
 422         }
 423         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 424         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 425 }
 426
 427 /**
 428  *
 429  * @param dev
 430  *   Pointer to Ethernet device structure.
 431  * @param idx
 432  *   RX queue index.
 433  * @param desc
 434  *   Number of descriptors to configure in queue.
 435  * @param socket
 436  *   NUMA socket on which memory must be allocated.
 437  * @param[in] conf
 438  *   Thresholds parameters.
 439  * @param mp
 440  *   Memory pool for buffer allocations.
 441  *
 442  * @return
 443  *   0 on success, a negative errno value otherwise and rte_errno is set.
 444  */
 445 int
 446 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 447                     unsigned int socket, const struct rte_eth_rxconf *conf,
 448                     struct rte_mempool *mp)
 449 {
 450         struct mlx5_priv *priv = dev->data->dev_private;
 451         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 452         struct mlx5_rxq_ctrl *rxq_ctrl =
 453                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 454
 455         if (!rte_is_power_of_2(desc)) {
 456                 desc = 1 << log2above(desc);
 457                 DRV_LOG(WARNING,
 458                         "port %u increased number of descriptors in Rx queue %u"
 459                         " to the next power of two (%d)",
 460                         dev->data->port_id, idx, desc);
 461         }
 462         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 463                 dev->data->port_id, idx, desc);
 464         if (idx >= priv->rxqs_n) {
 465                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 466                         dev->data->port_id, idx, priv->rxqs_n);
 467                 rte_errno = EOVERFLOW;
 468                 return -rte_errno;
 469         }
 470         if (!mlx5_rxq_releasable(dev, idx)) {
 471                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 472                         dev->data->port_id, idx);
 473                 rte_errno = EBUSY;
 474                 return -rte_errno;
 475         }
 476         mlx5_rxq_release(dev, idx);
 477         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 478         if (!rxq_ctrl) {
 479                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 480                         dev->data->port_id, idx);
 481                 rte_errno = ENOMEM;
 482                 return -rte_errno;
 483         }
 484         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 485                 dev->data->port_id, idx);
 486         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 487         return 0;
 488 }
 489
 490 /**
 491  * DPDK callback to release a RX queue.
 492  *
 493  * @param dpdk_rxq
 494  *   Generic RX queue pointer.
 495  */
 496 void
 497 mlx5_rx_queue_release(void *dpdk_rxq)
 498 {
 499         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 500         struct mlx5_rxq_ctrl *rxq_ctrl;
 501         struct mlx5_priv *priv;
 502
 503         if (rxq == NULL)
 504                 return;
 505         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 506         priv = rxq_ctrl->priv;
 507         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 508                 rte_panic("port %u Rx queue %u is still used by a flow and"
 509                           " cannot be removed\n",
 510                           PORT_ID(priv), rxq->idx);
 511         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 512 }
 513
 514 /**
 515  * Get an Rx queue Verbs object.
 516  *
 517  * @param dev
 518  *   Pointer to Ethernet device.
 519  * @param idx
 520  *   Queue index in DPDK Rx queue array
 521  *
 522  * @return
 523  *   The Verbs object if it exists.
 524  */
 525 static struct mlx5_rxq_ibv *
 526 mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx)
 527 {
 528         struct mlx5_priv *priv = dev->data->dev_private;
 529         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 530         struct mlx5_rxq_ctrl *rxq_ctrl;
 531
 532         if (idx >= priv->rxqs_n)
 533                 return NULL;
 534         if (!rxq_data)
 535                 return NULL;
 536         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 537         if (rxq_ctrl->ibv)
 538                 rte_atomic32_inc(&rxq_ctrl->ibv->refcnt);
 539         return rxq_ctrl->ibv;
 540 }
 541
 542 /**
 543  * Release an Rx verbs queue object.
 544  *
 545  * @param rxq_ibv
 546  *   Verbs Rx queue object.
 547  *
 548  * @return
 549  *   1 while a reference on it exists, 0 when freed.
 550  */
 551 static int
 552 mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv)
 553 {
 554         assert(rxq_ibv);
 555         assert(rxq_ibv->wq);
 556         assert(rxq_ibv->cq);
 557         if (rte_atomic32_dec_and_test(&rxq_ibv->refcnt)) {
 558                 rxq_free_elts(rxq_ibv->rxq_ctrl);
 559                 claim_zero(mlx5_glue->destroy_wq(rxq_ibv->wq));
 560                 claim_zero(mlx5_glue->destroy_cq(rxq_ibv->cq));
 561                 if (rxq_ibv->channel)
 562                         claim_zero(mlx5_glue->destroy_comp_channel
 563                                    (rxq_ibv->channel));
 564                 LIST_REMOVE(rxq_ibv, next);
 565                 rte_free(rxq_ibv);
 566                 return 0;
 567         }
 568         return 1;
 569 }
 570
 571 /**
 572  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 573  *
 574  * @param dev
 575  *   Pointer to Ethernet device.
 576  *
 577  * @return
 578  *   0 on success, a negative errno value otherwise and rte_errno is set.
 579  */
 580 int
 581 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 582 {
 583         struct mlx5_priv *priv = dev->data->dev_private;
 584         unsigned int i;
 585         unsigned int rxqs_n = priv->rxqs_n;
 586         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 587         unsigned int count = 0;
 588         struct rte_intr_handle *intr_handle = dev->intr_handle;
 589
 590         if (!dev->data->dev_conf.intr_conf.rxq)
 591                 return 0;
 592         mlx5_rx_intr_vec_disable(dev);
 593         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 594         if (intr_handle->intr_vec == NULL) {
 595                 DRV_LOG(ERR,
 596                         "port %u failed to allocate memory for interrupt"
 597                         " vector, Rx interrupts will not be supported",
 598                         dev->data->port_id);
 599                 rte_errno = ENOMEM;
 600                 return -rte_errno;
 601         }
 602         intr_handle->type = RTE_INTR_HANDLE_EXT;
 603         for (i = 0; i != n; ++i) {
 604                 /* This rxq ibv must not be released in this function. */
 605                 struct mlx5_rxq_ibv *rxq_ibv = mlx5_rxq_ibv_get(dev, i);
 606                 int fd;
 607                 int flags;
 608                 int rc;
 609
 610                 /* Skip queues that cannot request interrupts. */
 611                 if (!rxq_ibv || !rxq_ibv->channel) {
 612                         /* Use invalid intr_vec[] index to disable entry. */
 613                         intr_handle->intr_vec[i] =
 614                                 RTE_INTR_VEC_RXTX_OFFSET +
 615                                 RTE_MAX_RXTX_INTR_VEC_ID;
 616                         continue;
 617                 }
 618                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 619                         DRV_LOG(ERR,
 620                                 "port %u too many Rx queues for interrupt"
 621                                 " vector size (%d), Rx interrupts cannot be"
 622                                 " enabled",
 623                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 624                         mlx5_rx_intr_vec_disable(dev);
 625                         rte_errno = ENOMEM;
 626                         return -rte_errno;
 627                 }
 628                 fd = rxq_ibv->channel->fd;
 629                 flags = fcntl(fd, F_GETFL);
 630                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 631                 if (rc < 0) {
 632                         rte_errno = errno;
 633                         DRV_LOG(ERR,
 634                                 "port %u failed to make Rx interrupt file"
 635                                 " descriptor %d non-blocking for queue index"
 636                                 " %d",
 637                                 dev->data->port_id, fd, i);
 638                         mlx5_rx_intr_vec_disable(dev);
 639                         return -rte_errno;
 640                 }
 641                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 642                 intr_handle->efds[count] = fd;
 643                 count++;
 644         }
 645         if (!count)
 646                 mlx5_rx_intr_vec_disable(dev);
 647         else
 648                 intr_handle->nb_efd = count;
 649         return 0;
 650 }
 651
 652 /**
 653  * Clean up Rx interrupts handler.
 654  *
 655  * @param dev
 656  *   Pointer to Ethernet device.
 657  */
 658 void
 659 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 660 {
 661         struct mlx5_priv *priv = dev->data->dev_private;
 662         struct rte_intr_handle *intr_handle = dev->intr_handle;
 663         unsigned int i;
 664         unsigned int rxqs_n = priv->rxqs_n;
 665         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 666
 667         if (!dev->data->dev_conf.intr_conf.rxq)
 668                 return;
 669         if (!intr_handle->intr_vec)
 670                 goto free;
 671         for (i = 0; i != n; ++i) {
 672                 struct mlx5_rxq_ctrl *rxq_ctrl;
 673                 struct mlx5_rxq_data *rxq_data;
 674
 675                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 676                     RTE_MAX_RXTX_INTR_VEC_ID)
 677                         continue;
 678                 /**
 679                  * Need to access directly the queue to release the reference
 680                  * kept in mlx5_rx_intr_vec_enable().
 681                  */
 682                 rxq_data = (*priv->rxqs)[i];
 683                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 684                 if (rxq_ctrl->ibv)
 685                         mlx5_rxq_ibv_release(rxq_ctrl->ibv);
 686         }
 687 free:
 688         rte_intr_free_epoll_fd(intr_handle);
 689         if (intr_handle->intr_vec)
 690                 free(intr_handle->intr_vec);
 691         intr_handle->nb_efd = 0;
 692         intr_handle->intr_vec = NULL;
 693 }
 694
 695 /**
 696  *  MLX5 CQ notification .
 697  *
 698  *  @param rxq
 699  *     Pointer to receive queue structure.
 700  *  @param sq_n_rxq
 701  *     Sequence number per receive queue .
 702  */
 703 static inline void
 704 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 705 {
 706         int sq_n = 0;
 707         uint32_t doorbell_hi;
 708         uint64_t doorbell;
 709         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 710
 711         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 712         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 713         doorbell = (uint64_t)doorbell_hi << 32;
 714         doorbell |=  rxq->cqn;
 715         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 716         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 717                          cq_db_reg, rxq->uar_lock_cq);
 718 }
 719
 720 /**
 721  * DPDK callback for Rx queue interrupt enable.
 722  *
 723  * @param dev
 724  *   Pointer to Ethernet device structure.
 725  * @param rx_queue_id
 726  *   Rx queue number.
 727  *
 728  * @return
 729  *   0 on success, a negative errno value otherwise and rte_errno is set.
 730  */
 731 int
 732 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 733 {
 734         struct mlx5_priv *priv = dev->data->dev_private;
 735         struct mlx5_rxq_data *rxq_data;
 736         struct mlx5_rxq_ctrl *rxq_ctrl;
 737
 738         rxq_data = (*priv->rxqs)[rx_queue_id];
 739         if (!rxq_data) {
 740                 rte_errno = EINVAL;
 741                 return -rte_errno;
 742         }
 743         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 744         if (rxq_ctrl->irq) {
 745                 struct mlx5_rxq_ibv *rxq_ibv;
 746
 747                 rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 748                 if (!rxq_ibv) {
 749                         rte_errno = EINVAL;
 750                         return -rte_errno;
 751                 }
 752                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 753                 mlx5_rxq_ibv_release(rxq_ibv);
 754         }
 755         return 0;
 756 }
 757
 758 /**
 759  * DPDK callback for Rx queue interrupt disable.
 760  *
 761  * @param dev
 762  *   Pointer to Ethernet device structure.
 763  * @param rx_queue_id
 764  *   Rx queue number.
 765  *
 766  * @return
 767  *   0 on success, a negative errno value otherwise and rte_errno is set.
 768  */
 769 int
 770 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 771 {
 772         struct mlx5_priv *priv = dev->data->dev_private;
 773         struct mlx5_rxq_data *rxq_data;
 774         struct mlx5_rxq_ctrl *rxq_ctrl;
 775         struct mlx5_rxq_ibv *rxq_ibv = NULL;
 776         struct ibv_cq *ev_cq;
 777         void *ev_ctx;
 778         int ret;
 779
 780         rxq_data = (*priv->rxqs)[rx_queue_id];
 781         if (!rxq_data) {
 782                 rte_errno = EINVAL;
 783                 return -rte_errno;
 784         }
 785         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 786         if (!rxq_ctrl->irq)
 787                 return 0;
 788         rxq_ibv = mlx5_rxq_ibv_get(dev, rx_queue_id);
 789         if (!rxq_ibv) {
 790                 rte_errno = EINVAL;
 791                 return -rte_errno;
 792         }
 793         ret = mlx5_glue->get_cq_event(rxq_ibv->channel, &ev_cq, &ev_ctx);
 794         if (ret || ev_cq != rxq_ibv->cq) {
 795                 rte_errno = EINVAL;
 796                 goto exit;
 797         }
 798         rxq_data->cq_arm_sn++;
 799         mlx5_glue->ack_cq_events(rxq_ibv->cq, 1);
 800         mlx5_rxq_ibv_release(rxq_ibv);
 801         return 0;
 802 exit:
 803         ret = rte_errno; /* Save rte_errno before cleanup. */
 804         if (rxq_ibv)
 805                 mlx5_rxq_ibv_release(rxq_ibv);
 806         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 807                 dev->data->port_id, rx_queue_id);
 808         rte_errno = ret; /* Restore rte_errno. */
 809         return -rte_errno;
 810 }
 811
 812 /**
 813  * Create the Rx queue Verbs object.
 814  *
 815  * @param dev
 816  *   Pointer to Ethernet device.
 817  * @param idx
 818  *   Queue index in DPDK Rx queue array
 819  *
 820  * @return
 821  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 822  */
 823 struct mlx5_rxq_ibv *
 824 mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx)
 825 {
 826         struct mlx5_priv *priv = dev->data->dev_private;
 827         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 828         struct mlx5_rxq_ctrl *rxq_ctrl =
 829                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 830         struct ibv_wq_attr mod;
 831         union {
 832                 struct {
 833                         struct ibv_cq_init_attr_ex ibv;
 834                         struct mlx5dv_cq_init_attr mlx5;
 835                 } cq;
 836                 struct {
 837                         struct ibv_wq_init_attr ibv;
 838 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 839                         struct mlx5dv_wq_init_attr mlx5;
 840 #endif
 841                 } wq;
 842                 struct ibv_cq_ex cq_attr;
 843         } attr;
 844         unsigned int cqe_n;
 845         unsigned int wqe_n = 1 << rxq_data->elts_n;
 846         struct mlx5_rxq_ibv *tmpl;
 847         struct mlx5dv_cq cq_info;
 848         struct mlx5dv_rwq rwq;
 849         unsigned int i;
 850         int ret = 0;
 851         struct mlx5dv_obj obj;
 852         struct mlx5_dev_config *config = &priv->config;
 853         const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
 854
 855         assert(rxq_data);
 856         assert(!rxq_ctrl->ibv);
 857         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
 858         priv->verbs_alloc_ctx.obj = rxq_ctrl;
 859         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
 860                                  rxq_ctrl->socket);
 861         if (!tmpl) {
 862                 DRV_LOG(ERR,
 863                         "port %u Rx queue %u cannot allocate verbs resources",
 864                         dev->data->port_id, rxq_data->idx);
 865                 rte_errno = ENOMEM;
 866                 goto error;
 867         }
 868         tmpl->rxq_ctrl = rxq_ctrl;
 869         if (rxq_ctrl->irq) {
 870                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
 871                 if (!tmpl->channel) {
 872                         DRV_LOG(ERR, "port %u: comp channel creation failure",
 873                                 dev->data->port_id);
 874                         rte_errno = ENOMEM;
 875                         goto error;
 876                 }
 877         }
 878         if (mprq_en)
 879                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 880         else
 881                 cqe_n = wqe_n  - 1;
 882         attr.cq.ibv = (struct ibv_cq_init_attr_ex){
 883                 .cqe = cqe_n,
 884                 .channel = tmpl->channel,
 885                 .comp_mask = 0,
 886         };
 887         attr.cq.mlx5 = (struct mlx5dv_cq_init_attr){
 888                 .comp_mask = 0,
 889         };
 890         if (config->cqe_comp && !rxq_data->hw_timestamp) {
 891                 attr.cq.mlx5.comp_mask |=
 892                         MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 893 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 894                 attr.cq.mlx5.cqe_comp_res_format =
 895                         mprq_en ? MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 896                                   MLX5DV_CQE_RES_FORMAT_HASH;
 897 #else
 898                 attr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 899 #endif
 900                 /*
 901                  * For vectorized Rx, it must not be doubled in order to
 902                  * make cq_ci and rq_ci aligned.
 903                  */
 904                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 905                         attr.cq.ibv.cqe *= 2;
 906         } else if (config->cqe_comp && rxq_data->hw_timestamp) {
 907                 DRV_LOG(DEBUG,
 908                         "port %u Rx CQE compression is disabled for HW"
 909                         " timestamp",
 910                         dev->data->port_id);
 911         }
 912 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 913         if (config->cqe_pad) {
 914                 attr.cq.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 915                 attr.cq.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 916         }
 917 #endif
 918         tmpl->cq = mlx5_glue->cq_ex_to_cq
 919                 (mlx5_glue->dv_create_cq(priv->sh->ctx, &attr.cq.ibv,
 920                                          &attr.cq.mlx5));
 921         if (tmpl->cq == NULL) {
 922                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
 923                         dev->data->port_id, idx);
 924                 rte_errno = ENOMEM;
 925                 goto error;
 926         }
 927         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
 928                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
 929         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
 930                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
 931         attr.wq.ibv = (struct ibv_wq_init_attr){
 932                 .wq_context = NULL, /* Could be useful in the future. */
 933                 .wq_type = IBV_WQT_RQ,
 934                 /* Max number of outstanding WRs. */
 935                 .max_wr = wqe_n >> rxq_data->sges_n,
 936                 /* Max number of scatter/gather elements in a WR. */
 937                 .max_sge = 1 << rxq_data->sges_n,
 938                 .pd = priv->sh->pd,
 939                 .cq = tmpl->cq,
 940                 .comp_mask =
 941                         IBV_WQ_FLAGS_CVLAN_STRIPPING |
 942                         0,
 943                 .create_flags = (rxq_data->vlan_strip ?
 944                                  IBV_WQ_FLAGS_CVLAN_STRIPPING :
 945                                  0),
 946         };
 947         /* By default, FCS (CRC) is stripped by hardware. */
 948         if (rxq_data->crc_present) {
 949                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 950                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 951         }
 952         if (config->hw_padding) {
 953 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 954                 attr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 955                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 956 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 957                 attr.wq.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 958                 attr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 959 #endif
 960         }
 961 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 962         attr.wq.mlx5 = (struct mlx5dv_wq_init_attr){
 963                 .comp_mask = 0,
 964         };
 965         if (mprq_en) {
 966                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 967                         &attr.wq.mlx5.striding_rq_attrs;
 968
 969                 attr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 970                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 971                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 972                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 973                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 974                 };
 975         }
 976         tmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &attr.wq.ibv,
 977                                            &attr.wq.mlx5);
 978 #else
 979         tmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &attr.wq.ibv);
 980 #endif
 981         if (tmpl->wq == NULL) {
 982                 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
 983                         dev->data->port_id, idx);
 984                 rte_errno = ENOMEM;
 985                 goto error;
 986         }
 987         /*
 988          * Make sure number of WRs*SGEs match expectations since a queue
 989          * cannot allocate more than "desc" buffers.
 990          */
 991         if (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
 992             attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {
 993                 DRV_LOG(ERR,
 994                         "port %u Rx queue %u requested %u*%u but got %u*%u"
 995                         " WRs*SGEs",
 996                         dev->data->port_id, idx,
 997                         wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
 998                         attr.wq.ibv.max_wr, attr.wq.ibv.max_sge);
 999                 rte_errno = EINVAL;
1000                 goto error;
1001         }
1002         /* Change queue state to ready. */
1003         mod = (struct ibv_wq_attr){
1004                 .attr_mask = IBV_WQ_ATTR_STATE,
1005                 .wq_state = IBV_WQS_RDY,
1006         };
1007         ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1008         if (ret) {
1009                 DRV_LOG(ERR,
1010                         "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
1011                         dev->data->port_id, idx);
1012                 rte_errno = ret;
1013                 goto error;
1014         }
1015         obj.cq.in = tmpl->cq;
1016         obj.cq.out = &cq_info;
1017         obj.rwq.in = tmpl->wq;
1018         obj.rwq.out = &rwq;
1019         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
1020         if (ret) {
1021                 rte_errno = ret;
1022                 goto error;
1023         }
1024         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1025                 DRV_LOG(ERR,
1026                         "port %u wrong MLX5_CQE_SIZE environment variable"
1027                         " value: it should be set to %u",
1028                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1029                 rte_errno = EINVAL;
1030                 goto error;
1031         }
1032         /* Fill the rings. */
1033         rxq_data->wqes = rwq.buf;
1034         for (i = 0; (i != wqe_n); ++i) {
1035                 volatile struct mlx5_wqe_data_seg *scat;
1036                 uintptr_t addr;
1037                 uint32_t byte_count;
1038
1039                 if (mprq_en) {
1040                         struct mlx5_mprq_buf *buf = (*rxq_data->mprq_bufs)[i];
1041
1042                         scat = &((volatile struct mlx5_wqe_mprq *)
1043                                  rxq_data->wqes)[i].dseg;
1044                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
1045                         byte_count = (1 << rxq_data->strd_sz_n) *
1046                                      (1 << rxq_data->strd_num_n);
1047                 } else {
1048                         struct rte_mbuf *buf = (*rxq_data->elts)[i];
1049
1050                         scat = &((volatile struct mlx5_wqe_data_seg *)
1051                                  rxq_data->wqes)[i];
1052                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1053                         byte_count = DATA_LEN(buf);
1054                 }
1055                 /* scat->addr must be able to store a pointer. */
1056                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
1057                 *scat = (struct mlx5_wqe_data_seg){
1058                         .addr = rte_cpu_to_be_64(addr),
1059                         .byte_count = rte_cpu_to_be_32(byte_count),
1060                         .lkey = mlx5_rx_addr2mr(rxq_data, addr),
1061                 };
1062         }
1063         rxq_data->rq_db = rwq.dbrec;
1064         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1065         rxq_data->cq_ci = 0;
1066         rxq_data->consumed_strd = 0;
1067         rxq_data->rq_pi = 0;
1068         rxq_data->zip = (struct rxq_zip){
1069                 .ai = 0,
1070         };
1071         rxq_data->cq_db = cq_info.dbrec;
1072         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1073         rxq_data->cq_uar = cq_info.cq_uar;
1074         rxq_data->cqn = cq_info.cqn;
1075         rxq_data->cq_arm_sn = 0;
1076         /* Update doorbell counter. */
1077         rxq_data->rq_ci = wqe_n >> rxq_data->sges_n;
1078         rte_wmb();
1079         *rxq_data->rq_db = rte_cpu_to_be_32(rxq_data->rq_ci);
1080         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1081                 idx, (void *)&tmpl);
1082         rte_atomic32_inc(&tmpl->refcnt);
1083         LIST_INSERT_HEAD(&priv->rxqsibv, tmpl, next);
1084         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1085         return tmpl;
1086 error:
1087         ret = rte_errno; /* Save rte_errno before cleanup. */
1088         if (tmpl->wq)
1089                 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1090         if (tmpl->cq)
1091                 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1092         if (tmpl->channel)
1093                 claim_zero(mlx5_glue->destroy_comp_channel(tmpl->channel));
1094         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1095         rte_errno = ret; /* Restore rte_errno. */
1096         return NULL;
1097 }
1098
1099 /**
1100  * Verify the Verbs Rx queue list is empty
1101  *
1102  * @param dev
1103  *   Pointer to Ethernet device.
1104  *
1105  * @return
1106  *   The number of object not released.
1107  */
1108 int
1109 mlx5_rxq_ibv_verify(struct rte_eth_dev *dev)
1110 {
1111         struct mlx5_priv *priv = dev->data->dev_private;
1112         int ret = 0;
1113         struct mlx5_rxq_ibv *rxq_ibv;
1114
1115         LIST_FOREACH(rxq_ibv, &priv->rxqsibv, next) {
1116                 DRV_LOG(DEBUG, "port %u Verbs Rx queue %u still referenced",
1117                         dev->data->port_id, rxq_ibv->rxq_ctrl->rxq.idx);
1118                 ++ret;
1119         }
1120         return ret;
1121 }
1122
1123 /**
1124  * Callback function to initialize mbufs for Multi-Packet RQ.
1125  */
1126 static inline void
1127 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1128                     void *_m, unsigned int i __rte_unused)
1129 {
1130         struct mlx5_mprq_buf *buf = _m;
1131
1132         memset(_m, 0, sizeof(*buf));
1133         buf->mp = mp;
1134         rte_atomic16_set(&buf->refcnt, 1);
1135 }
1136
1137 /**
1138  * Free mempool of Multi-Packet RQ.
1139  *
1140  * @param dev
1141  *   Pointer to Ethernet device.
1142  *
1143  * @return
1144  *   0 on success, negative errno value on failure.
1145  */
1146 int
1147 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1148 {
1149         struct mlx5_priv *priv = dev->data->dev_private;
1150         struct rte_mempool *mp = priv->mprq_mp;
1151         unsigned int i;
1152
1153         if (mp == NULL)
1154                 return 0;
1155         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1156                 dev->data->port_id, mp->name);
1157         /*
1158          * If a buffer in the pool has been externally attached to a mbuf and it
1159          * is still in use by application, destroying the Rx qeueue can spoil
1160          * the packet. It is unlikely to happen but if application dynamically
1161          * creates and destroys with holding Rx packets, this can happen.
1162          *
1163          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1164          * RQ isn't provided by application but managed by PMD.
1165          */
1166         if (!rte_mempool_full(mp)) {
1167                 DRV_LOG(ERR,
1168                         "port %u mempool for Multi-Packet RQ is still in use",
1169                         dev->data->port_id);
1170                 rte_errno = EBUSY;
1171                 return -rte_errno;
1172         }
1173         rte_mempool_free(mp);
1174         /* Unset mempool for each Rx queue. */
1175         for (i = 0; i != priv->rxqs_n; ++i) {
1176                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1177
1178                 if (rxq == NULL)
1179                         continue;
1180                 rxq->mprq_mp = NULL;
1181         }
1182         priv->mprq_mp = NULL;
1183         return 0;
1184 }
1185
1186 /**
1187  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1188  * mempool. If already allocated, reuse it if there're enough elements.
1189  * Otherwise, resize it.
1190  *
1191  * @param dev
1192  *   Pointer to Ethernet device.
1193  *
1194  * @return
1195  *   0 on success, negative errno value on failure.
1196  */
1197 int
1198 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1199 {
1200         struct mlx5_priv *priv = dev->data->dev_private;
1201         struct rte_mempool *mp = priv->mprq_mp;
1202         char name[RTE_MEMPOOL_NAMESIZE];
1203         unsigned int desc = 0;
1204         unsigned int buf_len;
1205         unsigned int obj_num;
1206         unsigned int obj_size;
1207         unsigned int strd_num_n = 0;
1208         unsigned int strd_sz_n = 0;
1209         unsigned int i;
1210
1211         if (!mlx5_mprq_enabled(dev))
1212                 return 0;
1213         /* Count the total number of descriptors configured. */
1214         for (i = 0; i != priv->rxqs_n; ++i) {
1215                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1216
1217                 if (rxq == NULL)
1218                         continue;
1219                 desc += 1 << rxq->elts_n;
1220                 /* Get the max number of strides. */
1221                 if (strd_num_n < rxq->strd_num_n)
1222                         strd_num_n = rxq->strd_num_n;
1223                 /* Get the max size of a stride. */
1224                 if (strd_sz_n < rxq->strd_sz_n)
1225                         strd_sz_n = rxq->strd_sz_n;
1226         }
1227         assert(strd_num_n && strd_sz_n);
1228         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1229         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1230         /*
1231          * Received packets can be either memcpy'd or externally referenced. In
1232          * case that the packet is attached to an mbuf as an external buffer, as
1233          * it isn't possible to predict how the buffers will be queued by
1234          * application, there's no option to exactly pre-allocate needed buffers
1235          * in advance but to speculatively prepares enough buffers.
1236          *
1237          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1238          * received packets to buffers provided by application (rxq->mp) until
1239          * this Mempool gets available again.
1240          */
1241         desc *= 4;
1242         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1243         /*
1244          * rte_mempool_create_empty() has sanity check to refuse large cache
1245          * size compared to the number of elements.
1246          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1247          * constant number 2 instead.
1248          */
1249         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1250         /* Check a mempool is already allocated and if it can be resued. */
1251         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1252                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1253                         dev->data->port_id, mp->name);
1254                 /* Reuse. */
1255                 goto exit;
1256         } else if (mp != NULL) {
1257                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1258                         dev->data->port_id, mp->name);
1259                 /*
1260                  * If failed to free, which means it may be still in use, no way
1261                  * but to keep using the existing one. On buffer underrun,
1262                  * packets will be memcpy'd instead of external buffer
1263                  * attachment.
1264                  */
1265                 if (mlx5_mprq_free_mp(dev)) {
1266                         if (mp->elt_size >= obj_size)
1267                                 goto exit;
1268                         else
1269                                 return -rte_errno;
1270                 }
1271         }
1272         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1273         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1274                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1275                                 dev->device->numa_node, 0);
1276         if (mp == NULL) {
1277                 DRV_LOG(ERR,
1278                         "port %u failed to allocate a mempool for"
1279                         " Multi-Packet RQ, count=%u, size=%u",
1280                         dev->data->port_id, obj_num, obj_size);
1281                 rte_errno = ENOMEM;
1282                 return -rte_errno;
1283         }
1284         priv->mprq_mp = mp;
1285 exit:
1286         /* Set mempool for each Rx queue. */
1287         for (i = 0; i != priv->rxqs_n; ++i) {
1288                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1289
1290                 if (rxq == NULL)
1291                         continue;
1292                 rxq->mprq_mp = mp;
1293         }
1294         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1295                 dev->data->port_id);
1296         return 0;
1297 }
1298
1299 /**
1300  * Create a DPDK Rx queue.
1301  *
1302  * @param dev
1303  *   Pointer to Ethernet device.
1304  * @param idx
1305  *   RX queue index.
1306  * @param desc
1307  *   Number of descriptors to configure in queue.
1308  * @param socket
1309  *   NUMA socket on which memory must be allocated.
1310  *
1311  * @return
1312  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1313  */
1314 struct mlx5_rxq_ctrl *
1315 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1316              unsigned int socket, const struct rte_eth_rxconf *conf,
1317              struct rte_mempool *mp)
1318 {
1319         struct mlx5_priv *priv = dev->data->dev_private;
1320         struct mlx5_rxq_ctrl *tmpl;
1321         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1322         unsigned int mprq_stride_size;
1323         struct mlx5_dev_config *config = &priv->config;
1324         /*
1325          * Always allocate extra slots, even if eventually
1326          * the vector Rx will not be used.
1327          */
1328         uint16_t desc_n =
1329                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1330         uint64_t offloads = conf->offloads |
1331                            dev->data->dev_conf.rxmode.offloads;
1332         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1333
1334         tmpl = rte_calloc_socket("RXQ", 1,
1335                                  sizeof(*tmpl) +
1336                                  desc_n * sizeof(struct rte_mbuf *),
1337                                  0, socket);
1338         if (!tmpl) {
1339                 rte_errno = ENOMEM;
1340                 return NULL;
1341         }
1342         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1343                                MLX5_MR_BTREE_CACHE_N, socket)) {
1344                 /* rte_errno is already set. */
1345                 goto error;
1346         }
1347         tmpl->socket = socket;
1348         if (dev->data->dev_conf.intr_conf.rxq)
1349                 tmpl->irq = 1;
1350         /*
1351          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1352          * following conditions are met:
1353          *  - MPRQ is enabled.
1354          *  - The number of descs is more than the number of strides.
1355          *  - max_rx_pkt_len plus overhead is less than the max size of a
1356          *    stride.
1357          *  Otherwise, enable Rx scatter if necessary.
1358          */
1359         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1360         mprq_stride_size =
1361                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1362                 sizeof(struct rte_mbuf_ext_shared_info) +
1363                 RTE_PKTMBUF_HEADROOM;
1364         if (mprq_en &&
1365             desc > (1U << config->mprq.stride_num_n) &&
1366             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1367                 /* TODO: Rx scatter isn't supported yet. */
1368                 tmpl->rxq.sges_n = 0;
1369                 /* Trim the number of descs needed. */
1370                 desc >>= config->mprq.stride_num_n;
1371                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1372                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1373                                               config->mprq.min_stride_size_n);
1374                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1375                 tmpl->rxq.mprq_max_memcpy_len =
1376                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1377                                 config->mprq.max_memcpy_len);
1378                 DRV_LOG(DEBUG,
1379                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1380                         " strd_num_n = %u, strd_sz_n = %u",
1381                         dev->data->port_id, idx,
1382                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1383         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1384                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1385                 tmpl->rxq.sges_n = 0;
1386         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1387                 unsigned int size =
1388                         RTE_PKTMBUF_HEADROOM +
1389                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1390                 unsigned int sges_n;
1391
1392                 /*
1393                  * Determine the number of SGEs needed for a full packet
1394                  * and round it to the next power of two.
1395                  */
1396                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1397                 tmpl->rxq.sges_n = sges_n;
1398                 /* Make sure rxq.sges_n did not overflow. */
1399                 size = mb_len * (1 << tmpl->rxq.sges_n);
1400                 size -= RTE_PKTMBUF_HEADROOM;
1401                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1402                         DRV_LOG(ERR,
1403                                 "port %u too many SGEs (%u) needed to handle"
1404                                 " requested maximum packet size %u",
1405                                 dev->data->port_id,
1406                                 1 << sges_n,
1407                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1408                         rte_errno = EOVERFLOW;
1409                         goto error;
1410                 }
1411         } else {
1412                 DRV_LOG(WARNING,
1413                         "port %u the requested maximum Rx packet size (%u) is"
1414                         " larger than a single mbuf (%u) and scattered mode has"
1415                         " not been requested",
1416                         dev->data->port_id,
1417                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1418                         mb_len - RTE_PKTMBUF_HEADROOM);
1419         }
1420         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1421                 DRV_LOG(WARNING,
1422                         "port %u MPRQ is requested but cannot be enabled"
1423                         " (requested: desc = %u, stride_sz = %u,"
1424                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1425                         dev->data->port_id, desc, mprq_stride_size,
1426                         (1 << config->mprq.stride_num_n),
1427                         (1 << config->mprq.max_stride_size_n));
1428         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1429                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1430         if (desc % (1 << tmpl->rxq.sges_n)) {
1431                 DRV_LOG(ERR,
1432                         "port %u number of Rx queue descriptors (%u) is not a"
1433                         " multiple of SGEs per packet (%u)",
1434                         dev->data->port_id,
1435                         desc,
1436                         1 << tmpl->rxq.sges_n);
1437                 rte_errno = EINVAL;
1438                 goto error;
1439         }
1440         /* Toggle RX checksum offload if hardware supports it. */
1441         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1442         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1443         /* Configure VLAN stripping. */
1444         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1445         /* By default, FCS (CRC) is stripped by hardware. */
1446         tmpl->rxq.crc_present = 0;
1447         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1448                 if (config->hw_fcs_strip) {
1449                         tmpl->rxq.crc_present = 1;
1450                 } else {
1451                         DRV_LOG(WARNING,
1452                                 "port %u CRC stripping has been disabled but will"
1453                                 " still be performed by hardware, make sure MLNX_OFED"
1454                                 " and firmware are up to date",
1455                                 dev->data->port_id);
1456                 }
1457         }
1458         DRV_LOG(DEBUG,
1459                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1460                 " incoming frames to hide it",
1461                 dev->data->port_id,
1462                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1463                 tmpl->rxq.crc_present << 2);
1464         /* Save port ID. */
1465         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1466                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1467         tmpl->rxq.port_id = dev->data->port_id;
1468         tmpl->priv = priv;
1469         tmpl->rxq.mp = mp;
1470         tmpl->rxq.elts_n = log2above(desc);
1471         tmpl->rxq.rq_repl_thresh =
1472                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1473         tmpl->rxq.elts =
1474                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1475 #ifndef RTE_ARCH_64
1476         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1477 #endif
1478         tmpl->rxq.idx = idx;
1479         rte_atomic32_inc(&tmpl->refcnt);
1480         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1481         return tmpl;
1482 error:
1483         rte_free(tmpl);
1484         return NULL;
1485 }
1486
1487 /**
1488  * Get a Rx queue.
1489  *
1490  * @param dev
1491  *   Pointer to Ethernet device.
1492  * @param idx
1493  *   RX queue index.
1494  *
1495  * @return
1496  *   A pointer to the queue if it exists, NULL otherwise.
1497  */
1498 struct mlx5_rxq_ctrl *
1499 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1500 {
1501         struct mlx5_priv *priv = dev->data->dev_private;
1502         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1503
1504         if ((*priv->rxqs)[idx]) {
1505                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1506                                         struct mlx5_rxq_ctrl,
1507                                         rxq);
1508                 mlx5_rxq_ibv_get(dev, idx);
1509                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1510         }
1511         return rxq_ctrl;
1512 }
1513
1514 /**
1515  * Release a Rx queue.
1516  *
1517  * @param dev
1518  *   Pointer to Ethernet device.
1519  * @param idx
1520  *   RX queue index.
1521  *
1522  * @return
1523  *   1 while a reference on it exists, 0 when freed.
1524  */
1525 int
1526 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1527 {
1528         struct mlx5_priv *priv = dev->data->dev_private;
1529         struct mlx5_rxq_ctrl *rxq_ctrl;
1530
1531         if (!(*priv->rxqs)[idx])
1532                 return 0;
1533         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1534         assert(rxq_ctrl->priv);
1535         if (rxq_ctrl->ibv && !mlx5_rxq_ibv_release(rxq_ctrl->ibv))
1536                 rxq_ctrl->ibv = NULL;
1537         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1538                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1539                 LIST_REMOVE(rxq_ctrl, next);
1540                 rte_free(rxq_ctrl);
1541                 (*priv->rxqs)[idx] = NULL;
1542                 return 0;
1543         }
1544         return 1;
1545 }
1546
1547 /**
1548  * Verify the Rx Queue list is empty
1549  *
1550  * @param dev
1551  *   Pointer to Ethernet device.
1552  *
1553  * @return
1554  *   The number of object not released.
1555  */
1556 int
1557 mlx5_rxq_verify(struct rte_eth_dev *dev)
1558 {
1559         struct mlx5_priv *priv = dev->data->dev_private;
1560         struct mlx5_rxq_ctrl *rxq_ctrl;
1561         int ret = 0;
1562
1563         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1564                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1565                         dev->data->port_id, rxq_ctrl->rxq.idx);
1566                 ++ret;
1567         }
1568         return ret;
1569 }
1570
1571 /**
1572  * Create an indirection table.
1573  *
1574  * @param dev
1575  *   Pointer to Ethernet device.
1576  * @param queues
1577  *   Queues entering in the indirection table.
1578  * @param queues_n
1579  *   Number of queues in the array.
1580  *
1581  * @return
1582  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1583  */
1584 static struct mlx5_ind_table_ibv *
1585 mlx5_ind_table_ibv_new(struct rte_eth_dev *dev, const uint16_t *queues,
1586                        uint32_t queues_n)
1587 {
1588         struct mlx5_priv *priv = dev->data->dev_private;
1589         struct mlx5_ind_table_ibv *ind_tbl;
1590         const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1591                 log2above(queues_n) :
1592                 log2above(priv->config.ind_table_max_size);
1593         struct ibv_wq *wq[1 << wq_n];
1594         unsigned int i;
1595         unsigned int j;
1596
1597         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1598                              queues_n * sizeof(uint16_t), 0);
1599         if (!ind_tbl) {
1600                 rte_errno = ENOMEM;
1601                 return NULL;
1602         }
1603         for (i = 0; i != queues_n; ++i) {
1604                 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1605
1606                 if (!rxq)
1607                         goto error;
1608                 wq[i] = rxq->ibv->wq;
1609                 ind_tbl->queues[i] = queues[i];
1610         }
1611         ind_tbl->queues_n = queues_n;
1612         /* Finalise indirection table. */
1613         for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1614                 wq[i] = wq[j];
1615         ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1616                 (priv->sh->ctx,
1617                  &(struct ibv_rwq_ind_table_init_attr){
1618                         .log_ind_tbl_size = wq_n,
1619                         .ind_tbl = wq,
1620                         .comp_mask = 0,
1621                  });
1622         if (!ind_tbl->ind_table) {
1623                 rte_errno = errno;
1624                 goto error;
1625         }
1626         rte_atomic32_inc(&ind_tbl->refcnt);
1627         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1628         return ind_tbl;
1629 error:
1630         rte_free(ind_tbl);
1631         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1632         return NULL;
1633 }
1634
1635 /**
1636  * Get an indirection table.
1637  *
1638  * @param dev
1639  *   Pointer to Ethernet device.
1640  * @param queues
1641  *   Queues entering in the indirection table.
1642  * @param queues_n
1643  *   Number of queues in the array.
1644  *
1645  * @return
1646  *   An indirection table if found.
1647  */
1648 static struct mlx5_ind_table_ibv *
1649 mlx5_ind_table_ibv_get(struct rte_eth_dev *dev, const uint16_t *queues,
1650                        uint32_t queues_n)
1651 {
1652         struct mlx5_priv *priv = dev->data->dev_private;
1653         struct mlx5_ind_table_ibv *ind_tbl;
1654
1655         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1656                 if ((ind_tbl->queues_n == queues_n) &&
1657                     (memcmp(ind_tbl->queues, queues,
1658                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1659                      == 0))
1660                         break;
1661         }
1662         if (ind_tbl) {
1663                 unsigned int i;
1664
1665                 rte_atomic32_inc(&ind_tbl->refcnt);
1666                 for (i = 0; i != ind_tbl->queues_n; ++i)
1667                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1668         }
1669         return ind_tbl;
1670 }
1671
1672 /**
1673  * Release an indirection table.
1674  *
1675  * @param dev
1676  *   Pointer to Ethernet device.
1677  * @param ind_table
1678  *   Indirection table to release.
1679  *
1680  * @return
1681  *   1 while a reference on it exists, 0 when freed.
1682  */
1683 static int
1684 mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
1685                            struct mlx5_ind_table_ibv *ind_tbl)
1686 {
1687         unsigned int i;
1688
1689         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1690                 claim_zero(mlx5_glue->destroy_rwq_ind_table
1691                            (ind_tbl->ind_table));
1692         for (i = 0; i != ind_tbl->queues_n; ++i)
1693                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1694         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1695                 LIST_REMOVE(ind_tbl, next);
1696                 rte_free(ind_tbl);
1697                 return 0;
1698         }
1699         return 1;
1700 }
1701
1702 /**
1703  * Verify the Rx Queue list is empty
1704  *
1705  * @param dev
1706  *   Pointer to Ethernet device.
1707  *
1708  * @return
1709  *   The number of object not released.
1710  */
1711 int
1712 mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev)
1713 {
1714         struct mlx5_priv *priv = dev->data->dev_private;
1715         struct mlx5_ind_table_ibv *ind_tbl;
1716         int ret = 0;
1717
1718         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1719                 DRV_LOG(DEBUG,
1720                         "port %u Verbs indirection table %p still referenced",
1721                         dev->data->port_id, (void *)ind_tbl);
1722                 ++ret;
1723         }
1724         return ret;
1725 }
1726
1727 /**
1728  * Create an Rx Hash queue.
1729  *
1730  * @param dev
1731  *   Pointer to Ethernet device.
1732  * @param rss_key
1733  *   RSS key for the Rx hash queue.
1734  * @param rss_key_len
1735  *   RSS key length.
1736  * @param hash_fields
1737  *   Verbs protocol hash field to make the RSS on.
1738  * @param queues
1739  *   Queues entering in hash queue. In case of empty hash_fields only the
1740  *   first queue index will be taken for the indirection table.
1741  * @param queues_n
1742  *   Number of queues.
1743  * @param tunnel
1744  *   Tunnel type.
1745  *
1746  * @return
1747  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1748  */
1749 struct mlx5_hrxq *
1750 mlx5_hrxq_new(struct rte_eth_dev *dev,
1751               const uint8_t *rss_key, uint32_t rss_key_len,
1752               uint64_t hash_fields,
1753               const uint16_t *queues, uint32_t queues_n,
1754               int tunnel __rte_unused)
1755 {
1756         struct mlx5_priv *priv = dev->data->dev_private;
1757         struct mlx5_hrxq *hrxq;
1758         struct mlx5_ind_table_ibv *ind_tbl;
1759         struct ibv_qp *qp;
1760 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1761         struct mlx5dv_qp_init_attr qp_init_attr;
1762 #endif
1763         int err;
1764
1765         queues_n = hash_fields ? queues_n : 1;
1766         ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1767         if (!ind_tbl)
1768                 ind_tbl = mlx5_ind_table_ibv_new(dev, queues, queues_n);
1769         if (!ind_tbl) {
1770                 rte_errno = ENOMEM;
1771                 return NULL;
1772         }
1773 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1774         memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1775         if (tunnel) {
1776                 qp_init_attr.comp_mask =
1777                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1778                 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1779         }
1780 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1781         if (dev->data->dev_conf.lpbk_mode) {
1782                 /* Allow packet sent from NIC loop back w/o source MAC check. */
1783                 qp_init_attr.comp_mask |=
1784                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1785                 qp_init_attr.create_flags |=
1786                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1787         }
1788 #endif
1789         qp = mlx5_glue->dv_create_qp
1790                 (priv->sh->ctx,
1791                  &(struct ibv_qp_init_attr_ex){
1792                         .qp_type = IBV_QPT_RAW_PACKET,
1793                         .comp_mask =
1794                                 IBV_QP_INIT_ATTR_PD |
1795                                 IBV_QP_INIT_ATTR_IND_TABLE |
1796                                 IBV_QP_INIT_ATTR_RX_HASH,
1797                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1798                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1799                                 .rx_hash_key_len = rss_key_len,
1800                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1801                                 .rx_hash_fields_mask = hash_fields,
1802                         },
1803                         .rwq_ind_tbl = ind_tbl->ind_table,
1804                         .pd = priv->sh->pd,
1805                  },
1806                  &qp_init_attr);
1807 #else
1808         qp = mlx5_glue->create_qp_ex
1809                 (priv->sh->ctx,
1810                  &(struct ibv_qp_init_attr_ex){
1811                         .qp_type = IBV_QPT_RAW_PACKET,
1812                         .comp_mask =
1813                                 IBV_QP_INIT_ATTR_PD |
1814                                 IBV_QP_INIT_ATTR_IND_TABLE |
1815                                 IBV_QP_INIT_ATTR_RX_HASH,
1816                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1817                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1818                                 .rx_hash_key_len = rss_key_len,
1819                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1820                                 .rx_hash_fields_mask = hash_fields,
1821                         },
1822                         .rwq_ind_tbl = ind_tbl->ind_table,
1823                         .pd = priv->sh->pd,
1824                  });
1825 #endif
1826         if (!qp) {
1827                 rte_errno = errno;
1828                 goto error;
1829         }
1830         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1831         if (!hrxq)
1832                 goto error;
1833         hrxq->ind_table = ind_tbl;
1834         hrxq->qp = qp;
1835         hrxq->rss_key_len = rss_key_len;
1836         hrxq->hash_fields = hash_fields;
1837         memcpy(hrxq->rss_key, rss_key, rss_key_len);
1838 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1839         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
1840         if (!hrxq->action) {
1841                 rte_errno = errno;
1842                 goto error;
1843         }
1844 #endif
1845         rte_atomic32_inc(&hrxq->refcnt);
1846         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1847         return hrxq;
1848 error:
1849         err = rte_errno; /* Save rte_errno before cleanup. */
1850         mlx5_ind_table_ibv_release(dev, ind_tbl);
1851         if (qp)
1852                 claim_zero(mlx5_glue->destroy_qp(qp));
1853         rte_errno = err; /* Restore rte_errno. */
1854         return NULL;
1855 }
1856
1857 /**
1858  * Get an Rx Hash queue.
1859  *
1860  * @param dev
1861  *   Pointer to Ethernet device.
1862  * @param rss_conf
1863  *   RSS configuration for the Rx hash queue.
1864  * @param queues
1865  *   Queues entering in hash queue. In case of empty hash_fields only the
1866  *   first queue index will be taken for the indirection table.
1867  * @param queues_n
1868  *   Number of queues.
1869  *
1870  * @return
1871  *   An hash Rx queue on success.
1872  */
1873 struct mlx5_hrxq *
1874 mlx5_hrxq_get(struct rte_eth_dev *dev,
1875               const uint8_t *rss_key, uint32_t rss_key_len,
1876               uint64_t hash_fields,
1877               const uint16_t *queues, uint32_t queues_n)
1878 {
1879         struct mlx5_priv *priv = dev->data->dev_private;
1880         struct mlx5_hrxq *hrxq;
1881
1882         queues_n = hash_fields ? queues_n : 1;
1883         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1884                 struct mlx5_ind_table_ibv *ind_tbl;
1885
1886                 if (hrxq->rss_key_len != rss_key_len)
1887                         continue;
1888                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1889                         continue;
1890                 if (hrxq->hash_fields != hash_fields)
1891                         continue;
1892                 ind_tbl = mlx5_ind_table_ibv_get(dev, queues, queues_n);
1893                 if (!ind_tbl)
1894                         continue;
1895                 if (ind_tbl != hrxq->ind_table) {
1896                         mlx5_ind_table_ibv_release(dev, ind_tbl);
1897                         continue;
1898                 }
1899                 rte_atomic32_inc(&hrxq->refcnt);
1900                 return hrxq;
1901         }
1902         return NULL;
1903 }
1904
1905 /**
1906  * Release the hash Rx queue.
1907  *
1908  * @param dev
1909  *   Pointer to Ethernet device.
1910  * @param hrxq
1911  *   Pointer to Hash Rx queue to release.
1912  *
1913  * @return
1914  *   1 while a reference on it exists, 0 when freed.
1915  */
1916 int
1917 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1918 {
1919         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1920 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1921                 mlx5_glue->destroy_flow_action(hrxq->action);
1922 #endif
1923                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1924                 mlx5_ind_table_ibv_release(dev, hrxq->ind_table);
1925                 LIST_REMOVE(hrxq, next);
1926                 rte_free(hrxq);
1927                 return 0;
1928         }
1929         claim_nonzero(mlx5_ind_table_ibv_release(dev, hrxq->ind_table));
1930         return 1;
1931 }
1932
1933 /**
1934  * Verify the Rx Queue list is empty
1935  *
1936  * @param dev
1937  *   Pointer to Ethernet device.
1938  *
1939  * @return
1940  *   The number of object not released.
1941  */
1942 int
1943 mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev)
1944 {
1945         struct mlx5_priv *priv = dev->data->dev_private;
1946         struct mlx5_hrxq *hrxq;
1947         int ret = 0;
1948
1949         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1950                 DRV_LOG(DEBUG,
1951                         "port %u Verbs hash Rx queue %p still referenced",
1952                         dev->data->port_id, (void *)hrxq);
1953                 ++ret;
1954         }
1955         return ret;
1956 }
1957
1958 /**
1959  * Create a drop Rx queue Verbs object.
1960  *
1961  * @param dev
1962  *   Pointer to Ethernet device.
1963  *
1964  * @return
1965  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1966  */
1967 static struct mlx5_rxq_ibv *
1968 mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev)
1969 {
1970         struct mlx5_priv *priv = dev->data->dev_private;
1971         struct ibv_context *ctx = priv->sh->ctx;
1972         struct ibv_cq *cq;
1973         struct ibv_wq *wq = NULL;
1974         struct mlx5_rxq_ibv *rxq;
1975
1976         if (priv->drop_queue.rxq)
1977                 return priv->drop_queue.rxq;
1978         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
1979         if (!cq) {
1980                 DEBUG("port %u cannot allocate CQ for drop queue",
1981                       dev->data->port_id);
1982                 rte_errno = errno;
1983                 goto error;
1984         }
1985         wq = mlx5_glue->create_wq(ctx,
1986                  &(struct ibv_wq_init_attr){
1987                         .wq_type = IBV_WQT_RQ,
1988                         .max_wr = 1,
1989                         .max_sge = 1,
1990                         .pd = priv->sh->pd,
1991                         .cq = cq,
1992                  });
1993         if (!wq) {
1994                 DEBUG("port %u cannot allocate WQ for drop queue",
1995                       dev->data->port_id);
1996                 rte_errno = errno;
1997                 goto error;
1998         }
1999         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2000         if (!rxq) {
2001                 DEBUG("port %u cannot allocate drop Rx queue memory",
2002                       dev->data->port_id);
2003                 rte_errno = ENOMEM;
2004                 goto error;
2005         }
2006         rxq->cq = cq;
2007         rxq->wq = wq;
2008         priv->drop_queue.rxq = rxq;
2009         return rxq;
2010 error:
2011         if (wq)
2012                 claim_zero(mlx5_glue->destroy_wq(wq));
2013         if (cq)
2014                 claim_zero(mlx5_glue->destroy_cq(cq));
2015         return NULL;
2016 }
2017
2018 /**
2019  * Release a drop Rx queue Verbs object.
2020  *
2021  * @param dev
2022  *   Pointer to Ethernet device.
2023  *
2024  * @return
2025  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2026  */
2027 static void
2028 mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev)
2029 {
2030         struct mlx5_priv *priv = dev->data->dev_private;
2031         struct mlx5_rxq_ibv *rxq = priv->drop_queue.rxq;
2032
2033         if (rxq->wq)
2034                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2035         if (rxq->cq)
2036                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2037         rte_free(rxq);
2038         priv->drop_queue.rxq = NULL;
2039 }
2040
2041 /**
2042  * Create a drop indirection table.
2043  *
2044  * @param dev
2045  *   Pointer to Ethernet device.
2046  *
2047  * @return
2048  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2049  */
2050 static struct mlx5_ind_table_ibv *
2051 mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev)
2052 {
2053         struct mlx5_priv *priv = dev->data->dev_private;
2054         struct mlx5_ind_table_ibv *ind_tbl;
2055         struct mlx5_rxq_ibv *rxq;
2056         struct mlx5_ind_table_ibv tmpl;
2057
2058         rxq = mlx5_rxq_ibv_drop_new(dev);
2059         if (!rxq)
2060                 return NULL;
2061         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2062                 (priv->sh->ctx,
2063                  &(struct ibv_rwq_ind_table_init_attr){
2064                         .log_ind_tbl_size = 0,
2065                         .ind_tbl = &rxq->wq,
2066                         .comp_mask = 0,
2067                  });
2068         if (!tmpl.ind_table) {
2069                 DEBUG("port %u cannot allocate indirection table for drop"
2070                       " queue",
2071                       dev->data->port_id);
2072                 rte_errno = errno;
2073                 goto error;
2074         }
2075         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2076         if (!ind_tbl) {
2077                 rte_errno = ENOMEM;
2078                 goto error;
2079         }
2080         ind_tbl->ind_table = tmpl.ind_table;
2081         return ind_tbl;
2082 error:
2083         mlx5_rxq_ibv_drop_release(dev);
2084         return NULL;
2085 }
2086
2087 /**
2088  * Release a drop indirection table.
2089  *
2090  * @param dev
2091  *   Pointer to Ethernet device.
2092  */
2093 static void
2094 mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev)
2095 {
2096         struct mlx5_priv *priv = dev->data->dev_private;
2097         struct mlx5_ind_table_ibv *ind_tbl = priv->drop_queue.hrxq->ind_table;
2098
2099         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2100         mlx5_rxq_ibv_drop_release(dev);
2101         rte_free(ind_tbl);
2102         priv->drop_queue.hrxq->ind_table = NULL;
2103 }
2104
2105 /**
2106  * Create a drop Rx Hash queue.
2107  *
2108  * @param dev
2109  *   Pointer to Ethernet device.
2110  *
2111  * @return
2112  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
2113  */
2114 struct mlx5_hrxq *
2115 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2116 {
2117         struct mlx5_priv *priv = dev->data->dev_private;
2118         struct mlx5_ind_table_ibv *ind_tbl;
2119         struct ibv_qp *qp;
2120         struct mlx5_hrxq *hrxq;
2121
2122         if (priv->drop_queue.hrxq) {
2123                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2124                 return priv->drop_queue.hrxq;
2125         }
2126         ind_tbl = mlx5_ind_table_ibv_drop_new(dev);
2127         if (!ind_tbl)
2128                 return NULL;
2129         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2130                  &(struct ibv_qp_init_attr_ex){
2131                         .qp_type = IBV_QPT_RAW_PACKET,
2132                         .comp_mask =
2133                                 IBV_QP_INIT_ATTR_PD |
2134                                 IBV_QP_INIT_ATTR_IND_TABLE |
2135                                 IBV_QP_INIT_ATTR_RX_HASH,
2136                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2137                                 .rx_hash_function =
2138                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2139                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2140                                 .rx_hash_key = rss_hash_default_key,
2141                                 .rx_hash_fields_mask = 0,
2142                                 },
2143                         .rwq_ind_tbl = ind_tbl->ind_table,
2144                         .pd = priv->sh->pd
2145                  });
2146         if (!qp) {
2147                 DEBUG("port %u cannot allocate QP for drop queue",
2148                       dev->data->port_id);
2149                 rte_errno = errno;
2150                 goto error;
2151         }
2152         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2153         if (!hrxq) {
2154                 DRV_LOG(WARNING,
2155                         "port %u cannot allocate memory for drop queue",
2156                         dev->data->port_id);
2157                 rte_errno = ENOMEM;
2158                 goto error;
2159         }
2160         hrxq->ind_table = ind_tbl;
2161         hrxq->qp = qp;
2162 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2163         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2164         if (!hrxq->action) {
2165                 rte_errno = errno;
2166                 goto error;
2167         }
2168 #endif
2169         priv->drop_queue.hrxq = hrxq;
2170         rte_atomic32_set(&hrxq->refcnt, 1);
2171         return hrxq;
2172 error:
2173         if (ind_tbl)
2174                 mlx5_ind_table_ibv_drop_release(dev);
2175         return NULL;
2176 }
2177
2178 /**
2179  * Release a drop hash Rx queue.
2180  *
2181  * @param dev
2182  *   Pointer to Ethernet device.
2183  */
2184 void
2185 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2186 {
2187         struct mlx5_priv *priv = dev->data->dev_private;
2188         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2189
2190         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2191 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2192                 mlx5_glue->destroy_flow_action(hrxq->action);
2193 #endif
2194                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2195                 mlx5_ind_table_ibv_drop_release(dev);
2196                 rte_free(hrxq);
2197                 priv->drop_queue.hrxq = NULL;
2198         }
2199 }