1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_malloc.h>
26 #include <rte_ethdev_driver.h>
27 #include <rte_common.h>
28 #include <rte_interrupts.h>
29 #include <rte_debug.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
34 #include <mlx5_malloc.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_common_os.h"
39 #include "mlx5_rxtx.h"
40 #include "mlx5_utils.h"
41 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
45 /* Default RSS hash key also used for ConnectX-3. */
46 uint8_t rss_hash_default_key[] = {
47 0x2c, 0xc6, 0x81, 0xd1,
48 0x5b, 0xdb, 0xf4, 0xf7,
49 0xfc, 0xa2, 0x83, 0x19,
50 0xdb, 0x1a, 0x3e, 0x94,
51 0x6b, 0x9e, 0x38, 0xd9,
52 0x2c, 0x9c, 0x03, 0xd1,
53 0xad, 0x99, 0x44, 0xa7,
54 0xd9, 0x56, 0x3d, 0x59,
55 0x06, 0x3c, 0x25, 0xf3,
56 0xfc, 0x1f, 0xdc, 0x2a,
59 /* Length of the default RSS hash key. */
60 static_assert(MLX5_RSS_HASH_KEY_LEN ==
61 (unsigned int)sizeof(rss_hash_default_key),
62 "wrong RSS default key size.");
65 * Check whether Multi-Packet RQ can be enabled for the device.
68 * Pointer to Ethernet device.
71 * 1 if supported, negative errno value if not.
74 mlx5_check_mprq_support(struct rte_eth_dev *dev)
76 struct mlx5_priv *priv = dev->data->dev_private;
78 if (priv->config.mprq.enabled &&
79 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
85 * Check whether Multi-Packet RQ is enabled for the Rx queue.
88 * Pointer to receive queue structure.
91 * 0 if disabled, otherwise enabled.
94 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
96 return rxq->strd_num_n > 0;
100 * Check whether Multi-Packet RQ is enabled for the device.
103 * Pointer to Ethernet device.
106 * 0 if disabled, otherwise enabled.
109 mlx5_mprq_enabled(struct rte_eth_dev *dev)
111 struct mlx5_priv *priv = dev->data->dev_private;
116 if (mlx5_check_mprq_support(dev) < 0)
118 /* All the configured queues should be enabled. */
119 for (i = 0; i < priv->rxqs_n; ++i) {
120 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
121 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
122 (rxq, struct mlx5_rxq_ctrl, rxq);
124 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
127 if (mlx5_rxq_mprq_enabled(rxq))
130 /* Multi-Packet RQ can't be partially configured. */
131 MLX5_ASSERT(n == 0 || n == n_ibv);
136 * Allocate RX queue elements for Multi-Packet RQ.
139 * Pointer to RX queue structure.
142 * 0 on success, a negative errno value otherwise and rte_errno is set.
145 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
147 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
148 unsigned int wqe_n = 1 << rxq->elts_n;
152 /* Iterate on segments. */
153 for (i = 0; i <= wqe_n; ++i) {
154 struct mlx5_mprq_buf *buf;
156 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
157 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
162 (*rxq->mprq_bufs)[i] = buf;
164 rxq->mprq_repl = buf;
167 "port %u Rx queue %u allocated and configured %u segments",
168 rxq->port_id, rxq->idx, wqe_n);
171 err = rte_errno; /* Save rte_errno before cleanup. */
173 for (i = 0; (i != wqe_n); ++i) {
174 if ((*rxq->mprq_bufs)[i] != NULL)
175 rte_mempool_put(rxq->mprq_mp,
176 (*rxq->mprq_bufs)[i]);
177 (*rxq->mprq_bufs)[i] = NULL;
179 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
180 rxq->port_id, rxq->idx);
181 rte_errno = err; /* Restore rte_errno. */
186 * Allocate RX queue elements for Single-Packet RQ.
189 * Pointer to RX queue structure.
192 * 0 on success, errno value on failure.
195 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
197 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
198 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
202 /* Iterate on segments. */
203 for (i = 0; (i != elts_n); ++i) {
204 struct rte_mbuf *buf;
206 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
208 DRV_LOG(ERR, "port %u empty mbuf pool",
209 PORT_ID(rxq_ctrl->priv));
213 /* Headroom is reserved by rte_pktmbuf_alloc(). */
214 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
215 /* Buffer is supposed to be empty. */
216 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
217 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
218 MLX5_ASSERT(!buf->next);
219 /* Only the first segment keeps headroom. */
221 SET_DATA_OFF(buf, 0);
222 PORT(buf) = rxq_ctrl->rxq.port_id;
223 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
224 PKT_LEN(buf) = DATA_LEN(buf);
226 (*rxq_ctrl->rxq.elts)[i] = buf;
228 /* If Rx vector is activated. */
229 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
230 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
231 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
232 struct rte_pktmbuf_pool_private *priv =
233 (struct rte_pktmbuf_pool_private *)
234 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
237 /* Initialize default rearm_data for vPMD. */
238 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
239 rte_mbuf_refcnt_set(mbuf_init, 1);
240 mbuf_init->nb_segs = 1;
241 mbuf_init->port = rxq->port_id;
242 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
243 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
245 * prevent compiler reordering:
246 * rearm_data covers previous fields.
248 rte_compiler_barrier();
249 rxq->mbuf_initializer =
250 *(rte_xmm_t *)&mbuf_init->rearm_data;
251 /* Padding with a fake mbuf for vectorized Rx. */
252 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
253 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
256 "port %u Rx queue %u allocated and configured %u segments"
258 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
259 elts_n / (1 << rxq_ctrl->rxq.sges_n));
262 err = rte_errno; /* Save rte_errno before cleanup. */
264 for (i = 0; (i != elts_n); ++i) {
265 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
266 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
267 (*rxq_ctrl->rxq.elts)[i] = NULL;
269 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
270 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
271 rte_errno = err; /* Restore rte_errno. */
276 * Allocate RX queue elements.
279 * Pointer to RX queue structure.
282 * 0 on success, errno value on failure.
285 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
287 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
288 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
292 * Free RX queue elements for Multi-Packet RQ.
295 * Pointer to RX queue structure.
298 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
300 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
303 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
304 rxq->port_id, rxq->idx);
305 if (rxq->mprq_bufs == NULL)
307 MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
308 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
309 if ((*rxq->mprq_bufs)[i] != NULL)
310 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
311 (*rxq->mprq_bufs)[i] = NULL;
313 if (rxq->mprq_repl != NULL) {
314 mlx5_mprq_buf_free(rxq->mprq_repl);
315 rxq->mprq_repl = NULL;
320 * Free RX queue elements for Single-Packet RQ.
323 * Pointer to RX queue structure.
326 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
328 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
329 const uint16_t q_n = (1 << rxq->elts_n);
330 const uint16_t q_mask = q_n - 1;
331 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
334 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
335 PORT_ID(rxq_ctrl->priv), rxq->idx);
336 if (rxq->elts == NULL)
339 * Some mbuf in the Ring belongs to the application. They cannot be
342 if (mlx5_rxq_check_vec_support(rxq) > 0) {
343 for (i = 0; i < used; ++i)
344 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
345 rxq->rq_pi = rxq->rq_ci;
347 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
348 if ((*rxq->elts)[i] != NULL)
349 rte_pktmbuf_free_seg((*rxq->elts)[i]);
350 (*rxq->elts)[i] = NULL;
355 * Free RX queue elements.
358 * Pointer to RX queue structure.
361 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
363 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
364 rxq_free_elts_mprq(rxq_ctrl);
366 rxq_free_elts_sprq(rxq_ctrl);
370 * Returns the per-queue supported offloads.
373 * Pointer to Ethernet device.
376 * Supported Rx offloads.
379 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
381 struct mlx5_priv *priv = dev->data->dev_private;
382 struct mlx5_dev_config *config = &priv->config;
383 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
384 DEV_RX_OFFLOAD_TIMESTAMP |
385 DEV_RX_OFFLOAD_JUMBO_FRAME |
386 DEV_RX_OFFLOAD_RSS_HASH);
388 if (config->hw_fcs_strip)
389 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
392 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
393 DEV_RX_OFFLOAD_UDP_CKSUM |
394 DEV_RX_OFFLOAD_TCP_CKSUM);
395 if (config->hw_vlan_strip)
396 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
397 if (MLX5_LRO_SUPPORTED(dev))
398 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
404 * Returns the per-port supported offloads.
407 * Supported Rx offloads.
410 mlx5_get_rx_port_offloads(void)
412 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
418 * Verify if the queue can be released.
421 * Pointer to Ethernet device.
426 * 1 if the queue can be released
427 * 0 if the queue can not be released, there are references to it.
428 * Negative errno and rte_errno is set if queue doesn't exist.
431 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
433 struct mlx5_priv *priv = dev->data->dev_private;
434 struct mlx5_rxq_ctrl *rxq_ctrl;
436 if (!(*priv->rxqs)[idx]) {
440 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
441 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
445 * Rx queue presetup checks.
448 * Pointer to Ethernet device structure.
452 * Number of descriptors to configure in queue.
455 * 0 on success, a negative errno value otherwise and rte_errno is set.
458 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
460 struct mlx5_priv *priv = dev->data->dev_private;
462 if (!rte_is_power_of_2(*desc)) {
463 *desc = 1 << log2above(*desc);
465 "port %u increased number of descriptors in Rx queue %u"
466 " to the next power of two (%d)",
467 dev->data->port_id, idx, *desc);
469 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
470 dev->data->port_id, idx, *desc);
471 if (idx >= priv->rxqs_n) {
472 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
473 dev->data->port_id, idx, priv->rxqs_n);
474 rte_errno = EOVERFLOW;
477 if (!mlx5_rxq_releasable(dev, idx)) {
478 DRV_LOG(ERR, "port %u unable to release queue index %u",
479 dev->data->port_id, idx);
483 mlx5_rxq_release(dev, idx);
490 * Pointer to Ethernet device structure.
494 * Number of descriptors to configure in queue.
496 * NUMA socket on which memory must be allocated.
498 * Thresholds parameters.
500 * Memory pool for buffer allocations.
503 * 0 on success, a negative errno value otherwise and rte_errno is set.
506 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
507 unsigned int socket, const struct rte_eth_rxconf *conf,
508 struct rte_mempool *mp)
510 struct mlx5_priv *priv = dev->data->dev_private;
511 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
512 struct mlx5_rxq_ctrl *rxq_ctrl =
513 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
516 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
519 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
521 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
522 dev->data->port_id, idx);
526 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
527 dev->data->port_id, idx);
528 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
535 * Pointer to Ethernet device structure.
539 * Number of descriptors to configure in queue.
540 * @param hairpin_conf
541 * Hairpin configuration parameters.
544 * 0 on success, a negative errno value otherwise and rte_errno is set.
547 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
549 const struct rte_eth_hairpin_conf *hairpin_conf)
551 struct mlx5_priv *priv = dev->data->dev_private;
552 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
553 struct mlx5_rxq_ctrl *rxq_ctrl =
554 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
557 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
560 if (hairpin_conf->peer_count != 1 ||
561 hairpin_conf->peers[0].port != dev->data->port_id ||
562 hairpin_conf->peers[0].queue >= priv->txqs_n) {
563 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
564 " invalid hairpind configuration", dev->data->port_id,
569 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
571 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
572 dev->data->port_id, idx);
576 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
577 dev->data->port_id, idx);
578 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
583 * DPDK callback to release a RX queue.
586 * Generic RX queue pointer.
589 mlx5_rx_queue_release(void *dpdk_rxq)
591 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
592 struct mlx5_rxq_ctrl *rxq_ctrl;
593 struct mlx5_priv *priv;
597 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
598 priv = rxq_ctrl->priv;
599 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
600 rte_panic("port %u Rx queue %u is still used by a flow and"
601 " cannot be removed\n",
602 PORT_ID(priv), rxq->idx);
603 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
607 * Get an Rx queue Verbs/DevX object.
610 * Pointer to Ethernet device.
612 * Queue index in DPDK Rx queue array
615 * The Verbs/DevX object if it exists.
617 static struct mlx5_rxq_obj *
618 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
620 struct mlx5_priv *priv = dev->data->dev_private;
621 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
622 struct mlx5_rxq_ctrl *rxq_ctrl;
624 if (idx >= priv->rxqs_n)
628 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
630 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
631 return rxq_ctrl->obj;
635 * Release the resources allocated for an RQ DevX object.
638 * DevX Rx queue object.
641 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
643 if (rxq_ctrl->rxq.wqes) {
644 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
645 rxq_ctrl->rxq.wqes = NULL;
647 if (rxq_ctrl->wq_umem) {
648 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
649 rxq_ctrl->wq_umem = NULL;
654 * Release an Rx hairpin related resources.
657 * Hairpin Rx queue object.
660 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
662 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
664 MLX5_ASSERT(rxq_obj);
665 rq_attr.state = MLX5_RQC_STATE_RST;
666 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
667 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
668 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
672 * Release an Rx verbs/DevX queue object.
675 * Verbs/DevX Rx queue object.
678 * 1 while a reference on it exists, 0 when freed.
681 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
683 MLX5_ASSERT(rxq_obj);
684 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
685 switch (rxq_obj->type) {
686 case MLX5_RXQ_OBJ_TYPE_IBV:
687 MLX5_ASSERT(rxq_obj->wq);
688 MLX5_ASSERT(rxq_obj->cq);
689 rxq_free_elts(rxq_obj->rxq_ctrl);
690 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
691 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
693 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
694 MLX5_ASSERT(rxq_obj->cq);
695 MLX5_ASSERT(rxq_obj->rq);
696 rxq_free_elts(rxq_obj->rxq_ctrl);
697 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
698 rxq_release_rq_resources(rxq_obj->rxq_ctrl);
699 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
701 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
702 MLX5_ASSERT(rxq_obj->rq);
703 rxq_obj_hairpin_release(rxq_obj);
706 if (rxq_obj->channel)
707 claim_zero(mlx5_glue->destroy_comp_channel
709 LIST_REMOVE(rxq_obj, next);
717 * Allocate queue vector and fill epoll fd list for Rx interrupts.
720 * Pointer to Ethernet device.
723 * 0 on success, a negative errno value otherwise and rte_errno is set.
726 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
728 struct mlx5_priv *priv = dev->data->dev_private;
730 unsigned int rxqs_n = priv->rxqs_n;
731 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
732 unsigned int count = 0;
733 struct rte_intr_handle *intr_handle = dev->intr_handle;
735 if (!dev->data->dev_conf.intr_conf.rxq)
737 mlx5_rx_intr_vec_disable(dev);
738 intr_handle->intr_vec = mlx5_malloc(0,
739 n * sizeof(intr_handle->intr_vec[0]),
741 if (intr_handle->intr_vec == NULL) {
743 "port %u failed to allocate memory for interrupt"
744 " vector, Rx interrupts will not be supported",
749 intr_handle->type = RTE_INTR_HANDLE_EXT;
750 for (i = 0; i != n; ++i) {
751 /* This rxq obj must not be released in this function. */
752 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
757 /* Skip queues that cannot request interrupts. */
758 if (!rxq_obj || !rxq_obj->channel) {
759 /* Use invalid intr_vec[] index to disable entry. */
760 intr_handle->intr_vec[i] =
761 RTE_INTR_VEC_RXTX_OFFSET +
762 RTE_MAX_RXTX_INTR_VEC_ID;
765 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
767 "port %u too many Rx queues for interrupt"
768 " vector size (%d), Rx interrupts cannot be"
770 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
771 mlx5_rx_intr_vec_disable(dev);
775 fd = rxq_obj->channel->fd;
776 flags = fcntl(fd, F_GETFL);
777 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
781 "port %u failed to make Rx interrupt file"
782 " descriptor %d non-blocking for queue index"
784 dev->data->port_id, fd, i);
785 mlx5_rx_intr_vec_disable(dev);
788 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
789 intr_handle->efds[count] = fd;
793 mlx5_rx_intr_vec_disable(dev);
795 intr_handle->nb_efd = count;
800 * Clean up Rx interrupts handler.
803 * Pointer to Ethernet device.
806 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
808 struct mlx5_priv *priv = dev->data->dev_private;
809 struct rte_intr_handle *intr_handle = dev->intr_handle;
811 unsigned int rxqs_n = priv->rxqs_n;
812 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
814 if (!dev->data->dev_conf.intr_conf.rxq)
816 if (!intr_handle->intr_vec)
818 for (i = 0; i != n; ++i) {
819 struct mlx5_rxq_ctrl *rxq_ctrl;
820 struct mlx5_rxq_data *rxq_data;
822 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
823 RTE_MAX_RXTX_INTR_VEC_ID)
826 * Need to access directly the queue to release the reference
827 * kept in mlx5_rx_intr_vec_enable().
829 rxq_data = (*priv->rxqs)[i];
830 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
832 mlx5_rxq_obj_release(rxq_ctrl->obj);
835 rte_intr_free_epoll_fd(intr_handle);
836 if (intr_handle->intr_vec)
837 mlx5_free(intr_handle->intr_vec);
838 intr_handle->nb_efd = 0;
839 intr_handle->intr_vec = NULL;
843 * MLX5 CQ notification .
846 * Pointer to receive queue structure.
848 * Sequence number per receive queue .
851 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
854 uint32_t doorbell_hi;
856 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
858 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
859 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
860 doorbell = (uint64_t)doorbell_hi << 32;
861 doorbell |= rxq->cqn;
862 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
863 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
864 cq_db_reg, rxq->uar_lock_cq);
868 * DPDK callback for Rx queue interrupt enable.
871 * Pointer to Ethernet device structure.
876 * 0 on success, a negative errno value otherwise and rte_errno is set.
879 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
881 struct mlx5_priv *priv = dev->data->dev_private;
882 struct mlx5_rxq_data *rxq_data;
883 struct mlx5_rxq_ctrl *rxq_ctrl;
885 rxq_data = (*priv->rxqs)[rx_queue_id];
890 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
892 struct mlx5_rxq_obj *rxq_obj;
894 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
899 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
900 mlx5_rxq_obj_release(rxq_obj);
906 * DPDK callback for Rx queue interrupt disable.
909 * Pointer to Ethernet device structure.
914 * 0 on success, a negative errno value otherwise and rte_errno is set.
917 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
919 struct mlx5_priv *priv = dev->data->dev_private;
920 struct mlx5_rxq_data *rxq_data;
921 struct mlx5_rxq_ctrl *rxq_ctrl;
922 struct mlx5_rxq_obj *rxq_obj = NULL;
923 struct ibv_cq *ev_cq;
927 rxq_data = (*priv->rxqs)[rx_queue_id];
932 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
935 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
940 ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
941 if (ret || ev_cq != rxq_obj->cq) {
945 rxq_data->cq_arm_sn++;
946 mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
947 mlx5_rxq_obj_release(rxq_obj);
950 ret = rte_errno; /* Save rte_errno before cleanup. */
952 mlx5_rxq_obj_release(rxq_obj);
953 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
954 dev->data->port_id, rx_queue_id);
955 rte_errno = ret; /* Restore rte_errno. */
960 * Create a CQ Verbs object.
963 * Pointer to Ethernet device.
965 * Pointer to device private data.
967 * Pointer to Rx queue data.
969 * Number of CQEs in CQ.
971 * Pointer to Rx queue object data.
974 * The Verbs object initialised, NULL otherwise and rte_errno is set.
976 static struct ibv_cq *
977 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
978 struct mlx5_rxq_data *rxq_data,
979 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
982 struct ibv_cq_init_attr_ex ibv;
983 struct mlx5dv_cq_init_attr mlx5;
986 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
988 .channel = rxq_obj->channel,
991 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
994 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
996 cq_attr.mlx5.comp_mask |=
997 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
998 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
999 cq_attr.mlx5.cqe_comp_res_format =
1000 mlx5_rxq_mprq_enabled(rxq_data) ?
1001 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1002 MLX5DV_CQE_RES_FORMAT_HASH;
1004 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1007 * For vectorized Rx, it must not be doubled in order to
1008 * make cq_ci and rq_ci aligned.
1010 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1011 cq_attr.ibv.cqe *= 2;
1012 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1014 "port %u Rx CQE compression is disabled for HW"
1016 dev->data->port_id);
1017 } else if (priv->config.cqe_comp && rxq_data->lro) {
1019 "port %u Rx CQE compression is disabled for LRO",
1020 dev->data->port_id);
1022 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1023 if (priv->config.cqe_pad) {
1024 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1025 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1028 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1034 * Create a WQ Verbs object.
1037 * Pointer to Ethernet device.
1039 * Pointer to device private data.
1041 * Pointer to Rx queue data.
1043 * Queue index in DPDK Rx queue array
1045 * Number of WQEs in WQ.
1047 * Pointer to Rx queue object data.
1050 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1052 static struct ibv_wq *
1053 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1054 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1055 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1058 struct ibv_wq_init_attr ibv;
1059 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1060 struct mlx5dv_wq_init_attr mlx5;
1064 wq_attr.ibv = (struct ibv_wq_init_attr){
1065 .wq_context = NULL, /* Could be useful in the future. */
1066 .wq_type = IBV_WQT_RQ,
1067 /* Max number of outstanding WRs. */
1068 .max_wr = wqe_n >> rxq_data->sges_n,
1069 /* Max number of scatter/gather elements in a WR. */
1070 .max_sge = 1 << rxq_data->sges_n,
1073 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1074 .create_flags = (rxq_data->vlan_strip ?
1075 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1077 /* By default, FCS (CRC) is stripped by hardware. */
1078 if (rxq_data->crc_present) {
1079 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1080 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1082 if (priv->config.hw_padding) {
1083 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1084 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1085 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1086 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1087 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1088 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1091 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1092 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1095 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1096 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1097 &wq_attr.mlx5.striding_rq_attrs;
1099 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1100 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1101 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1102 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1103 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1106 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1109 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1113 * Make sure number of WRs*SGEs match expectations since a queue
1114 * cannot allocate more than "desc" buffers.
1116 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1117 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1119 "port %u Rx queue %u requested %u*%u but got"
1121 dev->data->port_id, idx,
1122 wqe_n >> rxq_data->sges_n,
1123 (1 << rxq_data->sges_n),
1124 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1125 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1134 * Fill common fields of create RQ attributes structure.
1137 * Pointer to Rx queue data.
1139 * CQ number to use with this RQ.
1141 * RQ attributes structure to fill..
1144 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1145 struct mlx5_devx_create_rq_attr *rq_attr)
1147 rq_attr->state = MLX5_RQC_STATE_RST;
1148 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1150 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1154 * Fill common fields of DevX WQ attributes structure.
1157 * Pointer to device private data.
1159 * Pointer to Rx queue control structure.
1161 * WQ attributes structure to fill..
1164 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1165 struct mlx5_devx_wq_attr *wq_attr)
1167 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1168 MLX5_WQ_END_PAD_MODE_ALIGN :
1169 MLX5_WQ_END_PAD_MODE_NONE;
1170 wq_attr->pd = priv->sh->pdn;
1171 wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1172 wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1173 wq_attr->dbr_umem_valid = 1;
1174 wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1175 wq_attr->wq_umem_valid = 1;
1179 * Create a RQ object using DevX.
1182 * Pointer to Ethernet device.
1184 * Queue index in DPDK Rx queue array
1186 * CQ number to use with this RQ.
1189 * The DevX object initialised, NULL otherwise and rte_errno is set.
1191 static struct mlx5_devx_obj *
1192 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1194 struct mlx5_priv *priv = dev->data->dev_private;
1195 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1196 struct mlx5_rxq_ctrl *rxq_ctrl =
1197 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1198 struct mlx5_devx_create_rq_attr rq_attr;
1199 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1200 uint32_t wq_size = 0;
1201 uint32_t wqe_size = 0;
1202 uint32_t log_wqe_size = 0;
1204 struct mlx5_devx_obj *rq;
1206 memset(&rq_attr, 0, sizeof(rq_attr));
1207 /* Fill RQ attributes. */
1208 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1209 rq_attr.flush_in_error_en = 1;
1210 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1211 /* Fill WQ attributes for this RQ. */
1212 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1213 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1215 * Number of strides in each WQE:
1216 * 512*2^single_wqe_log_num_of_strides.
1218 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1219 rxq_data->strd_num_n -
1220 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1221 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1222 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1223 rxq_data->strd_sz_n -
1224 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1225 wqe_size = sizeof(struct mlx5_wqe_mprq);
1227 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1228 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1230 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1231 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1232 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1233 /* Calculate and allocate WQ memory space. */
1234 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1235 wq_size = wqe_n * wqe_size;
1236 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
1237 MLX5_WQE_BUF_ALIGNMENT, rxq_ctrl->socket);
1240 rxq_data->wqes = buf;
1241 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1243 if (!rxq_ctrl->wq_umem) {
1247 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1248 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1250 rxq_release_rq_resources(rxq_ctrl);
1255 * Create the Rx hairpin queue object.
1258 * Pointer to Ethernet device.
1260 * Queue index in DPDK Rx queue array
1263 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1265 static struct mlx5_rxq_obj *
1266 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1268 struct mlx5_priv *priv = dev->data->dev_private;
1269 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1270 struct mlx5_rxq_ctrl *rxq_ctrl =
1271 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1272 struct mlx5_devx_create_rq_attr attr = { 0 };
1273 struct mlx5_rxq_obj *tmpl = NULL;
1274 uint32_t max_wq_data;
1276 MLX5_ASSERT(rxq_data);
1277 MLX5_ASSERT(!rxq_ctrl->obj);
1278 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1282 "port %u Rx queue %u cannot allocate verbs resources",
1283 dev->data->port_id, rxq_data->idx);
1287 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1288 tmpl->rxq_ctrl = rxq_ctrl;
1290 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1291 /* Jumbo frames > 9KB should be supported, and more packets. */
1292 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1293 if (priv->config.log_hp_size > max_wq_data) {
1294 DRV_LOG(ERR, "total data size %u power of 2 is "
1295 "too large for hairpin",
1296 priv->config.log_hp_size);
1301 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1303 attr.wq_attr.log_hairpin_data_sz =
1304 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1305 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1307 /* Set the packets number to the maximum value for performance. */
1308 attr.wq_attr.log_hairpin_num_packets =
1309 attr.wq_attr.log_hairpin_data_sz -
1310 MLX5_HAIRPIN_QUEUE_STRIDE;
1311 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1315 "port %u Rx hairpin queue %u can't create rq object",
1316 dev->data->port_id, idx);
1321 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1322 idx, (void *)&tmpl);
1323 rte_atomic32_inc(&tmpl->refcnt);
1324 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1325 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1330 * Create the Rx queue Verbs/DevX object.
1333 * Pointer to Ethernet device.
1335 * Queue index in DPDK Rx queue array
1337 * Type of Rx queue object to create.
1340 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1342 struct mlx5_rxq_obj *
1343 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1344 enum mlx5_rxq_obj_type type)
1346 struct mlx5_priv *priv = dev->data->dev_private;
1347 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1348 struct mlx5_rxq_ctrl *rxq_ctrl =
1349 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1350 struct ibv_wq_attr mod;
1352 unsigned int wqe_n = 1 << rxq_data->elts_n;
1353 struct mlx5_rxq_obj *tmpl = NULL;
1354 struct mlx5dv_cq cq_info;
1355 struct mlx5dv_rwq rwq;
1357 struct mlx5dv_obj obj;
1359 MLX5_ASSERT(rxq_data);
1360 MLX5_ASSERT(!rxq_ctrl->obj);
1361 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1362 return mlx5_rxq_obj_hairpin_new(dev, idx);
1363 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1364 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1365 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1369 "port %u Rx queue %u cannot allocate verbs resources",
1370 dev->data->port_id, rxq_data->idx);
1375 tmpl->rxq_ctrl = rxq_ctrl;
1376 if (rxq_ctrl->irq) {
1377 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1378 if (!tmpl->channel) {
1379 DRV_LOG(ERR, "port %u: comp channel creation failure",
1380 dev->data->port_id);
1385 if (mlx5_rxq_mprq_enabled(rxq_data))
1386 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1389 tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1391 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1392 dev->data->port_id, idx);
1396 obj.cq.in = tmpl->cq;
1397 obj.cq.out = &cq_info;
1398 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1403 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1405 "port %u wrong MLX5_CQE_SIZE environment variable"
1406 " value: it should be set to %u",
1407 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1411 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1412 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1413 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1414 dev->data->port_id, priv->sh->device_attr.max_sge);
1415 /* Allocate door-bell for types created with DevX. */
1416 if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1417 struct mlx5_devx_dbr_page *dbr_page;
1420 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1424 rxq_ctrl->dbr_offset = dbr_offset;
1425 rxq_ctrl->dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1426 rxq_ctrl->dbr_umem_id_valid = 1;
1427 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1428 (uintptr_t)rxq_ctrl->dbr_offset);
1430 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1431 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1434 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1435 dev->data->port_id, idx);
1439 /* Change queue state to ready. */
1440 mod = (struct ibv_wq_attr){
1441 .attr_mask = IBV_WQ_ATTR_STATE,
1442 .wq_state = IBV_WQS_RDY,
1444 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1447 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1448 " failed", dev->data->port_id, idx);
1452 obj.rwq.in = tmpl->wq;
1454 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1459 rxq_data->wqes = rwq.buf;
1460 rxq_data->rq_db = rwq.dbrec;
1461 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1462 struct mlx5_devx_modify_rq_attr rq_attr;
1464 memset(&rq_attr, 0, sizeof(rq_attr));
1465 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1467 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1468 dev->data->port_id, idx);
1472 /* Change queue state to ready. */
1473 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1474 rq_attr.state = MLX5_RQC_STATE_RDY;
1475 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1479 /* Fill the rings. */
1480 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1481 rxq_data->cq_db = cq_info.dbrec;
1482 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1483 rxq_data->cq_uar = cq_info.cq_uar;
1484 rxq_data->cqn = cq_info.cqn;
1485 rxq_data->cq_arm_sn = 0;
1486 mlx5_rxq_initialize(rxq_data);
1487 rxq_data->cq_ci = 0;
1488 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1489 idx, (void *)&tmpl);
1490 rte_atomic32_inc(&tmpl->refcnt);
1491 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1492 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1496 ret = rte_errno; /* Save rte_errno before cleanup. */
1497 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1498 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1499 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1500 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1502 claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1504 claim_zero(mlx5_glue->destroy_comp_channel
1507 rte_errno = ret; /* Restore rte_errno. */
1509 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1510 rxq_release_rq_resources(rxq_ctrl);
1511 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1516 * Verify the Rx queue objects list is empty
1519 * Pointer to Ethernet device.
1522 * The number of objects not released.
1525 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1527 struct mlx5_priv *priv = dev->data->dev_private;
1529 struct mlx5_rxq_obj *rxq_obj;
1531 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1532 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1533 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1540 * Callback function to initialize mbufs for Multi-Packet RQ.
1543 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1544 void *_m, unsigned int i __rte_unused)
1546 struct mlx5_mprq_buf *buf = _m;
1547 struct rte_mbuf_ext_shared_info *shinfo;
1548 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1551 memset(_m, 0, sizeof(*buf));
1553 rte_atomic16_set(&buf->refcnt, 1);
1554 for (j = 0; j != strd_n; ++j) {
1555 shinfo = &buf->shinfos[j];
1556 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1557 shinfo->fcb_opaque = buf;
1562 * Free mempool of Multi-Packet RQ.
1565 * Pointer to Ethernet device.
1568 * 0 on success, negative errno value on failure.
1571 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1573 struct mlx5_priv *priv = dev->data->dev_private;
1574 struct rte_mempool *mp = priv->mprq_mp;
1579 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1580 dev->data->port_id, mp->name);
1582 * If a buffer in the pool has been externally attached to a mbuf and it
1583 * is still in use by application, destroying the Rx queue can spoil
1584 * the packet. It is unlikely to happen but if application dynamically
1585 * creates and destroys with holding Rx packets, this can happen.
1587 * TODO: It is unavoidable for now because the mempool for Multi-Packet
1588 * RQ isn't provided by application but managed by PMD.
1590 if (!rte_mempool_full(mp)) {
1592 "port %u mempool for Multi-Packet RQ is still in use",
1593 dev->data->port_id);
1597 rte_mempool_free(mp);
1598 /* Unset mempool for each Rx queue. */
1599 for (i = 0; i != priv->rxqs_n; ++i) {
1600 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1604 rxq->mprq_mp = NULL;
1606 priv->mprq_mp = NULL;
1611 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1612 * mempool. If already allocated, reuse it if there're enough elements.
1613 * Otherwise, resize it.
1616 * Pointer to Ethernet device.
1619 * 0 on success, negative errno value on failure.
1622 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1624 struct mlx5_priv *priv = dev->data->dev_private;
1625 struct rte_mempool *mp = priv->mprq_mp;
1626 char name[RTE_MEMPOOL_NAMESIZE];
1627 unsigned int desc = 0;
1628 unsigned int buf_len;
1629 unsigned int obj_num;
1630 unsigned int obj_size;
1631 unsigned int strd_num_n = 0;
1632 unsigned int strd_sz_n = 0;
1634 unsigned int n_ibv = 0;
1636 if (!mlx5_mprq_enabled(dev))
1638 /* Count the total number of descriptors configured. */
1639 for (i = 0; i != priv->rxqs_n; ++i) {
1640 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1641 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1642 (rxq, struct mlx5_rxq_ctrl, rxq);
1644 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1647 desc += 1 << rxq->elts_n;
1648 /* Get the max number of strides. */
1649 if (strd_num_n < rxq->strd_num_n)
1650 strd_num_n = rxq->strd_num_n;
1651 /* Get the max size of a stride. */
1652 if (strd_sz_n < rxq->strd_sz_n)
1653 strd_sz_n = rxq->strd_sz_n;
1655 MLX5_ASSERT(strd_num_n && strd_sz_n);
1656 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1657 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1658 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1660 * Received packets can be either memcpy'd or externally referenced. In
1661 * case that the packet is attached to an mbuf as an external buffer, as
1662 * it isn't possible to predict how the buffers will be queued by
1663 * application, there's no option to exactly pre-allocate needed buffers
1664 * in advance but to speculatively prepares enough buffers.
1666 * In the data path, if this Mempool is depleted, PMD will try to memcpy
1667 * received packets to buffers provided by application (rxq->mp) until
1668 * this Mempool gets available again.
1671 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1673 * rte_mempool_create_empty() has sanity check to refuse large cache
1674 * size compared to the number of elements.
1675 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1676 * constant number 2 instead.
1678 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1679 /* Check a mempool is already allocated and if it can be resued. */
1680 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1681 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1682 dev->data->port_id, mp->name);
1685 } else if (mp != NULL) {
1686 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1687 dev->data->port_id, mp->name);
1689 * If failed to free, which means it may be still in use, no way
1690 * but to keep using the existing one. On buffer underrun,
1691 * packets will be memcpy'd instead of external buffer
1694 if (mlx5_mprq_free_mp(dev)) {
1695 if (mp->elt_size >= obj_size)
1701 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1702 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1703 0, NULL, NULL, mlx5_mprq_buf_init,
1704 (void *)(uintptr_t)(1 << strd_num_n),
1705 dev->device->numa_node, 0);
1708 "port %u failed to allocate a mempool for"
1709 " Multi-Packet RQ, count=%u, size=%u",
1710 dev->data->port_id, obj_num, obj_size);
1716 /* Set mempool for each Rx queue. */
1717 for (i = 0; i != priv->rxqs_n; ++i) {
1718 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1719 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1720 (rxq, struct mlx5_rxq_ctrl, rxq);
1722 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1726 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1727 dev->data->port_id);
1731 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1732 sizeof(struct rte_vlan_hdr) * 2 + \
1733 sizeof(struct rte_ipv6_hdr)))
1734 #define MAX_TCP_OPTION_SIZE 40u
1735 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1736 sizeof(struct rte_tcp_hdr) + \
1737 MAX_TCP_OPTION_SIZE))
1740 * Adjust the maximum LRO massage size.
1743 * Pointer to Ethernet device.
1746 * @param max_lro_size
1747 * The maximum size for LRO packet.
1750 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1751 uint32_t max_lro_size)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1755 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1756 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1757 MLX5_MAX_TCP_HDR_OFFSET)
1758 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1759 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1760 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1761 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1762 if (priv->max_lro_msg_size)
1763 priv->max_lro_msg_size =
1764 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1766 priv->max_lro_msg_size = max_lro_size;
1768 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1769 dev->data->port_id, idx,
1770 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1774 * Create a DPDK Rx queue.
1777 * Pointer to Ethernet device.
1781 * Number of descriptors to configure in queue.
1783 * NUMA socket on which memory must be allocated.
1786 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
1788 struct mlx5_rxq_ctrl *
1789 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1790 unsigned int socket, const struct rte_eth_rxconf *conf,
1791 struct rte_mempool *mp)
1793 struct mlx5_priv *priv = dev->data->dev_private;
1794 struct mlx5_rxq_ctrl *tmpl;
1795 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1796 unsigned int mprq_stride_nums;
1797 unsigned int mprq_stride_size;
1798 unsigned int mprq_stride_cap;
1799 struct mlx5_dev_config *config = &priv->config;
1801 * Always allocate extra slots, even if eventually
1802 * the vector Rx will not be used.
1805 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1806 uint64_t offloads = conf->offloads |
1807 dev->data->dev_conf.rxmode.offloads;
1808 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1809 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1810 unsigned int max_rx_pkt_len = lro_on_queue ?
1811 dev->data->dev_conf.rxmode.max_lro_pkt_size :
1812 dev->data->dev_conf.rxmode.max_rx_pkt_len;
1813 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1814 RTE_PKTMBUF_HEADROOM;
1815 unsigned int max_lro_size = 0;
1816 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1818 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1819 DEV_RX_OFFLOAD_SCATTER)) {
1820 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1821 " configured and no enough mbuf space(%u) to contain "
1822 "the maximum RX packet length(%u) with head-room(%u)",
1823 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1824 RTE_PKTMBUF_HEADROOM);
1828 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
1829 desc_n * sizeof(struct rte_mbuf *), 0, socket);
1834 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1835 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1836 MLX5_MR_BTREE_CACHE_N, socket)) {
1837 /* rte_errno is already set. */
1840 tmpl->socket = socket;
1841 if (dev->data->dev_conf.intr_conf.rxq)
1843 mprq_stride_nums = config->mprq.stride_num_n ?
1844 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1845 mprq_stride_size = non_scatter_min_mbuf_size <=
1846 (1U << config->mprq.max_stride_size_n) ?
1847 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1848 mprq_stride_cap = (config->mprq.stride_num_n ?
1849 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1850 (config->mprq.stride_size_n ?
1851 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1853 * This Rx queue can be configured as a Multi-Packet RQ if all of the
1854 * following conditions are met:
1855 * - MPRQ is enabled.
1856 * - The number of descs is more than the number of strides.
1857 * - max_rx_pkt_len plus overhead is less than the max size
1858 * of a stride or mprq_stride_size is specified by a user.
1859 * Need to nake sure that there are enough stides to encap
1860 * the maximum packet size in case mprq_stride_size is set.
1861 * Otherwise, enable Rx scatter if necessary.
1863 if (mprq_en && desc > (1U << mprq_stride_nums) &&
1864 (non_scatter_min_mbuf_size <=
1865 (1U << config->mprq.max_stride_size_n) ||
1866 (config->mprq.stride_size_n &&
1867 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1868 /* TODO: Rx scatter isn't supported yet. */
1869 tmpl->rxq.sges_n = 0;
1870 /* Trim the number of descs needed. */
1871 desc >>= mprq_stride_nums;
1872 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1873 config->mprq.stride_num_n : mprq_stride_nums;
1874 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1875 config->mprq.stride_size_n : mprq_stride_size;
1876 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1877 tmpl->rxq.strd_scatter_en =
1878 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1879 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1880 config->mprq.max_memcpy_len);
1881 max_lro_size = RTE_MIN(max_rx_pkt_len,
1882 (1u << tmpl->rxq.strd_num_n) *
1883 (1u << tmpl->rxq.strd_sz_n));
1885 "port %u Rx queue %u: Multi-Packet RQ is enabled"
1886 " strd_num_n = %u, strd_sz_n = %u",
1887 dev->data->port_id, idx,
1888 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1889 } else if (max_rx_pkt_len <= first_mb_free_size) {
1890 tmpl->rxq.sges_n = 0;
1891 max_lro_size = max_rx_pkt_len;
1892 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1893 unsigned int size = non_scatter_min_mbuf_size;
1894 unsigned int sges_n;
1896 if (lro_on_queue && first_mb_free_size <
1897 MLX5_MAX_LRO_HEADER_FIX) {
1898 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1899 " to include the max header size(%u) for LRO",
1900 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1901 rte_errno = ENOTSUP;
1905 * Determine the number of SGEs needed for a full packet
1906 * and round it to the next power of two.
1908 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1909 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1911 "port %u too many SGEs (%u) needed to handle"
1912 " requested maximum packet size %u, the maximum"
1913 " supported are %u", dev->data->port_id,
1914 1 << sges_n, max_rx_pkt_len,
1915 1u << MLX5_MAX_LOG_RQ_SEGS);
1916 rte_errno = ENOTSUP;
1919 tmpl->rxq.sges_n = sges_n;
1920 max_lro_size = max_rx_pkt_len;
1922 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1924 "port %u MPRQ is requested but cannot be enabled\n"
1925 " (requested: pkt_sz = %u, desc_num = %u,"
1926 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1927 " supported: min_rxqs_num = %u,"
1928 " min_stride_sz = %u, max_stride_sz = %u).",
1929 dev->data->port_id, non_scatter_min_mbuf_size,
1931 config->mprq.stride_size_n ?
1932 (1U << config->mprq.stride_size_n) :
1933 (1U << mprq_stride_size),
1934 config->mprq.stride_num_n ?
1935 (1U << config->mprq.stride_num_n) :
1936 (1U << mprq_stride_nums),
1937 config->mprq.min_rxqs_num,
1938 (1U << config->mprq.min_stride_size_n),
1939 (1U << config->mprq.max_stride_size_n));
1940 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1941 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1942 if (desc % (1 << tmpl->rxq.sges_n)) {
1944 "port %u number of Rx queue descriptors (%u) is not a"
1945 " multiple of SGEs per packet (%u)",
1948 1 << tmpl->rxq.sges_n);
1952 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1953 /* Toggle RX checksum offload if hardware supports it. */
1954 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1955 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1956 /* Configure VLAN stripping. */
1957 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1958 /* By default, FCS (CRC) is stripped by hardware. */
1959 tmpl->rxq.crc_present = 0;
1960 tmpl->rxq.lro = lro_on_queue;
1961 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1962 if (config->hw_fcs_strip) {
1964 * RQs used for LRO-enabled TIRs should not be
1965 * configured to scatter the FCS.
1969 "port %u CRC stripping has been "
1970 "disabled but will still be performed "
1971 "by hardware, because LRO is enabled",
1972 dev->data->port_id);
1974 tmpl->rxq.crc_present = 1;
1977 "port %u CRC stripping has been disabled but will"
1978 " still be performed by hardware, make sure MLNX_OFED"
1979 " and firmware are up to date",
1980 dev->data->port_id);
1984 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1985 " incoming frames to hide it",
1987 tmpl->rxq.crc_present ? "disabled" : "enabled",
1988 tmpl->rxq.crc_present << 2);
1990 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1991 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1992 tmpl->rxq.port_id = dev->data->port_id;
1995 tmpl->rxq.elts_n = log2above(desc);
1996 tmpl->rxq.rq_repl_thresh =
1997 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1999 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
2001 tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
2003 tmpl->rxq.idx = idx;
2004 rte_atomic32_inc(&tmpl->refcnt);
2005 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2013 * Create a DPDK Rx hairpin queue.
2016 * Pointer to Ethernet device.
2020 * Number of descriptors to configure in queue.
2021 * @param hairpin_conf
2022 * The hairpin binding configuration.
2025 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2027 struct mlx5_rxq_ctrl *
2028 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2029 const struct rte_eth_hairpin_conf *hairpin_conf)
2031 struct mlx5_priv *priv = dev->data->dev_private;
2032 struct mlx5_rxq_ctrl *tmpl;
2034 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
2040 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2041 tmpl->socket = SOCKET_ID_ANY;
2042 tmpl->rxq.rss_hash = 0;
2043 tmpl->rxq.port_id = dev->data->port_id;
2045 tmpl->rxq.mp = NULL;
2046 tmpl->rxq.elts_n = log2above(desc);
2047 tmpl->rxq.elts = NULL;
2048 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2049 tmpl->hairpin_conf = *hairpin_conf;
2050 tmpl->rxq.idx = idx;
2051 rte_atomic32_inc(&tmpl->refcnt);
2052 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2060 * Pointer to Ethernet device.
2065 * A pointer to the queue if it exists, NULL otherwise.
2067 struct mlx5_rxq_ctrl *
2068 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2070 struct mlx5_priv *priv = dev->data->dev_private;
2071 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2073 if ((*priv->rxqs)[idx]) {
2074 rxq_ctrl = container_of((*priv->rxqs)[idx],
2075 struct mlx5_rxq_ctrl,
2077 mlx5_rxq_obj_get(dev, idx);
2078 rte_atomic32_inc(&rxq_ctrl->refcnt);
2084 * Release a Rx queue.
2087 * Pointer to Ethernet device.
2092 * 1 while a reference on it exists, 0 when freed.
2095 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2097 struct mlx5_priv *priv = dev->data->dev_private;
2098 struct mlx5_rxq_ctrl *rxq_ctrl;
2100 if (!(*priv->rxqs)[idx])
2102 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2103 MLX5_ASSERT(rxq_ctrl->priv);
2104 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2105 rxq_ctrl->obj = NULL;
2106 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2107 if (rxq_ctrl->dbr_umem_id_valid)
2108 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2109 rxq_ctrl->dbr_umem_id,
2110 rxq_ctrl->dbr_offset));
2111 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2112 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2113 LIST_REMOVE(rxq_ctrl, next);
2114 mlx5_free(rxq_ctrl);
2115 (*priv->rxqs)[idx] = NULL;
2122 * Verify the Rx Queue list is empty
2125 * Pointer to Ethernet device.
2128 * The number of object not released.
2131 mlx5_rxq_verify(struct rte_eth_dev *dev)
2133 struct mlx5_priv *priv = dev->data->dev_private;
2134 struct mlx5_rxq_ctrl *rxq_ctrl;
2137 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2138 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2139 dev->data->port_id, rxq_ctrl->rxq.idx);
2146 * Get a Rx queue type.
2149 * Pointer to Ethernet device.
2154 * The Rx queue type.
2157 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2159 struct mlx5_priv *priv = dev->data->dev_private;
2160 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2162 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2163 rxq_ctrl = container_of((*priv->rxqs)[idx],
2164 struct mlx5_rxq_ctrl,
2166 return rxq_ctrl->type;
2168 return MLX5_RXQ_TYPE_UNDEFINED;
2172 * Create an indirection table.
2175 * Pointer to Ethernet device.
2177 * Queues entering in the indirection table.
2179 * Number of queues in the array.
2182 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2184 static struct mlx5_ind_table_obj *
2185 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2186 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2188 struct mlx5_priv *priv = dev->data->dev_private;
2189 struct mlx5_ind_table_obj *ind_tbl;
2190 unsigned int i = 0, j = 0, k = 0;
2192 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
2193 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
2198 ind_tbl->type = type;
2199 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2200 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2201 log2above(queues_n) :
2202 log2above(priv->config.ind_table_max_size);
2203 struct ibv_wq *wq[1 << wq_n];
2205 for (i = 0; i != queues_n; ++i) {
2206 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2210 wq[i] = rxq->obj->wq;
2211 ind_tbl->queues[i] = queues[i];
2213 ind_tbl->queues_n = queues_n;
2214 /* Finalise indirection table. */
2215 k = i; /* Retain value of i for use in error case. */
2216 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2218 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2220 &(struct ibv_rwq_ind_table_init_attr){
2221 .log_ind_tbl_size = wq_n,
2225 if (!ind_tbl->ind_table) {
2229 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2230 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2231 const unsigned int rqt_n =
2232 1 << (rte_is_power_of_2(queues_n) ?
2233 log2above(queues_n) :
2234 log2above(priv->config.ind_table_max_size));
2236 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
2237 rqt_n * sizeof(uint32_t), 0,
2240 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2241 dev->data->port_id);
2245 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2246 rqt_attr->rqt_actual_size = rqt_n;
2247 for (i = 0; i != queues_n; ++i) {
2248 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2252 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2253 ind_tbl->queues[i] = queues[i];
2255 k = i; /* Retain value of i for use in error case. */
2256 for (j = 0; k != rqt_n; ++k, ++j)
2257 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2258 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2260 mlx5_free(rqt_attr);
2261 if (!ind_tbl->rqt) {
2262 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2263 dev->data->port_id);
2267 ind_tbl->queues_n = queues_n;
2269 rte_atomic32_inc(&ind_tbl->refcnt);
2270 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2273 for (j = 0; j < i; j++)
2274 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2276 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2281 * Get an indirection table.
2284 * Pointer to Ethernet device.
2286 * Queues entering in the indirection table.
2288 * Number of queues in the array.
2291 * An indirection table if found.
2293 static struct mlx5_ind_table_obj *
2294 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2297 struct mlx5_priv *priv = dev->data->dev_private;
2298 struct mlx5_ind_table_obj *ind_tbl;
2300 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2301 if ((ind_tbl->queues_n == queues_n) &&
2302 (memcmp(ind_tbl->queues, queues,
2303 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2310 rte_atomic32_inc(&ind_tbl->refcnt);
2311 for (i = 0; i != ind_tbl->queues_n; ++i)
2312 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2318 * Release an indirection table.
2321 * Pointer to Ethernet device.
2323 * Indirection table to release.
2326 * 1 while a reference on it exists, 0 when freed.
2329 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2330 struct mlx5_ind_table_obj *ind_tbl)
2334 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2335 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2336 claim_zero(mlx5_glue->destroy_rwq_ind_table
2337 (ind_tbl->ind_table));
2338 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2339 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2341 for (i = 0; i != ind_tbl->queues_n; ++i)
2342 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2343 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2344 LIST_REMOVE(ind_tbl, next);
2352 * Verify the Rx Queue list is empty
2355 * Pointer to Ethernet device.
2358 * The number of object not released.
2361 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2363 struct mlx5_priv *priv = dev->data->dev_private;
2364 struct mlx5_ind_table_obj *ind_tbl;
2367 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2369 "port %u indirection table obj %p still referenced",
2370 dev->data->port_id, (void *)ind_tbl);
2377 * Create an Rx Hash queue.
2380 * Pointer to Ethernet device.
2382 * RSS key for the Rx hash queue.
2383 * @param rss_key_len
2385 * @param hash_fields
2386 * Verbs protocol hash field to make the RSS on.
2388 * Queues entering in hash queue. In case of empty hash_fields only the
2389 * first queue index will be taken for the indirection table.
2396 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2399 mlx5_hrxq_new(struct rte_eth_dev *dev,
2400 const uint8_t *rss_key, uint32_t rss_key_len,
2401 uint64_t hash_fields,
2402 const uint16_t *queues, uint32_t queues_n,
2403 int tunnel __rte_unused)
2405 struct mlx5_priv *priv = dev->data->dev_private;
2406 struct mlx5_hrxq *hrxq;
2407 uint32_t hrxq_idx = 0;
2408 struct ibv_qp *qp = NULL;
2409 struct mlx5_ind_table_obj *ind_tbl;
2411 struct mlx5_devx_obj *tir = NULL;
2412 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2413 struct mlx5_rxq_ctrl *rxq_ctrl =
2414 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2416 queues_n = hash_fields ? queues_n : 1;
2417 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2419 enum mlx5_ind_tbl_type type;
2421 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2422 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2423 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2429 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2430 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2431 struct mlx5dv_qp_init_attr qp_init_attr;
2433 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2435 qp_init_attr.comp_mask =
2436 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2437 qp_init_attr.create_flags =
2438 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2440 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2441 if (dev->data->dev_conf.lpbk_mode) {
2443 * Allow packet sent from NIC loop back
2444 * w/o source MAC check.
2446 qp_init_attr.comp_mask |=
2447 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2448 qp_init_attr.create_flags |=
2449 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2452 qp = mlx5_glue->dv_create_qp
2454 &(struct ibv_qp_init_attr_ex){
2455 .qp_type = IBV_QPT_RAW_PACKET,
2457 IBV_QP_INIT_ATTR_PD |
2458 IBV_QP_INIT_ATTR_IND_TABLE |
2459 IBV_QP_INIT_ATTR_RX_HASH,
2460 .rx_hash_conf = (struct ibv_rx_hash_conf){
2462 IBV_RX_HASH_FUNC_TOEPLITZ,
2463 .rx_hash_key_len = rss_key_len,
2465 (void *)(uintptr_t)rss_key,
2466 .rx_hash_fields_mask = hash_fields,
2468 .rwq_ind_tbl = ind_tbl->ind_table,
2473 qp = mlx5_glue->create_qp_ex
2475 &(struct ibv_qp_init_attr_ex){
2476 .qp_type = IBV_QPT_RAW_PACKET,
2478 IBV_QP_INIT_ATTR_PD |
2479 IBV_QP_INIT_ATTR_IND_TABLE |
2480 IBV_QP_INIT_ATTR_RX_HASH,
2481 .rx_hash_conf = (struct ibv_rx_hash_conf){
2483 IBV_RX_HASH_FUNC_TOEPLITZ,
2484 .rx_hash_key_len = rss_key_len,
2486 (void *)(uintptr_t)rss_key,
2487 .rx_hash_fields_mask = hash_fields,
2489 .rwq_ind_tbl = ind_tbl->ind_table,
2497 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2498 struct mlx5_devx_tir_attr tir_attr;
2502 /* Enable TIR LRO only if all the queues were configured for. */
2503 for (i = 0; i < queues_n; ++i) {
2504 if (!(*priv->rxqs)[queues[i]]->lro) {
2509 memset(&tir_attr, 0, sizeof(tir_attr));
2510 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2511 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2512 tir_attr.tunneled_offload_en = !!tunnel;
2513 /* If needed, translate hash_fields bitmap to PRM format. */
2515 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2516 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2517 hash_fields & IBV_RX_HASH_INNER ?
2518 &tir_attr.rx_hash_field_selector_inner :
2519 &tir_attr.rx_hash_field_selector_outer;
2521 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2522 &tir_attr.rx_hash_field_selector_outer;
2525 /* 1 bit: 0: IPv4, 1: IPv6. */
2526 rx_hash_field_select->l3_prot_type =
2527 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2528 /* 1 bit: 0: TCP, 1: UDP. */
2529 rx_hash_field_select->l4_prot_type =
2530 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2531 /* Bitmask which sets which fields to use in RX Hash. */
2532 rx_hash_field_select->selected_fields =
2533 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2534 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2535 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2536 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2537 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2538 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2539 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2540 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2542 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2543 tir_attr.transport_domain = priv->sh->td->id;
2545 tir_attr.transport_domain = priv->sh->tdn;
2546 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2547 MLX5_RSS_HASH_KEY_LEN);
2548 tir_attr.indirect_table = ind_tbl->rqt->id;
2549 if (dev->data->dev_conf.lpbk_mode)
2550 tir_attr.self_lb_block =
2551 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2553 tir_attr.lro_timeout_period_usecs =
2554 priv->config.lro.timeout;
2555 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2556 tir_attr.lro_enable_mask =
2557 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2558 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2560 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2562 DRV_LOG(ERR, "port %u cannot create DevX TIR",
2563 dev->data->port_id);
2568 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2571 hrxq->ind_table = ind_tbl;
2572 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2574 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2576 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2577 if (!hrxq->action) {
2582 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2584 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2585 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2587 if (!hrxq->action) {
2593 hrxq->rss_key_len = rss_key_len;
2594 hrxq->hash_fields = hash_fields;
2595 memcpy(hrxq->rss_key, rss_key, rss_key_len);
2596 rte_atomic32_inc(&hrxq->refcnt);
2597 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2601 err = rte_errno; /* Save rte_errno before cleanup. */
2602 mlx5_ind_table_obj_release(dev, ind_tbl);
2604 claim_zero(mlx5_glue->destroy_qp(qp));
2606 claim_zero(mlx5_devx_cmd_destroy(tir));
2607 rte_errno = err; /* Restore rte_errno. */
2612 * Get an Rx Hash queue.
2615 * Pointer to Ethernet device.
2617 * RSS configuration for the Rx hash queue.
2619 * Queues entering in hash queue. In case of empty hash_fields only the
2620 * first queue index will be taken for the indirection table.
2625 * An hash Rx queue index on success.
2628 mlx5_hrxq_get(struct rte_eth_dev *dev,
2629 const uint8_t *rss_key, uint32_t rss_key_len,
2630 uint64_t hash_fields,
2631 const uint16_t *queues, uint32_t queues_n)
2633 struct mlx5_priv *priv = dev->data->dev_private;
2634 struct mlx5_hrxq *hrxq;
2637 queues_n = hash_fields ? queues_n : 1;
2638 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2640 struct mlx5_ind_table_obj *ind_tbl;
2642 if (hrxq->rss_key_len != rss_key_len)
2644 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2646 if (hrxq->hash_fields != hash_fields)
2648 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2651 if (ind_tbl != hrxq->ind_table) {
2652 mlx5_ind_table_obj_release(dev, ind_tbl);
2655 rte_atomic32_inc(&hrxq->refcnt);
2662 * Release the hash Rx queue.
2665 * Pointer to Ethernet device.
2667 * Index to Hash Rx queue to release.
2670 * 1 while a reference on it exists, 0 when freed.
2673 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2675 struct mlx5_priv *priv = dev->data->dev_private;
2676 struct mlx5_hrxq *hrxq;
2678 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2681 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2682 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2683 mlx5_glue->destroy_flow_action(hrxq->action);
2685 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2686 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2687 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2688 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2689 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2690 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2691 hrxq_idx, hrxq, next);
2692 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2695 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2700 * Verify the Rx Queue list is empty
2703 * Pointer to Ethernet device.
2706 * The number of object not released.
2709 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2711 struct mlx5_priv *priv = dev->data->dev_private;
2712 struct mlx5_hrxq *hrxq;
2716 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2719 "port %u hash Rx queue %p still referenced",
2720 dev->data->port_id, (void *)hrxq);
2727 * Create a drop Rx queue Verbs/DevX object.
2730 * Pointer to Ethernet device.
2733 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2735 static struct mlx5_rxq_obj *
2736 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2738 struct mlx5_priv *priv = dev->data->dev_private;
2739 struct ibv_context *ctx = priv->sh->ctx;
2741 struct ibv_wq *wq = NULL;
2742 struct mlx5_rxq_obj *rxq;
2744 if (priv->drop_queue.rxq)
2745 return priv->drop_queue.rxq;
2746 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2748 DEBUG("port %u cannot allocate CQ for drop queue",
2749 dev->data->port_id);
2753 wq = mlx5_glue->create_wq(ctx,
2754 &(struct ibv_wq_init_attr){
2755 .wq_type = IBV_WQT_RQ,
2762 DEBUG("port %u cannot allocate WQ for drop queue",
2763 dev->data->port_id);
2767 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
2769 DEBUG("port %u cannot allocate drop Rx queue memory",
2770 dev->data->port_id);
2776 priv->drop_queue.rxq = rxq;
2780 claim_zero(mlx5_glue->destroy_wq(wq));
2782 claim_zero(mlx5_glue->destroy_cq(cq));
2787 * Release a drop Rx queue Verbs/DevX object.
2790 * Pointer to Ethernet device.
2793 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2796 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2798 struct mlx5_priv *priv = dev->data->dev_private;
2799 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2802 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2804 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2806 priv->drop_queue.rxq = NULL;
2810 * Create a drop indirection table.
2813 * Pointer to Ethernet device.
2816 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2818 static struct mlx5_ind_table_obj *
2819 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2821 struct mlx5_priv *priv = dev->data->dev_private;
2822 struct mlx5_ind_table_obj *ind_tbl;
2823 struct mlx5_rxq_obj *rxq;
2824 struct mlx5_ind_table_obj tmpl;
2826 rxq = mlx5_rxq_obj_drop_new(dev);
2829 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2831 &(struct ibv_rwq_ind_table_init_attr){
2832 .log_ind_tbl_size = 0,
2833 .ind_tbl = &rxq->wq,
2836 if (!tmpl.ind_table) {
2837 DEBUG("port %u cannot allocate indirection table for drop"
2839 dev->data->port_id);
2843 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
2849 ind_tbl->ind_table = tmpl.ind_table;
2852 mlx5_rxq_obj_drop_release(dev);
2857 * Release a drop indirection table.
2860 * Pointer to Ethernet device.
2863 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2865 struct mlx5_priv *priv = dev->data->dev_private;
2866 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2868 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2869 mlx5_rxq_obj_drop_release(dev);
2871 priv->drop_queue.hrxq->ind_table = NULL;
2875 * Create a drop Rx Hash queue.
2878 * Pointer to Ethernet device.
2881 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2884 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2886 struct mlx5_priv *priv = dev->data->dev_private;
2887 struct mlx5_ind_table_obj *ind_tbl = NULL;
2888 struct ibv_qp *qp = NULL;
2889 struct mlx5_hrxq *hrxq = NULL;
2891 if (priv->drop_queue.hrxq) {
2892 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2893 return priv->drop_queue.hrxq;
2895 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
2898 "port %u cannot allocate memory for drop queue",
2899 dev->data->port_id);
2903 priv->drop_queue.hrxq = hrxq;
2904 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2907 hrxq->ind_table = ind_tbl;
2908 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2909 &(struct ibv_qp_init_attr_ex){
2910 .qp_type = IBV_QPT_RAW_PACKET,
2912 IBV_QP_INIT_ATTR_PD |
2913 IBV_QP_INIT_ATTR_IND_TABLE |
2914 IBV_QP_INIT_ATTR_RX_HASH,
2915 .rx_hash_conf = (struct ibv_rx_hash_conf){
2917 IBV_RX_HASH_FUNC_TOEPLITZ,
2918 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2919 .rx_hash_key = rss_hash_default_key,
2920 .rx_hash_fields_mask = 0,
2922 .rwq_ind_tbl = ind_tbl->ind_table,
2926 DEBUG("port %u cannot allocate QP for drop queue",
2927 dev->data->port_id);
2932 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2933 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2934 if (!hrxq->action) {
2939 rte_atomic32_set(&hrxq->refcnt, 1);
2942 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2943 if (hrxq && hrxq->action)
2944 mlx5_glue->destroy_flow_action(hrxq->action);
2947 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2949 mlx5_ind_table_obj_drop_release(dev);
2951 priv->drop_queue.hrxq = NULL;
2958 * Release a drop hash Rx queue.
2961 * Pointer to Ethernet device.
2964 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2966 struct mlx5_priv *priv = dev->data->dev_private;
2967 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2969 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2970 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2971 mlx5_glue->destroy_flow_action(hrxq->action);
2973 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2974 mlx5_ind_table_obj_drop_release(dev);
2976 priv->drop_queue.hrxq = NULL;
2982 * Set the Rx queue timestamp conversion parameters
2985 * Pointer to the Ethernet device structure.
2988 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
2990 struct mlx5_priv *priv = dev->data->dev_private;
2991 struct mlx5_dev_ctx_shared *sh = priv->sh;
2992 struct mlx5_rxq_data *data;
2995 for (i = 0; i != priv->rxqs_n; ++i) {
2996 if (!(*priv->rxqs)[i])
2998 data = (*priv->rxqs)[i];
3000 data->rt_timestamp = priv->config.rt_timestamp;