1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
11 #include <sys/queue.h>
14 #include <rte_malloc.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_common.h>
17 #include <rte_interrupts.h>
18 #include <rte_debug.h>
20 #include <rte_eal_paging.h>
22 #include <mlx5_glue.h>
23 #include <mlx5_devx_cmds.h>
24 #include <mlx5_malloc.h>
26 #include "mlx5_defs.h"
28 #include "mlx5_common_os.h"
29 #include "mlx5_rxtx.h"
30 #include "mlx5_utils.h"
31 #include "mlx5_autoconf.h"
32 #include "mlx5_flow.h"
35 /* Default RSS hash key also used for ConnectX-3. */
36 uint8_t rss_hash_default_key[] = {
37 0x2c, 0xc6, 0x81, 0xd1,
38 0x5b, 0xdb, 0xf4, 0xf7,
39 0xfc, 0xa2, 0x83, 0x19,
40 0xdb, 0x1a, 0x3e, 0x94,
41 0x6b, 0x9e, 0x38, 0xd9,
42 0x2c, 0x9c, 0x03, 0xd1,
43 0xad, 0x99, 0x44, 0xa7,
44 0xd9, 0x56, 0x3d, 0x59,
45 0x06, 0x3c, 0x25, 0xf3,
46 0xfc, 0x1f, 0xdc, 0x2a,
49 /* Length of the default RSS hash key. */
50 static_assert(MLX5_RSS_HASH_KEY_LEN ==
51 (unsigned int)sizeof(rss_hash_default_key),
52 "wrong RSS default key size.");
55 * Check whether Multi-Packet RQ can be enabled for the device.
58 * Pointer to Ethernet device.
61 * 1 if supported, negative errno value if not.
64 mlx5_check_mprq_support(struct rte_eth_dev *dev)
66 struct mlx5_priv *priv = dev->data->dev_private;
68 if (priv->config.mprq.enabled &&
69 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
75 * Check whether Multi-Packet RQ is enabled for the Rx queue.
78 * Pointer to receive queue structure.
81 * 0 if disabled, otherwise enabled.
84 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
86 return rxq->strd_num_n > 0;
90 * Check whether Multi-Packet RQ is enabled for the device.
93 * Pointer to Ethernet device.
96 * 0 if disabled, otherwise enabled.
99 mlx5_mprq_enabled(struct rte_eth_dev *dev)
101 struct mlx5_priv *priv = dev->data->dev_private;
106 if (mlx5_check_mprq_support(dev) < 0)
108 /* All the configured queues should be enabled. */
109 for (i = 0; i < priv->rxqs_n; ++i) {
110 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
111 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
112 (rxq, struct mlx5_rxq_ctrl, rxq);
114 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
117 if (mlx5_rxq_mprq_enabled(rxq))
120 /* Multi-Packet RQ can't be partially configured. */
121 MLX5_ASSERT(n == 0 || n == n_ibv);
126 * Allocate RX queue elements for Multi-Packet RQ.
129 * Pointer to RX queue structure.
132 * 0 on success, a negative errno value otherwise and rte_errno is set.
135 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
137 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
138 unsigned int wqe_n = 1 << rxq->elts_n;
142 /* Iterate on segments. */
143 for (i = 0; i <= wqe_n; ++i) {
144 struct mlx5_mprq_buf *buf;
146 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
147 DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
152 (*rxq->mprq_bufs)[i] = buf;
154 rxq->mprq_repl = buf;
157 "port %u Rx queue %u allocated and configured %u segments",
158 rxq->port_id, rxq->idx, wqe_n);
161 err = rte_errno; /* Save rte_errno before cleanup. */
163 for (i = 0; (i != wqe_n); ++i) {
164 if ((*rxq->mprq_bufs)[i] != NULL)
165 rte_mempool_put(rxq->mprq_mp,
166 (*rxq->mprq_bufs)[i]);
167 (*rxq->mprq_bufs)[i] = NULL;
169 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
170 rxq->port_id, rxq->idx);
171 rte_errno = err; /* Restore rte_errno. */
176 * Allocate RX queue elements for Single-Packet RQ.
179 * Pointer to RX queue structure.
182 * 0 on success, errno value on failure.
185 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
187 const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
188 unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
192 /* Iterate on segments. */
193 for (i = 0; (i != elts_n); ++i) {
194 struct rte_mbuf *buf;
196 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
198 DRV_LOG(ERR, "port %u empty mbuf pool",
199 PORT_ID(rxq_ctrl->priv));
203 /* Headroom is reserved by rte_pktmbuf_alloc(). */
204 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
205 /* Buffer is supposed to be empty. */
206 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
207 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
208 MLX5_ASSERT(!buf->next);
209 /* Only the first segment keeps headroom. */
211 SET_DATA_OFF(buf, 0);
212 PORT(buf) = rxq_ctrl->rxq.port_id;
213 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
214 PKT_LEN(buf) = DATA_LEN(buf);
216 (*rxq_ctrl->rxq.elts)[i] = buf;
218 /* If Rx vector is activated. */
219 if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
220 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
221 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
222 struct rte_pktmbuf_pool_private *priv =
223 (struct rte_pktmbuf_pool_private *)
224 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
227 /* Initialize default rearm_data for vPMD. */
228 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
229 rte_mbuf_refcnt_set(mbuf_init, 1);
230 mbuf_init->nb_segs = 1;
231 mbuf_init->port = rxq->port_id;
232 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
233 mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
235 * prevent compiler reordering:
236 * rearm_data covers previous fields.
238 rte_compiler_barrier();
239 rxq->mbuf_initializer =
240 *(rte_xmm_t *)&mbuf_init->rearm_data;
241 /* Padding with a fake mbuf for vectorized Rx. */
242 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
243 (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
246 "port %u Rx queue %u allocated and configured %u segments"
248 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
249 elts_n / (1 << rxq_ctrl->rxq.sges_n));
252 err = rte_errno; /* Save rte_errno before cleanup. */
254 for (i = 0; (i != elts_n); ++i) {
255 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
256 rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
257 (*rxq_ctrl->rxq.elts)[i] = NULL;
259 DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
260 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
261 rte_errno = err; /* Restore rte_errno. */
266 * Allocate RX queue elements.
269 * Pointer to RX queue structure.
272 * 0 on success, errno value on failure.
275 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
277 return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
278 rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
282 * Free RX queue elements for Multi-Packet RQ.
285 * Pointer to RX queue structure.
288 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
290 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
293 DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
294 rxq->port_id, rxq->idx);
295 if (rxq->mprq_bufs == NULL)
297 MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
298 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
299 if ((*rxq->mprq_bufs)[i] != NULL)
300 mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
301 (*rxq->mprq_bufs)[i] = NULL;
303 if (rxq->mprq_repl != NULL) {
304 mlx5_mprq_buf_free(rxq->mprq_repl);
305 rxq->mprq_repl = NULL;
310 * Free RX queue elements for Single-Packet RQ.
313 * Pointer to RX queue structure.
316 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
318 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
319 const uint16_t q_n = (1 << rxq->elts_n);
320 const uint16_t q_mask = q_n - 1;
321 uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
324 DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
325 PORT_ID(rxq_ctrl->priv), rxq->idx);
326 if (rxq->elts == NULL)
329 * Some mbuf in the Ring belongs to the application. They cannot be
332 if (mlx5_rxq_check_vec_support(rxq) > 0) {
333 for (i = 0; i < used; ++i)
334 (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
335 rxq->rq_pi = rxq->rq_ci;
337 for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
338 if ((*rxq->elts)[i] != NULL)
339 rte_pktmbuf_free_seg((*rxq->elts)[i]);
340 (*rxq->elts)[i] = NULL;
345 * Free RX queue elements.
348 * Pointer to RX queue structure.
351 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
353 if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
354 rxq_free_elts_mprq(rxq_ctrl);
356 rxq_free_elts_sprq(rxq_ctrl);
360 * Returns the per-queue supported offloads.
363 * Pointer to Ethernet device.
366 * Supported Rx offloads.
369 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
371 struct mlx5_priv *priv = dev->data->dev_private;
372 struct mlx5_dev_config *config = &priv->config;
373 uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
374 DEV_RX_OFFLOAD_TIMESTAMP |
375 DEV_RX_OFFLOAD_JUMBO_FRAME |
376 DEV_RX_OFFLOAD_RSS_HASH);
378 if (config->hw_fcs_strip)
379 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
382 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
383 DEV_RX_OFFLOAD_UDP_CKSUM |
384 DEV_RX_OFFLOAD_TCP_CKSUM);
385 if (config->hw_vlan_strip)
386 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
387 if (MLX5_LRO_SUPPORTED(dev))
388 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
394 * Returns the per-port supported offloads.
397 * Supported Rx offloads.
400 mlx5_get_rx_port_offloads(void)
402 uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
408 * Verify if the queue can be released.
411 * Pointer to Ethernet device.
416 * 1 if the queue can be released
417 * 0 if the queue can not be released, there are references to it.
418 * Negative errno and rte_errno is set if queue doesn't exist.
421 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
423 struct mlx5_priv *priv = dev->data->dev_private;
424 struct mlx5_rxq_ctrl *rxq_ctrl;
426 if (!(*priv->rxqs)[idx]) {
430 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
431 return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
434 /* Fetches and drops all SW-owned and error CQEs to synchronize CQ. */
436 rxq_sync_cq(struct mlx5_rxq_data *rxq)
438 const uint16_t cqe_n = 1 << rxq->cqe_n;
439 const uint16_t cqe_mask = cqe_n - 1;
440 volatile struct mlx5_cqe *cqe;
445 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask];
446 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
447 if (ret == MLX5_CQE_STATUS_HW_OWN)
449 if (ret == MLX5_CQE_STATUS_ERR) {
453 MLX5_ASSERT(ret == MLX5_CQE_STATUS_SW_OWN);
454 if (MLX5_CQE_FORMAT(cqe->op_own) != MLX5_COMPRESSED) {
458 /* Compute the next non compressed CQE. */
459 rxq->cq_ci += rte_be_to_cpu_32(cqe->byte_cnt);
462 /* Move all CQEs to HW ownership, including possible MiniCQEs. */
463 for (i = 0; i < cqe_n; i++) {
464 cqe = &(*rxq->cqes)[i];
465 cqe->op_own = MLX5_CQE_INVALIDATE;
467 /* Resync CQE and WQE (WQ in RESET state). */
469 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
471 *rxq->rq_db = rte_cpu_to_be_32(0);
476 * Rx queue stop. Device queue goes to the RESET state,
477 * all involved mbufs are freed from WQ.
480 * Pointer to Ethernet device structure.
485 * 0 on success, a negative errno value otherwise and rte_errno is set.
488 mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t idx)
490 struct mlx5_priv *priv = dev->data->dev_private;
491 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
492 struct mlx5_rxq_ctrl *rxq_ctrl =
493 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
496 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
497 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
498 struct ibv_wq_attr mod = {
499 .attr_mask = IBV_WQ_ATTR_STATE,
500 .wq_state = IBV_WQS_RESET,
503 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
504 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
505 struct mlx5_devx_modify_rq_attr rq_attr;
507 memset(&rq_attr, 0, sizeof(rq_attr));
508 rq_attr.rq_state = MLX5_RQC_STATE_RST;
509 rq_attr.state = MLX5_RQC_STATE_RDY;
510 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
513 DRV_LOG(ERR, "Cannot change Rx WQ state to RESET: %s",
518 /* Remove all processes CQEs. */
520 /* Free all involved mbufs. */
521 rxq_free_elts(rxq_ctrl);
522 /* Set the actual queue state. */
523 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STOPPED;
528 * Rx queue stop. Device queue goes to the RESET state,
529 * all involved mbufs are freed from WQ.
532 * Pointer to Ethernet device structure.
537 * 0 on success, a negative errno value otherwise and rte_errno is set.
540 mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t idx)
542 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
545 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
546 DRV_LOG(ERR, "Hairpin queue can't be stopped");
550 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STOPPED)
553 * Vectorized Rx burst requires the CQ and RQ indices
554 * synchronized, that might be broken on RQ restart
555 * and cause Rx malfunction, so queue stopping is
556 * not supported if vectorized Rx burst is engaged.
557 * The routine pointer depends on the process
558 * type, should perform check there.
560 if (pkt_burst == mlx5_rx_burst) {
561 DRV_LOG(ERR, "Rx queue stop is not supported "
562 "for vectorized Rx");
566 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
567 ret = mlx5_mp_os_req_queue_control(dev, idx,
568 MLX5_MP_REQ_QUEUE_RX_STOP);
570 ret = mlx5_rx_queue_stop_primary(dev, idx);
576 * Rx queue start. Device queue goes to the ready state,
577 * all required mbufs are allocated and WQ is replenished.
580 * Pointer to Ethernet device structure.
585 * 0 on success, a negative errno value otherwise and rte_errno is set.
588 mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t idx)
590 struct mlx5_priv *priv = dev->data->dev_private;
591 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
592 struct mlx5_rxq_ctrl *rxq_ctrl =
593 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
596 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
597 /* Allocate needed buffers. */
598 ret = rxq_alloc_elts(rxq_ctrl);
600 DRV_LOG(ERR, "Cannot reallocate buffers for Rx WQ");
605 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
607 /* Reset RQ consumer before moving queue ro READY state. */
608 *rxq->rq_db = rte_cpu_to_be_32(0);
610 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
611 struct ibv_wq_attr mod = {
612 .attr_mask = IBV_WQ_ATTR_STATE,
613 .wq_state = IBV_WQS_RDY,
616 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
617 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
618 struct mlx5_devx_modify_rq_attr rq_attr;
620 memset(&rq_attr, 0, sizeof(rq_attr));
621 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
622 rq_attr.state = MLX5_RQC_STATE_RST;
623 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);
626 DRV_LOG(ERR, "Cannot change Rx WQ state to READY: %s",
631 /* Reinitialize RQ - set WQEs. */
632 mlx5_rxq_initialize(rxq);
633 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
634 /* Set actual queue state. */
635 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
640 * Rx queue start. Device queue goes to the ready state,
641 * all required mbufs are allocated and WQ is replenished.
644 * Pointer to Ethernet device structure.
649 * 0 on success, a negative errno value otherwise and rte_errno is set.
652 mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t idx)
656 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_HAIRPIN) {
657 DRV_LOG(ERR, "Hairpin queue can't be started");
661 if (dev->data->rx_queue_state[idx] == RTE_ETH_QUEUE_STATE_STARTED)
663 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
664 ret = mlx5_mp_os_req_queue_control(dev, idx,
665 MLX5_MP_REQ_QUEUE_RX_START);
667 ret = mlx5_rx_queue_start_primary(dev, idx);
673 * Rx queue presetup checks.
676 * Pointer to Ethernet device structure.
680 * Number of descriptors to configure in queue.
683 * 0 on success, a negative errno value otherwise and rte_errno is set.
686 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
688 struct mlx5_priv *priv = dev->data->dev_private;
690 if (!rte_is_power_of_2(*desc)) {
691 *desc = 1 << log2above(*desc);
693 "port %u increased number of descriptors in Rx queue %u"
694 " to the next power of two (%d)",
695 dev->data->port_id, idx, *desc);
697 DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
698 dev->data->port_id, idx, *desc);
699 if (idx >= priv->rxqs_n) {
700 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
701 dev->data->port_id, idx, priv->rxqs_n);
702 rte_errno = EOVERFLOW;
705 if (!mlx5_rxq_releasable(dev, idx)) {
706 DRV_LOG(ERR, "port %u unable to release queue index %u",
707 dev->data->port_id, idx);
711 mlx5_rxq_release(dev, idx);
718 * Pointer to Ethernet device structure.
722 * Number of descriptors to configure in queue.
724 * NUMA socket on which memory must be allocated.
726 * Thresholds parameters.
728 * Memory pool for buffer allocations.
731 * 0 on success, a negative errno value otherwise and rte_errno is set.
734 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
735 unsigned int socket, const struct rte_eth_rxconf *conf,
736 struct rte_mempool *mp)
738 struct mlx5_priv *priv = dev->data->dev_private;
739 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
740 struct mlx5_rxq_ctrl *rxq_ctrl =
741 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
744 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
747 rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
749 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
750 dev->data->port_id, idx);
754 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
755 dev->data->port_id, idx);
756 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
763 * Pointer to Ethernet device structure.
767 * Number of descriptors to configure in queue.
768 * @param hairpin_conf
769 * Hairpin configuration parameters.
772 * 0 on success, a negative errno value otherwise and rte_errno is set.
775 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
777 const struct rte_eth_hairpin_conf *hairpin_conf)
779 struct mlx5_priv *priv = dev->data->dev_private;
780 struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
781 struct mlx5_rxq_ctrl *rxq_ctrl =
782 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
785 res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
788 if (hairpin_conf->peer_count != 1 ||
789 hairpin_conf->peers[0].port != dev->data->port_id ||
790 hairpin_conf->peers[0].queue >= priv->txqs_n) {
791 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
792 " invalid hairpind configuration", dev->data->port_id,
797 rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
799 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
800 dev->data->port_id, idx);
804 DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
805 dev->data->port_id, idx);
806 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
811 * DPDK callback to release a RX queue.
814 * Generic RX queue pointer.
817 mlx5_rx_queue_release(void *dpdk_rxq)
819 struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
820 struct mlx5_rxq_ctrl *rxq_ctrl;
821 struct mlx5_priv *priv;
825 rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
826 priv = rxq_ctrl->priv;
827 if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
828 rte_panic("port %u Rx queue %u is still used by a flow and"
829 " cannot be removed\n",
830 PORT_ID(priv), rxq->idx);
831 mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
835 * Get an Rx queue Verbs/DevX object.
838 * Pointer to Ethernet device.
840 * Queue index in DPDK Rx queue array
843 * The Verbs/DevX object if it exists.
845 static struct mlx5_rxq_obj *
846 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
848 struct mlx5_priv *priv = dev->data->dev_private;
849 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
850 struct mlx5_rxq_ctrl *rxq_ctrl;
852 if (idx >= priv->rxqs_n)
856 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
858 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
859 return rxq_ctrl->obj;
863 * Release the resources allocated for an RQ DevX object.
866 * DevX Rx queue object.
869 rxq_release_devx_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
871 if (rxq_ctrl->rxq.wqes) {
872 mlx5_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
873 rxq_ctrl->rxq.wqes = NULL;
875 if (rxq_ctrl->wq_umem) {
876 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
877 rxq_ctrl->wq_umem = NULL;
882 * Release the resources allocated for the Rx CQ DevX object.
885 * DevX Rx queue object.
888 rxq_release_devx_cq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
890 if (rxq_ctrl->rxq.cqes) {
891 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.cqes);
892 rxq_ctrl->rxq.cqes = NULL;
894 if (rxq_ctrl->cq_umem) {
895 mlx5_glue->devx_umem_dereg(rxq_ctrl->cq_umem);
896 rxq_ctrl->cq_umem = NULL;
901 * Release an Rx hairpin related resources.
904 * Hairpin Rx queue object.
907 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
909 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
911 MLX5_ASSERT(rxq_obj);
912 rq_attr.state = MLX5_RQC_STATE_RST;
913 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
914 mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
915 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
919 * Release an Rx verbs/DevX queue object.
922 * Verbs/DevX Rx queue object.
925 * 1 while a reference on it exists, 0 when freed.
928 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
930 MLX5_ASSERT(rxq_obj);
931 if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
932 switch (rxq_obj->type) {
933 case MLX5_RXQ_OBJ_TYPE_IBV:
934 MLX5_ASSERT(rxq_obj->wq);
935 MLX5_ASSERT(rxq_obj->ibv_cq);
936 rxq_free_elts(rxq_obj->rxq_ctrl);
937 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
938 claim_zero(mlx5_glue->destroy_cq(rxq_obj->ibv_cq));
939 if (rxq_obj->ibv_channel)
940 claim_zero(mlx5_glue->destroy_comp_channel
941 (rxq_obj->ibv_channel));
943 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
944 MLX5_ASSERT(rxq_obj->rq);
945 MLX5_ASSERT(rxq_obj->devx_cq);
946 rxq_free_elts(rxq_obj->rxq_ctrl);
947 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
948 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->devx_cq));
949 if (rxq_obj->devx_channel)
950 mlx5_glue->devx_destroy_event_channel
951 (rxq_obj->devx_channel);
952 rxq_release_devx_rq_resources(rxq_obj->rxq_ctrl);
953 rxq_release_devx_cq_resources(rxq_obj->rxq_ctrl);
955 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
956 MLX5_ASSERT(rxq_obj->rq);
957 rxq_obj_hairpin_release(rxq_obj);
960 LIST_REMOVE(rxq_obj, next);
968 * Allocate queue vector and fill epoll fd list for Rx interrupts.
971 * Pointer to Ethernet device.
974 * 0 on success, a negative errno value otherwise and rte_errno is set.
977 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
979 struct mlx5_priv *priv = dev->data->dev_private;
981 unsigned int rxqs_n = priv->rxqs_n;
982 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
983 unsigned int count = 0;
984 struct rte_intr_handle *intr_handle = dev->intr_handle;
986 if (!dev->data->dev_conf.intr_conf.rxq)
988 mlx5_rx_intr_vec_disable(dev);
989 intr_handle->intr_vec = mlx5_malloc(0,
990 n * sizeof(intr_handle->intr_vec[0]),
992 if (intr_handle->intr_vec == NULL) {
994 "port %u failed to allocate memory for interrupt"
995 " vector, Rx interrupts will not be supported",
1000 intr_handle->type = RTE_INTR_HANDLE_EXT;
1001 for (i = 0; i != n; ++i) {
1002 /* This rxq obj must not be released in this function. */
1003 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
1006 /* Skip queues that cannot request interrupts. */
1007 if (!rxq_obj || (!rxq_obj->ibv_channel &&
1008 !rxq_obj->devx_channel)) {
1009 /* Use invalid intr_vec[] index to disable entry. */
1010 intr_handle->intr_vec[i] =
1011 RTE_INTR_VEC_RXTX_OFFSET +
1012 RTE_MAX_RXTX_INTR_VEC_ID;
1015 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
1017 "port %u too many Rx queues for interrupt"
1018 " vector size (%d), Rx interrupts cannot be"
1020 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
1021 mlx5_rx_intr_vec_disable(dev);
1025 rc = mlx5_os_set_nonblock_channel_fd(rxq_obj->fd);
1029 "port %u failed to make Rx interrupt file"
1030 " descriptor %d non-blocking for queue index"
1032 dev->data->port_id, rxq_obj->fd, i);
1033 mlx5_rx_intr_vec_disable(dev);
1036 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
1037 intr_handle->efds[count] = rxq_obj->fd;
1041 mlx5_rx_intr_vec_disable(dev);
1043 intr_handle->nb_efd = count;
1048 * Clean up Rx interrupts handler.
1051 * Pointer to Ethernet device.
1054 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
1056 struct mlx5_priv *priv = dev->data->dev_private;
1057 struct rte_intr_handle *intr_handle = dev->intr_handle;
1059 unsigned int rxqs_n = priv->rxqs_n;
1060 unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
1062 if (!dev->data->dev_conf.intr_conf.rxq)
1064 if (!intr_handle->intr_vec)
1066 for (i = 0; i != n; ++i) {
1067 struct mlx5_rxq_ctrl *rxq_ctrl;
1068 struct mlx5_rxq_data *rxq_data;
1070 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
1071 RTE_MAX_RXTX_INTR_VEC_ID)
1074 * Need to access directly the queue to release the reference
1075 * kept in mlx5_rx_intr_vec_enable().
1077 rxq_data = (*priv->rxqs)[i];
1078 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1080 mlx5_rxq_obj_release(rxq_ctrl->obj);
1083 rte_intr_free_epoll_fd(intr_handle);
1084 if (intr_handle->intr_vec)
1085 mlx5_free(intr_handle->intr_vec);
1086 intr_handle->nb_efd = 0;
1087 intr_handle->intr_vec = NULL;
1091 * MLX5 CQ notification .
1094 * Pointer to receive queue structure.
1096 * Sequence number per receive queue .
1099 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
1102 uint32_t doorbell_hi;
1104 void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
1106 sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
1107 doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
1108 doorbell = (uint64_t)doorbell_hi << 32;
1109 doorbell |= rxq->cqn;
1110 rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
1111 mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
1112 cq_db_reg, rxq->uar_lock_cq);
1116 * DPDK callback for Rx queue interrupt enable.
1119 * Pointer to Ethernet device structure.
1120 * @param rx_queue_id
1124 * 0 on success, a negative errno value otherwise and rte_errno is set.
1127 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1129 struct mlx5_priv *priv = dev->data->dev_private;
1130 struct mlx5_rxq_data *rxq_data;
1131 struct mlx5_rxq_ctrl *rxq_ctrl;
1133 rxq_data = (*priv->rxqs)[rx_queue_id];
1138 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1139 if (rxq_ctrl->irq) {
1140 struct mlx5_rxq_obj *rxq_obj;
1142 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
1147 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
1148 mlx5_rxq_obj_release(rxq_obj);
1154 * DPDK callback for Rx queue interrupt disable.
1157 * Pointer to Ethernet device structure.
1158 * @param rx_queue_id
1162 * 0 on success, a negative errno value otherwise and rte_errno is set.
1165 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1167 struct mlx5_priv *priv = dev->data->dev_private;
1168 struct mlx5_rxq_data *rxq_data;
1169 struct mlx5_rxq_ctrl *rxq_ctrl;
1170 struct mlx5_rxq_obj *rxq_obj = NULL;
1171 struct ibv_cq *ev_cq;
1175 rxq_data = (*priv->rxqs)[rx_queue_id];
1180 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1183 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
1188 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1189 ret = mlx5_glue->get_cq_event(rxq_obj->ibv_channel, &ev_cq,
1191 if (ret < 0 || ev_cq != rxq_obj->ibv_cq)
1193 mlx5_glue->ack_cq_events(rxq_obj->ibv_cq, 1);
1194 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1195 #ifdef HAVE_IBV_DEVX_EVENT
1197 struct mlx5dv_devx_async_event_hdr event_resp;
1198 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr)
1202 ret = mlx5_glue->devx_get_event
1203 (rxq_obj->devx_channel, &out.event_resp,
1205 if (ret < 0 || out.event_resp.cookie !=
1206 (uint64_t)(uintptr_t)rxq_obj->devx_cq)
1208 #endif /* HAVE_IBV_DEVX_EVENT */
1210 rxq_data->cq_arm_sn++;
1211 mlx5_rxq_obj_release(rxq_obj);
1215 * For ret < 0 save the errno (may be EAGAIN which means the get_event
1216 * function was called before receiving one).
1222 ret = rte_errno; /* Save rte_errno before cleanup. */
1224 mlx5_rxq_obj_release(rxq_obj);
1226 DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
1227 dev->data->port_id, rx_queue_id);
1228 rte_errno = ret; /* Restore rte_errno. */
1233 * Create a CQ Verbs object.
1236 * Pointer to Ethernet device.
1238 * Pointer to device private data.
1240 * Pointer to Rx queue data.
1242 * Number of CQEs in CQ.
1244 * Pointer to Rx queue object data.
1247 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1249 static struct ibv_cq *
1250 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1251 struct mlx5_rxq_data *rxq_data,
1252 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
1255 struct ibv_cq_init_attr_ex ibv;
1256 struct mlx5dv_cq_init_attr mlx5;
1259 cq_attr.ibv = (struct ibv_cq_init_attr_ex){
1261 .channel = rxq_obj->ibv_channel,
1264 cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
1267 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
1269 cq_attr.mlx5.comp_mask |=
1270 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1271 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1272 cq_attr.mlx5.cqe_comp_res_format =
1273 mlx5_rxq_mprq_enabled(rxq_data) ?
1274 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1275 MLX5DV_CQE_RES_FORMAT_HASH;
1277 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1280 * For vectorized Rx, it must not be doubled in order to
1281 * make cq_ci and rq_ci aligned.
1283 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1284 cq_attr.ibv.cqe *= 2;
1285 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1287 "port %u Rx CQE compression is disabled for HW"
1289 dev->data->port_id);
1290 } else if (priv->config.cqe_comp && rxq_data->lro) {
1292 "port %u Rx CQE compression is disabled for LRO",
1293 dev->data->port_id);
1295 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1296 if (priv->config.cqe_pad) {
1297 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1298 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1301 return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1307 * Create a WQ Verbs object.
1310 * Pointer to Ethernet device.
1312 * Pointer to device private data.
1314 * Pointer to Rx queue data.
1316 * Queue index in DPDK Rx queue array
1318 * Number of WQEs in WQ.
1320 * Pointer to Rx queue object data.
1323 * The Verbs object initialised, NULL otherwise and rte_errno is set.
1325 static struct ibv_wq *
1326 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1327 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1328 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1331 struct ibv_wq_init_attr ibv;
1332 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1333 struct mlx5dv_wq_init_attr mlx5;
1337 wq_attr.ibv = (struct ibv_wq_init_attr){
1338 .wq_context = NULL, /* Could be useful in the future. */
1339 .wq_type = IBV_WQT_RQ,
1340 /* Max number of outstanding WRs. */
1341 .max_wr = wqe_n >> rxq_data->sges_n,
1342 /* Max number of scatter/gather elements in a WR. */
1343 .max_sge = 1 << rxq_data->sges_n,
1345 .cq = rxq_obj->ibv_cq,
1346 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1347 .create_flags = (rxq_data->vlan_strip ?
1348 IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1350 /* By default, FCS (CRC) is stripped by hardware. */
1351 if (rxq_data->crc_present) {
1352 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1353 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1355 if (priv->config.hw_padding) {
1356 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1357 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1358 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1359 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1360 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1361 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1364 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1365 wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1368 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1369 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1370 &wq_attr.mlx5.striding_rq_attrs;
1372 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1373 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1374 .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1375 .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1376 .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1379 rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1382 rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1386 * Make sure number of WRs*SGEs match expectations since a queue
1387 * cannot allocate more than "desc" buffers.
1389 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1390 wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1392 "port %u Rx queue %u requested %u*%u but got"
1394 dev->data->port_id, idx,
1395 wqe_n >> rxq_data->sges_n,
1396 (1 << rxq_data->sges_n),
1397 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1398 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1407 * Fill common fields of create RQ attributes structure.
1410 * Pointer to Rx queue data.
1412 * CQ number to use with this RQ.
1414 * RQ attributes structure to fill..
1417 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1418 struct mlx5_devx_create_rq_attr *rq_attr)
1420 rq_attr->state = MLX5_RQC_STATE_RST;
1421 rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1423 rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1427 * Fill common fields of DevX WQ attributes structure.
1430 * Pointer to device private data.
1432 * Pointer to Rx queue control structure.
1434 * WQ attributes structure to fill..
1437 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1438 struct mlx5_devx_wq_attr *wq_attr)
1440 wq_attr->end_padding_mode = priv->config.cqe_pad ?
1441 MLX5_WQ_END_PAD_MODE_ALIGN :
1442 MLX5_WQ_END_PAD_MODE_NONE;
1443 wq_attr->pd = priv->sh->pdn;
1444 wq_attr->dbr_addr = rxq_ctrl->rq_dbr_offset;
1445 wq_attr->dbr_umem_id = rxq_ctrl->rq_dbr_umem_id;
1446 wq_attr->dbr_umem_valid = 1;
1447 wq_attr->wq_umem_id = mlx5_os_get_umem_id(rxq_ctrl->wq_umem);
1448 wq_attr->wq_umem_valid = 1;
1452 * Create a RQ object using DevX.
1455 * Pointer to Ethernet device.
1457 * Queue index in DPDK Rx queue array
1459 * CQ number to use with this RQ.
1462 * The DevX object initialised, NULL otherwise and rte_errno is set.
1464 static struct mlx5_devx_obj *
1465 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1467 struct mlx5_priv *priv = dev->data->dev_private;
1468 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1469 struct mlx5_rxq_ctrl *rxq_ctrl =
1470 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1471 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
1472 uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1473 uint32_t wq_size = 0;
1474 uint32_t wqe_size = 0;
1475 uint32_t log_wqe_size = 0;
1477 struct mlx5_devx_obj *rq;
1479 /* Fill RQ attributes. */
1480 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1481 rq_attr.flush_in_error_en = 1;
1482 mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1483 /* Fill WQ attributes for this RQ. */
1484 if (mlx5_rxq_mprq_enabled(rxq_data)) {
1485 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1487 * Number of strides in each WQE:
1488 * 512*2^single_wqe_log_num_of_strides.
1490 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1491 rxq_data->strd_num_n -
1492 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1493 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1494 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1495 rxq_data->strd_sz_n -
1496 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1497 wqe_size = sizeof(struct mlx5_wqe_mprq);
1499 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1500 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1502 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1503 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1504 rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1505 /* Calculate and allocate WQ memory space. */
1506 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1507 wq_size = wqe_n * wqe_size;
1508 size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
1509 if (alignment == (size_t)-1) {
1510 DRV_LOG(ERR, "Failed to get mem page size");
1514 buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
1515 alignment, rxq_ctrl->socket);
1518 rxq_data->wqes = buf;
1519 rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1521 if (!rxq_ctrl->wq_umem) {
1525 mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1526 rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1528 rxq_release_devx_rq_resources(rxq_ctrl);
1533 * Create a DevX CQ object for an Rx queue.
1536 * Pointer to Ethernet device.
1538 * Number of CQEs in CQ.
1540 * Queue index in DPDK Rx queue array
1542 * Pointer to Rx queue object data.
1545 * The DevX object initialised, NULL otherwise and rte_errno is set.
1547 static struct mlx5_devx_obj *
1548 mlx5_devx_cq_new(struct rte_eth_dev *dev, unsigned int cqe_n, uint16_t idx,
1549 struct mlx5_rxq_obj *rxq_obj)
1551 struct mlx5_devx_obj *cq_obj = 0;
1552 struct mlx5_devx_cq_attr cq_attr = { 0 };
1553 struct mlx5_priv *priv = dev->data->dev_private;
1554 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1555 struct mlx5_rxq_ctrl *rxq_ctrl =
1556 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1557 size_t page_size = rte_mem_page_size();
1558 uint32_t lcore = (uint32_t)rte_lcore_to_cpu_id(-1);
1561 uint16_t event_nums[1] = {0};
1566 if (page_size == (size_t)-1) {
1567 DRV_LOG(ERR, "Failed to get page_size.");
1570 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
1572 cq_attr.cqe_comp_en = MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
1573 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1574 cq_attr.mini_cqe_res_format =
1575 mlx5_rxq_mprq_enabled(rxq_data) ?
1576 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
1577 MLX5DV_CQE_RES_FORMAT_HASH;
1579 cq_attr.mini_cqe_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1582 * For vectorized Rx, it must not be doubled in order to
1583 * make cq_ci and rq_ci aligned.
1585 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1587 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1589 "port %u Rx CQE compression is disabled for HW"
1591 dev->data->port_id);
1592 } else if (priv->config.cqe_comp && rxq_data->lro) {
1594 "port %u Rx CQE compression is disabled for LRO",
1595 dev->data->port_id);
1597 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1598 if (priv->config.cqe_pad)
1599 cq_attr.cqe_size = MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1601 log_cqe_n = log2above(cqe_n);
1602 cq_size = sizeof(struct mlx5_cqe) * (1 << log_cqe_n);
1603 /* Query the EQN for this core. */
1604 if (mlx5_glue->devx_query_eqn(priv->sh->ctx, lcore, &eqn)) {
1605 DRV_LOG(ERR, "Failed to query EQN for CQ.");
1609 buf = rte_calloc_socket(__func__, 1, cq_size, page_size,
1612 DRV_LOG(ERR, "Failed to allocate memory for CQ.");
1615 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)buf;
1616 rxq_ctrl->cq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, buf,
1618 IBV_ACCESS_LOCAL_WRITE);
1619 if (!rxq_ctrl->cq_umem) {
1620 DRV_LOG(ERR, "Failed to register umem for CQ.");
1623 cq_attr.uar_page_id =
1624 mlx5_os_get_devx_uar_page_id(priv->sh->devx_rx_uar);
1625 cq_attr.q_umem_id = mlx5_os_get_umem_id(rxq_ctrl->cq_umem);
1626 cq_attr.q_umem_valid = 1;
1627 cq_attr.log_cq_size = log_cqe_n;
1628 cq_attr.log_page_size = rte_log2_u32(page_size);
1629 cq_attr.db_umem_offset = rxq_ctrl->cq_dbr_offset;
1630 cq_attr.db_umem_id = rxq_ctrl->cq_dbr_umem_id;
1631 cq_attr.db_umem_valid = rxq_ctrl->cq_dbr_umem_id_valid;
1632 cq_obj = mlx5_devx_cmd_create_cq(priv->sh->ctx, &cq_attr);
1635 rxq_data->cqe_n = log_cqe_n;
1636 rxq_data->cqn = cq_obj->id;
1637 if (rxq_obj->devx_channel) {
1638 ret = mlx5_glue->devx_subscribe_devx_event
1639 (rxq_obj->devx_channel,
1643 (uint64_t)(uintptr_t)cq_obj);
1645 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
1650 /* Initialise CQ to 1's to mark HW ownership for all CQEs. */
1651 memset((void *)(uintptr_t)rxq_data->cqes, 0xFF, cq_size);
1655 mlx5_devx_cmd_destroy(cq_obj);
1656 rxq_release_devx_cq_resources(rxq_ctrl);
1661 * Create the Rx hairpin queue object.
1664 * Pointer to Ethernet device.
1666 * Queue index in DPDK Rx queue array
1669 * The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1671 static struct mlx5_rxq_obj *
1672 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1674 struct mlx5_priv *priv = dev->data->dev_private;
1675 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1676 struct mlx5_rxq_ctrl *rxq_ctrl =
1677 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1678 struct mlx5_devx_create_rq_attr attr = { 0 };
1679 struct mlx5_rxq_obj *tmpl = NULL;
1680 uint32_t max_wq_data;
1682 MLX5_ASSERT(rxq_data);
1683 MLX5_ASSERT(!rxq_ctrl->obj);
1684 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1688 "port %u Rx queue %u cannot allocate verbs resources",
1689 dev->data->port_id, rxq_data->idx);
1693 tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1694 tmpl->rxq_ctrl = rxq_ctrl;
1696 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1697 /* Jumbo frames > 9KB should be supported, and more packets. */
1698 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1699 if (priv->config.log_hp_size > max_wq_data) {
1700 DRV_LOG(ERR, "total data size %u power of 2 is "
1701 "too large for hairpin",
1702 priv->config.log_hp_size);
1707 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1709 attr.wq_attr.log_hairpin_data_sz =
1710 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1711 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1713 /* Set the packets number to the maximum value for performance. */
1714 attr.wq_attr.log_hairpin_num_packets =
1715 attr.wq_attr.log_hairpin_data_sz -
1716 MLX5_HAIRPIN_QUEUE_STRIDE;
1717 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1721 "port %u Rx hairpin queue %u can't create rq object",
1722 dev->data->port_id, idx);
1727 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1728 idx, (void *)&tmpl);
1729 rte_atomic32_inc(&tmpl->refcnt);
1730 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1731 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1732 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
1737 * Create the Rx queue Verbs/DevX object.
1740 * Pointer to Ethernet device.
1742 * Queue index in DPDK Rx queue array
1744 * Type of Rx queue object to create.
1747 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1749 struct mlx5_rxq_obj *
1750 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1751 enum mlx5_rxq_obj_type type)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1755 struct mlx5_rxq_ctrl *rxq_ctrl =
1756 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1757 struct ibv_wq_attr mod;
1759 unsigned int wqe_n = 1 << rxq_data->elts_n;
1760 struct mlx5_rxq_obj *tmpl = NULL;
1761 struct mlx5dv_cq cq_info;
1762 struct mlx5dv_rwq rwq;
1764 struct mlx5dv_obj obj;
1766 MLX5_ASSERT(rxq_data);
1767 MLX5_ASSERT(!rxq_ctrl->obj);
1768 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1769 return mlx5_rxq_obj_hairpin_new(dev, idx);
1770 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1771 priv->verbs_alloc_ctx.obj = rxq_ctrl;
1772 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
1776 "port %u Rx queue %u cannot allocate resources",
1777 dev->data->port_id, rxq_data->idx);
1782 tmpl->rxq_ctrl = rxq_ctrl;
1783 if (rxq_ctrl->irq) {
1784 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1786 mlx5_glue->create_comp_channel(priv->sh->ctx);
1787 if (!tmpl->ibv_channel) {
1788 DRV_LOG(ERR, "port %u: comp channel creation "
1789 "failure", dev->data->port_id);
1793 tmpl->fd = tmpl->ibv_channel->fd;
1794 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1796 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
1798 tmpl->devx_channel =
1799 mlx5_glue->devx_create_event_channel
1802 if (!tmpl->devx_channel) {
1805 "Failed to create event channel %d.",
1810 mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
1813 if (mlx5_rxq_mprq_enabled(rxq_data))
1814 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1817 DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1818 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1819 DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1820 dev->data->port_id, priv->sh->device_attr.max_sge);
1821 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1822 /* Create CQ using Verbs API. */
1823 tmpl->ibv_cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n,
1825 if (!tmpl->ibv_cq) {
1826 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1827 dev->data->port_id, idx);
1831 obj.cq.in = tmpl->ibv_cq;
1832 obj.cq.out = &cq_info;
1833 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1838 if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1840 "port %u wrong MLX5_CQE_SIZE environment "
1841 "variable value: it should be set to %u",
1842 dev->data->port_id, RTE_CACHE_LINE_SIZE);
1846 /* Fill the rings. */
1847 rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1848 rxq_data->cq_db = cq_info.dbrec;
1850 (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1851 rxq_data->cq_uar = cq_info.cq_uar;
1852 rxq_data->cqn = cq_info.cqn;
1853 /* Create WQ (RQ) using Verbs API. */
1854 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1857 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1858 dev->data->port_id, idx);
1862 /* Change queue state to ready. */
1863 mod = (struct ibv_wq_attr){
1864 .attr_mask = IBV_WQ_ATTR_STATE,
1865 .wq_state = IBV_WQS_RDY,
1867 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1870 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1871 " failed", dev->data->port_id, idx);
1875 obj.rwq.in = tmpl->wq;
1877 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1882 rxq_data->wqes = rwq.buf;
1883 rxq_data->rq_db = rwq.dbrec;
1884 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1885 struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
1886 struct mlx5_devx_dbr_page *dbr_page;
1889 /* Allocate CQ door-bell. */
1890 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1892 if (dbr_offset < 0) {
1893 DRV_LOG(ERR, "Failed to allocate CQ door-bell.");
1896 rxq_ctrl->cq_dbr_offset = dbr_offset;
1897 rxq_ctrl->cq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1898 rxq_ctrl->cq_dbr_umem_id_valid = 1;
1900 (uint32_t *)((uintptr_t)dbr_page->dbrs +
1901 (uintptr_t)rxq_ctrl->cq_dbr_offset);
1903 mlx5_os_get_devx_uar_base_addr(priv->sh->devx_rx_uar);
1904 /* Create CQ using DevX API. */
1905 tmpl->devx_cq = mlx5_devx_cq_new(dev, cqe_n, idx, tmpl);
1906 if (!tmpl->devx_cq) {
1907 DRV_LOG(ERR, "Failed to create CQ.");
1910 /* Allocate RQ door-bell. */
1911 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1913 if (dbr_offset < 0) {
1914 DRV_LOG(ERR, "Failed to allocate RQ door-bell.");
1917 rxq_ctrl->rq_dbr_offset = dbr_offset;
1918 rxq_ctrl->rq_dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1919 rxq_ctrl->rq_dbr_umem_id_valid = 1;
1921 (uint32_t *)((uintptr_t)dbr_page->dbrs +
1922 (uintptr_t)rxq_ctrl->rq_dbr_offset);
1923 /* Create RQ using DevX API. */
1924 tmpl->rq = mlx5_devx_rq_new(dev, idx, tmpl->devx_cq->id);
1926 DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1927 dev->data->port_id, idx);
1931 /* Change queue state to ready. */
1932 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1933 rq_attr.state = MLX5_RQC_STATE_RDY;
1934 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1938 rxq_data->cq_arm_sn = 0;
1939 mlx5_rxq_initialize(rxq_data);
1940 rxq_data->cq_ci = 0;
1941 DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1942 idx, (void *)&tmpl);
1943 rte_atomic32_inc(&tmpl->refcnt);
1944 LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1945 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1946 dev->data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1950 ret = rte_errno; /* Save rte_errno before cleanup. */
1951 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1953 claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1955 claim_zero(mlx5_glue->destroy_cq(tmpl->ibv_cq));
1956 if (tmpl->ibv_channel)
1957 claim_zero(mlx5_glue->destroy_comp_channel
1958 (tmpl->ibv_channel));
1959 } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1961 claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1963 claim_zero(mlx5_devx_cmd_destroy
1965 if (tmpl->devx_channel)
1966 mlx5_glue->devx_destroy_event_channel
1967 (tmpl->devx_channel);
1970 rte_errno = ret; /* Restore rte_errno. */
1972 if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1973 rxq_release_devx_rq_resources(rxq_ctrl);
1974 rxq_release_devx_cq_resources(rxq_ctrl);
1976 priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1981 * Verify the Rx queue objects list is empty
1984 * Pointer to Ethernet device.
1987 * The number of objects not released.
1990 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1992 struct mlx5_priv *priv = dev->data->dev_private;
1994 struct mlx5_rxq_obj *rxq_obj;
1996 LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1997 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1998 dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
2005 * Callback function to initialize mbufs for Multi-Packet RQ.
2008 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
2009 void *_m, unsigned int i __rte_unused)
2011 struct mlx5_mprq_buf *buf = _m;
2012 struct rte_mbuf_ext_shared_info *shinfo;
2013 unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
2016 memset(_m, 0, sizeof(*buf));
2018 rte_atomic16_set(&buf->refcnt, 1);
2019 for (j = 0; j != strd_n; ++j) {
2020 shinfo = &buf->shinfos[j];
2021 shinfo->free_cb = mlx5_mprq_buf_free_cb;
2022 shinfo->fcb_opaque = buf;
2027 * Free mempool of Multi-Packet RQ.
2030 * Pointer to Ethernet device.
2033 * 0 on success, negative errno value on failure.
2036 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
2038 struct mlx5_priv *priv = dev->data->dev_private;
2039 struct rte_mempool *mp = priv->mprq_mp;
2044 DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
2045 dev->data->port_id, mp->name);
2047 * If a buffer in the pool has been externally attached to a mbuf and it
2048 * is still in use by application, destroying the Rx queue can spoil
2049 * the packet. It is unlikely to happen but if application dynamically
2050 * creates and destroys with holding Rx packets, this can happen.
2052 * TODO: It is unavoidable for now because the mempool for Multi-Packet
2053 * RQ isn't provided by application but managed by PMD.
2055 if (!rte_mempool_full(mp)) {
2057 "port %u mempool for Multi-Packet RQ is still in use",
2058 dev->data->port_id);
2062 rte_mempool_free(mp);
2063 /* Unset mempool for each Rx queue. */
2064 for (i = 0; i != priv->rxqs_n; ++i) {
2065 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2069 rxq->mprq_mp = NULL;
2071 priv->mprq_mp = NULL;
2076 * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
2077 * mempool. If already allocated, reuse it if there're enough elements.
2078 * Otherwise, resize it.
2081 * Pointer to Ethernet device.
2084 * 0 on success, negative errno value on failure.
2087 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
2089 struct mlx5_priv *priv = dev->data->dev_private;
2090 struct rte_mempool *mp = priv->mprq_mp;
2091 char name[RTE_MEMPOOL_NAMESIZE];
2092 unsigned int desc = 0;
2093 unsigned int buf_len;
2094 unsigned int obj_num;
2095 unsigned int obj_size;
2096 unsigned int strd_num_n = 0;
2097 unsigned int strd_sz_n = 0;
2099 unsigned int n_ibv = 0;
2101 if (!mlx5_mprq_enabled(dev))
2103 /* Count the total number of descriptors configured. */
2104 for (i = 0; i != priv->rxqs_n; ++i) {
2105 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2106 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
2107 (rxq, struct mlx5_rxq_ctrl, rxq);
2109 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
2112 desc += 1 << rxq->elts_n;
2113 /* Get the max number of strides. */
2114 if (strd_num_n < rxq->strd_num_n)
2115 strd_num_n = rxq->strd_num_n;
2116 /* Get the max size of a stride. */
2117 if (strd_sz_n < rxq->strd_sz_n)
2118 strd_sz_n = rxq->strd_sz_n;
2120 MLX5_ASSERT(strd_num_n && strd_sz_n);
2121 buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
2122 obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
2123 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
2125 * Received packets can be either memcpy'd or externally referenced. In
2126 * case that the packet is attached to an mbuf as an external buffer, as
2127 * it isn't possible to predict how the buffers will be queued by
2128 * application, there's no option to exactly pre-allocate needed buffers
2129 * in advance but to speculatively prepares enough buffers.
2131 * In the data path, if this Mempool is depleted, PMD will try to memcpy
2132 * received packets to buffers provided by application (rxq->mp) until
2133 * this Mempool gets available again.
2136 obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
2138 * rte_mempool_create_empty() has sanity check to refuse large cache
2139 * size compared to the number of elements.
2140 * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
2141 * constant number 2 instead.
2143 obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
2144 /* Check a mempool is already allocated and if it can be resued. */
2145 if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
2146 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
2147 dev->data->port_id, mp->name);
2150 } else if (mp != NULL) {
2151 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
2152 dev->data->port_id, mp->name);
2154 * If failed to free, which means it may be still in use, no way
2155 * but to keep using the existing one. On buffer underrun,
2156 * packets will be memcpy'd instead of external buffer
2159 if (mlx5_mprq_free_mp(dev)) {
2160 if (mp->elt_size >= obj_size)
2166 snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
2167 mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
2168 0, NULL, NULL, mlx5_mprq_buf_init,
2169 (void *)(uintptr_t)(1 << strd_num_n),
2170 dev->device->numa_node, 0);
2173 "port %u failed to allocate a mempool for"
2174 " Multi-Packet RQ, count=%u, size=%u",
2175 dev->data->port_id, obj_num, obj_size);
2181 /* Set mempool for each Rx queue. */
2182 for (i = 0; i != priv->rxqs_n; ++i) {
2183 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
2184 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
2185 (rxq, struct mlx5_rxq_ctrl, rxq);
2187 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
2191 DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
2192 dev->data->port_id);
2196 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
2197 sizeof(struct rte_vlan_hdr) * 2 + \
2198 sizeof(struct rte_ipv6_hdr)))
2199 #define MAX_TCP_OPTION_SIZE 40u
2200 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
2201 sizeof(struct rte_tcp_hdr) + \
2202 MAX_TCP_OPTION_SIZE))
2205 * Adjust the maximum LRO massage size.
2208 * Pointer to Ethernet device.
2211 * @param max_lro_size
2212 * The maximum size for LRO packet.
2215 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
2216 uint32_t max_lro_size)
2218 struct mlx5_priv *priv = dev->data->dev_private;
2220 if (priv->config.hca_attr.lro_max_msg_sz_mode ==
2221 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
2222 MLX5_MAX_TCP_HDR_OFFSET)
2223 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
2224 max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
2225 MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
2226 max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
2227 if (priv->max_lro_msg_size)
2228 priv->max_lro_msg_size =
2229 RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
2231 priv->max_lro_msg_size = max_lro_size;
2233 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
2234 dev->data->port_id, idx,
2235 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
2239 * Create a DPDK Rx queue.
2242 * Pointer to Ethernet device.
2246 * Number of descriptors to configure in queue.
2248 * NUMA socket on which memory must be allocated.
2251 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2253 struct mlx5_rxq_ctrl *
2254 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2255 unsigned int socket, const struct rte_eth_rxconf *conf,
2256 struct rte_mempool *mp)
2258 struct mlx5_priv *priv = dev->data->dev_private;
2259 struct mlx5_rxq_ctrl *tmpl;
2260 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
2261 unsigned int mprq_stride_nums;
2262 unsigned int mprq_stride_size;
2263 unsigned int mprq_stride_cap;
2264 struct mlx5_dev_config *config = &priv->config;
2266 * Always allocate extra slots, even if eventually
2267 * the vector Rx will not be used.
2270 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
2271 uint64_t offloads = conf->offloads |
2272 dev->data->dev_conf.rxmode.offloads;
2273 unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
2274 const int mprq_en = mlx5_check_mprq_support(dev) > 0;
2275 unsigned int max_rx_pkt_len = lro_on_queue ?
2276 dev->data->dev_conf.rxmode.max_lro_pkt_size :
2277 dev->data->dev_conf.rxmode.max_rx_pkt_len;
2278 unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
2279 RTE_PKTMBUF_HEADROOM;
2280 unsigned int max_lro_size = 0;
2281 unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
2283 if (non_scatter_min_mbuf_size > mb_len && !(offloads &
2284 DEV_RX_OFFLOAD_SCATTER)) {
2285 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
2286 " configured and no enough mbuf space(%u) to contain "
2287 "the maximum RX packet length(%u) with head-room(%u)",
2288 dev->data->port_id, idx, mb_len, max_rx_pkt_len,
2289 RTE_PKTMBUF_HEADROOM);
2293 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl) +
2294 desc_n * sizeof(struct rte_mbuf *), 0, socket);
2299 tmpl->type = MLX5_RXQ_TYPE_STANDARD;
2300 if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
2301 MLX5_MR_BTREE_CACHE_N, socket)) {
2302 /* rte_errno is already set. */
2305 tmpl->socket = socket;
2306 if (dev->data->dev_conf.intr_conf.rxq)
2308 mprq_stride_nums = config->mprq.stride_num_n ?
2309 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
2310 mprq_stride_size = non_scatter_min_mbuf_size <=
2311 (1U << config->mprq.max_stride_size_n) ?
2312 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
2313 mprq_stride_cap = (config->mprq.stride_num_n ?
2314 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
2315 (config->mprq.stride_size_n ?
2316 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
2318 * This Rx queue can be configured as a Multi-Packet RQ if all of the
2319 * following conditions are met:
2320 * - MPRQ is enabled.
2321 * - The number of descs is more than the number of strides.
2322 * - max_rx_pkt_len plus overhead is less than the max size
2323 * of a stride or mprq_stride_size is specified by a user.
2324 * Need to nake sure that there are enough stides to encap
2325 * the maximum packet size in case mprq_stride_size is set.
2326 * Otherwise, enable Rx scatter if necessary.
2328 if (mprq_en && desc > (1U << mprq_stride_nums) &&
2329 (non_scatter_min_mbuf_size <=
2330 (1U << config->mprq.max_stride_size_n) ||
2331 (config->mprq.stride_size_n &&
2332 non_scatter_min_mbuf_size <= mprq_stride_cap))) {
2333 /* TODO: Rx scatter isn't supported yet. */
2334 tmpl->rxq.sges_n = 0;
2335 /* Trim the number of descs needed. */
2336 desc >>= mprq_stride_nums;
2337 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
2338 config->mprq.stride_num_n : mprq_stride_nums;
2339 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
2340 config->mprq.stride_size_n : mprq_stride_size;
2341 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
2342 tmpl->rxq.strd_scatter_en =
2343 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
2344 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
2345 config->mprq.max_memcpy_len);
2346 max_lro_size = RTE_MIN(max_rx_pkt_len,
2347 (1u << tmpl->rxq.strd_num_n) *
2348 (1u << tmpl->rxq.strd_sz_n));
2350 "port %u Rx queue %u: Multi-Packet RQ is enabled"
2351 " strd_num_n = %u, strd_sz_n = %u",
2352 dev->data->port_id, idx,
2353 tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
2354 } else if (max_rx_pkt_len <= first_mb_free_size) {
2355 tmpl->rxq.sges_n = 0;
2356 max_lro_size = max_rx_pkt_len;
2357 } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
2358 unsigned int size = non_scatter_min_mbuf_size;
2359 unsigned int sges_n;
2361 if (lro_on_queue && first_mb_free_size <
2362 MLX5_MAX_LRO_HEADER_FIX) {
2363 DRV_LOG(ERR, "Not enough space in the first segment(%u)"
2364 " to include the max header size(%u) for LRO",
2365 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
2366 rte_errno = ENOTSUP;
2370 * Determine the number of SGEs needed for a full packet
2371 * and round it to the next power of two.
2373 sges_n = log2above((size / mb_len) + !!(size % mb_len));
2374 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
2376 "port %u too many SGEs (%u) needed to handle"
2377 " requested maximum packet size %u, the maximum"
2378 " supported are %u", dev->data->port_id,
2379 1 << sges_n, max_rx_pkt_len,
2380 1u << MLX5_MAX_LOG_RQ_SEGS);
2381 rte_errno = ENOTSUP;
2384 tmpl->rxq.sges_n = sges_n;
2385 max_lro_size = max_rx_pkt_len;
2387 if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
2389 "port %u MPRQ is requested but cannot be enabled\n"
2390 " (requested: pkt_sz = %u, desc_num = %u,"
2391 " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
2392 " supported: min_rxqs_num = %u,"
2393 " min_stride_sz = %u, max_stride_sz = %u).",
2394 dev->data->port_id, non_scatter_min_mbuf_size,
2396 config->mprq.stride_size_n ?
2397 (1U << config->mprq.stride_size_n) :
2398 (1U << mprq_stride_size),
2399 config->mprq.stride_num_n ?
2400 (1U << config->mprq.stride_num_n) :
2401 (1U << mprq_stride_nums),
2402 config->mprq.min_rxqs_num,
2403 (1U << config->mprq.min_stride_size_n),
2404 (1U << config->mprq.max_stride_size_n));
2405 DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
2406 dev->data->port_id, 1 << tmpl->rxq.sges_n);
2407 if (desc % (1 << tmpl->rxq.sges_n)) {
2409 "port %u number of Rx queue descriptors (%u) is not a"
2410 " multiple of SGEs per packet (%u)",
2413 1 << tmpl->rxq.sges_n);
2417 mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
2418 /* Toggle RX checksum offload if hardware supports it. */
2419 tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
2420 tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
2421 /* Configure VLAN stripping. */
2422 tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
2423 /* By default, FCS (CRC) is stripped by hardware. */
2424 tmpl->rxq.crc_present = 0;
2425 tmpl->rxq.lro = lro_on_queue;
2426 if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
2427 if (config->hw_fcs_strip) {
2429 * RQs used for LRO-enabled TIRs should not be
2430 * configured to scatter the FCS.
2434 "port %u CRC stripping has been "
2435 "disabled but will still be performed "
2436 "by hardware, because LRO is enabled",
2437 dev->data->port_id);
2439 tmpl->rxq.crc_present = 1;
2442 "port %u CRC stripping has been disabled but will"
2443 " still be performed by hardware, make sure MLNX_OFED"
2444 " and firmware are up to date",
2445 dev->data->port_id);
2449 "port %u CRC stripping is %s, %u bytes will be subtracted from"
2450 " incoming frames to hide it",
2452 tmpl->rxq.crc_present ? "disabled" : "enabled",
2453 tmpl->rxq.crc_present << 2);
2455 tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
2456 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
2457 tmpl->rxq.port_id = dev->data->port_id;
2460 tmpl->rxq.elts_n = log2above(desc);
2461 tmpl->rxq.rq_repl_thresh =
2462 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
2464 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
2466 tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
2468 tmpl->rxq.idx = idx;
2469 rte_atomic32_inc(&tmpl->refcnt);
2470 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2478 * Create a DPDK Rx hairpin queue.
2481 * Pointer to Ethernet device.
2485 * Number of descriptors to configure in queue.
2486 * @param hairpin_conf
2487 * The hairpin binding configuration.
2490 * A DPDK queue object on success, NULL otherwise and rte_errno is set.
2492 struct mlx5_rxq_ctrl *
2493 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2494 const struct rte_eth_hairpin_conf *hairpin_conf)
2496 struct mlx5_priv *priv = dev->data->dev_private;
2497 struct mlx5_rxq_ctrl *tmpl;
2499 tmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, sizeof(*tmpl), 0,
2505 tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2506 tmpl->socket = SOCKET_ID_ANY;
2507 tmpl->rxq.rss_hash = 0;
2508 tmpl->rxq.port_id = dev->data->port_id;
2510 tmpl->rxq.mp = NULL;
2511 tmpl->rxq.elts_n = log2above(desc);
2512 tmpl->rxq.elts = NULL;
2513 tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2514 tmpl->hairpin_conf = *hairpin_conf;
2515 tmpl->rxq.idx = idx;
2516 rte_atomic32_inc(&tmpl->refcnt);
2517 LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2525 * Pointer to Ethernet device.
2530 * A pointer to the queue if it exists, NULL otherwise.
2532 struct mlx5_rxq_ctrl *
2533 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2535 struct mlx5_priv *priv = dev->data->dev_private;
2536 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2538 if ((*priv->rxqs)[idx]) {
2539 rxq_ctrl = container_of((*priv->rxqs)[idx],
2540 struct mlx5_rxq_ctrl,
2542 mlx5_rxq_obj_get(dev, idx);
2543 rte_atomic32_inc(&rxq_ctrl->refcnt);
2549 * Release a Rx queue.
2552 * Pointer to Ethernet device.
2557 * 1 while a reference on it exists, 0 when freed.
2560 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2562 struct mlx5_priv *priv = dev->data->dev_private;
2563 struct mlx5_rxq_ctrl *rxq_ctrl;
2565 if (!(*priv->rxqs)[idx])
2567 rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2568 MLX5_ASSERT(rxq_ctrl->priv);
2569 if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2570 rxq_ctrl->obj = NULL;
2571 if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2572 if (rxq_ctrl->rq_dbr_umem_id_valid)
2573 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2574 rxq_ctrl->rq_dbr_umem_id,
2575 rxq_ctrl->rq_dbr_offset));
2576 if (rxq_ctrl->cq_dbr_umem_id_valid)
2577 claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2578 rxq_ctrl->cq_dbr_umem_id,
2579 rxq_ctrl->cq_dbr_offset));
2580 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2581 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2582 LIST_REMOVE(rxq_ctrl, next);
2583 mlx5_free(rxq_ctrl);
2584 (*priv->rxqs)[idx] = NULL;
2591 * Verify the Rx Queue list is empty
2594 * Pointer to Ethernet device.
2597 * The number of object not released.
2600 mlx5_rxq_verify(struct rte_eth_dev *dev)
2602 struct mlx5_priv *priv = dev->data->dev_private;
2603 struct mlx5_rxq_ctrl *rxq_ctrl;
2606 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2607 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2608 dev->data->port_id, rxq_ctrl->rxq.idx);
2615 * Get a Rx queue type.
2618 * Pointer to Ethernet device.
2623 * The Rx queue type.
2626 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2628 struct mlx5_priv *priv = dev->data->dev_private;
2629 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2631 if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2632 rxq_ctrl = container_of((*priv->rxqs)[idx],
2633 struct mlx5_rxq_ctrl,
2635 return rxq_ctrl->type;
2637 return MLX5_RXQ_TYPE_UNDEFINED;
2641 * Create an indirection table.
2644 * Pointer to Ethernet device.
2646 * Queues entering in the indirection table.
2648 * Number of queues in the array.
2651 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2653 static struct mlx5_ind_table_obj *
2654 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2655 uint32_t queues_n, enum mlx5_ind_tbl_type type)
2657 struct mlx5_priv *priv = dev->data->dev_private;
2658 struct mlx5_ind_table_obj *ind_tbl;
2659 unsigned int i = 0, j = 0, k = 0;
2661 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl) +
2662 queues_n * sizeof(uint16_t), 0, SOCKET_ID_ANY);
2667 ind_tbl->type = type;
2668 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2669 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2670 log2above(queues_n) :
2671 log2above(priv->config.ind_table_max_size);
2672 struct ibv_wq *wq[1 << wq_n];
2674 for (i = 0; i != queues_n; ++i) {
2675 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2679 wq[i] = rxq->obj->wq;
2680 ind_tbl->queues[i] = queues[i];
2682 ind_tbl->queues_n = queues_n;
2683 /* Finalise indirection table. */
2684 k = i; /* Retain value of i for use in error case. */
2685 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2687 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2689 &(struct ibv_rwq_ind_table_init_attr){
2690 .log_ind_tbl_size = wq_n,
2694 if (!ind_tbl->ind_table) {
2698 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2699 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2700 const unsigned int rqt_n =
2701 1 << (rte_is_power_of_2(queues_n) ?
2702 log2above(queues_n) :
2703 log2above(priv->config.ind_table_max_size));
2705 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
2706 rqt_n * sizeof(uint32_t), 0,
2709 DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2710 dev->data->port_id);
2714 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2715 rqt_attr->rqt_actual_size = rqt_n;
2716 for (i = 0; i != queues_n; ++i) {
2717 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2721 rqt_attr->rq_list[i] = rxq->obj->rq->id;
2722 ind_tbl->queues[i] = queues[i];
2724 k = i; /* Retain value of i for use in error case. */
2725 for (j = 0; k != rqt_n; ++k, ++j)
2726 rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2727 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2729 mlx5_free(rqt_attr);
2730 if (!ind_tbl->rqt) {
2731 DRV_LOG(ERR, "port %u cannot create DevX RQT",
2732 dev->data->port_id);
2736 ind_tbl->queues_n = queues_n;
2738 rte_atomic32_inc(&ind_tbl->refcnt);
2739 LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2742 for (j = 0; j < i; j++)
2743 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2745 DEBUG("port %u cannot create indirection table", dev->data->port_id);
2750 * Get an indirection table.
2753 * Pointer to Ethernet device.
2755 * Queues entering in the indirection table.
2757 * Number of queues in the array.
2760 * An indirection table if found.
2762 static struct mlx5_ind_table_obj *
2763 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2766 struct mlx5_priv *priv = dev->data->dev_private;
2767 struct mlx5_ind_table_obj *ind_tbl;
2769 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2770 if ((ind_tbl->queues_n == queues_n) &&
2771 (memcmp(ind_tbl->queues, queues,
2772 ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2779 rte_atomic32_inc(&ind_tbl->refcnt);
2780 for (i = 0; i != ind_tbl->queues_n; ++i)
2781 mlx5_rxq_get(dev, ind_tbl->queues[i]);
2787 * Release an indirection table.
2790 * Pointer to Ethernet device.
2792 * Indirection table to release.
2795 * 1 while a reference on it exists, 0 when freed.
2798 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2799 struct mlx5_ind_table_obj *ind_tbl)
2803 if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2804 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2805 claim_zero(mlx5_glue->destroy_rwq_ind_table
2806 (ind_tbl->ind_table));
2807 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2808 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2810 for (i = 0; i != ind_tbl->queues_n; ++i)
2811 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2812 if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2813 LIST_REMOVE(ind_tbl, next);
2821 * Verify the Rx Queue list is empty
2824 * Pointer to Ethernet device.
2827 * The number of object not released.
2830 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2832 struct mlx5_priv *priv = dev->data->dev_private;
2833 struct mlx5_ind_table_obj *ind_tbl;
2836 LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2838 "port %u indirection table obj %p still referenced",
2839 dev->data->port_id, (void *)ind_tbl);
2846 * Create an Rx Hash queue.
2849 * Pointer to Ethernet device.
2851 * RSS key for the Rx hash queue.
2852 * @param rss_key_len
2854 * @param hash_fields
2855 * Verbs protocol hash field to make the RSS on.
2857 * Queues entering in hash queue. In case of empty hash_fields only the
2858 * first queue index will be taken for the indirection table.
2865 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2868 mlx5_hrxq_new(struct rte_eth_dev *dev,
2869 const uint8_t *rss_key, uint32_t rss_key_len,
2870 uint64_t hash_fields,
2871 const uint16_t *queues, uint32_t queues_n,
2872 int tunnel __rte_unused)
2874 struct mlx5_priv *priv = dev->data->dev_private;
2875 struct mlx5_hrxq *hrxq;
2876 uint32_t hrxq_idx = 0;
2877 struct ibv_qp *qp = NULL;
2878 struct mlx5_ind_table_obj *ind_tbl;
2880 struct mlx5_devx_obj *tir = NULL;
2881 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2882 struct mlx5_rxq_ctrl *rxq_ctrl =
2883 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2885 queues_n = hash_fields ? queues_n : 1;
2886 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2888 enum mlx5_ind_tbl_type type;
2890 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2891 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2892 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2898 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2899 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2900 struct mlx5dv_qp_init_attr qp_init_attr;
2902 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2904 qp_init_attr.comp_mask =
2905 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2906 qp_init_attr.create_flags =
2907 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2909 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2910 if (dev->data->dev_conf.lpbk_mode) {
2912 * Allow packet sent from NIC loop back
2913 * w/o source MAC check.
2915 qp_init_attr.comp_mask |=
2916 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2917 qp_init_attr.create_flags |=
2918 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2921 qp = mlx5_glue->dv_create_qp
2923 &(struct ibv_qp_init_attr_ex){
2924 .qp_type = IBV_QPT_RAW_PACKET,
2926 IBV_QP_INIT_ATTR_PD |
2927 IBV_QP_INIT_ATTR_IND_TABLE |
2928 IBV_QP_INIT_ATTR_RX_HASH,
2929 .rx_hash_conf = (struct ibv_rx_hash_conf){
2931 IBV_RX_HASH_FUNC_TOEPLITZ,
2932 .rx_hash_key_len = rss_key_len,
2934 (void *)(uintptr_t)rss_key,
2935 .rx_hash_fields_mask = hash_fields,
2937 .rwq_ind_tbl = ind_tbl->ind_table,
2942 qp = mlx5_glue->create_qp_ex
2944 &(struct ibv_qp_init_attr_ex){
2945 .qp_type = IBV_QPT_RAW_PACKET,
2947 IBV_QP_INIT_ATTR_PD |
2948 IBV_QP_INIT_ATTR_IND_TABLE |
2949 IBV_QP_INIT_ATTR_RX_HASH,
2950 .rx_hash_conf = (struct ibv_rx_hash_conf){
2952 IBV_RX_HASH_FUNC_TOEPLITZ,
2953 .rx_hash_key_len = rss_key_len,
2955 (void *)(uintptr_t)rss_key,
2956 .rx_hash_fields_mask = hash_fields,
2958 .rwq_ind_tbl = ind_tbl->ind_table,
2966 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2967 struct mlx5_devx_tir_attr tir_attr;
2971 /* Enable TIR LRO only if all the queues were configured for. */
2972 for (i = 0; i < queues_n; ++i) {
2973 if (!(*priv->rxqs)[queues[i]]->lro) {
2978 memset(&tir_attr, 0, sizeof(tir_attr));
2979 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2980 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2981 tir_attr.tunneled_offload_en = !!tunnel;
2982 /* If needed, translate hash_fields bitmap to PRM format. */
2984 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2985 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2986 hash_fields & IBV_RX_HASH_INNER ?
2987 &tir_attr.rx_hash_field_selector_inner :
2988 &tir_attr.rx_hash_field_selector_outer;
2990 struct mlx5_rx_hash_field_select *rx_hash_field_select =
2991 &tir_attr.rx_hash_field_selector_outer;
2994 /* 1 bit: 0: IPv4, 1: IPv6. */
2995 rx_hash_field_select->l3_prot_type =
2996 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2997 /* 1 bit: 0: TCP, 1: UDP. */
2998 rx_hash_field_select->l4_prot_type =
2999 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
3000 /* Bitmask which sets which fields to use in RX Hash. */
3001 rx_hash_field_select->selected_fields =
3002 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
3003 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
3004 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
3005 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
3006 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
3007 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
3008 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
3009 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
3011 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
3012 tir_attr.transport_domain = priv->sh->td->id;
3014 tir_attr.transport_domain = priv->sh->tdn;
3015 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
3016 MLX5_RSS_HASH_KEY_LEN);
3017 tir_attr.indirect_table = ind_tbl->rqt->id;
3018 if (dev->data->dev_conf.lpbk_mode)
3019 tir_attr.self_lb_block =
3020 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
3022 tir_attr.lro_timeout_period_usecs =
3023 priv->config.lro.timeout;
3024 tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
3025 tir_attr.lro_enable_mask =
3026 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
3027 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
3029 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
3031 DRV_LOG(ERR, "port %u cannot create DevX TIR",
3032 dev->data->port_id);
3037 hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
3040 hrxq->ind_table = ind_tbl;
3041 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
3043 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3045 mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
3046 if (!hrxq->action) {
3051 } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
3053 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3054 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
3056 if (!hrxq->action) {
3062 hrxq->rss_key_len = rss_key_len;
3063 hrxq->hash_fields = hash_fields;
3064 memcpy(hrxq->rss_key, rss_key, rss_key_len);
3065 rte_atomic32_inc(&hrxq->refcnt);
3066 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
3070 err = rte_errno; /* Save rte_errno before cleanup. */
3071 mlx5_ind_table_obj_release(dev, ind_tbl);
3073 claim_zero(mlx5_glue->destroy_qp(qp));
3075 claim_zero(mlx5_devx_cmd_destroy(tir));
3076 rte_errno = err; /* Restore rte_errno. */
3081 * Get an Rx Hash queue.
3084 * Pointer to Ethernet device.
3086 * RSS configuration for the Rx hash queue.
3088 * Queues entering in hash queue. In case of empty hash_fields only the
3089 * first queue index will be taken for the indirection table.
3094 * An hash Rx queue index on success.
3097 mlx5_hrxq_get(struct rte_eth_dev *dev,
3098 const uint8_t *rss_key, uint32_t rss_key_len,
3099 uint64_t hash_fields,
3100 const uint16_t *queues, uint32_t queues_n)
3102 struct mlx5_priv *priv = dev->data->dev_private;
3103 struct mlx5_hrxq *hrxq;
3106 queues_n = hash_fields ? queues_n : 1;
3107 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
3109 struct mlx5_ind_table_obj *ind_tbl;
3111 if (hrxq->rss_key_len != rss_key_len)
3113 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
3115 if (hrxq->hash_fields != hash_fields)
3117 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
3120 if (ind_tbl != hrxq->ind_table) {
3121 mlx5_ind_table_obj_release(dev, ind_tbl);
3124 rte_atomic32_inc(&hrxq->refcnt);
3131 * Release the hash Rx queue.
3134 * Pointer to Ethernet device.
3136 * Index to Hash Rx queue to release.
3139 * 1 while a reference on it exists, 0 when freed.
3142 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
3144 struct mlx5_priv *priv = dev->data->dev_private;
3145 struct mlx5_hrxq *hrxq;
3147 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
3150 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
3151 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3152 mlx5_glue->destroy_flow_action(hrxq->action);
3154 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
3155 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3156 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
3157 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
3158 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
3159 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
3160 hrxq_idx, hrxq, next);
3161 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
3164 claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
3169 * Verify the Rx Queue list is empty
3172 * Pointer to Ethernet device.
3175 * The number of object not released.
3178 mlx5_hrxq_verify(struct rte_eth_dev *dev)
3180 struct mlx5_priv *priv = dev->data->dev_private;
3181 struct mlx5_hrxq *hrxq;
3185 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
3188 "port %u hash Rx queue %p still referenced",
3189 dev->data->port_id, (void *)hrxq);
3196 * Create a drop Rx queue Verbs/DevX object.
3199 * Pointer to Ethernet device.
3202 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3204 static struct mlx5_rxq_obj *
3205 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
3207 struct mlx5_priv *priv = dev->data->dev_private;
3208 struct ibv_context *ctx = priv->sh->ctx;
3210 struct ibv_wq *wq = NULL;
3211 struct mlx5_rxq_obj *rxq;
3213 if (priv->drop_queue.rxq)
3214 return priv->drop_queue.rxq;
3215 cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
3217 DEBUG("port %u cannot allocate CQ for drop queue",
3218 dev->data->port_id);
3222 wq = mlx5_glue->create_wq(ctx,
3223 &(struct ibv_wq_init_attr){
3224 .wq_type = IBV_WQT_RQ,
3231 DEBUG("port %u cannot allocate WQ for drop queue",
3232 dev->data->port_id);
3236 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, SOCKET_ID_ANY);
3238 DEBUG("port %u cannot allocate drop Rx queue memory",
3239 dev->data->port_id);
3245 priv->drop_queue.rxq = rxq;
3249 claim_zero(mlx5_glue->destroy_wq(wq));
3251 claim_zero(mlx5_glue->destroy_cq(cq));
3256 * Release a drop Rx queue Verbs/DevX object.
3259 * Pointer to Ethernet device.
3262 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3265 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
3267 struct mlx5_priv *priv = dev->data->dev_private;
3268 struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
3271 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
3273 claim_zero(mlx5_glue->destroy_cq(rxq->ibv_cq));
3275 priv->drop_queue.rxq = NULL;
3279 * Create a drop indirection table.
3282 * Pointer to Ethernet device.
3285 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3287 static struct mlx5_ind_table_obj *
3288 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
3290 struct mlx5_priv *priv = dev->data->dev_private;
3291 struct mlx5_ind_table_obj *ind_tbl;
3292 struct mlx5_rxq_obj *rxq;
3293 struct mlx5_ind_table_obj tmpl;
3295 rxq = mlx5_rxq_obj_drop_new(dev);
3298 tmpl.ind_table = mlx5_glue->create_rwq_ind_table
3300 &(struct ibv_rwq_ind_table_init_attr){
3301 .log_ind_tbl_size = 0,
3302 .ind_tbl = &rxq->wq,
3305 if (!tmpl.ind_table) {
3306 DEBUG("port %u cannot allocate indirection table for drop"
3308 dev->data->port_id);
3312 ind_tbl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ind_tbl), 0,
3318 ind_tbl->ind_table = tmpl.ind_table;
3321 mlx5_rxq_obj_drop_release(dev);
3326 * Release a drop indirection table.
3329 * Pointer to Ethernet device.
3332 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
3334 struct mlx5_priv *priv = dev->data->dev_private;
3335 struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
3337 claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
3338 mlx5_rxq_obj_drop_release(dev);
3340 priv->drop_queue.hrxq->ind_table = NULL;
3344 * Create a drop Rx Hash queue.
3347 * Pointer to Ethernet device.
3350 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
3353 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
3355 struct mlx5_priv *priv = dev->data->dev_private;
3356 struct mlx5_ind_table_obj *ind_tbl = NULL;
3357 struct ibv_qp *qp = NULL;
3358 struct mlx5_hrxq *hrxq = NULL;
3360 if (priv->drop_queue.hrxq) {
3361 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
3362 return priv->drop_queue.hrxq;
3364 hrxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hrxq), 0, SOCKET_ID_ANY);
3367 "port %u cannot allocate memory for drop queue",
3368 dev->data->port_id);
3372 priv->drop_queue.hrxq = hrxq;
3373 ind_tbl = mlx5_ind_table_obj_drop_new(dev);
3376 hrxq->ind_table = ind_tbl;
3377 qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
3378 &(struct ibv_qp_init_attr_ex){
3379 .qp_type = IBV_QPT_RAW_PACKET,
3381 IBV_QP_INIT_ATTR_PD |
3382 IBV_QP_INIT_ATTR_IND_TABLE |
3383 IBV_QP_INIT_ATTR_RX_HASH,
3384 .rx_hash_conf = (struct ibv_rx_hash_conf){
3386 IBV_RX_HASH_FUNC_TOEPLITZ,
3387 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
3388 .rx_hash_key = rss_hash_default_key,
3389 .rx_hash_fields_mask = 0,
3391 .rwq_ind_tbl = ind_tbl->ind_table,
3395 DEBUG("port %u cannot allocate QP for drop queue",
3396 dev->data->port_id);
3401 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3402 hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
3403 if (!hrxq->action) {
3408 rte_atomic32_set(&hrxq->refcnt, 1);
3411 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3412 if (hrxq && hrxq->action)
3413 mlx5_glue->destroy_flow_action(hrxq->action);
3416 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3418 mlx5_ind_table_obj_drop_release(dev);
3420 priv->drop_queue.hrxq = NULL;
3427 * Release a drop hash Rx queue.
3430 * Pointer to Ethernet device.
3433 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
3435 struct mlx5_priv *priv = dev->data->dev_private;
3436 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
3438 if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
3439 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
3440 mlx5_glue->destroy_flow_action(hrxq->action);
3442 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
3443 mlx5_ind_table_obj_drop_release(dev);
3445 priv->drop_queue.hrxq = NULL;
3451 * Set the Rx queue timestamp conversion parameters
3454 * Pointer to the Ethernet device structure.
3457 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
3459 struct mlx5_priv *priv = dev->data->dev_private;
3460 struct mlx5_dev_ctx_shared *sh = priv->sh;
3461 struct mlx5_rxq_data *data;
3464 for (i = 0; i != priv->rxqs_n; ++i) {
3465 if (!(*priv->rxqs)[i])
3467 data = (*priv->rxqs)[i];
3469 data->rt_timestamp = priv->config.rt_timestamp;