drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  * MPRQ can be enabled explicitly, or implicitly by enabling LRO.
  97  *
  98  * @param dev
  99  *   Pointer to Ethernet device.
 100  *
 101  * @return
 102  *   0 if disabled, otherwise enabled.
 103  */
 104 inline int
 105 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 106 {
 107         struct mlx5_priv *priv = dev->data->dev_private;
 108         uint16_t i;
 109         uint16_t n = 0;
 110
 111         if (mlx5_check_mprq_support(dev) < 0)
 112                 return 0;
 113         /* All the configured queues should be enabled. */
 114         for (i = 0; i < priv->rxqs_n; ++i) {
 115                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 116
 117                 if (!rxq)
 118                         continue;
 119                 if (mlx5_rxq_mprq_enabled(rxq))
 120                         ++n;
 121         }
 122         /* Multi-Packet RQ can't be partially configured. */
 123         assert(n == 0 || n == priv->rxqs_n);
 124         return n == priv->rxqs_n;
 125 }
 126
 127 /**
 128  * Check whether LRO is supported and enabled for the device.
 129  *
 130  * @param dev
 131  *   Pointer to Ethernet device.
 132  *
 133  * @return
 134  *   0 if disabled, 1 if enabled.
 135  */
 136 inline int
 137 mlx5_lro_on(struct rte_eth_dev *dev)
 138 {
 139         return (MLX5_LRO_SUPPORTED(dev) && MLX5_LRO_ENABLED(dev));
 140 }
 141
 142 /**
 143  * Allocate RX queue elements for Multi-Packet RQ.
 144  *
 145  * @param rxq_ctrl
 146  *   Pointer to RX queue structure.
 147  *
 148  * @return
 149  *   0 on success, a negative errno value otherwise and rte_errno is set.
 150  */
 151 static int
 152 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 153 {
 154         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 155         unsigned int wqe_n = 1 << rxq->elts_n;
 156         unsigned int i;
 157         int err;
 158
 159         /* Iterate on segments. */
 160         for (i = 0; i <= wqe_n; ++i) {
 161                 struct mlx5_mprq_buf *buf;
 162
 163                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 164                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 165                         rte_errno = ENOMEM;
 166                         goto error;
 167                 }
 168                 if (i < wqe_n)
 169                         (*rxq->mprq_bufs)[i] = buf;
 170                 else
 171                         rxq->mprq_repl = buf;
 172         }
 173         DRV_LOG(DEBUG,
 174                 "port %u Rx queue %u allocated and configured %u segments",
 175                 rxq->port_id, rxq->idx, wqe_n);
 176         return 0;
 177 error:
 178         err = rte_errno; /* Save rte_errno before cleanup. */
 179         wqe_n = i;
 180         for (i = 0; (i != wqe_n); ++i) {
 181                 if ((*rxq->mprq_bufs)[i] != NULL)
 182                         rte_mempool_put(rxq->mprq_mp,
 183                                         (*rxq->mprq_bufs)[i]);
 184                 (*rxq->mprq_bufs)[i] = NULL;
 185         }
 186         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 187                 rxq->port_id, rxq->idx);
 188         rte_errno = err; /* Restore rte_errno. */
 189         return -rte_errno;
 190 }
 191
 192 /**
 193  * Allocate RX queue elements for Single-Packet RQ.
 194  *
 195  * @param rxq_ctrl
 196  *   Pointer to RX queue structure.
 197  *
 198  * @return
 199  *   0 on success, errno value on failure.
 200  */
 201 static int
 202 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 203 {
 204         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 205         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 206         unsigned int i;
 207         int err;
 208
 209         /* Iterate on segments. */
 210         for (i = 0; (i != elts_n); ++i) {
 211                 struct rte_mbuf *buf;
 212
 213                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 214                 if (buf == NULL) {
 215                         DRV_LOG(ERR, "port %u empty mbuf pool",
 216                                 PORT_ID(rxq_ctrl->priv));
 217                         rte_errno = ENOMEM;
 218                         goto error;
 219                 }
 220                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 221                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 222                 /* Buffer is supposed to be empty. */
 223                 assert(rte_pktmbuf_data_len(buf) == 0);
 224                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 225                 assert(!buf->next);
 226                 /* Only the first segment keeps headroom. */
 227                 if (i % sges_n)
 228                         SET_DATA_OFF(buf, 0);
 229                 PORT(buf) = rxq_ctrl->rxq.port_id;
 230                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 231                 PKT_LEN(buf) = DATA_LEN(buf);
 232                 NB_SEGS(buf) = 1;
 233                 (*rxq_ctrl->rxq.elts)[i] = buf;
 234         }
 235         /* If Rx vector is activated. */
 236         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 237                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 238                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 239                 int j;
 240
 241                 /* Initialize default rearm_data for vPMD. */
 242                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 243                 rte_mbuf_refcnt_set(mbuf_init, 1);
 244                 mbuf_init->nb_segs = 1;
 245                 mbuf_init->port = rxq->port_id;
 246                 /*
 247                  * prevent compiler reordering:
 248                  * rearm_data covers previous fields.
 249                  */
 250                 rte_compiler_barrier();
 251                 rxq->mbuf_initializer =
 252                         *(uint64_t *)&mbuf_init->rearm_data;
 253                 /* Padding with a fake mbuf for vectorized Rx. */
 254                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 255                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 256         }
 257         DRV_LOG(DEBUG,
 258                 "port %u Rx queue %u allocated and configured %u segments"
 259                 " (max %u packets)",
 260                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 261                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 262         return 0;
 263 error:
 264         err = rte_errno; /* Save rte_errno before cleanup. */
 265         elts_n = i;
 266         for (i = 0; (i != elts_n); ++i) {
 267                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 268                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 269                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 270         }
 271         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 272                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 273         rte_errno = err; /* Restore rte_errno. */
 274         return -rte_errno;
 275 }
 276
 277 /**
 278  * Allocate RX queue elements.
 279  *
 280  * @param rxq_ctrl
 281  *   Pointer to RX queue structure.
 282  *
 283  * @return
 284  *   0 on success, errno value on failure.
 285  */
 286 int
 287 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 288 {
 289         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 290                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 291 }
 292
 293 /**
 294  * Free RX queue elements for Multi-Packet RQ.
 295  *
 296  * @param rxq_ctrl
 297  *   Pointer to RX queue structure.
 298  */
 299 static void
 300 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 301 {
 302         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 303         uint16_t i;
 304
 305         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 306                 rxq->port_id, rxq->idx);
 307         if (rxq->mprq_bufs == NULL)
 308                 return;
 309         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 310         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 311                 if ((*rxq->mprq_bufs)[i] != NULL)
 312                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 313                 (*rxq->mprq_bufs)[i] = NULL;
 314         }
 315         if (rxq->mprq_repl != NULL) {
 316                 mlx5_mprq_buf_free(rxq->mprq_repl);
 317                 rxq->mprq_repl = NULL;
 318         }
 319 }
 320
 321 /**
 322  * Free RX queue elements for Single-Packet RQ.
 323  *
 324  * @param rxq_ctrl
 325  *   Pointer to RX queue structure.
 326  */
 327 static void
 328 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 329 {
 330         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 331         const uint16_t q_n = (1 << rxq->elts_n);
 332         const uint16_t q_mask = q_n - 1;
 333         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 334         uint16_t i;
 335
 336         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 337                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 338         if (rxq->elts == NULL)
 339                 return;
 340         /**
 341          * Some mbuf in the Ring belongs to the application.  They cannot be
 342          * freed.
 343          */
 344         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 345                 for (i = 0; i < used; ++i)
 346                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 347                 rxq->rq_pi = rxq->rq_ci;
 348         }
 349         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 350                 if ((*rxq->elts)[i] != NULL)
 351                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 352                 (*rxq->elts)[i] = NULL;
 353         }
 354 }
 355
 356 /**
 357  * Free RX queue elements.
 358  *
 359  * @param rxq_ctrl
 360  *   Pointer to RX queue structure.
 361  */
 362 static void
 363 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 364 {
 365         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 366                 rxq_free_elts_mprq(rxq_ctrl);
 367         else
 368                 rxq_free_elts_sprq(rxq_ctrl);
 369 }
 370
 371 /**
 372  * Returns the per-queue supported offloads.
 373  *
 374  * @param dev
 375  *   Pointer to Ethernet device.
 376  *
 377  * @return
 378  *   Supported Rx offloads.
 379  */
 380 uint64_t
 381 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 382 {
 383         struct mlx5_priv *priv = dev->data->dev_private;
 384         struct mlx5_dev_config *config = &priv->config;
 385         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 386                              DEV_RX_OFFLOAD_TIMESTAMP |
 387                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 388
 389         if (config->hw_fcs_strip)
 390                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 391
 392         if (config->hw_csum)
 393                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 394                              DEV_RX_OFFLOAD_UDP_CKSUM |
 395                              DEV_RX_OFFLOAD_TCP_CKSUM);
 396         if (config->hw_vlan_strip)
 397                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 398         return offloads;
 399 }
 400
 401
 402 /**
 403  * Returns the per-port supported offloads.
 404  *
 405  * @param dev
 406  *   Pointer to Ethernet device.
 407  *
 408  * @return
 409  *   Supported Rx offloads.
 410  */
 411 uint64_t
 412 mlx5_get_rx_port_offloads(struct rte_eth_dev *dev)
 413 {
 414         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 415
 416         if (MLX5_LRO_SUPPORTED(dev))
 417                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 418         return offloads;
 419 }
 420
 421 /**
 422  * Verify if the queue can be released.
 423  *
 424  * @param dev
 425  *   Pointer to Ethernet device.
 426  * @param idx
 427  *   RX queue index.
 428  *
 429  * @return
 430  *   1 if the queue can be released
 431  *   0 if the queue can not be released, there are references to it.
 432  *   Negative errno and rte_errno is set if queue doesn't exist.
 433  */
 434 static int
 435 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 436 {
 437         struct mlx5_priv *priv = dev->data->dev_private;
 438         struct mlx5_rxq_ctrl *rxq_ctrl;
 439
 440         if (!(*priv->rxqs)[idx]) {
 441                 rte_errno = EINVAL;
 442                 return -rte_errno;
 443         }
 444         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 445         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 446 }
 447
 448 /**
 449  *
 450  * @param dev
 451  *   Pointer to Ethernet device structure.
 452  * @param idx
 453  *   RX queue index.
 454  * @param desc
 455  *   Number of descriptors to configure in queue.
 456  * @param socket
 457  *   NUMA socket on which memory must be allocated.
 458  * @param[in] conf
 459  *   Thresholds parameters.
 460  * @param mp
 461  *   Memory pool for buffer allocations.
 462  *
 463  * @return
 464  *   0 on success, a negative errno value otherwise and rte_errno is set.
 465  */
 466 int
 467 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 468                     unsigned int socket, const struct rte_eth_rxconf *conf,
 469                     struct rte_mempool *mp)
 470 {
 471         struct mlx5_priv *priv = dev->data->dev_private;
 472         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 473         struct mlx5_rxq_ctrl *rxq_ctrl =
 474                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 475
 476         if (!rte_is_power_of_2(desc)) {
 477                 desc = 1 << log2above(desc);
 478                 DRV_LOG(WARNING,
 479                         "port %u increased number of descriptors in Rx queue %u"
 480                         " to the next power of two (%d)",
 481                         dev->data->port_id, idx, desc);
 482         }
 483         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 484                 dev->data->port_id, idx, desc);
 485         if (idx >= priv->rxqs_n) {
 486                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 487                         dev->data->port_id, idx, priv->rxqs_n);
 488                 rte_errno = EOVERFLOW;
 489                 return -rte_errno;
 490         }
 491         if (!mlx5_rxq_releasable(dev, idx)) {
 492                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 493                         dev->data->port_id, idx);
 494                 rte_errno = EBUSY;
 495                 return -rte_errno;
 496         }
 497         mlx5_rxq_release(dev, idx);
 498         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 499         if (!rxq_ctrl) {
 500                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 501                         dev->data->port_id, idx);
 502                 rte_errno = ENOMEM;
 503                 return -rte_errno;
 504         }
 505         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 506                 dev->data->port_id, idx);
 507         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 508         return 0;
 509 }
 510
 511 /**
 512  * DPDK callback to release a RX queue.
 513  *
 514  * @param dpdk_rxq
 515  *   Generic RX queue pointer.
 516  */
 517 void
 518 mlx5_rx_queue_release(void *dpdk_rxq)
 519 {
 520         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 521         struct mlx5_rxq_ctrl *rxq_ctrl;
 522         struct mlx5_priv *priv;
 523
 524         if (rxq == NULL)
 525                 return;
 526         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 527         priv = rxq_ctrl->priv;
 528         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 529                 rte_panic("port %u Rx queue %u is still used by a flow and"
 530                           " cannot be removed\n",
 531                           PORT_ID(priv), rxq->idx);
 532         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 533 }
 534
 535 /**
 536  * Get an Rx queue Verbs/DevX object.
 537  *
 538  * @param dev
 539  *   Pointer to Ethernet device.
 540  * @param idx
 541  *   Queue index in DPDK Rx queue array
 542  *
 543  * @return
 544  *   The Verbs/DevX object if it exists.
 545  */
 546 static struct mlx5_rxq_obj *
 547 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 548 {
 549         struct mlx5_priv *priv = dev->data->dev_private;
 550         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 551         struct mlx5_rxq_ctrl *rxq_ctrl;
 552
 553         if (idx >= priv->rxqs_n)
 554                 return NULL;
 555         if (!rxq_data)
 556                 return NULL;
 557         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 558         if (rxq_ctrl->obj)
 559                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 560         return rxq_ctrl->obj;
 561 }
 562
 563 /**
 564  * Release an Rx verbs/DevX queue object.
 565  *
 566  * @param rxq_obj
 567  *   Verbs/DevX Rx queue object.
 568  *
 569  * @return
 570  *   1 while a reference on it exists, 0 when freed.
 571  */
 572 static int
 573 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 574 {
 575         assert(rxq_obj);
 576         assert(rxq_obj->wq);
 577         assert(rxq_obj->cq);
 578         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 579                 rxq_free_elts(rxq_obj->rxq_ctrl);
 580                 claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 581                 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 582                 if (rxq_obj->channel)
 583                         claim_zero(mlx5_glue->destroy_comp_channel
 584                                    (rxq_obj->channel));
 585                 LIST_REMOVE(rxq_obj, next);
 586                 rte_free(rxq_obj);
 587                 return 0;
 588         }
 589         return 1;
 590 }
 591
 592 /**
 593  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 594  *
 595  * @param dev
 596  *   Pointer to Ethernet device.
 597  *
 598  * @return
 599  *   0 on success, a negative errno value otherwise and rte_errno is set.
 600  */
 601 int
 602 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 603 {
 604         struct mlx5_priv *priv = dev->data->dev_private;
 605         unsigned int i;
 606         unsigned int rxqs_n = priv->rxqs_n;
 607         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 608         unsigned int count = 0;
 609         struct rte_intr_handle *intr_handle = dev->intr_handle;
 610
 611         if (!dev->data->dev_conf.intr_conf.rxq)
 612                 return 0;
 613         mlx5_rx_intr_vec_disable(dev);
 614         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 615         if (intr_handle->intr_vec == NULL) {
 616                 DRV_LOG(ERR,
 617                         "port %u failed to allocate memory for interrupt"
 618                         " vector, Rx interrupts will not be supported",
 619                         dev->data->port_id);
 620                 rte_errno = ENOMEM;
 621                 return -rte_errno;
 622         }
 623         intr_handle->type = RTE_INTR_HANDLE_EXT;
 624         for (i = 0; i != n; ++i) {
 625                 /* This rxq obj must not be released in this function. */
 626                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 627                 int fd;
 628                 int flags;
 629                 int rc;
 630
 631                 /* Skip queues that cannot request interrupts. */
 632                 if (!rxq_obj || !rxq_obj->channel) {
 633                         /* Use invalid intr_vec[] index to disable entry. */
 634                         intr_handle->intr_vec[i] =
 635                                 RTE_INTR_VEC_RXTX_OFFSET +
 636                                 RTE_MAX_RXTX_INTR_VEC_ID;
 637                         continue;
 638                 }
 639                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 640                         DRV_LOG(ERR,
 641                                 "port %u too many Rx queues for interrupt"
 642                                 " vector size (%d), Rx interrupts cannot be"
 643                                 " enabled",
 644                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 645                         mlx5_rx_intr_vec_disable(dev);
 646                         rte_errno = ENOMEM;
 647                         return -rte_errno;
 648                 }
 649                 fd = rxq_obj->channel->fd;
 650                 flags = fcntl(fd, F_GETFL);
 651                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 652                 if (rc < 0) {
 653                         rte_errno = errno;
 654                         DRV_LOG(ERR,
 655                                 "port %u failed to make Rx interrupt file"
 656                                 " descriptor %d non-blocking for queue index"
 657                                 " %d",
 658                                 dev->data->port_id, fd, i);
 659                         mlx5_rx_intr_vec_disable(dev);
 660                         return -rte_errno;
 661                 }
 662                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 663                 intr_handle->efds[count] = fd;
 664                 count++;
 665         }
 666         if (!count)
 667                 mlx5_rx_intr_vec_disable(dev);
 668         else
 669                 intr_handle->nb_efd = count;
 670         return 0;
 671 }
 672
 673 /**
 674  * Clean up Rx interrupts handler.
 675  *
 676  * @param dev
 677  *   Pointer to Ethernet device.
 678  */
 679 void
 680 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 681 {
 682         struct mlx5_priv *priv = dev->data->dev_private;
 683         struct rte_intr_handle *intr_handle = dev->intr_handle;
 684         unsigned int i;
 685         unsigned int rxqs_n = priv->rxqs_n;
 686         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 687
 688         if (!dev->data->dev_conf.intr_conf.rxq)
 689                 return;
 690         if (!intr_handle->intr_vec)
 691                 goto free;
 692         for (i = 0; i != n; ++i) {
 693                 struct mlx5_rxq_ctrl *rxq_ctrl;
 694                 struct mlx5_rxq_data *rxq_data;
 695
 696                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 697                     RTE_MAX_RXTX_INTR_VEC_ID)
 698                         continue;
 699                 /**
 700                  * Need to access directly the queue to release the reference
 701                  * kept in mlx5_rx_intr_vec_enable().
 702                  */
 703                 rxq_data = (*priv->rxqs)[i];
 704                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 705                 if (rxq_ctrl->obj)
 706                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 707         }
 708 free:
 709         rte_intr_free_epoll_fd(intr_handle);
 710         if (intr_handle->intr_vec)
 711                 free(intr_handle->intr_vec);
 712         intr_handle->nb_efd = 0;
 713         intr_handle->intr_vec = NULL;
 714 }
 715
 716 /**
 717  *  MLX5 CQ notification .
 718  *
 719  *  @param rxq
 720  *     Pointer to receive queue structure.
 721  *  @param sq_n_rxq
 722  *     Sequence number per receive queue .
 723  */
 724 static inline void
 725 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 726 {
 727         int sq_n = 0;
 728         uint32_t doorbell_hi;
 729         uint64_t doorbell;
 730         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 731
 732         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 733         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 734         doorbell = (uint64_t)doorbell_hi << 32;
 735         doorbell |=  rxq->cqn;
 736         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 737         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 738                          cq_db_reg, rxq->uar_lock_cq);
 739 }
 740
 741 /**
 742  * DPDK callback for Rx queue interrupt enable.
 743  *
 744  * @param dev
 745  *   Pointer to Ethernet device structure.
 746  * @param rx_queue_id
 747  *   Rx queue number.
 748  *
 749  * @return
 750  *   0 on success, a negative errno value otherwise and rte_errno is set.
 751  */
 752 int
 753 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 754 {
 755         struct mlx5_priv *priv = dev->data->dev_private;
 756         struct mlx5_rxq_data *rxq_data;
 757         struct mlx5_rxq_ctrl *rxq_ctrl;
 758
 759         rxq_data = (*priv->rxqs)[rx_queue_id];
 760         if (!rxq_data) {
 761                 rte_errno = EINVAL;
 762                 return -rte_errno;
 763         }
 764         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 765         if (rxq_ctrl->irq) {
 766                 struct mlx5_rxq_obj *rxq_obj;
 767
 768                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 769                 if (!rxq_obj) {
 770                         rte_errno = EINVAL;
 771                         return -rte_errno;
 772                 }
 773                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 774                 mlx5_rxq_obj_release(rxq_obj);
 775         }
 776         return 0;
 777 }
 778
 779 /**
 780  * DPDK callback for Rx queue interrupt disable.
 781  *
 782  * @param dev
 783  *   Pointer to Ethernet device structure.
 784  * @param rx_queue_id
 785  *   Rx queue number.
 786  *
 787  * @return
 788  *   0 on success, a negative errno value otherwise and rte_errno is set.
 789  */
 790 int
 791 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 792 {
 793         struct mlx5_priv *priv = dev->data->dev_private;
 794         struct mlx5_rxq_data *rxq_data;
 795         struct mlx5_rxq_ctrl *rxq_ctrl;
 796         struct mlx5_rxq_obj *rxq_obj = NULL;
 797         struct ibv_cq *ev_cq;
 798         void *ev_ctx;
 799         int ret;
 800
 801         rxq_data = (*priv->rxqs)[rx_queue_id];
 802         if (!rxq_data) {
 803                 rte_errno = EINVAL;
 804                 return -rte_errno;
 805         }
 806         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 807         if (!rxq_ctrl->irq)
 808                 return 0;
 809         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 810         if (!rxq_obj) {
 811                 rte_errno = EINVAL;
 812                 return -rte_errno;
 813         }
 814         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 815         if (ret || ev_cq != rxq_obj->cq) {
 816                 rte_errno = EINVAL;
 817                 goto exit;
 818         }
 819         rxq_data->cq_arm_sn++;
 820         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 821         mlx5_rxq_obj_release(rxq_obj);
 822         return 0;
 823 exit:
 824         ret = rte_errno; /* Save rte_errno before cleanup. */
 825         if (rxq_obj)
 826                 mlx5_rxq_obj_release(rxq_obj);
 827         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 828                 dev->data->port_id, rx_queue_id);
 829         rte_errno = ret; /* Restore rte_errno. */
 830         return -rte_errno;
 831 }
 832
 833 /**
 834  * Create a CQ Verbs object.
 835  *
 836  * @param dev
 837  *   Pointer to Ethernet device.
 838  * @param priv
 839  *   Pointer to device private data.
 840  * @param rxq_data
 841  *   Pointer to Rx queue data.
 842  * @param cqe_n
 843  *   Number of CQEs in CQ.
 844  * @param rxq_obj
 845  *   Pointer to Rx queue object data.
 846  *
 847  * @return
 848  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 849  */
 850 static struct ibv_cq *
 851 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 852                 struct mlx5_rxq_data *rxq_data,
 853                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 854 {
 855         struct {
 856                 struct ibv_cq_init_attr_ex ibv;
 857                 struct mlx5dv_cq_init_attr mlx5;
 858         } cq_attr;
 859
 860         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 861                 .cqe = cqe_n,
 862                 .channel = rxq_obj->channel,
 863                 .comp_mask = 0,
 864         };
 865         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 866                 .comp_mask = 0,
 867         };
 868         if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
 869                 cq_attr.mlx5.comp_mask |=
 870                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 871 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 872                 cq_attr.mlx5.cqe_comp_res_format =
 873                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 874                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 875                                 MLX5DV_CQE_RES_FORMAT_HASH;
 876 #else
 877                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 878 #endif
 879                 /*
 880                  * For vectorized Rx, it must not be doubled in order to
 881                  * make cq_ci and rq_ci aligned.
 882                  */
 883                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 884                         cq_attr.ibv.cqe *= 2;
 885         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
 886                 DRV_LOG(DEBUG,
 887                         "port %u Rx CQE compression is disabled for HW"
 888                         " timestamp",
 889                         dev->data->port_id);
 890         }
 891 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 892         if (priv->config.cqe_pad) {
 893                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 894                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 895         }
 896 #endif
 897         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
 898                                                               &cq_attr.ibv,
 899                                                               &cq_attr.mlx5));
 900 }
 901
 902 /**
 903  * Create the Rx queue Verbs/DevX object.
 904  *
 905  * @param dev
 906  *   Pointer to Ethernet device.
 907  * @param idx
 908  *   Queue index in DPDK Rx queue array
 909  *
 910  * @return
 911  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
 912  */
 913 struct mlx5_rxq_obj *
 914 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx)
 915 {
 916         struct mlx5_priv *priv = dev->data->dev_private;
 917         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 918         struct mlx5_rxq_ctrl *rxq_ctrl =
 919                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 920         struct ibv_wq_attr mod;
 921         struct {
 922                 struct ibv_wq_init_attr ibv;
 923 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 924                 struct mlx5dv_wq_init_attr mlx5;
 925 #endif
 926         } wq_attr;
 927         unsigned int cqe_n;
 928         unsigned int wqe_n = 1 << rxq_data->elts_n;
 929         struct mlx5_rxq_obj *tmpl = NULL;
 930         struct mlx5dv_cq cq_info;
 931         struct mlx5dv_rwq rwq;
 932         int ret = 0;
 933         struct mlx5dv_obj obj;
 934         struct mlx5_dev_config *config = &priv->config;
 935         const int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);
 936
 937         assert(rxq_data);
 938         assert(!rxq_ctrl->obj);
 939         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
 940         priv->verbs_alloc_ctx.obj = rxq_ctrl;
 941         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
 942                                  rxq_ctrl->socket);
 943         if (!tmpl) {
 944                 DRV_LOG(ERR,
 945                         "port %u Rx queue %u cannot allocate verbs resources",
 946                         dev->data->port_id, rxq_data->idx);
 947                 rte_errno = ENOMEM;
 948                 goto error;
 949         }
 950         tmpl->rxq_ctrl = rxq_ctrl;
 951         if (rxq_ctrl->irq) {
 952                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
 953                 if (!tmpl->channel) {
 954                         DRV_LOG(ERR, "port %u: comp channel creation failure",
 955                                 dev->data->port_id);
 956                         rte_errno = ENOMEM;
 957                         goto error;
 958                 }
 959         }
 960         if (mprq_en)
 961                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
 962         else
 963                 cqe_n = wqe_n  - 1;
 964         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
 965         if (!tmpl->cq) {
 966                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
 967                         dev->data->port_id, idx);
 968                 rte_errno = ENOMEM;
 969                 goto error;
 970         }
 971         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
 972                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
 973         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
 974                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
 975         wq_attr.ibv = (struct ibv_wq_init_attr){
 976                 .wq_context = NULL, /* Could be useful in the future. */
 977                 .wq_type = IBV_WQT_RQ,
 978                 /* Max number of outstanding WRs. */
 979                 .max_wr = wqe_n >> rxq_data->sges_n,
 980                 /* Max number of scatter/gather elements in a WR. */
 981                 .max_sge = 1 << rxq_data->sges_n,
 982                 .pd = priv->sh->pd,
 983                 .cq = tmpl->cq,
 984                 .comp_mask =
 985                         IBV_WQ_FLAGS_CVLAN_STRIPPING |
 986                         0,
 987                 .create_flags = (rxq_data->vlan_strip ?
 988                                  IBV_WQ_FLAGS_CVLAN_STRIPPING :
 989                                  0),
 990         };
 991         /* By default, FCS (CRC) is stripped by hardware. */
 992         if (rxq_data->crc_present) {
 993                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 994                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 995         }
 996         if (config->hw_padding) {
 997 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 998                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 999                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1000 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1001                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1002                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1003 #endif
1004         }
1005 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1006         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1007                 .comp_mask = 0,
1008         };
1009         if (mprq_en) {
1010                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1011                         &wq_attr.mlx5.striding_rq_attrs;
1012
1013                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1014                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1015                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1016                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1017                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1018                 };
1019         }
1020         tmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1021                                            &wq_attr.mlx5);
1022 #else
1023         tmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1024 #endif
1025         if (tmpl->wq == NULL) {
1026                 DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1027                         dev->data->port_id, idx);
1028                 rte_errno = ENOMEM;
1029                 goto error;
1030         }
1031         /*
1032          * Make sure number of WRs*SGEs match expectations since a queue
1033          * cannot allocate more than "desc" buffers.
1034          */
1035         if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1036             wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1037                 DRV_LOG(ERR,
1038                         "port %u Rx queue %u requested %u*%u but got %u*%u"
1039                         " WRs*SGEs",
1040                         dev->data->port_id, idx,
1041                         wqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),
1042                         wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1043                 rte_errno = EINVAL;
1044                 goto error;
1045         }
1046         /* Change queue state to ready. */
1047         mod = (struct ibv_wq_attr){
1048                 .attr_mask = IBV_WQ_ATTR_STATE,
1049                 .wq_state = IBV_WQS_RDY,
1050         };
1051         ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1052         if (ret) {
1053                 DRV_LOG(ERR,
1054                         "port %u Rx queue %u WQ state to IBV_WQS_RDY failed",
1055                         dev->data->port_id, idx);
1056                 rte_errno = ret;
1057                 goto error;
1058         }
1059         obj.cq.in = tmpl->cq;
1060         obj.cq.out = &cq_info;
1061         obj.rwq.in = tmpl->wq;
1062         obj.rwq.out = &rwq;
1063         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ | MLX5DV_OBJ_RWQ);
1064         if (ret) {
1065                 rte_errno = ret;
1066                 goto error;
1067         }
1068         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1069                 DRV_LOG(ERR,
1070                         "port %u wrong MLX5_CQE_SIZE environment variable"
1071                         " value: it should be set to %u",
1072                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1073                 rte_errno = EINVAL;
1074                 goto error;
1075         }
1076         /* Fill the rings. */
1077         rxq_data->wqes = rwq.buf;
1078         rxq_data->rq_db = rwq.dbrec;
1079         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1080         rxq_data->cq_db = cq_info.dbrec;
1081         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1082         rxq_data->cq_uar = cq_info.cq_uar;
1083         rxq_data->cqn = cq_info.cqn;
1084         rxq_data->cq_arm_sn = 0;
1085         mlx5_rxq_initialize(rxq_data);
1086         rxq_data->cq_ci = 0;
1087         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1088                 idx, (void *)&tmpl);
1089         rte_atomic32_inc(&tmpl->refcnt);
1090         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1091         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1092         return tmpl;
1093 error:
1094         if (tmpl) {
1095                 ret = rte_errno; /* Save rte_errno before cleanup. */
1096                 if (tmpl->wq)
1097                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1098                 if (tmpl->cq)
1099                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1100                 if (tmpl->channel)
1101                         claim_zero(mlx5_glue->destroy_comp_channel
1102                                                         (tmpl->channel));
1103                 rte_free(tmpl);
1104                 rte_errno = ret; /* Restore rte_errno. */
1105         }
1106         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1107         return NULL;
1108 }
1109
1110 /**
1111  * Verify the Rx queue objects list is empty
1112  *
1113  * @param dev
1114  *   Pointer to Ethernet device.
1115  *
1116  * @return
1117  *   The number of objects not released.
1118  */
1119 int
1120 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1121 {
1122         struct mlx5_priv *priv = dev->data->dev_private;
1123         int ret = 0;
1124         struct mlx5_rxq_obj *rxq_obj;
1125
1126         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1127                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1128                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1129                 ++ret;
1130         }
1131         return ret;
1132 }
1133
1134 /**
1135  * Callback function to initialize mbufs for Multi-Packet RQ.
1136  */
1137 static inline void
1138 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg __rte_unused,
1139                     void *_m, unsigned int i __rte_unused)
1140 {
1141         struct mlx5_mprq_buf *buf = _m;
1142
1143         memset(_m, 0, sizeof(*buf));
1144         buf->mp = mp;
1145         rte_atomic16_set(&buf->refcnt, 1);
1146 }
1147
1148 /**
1149  * Free mempool of Multi-Packet RQ.
1150  *
1151  * @param dev
1152  *   Pointer to Ethernet device.
1153  *
1154  * @return
1155  *   0 on success, negative errno value on failure.
1156  */
1157 int
1158 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1159 {
1160         struct mlx5_priv *priv = dev->data->dev_private;
1161         struct rte_mempool *mp = priv->mprq_mp;
1162         unsigned int i;
1163
1164         if (mp == NULL)
1165                 return 0;
1166         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1167                 dev->data->port_id, mp->name);
1168         /*
1169          * If a buffer in the pool has been externally attached to a mbuf and it
1170          * is still in use by application, destroying the Rx queue can spoil
1171          * the packet. It is unlikely to happen but if application dynamically
1172          * creates and destroys with holding Rx packets, this can happen.
1173          *
1174          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1175          * RQ isn't provided by application but managed by PMD.
1176          */
1177         if (!rte_mempool_full(mp)) {
1178                 DRV_LOG(ERR,
1179                         "port %u mempool for Multi-Packet RQ is still in use",
1180                         dev->data->port_id);
1181                 rte_errno = EBUSY;
1182                 return -rte_errno;
1183         }
1184         rte_mempool_free(mp);
1185         /* Unset mempool for each Rx queue. */
1186         for (i = 0; i != priv->rxqs_n; ++i) {
1187                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1188
1189                 if (rxq == NULL)
1190                         continue;
1191                 rxq->mprq_mp = NULL;
1192         }
1193         priv->mprq_mp = NULL;
1194         return 0;
1195 }
1196
1197 /**
1198  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1199  * mempool. If already allocated, reuse it if there're enough elements.
1200  * Otherwise, resize it.
1201  *
1202  * @param dev
1203  *   Pointer to Ethernet device.
1204  *
1205  * @return
1206  *   0 on success, negative errno value on failure.
1207  */
1208 int
1209 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1210 {
1211         struct mlx5_priv *priv = dev->data->dev_private;
1212         struct rte_mempool *mp = priv->mprq_mp;
1213         char name[RTE_MEMPOOL_NAMESIZE];
1214         unsigned int desc = 0;
1215         unsigned int buf_len;
1216         unsigned int obj_num;
1217         unsigned int obj_size;
1218         unsigned int strd_num_n = 0;
1219         unsigned int strd_sz_n = 0;
1220         unsigned int i;
1221
1222         if (!mlx5_mprq_enabled(dev))
1223                 return 0;
1224         /* Count the total number of descriptors configured. */
1225         for (i = 0; i != priv->rxqs_n; ++i) {
1226                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1227
1228                 if (rxq == NULL)
1229                         continue;
1230                 desc += 1 << rxq->elts_n;
1231                 /* Get the max number of strides. */
1232                 if (strd_num_n < rxq->strd_num_n)
1233                         strd_num_n = rxq->strd_num_n;
1234                 /* Get the max size of a stride. */
1235                 if (strd_sz_n < rxq->strd_sz_n)
1236                         strd_sz_n = rxq->strd_sz_n;
1237         }
1238         assert(strd_num_n && strd_sz_n);
1239         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1240         obj_size = buf_len + sizeof(struct mlx5_mprq_buf);
1241         /*
1242          * Received packets can be either memcpy'd or externally referenced. In
1243          * case that the packet is attached to an mbuf as an external buffer, as
1244          * it isn't possible to predict how the buffers will be queued by
1245          * application, there's no option to exactly pre-allocate needed buffers
1246          * in advance but to speculatively prepares enough buffers.
1247          *
1248          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1249          * received packets to buffers provided by application (rxq->mp) until
1250          * this Mempool gets available again.
1251          */
1252         desc *= 4;
1253         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1254         /*
1255          * rte_mempool_create_empty() has sanity check to refuse large cache
1256          * size compared to the number of elements.
1257          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1258          * constant number 2 instead.
1259          */
1260         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1261         /* Check a mempool is already allocated and if it can be resued. */
1262         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1263                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1264                         dev->data->port_id, mp->name);
1265                 /* Reuse. */
1266                 goto exit;
1267         } else if (mp != NULL) {
1268                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1269                         dev->data->port_id, mp->name);
1270                 /*
1271                  * If failed to free, which means it may be still in use, no way
1272                  * but to keep using the existing one. On buffer underrun,
1273                  * packets will be memcpy'd instead of external buffer
1274                  * attachment.
1275                  */
1276                 if (mlx5_mprq_free_mp(dev)) {
1277                         if (mp->elt_size >= obj_size)
1278                                 goto exit;
1279                         else
1280                                 return -rte_errno;
1281                 }
1282         }
1283         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1284         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1285                                 0, NULL, NULL, mlx5_mprq_buf_init, NULL,
1286                                 dev->device->numa_node, 0);
1287         if (mp == NULL) {
1288                 DRV_LOG(ERR,
1289                         "port %u failed to allocate a mempool for"
1290                         " Multi-Packet RQ, count=%u, size=%u",
1291                         dev->data->port_id, obj_num, obj_size);
1292                 rte_errno = ENOMEM;
1293                 return -rte_errno;
1294         }
1295         priv->mprq_mp = mp;
1296 exit:
1297         /* Set mempool for each Rx queue. */
1298         for (i = 0; i != priv->rxqs_n; ++i) {
1299                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1300
1301                 if (rxq == NULL)
1302                         continue;
1303                 rxq->mprq_mp = mp;
1304         }
1305         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1306                 dev->data->port_id);
1307         return 0;
1308 }
1309
1310 /**
1311  * Create a DPDK Rx queue.
1312  *
1313  * @param dev
1314  *   Pointer to Ethernet device.
1315  * @param idx
1316  *   RX queue index.
1317  * @param desc
1318  *   Number of descriptors to configure in queue.
1319  * @param socket
1320  *   NUMA socket on which memory must be allocated.
1321  *
1322  * @return
1323  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1324  */
1325 struct mlx5_rxq_ctrl *
1326 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1327              unsigned int socket, const struct rte_eth_rxconf *conf,
1328              struct rte_mempool *mp)
1329 {
1330         struct mlx5_priv *priv = dev->data->dev_private;
1331         struct mlx5_rxq_ctrl *tmpl;
1332         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1333         unsigned int mprq_stride_size;
1334         struct mlx5_dev_config *config = &priv->config;
1335         /*
1336          * Always allocate extra slots, even if eventually
1337          * the vector Rx will not be used.
1338          */
1339         uint16_t desc_n =
1340                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1341         uint64_t offloads = conf->offloads |
1342                            dev->data->dev_conf.rxmode.offloads;
1343         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1344
1345         tmpl = rte_calloc_socket("RXQ", 1,
1346                                  sizeof(*tmpl) +
1347                                  desc_n * sizeof(struct rte_mbuf *),
1348                                  0, socket);
1349         if (!tmpl) {
1350                 rte_errno = ENOMEM;
1351                 return NULL;
1352         }
1353         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1354                                MLX5_MR_BTREE_CACHE_N, socket)) {
1355                 /* rte_errno is already set. */
1356                 goto error;
1357         }
1358         tmpl->socket = socket;
1359         if (dev->data->dev_conf.intr_conf.rxq)
1360                 tmpl->irq = 1;
1361         /*
1362          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1363          * following conditions are met:
1364          *  - MPRQ is enabled.
1365          *  - The number of descs is more than the number of strides.
1366          *  - max_rx_pkt_len plus overhead is less than the max size of a
1367          *    stride.
1368          *  Otherwise, enable Rx scatter if necessary.
1369          */
1370         assert(mb_len >= RTE_PKTMBUF_HEADROOM);
1371         mprq_stride_size =
1372                 dev->data->dev_conf.rxmode.max_rx_pkt_len +
1373                 sizeof(struct rte_mbuf_ext_shared_info) +
1374                 RTE_PKTMBUF_HEADROOM;
1375         if (mprq_en &&
1376             desc > (1U << config->mprq.stride_num_n) &&
1377             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1378                 /* TODO: Rx scatter isn't supported yet. */
1379                 tmpl->rxq.sges_n = 0;
1380                 /* Trim the number of descs needed. */
1381                 desc >>= config->mprq.stride_num_n;
1382                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1383                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1384                                               config->mprq.min_stride_size_n);
1385                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1386                 tmpl->rxq.mprq_max_memcpy_len =
1387                         RTE_MIN(mb_len - RTE_PKTMBUF_HEADROOM,
1388                                 config->mprq.max_memcpy_len);
1389                 DRV_LOG(DEBUG,
1390                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1391                         " strd_num_n = %u, strd_sz_n = %u",
1392                         dev->data->port_id, idx,
1393                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1394         } else if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
1395                    (mb_len - RTE_PKTMBUF_HEADROOM)) {
1396                 tmpl->rxq.sges_n = 0;
1397         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1398                 unsigned int size =
1399                         RTE_PKTMBUF_HEADROOM +
1400                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1401                 unsigned int sges_n;
1402
1403                 /*
1404                  * Determine the number of SGEs needed for a full packet
1405                  * and round it to the next power of two.
1406                  */
1407                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1408                 tmpl->rxq.sges_n = sges_n;
1409                 /* Make sure rxq.sges_n did not overflow. */
1410                 size = mb_len * (1 << tmpl->rxq.sges_n);
1411                 size -= RTE_PKTMBUF_HEADROOM;
1412                 if (size < dev->data->dev_conf.rxmode.max_rx_pkt_len) {
1413                         DRV_LOG(ERR,
1414                                 "port %u too many SGEs (%u) needed to handle"
1415                                 " requested maximum packet size %u",
1416                                 dev->data->port_id,
1417                                 1 << sges_n,
1418                                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1419                         rte_errno = EOVERFLOW;
1420                         goto error;
1421                 }
1422         } else {
1423                 DRV_LOG(WARNING,
1424                         "port %u the requested maximum Rx packet size (%u) is"
1425                         " larger than a single mbuf (%u) and scattered mode has"
1426                         " not been requested",
1427                         dev->data->port_id,
1428                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
1429                         mb_len - RTE_PKTMBUF_HEADROOM);
1430         }
1431         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1432                 DRV_LOG(WARNING,
1433                         "port %u MPRQ is requested but cannot be enabled"
1434                         " (requested: desc = %u, stride_sz = %u,"
1435                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1436                         dev->data->port_id, desc, mprq_stride_size,
1437                         (1 << config->mprq.stride_num_n),
1438                         (1 << config->mprq.max_stride_size_n));
1439         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1440                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1441         if (desc % (1 << tmpl->rxq.sges_n)) {
1442                 DRV_LOG(ERR,
1443                         "port %u number of Rx queue descriptors (%u) is not a"
1444                         " multiple of SGEs per packet (%u)",
1445                         dev->data->port_id,
1446                         desc,
1447                         1 << tmpl->rxq.sges_n);
1448                 rte_errno = EINVAL;
1449                 goto error;
1450         }
1451         /* Toggle RX checksum offload if hardware supports it. */
1452         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1453         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1454         /* Configure VLAN stripping. */
1455         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1456         /* By default, FCS (CRC) is stripped by hardware. */
1457         tmpl->rxq.crc_present = 0;
1458         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1459                 if (config->hw_fcs_strip) {
1460                         /*
1461                          * RQs used for LRO-enabled TIRs should not be
1462                          * configured to scatter the FCS.
1463                          */
1464                         if (mlx5_lro_on(dev))
1465                                 DRV_LOG(WARNING,
1466                                         "port %u CRC stripping has been "
1467                                         "disabled but will still be performed "
1468                                         "by hardware, because LRO is enabled",
1469                                         dev->data->port_id);
1470                         else
1471                                 tmpl->rxq.crc_present = 1;
1472                 } else {
1473                         DRV_LOG(WARNING,
1474                                 "port %u CRC stripping has been disabled but will"
1475                                 " still be performed by hardware, make sure MLNX_OFED"
1476                                 " and firmware are up to date",
1477                                 dev->data->port_id);
1478                 }
1479         }
1480         DRV_LOG(DEBUG,
1481                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1482                 " incoming frames to hide it",
1483                 dev->data->port_id,
1484                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1485                 tmpl->rxq.crc_present << 2);
1486         /* Save port ID. */
1487         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1488                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1489         tmpl->rxq.port_id = dev->data->port_id;
1490         tmpl->priv = priv;
1491         tmpl->rxq.mp = mp;
1492         tmpl->rxq.elts_n = log2above(desc);
1493         tmpl->rxq.rq_repl_thresh =
1494                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1495         tmpl->rxq.elts =
1496                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1497 #ifndef RTE_ARCH_64
1498         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1499 #endif
1500         tmpl->rxq.idx = idx;
1501         rte_atomic32_inc(&tmpl->refcnt);
1502         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1503         return tmpl;
1504 error:
1505         rte_free(tmpl);
1506         return NULL;
1507 }
1508
1509 /**
1510  * Get a Rx queue.
1511  *
1512  * @param dev
1513  *   Pointer to Ethernet device.
1514  * @param idx
1515  *   RX queue index.
1516  *
1517  * @return
1518  *   A pointer to the queue if it exists, NULL otherwise.
1519  */
1520 struct mlx5_rxq_ctrl *
1521 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1522 {
1523         struct mlx5_priv *priv = dev->data->dev_private;
1524         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1525
1526         if ((*priv->rxqs)[idx]) {
1527                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1528                                         struct mlx5_rxq_ctrl,
1529                                         rxq);
1530                 mlx5_rxq_obj_get(dev, idx);
1531                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1532         }
1533         return rxq_ctrl;
1534 }
1535
1536 /**
1537  * Release a Rx queue.
1538  *
1539  * @param dev
1540  *   Pointer to Ethernet device.
1541  * @param idx
1542  *   RX queue index.
1543  *
1544  * @return
1545  *   1 while a reference on it exists, 0 when freed.
1546  */
1547 int
1548 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1549 {
1550         struct mlx5_priv *priv = dev->data->dev_private;
1551         struct mlx5_rxq_ctrl *rxq_ctrl;
1552
1553         if (!(*priv->rxqs)[idx])
1554                 return 0;
1555         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1556         assert(rxq_ctrl->priv);
1557         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
1558                 rxq_ctrl->obj = NULL;
1559         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1560                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1561                 LIST_REMOVE(rxq_ctrl, next);
1562                 rte_free(rxq_ctrl);
1563                 (*priv->rxqs)[idx] = NULL;
1564                 return 0;
1565         }
1566         return 1;
1567 }
1568
1569 /**
1570  * Verify the Rx Queue list is empty
1571  *
1572  * @param dev
1573  *   Pointer to Ethernet device.
1574  *
1575  * @return
1576  *   The number of object not released.
1577  */
1578 int
1579 mlx5_rxq_verify(struct rte_eth_dev *dev)
1580 {
1581         struct mlx5_priv *priv = dev->data->dev_private;
1582         struct mlx5_rxq_ctrl *rxq_ctrl;
1583         int ret = 0;
1584
1585         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1586                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1587                         dev->data->port_id, rxq_ctrl->rxq.idx);
1588                 ++ret;
1589         }
1590         return ret;
1591 }
1592
1593 /**
1594  * Create an indirection table.
1595  *
1596  * @param dev
1597  *   Pointer to Ethernet device.
1598  * @param queues
1599  *   Queues entering in the indirection table.
1600  * @param queues_n
1601  *   Number of queues in the array.
1602  *
1603  * @return
1604  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1605  */
1606 static struct mlx5_ind_table_obj *
1607 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1608                        uint32_t queues_n)
1609 {
1610         struct mlx5_priv *priv = dev->data->dev_private;
1611         struct mlx5_ind_table_obj *ind_tbl;
1612         const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1613                 log2above(queues_n) :
1614                 log2above(priv->config.ind_table_max_size);
1615         struct ibv_wq *wq[1 << wq_n];
1616         unsigned int i;
1617         unsigned int j;
1618
1619         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1620                              queues_n * sizeof(uint16_t), 0);
1621         if (!ind_tbl) {
1622                 rte_errno = ENOMEM;
1623                 return NULL;
1624         }
1625         for (i = 0; i != queues_n; ++i) {
1626                 struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev, queues[i]);
1627
1628                 if (!rxq)
1629                         goto error;
1630                 wq[i] = rxq->obj->wq;
1631                 ind_tbl->queues[i] = queues[i];
1632         }
1633         ind_tbl->queues_n = queues_n;
1634         /* Finalise indirection table. */
1635         for (j = 0; i != (unsigned int)(1 << wq_n); ++i, ++j)
1636                 wq[i] = wq[j];
1637         ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1638                 (priv->sh->ctx,
1639                  &(struct ibv_rwq_ind_table_init_attr){
1640                         .log_ind_tbl_size = wq_n,
1641                         .ind_tbl = wq,
1642                         .comp_mask = 0,
1643                  });
1644         if (!ind_tbl->ind_table) {
1645                 rte_errno = errno;
1646                 goto error;
1647         }
1648         rte_atomic32_inc(&ind_tbl->refcnt);
1649         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1650         return ind_tbl;
1651 error:
1652         rte_free(ind_tbl);
1653         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1654         return NULL;
1655 }
1656
1657 /**
1658  * Get an indirection table.
1659  *
1660  * @param dev
1661  *   Pointer to Ethernet device.
1662  * @param queues
1663  *   Queues entering in the indirection table.
1664  * @param queues_n
1665  *   Number of queues in the array.
1666  *
1667  * @return
1668  *   An indirection table if found.
1669  */
1670 static struct mlx5_ind_table_obj *
1671 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
1672                        uint32_t queues_n)
1673 {
1674         struct mlx5_priv *priv = dev->data->dev_private;
1675         struct mlx5_ind_table_obj *ind_tbl;
1676
1677         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1678                 if ((ind_tbl->queues_n == queues_n) &&
1679                     (memcmp(ind_tbl->queues, queues,
1680                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
1681                      == 0))
1682                         break;
1683         }
1684         if (ind_tbl) {
1685                 unsigned int i;
1686
1687                 rte_atomic32_inc(&ind_tbl->refcnt);
1688                 for (i = 0; i != ind_tbl->queues_n; ++i)
1689                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
1690         }
1691         return ind_tbl;
1692 }
1693
1694 /**
1695  * Release an indirection table.
1696  *
1697  * @param dev
1698  *   Pointer to Ethernet device.
1699  * @param ind_table
1700  *   Indirection table to release.
1701  *
1702  * @return
1703  *   1 while a reference on it exists, 0 when freed.
1704  */
1705 static int
1706 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
1707                            struct mlx5_ind_table_obj *ind_tbl)
1708 {
1709         unsigned int i;
1710
1711         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt))
1712                 claim_zero(mlx5_glue->destroy_rwq_ind_table
1713                            (ind_tbl->ind_table));
1714         for (i = 0; i != ind_tbl->queues_n; ++i)
1715                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
1716         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
1717                 LIST_REMOVE(ind_tbl, next);
1718                 rte_free(ind_tbl);
1719                 return 0;
1720         }
1721         return 1;
1722 }
1723
1724 /**
1725  * Verify the Rx Queue list is empty
1726  *
1727  * @param dev
1728  *   Pointer to Ethernet device.
1729  *
1730  * @return
1731  *   The number of object not released.
1732  */
1733 int
1734 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
1735 {
1736         struct mlx5_priv *priv = dev->data->dev_private;
1737         struct mlx5_ind_table_obj *ind_tbl;
1738         int ret = 0;
1739
1740         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
1741                 DRV_LOG(DEBUG,
1742                         "port %u indirection table obj %p still referenced",
1743                         dev->data->port_id, (void *)ind_tbl);
1744                 ++ret;
1745         }
1746         return ret;
1747 }
1748
1749 /**
1750  * Create an Rx Hash queue.
1751  *
1752  * @param dev
1753  *   Pointer to Ethernet device.
1754  * @param rss_key
1755  *   RSS key for the Rx hash queue.
1756  * @param rss_key_len
1757  *   RSS key length.
1758  * @param hash_fields
1759  *   Verbs protocol hash field to make the RSS on.
1760  * @param queues
1761  *   Queues entering in hash queue. In case of empty hash_fields only the
1762  *   first queue index will be taken for the indirection table.
1763  * @param queues_n
1764  *   Number of queues.
1765  * @param tunnel
1766  *   Tunnel type.
1767  *
1768  * @return
1769  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1770  */
1771 struct mlx5_hrxq *
1772 mlx5_hrxq_new(struct rte_eth_dev *dev,
1773               const uint8_t *rss_key, uint32_t rss_key_len,
1774               uint64_t hash_fields,
1775               const uint16_t *queues, uint32_t queues_n,
1776               int tunnel __rte_unused)
1777 {
1778         struct mlx5_priv *priv = dev->data->dev_private;
1779         struct mlx5_hrxq *hrxq;
1780         struct mlx5_ind_table_obj *ind_tbl;
1781         struct ibv_qp *qp;
1782 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1783         struct mlx5dv_qp_init_attr qp_init_attr;
1784 #endif
1785         int err;
1786
1787         queues_n = hash_fields ? queues_n : 1;
1788         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
1789         if (!ind_tbl)
1790                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n);
1791         if (!ind_tbl) {
1792                 rte_errno = ENOMEM;
1793                 return NULL;
1794         }
1795 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1796         memset(&qp_init_attr, 0, sizeof(qp_init_attr));
1797         if (tunnel) {
1798                 qp_init_attr.comp_mask =
1799                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1800                 qp_init_attr.create_flags = MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
1801         }
1802 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1803         if (dev->data->dev_conf.lpbk_mode) {
1804                 /* Allow packet sent from NIC loop back w/o source MAC check. */
1805                 qp_init_attr.comp_mask |=
1806                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
1807                 qp_init_attr.create_flags |=
1808                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
1809         }
1810 #endif
1811         qp = mlx5_glue->dv_create_qp
1812                 (priv->sh->ctx,
1813                  &(struct ibv_qp_init_attr_ex){
1814                         .qp_type = IBV_QPT_RAW_PACKET,
1815                         .comp_mask =
1816                                 IBV_QP_INIT_ATTR_PD |
1817                                 IBV_QP_INIT_ATTR_IND_TABLE |
1818                                 IBV_QP_INIT_ATTR_RX_HASH,
1819                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1820                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1821                                 .rx_hash_key_len = rss_key_len,
1822                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1823                                 .rx_hash_fields_mask = hash_fields,
1824                         },
1825                         .rwq_ind_tbl = ind_tbl->ind_table,
1826                         .pd = priv->sh->pd,
1827                  },
1828                  &qp_init_attr);
1829 #else
1830         qp = mlx5_glue->create_qp_ex
1831                 (priv->sh->ctx,
1832                  &(struct ibv_qp_init_attr_ex){
1833                         .qp_type = IBV_QPT_RAW_PACKET,
1834                         .comp_mask =
1835                                 IBV_QP_INIT_ATTR_PD |
1836                                 IBV_QP_INIT_ATTR_IND_TABLE |
1837                                 IBV_QP_INIT_ATTR_RX_HASH,
1838                         .rx_hash_conf = (struct ibv_rx_hash_conf){
1839                                 .rx_hash_function = IBV_RX_HASH_FUNC_TOEPLITZ,
1840                                 .rx_hash_key_len = rss_key_len,
1841                                 .rx_hash_key = (void *)(uintptr_t)rss_key,
1842                                 .rx_hash_fields_mask = hash_fields,
1843                         },
1844                         .rwq_ind_tbl = ind_tbl->ind_table,
1845                         .pd = priv->sh->pd,
1846                  });
1847 #endif
1848         if (!qp) {
1849                 rte_errno = errno;
1850                 goto error;
1851         }
1852         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
1853         if (!hrxq)
1854                 goto error;
1855         hrxq->ind_table = ind_tbl;
1856         hrxq->qp = qp;
1857         hrxq->rss_key_len = rss_key_len;
1858         hrxq->hash_fields = hash_fields;
1859         memcpy(hrxq->rss_key, rss_key, rss_key_len);
1860 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1861         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
1862         if (!hrxq->action) {
1863                 rte_errno = errno;
1864                 goto error;
1865         }
1866 #endif
1867         rte_atomic32_inc(&hrxq->refcnt);
1868         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
1869         return hrxq;
1870 error:
1871         err = rte_errno; /* Save rte_errno before cleanup. */
1872         mlx5_ind_table_obj_release(dev, ind_tbl);
1873         if (qp)
1874                 claim_zero(mlx5_glue->destroy_qp(qp));
1875         rte_errno = err; /* Restore rte_errno. */
1876         return NULL;
1877 }
1878
1879 /**
1880  * Get an Rx Hash queue.
1881  *
1882  * @param dev
1883  *   Pointer to Ethernet device.
1884  * @param rss_conf
1885  *   RSS configuration for the Rx hash queue.
1886  * @param queues
1887  *   Queues entering in hash queue. In case of empty hash_fields only the
1888  *   first queue index will be taken for the indirection table.
1889  * @param queues_n
1890  *   Number of queues.
1891  *
1892  * @return
1893  *   An hash Rx queue on success.
1894  */
1895 struct mlx5_hrxq *
1896 mlx5_hrxq_get(struct rte_eth_dev *dev,
1897               const uint8_t *rss_key, uint32_t rss_key_len,
1898               uint64_t hash_fields,
1899               const uint16_t *queues, uint32_t queues_n)
1900 {
1901         struct mlx5_priv *priv = dev->data->dev_private;
1902         struct mlx5_hrxq *hrxq;
1903
1904         queues_n = hash_fields ? queues_n : 1;
1905         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1906                 struct mlx5_ind_table_obj *ind_tbl;
1907
1908                 if (hrxq->rss_key_len != rss_key_len)
1909                         continue;
1910                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
1911                         continue;
1912                 if (hrxq->hash_fields != hash_fields)
1913                         continue;
1914                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
1915                 if (!ind_tbl)
1916                         continue;
1917                 if (ind_tbl != hrxq->ind_table) {
1918                         mlx5_ind_table_obj_release(dev, ind_tbl);
1919                         continue;
1920                 }
1921                 rte_atomic32_inc(&hrxq->refcnt);
1922                 return hrxq;
1923         }
1924         return NULL;
1925 }
1926
1927 /**
1928  * Release the hash Rx queue.
1929  *
1930  * @param dev
1931  *   Pointer to Ethernet device.
1932  * @param hrxq
1933  *   Pointer to Hash Rx queue to release.
1934  *
1935  * @return
1936  *   1 while a reference on it exists, 0 when freed.
1937  */
1938 int
1939 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
1940 {
1941         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
1942 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1943                 mlx5_glue->destroy_flow_action(hrxq->action);
1944 #endif
1945                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
1946                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
1947                 LIST_REMOVE(hrxq, next);
1948                 rte_free(hrxq);
1949                 return 0;
1950         }
1951         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
1952         return 1;
1953 }
1954
1955 /**
1956  * Verify the Rx Queue list is empty
1957  *
1958  * @param dev
1959  *   Pointer to Ethernet device.
1960  *
1961  * @return
1962  *   The number of object not released.
1963  */
1964 int
1965 mlx5_hrxq_verify(struct rte_eth_dev *dev)
1966 {
1967         struct mlx5_priv *priv = dev->data->dev_private;
1968         struct mlx5_hrxq *hrxq;
1969         int ret = 0;
1970
1971         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
1972                 DRV_LOG(DEBUG,
1973                         "port %u hash Rx queue %p still referenced",
1974                         dev->data->port_id, (void *)hrxq);
1975                 ++ret;
1976         }
1977         return ret;
1978 }
1979
1980 /**
1981  * Create a drop Rx queue Verbs/DevX object.
1982  *
1983  * @param dev
1984  *   Pointer to Ethernet device.
1985  *
1986  * @return
1987  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1988  */
1989 static struct mlx5_rxq_obj *
1990 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
1991 {
1992         struct mlx5_priv *priv = dev->data->dev_private;
1993         struct ibv_context *ctx = priv->sh->ctx;
1994         struct ibv_cq *cq;
1995         struct ibv_wq *wq = NULL;
1996         struct mlx5_rxq_obj *rxq;
1997
1998         if (priv->drop_queue.rxq)
1999                 return priv->drop_queue.rxq;
2000         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2001         if (!cq) {
2002                 DEBUG("port %u cannot allocate CQ for drop queue",
2003                       dev->data->port_id);
2004                 rte_errno = errno;
2005                 goto error;
2006         }
2007         wq = mlx5_glue->create_wq(ctx,
2008                  &(struct ibv_wq_init_attr){
2009                         .wq_type = IBV_WQT_RQ,
2010                         .max_wr = 1,
2011                         .max_sge = 1,
2012                         .pd = priv->sh->pd,
2013                         .cq = cq,
2014                  });
2015         if (!wq) {
2016                 DEBUG("port %u cannot allocate WQ for drop queue",
2017                       dev->data->port_id);
2018                 rte_errno = errno;
2019                 goto error;
2020         }
2021         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2022         if (!rxq) {
2023                 DEBUG("port %u cannot allocate drop Rx queue memory",
2024                       dev->data->port_id);
2025                 rte_errno = ENOMEM;
2026                 goto error;
2027         }
2028         rxq->cq = cq;
2029         rxq->wq = wq;
2030         priv->drop_queue.rxq = rxq;
2031         return rxq;
2032 error:
2033         if (wq)
2034                 claim_zero(mlx5_glue->destroy_wq(wq));
2035         if (cq)
2036                 claim_zero(mlx5_glue->destroy_cq(cq));
2037         return NULL;
2038 }
2039
2040 /**
2041  * Release a drop Rx queue Verbs/DevX object.
2042  *
2043  * @param dev
2044  *   Pointer to Ethernet device.
2045  *
2046  * @return
2047  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2048  */
2049 static void
2050 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2051 {
2052         struct mlx5_priv *priv = dev->data->dev_private;
2053         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2054
2055         if (rxq->wq)
2056                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2057         if (rxq->cq)
2058                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2059         rte_free(rxq);
2060         priv->drop_queue.rxq = NULL;
2061 }
2062
2063 /**
2064  * Create a drop indirection table.
2065  *
2066  * @param dev
2067  *   Pointer to Ethernet device.
2068  *
2069  * @return
2070  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2071  */
2072 static struct mlx5_ind_table_obj *
2073 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2074 {
2075         struct mlx5_priv *priv = dev->data->dev_private;
2076         struct mlx5_ind_table_obj *ind_tbl;
2077         struct mlx5_rxq_obj *rxq;
2078         struct mlx5_ind_table_obj tmpl;
2079
2080         rxq = mlx5_rxq_obj_drop_new(dev);
2081         if (!rxq)
2082                 return NULL;
2083         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2084                 (priv->sh->ctx,
2085                  &(struct ibv_rwq_ind_table_init_attr){
2086                         .log_ind_tbl_size = 0,
2087                         .ind_tbl = &rxq->wq,
2088                         .comp_mask = 0,
2089                  });
2090         if (!tmpl.ind_table) {
2091                 DEBUG("port %u cannot allocate indirection table for drop"
2092                       " queue",
2093                       dev->data->port_id);
2094                 rte_errno = errno;
2095                 goto error;
2096         }
2097         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2098         if (!ind_tbl) {
2099                 rte_errno = ENOMEM;
2100                 goto error;
2101         }
2102         ind_tbl->ind_table = tmpl.ind_table;
2103         return ind_tbl;
2104 error:
2105         mlx5_rxq_obj_drop_release(dev);
2106         return NULL;
2107 }
2108
2109 /**
2110  * Release a drop indirection table.
2111  *
2112  * @param dev
2113  *   Pointer to Ethernet device.
2114  */
2115 static void
2116 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2117 {
2118         struct mlx5_priv *priv = dev->data->dev_private;
2119         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2120
2121         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2122         mlx5_rxq_obj_drop_release(dev);
2123         rte_free(ind_tbl);
2124         priv->drop_queue.hrxq->ind_table = NULL;
2125 }
2126
2127 /**
2128  * Create a drop Rx Hash queue.
2129  *
2130  * @param dev
2131  *   Pointer to Ethernet device.
2132  *
2133  * @return
2134  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2135  */
2136 struct mlx5_hrxq *
2137 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2138 {
2139         struct mlx5_priv *priv = dev->data->dev_private;
2140         struct mlx5_ind_table_obj *ind_tbl;
2141         struct ibv_qp *qp;
2142         struct mlx5_hrxq *hrxq;
2143
2144         if (priv->drop_queue.hrxq) {
2145                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2146                 return priv->drop_queue.hrxq;
2147         }
2148         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2149         if (!ind_tbl)
2150                 return NULL;
2151         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2152                  &(struct ibv_qp_init_attr_ex){
2153                         .qp_type = IBV_QPT_RAW_PACKET,
2154                         .comp_mask =
2155                                 IBV_QP_INIT_ATTR_PD |
2156                                 IBV_QP_INIT_ATTR_IND_TABLE |
2157                                 IBV_QP_INIT_ATTR_RX_HASH,
2158                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2159                                 .rx_hash_function =
2160                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2161                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2162                                 .rx_hash_key = rss_hash_default_key,
2163                                 .rx_hash_fields_mask = 0,
2164                                 },
2165                         .rwq_ind_tbl = ind_tbl->ind_table,
2166                         .pd = priv->sh->pd
2167                  });
2168         if (!qp) {
2169                 DEBUG("port %u cannot allocate QP for drop queue",
2170                       dev->data->port_id);
2171                 rte_errno = errno;
2172                 goto error;
2173         }
2174         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2175         if (!hrxq) {
2176                 DRV_LOG(WARNING,
2177                         "port %u cannot allocate memory for drop queue",
2178                         dev->data->port_id);
2179                 rte_errno = ENOMEM;
2180                 goto error;
2181         }
2182         hrxq->ind_table = ind_tbl;
2183         hrxq->qp = qp;
2184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2185         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2186         if (!hrxq->action) {
2187                 rte_errno = errno;
2188                 goto error;
2189         }
2190 #endif
2191         priv->drop_queue.hrxq = hrxq;
2192         rte_atomic32_set(&hrxq->refcnt, 1);
2193         return hrxq;
2194 error:
2195         if (ind_tbl)
2196                 mlx5_ind_table_obj_drop_release(dev);
2197         return NULL;
2198 }
2199
2200 /**
2201  * Release a drop hash Rx queue.
2202  *
2203  * @param dev
2204  *   Pointer to Ethernet device.
2205  */
2206 void
2207 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2208 {
2209         struct mlx5_priv *priv = dev->data->dev_private;
2210         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2211
2212         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2213 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2214                 mlx5_glue->destroy_flow_action(hrxq->action);
2215 #endif
2216                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2217                 mlx5_ind_table_obj_drop_release(dev);
2218                 rte_free(hrxq);
2219                 priv->drop_queue.hrxq = NULL;
2220         }
2221 }