drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <errno.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <fcntl.h>
  11 #include <sys/queue.h>
  12
  13 /* Verbs header. */
  14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  15 #ifdef PEDANTIC
  16 #pragma GCC diagnostic ignored "-Wpedantic"
  17 #endif
  18 #include <infiniband/verbs.h>
  19 #include <infiniband/mlx5dv.h>
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic error "-Wpedantic"
  22 #endif
  23
  24 #include <rte_mbuf.h>
  25 #include <rte_malloc.h>
  26 #include <rte_ethdev_driver.h>
  27 #include <rte_common.h>
  28 #include <rte_interrupts.h>
  29 #include <rte_debug.h>
  30 #include <rte_io.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34
  35 #include "mlx5_defs.h"
  36 #include "mlx5.h"
  37 #include "mlx5_common_os.h"
  38 #include "mlx5_rxtx.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_flow.h"
  42
  43
  44 /* Default RSS hash key also used for ConnectX-3. */
  45 uint8_t rss_hash_default_key[] = {
  46         0x2c, 0xc6, 0x81, 0xd1,
  47         0x5b, 0xdb, 0xf4, 0xf7,
  48         0xfc, 0xa2, 0x83, 0x19,
  49         0xdb, 0x1a, 0x3e, 0x94,
  50         0x6b, 0x9e, 0x38, 0xd9,
  51         0x2c, 0x9c, 0x03, 0xd1,
  52         0xad, 0x99, 0x44, 0xa7,
  53         0xd9, 0x56, 0x3d, 0x59,
  54         0x06, 0x3c, 0x25, 0xf3,
  55         0xfc, 0x1f, 0xdc, 0x2a,
  56 };
  57
  58 /* Length of the default RSS hash key. */
  59 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  60               (unsigned int)sizeof(rss_hash_default_key),
  61               "wrong RSS default key size.");
  62
  63 /**
  64  * Check whether Multi-Packet RQ can be enabled for the device.
  65  *
  66  * @param dev
  67  *   Pointer to Ethernet device.
  68  *
  69  * @return
  70  *   1 if supported, negative errno value if not.
  71  */
  72 inline int
  73 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  74 {
  75         struct mlx5_priv *priv = dev->data->dev_private;
  76
  77         if (priv->config.mprq.enabled &&
  78             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  79                 return 1;
  80         return -ENOTSUP;
  81 }
  82
  83 /**
  84  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  85  *
  86  *  @param rxq
  87  *     Pointer to receive queue structure.
  88  *
  89  * @return
  90  *   0 if disabled, otherwise enabled.
  91  */
  92 inline int
  93 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  94 {
  95         return rxq->strd_num_n > 0;
  96 }
  97
  98 /**
  99  * Check whether Multi-Packet RQ is enabled for the device.
 100  *
 101  * @param dev
 102  *   Pointer to Ethernet device.
 103  *
 104  * @return
 105  *   0 if disabled, otherwise enabled.
 106  */
 107 inline int
 108 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 109 {
 110         struct mlx5_priv *priv = dev->data->dev_private;
 111         uint16_t i;
 112         uint16_t n = 0;
 113         uint16_t n_ibv = 0;
 114
 115         if (mlx5_check_mprq_support(dev) < 0)
 116                 return 0;
 117         /* All the configured queues should be enabled. */
 118         for (i = 0; i < priv->rxqs_n; ++i) {
 119                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 120                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
 121                         (rxq, struct mlx5_rxq_ctrl, rxq);
 122
 123                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
 124                         continue;
 125                 n_ibv++;
 126                 if (mlx5_rxq_mprq_enabled(rxq))
 127                         ++n;
 128         }
 129         /* Multi-Packet RQ can't be partially configured. */
 130         MLX5_ASSERT(n == 0 || n == n_ibv);
 131         return n == n_ibv;
 132 }
 133
 134 /**
 135  * Allocate RX queue elements for Multi-Packet RQ.
 136  *
 137  * @param rxq_ctrl
 138  *   Pointer to RX queue structure.
 139  *
 140  * @return
 141  *   0 on success, a negative errno value otherwise and rte_errno is set.
 142  */
 143 static int
 144 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 145 {
 146         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 147         unsigned int wqe_n = 1 << rxq->elts_n;
 148         unsigned int i;
 149         int err;
 150
 151         /* Iterate on segments. */
 152         for (i = 0; i <= wqe_n; ++i) {
 153                 struct mlx5_mprq_buf *buf;
 154
 155                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 156                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 157                         rte_errno = ENOMEM;
 158                         goto error;
 159                 }
 160                 if (i < wqe_n)
 161                         (*rxq->mprq_bufs)[i] = buf;
 162                 else
 163                         rxq->mprq_repl = buf;
 164         }
 165         DRV_LOG(DEBUG,
 166                 "port %u Rx queue %u allocated and configured %u segments",
 167                 rxq->port_id, rxq->idx, wqe_n);
 168         return 0;
 169 error:
 170         err = rte_errno; /* Save rte_errno before cleanup. */
 171         wqe_n = i;
 172         for (i = 0; (i != wqe_n); ++i) {
 173                 if ((*rxq->mprq_bufs)[i] != NULL)
 174                         rte_mempool_put(rxq->mprq_mp,
 175                                         (*rxq->mprq_bufs)[i]);
 176                 (*rxq->mprq_bufs)[i] = NULL;
 177         }
 178         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 179                 rxq->port_id, rxq->idx);
 180         rte_errno = err; /* Restore rte_errno. */
 181         return -rte_errno;
 182 }
 183
 184 /**
 185  * Allocate RX queue elements for Single-Packet RQ.
 186  *
 187  * @param rxq_ctrl
 188  *   Pointer to RX queue structure.
 189  *
 190  * @return
 191  *   0 on success, errno value on failure.
 192  */
 193 static int
 194 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 195 {
 196         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 197         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 198         unsigned int i;
 199         int err;
 200
 201         /* Iterate on segments. */
 202         for (i = 0; (i != elts_n); ++i) {
 203                 struct rte_mbuf *buf;
 204
 205                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 206                 if (buf == NULL) {
 207                         DRV_LOG(ERR, "port %u empty mbuf pool",
 208                                 PORT_ID(rxq_ctrl->priv));
 209                         rte_errno = ENOMEM;
 210                         goto error;
 211                 }
 212                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 213                 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 214                 /* Buffer is supposed to be empty. */
 215                 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
 216                 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
 217                 MLX5_ASSERT(!buf->next);
 218                 /* Only the first segment keeps headroom. */
 219                 if (i % sges_n)
 220                         SET_DATA_OFF(buf, 0);
 221                 PORT(buf) = rxq_ctrl->rxq.port_id;
 222                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 223                 PKT_LEN(buf) = DATA_LEN(buf);
 224                 NB_SEGS(buf) = 1;
 225                 (*rxq_ctrl->rxq.elts)[i] = buf;
 226         }
 227         /* If Rx vector is activated. */
 228         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 229                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 230                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 231                 struct rte_pktmbuf_pool_private *priv =
 232                         (struct rte_pktmbuf_pool_private *)
 233                                 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
 234                 int j;
 235
 236                 /* Initialize default rearm_data for vPMD. */
 237                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 238                 rte_mbuf_refcnt_set(mbuf_init, 1);
 239                 mbuf_init->nb_segs = 1;
 240                 mbuf_init->port = rxq->port_id;
 241                 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
 242                         mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
 243                 /*
 244                  * prevent compiler reordering:
 245                  * rearm_data covers previous fields.
 246                  */
 247                 rte_compiler_barrier();
 248                 rxq->mbuf_initializer =
 249                         *(rte_xmm_t *)&mbuf_init->rearm_data;
 250                 /* Padding with a fake mbuf for vectorized Rx. */
 251                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 252                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 253         }
 254         DRV_LOG(DEBUG,
 255                 "port %u Rx queue %u allocated and configured %u segments"
 256                 " (max %u packets)",
 257                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 258                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 259         return 0;
 260 error:
 261         err = rte_errno; /* Save rte_errno before cleanup. */
 262         elts_n = i;
 263         for (i = 0; (i != elts_n); ++i) {
 264                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 265                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 266                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 267         }
 268         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 269                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 270         rte_errno = err; /* Restore rte_errno. */
 271         return -rte_errno;
 272 }
 273
 274 /**
 275  * Allocate RX queue elements.
 276  *
 277  * @param rxq_ctrl
 278  *   Pointer to RX queue structure.
 279  *
 280  * @return
 281  *   0 on success, errno value on failure.
 282  */
 283 int
 284 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 285 {
 286         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 287                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 288 }
 289
 290 /**
 291  * Free RX queue elements for Multi-Packet RQ.
 292  *
 293  * @param rxq_ctrl
 294  *   Pointer to RX queue structure.
 295  */
 296 static void
 297 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 298 {
 299         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 300         uint16_t i;
 301
 302         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 303                 rxq->port_id, rxq->idx);
 304         if (rxq->mprq_bufs == NULL)
 305                 return;
 306         MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
 307         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 308                 if ((*rxq->mprq_bufs)[i] != NULL)
 309                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 310                 (*rxq->mprq_bufs)[i] = NULL;
 311         }
 312         if (rxq->mprq_repl != NULL) {
 313                 mlx5_mprq_buf_free(rxq->mprq_repl);
 314                 rxq->mprq_repl = NULL;
 315         }
 316 }
 317
 318 /**
 319  * Free RX queue elements for Single-Packet RQ.
 320  *
 321  * @param rxq_ctrl
 322  *   Pointer to RX queue structure.
 323  */
 324 static void
 325 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 326 {
 327         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 328         const uint16_t q_n = (1 << rxq->elts_n);
 329         const uint16_t q_mask = q_n - 1;
 330         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 331         uint16_t i;
 332
 333         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 334                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 335         if (rxq->elts == NULL)
 336                 return;
 337         /**
 338          * Some mbuf in the Ring belongs to the application.  They cannot be
 339          * freed.
 340          */
 341         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 342                 for (i = 0; i < used; ++i)
 343                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 344                 rxq->rq_pi = rxq->rq_ci;
 345         }
 346         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 347                 if ((*rxq->elts)[i] != NULL)
 348                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 349                 (*rxq->elts)[i] = NULL;
 350         }
 351 }
 352
 353 /**
 354  * Free RX queue elements.
 355  *
 356  * @param rxq_ctrl
 357  *   Pointer to RX queue structure.
 358  */
 359 static void
 360 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 361 {
 362         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 363                 rxq_free_elts_mprq(rxq_ctrl);
 364         else
 365                 rxq_free_elts_sprq(rxq_ctrl);
 366 }
 367
 368 /**
 369  * Returns the per-queue supported offloads.
 370  *
 371  * @param dev
 372  *   Pointer to Ethernet device.
 373  *
 374  * @return
 375  *   Supported Rx offloads.
 376  */
 377 uint64_t
 378 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 379 {
 380         struct mlx5_priv *priv = dev->data->dev_private;
 381         struct mlx5_dev_config *config = &priv->config;
 382         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 383                              DEV_RX_OFFLOAD_TIMESTAMP |
 384                              DEV_RX_OFFLOAD_JUMBO_FRAME |
 385                              DEV_RX_OFFLOAD_RSS_HASH);
 386
 387         if (config->hw_fcs_strip)
 388                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 389
 390         if (config->hw_csum)
 391                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 392                              DEV_RX_OFFLOAD_UDP_CKSUM |
 393                              DEV_RX_OFFLOAD_TCP_CKSUM);
 394         if (config->hw_vlan_strip)
 395                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 396         if (MLX5_LRO_SUPPORTED(dev))
 397                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 398         return offloads;
 399 }
 400
 401
 402 /**
 403  * Returns the per-port supported offloads.
 404  *
 405  * @return
 406  *   Supported Rx offloads.
 407  */
 408 uint64_t
 409 mlx5_get_rx_port_offloads(void)
 410 {
 411         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 412
 413         return offloads;
 414 }
 415
 416 /**
 417  * Verify if the queue can be released.
 418  *
 419  * @param dev
 420  *   Pointer to Ethernet device.
 421  * @param idx
 422  *   RX queue index.
 423  *
 424  * @return
 425  *   1 if the queue can be released
 426  *   0 if the queue can not be released, there are references to it.
 427  *   Negative errno and rte_errno is set if queue doesn't exist.
 428  */
 429 static int
 430 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 431 {
 432         struct mlx5_priv *priv = dev->data->dev_private;
 433         struct mlx5_rxq_ctrl *rxq_ctrl;
 434
 435         if (!(*priv->rxqs)[idx]) {
 436                 rte_errno = EINVAL;
 437                 return -rte_errno;
 438         }
 439         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 440         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 441 }
 442
 443 /**
 444  * Rx queue presetup checks.
 445  *
 446  * @param dev
 447  *   Pointer to Ethernet device structure.
 448  * @param idx
 449  *   RX queue index.
 450  * @param desc
 451  *   Number of descriptors to configure in queue.
 452  *
 453  * @return
 454  *   0 on success, a negative errno value otherwise and rte_errno is set.
 455  */
 456 static int
 457 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
 458 {
 459         struct mlx5_priv *priv = dev->data->dev_private;
 460
 461         if (!rte_is_power_of_2(*desc)) {
 462                 *desc = 1 << log2above(*desc);
 463                 DRV_LOG(WARNING,
 464                         "port %u increased number of descriptors in Rx queue %u"
 465                         " to the next power of two (%d)",
 466                         dev->data->port_id, idx, *desc);
 467         }
 468         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 469                 dev->data->port_id, idx, *desc);
 470         if (idx >= priv->rxqs_n) {
 471                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 472                         dev->data->port_id, idx, priv->rxqs_n);
 473                 rte_errno = EOVERFLOW;
 474                 return -rte_errno;
 475         }
 476         if (!mlx5_rxq_releasable(dev, idx)) {
 477                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 478                         dev->data->port_id, idx);
 479                 rte_errno = EBUSY;
 480                 return -rte_errno;
 481         }
 482         mlx5_rxq_release(dev, idx);
 483         return 0;
 484 }
 485
 486 /**
 487  *
 488  * @param dev
 489  *   Pointer to Ethernet device structure.
 490  * @param idx
 491  *   RX queue index.
 492  * @param desc
 493  *   Number of descriptors to configure in queue.
 494  * @param socket
 495  *   NUMA socket on which memory must be allocated.
 496  * @param[in] conf
 497  *   Thresholds parameters.
 498  * @param mp
 499  *   Memory pool for buffer allocations.
 500  *
 501  * @return
 502  *   0 on success, a negative errno value otherwise and rte_errno is set.
 503  */
 504 int
 505 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 506                     unsigned int socket, const struct rte_eth_rxconf *conf,
 507                     struct rte_mempool *mp)
 508 {
 509         struct mlx5_priv *priv = dev->data->dev_private;
 510         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 511         struct mlx5_rxq_ctrl *rxq_ctrl =
 512                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 513         int res;
 514
 515         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 516         if (res)
 517                 return res;
 518         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 519         if (!rxq_ctrl) {
 520                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 521                         dev->data->port_id, idx);
 522                 rte_errno = ENOMEM;
 523                 return -rte_errno;
 524         }
 525         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 526                 dev->data->port_id, idx);
 527         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 528         return 0;
 529 }
 530
 531 /**
 532  *
 533  * @param dev
 534  *   Pointer to Ethernet device structure.
 535  * @param idx
 536  *   RX queue index.
 537  * @param desc
 538  *   Number of descriptors to configure in queue.
 539  * @param hairpin_conf
 540  *   Hairpin configuration parameters.
 541  *
 542  * @return
 543  *   0 on success, a negative errno value otherwise and rte_errno is set.
 544  */
 545 int
 546 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 547                             uint16_t desc,
 548                             const struct rte_eth_hairpin_conf *hairpin_conf)
 549 {
 550         struct mlx5_priv *priv = dev->data->dev_private;
 551         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 552         struct mlx5_rxq_ctrl *rxq_ctrl =
 553                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 554         int res;
 555
 556         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 557         if (res)
 558                 return res;
 559         if (hairpin_conf->peer_count != 1 ||
 560             hairpin_conf->peers[0].port != dev->data->port_id ||
 561             hairpin_conf->peers[0].queue >= priv->txqs_n) {
 562                 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
 563                         " invalid hairpind configuration", dev->data->port_id,
 564                         idx);
 565                 rte_errno = EINVAL;
 566                 return -rte_errno;
 567         }
 568         rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
 569         if (!rxq_ctrl) {
 570                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 571                         dev->data->port_id, idx);
 572                 rte_errno = ENOMEM;
 573                 return -rte_errno;
 574         }
 575         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 576                 dev->data->port_id, idx);
 577         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 578         return 0;
 579 }
 580
 581 /**
 582  * DPDK callback to release a RX queue.
 583  *
 584  * @param dpdk_rxq
 585  *   Generic RX queue pointer.
 586  */
 587 void
 588 mlx5_rx_queue_release(void *dpdk_rxq)
 589 {
 590         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 591         struct mlx5_rxq_ctrl *rxq_ctrl;
 592         struct mlx5_priv *priv;
 593
 594         if (rxq == NULL)
 595                 return;
 596         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 597         priv = rxq_ctrl->priv;
 598         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 599                 rte_panic("port %u Rx queue %u is still used by a flow and"
 600                           " cannot be removed\n",
 601                           PORT_ID(priv), rxq->idx);
 602         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 603 }
 604
 605 /**
 606  * Get an Rx queue Verbs/DevX object.
 607  *
 608  * @param dev
 609  *   Pointer to Ethernet device.
 610  * @param idx
 611  *   Queue index in DPDK Rx queue array
 612  *
 613  * @return
 614  *   The Verbs/DevX object if it exists.
 615  */
 616 static struct mlx5_rxq_obj *
 617 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 618 {
 619         struct mlx5_priv *priv = dev->data->dev_private;
 620         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 621         struct mlx5_rxq_ctrl *rxq_ctrl;
 622
 623         if (idx >= priv->rxqs_n)
 624                 return NULL;
 625         if (!rxq_data)
 626                 return NULL;
 627         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 628         if (rxq_ctrl->obj)
 629                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 630         return rxq_ctrl->obj;
 631 }
 632
 633 /**
 634  * Release the resources allocated for an RQ DevX object.
 635  *
 636  * @param rxq_ctrl
 637  *   DevX Rx queue object.
 638  */
 639 static void
 640 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 641 {
 642         if (rxq_ctrl->rxq.wqes) {
 643                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 644                 rxq_ctrl->rxq.wqes = NULL;
 645         }
 646         if (rxq_ctrl->wq_umem) {
 647                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 648                 rxq_ctrl->wq_umem = NULL;
 649         }
 650 }
 651
 652 /**
 653  * Release an Rx hairpin related resources.
 654  *
 655  * @param rxq_obj
 656  *   Hairpin Rx queue object.
 657  */
 658 static void
 659 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
 660 {
 661         struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
 662
 663         MLX5_ASSERT(rxq_obj);
 664         rq_attr.state = MLX5_RQC_STATE_RST;
 665         rq_attr.rq_state = MLX5_RQC_STATE_RDY;
 666         mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
 667         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 668 }
 669
 670 /**
 671  * Release an Rx verbs/DevX queue object.
 672  *
 673  * @param rxq_obj
 674  *   Verbs/DevX Rx queue object.
 675  *
 676  * @return
 677  *   1 while a reference on it exists, 0 when freed.
 678  */
 679 static int
 680 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 681 {
 682         MLX5_ASSERT(rxq_obj);
 683         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 684                 switch (rxq_obj->type) {
 685                 case MLX5_RXQ_OBJ_TYPE_IBV:
 686                         MLX5_ASSERT(rxq_obj->wq);
 687                         MLX5_ASSERT(rxq_obj->cq);
 688                         rxq_free_elts(rxq_obj->rxq_ctrl);
 689                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 690                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 691                         break;
 692                 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
 693                         MLX5_ASSERT(rxq_obj->cq);
 694                         MLX5_ASSERT(rxq_obj->rq);
 695                         rxq_free_elts(rxq_obj->rxq_ctrl);
 696                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 697                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 698                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 699                         break;
 700                 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
 701                         MLX5_ASSERT(rxq_obj->rq);
 702                         rxq_obj_hairpin_release(rxq_obj);
 703                         break;
 704                 }
 705                 if (rxq_obj->channel)
 706                         claim_zero(mlx5_glue->destroy_comp_channel
 707                                    (rxq_obj->channel));
 708                 LIST_REMOVE(rxq_obj, next);
 709                 rte_free(rxq_obj);
 710                 return 0;
 711         }
 712         return 1;
 713 }
 714
 715 /**
 716  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 717  *
 718  * @param dev
 719  *   Pointer to Ethernet device.
 720  *
 721  * @return
 722  *   0 on success, a negative errno value otherwise and rte_errno is set.
 723  */
 724 int
 725 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 726 {
 727         struct mlx5_priv *priv = dev->data->dev_private;
 728         unsigned int i;
 729         unsigned int rxqs_n = priv->rxqs_n;
 730         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 731         unsigned int count = 0;
 732         struct rte_intr_handle *intr_handle = dev->intr_handle;
 733
 734         if (!dev->data->dev_conf.intr_conf.rxq)
 735                 return 0;
 736         mlx5_rx_intr_vec_disable(dev);
 737         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 738         if (intr_handle->intr_vec == NULL) {
 739                 DRV_LOG(ERR,
 740                         "port %u failed to allocate memory for interrupt"
 741                         " vector, Rx interrupts will not be supported",
 742                         dev->data->port_id);
 743                 rte_errno = ENOMEM;
 744                 return -rte_errno;
 745         }
 746         intr_handle->type = RTE_INTR_HANDLE_EXT;
 747         for (i = 0; i != n; ++i) {
 748                 /* This rxq obj must not be released in this function. */
 749                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 750                 int fd;
 751                 int flags;
 752                 int rc;
 753
 754                 /* Skip queues that cannot request interrupts. */
 755                 if (!rxq_obj || !rxq_obj->channel) {
 756                         /* Use invalid intr_vec[] index to disable entry. */
 757                         intr_handle->intr_vec[i] =
 758                                 RTE_INTR_VEC_RXTX_OFFSET +
 759                                 RTE_MAX_RXTX_INTR_VEC_ID;
 760                         continue;
 761                 }
 762                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 763                         DRV_LOG(ERR,
 764                                 "port %u too many Rx queues for interrupt"
 765                                 " vector size (%d), Rx interrupts cannot be"
 766                                 " enabled",
 767                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 768                         mlx5_rx_intr_vec_disable(dev);
 769                         rte_errno = ENOMEM;
 770                         return -rte_errno;
 771                 }
 772                 fd = rxq_obj->channel->fd;
 773                 flags = fcntl(fd, F_GETFL);
 774                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 775                 if (rc < 0) {
 776                         rte_errno = errno;
 777                         DRV_LOG(ERR,
 778                                 "port %u failed to make Rx interrupt file"
 779                                 " descriptor %d non-blocking for queue index"
 780                                 " %d",
 781                                 dev->data->port_id, fd, i);
 782                         mlx5_rx_intr_vec_disable(dev);
 783                         return -rte_errno;
 784                 }
 785                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 786                 intr_handle->efds[count] = fd;
 787                 count++;
 788         }
 789         if (!count)
 790                 mlx5_rx_intr_vec_disable(dev);
 791         else
 792                 intr_handle->nb_efd = count;
 793         return 0;
 794 }
 795
 796 /**
 797  * Clean up Rx interrupts handler.
 798  *
 799  * @param dev
 800  *   Pointer to Ethernet device.
 801  */
 802 void
 803 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 804 {
 805         struct mlx5_priv *priv = dev->data->dev_private;
 806         struct rte_intr_handle *intr_handle = dev->intr_handle;
 807         unsigned int i;
 808         unsigned int rxqs_n = priv->rxqs_n;
 809         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 810
 811         if (!dev->data->dev_conf.intr_conf.rxq)
 812                 return;
 813         if (!intr_handle->intr_vec)
 814                 goto free;
 815         for (i = 0; i != n; ++i) {
 816                 struct mlx5_rxq_ctrl *rxq_ctrl;
 817                 struct mlx5_rxq_data *rxq_data;
 818
 819                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 820                     RTE_MAX_RXTX_INTR_VEC_ID)
 821                         continue;
 822                 /**
 823                  * Need to access directly the queue to release the reference
 824                  * kept in mlx5_rx_intr_vec_enable().
 825                  */
 826                 rxq_data = (*priv->rxqs)[i];
 827                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 828                 if (rxq_ctrl->obj)
 829                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 830         }
 831 free:
 832         rte_intr_free_epoll_fd(intr_handle);
 833         if (intr_handle->intr_vec)
 834                 free(intr_handle->intr_vec);
 835         intr_handle->nb_efd = 0;
 836         intr_handle->intr_vec = NULL;
 837 }
 838
 839 /**
 840  *  MLX5 CQ notification .
 841  *
 842  *  @param rxq
 843  *     Pointer to receive queue structure.
 844  *  @param sq_n_rxq
 845  *     Sequence number per receive queue .
 846  */
 847 static inline void
 848 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 849 {
 850         int sq_n = 0;
 851         uint32_t doorbell_hi;
 852         uint64_t doorbell;
 853         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 854
 855         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 856         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 857         doorbell = (uint64_t)doorbell_hi << 32;
 858         doorbell |=  rxq->cqn;
 859         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 860         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 861                          cq_db_reg, rxq->uar_lock_cq);
 862 }
 863
 864 /**
 865  * DPDK callback for Rx queue interrupt enable.
 866  *
 867  * @param dev
 868  *   Pointer to Ethernet device structure.
 869  * @param rx_queue_id
 870  *   Rx queue number.
 871  *
 872  * @return
 873  *   0 on success, a negative errno value otherwise and rte_errno is set.
 874  */
 875 int
 876 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 877 {
 878         struct mlx5_priv *priv = dev->data->dev_private;
 879         struct mlx5_rxq_data *rxq_data;
 880         struct mlx5_rxq_ctrl *rxq_ctrl;
 881
 882         rxq_data = (*priv->rxqs)[rx_queue_id];
 883         if (!rxq_data) {
 884                 rte_errno = EINVAL;
 885                 return -rte_errno;
 886         }
 887         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 888         if (rxq_ctrl->irq) {
 889                 struct mlx5_rxq_obj *rxq_obj;
 890
 891                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 892                 if (!rxq_obj) {
 893                         rte_errno = EINVAL;
 894                         return -rte_errno;
 895                 }
 896                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 897                 mlx5_rxq_obj_release(rxq_obj);
 898         }
 899         return 0;
 900 }
 901
 902 /**
 903  * DPDK callback for Rx queue interrupt disable.
 904  *
 905  * @param dev
 906  *   Pointer to Ethernet device structure.
 907  * @param rx_queue_id
 908  *   Rx queue number.
 909  *
 910  * @return
 911  *   0 on success, a negative errno value otherwise and rte_errno is set.
 912  */
 913 int
 914 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 915 {
 916         struct mlx5_priv *priv = dev->data->dev_private;
 917         struct mlx5_rxq_data *rxq_data;
 918         struct mlx5_rxq_ctrl *rxq_ctrl;
 919         struct mlx5_rxq_obj *rxq_obj = NULL;
 920         struct ibv_cq *ev_cq;
 921         void *ev_ctx;
 922         int ret;
 923
 924         rxq_data = (*priv->rxqs)[rx_queue_id];
 925         if (!rxq_data) {
 926                 rte_errno = EINVAL;
 927                 return -rte_errno;
 928         }
 929         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 930         if (!rxq_ctrl->irq)
 931                 return 0;
 932         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 933         if (!rxq_obj) {
 934                 rte_errno = EINVAL;
 935                 return -rte_errno;
 936         }
 937         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 938         if (ret || ev_cq != rxq_obj->cq) {
 939                 rte_errno = EINVAL;
 940                 goto exit;
 941         }
 942         rxq_data->cq_arm_sn++;
 943         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 944         mlx5_rxq_obj_release(rxq_obj);
 945         return 0;
 946 exit:
 947         ret = rte_errno; /* Save rte_errno before cleanup. */
 948         if (rxq_obj)
 949                 mlx5_rxq_obj_release(rxq_obj);
 950         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 951                 dev->data->port_id, rx_queue_id);
 952         rte_errno = ret; /* Restore rte_errno. */
 953         return -rte_errno;
 954 }
 955
 956 /**
 957  * Create a CQ Verbs object.
 958  *
 959  * @param dev
 960  *   Pointer to Ethernet device.
 961  * @param priv
 962  *   Pointer to device private data.
 963  * @param rxq_data
 964  *   Pointer to Rx queue data.
 965  * @param cqe_n
 966  *   Number of CQEs in CQ.
 967  * @param rxq_obj
 968  *   Pointer to Rx queue object data.
 969  *
 970  * @return
 971  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 972  */
 973 static struct ibv_cq *
 974 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 975                 struct mlx5_rxq_data *rxq_data,
 976                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 977 {
 978         struct {
 979                 struct ibv_cq_init_attr_ex ibv;
 980                 struct mlx5dv_cq_init_attr mlx5;
 981         } cq_attr;
 982
 983         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 984                 .cqe = cqe_n,
 985                 .channel = rxq_obj->channel,
 986                 .comp_mask = 0,
 987         };
 988         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 989                 .comp_mask = 0,
 990         };
 991         if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
 992             !rxq_data->lro) {
 993                 cq_attr.mlx5.comp_mask |=
 994                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 995 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 996                 cq_attr.mlx5.cqe_comp_res_format =
 997                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 998                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 999                                 MLX5DV_CQE_RES_FORMAT_HASH;
1000 #else
1001                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1002 #endif
1003                 /*
1004                  * For vectorized Rx, it must not be doubled in order to
1005                  * make cq_ci and rq_ci aligned.
1006                  */
1007                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1008                         cq_attr.ibv.cqe *= 2;
1009         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1010                 DRV_LOG(DEBUG,
1011                         "port %u Rx CQE compression is disabled for HW"
1012                         " timestamp",
1013                         dev->data->port_id);
1014         } else if (priv->config.cqe_comp && rxq_data->lro) {
1015                 DRV_LOG(DEBUG,
1016                         "port %u Rx CQE compression is disabled for LRO",
1017                         dev->data->port_id);
1018         }
1019 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1020         if (priv->config.cqe_pad) {
1021                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1022                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1023         }
1024 #endif
1025         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1026                                                               &cq_attr.ibv,
1027                                                               &cq_attr.mlx5));
1028 }
1029
1030 /**
1031  * Create a WQ Verbs object.
1032  *
1033  * @param dev
1034  *   Pointer to Ethernet device.
1035  * @param priv
1036  *   Pointer to device private data.
1037  * @param rxq_data
1038  *   Pointer to Rx queue data.
1039  * @param idx
1040  *   Queue index in DPDK Rx queue array
1041  * @param wqe_n
1042  *   Number of WQEs in WQ.
1043  * @param rxq_obj
1044  *   Pointer to Rx queue object data.
1045  *
1046  * @return
1047  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1048  */
1049 static struct ibv_wq *
1050 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1051                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1052                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1053 {
1054         struct {
1055                 struct ibv_wq_init_attr ibv;
1056 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1057                 struct mlx5dv_wq_init_attr mlx5;
1058 #endif
1059         } wq_attr;
1060
1061         wq_attr.ibv = (struct ibv_wq_init_attr){
1062                 .wq_context = NULL, /* Could be useful in the future. */
1063                 .wq_type = IBV_WQT_RQ,
1064                 /* Max number of outstanding WRs. */
1065                 .max_wr = wqe_n >> rxq_data->sges_n,
1066                 /* Max number of scatter/gather elements in a WR. */
1067                 .max_sge = 1 << rxq_data->sges_n,
1068                 .pd = priv->sh->pd,
1069                 .cq = rxq_obj->cq,
1070                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1071                 .create_flags = (rxq_data->vlan_strip ?
1072                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1073         };
1074         /* By default, FCS (CRC) is stripped by hardware. */
1075         if (rxq_data->crc_present) {
1076                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1077                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1078         }
1079         if (priv->config.hw_padding) {
1080 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1081                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1082                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1083 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1084                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1085                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1086 #endif
1087         }
1088 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1089         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1090                 .comp_mask = 0,
1091         };
1092         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1093                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1094                                                 &wq_attr.mlx5.striding_rq_attrs;
1095
1096                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1097                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1098                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1099                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1100                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1101                 };
1102         }
1103         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1104                                               &wq_attr.mlx5);
1105 #else
1106         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1107 #endif
1108         if (rxq_obj->wq) {
1109                 /*
1110                  * Make sure number of WRs*SGEs match expectations since a queue
1111                  * cannot allocate more than "desc" buffers.
1112                  */
1113                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1114                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1115                         DRV_LOG(ERR,
1116                                 "port %u Rx queue %u requested %u*%u but got"
1117                                 " %u*%u WRs*SGEs",
1118                                 dev->data->port_id, idx,
1119                                 wqe_n >> rxq_data->sges_n,
1120                                 (1 << rxq_data->sges_n),
1121                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1122                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1123                         rxq_obj->wq = NULL;
1124                         rte_errno = EINVAL;
1125                 }
1126         }
1127         return rxq_obj->wq;
1128 }
1129
1130 /**
1131  * Fill common fields of create RQ attributes structure.
1132  *
1133  * @param rxq_data
1134  *   Pointer to Rx queue data.
1135  * @param cqn
1136  *   CQ number to use with this RQ.
1137  * @param rq_attr
1138  *   RQ attributes structure to fill..
1139  */
1140 static void
1141 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1142                               struct mlx5_devx_create_rq_attr *rq_attr)
1143 {
1144         rq_attr->state = MLX5_RQC_STATE_RST;
1145         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1146         rq_attr->cqn = cqn;
1147         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1148 }
1149
1150 /**
1151  * Fill common fields of DevX WQ attributes structure.
1152  *
1153  * @param priv
1154  *   Pointer to device private data.
1155  * @param rxq_ctrl
1156  *   Pointer to Rx queue control structure.
1157  * @param wq_attr
1158  *   WQ attributes structure to fill..
1159  */
1160 static void
1161 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1162                        struct mlx5_devx_wq_attr *wq_attr)
1163 {
1164         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1165                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1166                                         MLX5_WQ_END_PAD_MODE_NONE;
1167         wq_attr->pd = priv->sh->pdn;
1168         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1169         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1170         wq_attr->dbr_umem_valid = 1;
1171         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1172         wq_attr->wq_umem_valid = 1;
1173 }
1174
1175 /**
1176  * Create a RQ object using DevX.
1177  *
1178  * @param dev
1179  *   Pointer to Ethernet device.
1180  * @param idx
1181  *   Queue index in DPDK Rx queue array
1182  * @param cqn
1183  *   CQ number to use with this RQ.
1184  *
1185  * @return
1186  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1187  */
1188 static struct mlx5_devx_obj *
1189 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1190 {
1191         struct mlx5_priv *priv = dev->data->dev_private;
1192         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1193         struct mlx5_rxq_ctrl *rxq_ctrl =
1194                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1195         struct mlx5_devx_create_rq_attr rq_attr;
1196         uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1197         uint32_t wq_size = 0;
1198         uint32_t wqe_size = 0;
1199         uint32_t log_wqe_size = 0;
1200         void *buf = NULL;
1201         struct mlx5_devx_obj *rq;
1202
1203         memset(&rq_attr, 0, sizeof(rq_attr));
1204         /* Fill RQ attributes. */
1205         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1206         rq_attr.flush_in_error_en = 1;
1207         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1208         /* Fill WQ attributes for this RQ. */
1209         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1210                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1211                 /*
1212                  * Number of strides in each WQE:
1213                  * 512*2^single_wqe_log_num_of_strides.
1214                  */
1215                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1216                                 rxq_data->strd_num_n -
1217                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1218                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1219                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1220                                 rxq_data->strd_sz_n -
1221                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1222                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1223         } else {
1224                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1225                 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1226         }
1227         log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1228         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1229         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1230         /* Calculate and allocate WQ memory space. */
1231         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1232         wq_size = wqe_n * wqe_size;
1233         buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1234                                 rxq_ctrl->socket);
1235         if (!buf)
1236                 return NULL;
1237         rxq_data->wqes = buf;
1238         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1239                                                      buf, wq_size, 0);
1240         if (!rxq_ctrl->wq_umem) {
1241                 rte_free(buf);
1242                 return NULL;
1243         }
1244         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1245         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1246         if (!rq)
1247                 rxq_release_rq_resources(rxq_ctrl);
1248         return rq;
1249 }
1250
1251 /**
1252  * Create the Rx hairpin queue object.
1253  *
1254  * @param dev
1255  *   Pointer to Ethernet device.
1256  * @param idx
1257  *   Queue index in DPDK Rx queue array
1258  *
1259  * @return
1260  *   The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1261  */
1262 static struct mlx5_rxq_obj *
1263 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1264 {
1265         struct mlx5_priv *priv = dev->data->dev_private;
1266         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1267         struct mlx5_rxq_ctrl *rxq_ctrl =
1268                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1269         struct mlx5_devx_create_rq_attr attr = { 0 };
1270         struct mlx5_rxq_obj *tmpl = NULL;
1271         uint32_t max_wq_data;
1272
1273         MLX5_ASSERT(rxq_data);
1274         MLX5_ASSERT(!rxq_ctrl->obj);
1275         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1276                                  rxq_ctrl->socket);
1277         if (!tmpl) {
1278                 DRV_LOG(ERR,
1279                         "port %u Rx queue %u cannot allocate verbs resources",
1280                         dev->data->port_id, rxq_data->idx);
1281                 rte_errno = ENOMEM;
1282                 return NULL;
1283         }
1284         tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1285         tmpl->rxq_ctrl = rxq_ctrl;
1286         attr.hairpin = 1;
1287         max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1288         /* Jumbo frames > 9KB should be supported, and more packets. */
1289         if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1290                 if (priv->config.log_hp_size > max_wq_data) {
1291                         DRV_LOG(ERR, "total data size %u power of 2 is "
1292                                 "too large for hairpin",
1293                                 priv->config.log_hp_size);
1294                         rte_free(tmpl);
1295                         rte_errno = ERANGE;
1296                         return NULL;
1297                 }
1298                 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1299         } else {
1300                 attr.wq_attr.log_hairpin_data_sz =
1301                                 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1302                                  max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1303         }
1304         /* Set the packets number to the maximum value for performance. */
1305         attr.wq_attr.log_hairpin_num_packets =
1306                         attr.wq_attr.log_hairpin_data_sz -
1307                         MLX5_HAIRPIN_QUEUE_STRIDE;
1308         tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1309                                            rxq_ctrl->socket);
1310         if (!tmpl->rq) {
1311                 DRV_LOG(ERR,
1312                         "port %u Rx hairpin queue %u can't create rq object",
1313                         dev->data->port_id, idx);
1314                 rte_free(tmpl);
1315                 rte_errno = errno;
1316                 return NULL;
1317         }
1318         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1319                 idx, (void *)&tmpl);
1320         rte_atomic32_inc(&tmpl->refcnt);
1321         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1322         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1323         return tmpl;
1324 }
1325
1326 /**
1327  * Create the Rx queue Verbs/DevX object.
1328  *
1329  * @param dev
1330  *   Pointer to Ethernet device.
1331  * @param idx
1332  *   Queue index in DPDK Rx queue array
1333  * @param type
1334  *   Type of Rx queue object to create.
1335  *
1336  * @return
1337  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1338  */
1339 struct mlx5_rxq_obj *
1340 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1341                  enum mlx5_rxq_obj_type type)
1342 {
1343         struct mlx5_priv *priv = dev->data->dev_private;
1344         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1345         struct mlx5_rxq_ctrl *rxq_ctrl =
1346                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1347         struct ibv_wq_attr mod;
1348         unsigned int cqe_n;
1349         unsigned int wqe_n = 1 << rxq_data->elts_n;
1350         struct mlx5_rxq_obj *tmpl = NULL;
1351         struct mlx5dv_cq cq_info;
1352         struct mlx5dv_rwq rwq;
1353         int ret = 0;
1354         struct mlx5dv_obj obj;
1355
1356         MLX5_ASSERT(rxq_data);
1357         MLX5_ASSERT(!rxq_ctrl->obj);
1358         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1359                 return mlx5_rxq_obj_hairpin_new(dev, idx);
1360         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1361         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1362         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1363                                  rxq_ctrl->socket);
1364         if (!tmpl) {
1365                 DRV_LOG(ERR,
1366                         "port %u Rx queue %u cannot allocate verbs resources",
1367                         dev->data->port_id, rxq_data->idx);
1368                 rte_errno = ENOMEM;
1369                 goto error;
1370         }
1371         tmpl->type = type;
1372         tmpl->rxq_ctrl = rxq_ctrl;
1373         if (rxq_ctrl->irq) {
1374                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1375                 if (!tmpl->channel) {
1376                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1377                                 dev->data->port_id);
1378                         rte_errno = ENOMEM;
1379                         goto error;
1380                 }
1381         }
1382         if (mlx5_rxq_mprq_enabled(rxq_data))
1383                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1384         else
1385                 cqe_n = wqe_n  - 1;
1386         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1387         if (!tmpl->cq) {
1388                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1389                         dev->data->port_id, idx);
1390                 rte_errno = ENOMEM;
1391                 goto error;
1392         }
1393         obj.cq.in = tmpl->cq;
1394         obj.cq.out = &cq_info;
1395         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1396         if (ret) {
1397                 rte_errno = ret;
1398                 goto error;
1399         }
1400         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1401                 DRV_LOG(ERR,
1402                         "port %u wrong MLX5_CQE_SIZE environment variable"
1403                         " value: it should be set to %u",
1404                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1405                 rte_errno = EINVAL;
1406                 goto error;
1407         }
1408         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1409                 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1410         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1411                 dev->data->port_id, priv->sh->device_attr.max_sge);
1412         /* Allocate door-bell for types created with DevX. */
1413         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1414                 struct mlx5_devx_dbr_page *dbr_page;
1415                 int64_t dbr_offset;
1416
1417                 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1418                 if (dbr_offset < 0)
1419                         goto error;
1420                 rxq_ctrl->dbr_offset = dbr_offset;
1421                 rxq_ctrl->dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1422                 rxq_ctrl->dbr_umem_id_valid = 1;
1423                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1424                                                (uintptr_t)rxq_ctrl->dbr_offset);
1425         }
1426         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1427                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1428                                            tmpl);
1429                 if (!tmpl->wq) {
1430                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1431                                 dev->data->port_id, idx);
1432                         rte_errno = ENOMEM;
1433                         goto error;
1434                 }
1435                 /* Change queue state to ready. */
1436                 mod = (struct ibv_wq_attr){
1437                         .attr_mask = IBV_WQ_ATTR_STATE,
1438                         .wq_state = IBV_WQS_RDY,
1439                 };
1440                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1441                 if (ret) {
1442                         DRV_LOG(ERR,
1443                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1444                                 " failed", dev->data->port_id, idx);
1445                         rte_errno = ret;
1446                         goto error;
1447                 }
1448                 obj.rwq.in = tmpl->wq;
1449                 obj.rwq.out = &rwq;
1450                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1451                 if (ret) {
1452                         rte_errno = ret;
1453                         goto error;
1454                 }
1455                 rxq_data->wqes = rwq.buf;
1456                 rxq_data->rq_db = rwq.dbrec;
1457         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1458                 struct mlx5_devx_modify_rq_attr rq_attr;
1459
1460                 memset(&rq_attr, 0, sizeof(rq_attr));
1461                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1462                 if (!tmpl->rq) {
1463                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1464                                 dev->data->port_id, idx);
1465                         rte_errno = ENOMEM;
1466                         goto error;
1467                 }
1468                 /* Change queue state to ready. */
1469                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1470                 rq_attr.state = MLX5_RQC_STATE_RDY;
1471                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1472                 if (ret)
1473                         goto error;
1474         }
1475         /* Fill the rings. */
1476         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1477         rxq_data->cq_db = cq_info.dbrec;
1478         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1479         rxq_data->cq_uar = cq_info.cq_uar;
1480         rxq_data->cqn = cq_info.cqn;
1481         rxq_data->cq_arm_sn = 0;
1482         mlx5_rxq_initialize(rxq_data);
1483         rxq_data->cq_ci = 0;
1484         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1485                 idx, (void *)&tmpl);
1486         rte_atomic32_inc(&tmpl->refcnt);
1487         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1488         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1489         return tmpl;
1490 error:
1491         if (tmpl) {
1492                 ret = rte_errno; /* Save rte_errno before cleanup. */
1493                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1494                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1495                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1496                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1497                 if (tmpl->cq)
1498                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1499                 if (tmpl->channel)
1500                         claim_zero(mlx5_glue->destroy_comp_channel
1501                                                         (tmpl->channel));
1502                 rte_free(tmpl);
1503                 rte_errno = ret; /* Restore rte_errno. */
1504         }
1505         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1506                 rxq_release_rq_resources(rxq_ctrl);
1507         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1508         return NULL;
1509 }
1510
1511 /**
1512  * Verify the Rx queue objects list is empty
1513  *
1514  * @param dev
1515  *   Pointer to Ethernet device.
1516  *
1517  * @return
1518  *   The number of objects not released.
1519  */
1520 int
1521 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1522 {
1523         struct mlx5_priv *priv = dev->data->dev_private;
1524         int ret = 0;
1525         struct mlx5_rxq_obj *rxq_obj;
1526
1527         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1528                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1529                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1530                 ++ret;
1531         }
1532         return ret;
1533 }
1534
1535 /**
1536  * Callback function to initialize mbufs for Multi-Packet RQ.
1537  */
1538 static inline void
1539 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1540                     void *_m, unsigned int i __rte_unused)
1541 {
1542         struct mlx5_mprq_buf *buf = _m;
1543         struct rte_mbuf_ext_shared_info *shinfo;
1544         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1545         unsigned int j;
1546
1547         memset(_m, 0, sizeof(*buf));
1548         buf->mp = mp;
1549         rte_atomic16_set(&buf->refcnt, 1);
1550         for (j = 0; j != strd_n; ++j) {
1551                 shinfo = &buf->shinfos[j];
1552                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1553                 shinfo->fcb_opaque = buf;
1554         }
1555 }
1556
1557 /**
1558  * Free mempool of Multi-Packet RQ.
1559  *
1560  * @param dev
1561  *   Pointer to Ethernet device.
1562  *
1563  * @return
1564  *   0 on success, negative errno value on failure.
1565  */
1566 int
1567 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1568 {
1569         struct mlx5_priv *priv = dev->data->dev_private;
1570         struct rte_mempool *mp = priv->mprq_mp;
1571         unsigned int i;
1572
1573         if (mp == NULL)
1574                 return 0;
1575         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1576                 dev->data->port_id, mp->name);
1577         /*
1578          * If a buffer in the pool has been externally attached to a mbuf and it
1579          * is still in use by application, destroying the Rx queue can spoil
1580          * the packet. It is unlikely to happen but if application dynamically
1581          * creates and destroys with holding Rx packets, this can happen.
1582          *
1583          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1584          * RQ isn't provided by application but managed by PMD.
1585          */
1586         if (!rte_mempool_full(mp)) {
1587                 DRV_LOG(ERR,
1588                         "port %u mempool for Multi-Packet RQ is still in use",
1589                         dev->data->port_id);
1590                 rte_errno = EBUSY;
1591                 return -rte_errno;
1592         }
1593         rte_mempool_free(mp);
1594         /* Unset mempool for each Rx queue. */
1595         for (i = 0; i != priv->rxqs_n; ++i) {
1596                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1597
1598                 if (rxq == NULL)
1599                         continue;
1600                 rxq->mprq_mp = NULL;
1601         }
1602         priv->mprq_mp = NULL;
1603         return 0;
1604 }
1605
1606 /**
1607  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1608  * mempool. If already allocated, reuse it if there're enough elements.
1609  * Otherwise, resize it.
1610  *
1611  * @param dev
1612  *   Pointer to Ethernet device.
1613  *
1614  * @return
1615  *   0 on success, negative errno value on failure.
1616  */
1617 int
1618 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1619 {
1620         struct mlx5_priv *priv = dev->data->dev_private;
1621         struct rte_mempool *mp = priv->mprq_mp;
1622         char name[RTE_MEMPOOL_NAMESIZE];
1623         unsigned int desc = 0;
1624         unsigned int buf_len;
1625         unsigned int obj_num;
1626         unsigned int obj_size;
1627         unsigned int strd_num_n = 0;
1628         unsigned int strd_sz_n = 0;
1629         unsigned int i;
1630         unsigned int n_ibv = 0;
1631
1632         if (!mlx5_mprq_enabled(dev))
1633                 return 0;
1634         /* Count the total number of descriptors configured. */
1635         for (i = 0; i != priv->rxqs_n; ++i) {
1636                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1637                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1638                         (rxq, struct mlx5_rxq_ctrl, rxq);
1639
1640                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1641                         continue;
1642                 n_ibv++;
1643                 desc += 1 << rxq->elts_n;
1644                 /* Get the max number of strides. */
1645                 if (strd_num_n < rxq->strd_num_n)
1646                         strd_num_n = rxq->strd_num_n;
1647                 /* Get the max size of a stride. */
1648                 if (strd_sz_n < rxq->strd_sz_n)
1649                         strd_sz_n = rxq->strd_sz_n;
1650         }
1651         MLX5_ASSERT(strd_num_n && strd_sz_n);
1652         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1653         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1654                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1655         /*
1656          * Received packets can be either memcpy'd or externally referenced. In
1657          * case that the packet is attached to an mbuf as an external buffer, as
1658          * it isn't possible to predict how the buffers will be queued by
1659          * application, there's no option to exactly pre-allocate needed buffers
1660          * in advance but to speculatively prepares enough buffers.
1661          *
1662          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1663          * received packets to buffers provided by application (rxq->mp) until
1664          * this Mempool gets available again.
1665          */
1666         desc *= 4;
1667         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1668         /*
1669          * rte_mempool_create_empty() has sanity check to refuse large cache
1670          * size compared to the number of elements.
1671          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1672          * constant number 2 instead.
1673          */
1674         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1675         /* Check a mempool is already allocated and if it can be resued. */
1676         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1677                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1678                         dev->data->port_id, mp->name);
1679                 /* Reuse. */
1680                 goto exit;
1681         } else if (mp != NULL) {
1682                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1683                         dev->data->port_id, mp->name);
1684                 /*
1685                  * If failed to free, which means it may be still in use, no way
1686                  * but to keep using the existing one. On buffer underrun,
1687                  * packets will be memcpy'd instead of external buffer
1688                  * attachment.
1689                  */
1690                 if (mlx5_mprq_free_mp(dev)) {
1691                         if (mp->elt_size >= obj_size)
1692                                 goto exit;
1693                         else
1694                                 return -rte_errno;
1695                 }
1696         }
1697         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1698         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1699                                 0, NULL, NULL, mlx5_mprq_buf_init,
1700                                 (void *)(uintptr_t)(1 << strd_num_n),
1701                                 dev->device->numa_node, 0);
1702         if (mp == NULL) {
1703                 DRV_LOG(ERR,
1704                         "port %u failed to allocate a mempool for"
1705                         " Multi-Packet RQ, count=%u, size=%u",
1706                         dev->data->port_id, obj_num, obj_size);
1707                 rte_errno = ENOMEM;
1708                 return -rte_errno;
1709         }
1710         priv->mprq_mp = mp;
1711 exit:
1712         /* Set mempool for each Rx queue. */
1713         for (i = 0; i != priv->rxqs_n; ++i) {
1714                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1715                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1716                         (rxq, struct mlx5_rxq_ctrl, rxq);
1717
1718                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1719                         continue;
1720                 rxq->mprq_mp = mp;
1721         }
1722         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1723                 dev->data->port_id);
1724         return 0;
1725 }
1726
1727 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1728                                         sizeof(struct rte_vlan_hdr) * 2 + \
1729                                         sizeof(struct rte_ipv6_hdr)))
1730 #define MAX_TCP_OPTION_SIZE 40u
1731 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1732                                  sizeof(struct rte_tcp_hdr) + \
1733                                  MAX_TCP_OPTION_SIZE))
1734
1735 /**
1736  * Adjust the maximum LRO massage size.
1737  *
1738  * @param dev
1739  *   Pointer to Ethernet device.
1740  * @param idx
1741  *   RX queue index.
1742  * @param max_lro_size
1743  *   The maximum size for LRO packet.
1744  */
1745 static void
1746 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1747                              uint32_t max_lro_size)
1748 {
1749         struct mlx5_priv *priv = dev->data->dev_private;
1750
1751         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1752             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1753             MLX5_MAX_TCP_HDR_OFFSET)
1754                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1755         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1756         MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1757         max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1758         if (priv->max_lro_msg_size)
1759                 priv->max_lro_msg_size =
1760                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1761         else
1762                 priv->max_lro_msg_size = max_lro_size;
1763         DRV_LOG(DEBUG,
1764                 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1765                 dev->data->port_id, idx,
1766                 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1767 }
1768
1769 /**
1770  * Create a DPDK Rx queue.
1771  *
1772  * @param dev
1773  *   Pointer to Ethernet device.
1774  * @param idx
1775  *   RX queue index.
1776  * @param desc
1777  *   Number of descriptors to configure in queue.
1778  * @param socket
1779  *   NUMA socket on which memory must be allocated.
1780  *
1781  * @return
1782  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1783  */
1784 struct mlx5_rxq_ctrl *
1785 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1786              unsigned int socket, const struct rte_eth_rxconf *conf,
1787              struct rte_mempool *mp)
1788 {
1789         struct mlx5_priv *priv = dev->data->dev_private;
1790         struct mlx5_rxq_ctrl *tmpl;
1791         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1792         unsigned int mprq_stride_nums;
1793         unsigned int mprq_stride_size;
1794         unsigned int mprq_stride_cap;
1795         struct mlx5_dev_config *config = &priv->config;
1796         /*
1797          * Always allocate extra slots, even if eventually
1798          * the vector Rx will not be used.
1799          */
1800         uint16_t desc_n =
1801                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1802         uint64_t offloads = conf->offloads |
1803                            dev->data->dev_conf.rxmode.offloads;
1804         unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1805         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1806         unsigned int max_rx_pkt_len = lro_on_queue ?
1807                         dev->data->dev_conf.rxmode.max_lro_pkt_size :
1808                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1809         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1810                                                         RTE_PKTMBUF_HEADROOM;
1811         unsigned int max_lro_size = 0;
1812         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1813
1814         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1815                                                     DEV_RX_OFFLOAD_SCATTER)) {
1816                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1817                         " configured and no enough mbuf space(%u) to contain "
1818                         "the maximum RX packet length(%u) with head-room(%u)",
1819                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1820                         RTE_PKTMBUF_HEADROOM);
1821                 rte_errno = ENOSPC;
1822                 return NULL;
1823         }
1824         tmpl = rte_calloc_socket("RXQ", 1,
1825                                  sizeof(*tmpl) +
1826                                  desc_n * sizeof(struct rte_mbuf *),
1827                                  0, socket);
1828         if (!tmpl) {
1829                 rte_errno = ENOMEM;
1830                 return NULL;
1831         }
1832         tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1833         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1834                                MLX5_MR_BTREE_CACHE_N, socket)) {
1835                 /* rte_errno is already set. */
1836                 goto error;
1837         }
1838         tmpl->socket = socket;
1839         if (dev->data->dev_conf.intr_conf.rxq)
1840                 tmpl->irq = 1;
1841         mprq_stride_nums = config->mprq.stride_num_n ?
1842                 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1843         mprq_stride_size = non_scatter_min_mbuf_size <=
1844                 (1U << config->mprq.max_stride_size_n) ?
1845                 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1846         mprq_stride_cap = (config->mprq.stride_num_n ?
1847                 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1848                         (config->mprq.stride_size_n ?
1849                 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1850         /*
1851          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1852          * following conditions are met:
1853          *  - MPRQ is enabled.
1854          *  - The number of descs is more than the number of strides.
1855          *  - max_rx_pkt_len plus overhead is less than the max size
1856          *    of a stride or mprq_stride_size is specified by a user.
1857          *    Need to nake sure that there are enough stides to encap
1858          *    the maximum packet size in case mprq_stride_size is set.
1859          *  Otherwise, enable Rx scatter if necessary.
1860          */
1861         if (mprq_en && desc > (1U << mprq_stride_nums) &&
1862             (non_scatter_min_mbuf_size <=
1863              (1U << config->mprq.max_stride_size_n) ||
1864              (config->mprq.stride_size_n &&
1865               non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1866                 /* TODO: Rx scatter isn't supported yet. */
1867                 tmpl->rxq.sges_n = 0;
1868                 /* Trim the number of descs needed. */
1869                 desc >>= mprq_stride_nums;
1870                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1871                         config->mprq.stride_num_n : mprq_stride_nums;
1872                 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1873                         config->mprq.stride_size_n : mprq_stride_size;
1874                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1875                 tmpl->rxq.strd_scatter_en =
1876                                 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1877                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1878                                 config->mprq.max_memcpy_len);
1879                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1880                                        (1u << tmpl->rxq.strd_num_n) *
1881                                        (1u << tmpl->rxq.strd_sz_n));
1882                 DRV_LOG(DEBUG,
1883                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1884                         " strd_num_n = %u, strd_sz_n = %u",
1885                         dev->data->port_id, idx,
1886                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1887         } else if (max_rx_pkt_len <= first_mb_free_size) {
1888                 tmpl->rxq.sges_n = 0;
1889                 max_lro_size = max_rx_pkt_len;
1890         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1891                 unsigned int size = non_scatter_min_mbuf_size;
1892                 unsigned int sges_n;
1893
1894                 if (lro_on_queue && first_mb_free_size <
1895                     MLX5_MAX_LRO_HEADER_FIX) {
1896                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1897                                 " to include the max header size(%u) for LRO",
1898                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1899                         rte_errno = ENOTSUP;
1900                         goto error;
1901                 }
1902                 /*
1903                  * Determine the number of SGEs needed for a full packet
1904                  * and round it to the next power of two.
1905                  */
1906                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1907                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1908                         DRV_LOG(ERR,
1909                                 "port %u too many SGEs (%u) needed to handle"
1910                                 " requested maximum packet size %u, the maximum"
1911                                 " supported are %u", dev->data->port_id,
1912                                 1 << sges_n, max_rx_pkt_len,
1913                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1914                         rte_errno = ENOTSUP;
1915                         goto error;
1916                 }
1917                 tmpl->rxq.sges_n = sges_n;
1918                 max_lro_size = max_rx_pkt_len;
1919         }
1920         if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1921                 DRV_LOG(WARNING,
1922                         "port %u MPRQ is requested but cannot be enabled\n"
1923                         " (requested: pkt_sz = %u, desc_num = %u,"
1924                         " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1925                         "  supported: min_rxqs_num = %u,"
1926                         " min_stride_sz = %u, max_stride_sz = %u).",
1927                         dev->data->port_id, non_scatter_min_mbuf_size,
1928                         desc, priv->rxqs_n,
1929                         config->mprq.stride_size_n ?
1930                                 (1U << config->mprq.stride_size_n) :
1931                                 (1U << mprq_stride_size),
1932                         config->mprq.stride_num_n ?
1933                                 (1U << config->mprq.stride_num_n) :
1934                                 (1U << mprq_stride_nums),
1935                         config->mprq.min_rxqs_num,
1936                         (1U << config->mprq.min_stride_size_n),
1937                         (1U << config->mprq.max_stride_size_n));
1938         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1939                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1940         if (desc % (1 << tmpl->rxq.sges_n)) {
1941                 DRV_LOG(ERR,
1942                         "port %u number of Rx queue descriptors (%u) is not a"
1943                         " multiple of SGEs per packet (%u)",
1944                         dev->data->port_id,
1945                         desc,
1946                         1 << tmpl->rxq.sges_n);
1947                 rte_errno = EINVAL;
1948                 goto error;
1949         }
1950         mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1951         /* Toggle RX checksum offload if hardware supports it. */
1952         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1953         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1954         /* Configure VLAN stripping. */
1955         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1956         /* By default, FCS (CRC) is stripped by hardware. */
1957         tmpl->rxq.crc_present = 0;
1958         tmpl->rxq.lro = lro_on_queue;
1959         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1960                 if (config->hw_fcs_strip) {
1961                         /*
1962                          * RQs used for LRO-enabled TIRs should not be
1963                          * configured to scatter the FCS.
1964                          */
1965                         if (lro_on_queue)
1966                                 DRV_LOG(WARNING,
1967                                         "port %u CRC stripping has been "
1968                                         "disabled but will still be performed "
1969                                         "by hardware, because LRO is enabled",
1970                                         dev->data->port_id);
1971                         else
1972                                 tmpl->rxq.crc_present = 1;
1973                 } else {
1974                         DRV_LOG(WARNING,
1975                                 "port %u CRC stripping has been disabled but will"
1976                                 " still be performed by hardware, make sure MLNX_OFED"
1977                                 " and firmware are up to date",
1978                                 dev->data->port_id);
1979                 }
1980         }
1981         DRV_LOG(DEBUG,
1982                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1983                 " incoming frames to hide it",
1984                 dev->data->port_id,
1985                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1986                 tmpl->rxq.crc_present << 2);
1987         /* Save port ID. */
1988         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1989                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1990         tmpl->rxq.port_id = dev->data->port_id;
1991         tmpl->priv = priv;
1992         tmpl->rxq.mp = mp;
1993         tmpl->rxq.elts_n = log2above(desc);
1994         tmpl->rxq.rq_repl_thresh =
1995                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1996         tmpl->rxq.elts =
1997                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1998 #ifndef RTE_ARCH_64
1999         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
2000 #endif
2001         tmpl->rxq.idx = idx;
2002         rte_atomic32_inc(&tmpl->refcnt);
2003         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2004         return tmpl;
2005 error:
2006         rte_free(tmpl);
2007         return NULL;
2008 }
2009
2010 /**
2011  * Create a DPDK Rx hairpin queue.
2012  *
2013  * @param dev
2014  *   Pointer to Ethernet device.
2015  * @param idx
2016  *   RX queue index.
2017  * @param desc
2018  *   Number of descriptors to configure in queue.
2019  * @param hairpin_conf
2020  *   The hairpin binding configuration.
2021  *
2022  * @return
2023  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
2024  */
2025 struct mlx5_rxq_ctrl *
2026 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2027                      const struct rte_eth_hairpin_conf *hairpin_conf)
2028 {
2029         struct mlx5_priv *priv = dev->data->dev_private;
2030         struct mlx5_rxq_ctrl *tmpl;
2031
2032         tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2033         if (!tmpl) {
2034                 rte_errno = ENOMEM;
2035                 return NULL;
2036         }
2037         tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2038         tmpl->socket = SOCKET_ID_ANY;
2039         tmpl->rxq.rss_hash = 0;
2040         tmpl->rxq.port_id = dev->data->port_id;
2041         tmpl->priv = priv;
2042         tmpl->rxq.mp = NULL;
2043         tmpl->rxq.elts_n = log2above(desc);
2044         tmpl->rxq.elts = NULL;
2045         tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2046         tmpl->hairpin_conf = *hairpin_conf;
2047         tmpl->rxq.idx = idx;
2048         rte_atomic32_inc(&tmpl->refcnt);
2049         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2050         return tmpl;
2051 }
2052
2053 /**
2054  * Get a Rx queue.
2055  *
2056  * @param dev
2057  *   Pointer to Ethernet device.
2058  * @param idx
2059  *   RX queue index.
2060  *
2061  * @return
2062  *   A pointer to the queue if it exists, NULL otherwise.
2063  */
2064 struct mlx5_rxq_ctrl *
2065 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2066 {
2067         struct mlx5_priv *priv = dev->data->dev_private;
2068         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2069
2070         if ((*priv->rxqs)[idx]) {
2071                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2072                                         struct mlx5_rxq_ctrl,
2073                                         rxq);
2074                 mlx5_rxq_obj_get(dev, idx);
2075                 rte_atomic32_inc(&rxq_ctrl->refcnt);
2076         }
2077         return rxq_ctrl;
2078 }
2079
2080 /**
2081  * Release a Rx queue.
2082  *
2083  * @param dev
2084  *   Pointer to Ethernet device.
2085  * @param idx
2086  *   RX queue index.
2087  *
2088  * @return
2089  *   1 while a reference on it exists, 0 when freed.
2090  */
2091 int
2092 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2093 {
2094         struct mlx5_priv *priv = dev->data->dev_private;
2095         struct mlx5_rxq_ctrl *rxq_ctrl;
2096
2097         if (!(*priv->rxqs)[idx])
2098                 return 0;
2099         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2100         MLX5_ASSERT(rxq_ctrl->priv);
2101         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2102                 rxq_ctrl->obj = NULL;
2103         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2104                 if (rxq_ctrl->dbr_umem_id_valid)
2105                         claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
2106                                                     rxq_ctrl->dbr_offset));
2107                 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2108                         mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2109                 LIST_REMOVE(rxq_ctrl, next);
2110                 rte_free(rxq_ctrl);
2111                 (*priv->rxqs)[idx] = NULL;
2112                 return 0;
2113         }
2114         return 1;
2115 }
2116
2117 /**
2118  * Verify the Rx Queue list is empty
2119  *
2120  * @param dev
2121  *   Pointer to Ethernet device.
2122  *
2123  * @return
2124  *   The number of object not released.
2125  */
2126 int
2127 mlx5_rxq_verify(struct rte_eth_dev *dev)
2128 {
2129         struct mlx5_priv *priv = dev->data->dev_private;
2130         struct mlx5_rxq_ctrl *rxq_ctrl;
2131         int ret = 0;
2132
2133         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2134                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2135                         dev->data->port_id, rxq_ctrl->rxq.idx);
2136                 ++ret;
2137         }
2138         return ret;
2139 }
2140
2141 /**
2142  * Get a Rx queue type.
2143  *
2144  * @param dev
2145  *   Pointer to Ethernet device.
2146  * @param idx
2147  *   Rx queue index.
2148  *
2149  * @return
2150  *   The Rx queue type.
2151  */
2152 enum mlx5_rxq_type
2153 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2154 {
2155         struct mlx5_priv *priv = dev->data->dev_private;
2156         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2157
2158         if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2159                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2160                                         struct mlx5_rxq_ctrl,
2161                                         rxq);
2162                 return rxq_ctrl->type;
2163         }
2164         return MLX5_RXQ_TYPE_UNDEFINED;
2165 }
2166
2167 /**
2168  * Create an indirection table.
2169  *
2170  * @param dev
2171  *   Pointer to Ethernet device.
2172  * @param queues
2173  *   Queues entering in the indirection table.
2174  * @param queues_n
2175  *   Number of queues in the array.
2176  *
2177  * @return
2178  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2179  */
2180 static struct mlx5_ind_table_obj *
2181 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2182                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
2183 {
2184         struct mlx5_priv *priv = dev->data->dev_private;
2185         struct mlx5_ind_table_obj *ind_tbl;
2186         unsigned int i = 0, j = 0, k = 0;
2187
2188         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2189                              queues_n * sizeof(uint16_t), 0);
2190         if (!ind_tbl) {
2191                 rte_errno = ENOMEM;
2192                 return NULL;
2193         }
2194         ind_tbl->type = type;
2195         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2196                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2197                         log2above(queues_n) :
2198                         log2above(priv->config.ind_table_max_size);
2199                 struct ibv_wq *wq[1 << wq_n];
2200
2201                 for (i = 0; i != queues_n; ++i) {
2202                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2203                                                                  queues[i]);
2204                         if (!rxq)
2205                                 goto error;
2206                         wq[i] = rxq->obj->wq;
2207                         ind_tbl->queues[i] = queues[i];
2208                 }
2209                 ind_tbl->queues_n = queues_n;
2210                 /* Finalise indirection table. */
2211                 k = i; /* Retain value of i for use in error case. */
2212                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2213                         wq[k] = wq[j];
2214                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2215                         (priv->sh->ctx,
2216                          &(struct ibv_rwq_ind_table_init_attr){
2217                                 .log_ind_tbl_size = wq_n,
2218                                 .ind_tbl = wq,
2219                                 .comp_mask = 0,
2220                         });
2221                 if (!ind_tbl->ind_table) {
2222                         rte_errno = errno;
2223                         goto error;
2224                 }
2225         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2226                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2227                 const unsigned int rqt_n =
2228                         1 << (rte_is_power_of_2(queues_n) ?
2229                               log2above(queues_n) :
2230                               log2above(priv->config.ind_table_max_size));
2231
2232                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2233                                       rqt_n * sizeof(uint32_t), 0);
2234                 if (!rqt_attr) {
2235                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2236                                 dev->data->port_id);
2237                         rte_errno = ENOMEM;
2238                         goto error;
2239                 }
2240                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2241                 rqt_attr->rqt_actual_size = rqt_n;
2242                 for (i = 0; i != queues_n; ++i) {
2243                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2244                                                                  queues[i]);
2245                         if (!rxq)
2246                                 goto error;
2247                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
2248                         ind_tbl->queues[i] = queues[i];
2249                 }
2250                 k = i; /* Retain value of i for use in error case. */
2251                 for (j = 0; k != rqt_n; ++k, ++j)
2252                         rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2253                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2254                                                         rqt_attr);
2255                 rte_free(rqt_attr);
2256                 if (!ind_tbl->rqt) {
2257                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
2258                                 dev->data->port_id);
2259                         rte_errno = errno;
2260                         goto error;
2261                 }
2262                 ind_tbl->queues_n = queues_n;
2263         }
2264         rte_atomic32_inc(&ind_tbl->refcnt);
2265         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2266         return ind_tbl;
2267 error:
2268         for (j = 0; j < i; j++)
2269                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2270         rte_free(ind_tbl);
2271         DEBUG("port %u cannot create indirection table", dev->data->port_id);
2272         return NULL;
2273 }
2274
2275 /**
2276  * Get an indirection table.
2277  *
2278  * @param dev
2279  *   Pointer to Ethernet device.
2280  * @param queues
2281  *   Queues entering in the indirection table.
2282  * @param queues_n
2283  *   Number of queues in the array.
2284  *
2285  * @return
2286  *   An indirection table if found.
2287  */
2288 static struct mlx5_ind_table_obj *
2289 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2290                        uint32_t queues_n)
2291 {
2292         struct mlx5_priv *priv = dev->data->dev_private;
2293         struct mlx5_ind_table_obj *ind_tbl;
2294
2295         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2296                 if ((ind_tbl->queues_n == queues_n) &&
2297                     (memcmp(ind_tbl->queues, queues,
2298                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2299                      == 0))
2300                         break;
2301         }
2302         if (ind_tbl) {
2303                 unsigned int i;
2304
2305                 rte_atomic32_inc(&ind_tbl->refcnt);
2306                 for (i = 0; i != ind_tbl->queues_n; ++i)
2307                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
2308         }
2309         return ind_tbl;
2310 }
2311
2312 /**
2313  * Release an indirection table.
2314  *
2315  * @param dev
2316  *   Pointer to Ethernet device.
2317  * @param ind_table
2318  *   Indirection table to release.
2319  *
2320  * @return
2321  *   1 while a reference on it exists, 0 when freed.
2322  */
2323 static int
2324 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2325                            struct mlx5_ind_table_obj *ind_tbl)
2326 {
2327         unsigned int i;
2328
2329         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2330                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2331                         claim_zero(mlx5_glue->destroy_rwq_ind_table
2332                                                         (ind_tbl->ind_table));
2333                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2334                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2335         }
2336         for (i = 0; i != ind_tbl->queues_n; ++i)
2337                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2338         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2339                 LIST_REMOVE(ind_tbl, next);
2340                 rte_free(ind_tbl);
2341                 return 0;
2342         }
2343         return 1;
2344 }
2345
2346 /**
2347  * Verify the Rx Queue list is empty
2348  *
2349  * @param dev
2350  *   Pointer to Ethernet device.
2351  *
2352  * @return
2353  *   The number of object not released.
2354  */
2355 int
2356 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2357 {
2358         struct mlx5_priv *priv = dev->data->dev_private;
2359         struct mlx5_ind_table_obj *ind_tbl;
2360         int ret = 0;
2361
2362         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2363                 DRV_LOG(DEBUG,
2364                         "port %u indirection table obj %p still referenced",
2365                         dev->data->port_id, (void *)ind_tbl);
2366                 ++ret;
2367         }
2368         return ret;
2369 }
2370
2371 /**
2372  * Create an Rx Hash queue.
2373  *
2374  * @param dev
2375  *   Pointer to Ethernet device.
2376  * @param rss_key
2377  *   RSS key for the Rx hash queue.
2378  * @param rss_key_len
2379  *   RSS key length.
2380  * @param hash_fields
2381  *   Verbs protocol hash field to make the RSS on.
2382  * @param queues
2383  *   Queues entering in hash queue. In case of empty hash_fields only the
2384  *   first queue index will be taken for the indirection table.
2385  * @param queues_n
2386  *   Number of queues.
2387  * @param tunnel
2388  *   Tunnel type.
2389  *
2390  * @return
2391  *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2392  */
2393 uint32_t
2394 mlx5_hrxq_new(struct rte_eth_dev *dev,
2395               const uint8_t *rss_key, uint32_t rss_key_len,
2396               uint64_t hash_fields,
2397               const uint16_t *queues, uint32_t queues_n,
2398               int tunnel __rte_unused)
2399 {
2400         struct mlx5_priv *priv = dev->data->dev_private;
2401         struct mlx5_hrxq *hrxq;
2402         uint32_t hrxq_idx = 0;
2403         struct ibv_qp *qp = NULL;
2404         struct mlx5_ind_table_obj *ind_tbl;
2405         int err;
2406         struct mlx5_devx_obj *tir = NULL;
2407         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2408         struct mlx5_rxq_ctrl *rxq_ctrl =
2409                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2410
2411         queues_n = hash_fields ? queues_n : 1;
2412         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2413         if (!ind_tbl) {
2414                 enum mlx5_ind_tbl_type type;
2415
2416                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2417                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2418                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2419         }
2420         if (!ind_tbl) {
2421                 rte_errno = ENOMEM;
2422                 return 0;
2423         }
2424         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2425 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2426                 struct mlx5dv_qp_init_attr qp_init_attr;
2427
2428                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2429                 if (tunnel) {
2430                         qp_init_attr.comp_mask =
2431                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2432                         qp_init_attr.create_flags =
2433                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2434                 }
2435 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2436                 if (dev->data->dev_conf.lpbk_mode) {
2437                         /*
2438                          * Allow packet sent from NIC loop back
2439                          * w/o source MAC check.
2440                          */
2441                         qp_init_attr.comp_mask |=
2442                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2443                         qp_init_attr.create_flags |=
2444                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2445                 }
2446 #endif
2447                 qp = mlx5_glue->dv_create_qp
2448                         (priv->sh->ctx,
2449                          &(struct ibv_qp_init_attr_ex){
2450                                 .qp_type = IBV_QPT_RAW_PACKET,
2451                                 .comp_mask =
2452                                         IBV_QP_INIT_ATTR_PD |
2453                                         IBV_QP_INIT_ATTR_IND_TABLE |
2454                                         IBV_QP_INIT_ATTR_RX_HASH,
2455                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2456                                         .rx_hash_function =
2457                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2458                                         .rx_hash_key_len = rss_key_len,
2459                                         .rx_hash_key =
2460                                                 (void *)(uintptr_t)rss_key,
2461                                         .rx_hash_fields_mask = hash_fields,
2462                                 },
2463                                 .rwq_ind_tbl = ind_tbl->ind_table,
2464                                 .pd = priv->sh->pd,
2465                           },
2466                           &qp_init_attr);
2467 #else
2468                 qp = mlx5_glue->create_qp_ex
2469                         (priv->sh->ctx,
2470                          &(struct ibv_qp_init_attr_ex){
2471                                 .qp_type = IBV_QPT_RAW_PACKET,
2472                                 .comp_mask =
2473                                         IBV_QP_INIT_ATTR_PD |
2474                                         IBV_QP_INIT_ATTR_IND_TABLE |
2475                                         IBV_QP_INIT_ATTR_RX_HASH,
2476                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2477                                         .rx_hash_function =
2478                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2479                                         .rx_hash_key_len = rss_key_len,
2480                                         .rx_hash_key =
2481                                                 (void *)(uintptr_t)rss_key,
2482                                         .rx_hash_fields_mask = hash_fields,
2483                                 },
2484                                 .rwq_ind_tbl = ind_tbl->ind_table,
2485                                 .pd = priv->sh->pd,
2486                          });
2487 #endif
2488                 if (!qp) {
2489                         rte_errno = errno;
2490                         goto error;
2491                 }
2492         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2493                 struct mlx5_devx_tir_attr tir_attr;
2494                 uint32_t i;
2495                 uint32_t lro = 1;
2496
2497                 /* Enable TIR LRO only if all the queues were configured for. */
2498                 for (i = 0; i < queues_n; ++i) {
2499                         if (!(*priv->rxqs)[queues[i]]->lro) {
2500                                 lro = 0;
2501                                 break;
2502                         }
2503                 }
2504                 memset(&tir_attr, 0, sizeof(tir_attr));
2505                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2506                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2507                 tir_attr.tunneled_offload_en = !!tunnel;
2508                 /* If needed, translate hash_fields bitmap to PRM format. */
2509                 if (hash_fields) {
2510 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2511                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2512                                         hash_fields & IBV_RX_HASH_INNER ?
2513                                         &tir_attr.rx_hash_field_selector_inner :
2514                                         &tir_attr.rx_hash_field_selector_outer;
2515 #else
2516                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2517                                         &tir_attr.rx_hash_field_selector_outer;
2518 #endif
2519
2520                         /* 1 bit: 0: IPv4, 1: IPv6. */
2521                         rx_hash_field_select->l3_prot_type =
2522                                 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2523                         /* 1 bit: 0: TCP, 1: UDP. */
2524                         rx_hash_field_select->l4_prot_type =
2525                                 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2526                         /* Bitmask which sets which fields to use in RX Hash. */
2527                         rx_hash_field_select->selected_fields =
2528                         ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2529                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2530                         (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2531                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2532                         (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2533                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2534                         (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2535                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2536                 }
2537                 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2538                         tir_attr.transport_domain = priv->sh->td->id;
2539                 else
2540                         tir_attr.transport_domain = priv->sh->tdn;
2541                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2542                        MLX5_RSS_HASH_KEY_LEN);
2543                 tir_attr.indirect_table = ind_tbl->rqt->id;
2544                 if (dev->data->dev_conf.lpbk_mode)
2545                         tir_attr.self_lb_block =
2546                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2547                 if (lro) {
2548                         tir_attr.lro_timeout_period_usecs =
2549                                         priv->config.lro.timeout;
2550                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2551                         tir_attr.lro_enable_mask =
2552                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2553                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2554                 }
2555                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2556                 if (!tir) {
2557                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2558                                 dev->data->port_id);
2559                         rte_errno = errno;
2560                         goto error;
2561                 }
2562         }
2563         hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2564         if (!hrxq)
2565                 goto error;
2566         hrxq->ind_table = ind_tbl;
2567         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2568                 hrxq->qp = qp;
2569 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2570                 hrxq->action =
2571                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2572                 if (!hrxq->action) {
2573                         rte_errno = errno;
2574                         goto error;
2575                 }
2576 #endif
2577         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2578                 hrxq->tir = tir;
2579 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2580                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2581                                                         (hrxq->tir->obj);
2582                 if (!hrxq->action) {
2583                         rte_errno = errno;
2584                         goto error;
2585                 }
2586 #endif
2587         }
2588         hrxq->rss_key_len = rss_key_len;
2589         hrxq->hash_fields = hash_fields;
2590         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2591         rte_atomic32_inc(&hrxq->refcnt);
2592         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2593                      hrxq, next);
2594         return hrxq_idx;
2595 error:
2596         err = rte_errno; /* Save rte_errno before cleanup. */
2597         mlx5_ind_table_obj_release(dev, ind_tbl);
2598         if (qp)
2599                 claim_zero(mlx5_glue->destroy_qp(qp));
2600         else if (tir)
2601                 claim_zero(mlx5_devx_cmd_destroy(tir));
2602         rte_errno = err; /* Restore rte_errno. */
2603         return 0;
2604 }
2605
2606 /**
2607  * Get an Rx Hash queue.
2608  *
2609  * @param dev
2610  *   Pointer to Ethernet device.
2611  * @param rss_conf
2612  *   RSS configuration for the Rx hash queue.
2613  * @param queues
2614  *   Queues entering in hash queue. In case of empty hash_fields only the
2615  *   first queue index will be taken for the indirection table.
2616  * @param queues_n
2617  *   Number of queues.
2618  *
2619  * @return
2620  *   An hash Rx queue index on success.
2621  */
2622 uint32_t
2623 mlx5_hrxq_get(struct rte_eth_dev *dev,
2624               const uint8_t *rss_key, uint32_t rss_key_len,
2625               uint64_t hash_fields,
2626               const uint16_t *queues, uint32_t queues_n)
2627 {
2628         struct mlx5_priv *priv = dev->data->dev_private;
2629         struct mlx5_hrxq *hrxq;
2630         uint32_t idx;
2631
2632         queues_n = hash_fields ? queues_n : 1;
2633         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2634                       hrxq, next) {
2635                 struct mlx5_ind_table_obj *ind_tbl;
2636
2637                 if (hrxq->rss_key_len != rss_key_len)
2638                         continue;
2639                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2640                         continue;
2641                 if (hrxq->hash_fields != hash_fields)
2642                         continue;
2643                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2644                 if (!ind_tbl)
2645                         continue;
2646                 if (ind_tbl != hrxq->ind_table) {
2647                         mlx5_ind_table_obj_release(dev, ind_tbl);
2648                         continue;
2649                 }
2650                 rte_atomic32_inc(&hrxq->refcnt);
2651                 return idx;
2652         }
2653         return 0;
2654 }
2655
2656 /**
2657  * Release the hash Rx queue.
2658  *
2659  * @param dev
2660  *   Pointer to Ethernet device.
2661  * @param hrxq
2662  *   Index to Hash Rx queue to release.
2663  *
2664  * @return
2665  *   1 while a reference on it exists, 0 when freed.
2666  */
2667 int
2668 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2669 {
2670         struct mlx5_priv *priv = dev->data->dev_private;
2671         struct mlx5_hrxq *hrxq;
2672
2673         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2674         if (!hrxq)
2675                 return 0;
2676         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2677 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2678                 mlx5_glue->destroy_flow_action(hrxq->action);
2679 #endif
2680                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2681                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2682                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2683                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2684                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2685                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2686                              hrxq_idx, hrxq, next);
2687                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2688                 return 0;
2689         }
2690         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2691         return 1;
2692 }
2693
2694 /**
2695  * Verify the Rx Queue list is empty
2696  *
2697  * @param dev
2698  *   Pointer to Ethernet device.
2699  *
2700  * @return
2701  *   The number of object not released.
2702  */
2703 int
2704 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2705 {
2706         struct mlx5_priv *priv = dev->data->dev_private;
2707         struct mlx5_hrxq *hrxq;
2708         uint32_t idx;
2709         int ret = 0;
2710
2711         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2712                       hrxq, next) {
2713                 DRV_LOG(DEBUG,
2714                         "port %u hash Rx queue %p still referenced",
2715                         dev->data->port_id, (void *)hrxq);
2716                 ++ret;
2717         }
2718         return ret;
2719 }
2720
2721 /**
2722  * Create a drop Rx queue Verbs/DevX object.
2723  *
2724  * @param dev
2725  *   Pointer to Ethernet device.
2726  *
2727  * @return
2728  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2729  */
2730 static struct mlx5_rxq_obj *
2731 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2732 {
2733         struct mlx5_priv *priv = dev->data->dev_private;
2734         struct ibv_context *ctx = priv->sh->ctx;
2735         struct ibv_cq *cq;
2736         struct ibv_wq *wq = NULL;
2737         struct mlx5_rxq_obj *rxq;
2738
2739         if (priv->drop_queue.rxq)
2740                 return priv->drop_queue.rxq;
2741         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2742         if (!cq) {
2743                 DEBUG("port %u cannot allocate CQ for drop queue",
2744                       dev->data->port_id);
2745                 rte_errno = errno;
2746                 goto error;
2747         }
2748         wq = mlx5_glue->create_wq(ctx,
2749                  &(struct ibv_wq_init_attr){
2750                         .wq_type = IBV_WQT_RQ,
2751                         .max_wr = 1,
2752                         .max_sge = 1,
2753                         .pd = priv->sh->pd,
2754                         .cq = cq,
2755                  });
2756         if (!wq) {
2757                 DEBUG("port %u cannot allocate WQ for drop queue",
2758                       dev->data->port_id);
2759                 rte_errno = errno;
2760                 goto error;
2761         }
2762         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2763         if (!rxq) {
2764                 DEBUG("port %u cannot allocate drop Rx queue memory",
2765                       dev->data->port_id);
2766                 rte_errno = ENOMEM;
2767                 goto error;
2768         }
2769         rxq->cq = cq;
2770         rxq->wq = wq;
2771         priv->drop_queue.rxq = rxq;
2772         return rxq;
2773 error:
2774         if (wq)
2775                 claim_zero(mlx5_glue->destroy_wq(wq));
2776         if (cq)
2777                 claim_zero(mlx5_glue->destroy_cq(cq));
2778         return NULL;
2779 }
2780
2781 /**
2782  * Release a drop Rx queue Verbs/DevX object.
2783  *
2784  * @param dev
2785  *   Pointer to Ethernet device.
2786  *
2787  * @return
2788  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2789  */
2790 static void
2791 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2792 {
2793         struct mlx5_priv *priv = dev->data->dev_private;
2794         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2795
2796         if (rxq->wq)
2797                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2798         if (rxq->cq)
2799                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2800         rte_free(rxq);
2801         priv->drop_queue.rxq = NULL;
2802 }
2803
2804 /**
2805  * Create a drop indirection table.
2806  *
2807  * @param dev
2808  *   Pointer to Ethernet device.
2809  *
2810  * @return
2811  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2812  */
2813 static struct mlx5_ind_table_obj *
2814 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2815 {
2816         struct mlx5_priv *priv = dev->data->dev_private;
2817         struct mlx5_ind_table_obj *ind_tbl;
2818         struct mlx5_rxq_obj *rxq;
2819         struct mlx5_ind_table_obj tmpl;
2820
2821         rxq = mlx5_rxq_obj_drop_new(dev);
2822         if (!rxq)
2823                 return NULL;
2824         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2825                 (priv->sh->ctx,
2826                  &(struct ibv_rwq_ind_table_init_attr){
2827                         .log_ind_tbl_size = 0,
2828                         .ind_tbl = &rxq->wq,
2829                         .comp_mask = 0,
2830                  });
2831         if (!tmpl.ind_table) {
2832                 DEBUG("port %u cannot allocate indirection table for drop"
2833                       " queue",
2834                       dev->data->port_id);
2835                 rte_errno = errno;
2836                 goto error;
2837         }
2838         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2839         if (!ind_tbl) {
2840                 rte_errno = ENOMEM;
2841                 goto error;
2842         }
2843         ind_tbl->ind_table = tmpl.ind_table;
2844         return ind_tbl;
2845 error:
2846         mlx5_rxq_obj_drop_release(dev);
2847         return NULL;
2848 }
2849
2850 /**
2851  * Release a drop indirection table.
2852  *
2853  * @param dev
2854  *   Pointer to Ethernet device.
2855  */
2856 static void
2857 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2858 {
2859         struct mlx5_priv *priv = dev->data->dev_private;
2860         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2861
2862         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2863         mlx5_rxq_obj_drop_release(dev);
2864         rte_free(ind_tbl);
2865         priv->drop_queue.hrxq->ind_table = NULL;
2866 }
2867
2868 /**
2869  * Create a drop Rx Hash queue.
2870  *
2871  * @param dev
2872  *   Pointer to Ethernet device.
2873  *
2874  * @return
2875  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2876  */
2877 struct mlx5_hrxq *
2878 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2879 {
2880         struct mlx5_priv *priv = dev->data->dev_private;
2881         struct mlx5_ind_table_obj *ind_tbl = NULL;
2882         struct ibv_qp *qp = NULL;
2883         struct mlx5_hrxq *hrxq = NULL;
2884
2885         if (priv->drop_queue.hrxq) {
2886                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2887                 return priv->drop_queue.hrxq;
2888         }
2889         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2890         if (!hrxq) {
2891                 DRV_LOG(WARNING,
2892                         "port %u cannot allocate memory for drop queue",
2893                         dev->data->port_id);
2894                 rte_errno = ENOMEM;
2895                 goto error;
2896         }
2897         priv->drop_queue.hrxq = hrxq;
2898         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2899         if (!ind_tbl)
2900                 goto error;
2901         hrxq->ind_table = ind_tbl;
2902         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2903                  &(struct ibv_qp_init_attr_ex){
2904                         .qp_type = IBV_QPT_RAW_PACKET,
2905                         .comp_mask =
2906                                 IBV_QP_INIT_ATTR_PD |
2907                                 IBV_QP_INIT_ATTR_IND_TABLE |
2908                                 IBV_QP_INIT_ATTR_RX_HASH,
2909                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2910                                 .rx_hash_function =
2911                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2912                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2913                                 .rx_hash_key = rss_hash_default_key,
2914                                 .rx_hash_fields_mask = 0,
2915                                 },
2916                         .rwq_ind_tbl = ind_tbl->ind_table,
2917                         .pd = priv->sh->pd
2918                  });
2919         if (!qp) {
2920                 DEBUG("port %u cannot allocate QP for drop queue",
2921                       dev->data->port_id);
2922                 rte_errno = errno;
2923                 goto error;
2924         }
2925         hrxq->qp = qp;
2926 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2927         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2928         if (!hrxq->action) {
2929                 rte_errno = errno;
2930                 goto error;
2931         }
2932 #endif
2933         rte_atomic32_set(&hrxq->refcnt, 1);
2934         return hrxq;
2935 error:
2936 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2937         if (hrxq && hrxq->action)
2938                 mlx5_glue->destroy_flow_action(hrxq->action);
2939 #endif
2940         if (qp)
2941                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2942         if (ind_tbl)
2943                 mlx5_ind_table_obj_drop_release(dev);
2944         if (hrxq) {
2945                 priv->drop_queue.hrxq = NULL;
2946                 rte_free(hrxq);
2947         }
2948         return NULL;
2949 }
2950
2951 /**
2952  * Release a drop hash Rx queue.
2953  *
2954  * @param dev
2955  *   Pointer to Ethernet device.
2956  */
2957 void
2958 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2959 {
2960         struct mlx5_priv *priv = dev->data->dev_private;
2961         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2962
2963         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2964 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2965                 mlx5_glue->destroy_flow_action(hrxq->action);
2966 #endif
2967                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2968                 mlx5_ind_table_obj_drop_release(dev);
2969                 rte_free(hrxq);
2970                 priv->drop_queue.hrxq = NULL;
2971         }
2972 }