drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <string.h>
  10 #include <stdint.h>
  11 #include <fcntl.h>
  12 #include <sys/queue.h>
  13
  14 /* Verbs header. */
  15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic ignored "-Wpedantic"
  18 #endif
  19 #include <infiniband/verbs.h>
  20 #include <infiniband/mlx5dv.h>
  21 #ifdef PEDANTIC
  22 #pragma GCC diagnostic error "-Wpedantic"
  23 #endif
  24
  25 #include <rte_mbuf.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_common.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_debug.h>
  31 #include <rte_io.h>
  32
  33 #include "mlx5.h"
  34 #include "mlx5_rxtx.h"
  35 #include "mlx5_utils.h"
  36 #include "mlx5_autoconf.h"
  37 #include "mlx5_defs.h"
  38 #include "mlx5_glue.h"
  39
  40 /* Default RSS hash key also used for ConnectX-3. */
  41 uint8_t rss_hash_default_key[] = {
  42         0x2c, 0xc6, 0x81, 0xd1,
  43         0x5b, 0xdb, 0xf4, 0xf7,
  44         0xfc, 0xa2, 0x83, 0x19,
  45         0xdb, 0x1a, 0x3e, 0x94,
  46         0x6b, 0x9e, 0x38, 0xd9,
  47         0x2c, 0x9c, 0x03, 0xd1,
  48         0xad, 0x99, 0x44, 0xa7,
  49         0xd9, 0x56, 0x3d, 0x59,
  50         0x06, 0x3c, 0x25, 0xf3,
  51         0xfc, 0x1f, 0xdc, 0x2a,
  52 };
  53
  54 /* Length of the default RSS hash key. */
  55 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  56               (unsigned int)sizeof(rss_hash_default_key),
  57               "wrong RSS default key size.");
  58
  59 /**
  60  * Check whether Multi-Packet RQ can be enabled for the device.
  61  *
  62  * @param dev
  63  *   Pointer to Ethernet device.
  64  *
  65  * @return
  66  *   1 if supported, negative errno value if not.
  67  */
  68 inline int
  69 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  70 {
  71         struct mlx5_priv *priv = dev->data->dev_private;
  72
  73         if (priv->config.mprq.enabled &&
  74             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  75                 return 1;
  76         return -ENOTSUP;
  77 }
  78
  79 /**
  80  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  81  *
  82  *  @param rxq
  83  *     Pointer to receive queue structure.
  84  *
  85  * @return
  86  *   0 if disabled, otherwise enabled.
  87  */
  88 inline int
  89 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  90 {
  91         return rxq->strd_num_n > 0;
  92 }
  93
  94 /**
  95  * Check whether Multi-Packet RQ is enabled for the device.
  96  *
  97  * @param dev
  98  *   Pointer to Ethernet device.
  99  *
 100  * @return
 101  *   0 if disabled, otherwise enabled.
 102  */
 103 inline int
 104 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 105 {
 106         struct mlx5_priv *priv = dev->data->dev_private;
 107         uint16_t i;
 108         uint16_t n = 0;
 109
 110         if (mlx5_check_mprq_support(dev) < 0)
 111                 return 0;
 112         /* All the configured queues should be enabled. */
 113         for (i = 0; i < priv->rxqs_n; ++i) {
 114                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 115
 116                 if (!rxq)
 117                         continue;
 118                 if (mlx5_rxq_mprq_enabled(rxq))
 119                         ++n;
 120         }
 121         /* Multi-Packet RQ can't be partially configured. */
 122         assert(n == 0 || n == priv->rxqs_n);
 123         return n == priv->rxqs_n;
 124 }
 125
 126 /**
 127  * Check whether LRO is supported and enabled for the device.
 128  *
 129  * @param dev
 130  *   Pointer to Ethernet device.
 131  *
 132  * @return
 133  *   0 if disabled, 1 if enabled.
 134  */
 135 inline int
 136 mlx5_lro_on(struct rte_eth_dev *dev)
 137 {
 138         return (MLX5_LRO_SUPPORTED(dev) && MLX5_LRO_ENABLED(dev));
 139 }
 140
 141 /**
 142  * Allocate RX queue elements for Multi-Packet RQ.
 143  *
 144  * @param rxq_ctrl
 145  *   Pointer to RX queue structure.
 146  *
 147  * @return
 148  *   0 on success, a negative errno value otherwise and rte_errno is set.
 149  */
 150 static int
 151 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 152 {
 153         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 154         unsigned int wqe_n = 1 << rxq->elts_n;
 155         unsigned int i;
 156         int err;
 157
 158         /* Iterate on segments. */
 159         for (i = 0; i <= wqe_n; ++i) {
 160                 struct mlx5_mprq_buf *buf;
 161
 162                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 163                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 164                         rte_errno = ENOMEM;
 165                         goto error;
 166                 }
 167                 if (i < wqe_n)
 168                         (*rxq->mprq_bufs)[i] = buf;
 169                 else
 170                         rxq->mprq_repl = buf;
 171         }
 172         DRV_LOG(DEBUG,
 173                 "port %u Rx queue %u allocated and configured %u segments",
 174                 rxq->port_id, rxq->idx, wqe_n);
 175         return 0;
 176 error:
 177         err = rte_errno; /* Save rte_errno before cleanup. */
 178         wqe_n = i;
 179         for (i = 0; (i != wqe_n); ++i) {
 180                 if ((*rxq->mprq_bufs)[i] != NULL)
 181                         rte_mempool_put(rxq->mprq_mp,
 182                                         (*rxq->mprq_bufs)[i]);
 183                 (*rxq->mprq_bufs)[i] = NULL;
 184         }
 185         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 186                 rxq->port_id, rxq->idx);
 187         rte_errno = err; /* Restore rte_errno. */
 188         return -rte_errno;
 189 }
 190
 191 /**
 192  * Allocate RX queue elements for Single-Packet RQ.
 193  *
 194  * @param rxq_ctrl
 195  *   Pointer to RX queue structure.
 196  *
 197  * @return
 198  *   0 on success, errno value on failure.
 199  */
 200 static int
 201 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 202 {
 203         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 204         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 205         unsigned int i;
 206         int err;
 207
 208         /* Iterate on segments. */
 209         for (i = 0; (i != elts_n); ++i) {
 210                 struct rte_mbuf *buf;
 211
 212                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 213                 if (buf == NULL) {
 214                         DRV_LOG(ERR, "port %u empty mbuf pool",
 215                                 PORT_ID(rxq_ctrl->priv));
 216                         rte_errno = ENOMEM;
 217                         goto error;
 218                 }
 219                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 220                 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 221                 /* Buffer is supposed to be empty. */
 222                 assert(rte_pktmbuf_data_len(buf) == 0);
 223                 assert(rte_pktmbuf_pkt_len(buf) == 0);
 224                 assert(!buf->next);
 225                 /* Only the first segment keeps headroom. */
 226                 if (i % sges_n)
 227                         SET_DATA_OFF(buf, 0);
 228                 PORT(buf) = rxq_ctrl->rxq.port_id;
 229                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 230                 PKT_LEN(buf) = DATA_LEN(buf);
 231                 NB_SEGS(buf) = 1;
 232                 (*rxq_ctrl->rxq.elts)[i] = buf;
 233         }
 234         /* If Rx vector is activated. */
 235         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 236                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 237                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 238                 int j;
 239
 240                 /* Initialize default rearm_data for vPMD. */
 241                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 242                 rte_mbuf_refcnt_set(mbuf_init, 1);
 243                 mbuf_init->nb_segs = 1;
 244                 mbuf_init->port = rxq->port_id;
 245                 /*
 246                  * prevent compiler reordering:
 247                  * rearm_data covers previous fields.
 248                  */
 249                 rte_compiler_barrier();
 250                 rxq->mbuf_initializer =
 251                         *(uint64_t *)&mbuf_init->rearm_data;
 252                 /* Padding with a fake mbuf for vectorized Rx. */
 253                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 254                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 255         }
 256         DRV_LOG(DEBUG,
 257                 "port %u Rx queue %u allocated and configured %u segments"
 258                 " (max %u packets)",
 259                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 260                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 261         return 0;
 262 error:
 263         err = rte_errno; /* Save rte_errno before cleanup. */
 264         elts_n = i;
 265         for (i = 0; (i != elts_n); ++i) {
 266                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 267                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 268                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 269         }
 270         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 271                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 272         rte_errno = err; /* Restore rte_errno. */
 273         return -rte_errno;
 274 }
 275
 276 /**
 277  * Allocate RX queue elements.
 278  *
 279  * @param rxq_ctrl
 280  *   Pointer to RX queue structure.
 281  *
 282  * @return
 283  *   0 on success, errno value on failure.
 284  */
 285 int
 286 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 287 {
 288         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 289                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 290 }
 291
 292 /**
 293  * Free RX queue elements for Multi-Packet RQ.
 294  *
 295  * @param rxq_ctrl
 296  *   Pointer to RX queue structure.
 297  */
 298 static void
 299 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 300 {
 301         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 302         uint16_t i;
 303
 304         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 305                 rxq->port_id, rxq->idx);
 306         if (rxq->mprq_bufs == NULL)
 307                 return;
 308         assert(mlx5_rxq_check_vec_support(rxq) < 0);
 309         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 310                 if ((*rxq->mprq_bufs)[i] != NULL)
 311                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 312                 (*rxq->mprq_bufs)[i] = NULL;
 313         }
 314         if (rxq->mprq_repl != NULL) {
 315                 mlx5_mprq_buf_free(rxq->mprq_repl);
 316                 rxq->mprq_repl = NULL;
 317         }
 318 }
 319
 320 /**
 321  * Free RX queue elements for Single-Packet RQ.
 322  *
 323  * @param rxq_ctrl
 324  *   Pointer to RX queue structure.
 325  */
 326 static void
 327 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 328 {
 329         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 330         const uint16_t q_n = (1 << rxq->elts_n);
 331         const uint16_t q_mask = q_n - 1;
 332         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 333         uint16_t i;
 334
 335         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 336                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 337         if (rxq->elts == NULL)
 338                 return;
 339         /**
 340          * Some mbuf in the Ring belongs to the application.  They cannot be
 341          * freed.
 342          */
 343         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 344                 for (i = 0; i < used; ++i)
 345                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 346                 rxq->rq_pi = rxq->rq_ci;
 347         }
 348         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 349                 if ((*rxq->elts)[i] != NULL)
 350                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 351                 (*rxq->elts)[i] = NULL;
 352         }
 353 }
 354
 355 /**
 356  * Free RX queue elements.
 357  *
 358  * @param rxq_ctrl
 359  *   Pointer to RX queue structure.
 360  */
 361 static void
 362 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 363 {
 364         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 365                 rxq_free_elts_mprq(rxq_ctrl);
 366         else
 367                 rxq_free_elts_sprq(rxq_ctrl);
 368 }
 369
 370 /**
 371  * Returns the per-queue supported offloads.
 372  *
 373  * @param dev
 374  *   Pointer to Ethernet device.
 375  *
 376  * @return
 377  *   Supported Rx offloads.
 378  */
 379 uint64_t
 380 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 381 {
 382         struct mlx5_priv *priv = dev->data->dev_private;
 383         struct mlx5_dev_config *config = &priv->config;
 384         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 385                              DEV_RX_OFFLOAD_TIMESTAMP |
 386                              DEV_RX_OFFLOAD_JUMBO_FRAME);
 387
 388         if (config->hw_fcs_strip)
 389                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 390
 391         if (config->hw_csum)
 392                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 393                              DEV_RX_OFFLOAD_UDP_CKSUM |
 394                              DEV_RX_OFFLOAD_TCP_CKSUM);
 395         if (config->hw_vlan_strip)
 396                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 397         return offloads;
 398 }
 399
 400
 401 /**
 402  * Returns the per-port supported offloads.
 403  *
 404  * @param dev
 405  *   Pointer to Ethernet device.
 406  *
 407  * @return
 408  *   Supported Rx offloads.
 409  */
 410 uint64_t
 411 mlx5_get_rx_port_offloads(struct rte_eth_dev *dev)
 412 {
 413         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 414
 415         if (MLX5_LRO_SUPPORTED(dev))
 416                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 417         return offloads;
 418 }
 419
 420 /**
 421  * Verify if the queue can be released.
 422  *
 423  * @param dev
 424  *   Pointer to Ethernet device.
 425  * @param idx
 426  *   RX queue index.
 427  *
 428  * @return
 429  *   1 if the queue can be released
 430  *   0 if the queue can not be released, there are references to it.
 431  *   Negative errno and rte_errno is set if queue doesn't exist.
 432  */
 433 static int
 434 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 435 {
 436         struct mlx5_priv *priv = dev->data->dev_private;
 437         struct mlx5_rxq_ctrl *rxq_ctrl;
 438
 439         if (!(*priv->rxqs)[idx]) {
 440                 rte_errno = EINVAL;
 441                 return -rte_errno;
 442         }
 443         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 444         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 445 }
 446
 447 /**
 448  *
 449  * @param dev
 450  *   Pointer to Ethernet device structure.
 451  * @param idx
 452  *   RX queue index.
 453  * @param desc
 454  *   Number of descriptors to configure in queue.
 455  * @param socket
 456  *   NUMA socket on which memory must be allocated.
 457  * @param[in] conf
 458  *   Thresholds parameters.
 459  * @param mp
 460  *   Memory pool for buffer allocations.
 461  *
 462  * @return
 463  *   0 on success, a negative errno value otherwise and rte_errno is set.
 464  */
 465 int
 466 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 467                     unsigned int socket, const struct rte_eth_rxconf *conf,
 468                     struct rte_mempool *mp)
 469 {
 470         struct mlx5_priv *priv = dev->data->dev_private;
 471         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 472         struct mlx5_rxq_ctrl *rxq_ctrl =
 473                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 474
 475         if (!rte_is_power_of_2(desc)) {
 476                 desc = 1 << log2above(desc);
 477                 DRV_LOG(WARNING,
 478                         "port %u increased number of descriptors in Rx queue %u"
 479                         " to the next power of two (%d)",
 480                         dev->data->port_id, idx, desc);
 481         }
 482         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 483                 dev->data->port_id, idx, desc);
 484         if (idx >= priv->rxqs_n) {
 485                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 486                         dev->data->port_id, idx, priv->rxqs_n);
 487                 rte_errno = EOVERFLOW;
 488                 return -rte_errno;
 489         }
 490         if (!mlx5_rxq_releasable(dev, idx)) {
 491                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 492                         dev->data->port_id, idx);
 493                 rte_errno = EBUSY;
 494                 return -rte_errno;
 495         }
 496         mlx5_rxq_release(dev, idx);
 497         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 498         if (!rxq_ctrl) {
 499                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 500                         dev->data->port_id, idx);
 501                 rte_errno = ENOMEM;
 502                 return -rte_errno;
 503         }
 504         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 505                 dev->data->port_id, idx);
 506         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 507         return 0;
 508 }
 509
 510 /**
 511  * DPDK callback to release a RX queue.
 512  *
 513  * @param dpdk_rxq
 514  *   Generic RX queue pointer.
 515  */
 516 void
 517 mlx5_rx_queue_release(void *dpdk_rxq)
 518 {
 519         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 520         struct mlx5_rxq_ctrl *rxq_ctrl;
 521         struct mlx5_priv *priv;
 522
 523         if (rxq == NULL)
 524                 return;
 525         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 526         priv = rxq_ctrl->priv;
 527         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 528                 rte_panic("port %u Rx queue %u is still used by a flow and"
 529                           " cannot be removed\n",
 530                           PORT_ID(priv), rxq->idx);
 531         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 532 }
 533
 534 /**
 535  * Get an Rx queue Verbs/DevX object.
 536  *
 537  * @param dev
 538  *   Pointer to Ethernet device.
 539  * @param idx
 540  *   Queue index in DPDK Rx queue array
 541  *
 542  * @return
 543  *   The Verbs/DevX object if it exists.
 544  */
 545 static struct mlx5_rxq_obj *
 546 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 547 {
 548         struct mlx5_priv *priv = dev->data->dev_private;
 549         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 550         struct mlx5_rxq_ctrl *rxq_ctrl;
 551
 552         if (idx >= priv->rxqs_n)
 553                 return NULL;
 554         if (!rxq_data)
 555                 return NULL;
 556         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 557         if (rxq_ctrl->obj)
 558                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 559         return rxq_ctrl->obj;
 560 }
 561
 562 /**
 563  * Release the resources allocated for an RQ DevX object.
 564  *
 565  * @param rxq_ctrl
 566  *   DevX Rx queue object.
 567  */
 568 static void
 569 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 570 {
 571         if (rxq_ctrl->rxq.wqes) {
 572                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 573                 rxq_ctrl->rxq.wqes = NULL;
 574         }
 575         if (rxq_ctrl->wq_umem) {
 576                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 577                 rxq_ctrl->wq_umem = NULL;
 578         }
 579 }
 580
 581 /**
 582  * Release an Rx verbs/DevX queue object.
 583  *
 584  * @param rxq_obj
 585  *   Verbs/DevX Rx queue object.
 586  *
 587  * @return
 588  *   1 while a reference on it exists, 0 when freed.
 589  */
 590 static int
 591 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 592 {
 593         assert(rxq_obj);
 594         if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV)
 595                 assert(rxq_obj->wq);
 596         assert(rxq_obj->cq);
 597         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 598                 rxq_free_elts(rxq_obj->rxq_ctrl);
 599                 if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
 600                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 601                 } else if (rxq_obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
 602                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 603                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 604                 }
 605                 claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 606                 if (rxq_obj->channel)
 607                         claim_zero(mlx5_glue->destroy_comp_channel
 608                                    (rxq_obj->channel));
 609                 LIST_REMOVE(rxq_obj, next);
 610                 rte_free(rxq_obj);
 611                 return 0;
 612         }
 613         return 1;
 614 }
 615
 616 /**
 617  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 618  *
 619  * @param dev
 620  *   Pointer to Ethernet device.
 621  *
 622  * @return
 623  *   0 on success, a negative errno value otherwise and rte_errno is set.
 624  */
 625 int
 626 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 627 {
 628         struct mlx5_priv *priv = dev->data->dev_private;
 629         unsigned int i;
 630         unsigned int rxqs_n = priv->rxqs_n;
 631         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 632         unsigned int count = 0;
 633         struct rte_intr_handle *intr_handle = dev->intr_handle;
 634
 635         if (!dev->data->dev_conf.intr_conf.rxq)
 636                 return 0;
 637         mlx5_rx_intr_vec_disable(dev);
 638         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 639         if (intr_handle->intr_vec == NULL) {
 640                 DRV_LOG(ERR,
 641                         "port %u failed to allocate memory for interrupt"
 642                         " vector, Rx interrupts will not be supported",
 643                         dev->data->port_id);
 644                 rte_errno = ENOMEM;
 645                 return -rte_errno;
 646         }
 647         intr_handle->type = RTE_INTR_HANDLE_EXT;
 648         for (i = 0; i != n; ++i) {
 649                 /* This rxq obj must not be released in this function. */
 650                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 651                 int fd;
 652                 int flags;
 653                 int rc;
 654
 655                 /* Skip queues that cannot request interrupts. */
 656                 if (!rxq_obj || !rxq_obj->channel) {
 657                         /* Use invalid intr_vec[] index to disable entry. */
 658                         intr_handle->intr_vec[i] =
 659                                 RTE_INTR_VEC_RXTX_OFFSET +
 660                                 RTE_MAX_RXTX_INTR_VEC_ID;
 661                         continue;
 662                 }
 663                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 664                         DRV_LOG(ERR,
 665                                 "port %u too many Rx queues for interrupt"
 666                                 " vector size (%d), Rx interrupts cannot be"
 667                                 " enabled",
 668                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 669                         mlx5_rx_intr_vec_disable(dev);
 670                         rte_errno = ENOMEM;
 671                         return -rte_errno;
 672                 }
 673                 fd = rxq_obj->channel->fd;
 674                 flags = fcntl(fd, F_GETFL);
 675                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 676                 if (rc < 0) {
 677                         rte_errno = errno;
 678                         DRV_LOG(ERR,
 679                                 "port %u failed to make Rx interrupt file"
 680                                 " descriptor %d non-blocking for queue index"
 681                                 " %d",
 682                                 dev->data->port_id, fd, i);
 683                         mlx5_rx_intr_vec_disable(dev);
 684                         return -rte_errno;
 685                 }
 686                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 687                 intr_handle->efds[count] = fd;
 688                 count++;
 689         }
 690         if (!count)
 691                 mlx5_rx_intr_vec_disable(dev);
 692         else
 693                 intr_handle->nb_efd = count;
 694         return 0;
 695 }
 696
 697 /**
 698  * Clean up Rx interrupts handler.
 699  *
 700  * @param dev
 701  *   Pointer to Ethernet device.
 702  */
 703 void
 704 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 705 {
 706         struct mlx5_priv *priv = dev->data->dev_private;
 707         struct rte_intr_handle *intr_handle = dev->intr_handle;
 708         unsigned int i;
 709         unsigned int rxqs_n = priv->rxqs_n;
 710         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 711
 712         if (!dev->data->dev_conf.intr_conf.rxq)
 713                 return;
 714         if (!intr_handle->intr_vec)
 715                 goto free;
 716         for (i = 0; i != n; ++i) {
 717                 struct mlx5_rxq_ctrl *rxq_ctrl;
 718                 struct mlx5_rxq_data *rxq_data;
 719
 720                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 721                     RTE_MAX_RXTX_INTR_VEC_ID)
 722                         continue;
 723                 /**
 724                  * Need to access directly the queue to release the reference
 725                  * kept in mlx5_rx_intr_vec_enable().
 726                  */
 727                 rxq_data = (*priv->rxqs)[i];
 728                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 729                 if (rxq_ctrl->obj)
 730                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 731         }
 732 free:
 733         rte_intr_free_epoll_fd(intr_handle);
 734         if (intr_handle->intr_vec)
 735                 free(intr_handle->intr_vec);
 736         intr_handle->nb_efd = 0;
 737         intr_handle->intr_vec = NULL;
 738 }
 739
 740 /**
 741  *  MLX5 CQ notification .
 742  *
 743  *  @param rxq
 744  *     Pointer to receive queue structure.
 745  *  @param sq_n_rxq
 746  *     Sequence number per receive queue .
 747  */
 748 static inline void
 749 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 750 {
 751         int sq_n = 0;
 752         uint32_t doorbell_hi;
 753         uint64_t doorbell;
 754         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 755
 756         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 757         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 758         doorbell = (uint64_t)doorbell_hi << 32;
 759         doorbell |=  rxq->cqn;
 760         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 761         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 762                          cq_db_reg, rxq->uar_lock_cq);
 763 }
 764
 765 /**
 766  * DPDK callback for Rx queue interrupt enable.
 767  *
 768  * @param dev
 769  *   Pointer to Ethernet device structure.
 770  * @param rx_queue_id
 771  *   Rx queue number.
 772  *
 773  * @return
 774  *   0 on success, a negative errno value otherwise and rte_errno is set.
 775  */
 776 int
 777 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 778 {
 779         struct mlx5_priv *priv = dev->data->dev_private;
 780         struct mlx5_rxq_data *rxq_data;
 781         struct mlx5_rxq_ctrl *rxq_ctrl;
 782
 783         rxq_data = (*priv->rxqs)[rx_queue_id];
 784         if (!rxq_data) {
 785                 rte_errno = EINVAL;
 786                 return -rte_errno;
 787         }
 788         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 789         if (rxq_ctrl->irq) {
 790                 struct mlx5_rxq_obj *rxq_obj;
 791
 792                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 793                 if (!rxq_obj) {
 794                         rte_errno = EINVAL;
 795                         return -rte_errno;
 796                 }
 797                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 798                 mlx5_rxq_obj_release(rxq_obj);
 799         }
 800         return 0;
 801 }
 802
 803 /**
 804  * DPDK callback for Rx queue interrupt disable.
 805  *
 806  * @param dev
 807  *   Pointer to Ethernet device structure.
 808  * @param rx_queue_id
 809  *   Rx queue number.
 810  *
 811  * @return
 812  *   0 on success, a negative errno value otherwise and rte_errno is set.
 813  */
 814 int
 815 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 816 {
 817         struct mlx5_priv *priv = dev->data->dev_private;
 818         struct mlx5_rxq_data *rxq_data;
 819         struct mlx5_rxq_ctrl *rxq_ctrl;
 820         struct mlx5_rxq_obj *rxq_obj = NULL;
 821         struct ibv_cq *ev_cq;
 822         void *ev_ctx;
 823         int ret;
 824
 825         rxq_data = (*priv->rxqs)[rx_queue_id];
 826         if (!rxq_data) {
 827                 rte_errno = EINVAL;
 828                 return -rte_errno;
 829         }
 830         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 831         if (!rxq_ctrl->irq)
 832                 return 0;
 833         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 834         if (!rxq_obj) {
 835                 rte_errno = EINVAL;
 836                 return -rte_errno;
 837         }
 838         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 839         if (ret || ev_cq != rxq_obj->cq) {
 840                 rte_errno = EINVAL;
 841                 goto exit;
 842         }
 843         rxq_data->cq_arm_sn++;
 844         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 845         mlx5_rxq_obj_release(rxq_obj);
 846         return 0;
 847 exit:
 848         ret = rte_errno; /* Save rte_errno before cleanup. */
 849         if (rxq_obj)
 850                 mlx5_rxq_obj_release(rxq_obj);
 851         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 852                 dev->data->port_id, rx_queue_id);
 853         rte_errno = ret; /* Restore rte_errno. */
 854         return -rte_errno;
 855 }
 856
 857 /**
 858  * Create a CQ Verbs object.
 859  *
 860  * @param dev
 861  *   Pointer to Ethernet device.
 862  * @param priv
 863  *   Pointer to device private data.
 864  * @param rxq_data
 865  *   Pointer to Rx queue data.
 866  * @param cqe_n
 867  *   Number of CQEs in CQ.
 868  * @param rxq_obj
 869  *   Pointer to Rx queue object data.
 870  *
 871  * @return
 872  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 873  */
 874 static struct ibv_cq *
 875 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 876                 struct mlx5_rxq_data *rxq_data,
 877                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 878 {
 879         struct {
 880                 struct ibv_cq_init_attr_ex ibv;
 881                 struct mlx5dv_cq_init_attr mlx5;
 882         } cq_attr;
 883
 884         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 885                 .cqe = cqe_n,
 886                 .channel = rxq_obj->channel,
 887                 .comp_mask = 0,
 888         };
 889         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 890                 .comp_mask = 0,
 891         };
 892         if (priv->config.cqe_comp && !rxq_data->hw_timestamp) {
 893                 cq_attr.mlx5.comp_mask |=
 894                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 895 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 896                 cq_attr.mlx5.cqe_comp_res_format =
 897                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 898                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 899                                 MLX5DV_CQE_RES_FORMAT_HASH;
 900 #else
 901                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
 902 #endif
 903                 /*
 904                  * For vectorized Rx, it must not be doubled in order to
 905                  * make cq_ci and rq_ci aligned.
 906                  */
 907                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
 908                         cq_attr.ibv.cqe *= 2;
 909         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
 910                 DRV_LOG(DEBUG,
 911                         "port %u Rx CQE compression is disabled for HW"
 912                         " timestamp",
 913                         dev->data->port_id);
 914         }
 915 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
 916         if (priv->config.cqe_pad) {
 917                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
 918                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
 919         }
 920 #endif
 921         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
 922                                                               &cq_attr.ibv,
 923                                                               &cq_attr.mlx5));
 924 }
 925
 926 /**
 927  * Create a WQ Verbs object.
 928  *
 929  * @param dev
 930  *   Pointer to Ethernet device.
 931  * @param priv
 932  *   Pointer to device private data.
 933  * @param rxq_data
 934  *   Pointer to Rx queue data.
 935  * @param idx
 936  *   Queue index in DPDK Rx queue array
 937  * @param wqe_n
 938  *   Number of WQEs in WQ.
 939  * @param rxq_obj
 940  *   Pointer to Rx queue object data.
 941  *
 942  * @return
 943  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 944  */
 945 static struct ibv_wq *
 946 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 947                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
 948                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
 949 {
 950         struct {
 951                 struct ibv_wq_init_attr ibv;
 952 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 953                 struct mlx5dv_wq_init_attr mlx5;
 954 #endif
 955         } wq_attr;
 956
 957         wq_attr.ibv = (struct ibv_wq_init_attr){
 958                 .wq_context = NULL, /* Could be useful in the future. */
 959                 .wq_type = IBV_WQT_RQ,
 960                 /* Max number of outstanding WRs. */
 961                 .max_wr = wqe_n >> rxq_data->sges_n,
 962                 /* Max number of scatter/gather elements in a WR. */
 963                 .max_sge = 1 << rxq_data->sges_n,
 964                 .pd = priv->sh->pd,
 965                 .cq = rxq_obj->cq,
 966                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
 967                 .create_flags = (rxq_data->vlan_strip ?
 968                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
 969         };
 970         /* By default, FCS (CRC) is stripped by hardware. */
 971         if (rxq_data->crc_present) {
 972                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
 973                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 974         }
 975         if (priv->config.hw_padding) {
 976 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
 977                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
 978                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 979 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
 980                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
 981                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
 982 #endif
 983         }
 984 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 985         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
 986                 .comp_mask = 0,
 987         };
 988         if (mlx5_rxq_mprq_enabled(rxq_data)) {
 989                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
 990                                                 &wq_attr.mlx5.striding_rq_attrs;
 991
 992                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
 993                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
 994                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
 995                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
 996                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
 997                 };
 998         }
 999         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1000                                               &wq_attr.mlx5);
1001 #else
1002         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1003 #endif
1004         if (rxq_obj->wq) {
1005                 /*
1006                  * Make sure number of WRs*SGEs match expectations since a queue
1007                  * cannot allocate more than "desc" buffers.
1008                  */
1009                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1010                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1011                         DRV_LOG(ERR,
1012                                 "port %u Rx queue %u requested %u*%u but got"
1013                                 " %u*%u WRs*SGEs",
1014                                 dev->data->port_id, idx,
1015                                 wqe_n >> rxq_data->sges_n,
1016                                 (1 << rxq_data->sges_n),
1017                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1018                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1019                         rxq_obj->wq = NULL;
1020                         rte_errno = EINVAL;
1021                 }
1022         }
1023         return rxq_obj->wq;
1024 }
1025
1026 /**
1027  * Fill common fields of create RQ attributes structure.
1028  *
1029  * @param rxq_data
1030  *   Pointer to Rx queue data.
1031  * @param cqn
1032  *   CQ number to use with this RQ.
1033  * @param rq_attr
1034  *   RQ attributes structure to fill..
1035  */
1036 static void
1037 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1038                               struct mlx5_devx_create_rq_attr *rq_attr)
1039 {
1040         rq_attr->state = MLX5_RQC_STATE_RST;
1041         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1042         rq_attr->cqn = cqn;
1043         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1044 }
1045
1046 /**
1047  * Fill common fields of DevX WQ attributes structure.
1048  *
1049  * @param priv
1050  *   Pointer to device private data.
1051  * @param rxq_ctrl
1052  *   Pointer to Rx queue control structure.
1053  * @param wq_attr
1054  *   WQ attributes structure to fill..
1055  */
1056 static void
1057 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1058                        struct mlx5_devx_wq_attr *wq_attr)
1059 {
1060         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1061                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1062                                         MLX5_WQ_END_PAD_MODE_NONE;
1063         wq_attr->pd = priv->sh->pdn;
1064         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1065         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1066         wq_attr->dbr_umem_valid = 1;
1067         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1068         wq_attr->wq_umem_valid = 1;
1069 }
1070
1071 /**
1072  * Create a RQ object using DevX.
1073  *
1074  * @param dev
1075  *   Pointer to Ethernet device.
1076  * @param idx
1077  *   Queue index in DPDK Rx queue array
1078  * @param cqn
1079  *   CQ number to use with this RQ.
1080  *
1081  * @return
1082  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1083  */
1084 static struct mlx5_devx_obj *
1085 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1086 {
1087         struct mlx5_priv *priv = dev->data->dev_private;
1088         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1089         struct mlx5_rxq_ctrl *rxq_ctrl =
1090                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1091         struct mlx5_devx_create_rq_attr rq_attr;
1092         uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1093         uint32_t wq_size = 0;
1094         uint32_t wqe_size = 0;
1095         uint32_t log_wqe_size = 0;
1096         void *buf = NULL;
1097         struct mlx5_devx_obj *rq;
1098
1099         memset(&rq_attr, 0, sizeof(rq_attr));
1100         /* Fill RQ attributes. */
1101         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1102         rq_attr.flush_in_error_en = 1;
1103         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1104         /* Fill WQ attributes for this RQ. */
1105         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1106                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1107                 /*
1108                  * Number of strides in each WQE:
1109                  * 512*2^single_wqe_log_num_of_strides.
1110                  */
1111                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1112                                 rxq_data->strd_num_n -
1113                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1114                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1115                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1116                                 rxq_data->strd_sz_n -
1117                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1118                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1119         } else {
1120                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1121                 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1122         }
1123         log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1124         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1125         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1126         /* Calculate and allocate WQ memory space. */
1127         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1128         wq_size = wqe_n * wqe_size;
1129         buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1130                                 rxq_ctrl->socket);
1131         if (!buf)
1132                 return NULL;
1133         rxq_data->wqes = buf;
1134         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1135                                                      buf, wq_size, 0);
1136         if (!rxq_ctrl->wq_umem) {
1137                 rte_free(buf);
1138                 return NULL;
1139         }
1140         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1141         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1142         if (!rq)
1143                 rxq_release_rq_resources(rxq_ctrl);
1144         return rq;
1145 }
1146
1147 /**
1148  * Create the Rx queue Verbs/DevX object.
1149  *
1150  * @param dev
1151  *   Pointer to Ethernet device.
1152  * @param idx
1153  *   Queue index in DPDK Rx queue array
1154  * @param type
1155  *   Type of Rx queue object to create.
1156  *
1157  * @return
1158  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1159  */
1160 struct mlx5_rxq_obj *
1161 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1162                  enum mlx5_rxq_obj_type type)
1163 {
1164         struct mlx5_priv *priv = dev->data->dev_private;
1165         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1166         struct mlx5_rxq_ctrl *rxq_ctrl =
1167                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1168         struct ibv_wq_attr mod;
1169         unsigned int cqe_n;
1170         unsigned int wqe_n = 1 << rxq_data->elts_n;
1171         struct mlx5_rxq_obj *tmpl = NULL;
1172         struct mlx5dv_cq cq_info;
1173         struct mlx5dv_rwq rwq;
1174         int ret = 0;
1175         struct mlx5dv_obj obj;
1176
1177         assert(rxq_data);
1178         assert(!rxq_ctrl->obj);
1179         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1180         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1181         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1182                                  rxq_ctrl->socket);
1183         if (!tmpl) {
1184                 DRV_LOG(ERR,
1185                         "port %u Rx queue %u cannot allocate verbs resources",
1186                         dev->data->port_id, rxq_data->idx);
1187                 rte_errno = ENOMEM;
1188                 goto error;
1189         }
1190         tmpl->type = type;
1191         tmpl->rxq_ctrl = rxq_ctrl;
1192         if (rxq_ctrl->irq) {
1193                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1194                 if (!tmpl->channel) {
1195                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1196                                 dev->data->port_id);
1197                         rte_errno = ENOMEM;
1198                         goto error;
1199                 }
1200         }
1201         if (mlx5_rxq_mprq_enabled(rxq_data))
1202                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1203         else
1204                 cqe_n = wqe_n  - 1;
1205         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1206         if (!tmpl->cq) {
1207                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1208                         dev->data->port_id, idx);
1209                 rte_errno = ENOMEM;
1210                 goto error;
1211         }
1212         obj.cq.in = tmpl->cq;
1213         obj.cq.out = &cq_info;
1214         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1215         if (ret) {
1216                 rte_errno = ret;
1217                 goto error;
1218         }
1219         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1220                 DRV_LOG(ERR,
1221                         "port %u wrong MLX5_CQE_SIZE environment variable"
1222                         " value: it should be set to %u",
1223                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1224                 rte_errno = EINVAL;
1225                 goto error;
1226         }
1227         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1228                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);
1229         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1230                 dev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);
1231         /* Allocate door-bell for types created with DevX. */
1232         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1233                 struct mlx5_devx_dbr_page *dbr_page;
1234                 int64_t dbr_offset;
1235
1236                 dbr_offset = mlx5_get_dbr(dev, &dbr_page);
1237                 if (dbr_offset < 0)
1238                         goto error;
1239                 rxq_ctrl->dbr_offset = dbr_offset;
1240                 rxq_ctrl->dbr_umem_id = dbr_page->umem->umem_id;
1241                 rxq_ctrl->dbr_umem_id_valid = 1;
1242                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1243                                                (uintptr_t)rxq_ctrl->dbr_offset);
1244         }
1245         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1246                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1247                                            tmpl);
1248                 if (!tmpl->wq) {
1249                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1250                                 dev->data->port_id, idx);
1251                         rte_errno = ENOMEM;
1252                         goto error;
1253                 }
1254                 /* Change queue state to ready. */
1255                 mod = (struct ibv_wq_attr){
1256                         .attr_mask = IBV_WQ_ATTR_STATE,
1257                         .wq_state = IBV_WQS_RDY,
1258                 };
1259                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1260                 if (ret) {
1261                         DRV_LOG(ERR,
1262                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1263                                 " failed", dev->data->port_id, idx);
1264                         rte_errno = ret;
1265                         goto error;
1266                 }
1267                 obj.rwq.in = tmpl->wq;
1268                 obj.rwq.out = &rwq;
1269                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1270                 if (ret) {
1271                         rte_errno = ret;
1272                         goto error;
1273                 }
1274                 rxq_data->wqes = rwq.buf;
1275                 rxq_data->rq_db = rwq.dbrec;
1276         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1277                 struct mlx5_devx_modify_rq_attr rq_attr;
1278
1279                 memset(&rq_attr, 0, sizeof(rq_attr));
1280                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1281                 if (!tmpl->rq) {
1282                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1283                                 dev->data->port_id, idx);
1284                         rte_errno = ENOMEM;
1285                         goto error;
1286                 }
1287                 /* Change queue state to ready. */
1288                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1289                 rq_attr.state = MLX5_RQC_STATE_RDY;
1290                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1291                 if (ret)
1292                         goto error;
1293         }
1294         /* Fill the rings. */
1295         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1296         rxq_data->cq_db = cq_info.dbrec;
1297         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1298         rxq_data->cq_uar = cq_info.cq_uar;
1299         rxq_data->cqn = cq_info.cqn;
1300         rxq_data->cq_arm_sn = 0;
1301         mlx5_rxq_initialize(rxq_data);
1302         rxq_data->cq_ci = 0;
1303         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1304                 idx, (void *)&tmpl);
1305         rte_atomic32_inc(&tmpl->refcnt);
1306         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1307         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1308         return tmpl;
1309 error:
1310         if (tmpl) {
1311                 ret = rte_errno; /* Save rte_errno before cleanup. */
1312                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1313                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1314                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1315                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1316                 if (tmpl->cq)
1317                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1318                 if (tmpl->channel)
1319                         claim_zero(mlx5_glue->destroy_comp_channel
1320                                                         (tmpl->channel));
1321                 rte_free(tmpl);
1322                 rte_errno = ret; /* Restore rte_errno. */
1323         }
1324         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1325                 rxq_release_rq_resources(rxq_ctrl);
1326         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1327         return NULL;
1328 }
1329
1330 /**
1331  * Verify the Rx queue objects list is empty
1332  *
1333  * @param dev
1334  *   Pointer to Ethernet device.
1335  *
1336  * @return
1337  *   The number of objects not released.
1338  */
1339 int
1340 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1341 {
1342         struct mlx5_priv *priv = dev->data->dev_private;
1343         int ret = 0;
1344         struct mlx5_rxq_obj *rxq_obj;
1345
1346         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1347                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1348                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1349                 ++ret;
1350         }
1351         return ret;
1352 }
1353
1354 /**
1355  * Callback function to initialize mbufs for Multi-Packet RQ.
1356  */
1357 static inline void
1358 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1359                     void *_m, unsigned int i __rte_unused)
1360 {
1361         struct mlx5_mprq_buf *buf = _m;
1362         struct rte_mbuf_ext_shared_info *shinfo;
1363         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1364         unsigned int j;
1365
1366         memset(_m, 0, sizeof(*buf));
1367         buf->mp = mp;
1368         rte_atomic16_set(&buf->refcnt, 1);
1369         for (j = 0; j != strd_n; ++j) {
1370                 shinfo = &buf->shinfos[j];
1371                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1372                 shinfo->fcb_opaque = buf;
1373         }
1374 }
1375
1376 /**
1377  * Free mempool of Multi-Packet RQ.
1378  *
1379  * @param dev
1380  *   Pointer to Ethernet device.
1381  *
1382  * @return
1383  *   0 on success, negative errno value on failure.
1384  */
1385 int
1386 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1387 {
1388         struct mlx5_priv *priv = dev->data->dev_private;
1389         struct rte_mempool *mp = priv->mprq_mp;
1390         unsigned int i;
1391
1392         if (mp == NULL)
1393                 return 0;
1394         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1395                 dev->data->port_id, mp->name);
1396         /*
1397          * If a buffer in the pool has been externally attached to a mbuf and it
1398          * is still in use by application, destroying the Rx queue can spoil
1399          * the packet. It is unlikely to happen but if application dynamically
1400          * creates and destroys with holding Rx packets, this can happen.
1401          *
1402          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1403          * RQ isn't provided by application but managed by PMD.
1404          */
1405         if (!rte_mempool_full(mp)) {
1406                 DRV_LOG(ERR,
1407                         "port %u mempool for Multi-Packet RQ is still in use",
1408                         dev->data->port_id);
1409                 rte_errno = EBUSY;
1410                 return -rte_errno;
1411         }
1412         rte_mempool_free(mp);
1413         /* Unset mempool for each Rx queue. */
1414         for (i = 0; i != priv->rxqs_n; ++i) {
1415                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1416
1417                 if (rxq == NULL)
1418                         continue;
1419                 rxq->mprq_mp = NULL;
1420         }
1421         priv->mprq_mp = NULL;
1422         return 0;
1423 }
1424
1425 /**
1426  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1427  * mempool. If already allocated, reuse it if there're enough elements.
1428  * Otherwise, resize it.
1429  *
1430  * @param dev
1431  *   Pointer to Ethernet device.
1432  *
1433  * @return
1434  *   0 on success, negative errno value on failure.
1435  */
1436 int
1437 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1438 {
1439         struct mlx5_priv *priv = dev->data->dev_private;
1440         struct rte_mempool *mp = priv->mprq_mp;
1441         char name[RTE_MEMPOOL_NAMESIZE];
1442         unsigned int desc = 0;
1443         unsigned int buf_len;
1444         unsigned int obj_num;
1445         unsigned int obj_size;
1446         unsigned int strd_num_n = 0;
1447         unsigned int strd_sz_n = 0;
1448         unsigned int i;
1449
1450         if (!mlx5_mprq_enabled(dev))
1451                 return 0;
1452         /* Count the total number of descriptors configured. */
1453         for (i = 0; i != priv->rxqs_n; ++i) {
1454                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1455
1456                 if (rxq == NULL)
1457                         continue;
1458                 desc += 1 << rxq->elts_n;
1459                 /* Get the max number of strides. */
1460                 if (strd_num_n < rxq->strd_num_n)
1461                         strd_num_n = rxq->strd_num_n;
1462                 /* Get the max size of a stride. */
1463                 if (strd_sz_n < rxq->strd_sz_n)
1464                         strd_sz_n = rxq->strd_sz_n;
1465         }
1466         assert(strd_num_n && strd_sz_n);
1467         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1468         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1469                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1470         /*
1471          * Received packets can be either memcpy'd or externally referenced. In
1472          * case that the packet is attached to an mbuf as an external buffer, as
1473          * it isn't possible to predict how the buffers will be queued by
1474          * application, there's no option to exactly pre-allocate needed buffers
1475          * in advance but to speculatively prepares enough buffers.
1476          *
1477          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1478          * received packets to buffers provided by application (rxq->mp) until
1479          * this Mempool gets available again.
1480          */
1481         desc *= 4;
1482         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * priv->rxqs_n;
1483         /*
1484          * rte_mempool_create_empty() has sanity check to refuse large cache
1485          * size compared to the number of elements.
1486          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1487          * constant number 2 instead.
1488          */
1489         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1490         /* Check a mempool is already allocated and if it can be resued. */
1491         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1492                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1493                         dev->data->port_id, mp->name);
1494                 /* Reuse. */
1495                 goto exit;
1496         } else if (mp != NULL) {
1497                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1498                         dev->data->port_id, mp->name);
1499                 /*
1500                  * If failed to free, which means it may be still in use, no way
1501                  * but to keep using the existing one. On buffer underrun,
1502                  * packets will be memcpy'd instead of external buffer
1503                  * attachment.
1504                  */
1505                 if (mlx5_mprq_free_mp(dev)) {
1506                         if (mp->elt_size >= obj_size)
1507                                 goto exit;
1508                         else
1509                                 return -rte_errno;
1510                 }
1511         }
1512         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1513         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1514                                 0, NULL, NULL, mlx5_mprq_buf_init,
1515                                 (void *)(uintptr_t)(1 << strd_num_n),
1516                                 dev->device->numa_node, 0);
1517         if (mp == NULL) {
1518                 DRV_LOG(ERR,
1519                         "port %u failed to allocate a mempool for"
1520                         " Multi-Packet RQ, count=%u, size=%u",
1521                         dev->data->port_id, obj_num, obj_size);
1522                 rte_errno = ENOMEM;
1523                 return -rte_errno;
1524         }
1525         priv->mprq_mp = mp;
1526 exit:
1527         /* Set mempool for each Rx queue. */
1528         for (i = 0; i != priv->rxqs_n; ++i) {
1529                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1530
1531                 if (rxq == NULL)
1532                         continue;
1533                 rxq->mprq_mp = mp;
1534         }
1535         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1536                 dev->data->port_id);
1537         return 0;
1538 }
1539
1540 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * 256u)
1541 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1542                                         sizeof(struct rte_vlan_hdr) * 2 + \
1543                                         sizeof(struct rte_ipv6_hdr)))
1544 #define MAX_TCP_OPTION_SIZE 40u
1545 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1546                                  sizeof(struct rte_tcp_hdr) + \
1547                                  MAX_TCP_OPTION_SIZE))
1548
1549 /**
1550  * Adjust the maximum LRO massage size.
1551  *
1552  * @param dev
1553  *   Pointer to Ethernet device.
1554  * @param max_lro_size
1555  *   The maximum size for LRO packet.
1556  */
1557 static void
1558 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint32_t max_lro_size)
1559 {
1560         struct mlx5_priv *priv = dev->data->dev_private;
1561
1562         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1563             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1564             MLX5_MAX_TCP_HDR_OFFSET)
1565                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1566         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1567         assert(max_lro_size >= 256u);
1568         max_lro_size /= 256u;
1569         if (priv->max_lro_msg_size)
1570                 priv->max_lro_msg_size =
1571                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1572         else
1573                 priv->max_lro_msg_size = max_lro_size;
1574 }
1575
1576 /**
1577  * Create a DPDK Rx queue.
1578  *
1579  * @param dev
1580  *   Pointer to Ethernet device.
1581  * @param idx
1582  *   RX queue index.
1583  * @param desc
1584  *   Number of descriptors to configure in queue.
1585  * @param socket
1586  *   NUMA socket on which memory must be allocated.
1587  *
1588  * @return
1589  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1590  */
1591 struct mlx5_rxq_ctrl *
1592 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1593              unsigned int socket, const struct rte_eth_rxconf *conf,
1594              struct rte_mempool *mp)
1595 {
1596         struct mlx5_priv *priv = dev->data->dev_private;
1597         struct mlx5_rxq_ctrl *tmpl;
1598         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1599         unsigned int mprq_stride_size;
1600         struct mlx5_dev_config *config = &priv->config;
1601         unsigned int strd_headroom_en;
1602         /*
1603          * Always allocate extra slots, even if eventually
1604          * the vector Rx will not be used.
1605          */
1606         uint16_t desc_n =
1607                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1608         uint64_t offloads = conf->offloads |
1609                            dev->data->dev_conf.rxmode.offloads;
1610         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1611         unsigned int max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1612         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1613                                                         RTE_PKTMBUF_HEADROOM;
1614         unsigned int max_lro_size = 0;
1615         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1616
1617         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1618                                                     DEV_RX_OFFLOAD_SCATTER)) {
1619                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1620                         " configured and no enough mbuf space(%u) to contain "
1621                         "the maximum RX packet length(%u) with head-room(%u)",
1622                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1623                         RTE_PKTMBUF_HEADROOM);
1624                 rte_errno = ENOSPC;
1625                 return NULL;
1626         }
1627         tmpl = rte_calloc_socket("RXQ", 1,
1628                                  sizeof(*tmpl) +
1629                                  desc_n * sizeof(struct rte_mbuf *),
1630                                  0, socket);
1631         if (!tmpl) {
1632                 rte_errno = ENOMEM;
1633                 return NULL;
1634         }
1635         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1636                                MLX5_MR_BTREE_CACHE_N, socket)) {
1637                 /* rte_errno is already set. */
1638                 goto error;
1639         }
1640         tmpl->socket = socket;
1641         if (dev->data->dev_conf.intr_conf.rxq)
1642                 tmpl->irq = 1;
1643         /*
1644          * LRO packet may consume all the stride memory, hence we cannot
1645          * guaranty head-room near the packet memory in the stride.
1646          * In this case scatter is, for sure, enabled and an empty mbuf may be
1647          * added in the start for the head-room.
1648          */
1649         if (mlx5_lro_on(dev) && RTE_PKTMBUF_HEADROOM > 0 &&
1650             non_scatter_min_mbuf_size > mb_len) {
1651                 strd_headroom_en = 0;
1652                 mprq_stride_size = RTE_MIN(max_rx_pkt_len,
1653                                         1u << config->mprq.max_stride_size_n);
1654         } else {
1655                 strd_headroom_en = 1;
1656                 mprq_stride_size = non_scatter_min_mbuf_size;
1657         }
1658         /*
1659          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1660          * following conditions are met:
1661          *  - MPRQ is enabled.
1662          *  - The number of descs is more than the number of strides.
1663          *  - max_rx_pkt_len plus overhead is less than the max size of a
1664          *    stride.
1665          *  Otherwise, enable Rx scatter if necessary.
1666          */
1667         if (mprq_en &&
1668             desc > (1U << config->mprq.stride_num_n) &&
1669             mprq_stride_size <= (1U << config->mprq.max_stride_size_n)) {
1670                 /* TODO: Rx scatter isn't supported yet. */
1671                 tmpl->rxq.sges_n = 0;
1672                 /* Trim the number of descs needed. */
1673                 desc >>= config->mprq.stride_num_n;
1674                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n;
1675                 tmpl->rxq.strd_sz_n = RTE_MAX(log2above(mprq_stride_size),
1676                                               config->mprq.min_stride_size_n);
1677                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1678                 tmpl->rxq.strd_headroom_en = strd_headroom_en;
1679                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1680                                 config->mprq.max_memcpy_len);
1681                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1682                                        (1u << tmpl->rxq.strd_num_n) *
1683                                        (1u << tmpl->rxq.strd_sz_n));
1684                 DRV_LOG(DEBUG,
1685                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1686                         " strd_num_n = %u, strd_sz_n = %u",
1687                         dev->data->port_id, idx,
1688                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1689         } else if (max_rx_pkt_len <= first_mb_free_size) {
1690                 tmpl->rxq.sges_n = 0;
1691                 max_lro_size = max_rx_pkt_len;
1692         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1693                 unsigned int size = non_scatter_min_mbuf_size;
1694                 unsigned int sges_n;
1695
1696                 if (mlx5_lro_on(dev) && first_mb_free_size <
1697                     MLX5_MAX_LRO_HEADER_FIX) {
1698                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1699                                 " to include the max header size(%u) for LRO",
1700                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1701                         rte_errno = ENOTSUP;
1702                         goto error;
1703                 }
1704                 /*
1705                  * Determine the number of SGEs needed for a full packet
1706                  * and round it to the next power of two.
1707                  */
1708                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1709                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1710                         DRV_LOG(ERR,
1711                                 "port %u too many SGEs (%u) needed to handle"
1712                                 " requested maximum packet size %u, the maximum"
1713                                 " supported are %u", dev->data->port_id,
1714                                 1 << sges_n, max_rx_pkt_len,
1715                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1716                         rte_errno = ENOTSUP;
1717                         goto error;
1718                 }
1719                 tmpl->rxq.sges_n = sges_n;
1720                 max_lro_size = max_rx_pkt_len;
1721         }
1722         if (mprq_en && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1723                 DRV_LOG(WARNING,
1724                         "port %u MPRQ is requested but cannot be enabled"
1725                         " (requested: desc = %u, stride_sz = %u,"
1726                         " supported: min_stride_num = %u, max_stride_sz = %u).",
1727                         dev->data->port_id, desc, mprq_stride_size,
1728                         (1 << config->mprq.stride_num_n),
1729                         (1 << config->mprq.max_stride_size_n));
1730         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1731                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1732         if (desc % (1 << tmpl->rxq.sges_n)) {
1733                 DRV_LOG(ERR,
1734                         "port %u number of Rx queue descriptors (%u) is not a"
1735                         " multiple of SGEs per packet (%u)",
1736                         dev->data->port_id,
1737                         desc,
1738                         1 << tmpl->rxq.sges_n);
1739                 rte_errno = EINVAL;
1740                 goto error;
1741         }
1742         mlx5_max_lro_msg_size_adjust(dev, max_lro_size);
1743         /* Toggle RX checksum offload if hardware supports it. */
1744         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1745         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1746         /* Configure VLAN stripping. */
1747         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1748         /* By default, FCS (CRC) is stripped by hardware. */
1749         tmpl->rxq.crc_present = 0;
1750         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1751                 if (config->hw_fcs_strip) {
1752                         /*
1753                          * RQs used for LRO-enabled TIRs should not be
1754                          * configured to scatter the FCS.
1755                          */
1756                         if (mlx5_lro_on(dev))
1757                                 DRV_LOG(WARNING,
1758                                         "port %u CRC stripping has been "
1759                                         "disabled but will still be performed "
1760                                         "by hardware, because LRO is enabled",
1761                                         dev->data->port_id);
1762                         else
1763                                 tmpl->rxq.crc_present = 1;
1764                 } else {
1765                         DRV_LOG(WARNING,
1766                                 "port %u CRC stripping has been disabled but will"
1767                                 " still be performed by hardware, make sure MLNX_OFED"
1768                                 " and firmware are up to date",
1769                                 dev->data->port_id);
1770                 }
1771         }
1772         DRV_LOG(DEBUG,
1773                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1774                 " incoming frames to hide it",
1775                 dev->data->port_id,
1776                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1777                 tmpl->rxq.crc_present << 2);
1778         /* Save port ID. */
1779         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1780                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1781         tmpl->rxq.port_id = dev->data->port_id;
1782         tmpl->priv = priv;
1783         tmpl->rxq.mp = mp;
1784         tmpl->rxq.elts_n = log2above(desc);
1785         tmpl->rxq.rq_repl_thresh =
1786                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1787         tmpl->rxq.elts =
1788                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1789 #ifndef RTE_ARCH_64
1790         tmpl->rxq.uar_lock_cq = &priv->uar_lock_cq;
1791 #endif
1792         tmpl->rxq.idx = idx;
1793         rte_atomic32_inc(&tmpl->refcnt);
1794         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
1795         return tmpl;
1796 error:
1797         rte_free(tmpl);
1798         return NULL;
1799 }
1800
1801 /**
1802  * Get a Rx queue.
1803  *
1804  * @param dev
1805  *   Pointer to Ethernet device.
1806  * @param idx
1807  *   RX queue index.
1808  *
1809  * @return
1810  *   A pointer to the queue if it exists, NULL otherwise.
1811  */
1812 struct mlx5_rxq_ctrl *
1813 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
1814 {
1815         struct mlx5_priv *priv = dev->data->dev_private;
1816         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
1817
1818         if ((*priv->rxqs)[idx]) {
1819                 rxq_ctrl = container_of((*priv->rxqs)[idx],
1820                                         struct mlx5_rxq_ctrl,
1821                                         rxq);
1822                 mlx5_rxq_obj_get(dev, idx);
1823                 rte_atomic32_inc(&rxq_ctrl->refcnt);
1824         }
1825         return rxq_ctrl;
1826 }
1827
1828 /**
1829  * Release a Rx queue.
1830  *
1831  * @param dev
1832  *   Pointer to Ethernet device.
1833  * @param idx
1834  *   RX queue index.
1835  *
1836  * @return
1837  *   1 while a reference on it exists, 0 when freed.
1838  */
1839 int
1840 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
1841 {
1842         struct mlx5_priv *priv = dev->data->dev_private;
1843         struct mlx5_rxq_ctrl *rxq_ctrl;
1844
1845         if (!(*priv->rxqs)[idx])
1846                 return 0;
1847         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
1848         assert(rxq_ctrl->priv);
1849         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
1850                 rxq_ctrl->obj = NULL;
1851         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
1852                 if (rxq_ctrl->dbr_umem_id_valid)
1853                         claim_zero(mlx5_release_dbr(dev, rxq_ctrl->dbr_umem_id,
1854                                                     rxq_ctrl->dbr_offset));
1855                 mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
1856                 LIST_REMOVE(rxq_ctrl, next);
1857                 rte_free(rxq_ctrl);
1858                 (*priv->rxqs)[idx] = NULL;
1859                 return 0;
1860         }
1861         return 1;
1862 }
1863
1864 /**
1865  * Verify the Rx Queue list is empty
1866  *
1867  * @param dev
1868  *   Pointer to Ethernet device.
1869  *
1870  * @return
1871  *   The number of object not released.
1872  */
1873 int
1874 mlx5_rxq_verify(struct rte_eth_dev *dev)
1875 {
1876         struct mlx5_priv *priv = dev->data->dev_private;
1877         struct mlx5_rxq_ctrl *rxq_ctrl;
1878         int ret = 0;
1879
1880         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
1881                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
1882                         dev->data->port_id, rxq_ctrl->rxq.idx);
1883                 ++ret;
1884         }
1885         return ret;
1886 }
1887
1888 /**
1889  * Create an indirection table.
1890  *
1891  * @param dev
1892  *   Pointer to Ethernet device.
1893  * @param queues
1894  *   Queues entering in the indirection table.
1895  * @param queues_n
1896  *   Number of queues in the array.
1897  *
1898  * @return
1899  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1900  */
1901 static struct mlx5_ind_table_obj *
1902 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
1903                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
1904 {
1905         struct mlx5_priv *priv = dev->data->dev_private;
1906         struct mlx5_ind_table_obj *ind_tbl;
1907         unsigned int i = 0, j = 0, k = 0;
1908
1909         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
1910                              queues_n * sizeof(uint16_t), 0);
1911         if (!ind_tbl) {
1912                 rte_errno = ENOMEM;
1913                 return NULL;
1914         }
1915         ind_tbl->type = type;
1916         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
1917                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
1918                         log2above(queues_n) :
1919                         log2above(priv->config.ind_table_max_size);
1920                 struct ibv_wq *wq[1 << wq_n];
1921
1922                 for (i = 0; i != queues_n; ++i) {
1923                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1924                                                                  queues[i]);
1925                         if (!rxq)
1926                                 goto error;
1927                         wq[i] = rxq->obj->wq;
1928                         ind_tbl->queues[i] = queues[i];
1929                 }
1930                 ind_tbl->queues_n = queues_n;
1931                 /* Finalise indirection table. */
1932                 k = i; /* Retain value of i for use in error case. */
1933                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
1934                         wq[k] = wq[j];
1935                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
1936                         (priv->sh->ctx,
1937                          &(struct ibv_rwq_ind_table_init_attr){
1938                                 .log_ind_tbl_size = wq_n,
1939                                 .ind_tbl = wq,
1940                                 .comp_mask = 0,
1941                         });
1942                 if (!ind_tbl->ind_table) {
1943                         rte_errno = errno;
1944                         goto error;
1945                 }
1946         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
1947                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
1948
1949                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
1950                                       queues_n * sizeof(uint16_t), 0);
1951                 if (!rqt_attr) {
1952                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
1953                                 dev->data->port_id);
1954                         rte_errno = ENOMEM;
1955                         goto error;
1956                 }
1957                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
1958                 rqt_attr->rqt_actual_size = queues_n;
1959                 for (i = 0; i != queues_n; ++i) {
1960                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
1961                                                                  queues[i]);
1962                         if (!rxq)
1963                                 goto error;
1964                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
1965                         ind_tbl->queues[i] = queues[i];
1966                 }
1967                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
1968                                                         rqt_attr);
1969                 rte_free(rqt_attr);
1970                 if (!ind_tbl->rqt) {
1971                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
1972                                 dev->data->port_id);
1973                         rte_errno = errno;
1974                         goto error;
1975                 }
1976                 ind_tbl->queues_n = queues_n;
1977         }
1978         rte_atomic32_inc(&ind_tbl->refcnt);
1979         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
1980         return ind_tbl;
1981 error:
1982         for (j = 0; j < i; j++)
1983                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
1984         rte_free(ind_tbl);
1985         DEBUG("port %u cannot create indirection table", dev->data->port_id);
1986         return NULL;
1987 }
1988
1989 /**
1990  * Get an indirection table.
1991  *
1992  * @param dev
1993  *   Pointer to Ethernet device.
1994  * @param queues
1995  *   Queues entering in the indirection table.
1996  * @param queues_n
1997  *   Number of queues in the array.
1998  *
1999  * @return
2000  *   An indirection table if found.
2001  */
2002 static struct mlx5_ind_table_obj *
2003 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2004                        uint32_t queues_n)
2005 {
2006         struct mlx5_priv *priv = dev->data->dev_private;
2007         struct mlx5_ind_table_obj *ind_tbl;
2008
2009         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2010                 if ((ind_tbl->queues_n == queues_n) &&
2011                     (memcmp(ind_tbl->queues, queues,
2012                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2013                      == 0))
2014                         break;
2015         }
2016         if (ind_tbl) {
2017                 unsigned int i;
2018
2019                 rte_atomic32_inc(&ind_tbl->refcnt);
2020                 for (i = 0; i != ind_tbl->queues_n; ++i)
2021                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
2022         }
2023         return ind_tbl;
2024 }
2025
2026 /**
2027  * Release an indirection table.
2028  *
2029  * @param dev
2030  *   Pointer to Ethernet device.
2031  * @param ind_table
2032  *   Indirection table to release.
2033  *
2034  * @return
2035  *   1 while a reference on it exists, 0 when freed.
2036  */
2037 static int
2038 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2039                            struct mlx5_ind_table_obj *ind_tbl)
2040 {
2041         unsigned int i;
2042
2043         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2044                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2045                         claim_zero(mlx5_glue->destroy_rwq_ind_table
2046                                                         (ind_tbl->ind_table));
2047                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2048                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2049         }
2050         for (i = 0; i != ind_tbl->queues_n; ++i)
2051                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2052         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2053                 LIST_REMOVE(ind_tbl, next);
2054                 rte_free(ind_tbl);
2055                 return 0;
2056         }
2057         return 1;
2058 }
2059
2060 /**
2061  * Verify the Rx Queue list is empty
2062  *
2063  * @param dev
2064  *   Pointer to Ethernet device.
2065  *
2066  * @return
2067  *   The number of object not released.
2068  */
2069 int
2070 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2071 {
2072         struct mlx5_priv *priv = dev->data->dev_private;
2073         struct mlx5_ind_table_obj *ind_tbl;
2074         int ret = 0;
2075
2076         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2077                 DRV_LOG(DEBUG,
2078                         "port %u indirection table obj %p still referenced",
2079                         dev->data->port_id, (void *)ind_tbl);
2080                 ++ret;
2081         }
2082         return ret;
2083 }
2084
2085 /**
2086  * Create an Rx Hash queue.
2087  *
2088  * @param dev
2089  *   Pointer to Ethernet device.
2090  * @param rss_key
2091  *   RSS key for the Rx hash queue.
2092  * @param rss_key_len
2093  *   RSS key length.
2094  * @param hash_fields
2095  *   Verbs protocol hash field to make the RSS on.
2096  * @param queues
2097  *   Queues entering in hash queue. In case of empty hash_fields only the
2098  *   first queue index will be taken for the indirection table.
2099  * @param queues_n
2100  *   Number of queues.
2101  * @param tunnel
2102  *   Tunnel type.
2103  *
2104  * @return
2105  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2106  */
2107 struct mlx5_hrxq *
2108 mlx5_hrxq_new(struct rte_eth_dev *dev,
2109               const uint8_t *rss_key, uint32_t rss_key_len,
2110               uint64_t hash_fields,
2111               const uint16_t *queues, uint32_t queues_n,
2112               int tunnel __rte_unused)
2113 {
2114         struct mlx5_priv *priv = dev->data->dev_private;
2115         struct mlx5_hrxq *hrxq;
2116         struct ibv_qp *qp = NULL;
2117         struct mlx5_ind_table_obj *ind_tbl;
2118         int err;
2119         struct mlx5_devx_obj *tir = NULL;
2120
2121         queues_n = hash_fields ? queues_n : 1;
2122         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2123         if (!ind_tbl) {
2124                 struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2125                 struct mlx5_rxq_ctrl *rxq_ctrl =
2126                         container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2127                 enum mlx5_ind_tbl_type type;
2128
2129                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2130                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2131                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2132         }
2133         if (!ind_tbl) {
2134                 rte_errno = ENOMEM;
2135                 return NULL;
2136         }
2137         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2138 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2139                 struct mlx5dv_qp_init_attr qp_init_attr;
2140
2141                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2142                 if (tunnel) {
2143                         qp_init_attr.comp_mask =
2144                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2145                         qp_init_attr.create_flags =
2146                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2147                 }
2148 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2149                 if (dev->data->dev_conf.lpbk_mode) {
2150                         /*
2151                          * Allow packet sent from NIC loop back
2152                          * w/o source MAC check.
2153                          */
2154                         qp_init_attr.comp_mask |=
2155                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2156                         qp_init_attr.create_flags |=
2157                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2158                 }
2159 #endif
2160                 qp = mlx5_glue->dv_create_qp
2161                         (priv->sh->ctx,
2162                          &(struct ibv_qp_init_attr_ex){
2163                                 .qp_type = IBV_QPT_RAW_PACKET,
2164                                 .comp_mask =
2165                                         IBV_QP_INIT_ATTR_PD |
2166                                         IBV_QP_INIT_ATTR_IND_TABLE |
2167                                         IBV_QP_INIT_ATTR_RX_HASH,
2168                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2169                                         .rx_hash_function =
2170                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2171                                         .rx_hash_key_len = rss_key_len,
2172                                         .rx_hash_key =
2173                                                 (void *)(uintptr_t)rss_key,
2174                                         .rx_hash_fields_mask = hash_fields,
2175                                 },
2176                                 .rwq_ind_tbl = ind_tbl->ind_table,
2177                                 .pd = priv->sh->pd,
2178                           },
2179                           &qp_init_attr);
2180 #else
2181                 qp = mlx5_glue->create_qp_ex
2182                         (priv->sh->ctx,
2183                          &(struct ibv_qp_init_attr_ex){
2184                                 .qp_type = IBV_QPT_RAW_PACKET,
2185                                 .comp_mask =
2186                                         IBV_QP_INIT_ATTR_PD |
2187                                         IBV_QP_INIT_ATTR_IND_TABLE |
2188                                         IBV_QP_INIT_ATTR_RX_HASH,
2189                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2190                                         .rx_hash_function =
2191                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2192                                         .rx_hash_key_len = rss_key_len,
2193                                         .rx_hash_key =
2194                                                 (void *)(uintptr_t)rss_key,
2195                                         .rx_hash_fields_mask = hash_fields,
2196                                 },
2197                                 .rwq_ind_tbl = ind_tbl->ind_table,
2198                                 .pd = priv->sh->pd,
2199                          });
2200 #endif
2201                 if (!qp) {
2202                         rte_errno = errno;
2203                         goto error;
2204                 }
2205         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2206                 struct mlx5_devx_tir_attr tir_attr;
2207
2208                 memset(&tir_attr, 0, sizeof(tir_attr));
2209                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2210                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2211                 memcpy(&tir_attr.rx_hash_field_selector_outer, &hash_fields,
2212                        sizeof(uint64_t));
2213                 tir_attr.transport_domain = priv->sh->tdn;
2214                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key, rss_key_len);
2215                 tir_attr.indirect_table = ind_tbl->rqt->id;
2216                 if (dev->data->dev_conf.lpbk_mode)
2217                         tir_attr.self_lb_block =
2218                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2219                 if (mlx5_lro_on(dev)) {
2220                         tir_attr.lro_timeout_period_usecs =
2221                                         priv->config.lro.timeout;
2222                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2223                         tir_attr.lro_enable_mask =
2224                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2225                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2226                 }
2227                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2228                 if (!tir) {
2229                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2230                                 dev->data->port_id);
2231                         rte_errno = errno;
2232                         goto error;
2233                 }
2234         }
2235         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq) + rss_key_len, 0);
2236         if (!hrxq)
2237                 goto error;
2238         hrxq->ind_table = ind_tbl;
2239         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2240                 hrxq->qp = qp;
2241 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2242                 hrxq->action =
2243                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2244                 if (!hrxq->action) {
2245                         rte_errno = errno;
2246                         goto error;
2247                 }
2248 #endif
2249         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2250                 hrxq->tir = tir;
2251 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2252                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2253                                                         (hrxq->tir->obj);
2254                 if (!hrxq->action) {
2255                         rte_errno = errno;
2256                         goto error;
2257                 }
2258 #endif
2259         }
2260         hrxq->rss_key_len = rss_key_len;
2261         hrxq->hash_fields = hash_fields;
2262         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2263         rte_atomic32_inc(&hrxq->refcnt);
2264         LIST_INSERT_HEAD(&priv->hrxqs, hrxq, next);
2265         return hrxq;
2266 error:
2267         err = rte_errno; /* Save rte_errno before cleanup. */
2268         mlx5_ind_table_obj_release(dev, ind_tbl);
2269         if (qp)
2270                 claim_zero(mlx5_glue->destroy_qp(qp));
2271         else if (tir)
2272                 claim_zero(mlx5_devx_cmd_destroy(tir));
2273         rte_errno = err; /* Restore rte_errno. */
2274         return NULL;
2275 }
2276
2277 /**
2278  * Get an Rx Hash queue.
2279  *
2280  * @param dev
2281  *   Pointer to Ethernet device.
2282  * @param rss_conf
2283  *   RSS configuration for the Rx hash queue.
2284  * @param queues
2285  *   Queues entering in hash queue. In case of empty hash_fields only the
2286  *   first queue index will be taken for the indirection table.
2287  * @param queues_n
2288  *   Number of queues.
2289  *
2290  * @return
2291  *   An hash Rx queue on success.
2292  */
2293 struct mlx5_hrxq *
2294 mlx5_hrxq_get(struct rte_eth_dev *dev,
2295               const uint8_t *rss_key, uint32_t rss_key_len,
2296               uint64_t hash_fields,
2297               const uint16_t *queues, uint32_t queues_n)
2298 {
2299         struct mlx5_priv *priv = dev->data->dev_private;
2300         struct mlx5_hrxq *hrxq;
2301
2302         queues_n = hash_fields ? queues_n : 1;
2303         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2304                 struct mlx5_ind_table_obj *ind_tbl;
2305
2306                 if (hrxq->rss_key_len != rss_key_len)
2307                         continue;
2308                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2309                         continue;
2310                 if (hrxq->hash_fields != hash_fields)
2311                         continue;
2312                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2313                 if (!ind_tbl)
2314                         continue;
2315                 if (ind_tbl != hrxq->ind_table) {
2316                         mlx5_ind_table_obj_release(dev, ind_tbl);
2317                         continue;
2318                 }
2319                 rte_atomic32_inc(&hrxq->refcnt);
2320                 return hrxq;
2321         }
2322         return NULL;
2323 }
2324
2325 /**
2326  * Release the hash Rx queue.
2327  *
2328  * @param dev
2329  *   Pointer to Ethernet device.
2330  * @param hrxq
2331  *   Pointer to Hash Rx queue to release.
2332  *
2333  * @return
2334  *   1 while a reference on it exists, 0 when freed.
2335  */
2336 int
2337 mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq)
2338 {
2339         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2340 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2341                 mlx5_glue->destroy_flow_action(hrxq->action);
2342 #endif
2343                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2344                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2345                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2346                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2347                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2348                 LIST_REMOVE(hrxq, next);
2349                 rte_free(hrxq);
2350                 return 0;
2351         }
2352         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2353         return 1;
2354 }
2355
2356 /**
2357  * Verify the Rx Queue list is empty
2358  *
2359  * @param dev
2360  *   Pointer to Ethernet device.
2361  *
2362  * @return
2363  *   The number of object not released.
2364  */
2365 int
2366 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2367 {
2368         struct mlx5_priv *priv = dev->data->dev_private;
2369         struct mlx5_hrxq *hrxq;
2370         int ret = 0;
2371
2372         LIST_FOREACH(hrxq, &priv->hrxqs, next) {
2373                 DRV_LOG(DEBUG,
2374                         "port %u hash Rx queue %p still referenced",
2375                         dev->data->port_id, (void *)hrxq);
2376                 ++ret;
2377         }
2378         return ret;
2379 }
2380
2381 /**
2382  * Create a drop Rx queue Verbs/DevX object.
2383  *
2384  * @param dev
2385  *   Pointer to Ethernet device.
2386  *
2387  * @return
2388  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2389  */
2390 static struct mlx5_rxq_obj *
2391 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2392 {
2393         struct mlx5_priv *priv = dev->data->dev_private;
2394         struct ibv_context *ctx = priv->sh->ctx;
2395         struct ibv_cq *cq;
2396         struct ibv_wq *wq = NULL;
2397         struct mlx5_rxq_obj *rxq;
2398
2399         if (priv->drop_queue.rxq)
2400                 return priv->drop_queue.rxq;
2401         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2402         if (!cq) {
2403                 DEBUG("port %u cannot allocate CQ for drop queue",
2404                       dev->data->port_id);
2405                 rte_errno = errno;
2406                 goto error;
2407         }
2408         wq = mlx5_glue->create_wq(ctx,
2409                  &(struct ibv_wq_init_attr){
2410                         .wq_type = IBV_WQT_RQ,
2411                         .max_wr = 1,
2412                         .max_sge = 1,
2413                         .pd = priv->sh->pd,
2414                         .cq = cq,
2415                  });
2416         if (!wq) {
2417                 DEBUG("port %u cannot allocate WQ for drop queue",
2418                       dev->data->port_id);
2419                 rte_errno = errno;
2420                 goto error;
2421         }
2422         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2423         if (!rxq) {
2424                 DEBUG("port %u cannot allocate drop Rx queue memory",
2425                       dev->data->port_id);
2426                 rte_errno = ENOMEM;
2427                 goto error;
2428         }
2429         rxq->cq = cq;
2430         rxq->wq = wq;
2431         priv->drop_queue.rxq = rxq;
2432         return rxq;
2433 error:
2434         if (wq)
2435                 claim_zero(mlx5_glue->destroy_wq(wq));
2436         if (cq)
2437                 claim_zero(mlx5_glue->destroy_cq(cq));
2438         return NULL;
2439 }
2440
2441 /**
2442  * Release a drop Rx queue Verbs/DevX object.
2443  *
2444  * @param dev
2445  *   Pointer to Ethernet device.
2446  *
2447  * @return
2448  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2449  */
2450 static void
2451 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2452 {
2453         struct mlx5_priv *priv = dev->data->dev_private;
2454         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2455
2456         if (rxq->wq)
2457                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2458         if (rxq->cq)
2459                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2460         rte_free(rxq);
2461         priv->drop_queue.rxq = NULL;
2462 }
2463
2464 /**
2465  * Create a drop indirection table.
2466  *
2467  * @param dev
2468  *   Pointer to Ethernet device.
2469  *
2470  * @return
2471  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2472  */
2473 static struct mlx5_ind_table_obj *
2474 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2475 {
2476         struct mlx5_priv *priv = dev->data->dev_private;
2477         struct mlx5_ind_table_obj *ind_tbl;
2478         struct mlx5_rxq_obj *rxq;
2479         struct mlx5_ind_table_obj tmpl;
2480
2481         rxq = mlx5_rxq_obj_drop_new(dev);
2482         if (!rxq)
2483                 return NULL;
2484         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2485                 (priv->sh->ctx,
2486                  &(struct ibv_rwq_ind_table_init_attr){
2487                         .log_ind_tbl_size = 0,
2488                         .ind_tbl = &rxq->wq,
2489                         .comp_mask = 0,
2490                  });
2491         if (!tmpl.ind_table) {
2492                 DEBUG("port %u cannot allocate indirection table for drop"
2493                       " queue",
2494                       dev->data->port_id);
2495                 rte_errno = errno;
2496                 goto error;
2497         }
2498         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2499         if (!ind_tbl) {
2500                 rte_errno = ENOMEM;
2501                 goto error;
2502         }
2503         ind_tbl->ind_table = tmpl.ind_table;
2504         return ind_tbl;
2505 error:
2506         mlx5_rxq_obj_drop_release(dev);
2507         return NULL;
2508 }
2509
2510 /**
2511  * Release a drop indirection table.
2512  *
2513  * @param dev
2514  *   Pointer to Ethernet device.
2515  */
2516 static void
2517 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2518 {
2519         struct mlx5_priv *priv = dev->data->dev_private;
2520         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2521
2522         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2523         mlx5_rxq_obj_drop_release(dev);
2524         rte_free(ind_tbl);
2525         priv->drop_queue.hrxq->ind_table = NULL;
2526 }
2527
2528 /**
2529  * Create a drop Rx Hash queue.
2530  *
2531  * @param dev
2532  *   Pointer to Ethernet device.
2533  *
2534  * @return
2535  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2536  */
2537 struct mlx5_hrxq *
2538 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2539 {
2540         struct mlx5_priv *priv = dev->data->dev_private;
2541         struct mlx5_ind_table_obj *ind_tbl;
2542         struct ibv_qp *qp;
2543         struct mlx5_hrxq *hrxq;
2544
2545         if (priv->drop_queue.hrxq) {
2546                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2547                 return priv->drop_queue.hrxq;
2548         }
2549         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2550         if (!ind_tbl)
2551                 return NULL;
2552         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2553                  &(struct ibv_qp_init_attr_ex){
2554                         .qp_type = IBV_QPT_RAW_PACKET,
2555                         .comp_mask =
2556                                 IBV_QP_INIT_ATTR_PD |
2557                                 IBV_QP_INIT_ATTR_IND_TABLE |
2558                                 IBV_QP_INIT_ATTR_RX_HASH,
2559                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2560                                 .rx_hash_function =
2561                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2562                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2563                                 .rx_hash_key = rss_hash_default_key,
2564                                 .rx_hash_fields_mask = 0,
2565                                 },
2566                         .rwq_ind_tbl = ind_tbl->ind_table,
2567                         .pd = priv->sh->pd
2568                  });
2569         if (!qp) {
2570                 DEBUG("port %u cannot allocate QP for drop queue",
2571                       dev->data->port_id);
2572                 rte_errno = errno;
2573                 goto error;
2574         }
2575         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2576         if (!hrxq) {
2577                 DRV_LOG(WARNING,
2578                         "port %u cannot allocate memory for drop queue",
2579                         dev->data->port_id);
2580                 rte_errno = ENOMEM;
2581                 goto error;
2582         }
2583         hrxq->ind_table = ind_tbl;
2584         hrxq->qp = qp;
2585 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2586         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2587         if (!hrxq->action) {
2588                 rte_errno = errno;
2589                 goto error;
2590         }
2591 #endif
2592         priv->drop_queue.hrxq = hrxq;
2593         rte_atomic32_set(&hrxq->refcnt, 1);
2594         return hrxq;
2595 error:
2596         if (ind_tbl)
2597                 mlx5_ind_table_obj_drop_release(dev);
2598         return NULL;
2599 }
2600
2601 /**
2602  * Release a drop hash Rx queue.
2603  *
2604  * @param dev
2605  *   Pointer to Ethernet device.
2606  */
2607 void
2608 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2609 {
2610         struct mlx5_priv *priv = dev->data->dev_private;
2611         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2612
2613         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2614 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2615                 mlx5_glue->destroy_flow_action(hrxq->action);
2616 #endif
2617                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2618                 mlx5_ind_table_obj_drop_release(dev);
2619                 rte_free(hrxq);
2620                 priv->drop_queue.hrxq = NULL;
2621         }
2622 }