4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-pedantic"
45 #include <infiniband/verbs.h>
47 #pragma GCC diagnostic error "-pedantic"
50 /* DPDK headers don't like -pedantic. */
52 #pragma GCC diagnostic ignored "-pedantic"
55 #include <rte_malloc.h>
56 #include <rte_ethdev.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-pedantic"
63 #include "mlx5_rxtx.h"
64 #include "mlx5_utils.h"
65 #include "mlx5_autoconf.h"
66 #include "mlx5_defs.h"
68 /* Initialization data for hash RX queues. */
69 const struct hash_rxq_init hash_rxq_init[] = {
71 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV4 |
72 IBV_EXP_RX_HASH_DST_IPV4 |
73 IBV_EXP_RX_HASH_SRC_PORT_TCP |
74 IBV_EXP_RX_HASH_DST_PORT_TCP),
75 .dpdk_rss_hf = ETH_RSS_NONFRAG_IPV4_TCP,
77 .flow_spec.tcp_udp = {
78 .type = IBV_EXP_FLOW_SPEC_TCP,
79 .size = sizeof(hash_rxq_init[0].flow_spec.tcp_udp),
81 .underlayer = &hash_rxq_init[HASH_RXQ_IPV4],
84 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV4 |
85 IBV_EXP_RX_HASH_DST_IPV4 |
86 IBV_EXP_RX_HASH_SRC_PORT_UDP |
87 IBV_EXP_RX_HASH_DST_PORT_UDP),
88 .dpdk_rss_hf = ETH_RSS_NONFRAG_IPV4_UDP,
90 .flow_spec.tcp_udp = {
91 .type = IBV_EXP_FLOW_SPEC_UDP,
92 .size = sizeof(hash_rxq_init[0].flow_spec.tcp_udp),
94 .underlayer = &hash_rxq_init[HASH_RXQ_IPV4],
97 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV4 |
98 IBV_EXP_RX_HASH_DST_IPV4),
99 .dpdk_rss_hf = (ETH_RSS_IPV4 |
103 .type = IBV_EXP_FLOW_SPEC_IPV4,
104 .size = sizeof(hash_rxq_init[0].flow_spec.ipv4),
106 .underlayer = &hash_rxq_init[HASH_RXQ_ETH],
108 #ifdef HAVE_FLOW_SPEC_IPV6
110 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV6 |
111 IBV_EXP_RX_HASH_DST_IPV6 |
112 IBV_EXP_RX_HASH_SRC_PORT_TCP |
113 IBV_EXP_RX_HASH_DST_PORT_TCP),
114 .dpdk_rss_hf = ETH_RSS_NONFRAG_IPV6_TCP,
116 .flow_spec.tcp_udp = {
117 .type = IBV_EXP_FLOW_SPEC_TCP,
118 .size = sizeof(hash_rxq_init[0].flow_spec.tcp_udp),
120 .underlayer = &hash_rxq_init[HASH_RXQ_IPV6],
123 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV6 |
124 IBV_EXP_RX_HASH_DST_IPV6 |
125 IBV_EXP_RX_HASH_SRC_PORT_UDP |
126 IBV_EXP_RX_HASH_DST_PORT_UDP),
127 .dpdk_rss_hf = ETH_RSS_NONFRAG_IPV6_UDP,
129 .flow_spec.tcp_udp = {
130 .type = IBV_EXP_FLOW_SPEC_UDP,
131 .size = sizeof(hash_rxq_init[0].flow_spec.tcp_udp),
133 .underlayer = &hash_rxq_init[HASH_RXQ_IPV6],
136 .hash_fields = (IBV_EXP_RX_HASH_SRC_IPV6 |
137 IBV_EXP_RX_HASH_DST_IPV6),
138 .dpdk_rss_hf = (ETH_RSS_IPV6 |
142 .type = IBV_EXP_FLOW_SPEC_IPV6,
143 .size = sizeof(hash_rxq_init[0].flow_spec.ipv6),
145 .underlayer = &hash_rxq_init[HASH_RXQ_ETH],
147 #endif /* HAVE_FLOW_SPEC_IPV6 */
153 .type = IBV_EXP_FLOW_SPEC_ETH,
154 .size = sizeof(hash_rxq_init[0].flow_spec.eth),
160 /* Number of entries in hash_rxq_init[]. */
161 const unsigned int hash_rxq_init_n = RTE_DIM(hash_rxq_init);
163 /* Initialization data for hash RX queue indirection tables. */
164 static const struct ind_table_init ind_table_init[] = {
166 .max_size = -1u, /* Superseded by HW limitations. */
168 1 << HASH_RXQ_TCPV4 |
169 1 << HASH_RXQ_UDPV4 |
171 #ifdef HAVE_FLOW_SPEC_IPV6
172 1 << HASH_RXQ_TCPV6 |
173 1 << HASH_RXQ_UDPV6 |
175 #endif /* HAVE_FLOW_SPEC_IPV6 */
177 #ifdef HAVE_FLOW_SPEC_IPV6
179 #else /* HAVE_FLOW_SPEC_IPV6 */
181 #endif /* HAVE_FLOW_SPEC_IPV6 */
185 .hash_types = 1 << HASH_RXQ_ETH,
190 #define IND_TABLE_INIT_N RTE_DIM(ind_table_init)
192 /* Default RSS hash key also used for ConnectX-3. */
193 uint8_t rss_hash_default_key[] = {
194 0x2c, 0xc6, 0x81, 0xd1,
195 0x5b, 0xdb, 0xf4, 0xf7,
196 0xfc, 0xa2, 0x83, 0x19,
197 0xdb, 0x1a, 0x3e, 0x94,
198 0x6b, 0x9e, 0x38, 0xd9,
199 0x2c, 0x9c, 0x03, 0xd1,
200 0xad, 0x99, 0x44, 0xa7,
201 0xd9, 0x56, 0x3d, 0x59,
202 0x06, 0x3c, 0x25, 0xf3,
203 0xfc, 0x1f, 0xdc, 0x2a,
206 /* Length of the default RSS hash key. */
207 const size_t rss_hash_default_key_len = sizeof(rss_hash_default_key);
210 * Populate flow steering rule for a given hash RX queue type using
211 * information from hash_rxq_init[]. Nothing is written to flow_attr when
212 * flow_attr_size is not large enough, but the required size is still returned.
215 * Pointer to private structure.
216 * @param[out] flow_attr
217 * Pointer to flow attribute structure to fill. Note that the allocated
218 * area must be larger and large enough to hold all flow specifications.
219 * @param flow_attr_size
220 * Entire size of flow_attr and trailing room for flow specifications.
222 * Hash RX queue type to use for flow steering rule.
225 * Total size of the flow attribute buffer. No errors are defined.
228 priv_flow_attr(struct priv *priv, struct ibv_exp_flow_attr *flow_attr,
229 size_t flow_attr_size, enum hash_rxq_type type)
231 size_t offset = sizeof(*flow_attr);
232 const struct hash_rxq_init *init = &hash_rxq_init[type];
234 assert(priv != NULL);
235 assert((size_t)type < RTE_DIM(hash_rxq_init));
237 offset += init->flow_spec.hdr.size;
238 init = init->underlayer;
239 } while (init != NULL);
240 if (offset > flow_attr_size)
242 flow_attr_size = offset;
243 init = &hash_rxq_init[type];
244 *flow_attr = (struct ibv_exp_flow_attr){
245 .type = IBV_EXP_FLOW_ATTR_NORMAL,
246 #ifdef MLX5_FDIR_SUPPORT
247 /* Priorities < 3 are reserved for flow director. */
248 .priority = init->flow_priority + 3,
249 #else /* MLX5_FDIR_SUPPORT */
250 .priority = init->flow_priority,
251 #endif /* MLX5_FDIR_SUPPORT */
257 offset -= init->flow_spec.hdr.size;
258 memcpy((void *)((uintptr_t)flow_attr + offset),
260 init->flow_spec.hdr.size);
261 ++flow_attr->num_of_specs;
262 init = init->underlayer;
263 } while (init != NULL);
264 return flow_attr_size;
268 * Convert hash type position in indirection table initializer to
269 * hash RX queue type.
272 * Indirection table initializer.
274 * Hash type position.
277 * Hash RX queue type.
279 static enum hash_rxq_type
280 hash_rxq_type_from_pos(const struct ind_table_init *table, unsigned int pos)
282 enum hash_rxq_type type = 0;
284 assert(pos < table->hash_types_n);
286 if ((table->hash_types & (1 << type)) && (pos-- == 0))
294 * Filter out disabled hash RX queue types from ind_table_init[].
297 * Pointer to private structure.
302 * Number of table entries.
305 priv_make_ind_table_init(struct priv *priv,
306 struct ind_table_init (*table)[IND_TABLE_INIT_N])
311 unsigned int table_n = 0;
312 /* Mandatory to receive frames not handled by normal hash RX queues. */
313 unsigned int hash_types_sup = 1 << HASH_RXQ_ETH;
315 rss_hf = priv->rss_hf;
316 /* Process other protocols only if more than one queue. */
317 if (priv->rxqs_n > 1)
318 for (i = 0; (i != hash_rxq_init_n); ++i)
319 if (rss_hf & hash_rxq_init[i].dpdk_rss_hf)
320 hash_types_sup |= (1 << i);
322 /* Filter out entries whose protocols are not in the set. */
323 for (i = 0, j = 0; (i != IND_TABLE_INIT_N); ++i) {
327 /* j is increased only if the table has valid protocols. */
329 (*table)[j] = ind_table_init[i];
330 (*table)[j].hash_types &= hash_types_sup;
331 for (h = 0, nb = 0; (h != hash_rxq_init_n); ++h)
332 if (((*table)[j].hash_types >> h) & 0x1)
334 (*table)[i].hash_types_n = nb;
344 * Initialize hash RX queues and indirection table.
347 * Pointer to private structure.
350 * 0 on success, errno value on failure.
353 priv_create_hash_rxqs(struct priv *priv)
355 struct ibv_exp_wq *wqs[priv->reta_idx_n];
356 struct ind_table_init ind_table_init[IND_TABLE_INIT_N];
357 unsigned int ind_tables_n =
358 priv_make_ind_table_init(priv, &ind_table_init);
359 unsigned int hash_rxqs_n = 0;
360 struct hash_rxq (*hash_rxqs)[] = NULL;
361 struct ibv_exp_rwq_ind_table *(*ind_tables)[] = NULL;
367 assert(priv->ind_tables == NULL);
368 assert(priv->ind_tables_n == 0);
369 assert(priv->hash_rxqs == NULL);
370 assert(priv->hash_rxqs_n == 0);
371 assert(priv->pd != NULL);
372 assert(priv->ctx != NULL);
373 if (priv->rxqs_n == 0)
375 assert(priv->rxqs != NULL);
376 if (ind_tables_n == 0) {
377 ERROR("all hash RX queue types have been filtered out,"
378 " indirection table cannot be created");
381 if (priv->rxqs_n & (priv->rxqs_n - 1)) {
382 INFO("%u RX queues are configured, consider rounding this"
383 " number to the next power of two for better balancing",
385 DEBUG("indirection table extended to assume %u WQs",
388 for (i = 0; (i != priv->reta_idx_n); ++i)
389 wqs[i] = (*priv->rxqs)[(*priv->reta_idx)[i]]->wq;
390 /* Get number of hash RX queues to configure. */
391 for (i = 0, hash_rxqs_n = 0; (i != ind_tables_n); ++i)
392 hash_rxqs_n += ind_table_init[i].hash_types_n;
393 DEBUG("allocating %u hash RX queues for %u WQs, %u indirection tables",
394 hash_rxqs_n, priv->rxqs_n, ind_tables_n);
395 /* Create indirection tables. */
396 ind_tables = rte_calloc(__func__, ind_tables_n,
397 sizeof((*ind_tables)[0]), 0);
398 if (ind_tables == NULL) {
400 ERROR("cannot allocate indirection tables container: %s",
404 for (i = 0; (i != ind_tables_n); ++i) {
405 struct ibv_exp_rwq_ind_table_init_attr ind_init_attr = {
407 .log_ind_tbl_size = 0, /* Set below. */
411 unsigned int ind_tbl_size = ind_table_init[i].max_size;
412 struct ibv_exp_rwq_ind_table *ind_table;
414 if (priv->reta_idx_n < ind_tbl_size)
415 ind_tbl_size = priv->reta_idx_n;
416 ind_init_attr.log_ind_tbl_size = log2above(ind_tbl_size);
418 ind_table = ibv_exp_create_rwq_ind_table(priv->ctx,
420 if (ind_table != NULL) {
421 (*ind_tables)[i] = ind_table;
424 /* Not clear whether errno is set. */
425 err = (errno ? errno : EINVAL);
426 ERROR("RX indirection table creation failed with error %d: %s",
430 /* Allocate array that holds hash RX queues and related data. */
431 hash_rxqs = rte_calloc(__func__, hash_rxqs_n,
432 sizeof((*hash_rxqs)[0]), 0);
433 if (hash_rxqs == NULL) {
435 ERROR("cannot allocate hash RX queues container: %s",
439 for (i = 0, j = 0, k = 0;
440 ((i != hash_rxqs_n) && (j != ind_tables_n));
442 struct hash_rxq *hash_rxq = &(*hash_rxqs)[i];
443 enum hash_rxq_type type =
444 hash_rxq_type_from_pos(&ind_table_init[j], k);
445 struct rte_eth_rss_conf *priv_rss_conf =
446 (*priv->rss_conf)[type];
447 struct ibv_exp_rx_hash_conf hash_conf = {
448 .rx_hash_function = IBV_EXP_RX_HASH_FUNC_TOEPLITZ,
449 .rx_hash_key_len = (priv_rss_conf ?
450 priv_rss_conf->rss_key_len :
451 rss_hash_default_key_len),
452 .rx_hash_key = (priv_rss_conf ?
453 priv_rss_conf->rss_key :
454 rss_hash_default_key),
455 .rx_hash_fields_mask = hash_rxq_init[type].hash_fields,
456 .rwq_ind_tbl = (*ind_tables)[j],
458 struct ibv_exp_qp_init_attr qp_init_attr = {
459 .max_inl_recv = 0, /* Currently not supported. */
460 .qp_type = IBV_QPT_RAW_PACKET,
461 .comp_mask = (IBV_EXP_QP_INIT_ATTR_PD |
462 IBV_EXP_QP_INIT_ATTR_RX_HASH),
464 .rx_hash_conf = &hash_conf,
465 .port_num = priv->port,
468 DEBUG("using indirection table %u for hash RX queue %u type %d",
470 *hash_rxq = (struct hash_rxq){
472 .qp = ibv_exp_create_qp(priv->ctx, &qp_init_attr),
475 if (hash_rxq->qp == NULL) {
476 err = (errno ? errno : EINVAL);
477 ERROR("Hash RX QP creation failure: %s",
481 if (++k < ind_table_init[j].hash_types_n)
483 /* Switch to the next indirection table and reset hash RX
484 * queue type array index. */
488 priv->ind_tables = ind_tables;
489 priv->ind_tables_n = ind_tables_n;
490 priv->hash_rxqs = hash_rxqs;
491 priv->hash_rxqs_n = hash_rxqs_n;
495 if (hash_rxqs != NULL) {
496 for (i = 0; (i != hash_rxqs_n); ++i) {
497 struct ibv_qp *qp = (*hash_rxqs)[i].qp;
501 claim_zero(ibv_destroy_qp(qp));
505 if (ind_tables != NULL) {
506 for (j = 0; (j != ind_tables_n); ++j) {
507 struct ibv_exp_rwq_ind_table *ind_table =
510 if (ind_table == NULL)
512 claim_zero(ibv_exp_destroy_rwq_ind_table(ind_table));
514 rte_free(ind_tables);
520 * Clean up hash RX queues and indirection table.
523 * Pointer to private structure.
526 priv_destroy_hash_rxqs(struct priv *priv)
530 DEBUG("destroying %u hash RX queues", priv->hash_rxqs_n);
531 if (priv->hash_rxqs_n == 0) {
532 assert(priv->hash_rxqs == NULL);
533 assert(priv->ind_tables == NULL);
536 for (i = 0; (i != priv->hash_rxqs_n); ++i) {
537 struct hash_rxq *hash_rxq = &(*priv->hash_rxqs)[i];
540 assert(hash_rxq->priv == priv);
541 assert(hash_rxq->qp != NULL);
542 /* Also check that there are no remaining flows. */
543 for (j = 0; (j != RTE_DIM(hash_rxq->special_flow)); ++j)
545 (k != RTE_DIM(hash_rxq->special_flow[j]));
547 assert(hash_rxq->special_flow[j][k] == NULL);
548 for (j = 0; (j != RTE_DIM(hash_rxq->mac_flow)); ++j)
549 for (k = 0; (k != RTE_DIM(hash_rxq->mac_flow[j])); ++k)
550 assert(hash_rxq->mac_flow[j][k] == NULL);
551 claim_zero(ibv_destroy_qp(hash_rxq->qp));
553 priv->hash_rxqs_n = 0;
554 rte_free(priv->hash_rxqs);
555 priv->hash_rxqs = NULL;
556 for (i = 0; (i != priv->ind_tables_n); ++i) {
557 struct ibv_exp_rwq_ind_table *ind_table =
558 (*priv->ind_tables)[i];
560 assert(ind_table != NULL);
561 claim_zero(ibv_exp_destroy_rwq_ind_table(ind_table));
563 priv->ind_tables_n = 0;
564 rte_free(priv->ind_tables);
565 priv->ind_tables = NULL;
569 * Check whether a given flow type is allowed.
572 * Pointer to private structure.
574 * Flow type to check.
577 * Nonzero if the given flow type is allowed.
580 priv_allow_flow_type(struct priv *priv, enum hash_rxq_flow_type type)
582 /* Only FLOW_TYPE_PROMISC is allowed when promiscuous mode
583 * has been requested. */
584 if (priv->promisc_req)
585 return type == HASH_RXQ_FLOW_TYPE_PROMISC;
587 case HASH_RXQ_FLOW_TYPE_PROMISC:
588 return !!priv->promisc_req;
589 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
590 return !!priv->allmulti_req;
591 case HASH_RXQ_FLOW_TYPE_BROADCAST:
592 #ifdef HAVE_FLOW_SPEC_IPV6
593 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
594 #endif /* HAVE_FLOW_SPEC_IPV6 */
595 /* If allmulti is enabled, broadcast and ipv6multi
596 * are unnecessary. */
597 return !priv->allmulti_req;
598 case HASH_RXQ_FLOW_TYPE_MAC:
601 /* Unsupported flow type is not allowed. */
608 * Automatically enable/disable flows according to configuration.
614 * 0 on success, errno value on failure.
617 priv_rehash_flows(struct priv *priv)
621 for (i = 0; (i != RTE_DIM((*priv->hash_rxqs)[0].special_flow)); ++i)
622 if (!priv_allow_flow_type(priv, i)) {
623 priv_special_flow_disable(priv, i);
625 int ret = priv_special_flow_enable(priv, i);
630 if (priv_allow_flow_type(priv, HASH_RXQ_FLOW_TYPE_MAC))
631 return priv_mac_addrs_enable(priv);
632 priv_mac_addrs_disable(priv);
637 * Allocate RX queue elements.
640 * Pointer to RX queue structure.
642 * Number of elements to allocate.
644 * If not NULL, fetch buffers from this array instead of allocating them
645 * with rte_pktmbuf_alloc().
648 * 0 on success, errno value on failure.
651 rxq_alloc_elts(struct rxq_ctrl *rxq_ctrl, unsigned int elts_n,
652 struct rte_mbuf **pool)
655 struct rxq_elt (*elts)[elts_n] =
656 rte_calloc_socket("RXQ elements", 1, sizeof(*elts), 0,
661 ERROR("%p: can't allocate packets array", (void *)rxq_ctrl);
665 /* For each WR (packet). */
666 for (i = 0; (i != elts_n); ++i) {
667 struct rxq_elt *elt = &(*elts)[i];
668 struct ibv_sge *sge = &(*elts)[i].sge;
669 struct rte_mbuf *buf;
674 rte_pktmbuf_reset(buf);
676 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
678 assert(pool == NULL);
679 ERROR("%p: empty mbuf pool", (void *)rxq_ctrl);
684 /* Headroom is reserved by rte_pktmbuf_alloc(). */
685 assert(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
686 /* Buffer is supposed to be empty. */
687 assert(rte_pktmbuf_data_len(buf) == 0);
688 assert(rte_pktmbuf_pkt_len(buf) == 0);
689 /* sge->addr must be able to store a pointer. */
690 assert(sizeof(sge->addr) >= sizeof(uintptr_t));
691 /* SGE keeps its headroom. */
692 sge->addr = (uintptr_t)
693 ((uint8_t *)buf->buf_addr + RTE_PKTMBUF_HEADROOM);
694 sge->length = (buf->buf_len - RTE_PKTMBUF_HEADROOM);
695 sge->lkey = rxq_ctrl->mr->lkey;
696 /* Redundant check for tailroom. */
697 assert(sge->length == rte_pktmbuf_tailroom(buf));
699 DEBUG("%p: allocated and configured %u single-segment WRs",
700 (void *)rxq_ctrl, elts_n);
701 rxq_ctrl->rxq.elts_n = elts_n;
702 rxq_ctrl->rxq.elts_head = 0;
703 rxq_ctrl->rxq.elts = elts;
708 assert(pool == NULL);
709 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
710 struct rxq_elt *elt = &(*elts)[i];
711 struct rte_mbuf *buf = elt->buf;
714 rte_pktmbuf_free_seg(buf);
718 DEBUG("%p: failed, freed everything", (void *)rxq_ctrl);
724 * Free RX queue elements.
727 * Pointer to RX queue structure.
730 rxq_free_elts(struct rxq_ctrl *rxq_ctrl)
733 unsigned int elts_n = rxq_ctrl->rxq.elts_n;
734 struct rxq_elt (*elts)[elts_n] = rxq_ctrl->rxq.elts;
736 DEBUG("%p: freeing WRs", (void *)rxq_ctrl);
737 rxq_ctrl->rxq.elts_n = 0;
738 rxq_ctrl->rxq.elts = NULL;
741 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
742 struct rxq_elt *elt = &(*elts)[i];
743 struct rte_mbuf *buf = elt->buf;
746 rte_pktmbuf_free_seg(buf);
752 * Clean up a RX queue.
754 * Destroy objects, free allocated memory and reset the structure for reuse.
757 * Pointer to RX queue structure.
760 rxq_cleanup(struct rxq_ctrl *rxq_ctrl)
762 struct ibv_exp_release_intf_params params;
764 DEBUG("cleaning up %p", (void *)rxq_ctrl);
765 rxq_free_elts(rxq_ctrl);
766 rxq_ctrl->rxq.poll = NULL;
767 rxq_ctrl->rxq.recv = NULL;
768 if (rxq_ctrl->if_wq != NULL) {
769 assert(rxq_ctrl->rxq.priv != NULL);
770 assert(rxq_ctrl->rxq.priv->ctx != NULL);
771 assert(rxq_ctrl->rxq.wq != NULL);
772 params = (struct ibv_exp_release_intf_params){
775 claim_zero(ibv_exp_release_intf(rxq_ctrl->rxq.priv->ctx,
779 if (rxq_ctrl->if_cq != NULL) {
780 assert(rxq_ctrl->rxq.priv != NULL);
781 assert(rxq_ctrl->rxq.priv->ctx != NULL);
782 assert(rxq_ctrl->rxq.cq != NULL);
783 params = (struct ibv_exp_release_intf_params){
786 claim_zero(ibv_exp_release_intf(rxq_ctrl->rxq.priv->ctx,
790 if (rxq_ctrl->rxq.wq != NULL)
791 claim_zero(ibv_exp_destroy_wq(rxq_ctrl->rxq.wq));
792 if (rxq_ctrl->rxq.cq != NULL)
793 claim_zero(ibv_destroy_cq(rxq_ctrl->rxq.cq));
794 if (rxq_ctrl->rd != NULL) {
795 struct ibv_exp_destroy_res_domain_attr attr = {
799 assert(rxq_ctrl->rxq.priv != NULL);
800 assert(rxq_ctrl->rxq.priv->ctx != NULL);
801 claim_zero(ibv_exp_destroy_res_domain(rxq_ctrl->rxq.priv->ctx,
805 if (rxq_ctrl->mr != NULL)
806 claim_zero(ibv_dereg_mr(rxq_ctrl->mr));
807 memset(rxq_ctrl, 0, sizeof(*rxq_ctrl));
811 * Reconfigure a RX queue with new parameters.
813 * rxq_rehash() does not allocate mbufs, which, if not done from the right
814 * thread (such as a control thread), may corrupt the pool.
815 * In case of failure, the queue is left untouched.
818 * Pointer to Ethernet device structure.
823 * 0 on success, errno value on failure.
826 rxq_rehash(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl)
828 struct priv *priv = rxq_ctrl->rxq.priv;
829 struct rxq_ctrl tmpl = *rxq_ctrl;
832 struct rte_mbuf **pool;
834 struct ibv_exp_wq_attr mod;
835 struct rxq_elt (*elts)[tmpl.rxq.elts_n];
838 DEBUG("%p: rehashing queue %p", (void *)dev, (void *)rxq_ctrl);
839 /* Number of descriptors and mbufs currently allocated. */
840 desc_n = tmpl.rxq.elts_n;
842 /* Toggle RX checksum offload if hardware supports it. */
844 tmpl.rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
845 rxq_ctrl->rxq.csum = tmpl.rxq.csum;
847 if (priv->hw_csum_l2tun) {
848 tmpl.rxq.csum_l2tun =
849 !!dev->data->dev_conf.rxmode.hw_ip_checksum;
850 rxq_ctrl->rxq.csum_l2tun = tmpl.rxq.csum_l2tun;
852 /* From now on, any failure will render the queue unusable.
853 * Reinitialize WQ. */
854 mod = (struct ibv_exp_wq_attr){
855 .attr_mask = IBV_EXP_WQ_ATTR_STATE,
856 .wq_state = IBV_EXP_WQS_RESET,
858 err = ibv_exp_modify_wq(tmpl.rxq.wq, &mod);
860 ERROR("%p: cannot reset WQ: %s", (void *)dev, strerror(err));
865 pool = rte_malloc(__func__, (mbuf_n * sizeof(*pool)), 0);
867 ERROR("%p: cannot allocate memory", (void *)dev);
870 /* Snatch mbufs from original queue. */
872 elts = rxq_ctrl->rxq.elts;
873 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
874 struct rxq_elt *elt = &(*elts)[i];
875 struct rte_mbuf *buf = elt->buf;
881 tmpl.rxq.elts = NULL;
882 assert((void *)&tmpl.rxq.elts == NULL);
883 err = rxq_alloc_elts(&tmpl, desc_n, pool);
885 ERROR("%p: cannot reallocate WRs, aborting", (void *)dev);
890 assert(tmpl.rxq.elts_n == desc_n);
892 /* Clean up original data. */
893 rxq_ctrl->rxq.elts_n = 0;
894 rte_free(rxq_ctrl->rxq.elts);
895 rxq_ctrl->rxq.elts = NULL;
896 /* Change queue state to ready. */
897 mod = (struct ibv_exp_wq_attr){
898 .attr_mask = IBV_EXP_WQ_ATTR_STATE,
899 .wq_state = IBV_EXP_WQS_RDY,
901 err = ibv_exp_modify_wq(tmpl.rxq.wq, &mod);
903 ERROR("%p: WQ state to IBV_EXP_WQS_RDY failed: %s",
904 (void *)dev, strerror(err));
908 assert(tmpl.if_wq != NULL);
909 elts = tmpl.rxq.elts;
910 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
911 err = tmpl.if_wq->recv_burst(
919 ERROR("%p: failed to post SGEs with error %d",
921 /* Set err because it does not contain a valid errno value. */
925 tmpl.rxq.recv = tmpl.if_wq->recv_burst;
933 * Configure a RX queue.
936 * Pointer to Ethernet device structure.
938 * Pointer to RX queue structure.
940 * Number of descriptors to configure in queue.
942 * NUMA socket on which memory must be allocated.
944 * Thresholds parameters.
946 * Memory pool for buffer allocations.
949 * 0 on success, errno value on failure.
952 rxq_setup(struct rte_eth_dev *dev, struct rxq_ctrl *rxq_ctrl, uint16_t desc,
953 unsigned int socket, const struct rte_eth_rxconf *conf,
954 struct rte_mempool *mp)
956 struct priv *priv = dev->data->dev_private;
957 struct rxq_ctrl tmpl = {
964 struct ibv_exp_wq_attr mod;
966 struct ibv_exp_query_intf_params params;
967 struct ibv_exp_cq_init_attr cq;
968 struct ibv_exp_res_domain_init_attr rd;
969 struct ibv_exp_wq_init_attr wq;
971 enum ibv_exp_query_intf_status status;
972 unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
973 struct rxq_elt (*elts)[desc];
976 unsigned int cq_size = desc;
978 (void)conf; /* Thresholds configuration (ignored). */
980 ERROR("%p: invalid number of RX descriptors", (void *)dev);
983 /* Toggle RX checksum offload if hardware supports it. */
985 tmpl.rxq.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
986 if (priv->hw_csum_l2tun)
987 tmpl.rxq.csum_l2tun =
988 !!dev->data->dev_conf.rxmode.hw_ip_checksum;
989 (void)mb_len; /* I'll be back! */
990 /* Use the entire RX mempool as the memory region. */
991 tmpl.mr = mlx5_mp2mr(priv->pd, mp);
992 if (tmpl.mr == NULL) {
994 ERROR("%p: MR creation failure: %s",
995 (void *)dev, strerror(ret));
998 attr.rd = (struct ibv_exp_res_domain_init_attr){
999 .comp_mask = (IBV_EXP_RES_DOMAIN_THREAD_MODEL |
1000 IBV_EXP_RES_DOMAIN_MSG_MODEL),
1001 .thread_model = IBV_EXP_THREAD_SINGLE,
1002 .msg_model = IBV_EXP_MSG_HIGH_BW,
1004 tmpl.rd = ibv_exp_create_res_domain(priv->ctx, &attr.rd);
1005 if (tmpl.rd == NULL) {
1007 ERROR("%p: RD creation failure: %s",
1008 (void *)dev, strerror(ret));
1011 attr.cq = (struct ibv_exp_cq_init_attr){
1012 .comp_mask = IBV_EXP_CQ_INIT_ATTR_RES_DOMAIN,
1013 .res_domain = tmpl.rd,
1015 tmpl.rxq.cq = ibv_exp_create_cq(priv->ctx, cq_size, NULL, NULL, 0,
1017 if (tmpl.rxq.cq == NULL) {
1019 ERROR("%p: CQ creation failure: %s",
1020 (void *)dev, strerror(ret));
1023 DEBUG("priv->device_attr.max_qp_wr is %d",
1024 priv->device_attr.max_qp_wr);
1025 DEBUG("priv->device_attr.max_sge is %d",
1026 priv->device_attr.max_sge);
1027 /* Configure VLAN stripping. */
1028 tmpl.rxq.vlan_strip = (priv->hw_vlan_strip &&
1029 !!dev->data->dev_conf.rxmode.hw_vlan_strip);
1030 attr.wq = (struct ibv_exp_wq_init_attr){
1031 .wq_context = NULL, /* Could be useful in the future. */
1032 .wq_type = IBV_EXP_WQT_RQ,
1033 /* Max number of outstanding WRs. */
1034 .max_recv_wr = ((priv->device_attr.max_qp_wr < (int)cq_size) ?
1035 priv->device_attr.max_qp_wr :
1037 /* Max number of scatter/gather elements in a WR. */
1042 IBV_EXP_CREATE_WQ_RES_DOMAIN |
1043 #ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS
1044 IBV_EXP_CREATE_WQ_VLAN_OFFLOADS |
1045 #endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */
1047 .res_domain = tmpl.rd,
1048 #ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS
1049 .vlan_offloads = (tmpl.rxq.vlan_strip ?
1050 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP :
1052 #endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */
1055 #ifdef HAVE_VERBS_FCS
1056 /* By default, FCS (CRC) is stripped by hardware. */
1057 if (dev->data->dev_conf.rxmode.hw_strip_crc) {
1058 tmpl.rxq.crc_present = 0;
1059 } else if (priv->hw_fcs_strip) {
1060 /* Ask HW/Verbs to leave CRC in place when supported. */
1061 attr.wq.flags |= IBV_EXP_CREATE_WQ_FLAG_SCATTER_FCS;
1062 attr.wq.comp_mask |= IBV_EXP_CREATE_WQ_FLAGS;
1063 tmpl.rxq.crc_present = 1;
1065 WARN("%p: CRC stripping has been disabled but will still"
1066 " be performed by hardware, make sure MLNX_OFED and"
1067 " firmware are up to date",
1069 tmpl.rxq.crc_present = 0;
1071 DEBUG("%p: CRC stripping is %s, %u bytes will be subtracted from"
1072 " incoming frames to hide it",
1074 tmpl.rxq.crc_present ? "disabled" : "enabled",
1075 tmpl.rxq.crc_present << 2);
1076 #endif /* HAVE_VERBS_FCS */
1078 #ifdef HAVE_VERBS_RX_END_PADDING
1079 if (!mlx5_getenv_int("MLX5_PMD_ENABLE_PADDING"))
1080 ; /* Nothing else to do. */
1081 else if (priv->hw_padding) {
1082 INFO("%p: enabling packet padding on queue %p",
1083 (void *)dev, (void *)rxq_ctrl);
1084 attr.wq.flags |= IBV_EXP_CREATE_WQ_FLAG_RX_END_PADDING;
1085 attr.wq.comp_mask |= IBV_EXP_CREATE_WQ_FLAGS;
1087 WARN("%p: packet padding has been requested but is not"
1088 " supported, make sure MLNX_OFED and firmware are"
1091 #endif /* HAVE_VERBS_RX_END_PADDING */
1093 tmpl.rxq.wq = ibv_exp_create_wq(priv->ctx, &attr.wq);
1094 if (tmpl.rxq.wq == NULL) {
1095 ret = (errno ? errno : EINVAL);
1096 ERROR("%p: WQ creation failure: %s",
1097 (void *)dev, strerror(ret));
1100 ret = rxq_alloc_elts(&tmpl, desc, NULL);
1102 ERROR("%p: RXQ allocation failed: %s",
1103 (void *)dev, strerror(ret));
1107 tmpl.rxq.port_id = dev->data->port_id;
1108 DEBUG("%p: RTE port ID: %u", (void *)rxq_ctrl, tmpl.rxq.port_id);
1109 attr.params = (struct ibv_exp_query_intf_params){
1110 .intf_scope = IBV_EXP_INTF_GLOBAL,
1111 #ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS
1113 #endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */
1114 .intf = IBV_EXP_INTF_CQ,
1117 tmpl.if_cq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
1118 if (tmpl.if_cq == NULL) {
1119 ERROR("%p: CQ interface family query failed with status %d",
1120 (void *)dev, status);
1123 attr.params = (struct ibv_exp_query_intf_params){
1124 .intf_scope = IBV_EXP_INTF_GLOBAL,
1125 .intf = IBV_EXP_INTF_WQ,
1128 tmpl.if_wq = ibv_exp_query_intf(priv->ctx, &attr.params, &status);
1129 if (tmpl.if_wq == NULL) {
1130 ERROR("%p: WQ interface family query failed with status %d",
1131 (void *)dev, status);
1134 /* Change queue state to ready. */
1135 mod = (struct ibv_exp_wq_attr){
1136 .attr_mask = IBV_EXP_WQ_ATTR_STATE,
1137 .wq_state = IBV_EXP_WQS_RDY,
1139 ret = ibv_exp_modify_wq(tmpl.rxq.wq, &mod);
1141 ERROR("%p: WQ state to IBV_EXP_WQS_RDY failed: %s",
1142 (void *)dev, strerror(ret));
1146 elts = tmpl.rxq.elts;
1147 for (i = 0; (i != RTE_DIM(*elts)); ++i) {
1148 ret = tmpl.if_wq->recv_burst(
1156 ERROR("%p: failed to post SGEs with error %d",
1158 /* Set ret because it does not contain a valid errno value. */
1162 /* Clean up rxq in case we're reinitializing it. */
1163 DEBUG("%p: cleaning-up old rxq just in case", (void *)rxq_ctrl);
1164 rxq_cleanup(rxq_ctrl);
1166 DEBUG("%p: rxq updated with %p", (void *)rxq_ctrl, (void *)&tmpl);
1168 /* Assign function in queue. */
1169 #ifdef HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS
1170 rxq_ctrl->rxq.poll = rxq_ctrl->if_cq->poll_length_flags_cvlan;
1171 #else /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */
1172 rxq_ctrl->rxq.poll = rxq_ctrl->if_cq->poll_length_flags;
1173 #endif /* HAVE_EXP_DEVICE_ATTR_VLAN_OFFLOADS */
1174 rxq_ctrl->rxq.recv = rxq_ctrl->if_wq->recv_burst;
1183 * DPDK callback to configure a RX queue.
1186 * Pointer to Ethernet device structure.
1190 * Number of descriptors to configure in queue.
1192 * NUMA socket on which memory must be allocated.
1194 * Thresholds parameters.
1196 * Memory pool for buffer allocations.
1199 * 0 on success, negative errno value on failure.
1202 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1203 unsigned int socket, const struct rte_eth_rxconf *conf,
1204 struct rte_mempool *mp)
1206 struct priv *priv = dev->data->dev_private;
1207 struct rxq *rxq = (*priv->rxqs)[idx];
1208 struct rxq_ctrl *rxq_ctrl;
1211 if (mlx5_is_secondary())
1212 return -E_RTE_SECONDARY;
1215 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
1216 DEBUG("%p: configuring queue %u for %u descriptors",
1217 (void *)dev, idx, desc);
1218 if (idx >= priv->rxqs_n) {
1219 ERROR("%p: queue index out of range (%u >= %u)",
1220 (void *)dev, idx, priv->rxqs_n);
1225 DEBUG("%p: reusing already allocated queue index %u (%p)",
1226 (void *)dev, idx, (void *)rxq);
1227 if (priv->started) {
1231 (*priv->rxqs)[idx] = NULL;
1232 rxq_cleanup(rxq_ctrl);
1234 rxq_ctrl = rte_calloc_socket("RXQ", 1, sizeof(*rxq_ctrl), 0,
1236 if (rxq_ctrl == NULL) {
1237 ERROR("%p: unable to allocate queue index %u",
1243 ret = rxq_setup(dev, rxq_ctrl, desc, socket, conf, mp);
1247 rxq_ctrl->rxq.stats.idx = idx;
1248 DEBUG("%p: adding RX queue %p to list",
1249 (void *)dev, (void *)rxq_ctrl);
1250 (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
1251 /* Update receive callback. */
1252 dev->rx_pkt_burst = mlx5_rx_burst;
1259 * DPDK callback to release a RX queue.
1262 * Generic RX queue pointer.
1265 mlx5_rx_queue_release(void *dpdk_rxq)
1267 struct rxq *rxq = (struct rxq *)dpdk_rxq;
1268 struct rxq_ctrl *rxq_ctrl;
1272 if (mlx5_is_secondary())
1277 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
1280 for (i = 0; (i != priv->rxqs_n); ++i)
1281 if ((*priv->rxqs)[i] == rxq) {
1282 DEBUG("%p: removing RX queue %p from list",
1283 (void *)priv->dev, (void *)rxq);
1284 (*priv->rxqs)[i] = NULL;
1287 rxq_cleanup(rxq_ctrl);
1293 * DPDK callback for RX in secondary processes.
1295 * This function configures all queues from primary process information
1296 * if necessary before reverting to the normal RX burst callback.
1299 * Generic pointer to RX queue structure.
1301 * Array to store received packets.
1303 * Maximum number of packets in array.
1306 * Number of packets successfully received (<= pkts_n).
1309 mlx5_rx_burst_secondary_setup(void *dpdk_rxq, struct rte_mbuf **pkts,
1312 struct rxq *rxq = dpdk_rxq;
1313 struct priv *priv = mlx5_secondary_data_setup(rxq->priv);
1314 struct priv *primary_priv;
1320 mlx5_secondary_data[priv->dev->data->port_id].primary_priv;
1321 /* Look for queue index in both private structures. */
1322 for (index = 0; index != priv->rxqs_n; ++index)
1323 if (((*primary_priv->rxqs)[index] == rxq) ||
1324 ((*priv->rxqs)[index] == rxq))
1326 if (index == priv->rxqs_n)
1328 rxq = (*priv->rxqs)[index];
1329 return priv->dev->rx_pkt_burst(rxq, pkts, pkts_n);