drivers/net/mlx5/mlx5_rxq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <errno.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <fcntl.h>
  11 #include <sys/queue.h>
  12
  13 /* Verbs header. */
  14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  15 #ifdef PEDANTIC
  16 #pragma GCC diagnostic ignored "-Wpedantic"
  17 #endif
  18 #include <infiniband/verbs.h>
  19 #include <infiniband/mlx5dv.h>
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic error "-Wpedantic"
  22 #endif
  23
  24 #include <rte_mbuf.h>
  25 #include <rte_malloc.h>
  26 #include <rte_ethdev_driver.h>
  27 #include <rte_common.h>
  28 #include <rte_interrupts.h>
  29 #include <rte_debug.h>
  30 #include <rte_io.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34
  35 #include "mlx5_defs.h"
  36 #include "mlx5.h"
  37 #include "mlx5_common_os.h"
  38 #include "mlx5_rxtx.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_flow.h"
  42
  43
  44 /* Default RSS hash key also used for ConnectX-3. */
  45 uint8_t rss_hash_default_key[] = {
  46         0x2c, 0xc6, 0x81, 0xd1,
  47         0x5b, 0xdb, 0xf4, 0xf7,
  48         0xfc, 0xa2, 0x83, 0x19,
  49         0xdb, 0x1a, 0x3e, 0x94,
  50         0x6b, 0x9e, 0x38, 0xd9,
  51         0x2c, 0x9c, 0x03, 0xd1,
  52         0xad, 0x99, 0x44, 0xa7,
  53         0xd9, 0x56, 0x3d, 0x59,
  54         0x06, 0x3c, 0x25, 0xf3,
  55         0xfc, 0x1f, 0xdc, 0x2a,
  56 };
  57
  58 /* Length of the default RSS hash key. */
  59 static_assert(MLX5_RSS_HASH_KEY_LEN ==
  60               (unsigned int)sizeof(rss_hash_default_key),
  61               "wrong RSS default key size.");
  62
  63 /**
  64  * Check whether Multi-Packet RQ can be enabled for the device.
  65  *
  66  * @param dev
  67  *   Pointer to Ethernet device.
  68  *
  69  * @return
  70  *   1 if supported, negative errno value if not.
  71  */
  72 inline int
  73 mlx5_check_mprq_support(struct rte_eth_dev *dev)
  74 {
  75         struct mlx5_priv *priv = dev->data->dev_private;
  76
  77         if (priv->config.mprq.enabled &&
  78             priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
  79                 return 1;
  80         return -ENOTSUP;
  81 }
  82
  83 /**
  84  * Check whether Multi-Packet RQ is enabled for the Rx queue.
  85  *
  86  *  @param rxq
  87  *     Pointer to receive queue structure.
  88  *
  89  * @return
  90  *   0 if disabled, otherwise enabled.
  91  */
  92 inline int
  93 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
  94 {
  95         return rxq->strd_num_n > 0;
  96 }
  97
  98 /**
  99  * Check whether Multi-Packet RQ is enabled for the device.
 100  *
 101  * @param dev
 102  *   Pointer to Ethernet device.
 103  *
 104  * @return
 105  *   0 if disabled, otherwise enabled.
 106  */
 107 inline int
 108 mlx5_mprq_enabled(struct rte_eth_dev *dev)
 109 {
 110         struct mlx5_priv *priv = dev->data->dev_private;
 111         uint32_t i;
 112         uint16_t n = 0;
 113         uint16_t n_ibv = 0;
 114
 115         if (mlx5_check_mprq_support(dev) < 0)
 116                 return 0;
 117         /* All the configured queues should be enabled. */
 118         for (i = 0; i < priv->rxqs_n; ++i) {
 119                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
 120                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
 121                         (rxq, struct mlx5_rxq_ctrl, rxq);
 122
 123                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
 124                         continue;
 125                 n_ibv++;
 126                 if (mlx5_rxq_mprq_enabled(rxq))
 127                         ++n;
 128         }
 129         /* Multi-Packet RQ can't be partially configured. */
 130         MLX5_ASSERT(n == 0 || n == n_ibv);
 131         return n == n_ibv;
 132 }
 133
 134 /**
 135  * Allocate RX queue elements for Multi-Packet RQ.
 136  *
 137  * @param rxq_ctrl
 138  *   Pointer to RX queue structure.
 139  *
 140  * @return
 141  *   0 on success, a negative errno value otherwise and rte_errno is set.
 142  */
 143 static int
 144 rxq_alloc_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 145 {
 146         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 147         unsigned int wqe_n = 1 << rxq->elts_n;
 148         unsigned int i;
 149         int err;
 150
 151         /* Iterate on segments. */
 152         for (i = 0; i <= wqe_n; ++i) {
 153                 struct mlx5_mprq_buf *buf;
 154
 155                 if (rte_mempool_get(rxq->mprq_mp, (void **)&buf) < 0) {
 156                         DRV_LOG(ERR, "port %u empty mbuf pool", rxq->port_id);
 157                         rte_errno = ENOMEM;
 158                         goto error;
 159                 }
 160                 if (i < wqe_n)
 161                         (*rxq->mprq_bufs)[i] = buf;
 162                 else
 163                         rxq->mprq_repl = buf;
 164         }
 165         DRV_LOG(DEBUG,
 166                 "port %u Rx queue %u allocated and configured %u segments",
 167                 rxq->port_id, rxq->idx, wqe_n);
 168         return 0;
 169 error:
 170         err = rte_errno; /* Save rte_errno before cleanup. */
 171         wqe_n = i;
 172         for (i = 0; (i != wqe_n); ++i) {
 173                 if ((*rxq->mprq_bufs)[i] != NULL)
 174                         rte_mempool_put(rxq->mprq_mp,
 175                                         (*rxq->mprq_bufs)[i]);
 176                 (*rxq->mprq_bufs)[i] = NULL;
 177         }
 178         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 179                 rxq->port_id, rxq->idx);
 180         rte_errno = err; /* Restore rte_errno. */
 181         return -rte_errno;
 182 }
 183
 184 /**
 185  * Allocate RX queue elements for Single-Packet RQ.
 186  *
 187  * @param rxq_ctrl
 188  *   Pointer to RX queue structure.
 189  *
 190  * @return
 191  *   0 on success, errno value on failure.
 192  */
 193 static int
 194 rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 195 {
 196         const unsigned int sges_n = 1 << rxq_ctrl->rxq.sges_n;
 197         unsigned int elts_n = 1 << rxq_ctrl->rxq.elts_n;
 198         unsigned int i;
 199         int err;
 200
 201         /* Iterate on segments. */
 202         for (i = 0; (i != elts_n); ++i) {
 203                 struct rte_mbuf *buf;
 204
 205                 buf = rte_pktmbuf_alloc(rxq_ctrl->rxq.mp);
 206                 if (buf == NULL) {
 207                         DRV_LOG(ERR, "port %u empty mbuf pool",
 208                                 PORT_ID(rxq_ctrl->priv));
 209                         rte_errno = ENOMEM;
 210                         goto error;
 211                 }
 212                 /* Headroom is reserved by rte_pktmbuf_alloc(). */
 213                 MLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);
 214                 /* Buffer is supposed to be empty. */
 215                 MLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);
 216                 MLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);
 217                 MLX5_ASSERT(!buf->next);
 218                 /* Only the first segment keeps headroom. */
 219                 if (i % sges_n)
 220                         SET_DATA_OFF(buf, 0);
 221                 PORT(buf) = rxq_ctrl->rxq.port_id;
 222                 DATA_LEN(buf) = rte_pktmbuf_tailroom(buf);
 223                 PKT_LEN(buf) = DATA_LEN(buf);
 224                 NB_SEGS(buf) = 1;
 225                 (*rxq_ctrl->rxq.elts)[i] = buf;
 226         }
 227         /* If Rx vector is activated. */
 228         if (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {
 229                 struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 230                 struct rte_mbuf *mbuf_init = &rxq->fake_mbuf;
 231                 struct rte_pktmbuf_pool_private *priv =
 232                         (struct rte_pktmbuf_pool_private *)
 233                                 rte_mempool_get_priv(rxq_ctrl->rxq.mp);
 234                 int j;
 235
 236                 /* Initialize default rearm_data for vPMD. */
 237                 mbuf_init->data_off = RTE_PKTMBUF_HEADROOM;
 238                 rte_mbuf_refcnt_set(mbuf_init, 1);
 239                 mbuf_init->nb_segs = 1;
 240                 mbuf_init->port = rxq->port_id;
 241                 if (priv->flags & RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF)
 242                         mbuf_init->ol_flags = EXT_ATTACHED_MBUF;
 243                 /*
 244                  * prevent compiler reordering:
 245                  * rearm_data covers previous fields.
 246                  */
 247                 rte_compiler_barrier();
 248                 rxq->mbuf_initializer =
 249                         *(rte_xmm_t *)&mbuf_init->rearm_data;
 250                 /* Padding with a fake mbuf for vectorized Rx. */
 251                 for (j = 0; j < MLX5_VPMD_DESCS_PER_LOOP; ++j)
 252                         (*rxq->elts)[elts_n + j] = &rxq->fake_mbuf;
 253         }
 254         DRV_LOG(DEBUG,
 255                 "port %u Rx queue %u allocated and configured %u segments"
 256                 " (max %u packets)",
 257                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx, elts_n,
 258                 elts_n / (1 << rxq_ctrl->rxq.sges_n));
 259         return 0;
 260 error:
 261         err = rte_errno; /* Save rte_errno before cleanup. */
 262         elts_n = i;
 263         for (i = 0; (i != elts_n); ++i) {
 264                 if ((*rxq_ctrl->rxq.elts)[i] != NULL)
 265                         rte_pktmbuf_free_seg((*rxq_ctrl->rxq.elts)[i]);
 266                 (*rxq_ctrl->rxq.elts)[i] = NULL;
 267         }
 268         DRV_LOG(DEBUG, "port %u Rx queue %u failed, freed everything",
 269                 PORT_ID(rxq_ctrl->priv), rxq_ctrl->rxq.idx);
 270         rte_errno = err; /* Restore rte_errno. */
 271         return -rte_errno;
 272 }
 273
 274 /**
 275  * Allocate RX queue elements.
 276  *
 277  * @param rxq_ctrl
 278  *   Pointer to RX queue structure.
 279  *
 280  * @return
 281  *   0 on success, errno value on failure.
 282  */
 283 int
 284 rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 285 {
 286         return mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
 287                rxq_alloc_elts_mprq(rxq_ctrl) : rxq_alloc_elts_sprq(rxq_ctrl);
 288 }
 289
 290 /**
 291  * Free RX queue elements for Multi-Packet RQ.
 292  *
 293  * @param rxq_ctrl
 294  *   Pointer to RX queue structure.
 295  */
 296 static void
 297 rxq_free_elts_mprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 298 {
 299         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 300         uint16_t i;
 301
 302         DRV_LOG(DEBUG, "port %u Multi-Packet Rx queue %u freeing WRs",
 303                 rxq->port_id, rxq->idx);
 304         if (rxq->mprq_bufs == NULL)
 305                 return;
 306         MLX5_ASSERT(mlx5_rxq_check_vec_support(rxq) < 0);
 307         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 308                 if ((*rxq->mprq_bufs)[i] != NULL)
 309                         mlx5_mprq_buf_free((*rxq->mprq_bufs)[i]);
 310                 (*rxq->mprq_bufs)[i] = NULL;
 311         }
 312         if (rxq->mprq_repl != NULL) {
 313                 mlx5_mprq_buf_free(rxq->mprq_repl);
 314                 rxq->mprq_repl = NULL;
 315         }
 316 }
 317
 318 /**
 319  * Free RX queue elements for Single-Packet RQ.
 320  *
 321  * @param rxq_ctrl
 322  *   Pointer to RX queue structure.
 323  */
 324 static void
 325 rxq_free_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)
 326 {
 327         struct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;
 328         const uint16_t q_n = (1 << rxq->elts_n);
 329         const uint16_t q_mask = q_n - 1;
 330         uint16_t used = q_n - (rxq->rq_ci - rxq->rq_pi);
 331         uint16_t i;
 332
 333         DRV_LOG(DEBUG, "port %u Rx queue %u freeing WRs",
 334                 PORT_ID(rxq_ctrl->priv), rxq->idx);
 335         if (rxq->elts == NULL)
 336                 return;
 337         /**
 338          * Some mbuf in the Ring belongs to the application.  They cannot be
 339          * freed.
 340          */
 341         if (mlx5_rxq_check_vec_support(rxq) > 0) {
 342                 for (i = 0; i < used; ++i)
 343                         (*rxq->elts)[(rxq->rq_ci + i) & q_mask] = NULL;
 344                 rxq->rq_pi = rxq->rq_ci;
 345         }
 346         for (i = 0; (i != (1u << rxq->elts_n)); ++i) {
 347                 if ((*rxq->elts)[i] != NULL)
 348                         rte_pktmbuf_free_seg((*rxq->elts)[i]);
 349                 (*rxq->elts)[i] = NULL;
 350         }
 351 }
 352
 353 /**
 354  * Free RX queue elements.
 355  *
 356  * @param rxq_ctrl
 357  *   Pointer to RX queue structure.
 358  */
 359 static void
 360 rxq_free_elts(struct mlx5_rxq_ctrl *rxq_ctrl)
 361 {
 362         if (mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq))
 363                 rxq_free_elts_mprq(rxq_ctrl);
 364         else
 365                 rxq_free_elts_sprq(rxq_ctrl);
 366 }
 367
 368 /**
 369  * Returns the per-queue supported offloads.
 370  *
 371  * @param dev
 372  *   Pointer to Ethernet device.
 373  *
 374  * @return
 375  *   Supported Rx offloads.
 376  */
 377 uint64_t
 378 mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)
 379 {
 380         struct mlx5_priv *priv = dev->data->dev_private;
 381         struct mlx5_dev_config *config = &priv->config;
 382         uint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |
 383                              DEV_RX_OFFLOAD_TIMESTAMP |
 384                              DEV_RX_OFFLOAD_JUMBO_FRAME |
 385                              DEV_RX_OFFLOAD_RSS_HASH);
 386
 387         if (config->hw_fcs_strip)
 388                 offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
 389
 390         if (config->hw_csum)
 391                 offloads |= (DEV_RX_OFFLOAD_IPV4_CKSUM |
 392                              DEV_RX_OFFLOAD_UDP_CKSUM |
 393                              DEV_RX_OFFLOAD_TCP_CKSUM);
 394         if (config->hw_vlan_strip)
 395                 offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 396         if (MLX5_LRO_SUPPORTED(dev))
 397                 offloads |= DEV_RX_OFFLOAD_TCP_LRO;
 398         return offloads;
 399 }
 400
 401
 402 /**
 403  * Returns the per-port supported offloads.
 404  *
 405  * @return
 406  *   Supported Rx offloads.
 407  */
 408 uint64_t
 409 mlx5_get_rx_port_offloads(void)
 410 {
 411         uint64_t offloads = DEV_RX_OFFLOAD_VLAN_FILTER;
 412
 413         return offloads;
 414 }
 415
 416 /**
 417  * Verify if the queue can be released.
 418  *
 419  * @param dev
 420  *   Pointer to Ethernet device.
 421  * @param idx
 422  *   RX queue index.
 423  *
 424  * @return
 425  *   1 if the queue can be released
 426  *   0 if the queue can not be released, there are references to it.
 427  *   Negative errno and rte_errno is set if queue doesn't exist.
 428  */
 429 static int
 430 mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx)
 431 {
 432         struct mlx5_priv *priv = dev->data->dev_private;
 433         struct mlx5_rxq_ctrl *rxq_ctrl;
 434
 435         if (!(*priv->rxqs)[idx]) {
 436                 rte_errno = EINVAL;
 437                 return -rte_errno;
 438         }
 439         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
 440         return (rte_atomic32_read(&rxq_ctrl->refcnt) == 1);
 441 }
 442
 443 /**
 444  * Rx queue presetup checks.
 445  *
 446  * @param dev
 447  *   Pointer to Ethernet device structure.
 448  * @param idx
 449  *   RX queue index.
 450  * @param desc
 451  *   Number of descriptors to configure in queue.
 452  *
 453  * @return
 454  *   0 on success, a negative errno value otherwise and rte_errno is set.
 455  */
 456 static int
 457 mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)
 458 {
 459         struct mlx5_priv *priv = dev->data->dev_private;
 460
 461         if (!rte_is_power_of_2(*desc)) {
 462                 *desc = 1 << log2above(*desc);
 463                 DRV_LOG(WARNING,
 464                         "port %u increased number of descriptors in Rx queue %u"
 465                         " to the next power of two (%d)",
 466                         dev->data->port_id, idx, *desc);
 467         }
 468         DRV_LOG(DEBUG, "port %u configuring Rx queue %u for %u descriptors",
 469                 dev->data->port_id, idx, *desc);
 470         if (idx >= priv->rxqs_n) {
 471                 DRV_LOG(ERR, "port %u Rx queue index out of range (%u >= %u)",
 472                         dev->data->port_id, idx, priv->rxqs_n);
 473                 rte_errno = EOVERFLOW;
 474                 return -rte_errno;
 475         }
 476         if (!mlx5_rxq_releasable(dev, idx)) {
 477                 DRV_LOG(ERR, "port %u unable to release queue index %u",
 478                         dev->data->port_id, idx);
 479                 rte_errno = EBUSY;
 480                 return -rte_errno;
 481         }
 482         mlx5_rxq_release(dev, idx);
 483         return 0;
 484 }
 485
 486 /**
 487  *
 488  * @param dev
 489  *   Pointer to Ethernet device structure.
 490  * @param idx
 491  *   RX queue index.
 492  * @param desc
 493  *   Number of descriptors to configure in queue.
 494  * @param socket
 495  *   NUMA socket on which memory must be allocated.
 496  * @param[in] conf
 497  *   Thresholds parameters.
 498  * @param mp
 499  *   Memory pool for buffer allocations.
 500  *
 501  * @return
 502  *   0 on success, a negative errno value otherwise and rte_errno is set.
 503  */
 504 int
 505 mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 506                     unsigned int socket, const struct rte_eth_rxconf *conf,
 507                     struct rte_mempool *mp)
 508 {
 509         struct mlx5_priv *priv = dev->data->dev_private;
 510         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 511         struct mlx5_rxq_ctrl *rxq_ctrl =
 512                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 513         int res;
 514
 515         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 516         if (res)
 517                 return res;
 518         rxq_ctrl = mlx5_rxq_new(dev, idx, desc, socket, conf, mp);
 519         if (!rxq_ctrl) {
 520                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 521                         dev->data->port_id, idx);
 522                 rte_errno = ENOMEM;
 523                 return -rte_errno;
 524         }
 525         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 526                 dev->data->port_id, idx);
 527         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 528         return 0;
 529 }
 530
 531 /**
 532  *
 533  * @param dev
 534  *   Pointer to Ethernet device structure.
 535  * @param idx
 536  *   RX queue index.
 537  * @param desc
 538  *   Number of descriptors to configure in queue.
 539  * @param hairpin_conf
 540  *   Hairpin configuration parameters.
 541  *
 542  * @return
 543  *   0 on success, a negative errno value otherwise and rte_errno is set.
 544  */
 545 int
 546 mlx5_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
 547                             uint16_t desc,
 548                             const struct rte_eth_hairpin_conf *hairpin_conf)
 549 {
 550         struct mlx5_priv *priv = dev->data->dev_private;
 551         struct mlx5_rxq_data *rxq = (*priv->rxqs)[idx];
 552         struct mlx5_rxq_ctrl *rxq_ctrl =
 553                 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 554         int res;
 555
 556         res = mlx5_rx_queue_pre_setup(dev, idx, &desc);
 557         if (res)
 558                 return res;
 559         if (hairpin_conf->peer_count != 1 ||
 560             hairpin_conf->peers[0].port != dev->data->port_id ||
 561             hairpin_conf->peers[0].queue >= priv->txqs_n) {
 562                 DRV_LOG(ERR, "port %u unable to setup hairpin queue index %u "
 563                         " invalid hairpind configuration", dev->data->port_id,
 564                         idx);
 565                 rte_errno = EINVAL;
 566                 return -rte_errno;
 567         }
 568         rxq_ctrl = mlx5_rxq_hairpin_new(dev, idx, desc, hairpin_conf);
 569         if (!rxq_ctrl) {
 570                 DRV_LOG(ERR, "port %u unable to allocate queue index %u",
 571                         dev->data->port_id, idx);
 572                 rte_errno = ENOMEM;
 573                 return -rte_errno;
 574         }
 575         DRV_LOG(DEBUG, "port %u adding Rx queue %u to list",
 576                 dev->data->port_id, idx);
 577         (*priv->rxqs)[idx] = &rxq_ctrl->rxq;
 578         return 0;
 579 }
 580
 581 /**
 582  * DPDK callback to release a RX queue.
 583  *
 584  * @param dpdk_rxq
 585  *   Generic RX queue pointer.
 586  */
 587 void
 588 mlx5_rx_queue_release(void *dpdk_rxq)
 589 {
 590         struct mlx5_rxq_data *rxq = (struct mlx5_rxq_data *)dpdk_rxq;
 591         struct mlx5_rxq_ctrl *rxq_ctrl;
 592         struct mlx5_priv *priv;
 593
 594         if (rxq == NULL)
 595                 return;
 596         rxq_ctrl = container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 597         priv = rxq_ctrl->priv;
 598         if (!mlx5_rxq_releasable(ETH_DEV(priv), rxq_ctrl->rxq.idx))
 599                 rte_panic("port %u Rx queue %u is still used by a flow and"
 600                           " cannot be removed\n",
 601                           PORT_ID(priv), rxq->idx);
 602         mlx5_rxq_release(ETH_DEV(priv), rxq_ctrl->rxq.idx);
 603 }
 604
 605 /**
 606  * Get an Rx queue Verbs/DevX object.
 607  *
 608  * @param dev
 609  *   Pointer to Ethernet device.
 610  * @param idx
 611  *   Queue index in DPDK Rx queue array
 612  *
 613  * @return
 614  *   The Verbs/DevX object if it exists.
 615  */
 616 static struct mlx5_rxq_obj *
 617 mlx5_rxq_obj_get(struct rte_eth_dev *dev, uint16_t idx)
 618 {
 619         struct mlx5_priv *priv = dev->data->dev_private;
 620         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
 621         struct mlx5_rxq_ctrl *rxq_ctrl;
 622
 623         if (idx >= priv->rxqs_n)
 624                 return NULL;
 625         if (!rxq_data)
 626                 return NULL;
 627         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 628         if (rxq_ctrl->obj)
 629                 rte_atomic32_inc(&rxq_ctrl->obj->refcnt);
 630         return rxq_ctrl->obj;
 631 }
 632
 633 /**
 634  * Release the resources allocated for an RQ DevX object.
 635  *
 636  * @param rxq_ctrl
 637  *   DevX Rx queue object.
 638  */
 639 static void
 640 rxq_release_rq_resources(struct mlx5_rxq_ctrl *rxq_ctrl)
 641 {
 642         if (rxq_ctrl->rxq.wqes) {
 643                 rte_free((void *)(uintptr_t)rxq_ctrl->rxq.wqes);
 644                 rxq_ctrl->rxq.wqes = NULL;
 645         }
 646         if (rxq_ctrl->wq_umem) {
 647                 mlx5_glue->devx_umem_dereg(rxq_ctrl->wq_umem);
 648                 rxq_ctrl->wq_umem = NULL;
 649         }
 650 }
 651
 652 /**
 653  * Release an Rx hairpin related resources.
 654  *
 655  * @param rxq_obj
 656  *   Hairpin Rx queue object.
 657  */
 658 static void
 659 rxq_obj_hairpin_release(struct mlx5_rxq_obj *rxq_obj)
 660 {
 661         struct mlx5_devx_modify_rq_attr rq_attr = { 0 };
 662
 663         MLX5_ASSERT(rxq_obj);
 664         rq_attr.state = MLX5_RQC_STATE_RST;
 665         rq_attr.rq_state = MLX5_RQC_STATE_RDY;
 666         mlx5_devx_cmd_modify_rq(rxq_obj->rq, &rq_attr);
 667         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 668 }
 669
 670 /**
 671  * Release an Rx verbs/DevX queue object.
 672  *
 673  * @param rxq_obj
 674  *   Verbs/DevX Rx queue object.
 675  *
 676  * @return
 677  *   1 while a reference on it exists, 0 when freed.
 678  */
 679 static int
 680 mlx5_rxq_obj_release(struct mlx5_rxq_obj *rxq_obj)
 681 {
 682         MLX5_ASSERT(rxq_obj);
 683         if (rte_atomic32_dec_and_test(&rxq_obj->refcnt)) {
 684                 switch (rxq_obj->type) {
 685                 case MLX5_RXQ_OBJ_TYPE_IBV:
 686                         MLX5_ASSERT(rxq_obj->wq);
 687                         MLX5_ASSERT(rxq_obj->cq);
 688                         rxq_free_elts(rxq_obj->rxq_ctrl);
 689                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
 690                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 691                         break;
 692                 case MLX5_RXQ_OBJ_TYPE_DEVX_RQ:
 693                         MLX5_ASSERT(rxq_obj->cq);
 694                         MLX5_ASSERT(rxq_obj->rq);
 695                         rxq_free_elts(rxq_obj->rxq_ctrl);
 696                         claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
 697                         rxq_release_rq_resources(rxq_obj->rxq_ctrl);
 698                         claim_zero(mlx5_glue->destroy_cq(rxq_obj->cq));
 699                         break;
 700                 case MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN:
 701                         MLX5_ASSERT(rxq_obj->rq);
 702                         rxq_obj_hairpin_release(rxq_obj);
 703                         break;
 704                 }
 705                 if (rxq_obj->channel)
 706                         claim_zero(mlx5_glue->destroy_comp_channel
 707                                    (rxq_obj->channel));
 708                 LIST_REMOVE(rxq_obj, next);
 709                 rte_free(rxq_obj);
 710                 return 0;
 711         }
 712         return 1;
 713 }
 714
 715 /**
 716  * Allocate queue vector and fill epoll fd list for Rx interrupts.
 717  *
 718  * @param dev
 719  *   Pointer to Ethernet device.
 720  *
 721  * @return
 722  *   0 on success, a negative errno value otherwise and rte_errno is set.
 723  */
 724 int
 725 mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev)
 726 {
 727         struct mlx5_priv *priv = dev->data->dev_private;
 728         unsigned int i;
 729         unsigned int rxqs_n = priv->rxqs_n;
 730         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 731         unsigned int count = 0;
 732         struct rte_intr_handle *intr_handle = dev->intr_handle;
 733
 734         if (!dev->data->dev_conf.intr_conf.rxq)
 735                 return 0;
 736         mlx5_rx_intr_vec_disable(dev);
 737         intr_handle->intr_vec = malloc(n * sizeof(intr_handle->intr_vec[0]));
 738         if (intr_handle->intr_vec == NULL) {
 739                 DRV_LOG(ERR,
 740                         "port %u failed to allocate memory for interrupt"
 741                         " vector, Rx interrupts will not be supported",
 742                         dev->data->port_id);
 743                 rte_errno = ENOMEM;
 744                 return -rte_errno;
 745         }
 746         intr_handle->type = RTE_INTR_HANDLE_EXT;
 747         for (i = 0; i != n; ++i) {
 748                 /* This rxq obj must not be released in this function. */
 749                 struct mlx5_rxq_obj *rxq_obj = mlx5_rxq_obj_get(dev, i);
 750                 int fd;
 751                 int flags;
 752                 int rc;
 753
 754                 /* Skip queues that cannot request interrupts. */
 755                 if (!rxq_obj || !rxq_obj->channel) {
 756                         /* Use invalid intr_vec[] index to disable entry. */
 757                         intr_handle->intr_vec[i] =
 758                                 RTE_INTR_VEC_RXTX_OFFSET +
 759                                 RTE_MAX_RXTX_INTR_VEC_ID;
 760                         continue;
 761                 }
 762                 if (count >= RTE_MAX_RXTX_INTR_VEC_ID) {
 763                         DRV_LOG(ERR,
 764                                 "port %u too many Rx queues for interrupt"
 765                                 " vector size (%d), Rx interrupts cannot be"
 766                                 " enabled",
 767                                 dev->data->port_id, RTE_MAX_RXTX_INTR_VEC_ID);
 768                         mlx5_rx_intr_vec_disable(dev);
 769                         rte_errno = ENOMEM;
 770                         return -rte_errno;
 771                 }
 772                 fd = rxq_obj->channel->fd;
 773                 flags = fcntl(fd, F_GETFL);
 774                 rc = fcntl(fd, F_SETFL, flags | O_NONBLOCK);
 775                 if (rc < 0) {
 776                         rte_errno = errno;
 777                         DRV_LOG(ERR,
 778                                 "port %u failed to make Rx interrupt file"
 779                                 " descriptor %d non-blocking for queue index"
 780                                 " %d",
 781                                 dev->data->port_id, fd, i);
 782                         mlx5_rx_intr_vec_disable(dev);
 783                         return -rte_errno;
 784                 }
 785                 intr_handle->intr_vec[i] = RTE_INTR_VEC_RXTX_OFFSET + count;
 786                 intr_handle->efds[count] = fd;
 787                 count++;
 788         }
 789         if (!count)
 790                 mlx5_rx_intr_vec_disable(dev);
 791         else
 792                 intr_handle->nb_efd = count;
 793         return 0;
 794 }
 795
 796 /**
 797  * Clean up Rx interrupts handler.
 798  *
 799  * @param dev
 800  *   Pointer to Ethernet device.
 801  */
 802 void
 803 mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev)
 804 {
 805         struct mlx5_priv *priv = dev->data->dev_private;
 806         struct rte_intr_handle *intr_handle = dev->intr_handle;
 807         unsigned int i;
 808         unsigned int rxqs_n = priv->rxqs_n;
 809         unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID);
 810
 811         if (!dev->data->dev_conf.intr_conf.rxq)
 812                 return;
 813         if (!intr_handle->intr_vec)
 814                 goto free;
 815         for (i = 0; i != n; ++i) {
 816                 struct mlx5_rxq_ctrl *rxq_ctrl;
 817                 struct mlx5_rxq_data *rxq_data;
 818
 819                 if (intr_handle->intr_vec[i] == RTE_INTR_VEC_RXTX_OFFSET +
 820                     RTE_MAX_RXTX_INTR_VEC_ID)
 821                         continue;
 822                 /**
 823                  * Need to access directly the queue to release the reference
 824                  * kept in mlx5_rx_intr_vec_enable().
 825                  */
 826                 rxq_data = (*priv->rxqs)[i];
 827                 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 828                 if (rxq_ctrl->obj)
 829                         mlx5_rxq_obj_release(rxq_ctrl->obj);
 830         }
 831 free:
 832         rte_intr_free_epoll_fd(intr_handle);
 833         if (intr_handle->intr_vec)
 834                 free(intr_handle->intr_vec);
 835         intr_handle->nb_efd = 0;
 836         intr_handle->intr_vec = NULL;
 837 }
 838
 839 /**
 840  *  MLX5 CQ notification .
 841  *
 842  *  @param rxq
 843  *     Pointer to receive queue structure.
 844  *  @param sq_n_rxq
 845  *     Sequence number per receive queue .
 846  */
 847 static inline void
 848 mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq)
 849 {
 850         int sq_n = 0;
 851         uint32_t doorbell_hi;
 852         uint64_t doorbell;
 853         void *cq_db_reg = (char *)rxq->cq_uar + MLX5_CQ_DOORBELL;
 854
 855         sq_n = sq_n_rxq & MLX5_CQ_SQN_MASK;
 856         doorbell_hi = sq_n << MLX5_CQ_SQN_OFFSET | (rxq->cq_ci & MLX5_CI_MASK);
 857         doorbell = (uint64_t)doorbell_hi << 32;
 858         doorbell |=  rxq->cqn;
 859         rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi);
 860         mlx5_uar_write64(rte_cpu_to_be_64(doorbell),
 861                          cq_db_reg, rxq->uar_lock_cq);
 862 }
 863
 864 /**
 865  * DPDK callback for Rx queue interrupt enable.
 866  *
 867  * @param dev
 868  *   Pointer to Ethernet device structure.
 869  * @param rx_queue_id
 870  *   Rx queue number.
 871  *
 872  * @return
 873  *   0 on success, a negative errno value otherwise and rte_errno is set.
 874  */
 875 int
 876 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 877 {
 878         struct mlx5_priv *priv = dev->data->dev_private;
 879         struct mlx5_rxq_data *rxq_data;
 880         struct mlx5_rxq_ctrl *rxq_ctrl;
 881
 882         rxq_data = (*priv->rxqs)[rx_queue_id];
 883         if (!rxq_data) {
 884                 rte_errno = EINVAL;
 885                 return -rte_errno;
 886         }
 887         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 888         if (rxq_ctrl->irq) {
 889                 struct mlx5_rxq_obj *rxq_obj;
 890
 891                 rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 892                 if (!rxq_obj) {
 893                         rte_errno = EINVAL;
 894                         return -rte_errno;
 895                 }
 896                 mlx5_arm_cq(rxq_data, rxq_data->cq_arm_sn);
 897                 mlx5_rxq_obj_release(rxq_obj);
 898         }
 899         return 0;
 900 }
 901
 902 /**
 903  * DPDK callback for Rx queue interrupt disable.
 904  *
 905  * @param dev
 906  *   Pointer to Ethernet device structure.
 907  * @param rx_queue_id
 908  *   Rx queue number.
 909  *
 910  * @return
 911  *   0 on success, a negative errno value otherwise and rte_errno is set.
 912  */
 913 int
 914 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 915 {
 916         struct mlx5_priv *priv = dev->data->dev_private;
 917         struct mlx5_rxq_data *rxq_data;
 918         struct mlx5_rxq_ctrl *rxq_ctrl;
 919         struct mlx5_rxq_obj *rxq_obj = NULL;
 920         struct ibv_cq *ev_cq;
 921         void *ev_ctx;
 922         int ret;
 923
 924         rxq_data = (*priv->rxqs)[rx_queue_id];
 925         if (!rxq_data) {
 926                 rte_errno = EINVAL;
 927                 return -rte_errno;
 928         }
 929         rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
 930         if (!rxq_ctrl->irq)
 931                 return 0;
 932         rxq_obj = mlx5_rxq_obj_get(dev, rx_queue_id);
 933         if (!rxq_obj) {
 934                 rte_errno = EINVAL;
 935                 return -rte_errno;
 936         }
 937         ret = mlx5_glue->get_cq_event(rxq_obj->channel, &ev_cq, &ev_ctx);
 938         if (ret || ev_cq != rxq_obj->cq) {
 939                 rte_errno = EINVAL;
 940                 goto exit;
 941         }
 942         rxq_data->cq_arm_sn++;
 943         mlx5_glue->ack_cq_events(rxq_obj->cq, 1);
 944         mlx5_rxq_obj_release(rxq_obj);
 945         return 0;
 946 exit:
 947         ret = rte_errno; /* Save rte_errno before cleanup. */
 948         if (rxq_obj)
 949                 mlx5_rxq_obj_release(rxq_obj);
 950         DRV_LOG(WARNING, "port %u unable to disable interrupt on Rx queue %d",
 951                 dev->data->port_id, rx_queue_id);
 952         rte_errno = ret; /* Restore rte_errno. */
 953         return -rte_errno;
 954 }
 955
 956 /**
 957  * Create a CQ Verbs object.
 958  *
 959  * @param dev
 960  *   Pointer to Ethernet device.
 961  * @param priv
 962  *   Pointer to device private data.
 963  * @param rxq_data
 964  *   Pointer to Rx queue data.
 965  * @param cqe_n
 966  *   Number of CQEs in CQ.
 967  * @param rxq_obj
 968  *   Pointer to Rx queue object data.
 969  *
 970  * @return
 971  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
 972  */
 973 static struct ibv_cq *
 974 mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
 975                 struct mlx5_rxq_data *rxq_data,
 976                 unsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)
 977 {
 978         struct {
 979                 struct ibv_cq_init_attr_ex ibv;
 980                 struct mlx5dv_cq_init_attr mlx5;
 981         } cq_attr;
 982
 983         cq_attr.ibv = (struct ibv_cq_init_attr_ex){
 984                 .cqe = cqe_n,
 985                 .channel = rxq_obj->channel,
 986                 .comp_mask = 0,
 987         };
 988         cq_attr.mlx5 = (struct mlx5dv_cq_init_attr){
 989                 .comp_mask = 0,
 990         };
 991         if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
 992             !rxq_data->lro) {
 993                 cq_attr.mlx5.comp_mask |=
 994                                 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;
 995 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 996                 cq_attr.mlx5.cqe_comp_res_format =
 997                                 mlx5_rxq_mprq_enabled(rxq_data) ?
 998                                 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :
 999                                 MLX5DV_CQE_RES_FORMAT_HASH;
1000 #else
1001                 cq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;
1002 #endif
1003                 /*
1004                  * For vectorized Rx, it must not be doubled in order to
1005                  * make cq_ci and rq_ci aligned.
1006                  */
1007                 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
1008                         cq_attr.ibv.cqe *= 2;
1009         } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
1010                 DRV_LOG(DEBUG,
1011                         "port %u Rx CQE compression is disabled for HW"
1012                         " timestamp",
1013                         dev->data->port_id);
1014         } else if (priv->config.cqe_comp && rxq_data->lro) {
1015                 DRV_LOG(DEBUG,
1016                         "port %u Rx CQE compression is disabled for LRO",
1017                         dev->data->port_id);
1018         }
1019 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1020         if (priv->config.cqe_pad) {
1021                 cq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;
1022                 cq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;
1023         }
1024 #endif
1025         return mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,
1026                                                               &cq_attr.ibv,
1027                                                               &cq_attr.mlx5));
1028 }
1029
1030 /**
1031  * Create a WQ Verbs object.
1032  *
1033  * @param dev
1034  *   Pointer to Ethernet device.
1035  * @param priv
1036  *   Pointer to device private data.
1037  * @param rxq_data
1038  *   Pointer to Rx queue data.
1039  * @param idx
1040  *   Queue index in DPDK Rx queue array
1041  * @param wqe_n
1042  *   Number of WQEs in WQ.
1043  * @param rxq_obj
1044  *   Pointer to Rx queue object data.
1045  *
1046  * @return
1047  *   The Verbs object initialised, NULL otherwise and rte_errno is set.
1048  */
1049 static struct ibv_wq *
1050 mlx5_ibv_wq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,
1051                 struct mlx5_rxq_data *rxq_data, uint16_t idx,
1052                 unsigned int wqe_n, struct mlx5_rxq_obj *rxq_obj)
1053 {
1054         struct {
1055                 struct ibv_wq_init_attr ibv;
1056 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1057                 struct mlx5dv_wq_init_attr mlx5;
1058 #endif
1059         } wq_attr;
1060
1061         wq_attr.ibv = (struct ibv_wq_init_attr){
1062                 .wq_context = NULL, /* Could be useful in the future. */
1063                 .wq_type = IBV_WQT_RQ,
1064                 /* Max number of outstanding WRs. */
1065                 .max_wr = wqe_n >> rxq_data->sges_n,
1066                 /* Max number of scatter/gather elements in a WR. */
1067                 .max_sge = 1 << rxq_data->sges_n,
1068                 .pd = priv->sh->pd,
1069                 .cq = rxq_obj->cq,
1070                 .comp_mask = IBV_WQ_FLAGS_CVLAN_STRIPPING | 0,
1071                 .create_flags = (rxq_data->vlan_strip ?
1072                                  IBV_WQ_FLAGS_CVLAN_STRIPPING : 0),
1073         };
1074         /* By default, FCS (CRC) is stripped by hardware. */
1075         if (rxq_data->crc_present) {
1076                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;
1077                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1078         }
1079         if (priv->config.hw_padding) {
1080 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1081                 wq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;
1082                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1083 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1084                 wq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;
1085                 wq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;
1086 #endif
1087         }
1088 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1089         wq_attr.mlx5 = (struct mlx5dv_wq_init_attr){
1090                 .comp_mask = 0,
1091         };
1092         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1093                 struct mlx5dv_striding_rq_init_attr *mprq_attr =
1094                                                 &wq_attr.mlx5.striding_rq_attrs;
1095
1096                 wq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;
1097                 *mprq_attr = (struct mlx5dv_striding_rq_init_attr){
1098                         .single_stride_log_num_of_bytes = rxq_data->strd_sz_n,
1099                         .single_wqe_log_num_of_strides = rxq_data->strd_num_n,
1100                         .two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,
1101                 };
1102         }
1103         rxq_obj->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,
1104                                               &wq_attr.mlx5);
1105 #else
1106         rxq_obj->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);
1107 #endif
1108         if (rxq_obj->wq) {
1109                 /*
1110                  * Make sure number of WRs*SGEs match expectations since a queue
1111                  * cannot allocate more than "desc" buffers.
1112                  */
1113                 if (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||
1114                     wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {
1115                         DRV_LOG(ERR,
1116                                 "port %u Rx queue %u requested %u*%u but got"
1117                                 " %u*%u WRs*SGEs",
1118                                 dev->data->port_id, idx,
1119                                 wqe_n >> rxq_data->sges_n,
1120                                 (1 << rxq_data->sges_n),
1121                                 wq_attr.ibv.max_wr, wq_attr.ibv.max_sge);
1122                         claim_zero(mlx5_glue->destroy_wq(rxq_obj->wq));
1123                         rxq_obj->wq = NULL;
1124                         rte_errno = EINVAL;
1125                 }
1126         }
1127         return rxq_obj->wq;
1128 }
1129
1130 /**
1131  * Fill common fields of create RQ attributes structure.
1132  *
1133  * @param rxq_data
1134  *   Pointer to Rx queue data.
1135  * @param cqn
1136  *   CQ number to use with this RQ.
1137  * @param rq_attr
1138  *   RQ attributes structure to fill..
1139  */
1140 static void
1141 mlx5_devx_create_rq_attr_fill(struct mlx5_rxq_data *rxq_data, uint32_t cqn,
1142                               struct mlx5_devx_create_rq_attr *rq_attr)
1143 {
1144         rq_attr->state = MLX5_RQC_STATE_RST;
1145         rq_attr->vsd = (rxq_data->vlan_strip) ? 0 : 1;
1146         rq_attr->cqn = cqn;
1147         rq_attr->scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
1148 }
1149
1150 /**
1151  * Fill common fields of DevX WQ attributes structure.
1152  *
1153  * @param priv
1154  *   Pointer to device private data.
1155  * @param rxq_ctrl
1156  *   Pointer to Rx queue control structure.
1157  * @param wq_attr
1158  *   WQ attributes structure to fill..
1159  */
1160 static void
1161 mlx5_devx_wq_attr_fill(struct mlx5_priv *priv, struct mlx5_rxq_ctrl *rxq_ctrl,
1162                        struct mlx5_devx_wq_attr *wq_attr)
1163 {
1164         wq_attr->end_padding_mode = priv->config.cqe_pad ?
1165                                         MLX5_WQ_END_PAD_MODE_ALIGN :
1166                                         MLX5_WQ_END_PAD_MODE_NONE;
1167         wq_attr->pd = priv->sh->pdn;
1168         wq_attr->dbr_addr = rxq_ctrl->dbr_offset;
1169         wq_attr->dbr_umem_id = rxq_ctrl->dbr_umem_id;
1170         wq_attr->dbr_umem_valid = 1;
1171         wq_attr->wq_umem_id = rxq_ctrl->wq_umem->umem_id;
1172         wq_attr->wq_umem_valid = 1;
1173 }
1174
1175 /**
1176  * Create a RQ object using DevX.
1177  *
1178  * @param dev
1179  *   Pointer to Ethernet device.
1180  * @param idx
1181  *   Queue index in DPDK Rx queue array
1182  * @param cqn
1183  *   CQ number to use with this RQ.
1184  *
1185  * @return
1186  *   The DevX object initialised, NULL otherwise and rte_errno is set.
1187  */
1188 static struct mlx5_devx_obj *
1189 mlx5_devx_rq_new(struct rte_eth_dev *dev, uint16_t idx, uint32_t cqn)
1190 {
1191         struct mlx5_priv *priv = dev->data->dev_private;
1192         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1193         struct mlx5_rxq_ctrl *rxq_ctrl =
1194                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1195         struct mlx5_devx_create_rq_attr rq_attr;
1196         uint32_t wqe_n = 1 << (rxq_data->elts_n - rxq_data->sges_n);
1197         uint32_t wq_size = 0;
1198         uint32_t wqe_size = 0;
1199         uint32_t log_wqe_size = 0;
1200         void *buf = NULL;
1201         struct mlx5_devx_obj *rq;
1202
1203         memset(&rq_attr, 0, sizeof(rq_attr));
1204         /* Fill RQ attributes. */
1205         rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
1206         rq_attr.flush_in_error_en = 1;
1207         mlx5_devx_create_rq_attr_fill(rxq_data, cqn, &rq_attr);
1208         /* Fill WQ attributes for this RQ. */
1209         if (mlx5_rxq_mprq_enabled(rxq_data)) {
1210                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
1211                 /*
1212                  * Number of strides in each WQE:
1213                  * 512*2^single_wqe_log_num_of_strides.
1214                  */
1215                 rq_attr.wq_attr.single_wqe_log_num_of_strides =
1216                                 rxq_data->strd_num_n -
1217                                 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1218                 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
1219                 rq_attr.wq_attr.single_stride_log_num_of_bytes =
1220                                 rxq_data->strd_sz_n -
1221                                 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1222                 wqe_size = sizeof(struct mlx5_wqe_mprq);
1223         } else {
1224                 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
1225                 wqe_size = sizeof(struct mlx5_wqe_data_seg);
1226         }
1227         log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
1228         rq_attr.wq_attr.log_wq_stride = log_wqe_size;
1229         rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
1230         /* Calculate and allocate WQ memory space. */
1231         wqe_size = 1 << log_wqe_size; /* round up power of two.*/
1232         wq_size = wqe_n * wqe_size;
1233         buf = rte_calloc_socket(__func__, 1, wq_size, MLX5_WQE_BUF_ALIGNMENT,
1234                                 rxq_ctrl->socket);
1235         if (!buf)
1236                 return NULL;
1237         rxq_data->wqes = buf;
1238         rxq_ctrl->wq_umem = mlx5_glue->devx_umem_reg(priv->sh->ctx,
1239                                                      buf, wq_size, 0);
1240         if (!rxq_ctrl->wq_umem) {
1241                 rte_free(buf);
1242                 return NULL;
1243         }
1244         mlx5_devx_wq_attr_fill(priv, rxq_ctrl, &rq_attr.wq_attr);
1245         rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &rq_attr, rxq_ctrl->socket);
1246         if (!rq)
1247                 rxq_release_rq_resources(rxq_ctrl);
1248         return rq;
1249 }
1250
1251 /**
1252  * Create the Rx hairpin queue object.
1253  *
1254  * @param dev
1255  *   Pointer to Ethernet device.
1256  * @param idx
1257  *   Queue index in DPDK Rx queue array
1258  *
1259  * @return
1260  *   The hairpin DevX object initialised, NULL otherwise and rte_errno is set.
1261  */
1262 static struct mlx5_rxq_obj *
1263 mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1264 {
1265         struct mlx5_priv *priv = dev->data->dev_private;
1266         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1267         struct mlx5_rxq_ctrl *rxq_ctrl =
1268                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1269         struct mlx5_devx_create_rq_attr attr = { 0 };
1270         struct mlx5_rxq_obj *tmpl = NULL;
1271         uint32_t max_wq_data;
1272
1273         MLX5_ASSERT(rxq_data);
1274         MLX5_ASSERT(!rxq_ctrl->obj);
1275         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1276                                  rxq_ctrl->socket);
1277         if (!tmpl) {
1278                 DRV_LOG(ERR,
1279                         "port %u Rx queue %u cannot allocate verbs resources",
1280                         dev->data->port_id, rxq_data->idx);
1281                 rte_errno = ENOMEM;
1282                 return NULL;
1283         }
1284         tmpl->type = MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN;
1285         tmpl->rxq_ctrl = rxq_ctrl;
1286         attr.hairpin = 1;
1287         max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1288         /* Jumbo frames > 9KB should be supported, and more packets. */
1289         if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1290                 if (priv->config.log_hp_size > max_wq_data) {
1291                         DRV_LOG(ERR, "total data size %u power of 2 is "
1292                                 "too large for hairpin",
1293                                 priv->config.log_hp_size);
1294                         rte_free(tmpl);
1295                         rte_errno = ERANGE;
1296                         return NULL;
1297                 }
1298                 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1299         } else {
1300                 attr.wq_attr.log_hairpin_data_sz =
1301                                 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1302                                  max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1303         }
1304         /* Set the packets number to the maximum value for performance. */
1305         attr.wq_attr.log_hairpin_num_packets =
1306                         attr.wq_attr.log_hairpin_data_sz -
1307                         MLX5_HAIRPIN_QUEUE_STRIDE;
1308         tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->ctx, &attr,
1309                                            rxq_ctrl->socket);
1310         if (!tmpl->rq) {
1311                 DRV_LOG(ERR,
1312                         "port %u Rx hairpin queue %u can't create rq object",
1313                         dev->data->port_id, idx);
1314                 rte_free(tmpl);
1315                 rte_errno = errno;
1316                 return NULL;
1317         }
1318         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1319                 idx, (void *)&tmpl);
1320         rte_atomic32_inc(&tmpl->refcnt);
1321         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1322         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1323         return tmpl;
1324 }
1325
1326 /**
1327  * Create the Rx queue Verbs/DevX object.
1328  *
1329  * @param dev
1330  *   Pointer to Ethernet device.
1331  * @param idx
1332  *   Queue index in DPDK Rx queue array
1333  * @param type
1334  *   Type of Rx queue object to create.
1335  *
1336  * @return
1337  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
1338  */
1339 struct mlx5_rxq_obj *
1340 mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
1341                  enum mlx5_rxq_obj_type type)
1342 {
1343         struct mlx5_priv *priv = dev->data->dev_private;
1344         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[idx];
1345         struct mlx5_rxq_ctrl *rxq_ctrl =
1346                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
1347         struct ibv_wq_attr mod;
1348         unsigned int cqe_n;
1349         unsigned int wqe_n = 1 << rxq_data->elts_n;
1350         struct mlx5_rxq_obj *tmpl = NULL;
1351         struct mlx5dv_cq cq_info;
1352         struct mlx5dv_rwq rwq;
1353         int ret = 0;
1354         struct mlx5dv_obj obj;
1355
1356         MLX5_ASSERT(rxq_data);
1357         MLX5_ASSERT(!rxq_ctrl->obj);
1358         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
1359                 return mlx5_rxq_obj_hairpin_new(dev, idx);
1360         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;
1361         priv->verbs_alloc_ctx.obj = rxq_ctrl;
1362         tmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,
1363                                  rxq_ctrl->socket);
1364         if (!tmpl) {
1365                 DRV_LOG(ERR,
1366                         "port %u Rx queue %u cannot allocate verbs resources",
1367                         dev->data->port_id, rxq_data->idx);
1368                 rte_errno = ENOMEM;
1369                 goto error;
1370         }
1371         tmpl->type = type;
1372         tmpl->rxq_ctrl = rxq_ctrl;
1373         if (rxq_ctrl->irq) {
1374                 tmpl->channel = mlx5_glue->create_comp_channel(priv->sh->ctx);
1375                 if (!tmpl->channel) {
1376                         DRV_LOG(ERR, "port %u: comp channel creation failure",
1377                                 dev->data->port_id);
1378                         rte_errno = ENOMEM;
1379                         goto error;
1380                 }
1381         }
1382         if (mlx5_rxq_mprq_enabled(rxq_data))
1383                 cqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;
1384         else
1385                 cqe_n = wqe_n  - 1;
1386         tmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);
1387         if (!tmpl->cq) {
1388                 DRV_LOG(ERR, "port %u Rx queue %u CQ creation failure",
1389                         dev->data->port_id, idx);
1390                 rte_errno = ENOMEM;
1391                 goto error;
1392         }
1393         obj.cq.in = tmpl->cq;
1394         obj.cq.out = &cq_info;
1395         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_CQ);
1396         if (ret) {
1397                 rte_errno = ret;
1398                 goto error;
1399         }
1400         if (cq_info.cqe_size != RTE_CACHE_LINE_SIZE) {
1401                 DRV_LOG(ERR,
1402                         "port %u wrong MLX5_CQE_SIZE environment variable"
1403                         " value: it should be set to %u",
1404                         dev->data->port_id, RTE_CACHE_LINE_SIZE);
1405                 rte_errno = EINVAL;
1406                 goto error;
1407         }
1408         DRV_LOG(DEBUG, "port %u device_attr.max_qp_wr is %d",
1409                 dev->data->port_id, priv->sh->device_attr.max_qp_wr);
1410         DRV_LOG(DEBUG, "port %u device_attr.max_sge is %d",
1411                 dev->data->port_id, priv->sh->device_attr.max_sge);
1412         /* Allocate door-bell for types created with DevX. */
1413         if (tmpl->type != MLX5_RXQ_OBJ_TYPE_IBV) {
1414                 struct mlx5_devx_dbr_page *dbr_page;
1415                 int64_t dbr_offset;
1416
1417                 dbr_offset = mlx5_get_dbr(priv->sh->ctx, &priv->dbrpgs,
1418                                           &dbr_page);
1419                 if (dbr_offset < 0)
1420                         goto error;
1421                 rxq_ctrl->dbr_offset = dbr_offset;
1422                 rxq_ctrl->dbr_umem_id = mlx5_os_get_umem_id(dbr_page->umem);
1423                 rxq_ctrl->dbr_umem_id_valid = 1;
1424                 rxq_data->rq_db = (uint32_t *)((uintptr_t)dbr_page->dbrs +
1425                                                (uintptr_t)rxq_ctrl->dbr_offset);
1426         }
1427         if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV) {
1428                 tmpl->wq = mlx5_ibv_wq_new(dev, priv, rxq_data, idx, wqe_n,
1429                                            tmpl);
1430                 if (!tmpl->wq) {
1431                         DRV_LOG(ERR, "port %u Rx queue %u WQ creation failure",
1432                                 dev->data->port_id, idx);
1433                         rte_errno = ENOMEM;
1434                         goto error;
1435                 }
1436                 /* Change queue state to ready. */
1437                 mod = (struct ibv_wq_attr){
1438                         .attr_mask = IBV_WQ_ATTR_STATE,
1439                         .wq_state = IBV_WQS_RDY,
1440                 };
1441                 ret = mlx5_glue->modify_wq(tmpl->wq, &mod);
1442                 if (ret) {
1443                         DRV_LOG(ERR,
1444                                 "port %u Rx queue %u WQ state to IBV_WQS_RDY"
1445                                 " failed", dev->data->port_id, idx);
1446                         rte_errno = ret;
1447                         goto error;
1448                 }
1449                 obj.rwq.in = tmpl->wq;
1450                 obj.rwq.out = &rwq;
1451                 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_RWQ);
1452                 if (ret) {
1453                         rte_errno = ret;
1454                         goto error;
1455                 }
1456                 rxq_data->wqes = rwq.buf;
1457                 rxq_data->rq_db = rwq.dbrec;
1458         } else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ) {
1459                 struct mlx5_devx_modify_rq_attr rq_attr;
1460
1461                 memset(&rq_attr, 0, sizeof(rq_attr));
1462                 tmpl->rq = mlx5_devx_rq_new(dev, idx, cq_info.cqn);
1463                 if (!tmpl->rq) {
1464                         DRV_LOG(ERR, "port %u Rx queue %u RQ creation failure",
1465                                 dev->data->port_id, idx);
1466                         rte_errno = ENOMEM;
1467                         goto error;
1468                 }
1469                 /* Change queue state to ready. */
1470                 rq_attr.rq_state = MLX5_RQC_STATE_RST;
1471                 rq_attr.state = MLX5_RQC_STATE_RDY;
1472                 ret = mlx5_devx_cmd_modify_rq(tmpl->rq, &rq_attr);
1473                 if (ret)
1474                         goto error;
1475         }
1476         /* Fill the rings. */
1477         rxq_data->cqe_n = log2above(cq_info.cqe_cnt);
1478         rxq_data->cq_db = cq_info.dbrec;
1479         rxq_data->cqes = (volatile struct mlx5_cqe (*)[])(uintptr_t)cq_info.buf;
1480         rxq_data->cq_uar = cq_info.cq_uar;
1481         rxq_data->cqn = cq_info.cqn;
1482         rxq_data->cq_arm_sn = 0;
1483         mlx5_rxq_initialize(rxq_data);
1484         rxq_data->cq_ci = 0;
1485         DRV_LOG(DEBUG, "port %u rxq %u updated with %p", dev->data->port_id,
1486                 idx, (void *)&tmpl);
1487         rte_atomic32_inc(&tmpl->refcnt);
1488         LIST_INSERT_HEAD(&priv->rxqsobj, tmpl, next);
1489         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1490         return tmpl;
1491 error:
1492         if (tmpl) {
1493                 ret = rte_errno; /* Save rte_errno before cleanup. */
1494                 if (tmpl->type == MLX5_RXQ_OBJ_TYPE_IBV && tmpl->wq)
1495                         claim_zero(mlx5_glue->destroy_wq(tmpl->wq));
1496                 else if (tmpl->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ && tmpl->rq)
1497                         claim_zero(mlx5_devx_cmd_destroy(tmpl->rq));
1498                 if (tmpl->cq)
1499                         claim_zero(mlx5_glue->destroy_cq(tmpl->cq));
1500                 if (tmpl->channel)
1501                         claim_zero(mlx5_glue->destroy_comp_channel
1502                                                         (tmpl->channel));
1503                 rte_free(tmpl);
1504                 rte_errno = ret; /* Restore rte_errno. */
1505         }
1506         if (type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ)
1507                 rxq_release_rq_resources(rxq_ctrl);
1508         priv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_NONE;
1509         return NULL;
1510 }
1511
1512 /**
1513  * Verify the Rx queue objects list is empty
1514  *
1515  * @param dev
1516  *   Pointer to Ethernet device.
1517  *
1518  * @return
1519  *   The number of objects not released.
1520  */
1521 int
1522 mlx5_rxq_obj_verify(struct rte_eth_dev *dev)
1523 {
1524         struct mlx5_priv *priv = dev->data->dev_private;
1525         int ret = 0;
1526         struct mlx5_rxq_obj *rxq_obj;
1527
1528         LIST_FOREACH(rxq_obj, &priv->rxqsobj, next) {
1529                 DRV_LOG(DEBUG, "port %u Rx queue %u still referenced",
1530                         dev->data->port_id, rxq_obj->rxq_ctrl->rxq.idx);
1531                 ++ret;
1532         }
1533         return ret;
1534 }
1535
1536 /**
1537  * Callback function to initialize mbufs for Multi-Packet RQ.
1538  */
1539 static inline void
1540 mlx5_mprq_buf_init(struct rte_mempool *mp, void *opaque_arg,
1541                     void *_m, unsigned int i __rte_unused)
1542 {
1543         struct mlx5_mprq_buf *buf = _m;
1544         struct rte_mbuf_ext_shared_info *shinfo;
1545         unsigned int strd_n = (unsigned int)(uintptr_t)opaque_arg;
1546         unsigned int j;
1547
1548         memset(_m, 0, sizeof(*buf));
1549         buf->mp = mp;
1550         rte_atomic16_set(&buf->refcnt, 1);
1551         for (j = 0; j != strd_n; ++j) {
1552                 shinfo = &buf->shinfos[j];
1553                 shinfo->free_cb = mlx5_mprq_buf_free_cb;
1554                 shinfo->fcb_opaque = buf;
1555         }
1556 }
1557
1558 /**
1559  * Free mempool of Multi-Packet RQ.
1560  *
1561  * @param dev
1562  *   Pointer to Ethernet device.
1563  *
1564  * @return
1565  *   0 on success, negative errno value on failure.
1566  */
1567 int
1568 mlx5_mprq_free_mp(struct rte_eth_dev *dev)
1569 {
1570         struct mlx5_priv *priv = dev->data->dev_private;
1571         struct rte_mempool *mp = priv->mprq_mp;
1572         unsigned int i;
1573
1574         if (mp == NULL)
1575                 return 0;
1576         DRV_LOG(DEBUG, "port %u freeing mempool (%s) for Multi-Packet RQ",
1577                 dev->data->port_id, mp->name);
1578         /*
1579          * If a buffer in the pool has been externally attached to a mbuf and it
1580          * is still in use by application, destroying the Rx queue can spoil
1581          * the packet. It is unlikely to happen but if application dynamically
1582          * creates and destroys with holding Rx packets, this can happen.
1583          *
1584          * TODO: It is unavoidable for now because the mempool for Multi-Packet
1585          * RQ isn't provided by application but managed by PMD.
1586          */
1587         if (!rte_mempool_full(mp)) {
1588                 DRV_LOG(ERR,
1589                         "port %u mempool for Multi-Packet RQ is still in use",
1590                         dev->data->port_id);
1591                 rte_errno = EBUSY;
1592                 return -rte_errno;
1593         }
1594         rte_mempool_free(mp);
1595         /* Unset mempool for each Rx queue. */
1596         for (i = 0; i != priv->rxqs_n; ++i) {
1597                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1598
1599                 if (rxq == NULL)
1600                         continue;
1601                 rxq->mprq_mp = NULL;
1602         }
1603         priv->mprq_mp = NULL;
1604         return 0;
1605 }
1606
1607 /**
1608  * Allocate a mempool for Multi-Packet RQ. All configured Rx queues share the
1609  * mempool. If already allocated, reuse it if there're enough elements.
1610  * Otherwise, resize it.
1611  *
1612  * @param dev
1613  *   Pointer to Ethernet device.
1614  *
1615  * @return
1616  *   0 on success, negative errno value on failure.
1617  */
1618 int
1619 mlx5_mprq_alloc_mp(struct rte_eth_dev *dev)
1620 {
1621         struct mlx5_priv *priv = dev->data->dev_private;
1622         struct rte_mempool *mp = priv->mprq_mp;
1623         char name[RTE_MEMPOOL_NAMESIZE];
1624         unsigned int desc = 0;
1625         unsigned int buf_len;
1626         unsigned int obj_num;
1627         unsigned int obj_size;
1628         unsigned int strd_num_n = 0;
1629         unsigned int strd_sz_n = 0;
1630         unsigned int i;
1631         unsigned int n_ibv = 0;
1632
1633         if (!mlx5_mprq_enabled(dev))
1634                 return 0;
1635         /* Count the total number of descriptors configured. */
1636         for (i = 0; i != priv->rxqs_n; ++i) {
1637                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1638                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1639                         (rxq, struct mlx5_rxq_ctrl, rxq);
1640
1641                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1642                         continue;
1643                 n_ibv++;
1644                 desc += 1 << rxq->elts_n;
1645                 /* Get the max number of strides. */
1646                 if (strd_num_n < rxq->strd_num_n)
1647                         strd_num_n = rxq->strd_num_n;
1648                 /* Get the max size of a stride. */
1649                 if (strd_sz_n < rxq->strd_sz_n)
1650                         strd_sz_n = rxq->strd_sz_n;
1651         }
1652         MLX5_ASSERT(strd_num_n && strd_sz_n);
1653         buf_len = (1 << strd_num_n) * (1 << strd_sz_n);
1654         obj_size = sizeof(struct mlx5_mprq_buf) + buf_len + (1 << strd_num_n) *
1655                 sizeof(struct rte_mbuf_ext_shared_info) + RTE_PKTMBUF_HEADROOM;
1656         /*
1657          * Received packets can be either memcpy'd or externally referenced. In
1658          * case that the packet is attached to an mbuf as an external buffer, as
1659          * it isn't possible to predict how the buffers will be queued by
1660          * application, there's no option to exactly pre-allocate needed buffers
1661          * in advance but to speculatively prepares enough buffers.
1662          *
1663          * In the data path, if this Mempool is depleted, PMD will try to memcpy
1664          * received packets to buffers provided by application (rxq->mp) until
1665          * this Mempool gets available again.
1666          */
1667         desc *= 4;
1668         obj_num = desc + MLX5_MPRQ_MP_CACHE_SZ * n_ibv;
1669         /*
1670          * rte_mempool_create_empty() has sanity check to refuse large cache
1671          * size compared to the number of elements.
1672          * CACHE_FLUSHTHRESH_MULTIPLIER is defined in a C file, so using a
1673          * constant number 2 instead.
1674          */
1675         obj_num = RTE_MAX(obj_num, MLX5_MPRQ_MP_CACHE_SZ * 2);
1676         /* Check a mempool is already allocated and if it can be resued. */
1677         if (mp != NULL && mp->elt_size >= obj_size && mp->size >= obj_num) {
1678                 DRV_LOG(DEBUG, "port %u mempool %s is being reused",
1679                         dev->data->port_id, mp->name);
1680                 /* Reuse. */
1681                 goto exit;
1682         } else if (mp != NULL) {
1683                 DRV_LOG(DEBUG, "port %u mempool %s should be resized, freeing it",
1684                         dev->data->port_id, mp->name);
1685                 /*
1686                  * If failed to free, which means it may be still in use, no way
1687                  * but to keep using the existing one. On buffer underrun,
1688                  * packets will be memcpy'd instead of external buffer
1689                  * attachment.
1690                  */
1691                 if (mlx5_mprq_free_mp(dev)) {
1692                         if (mp->elt_size >= obj_size)
1693                                 goto exit;
1694                         else
1695                                 return -rte_errno;
1696                 }
1697         }
1698         snprintf(name, sizeof(name), "port-%u-mprq", dev->data->port_id);
1699         mp = rte_mempool_create(name, obj_num, obj_size, MLX5_MPRQ_MP_CACHE_SZ,
1700                                 0, NULL, NULL, mlx5_mprq_buf_init,
1701                                 (void *)(uintptr_t)(1 << strd_num_n),
1702                                 dev->device->numa_node, 0);
1703         if (mp == NULL) {
1704                 DRV_LOG(ERR,
1705                         "port %u failed to allocate a mempool for"
1706                         " Multi-Packet RQ, count=%u, size=%u",
1707                         dev->data->port_id, obj_num, obj_size);
1708                 rte_errno = ENOMEM;
1709                 return -rte_errno;
1710         }
1711         priv->mprq_mp = mp;
1712 exit:
1713         /* Set mempool for each Rx queue. */
1714         for (i = 0; i != priv->rxqs_n; ++i) {
1715                 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
1716                 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
1717                         (rxq, struct mlx5_rxq_ctrl, rxq);
1718
1719                 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
1720                         continue;
1721                 rxq->mprq_mp = mp;
1722         }
1723         DRV_LOG(INFO, "port %u Multi-Packet RQ is configured",
1724                 dev->data->port_id);
1725         return 0;
1726 }
1727
1728 #define MLX5_MAX_TCP_HDR_OFFSET ((unsigned int)(sizeof(struct rte_ether_hdr) + \
1729                                         sizeof(struct rte_vlan_hdr) * 2 + \
1730                                         sizeof(struct rte_ipv6_hdr)))
1731 #define MAX_TCP_OPTION_SIZE 40u
1732 #define MLX5_MAX_LRO_HEADER_FIX ((unsigned int)(MLX5_MAX_TCP_HDR_OFFSET + \
1733                                  sizeof(struct rte_tcp_hdr) + \
1734                                  MAX_TCP_OPTION_SIZE))
1735
1736 /**
1737  * Adjust the maximum LRO massage size.
1738  *
1739  * @param dev
1740  *   Pointer to Ethernet device.
1741  * @param idx
1742  *   RX queue index.
1743  * @param max_lro_size
1744  *   The maximum size for LRO packet.
1745  */
1746 static void
1747 mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,
1748                              uint32_t max_lro_size)
1749 {
1750         struct mlx5_priv *priv = dev->data->dev_private;
1751
1752         if (priv->config.hca_attr.lro_max_msg_sz_mode ==
1753             MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 && max_lro_size >
1754             MLX5_MAX_TCP_HDR_OFFSET)
1755                 max_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;
1756         max_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);
1757         MLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);
1758         max_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;
1759         if (priv->max_lro_msg_size)
1760                 priv->max_lro_msg_size =
1761                         RTE_MIN((uint32_t)priv->max_lro_msg_size, max_lro_size);
1762         else
1763                 priv->max_lro_msg_size = max_lro_size;
1764         DRV_LOG(DEBUG,
1765                 "port %u Rx Queue %u max LRO message size adjusted to %u bytes",
1766                 dev->data->port_id, idx,
1767                 priv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);
1768 }
1769
1770 /**
1771  * Create a DPDK Rx queue.
1772  *
1773  * @param dev
1774  *   Pointer to Ethernet device.
1775  * @param idx
1776  *   RX queue index.
1777  * @param desc
1778  *   Number of descriptors to configure in queue.
1779  * @param socket
1780  *   NUMA socket on which memory must be allocated.
1781  *
1782  * @return
1783  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
1784  */
1785 struct mlx5_rxq_ctrl *
1786 mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
1787              unsigned int socket, const struct rte_eth_rxconf *conf,
1788              struct rte_mempool *mp)
1789 {
1790         struct mlx5_priv *priv = dev->data->dev_private;
1791         struct mlx5_rxq_ctrl *tmpl;
1792         unsigned int mb_len = rte_pktmbuf_data_room_size(mp);
1793         unsigned int mprq_stride_nums;
1794         unsigned int mprq_stride_size;
1795         unsigned int mprq_stride_cap;
1796         struct mlx5_dev_config *config = &priv->config;
1797         /*
1798          * Always allocate extra slots, even if eventually
1799          * the vector Rx will not be used.
1800          */
1801         uint16_t desc_n =
1802                 desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;
1803         uint64_t offloads = conf->offloads |
1804                            dev->data->dev_conf.rxmode.offloads;
1805         unsigned int lro_on_queue = !!(offloads & DEV_RX_OFFLOAD_TCP_LRO);
1806         const int mprq_en = mlx5_check_mprq_support(dev) > 0;
1807         unsigned int max_rx_pkt_len = lro_on_queue ?
1808                         dev->data->dev_conf.rxmode.max_lro_pkt_size :
1809                         dev->data->dev_conf.rxmode.max_rx_pkt_len;
1810         unsigned int non_scatter_min_mbuf_size = max_rx_pkt_len +
1811                                                         RTE_PKTMBUF_HEADROOM;
1812         unsigned int max_lro_size = 0;
1813         unsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;
1814
1815         if (non_scatter_min_mbuf_size > mb_len && !(offloads &
1816                                                     DEV_RX_OFFLOAD_SCATTER)) {
1817                 DRV_LOG(ERR, "port %u Rx queue %u: Scatter offload is not"
1818                         " configured and no enough mbuf space(%u) to contain "
1819                         "the maximum RX packet length(%u) with head-room(%u)",
1820                         dev->data->port_id, idx, mb_len, max_rx_pkt_len,
1821                         RTE_PKTMBUF_HEADROOM);
1822                 rte_errno = ENOSPC;
1823                 return NULL;
1824         }
1825         tmpl = rte_calloc_socket("RXQ", 1,
1826                                  sizeof(*tmpl) +
1827                                  desc_n * sizeof(struct rte_mbuf *),
1828                                  0, socket);
1829         if (!tmpl) {
1830                 rte_errno = ENOMEM;
1831                 return NULL;
1832         }
1833         tmpl->type = MLX5_RXQ_TYPE_STANDARD;
1834         if (mlx5_mr_btree_init(&tmpl->rxq.mr_ctrl.cache_bh,
1835                                MLX5_MR_BTREE_CACHE_N, socket)) {
1836                 /* rte_errno is already set. */
1837                 goto error;
1838         }
1839         tmpl->socket = socket;
1840         if (dev->data->dev_conf.intr_conf.rxq)
1841                 tmpl->irq = 1;
1842         mprq_stride_nums = config->mprq.stride_num_n ?
1843                 config->mprq.stride_num_n : MLX5_MPRQ_STRIDE_NUM_N;
1844         mprq_stride_size = non_scatter_min_mbuf_size <=
1845                 (1U << config->mprq.max_stride_size_n) ?
1846                 log2above(non_scatter_min_mbuf_size) : MLX5_MPRQ_STRIDE_SIZE_N;
1847         mprq_stride_cap = (config->mprq.stride_num_n ?
1848                 (1U << config->mprq.stride_num_n) : (1U << mprq_stride_nums)) *
1849                         (config->mprq.stride_size_n ?
1850                 (1U << config->mprq.stride_size_n) : (1U << mprq_stride_size));
1851         /*
1852          * This Rx queue can be configured as a Multi-Packet RQ if all of the
1853          * following conditions are met:
1854          *  - MPRQ is enabled.
1855          *  - The number of descs is more than the number of strides.
1856          *  - max_rx_pkt_len plus overhead is less than the max size
1857          *    of a stride or mprq_stride_size is specified by a user.
1858          *    Need to nake sure that there are enough stides to encap
1859          *    the maximum packet size in case mprq_stride_size is set.
1860          *  Otherwise, enable Rx scatter if necessary.
1861          */
1862         if (mprq_en && desc > (1U << mprq_stride_nums) &&
1863             (non_scatter_min_mbuf_size <=
1864              (1U << config->mprq.max_stride_size_n) ||
1865              (config->mprq.stride_size_n &&
1866               non_scatter_min_mbuf_size <= mprq_stride_cap))) {
1867                 /* TODO: Rx scatter isn't supported yet. */
1868                 tmpl->rxq.sges_n = 0;
1869                 /* Trim the number of descs needed. */
1870                 desc >>= mprq_stride_nums;
1871                 tmpl->rxq.strd_num_n = config->mprq.stride_num_n ?
1872                         config->mprq.stride_num_n : mprq_stride_nums;
1873                 tmpl->rxq.strd_sz_n = config->mprq.stride_size_n ?
1874                         config->mprq.stride_size_n : mprq_stride_size;
1875                 tmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;
1876                 tmpl->rxq.strd_scatter_en =
1877                                 !!(offloads & DEV_RX_OFFLOAD_SCATTER);
1878                 tmpl->rxq.mprq_max_memcpy_len = RTE_MIN(first_mb_free_size,
1879                                 config->mprq.max_memcpy_len);
1880                 max_lro_size = RTE_MIN(max_rx_pkt_len,
1881                                        (1u << tmpl->rxq.strd_num_n) *
1882                                        (1u << tmpl->rxq.strd_sz_n));
1883                 DRV_LOG(DEBUG,
1884                         "port %u Rx queue %u: Multi-Packet RQ is enabled"
1885                         " strd_num_n = %u, strd_sz_n = %u",
1886                         dev->data->port_id, idx,
1887                         tmpl->rxq.strd_num_n, tmpl->rxq.strd_sz_n);
1888         } else if (max_rx_pkt_len <= first_mb_free_size) {
1889                 tmpl->rxq.sges_n = 0;
1890                 max_lro_size = max_rx_pkt_len;
1891         } else if (offloads & DEV_RX_OFFLOAD_SCATTER) {
1892                 unsigned int size = non_scatter_min_mbuf_size;
1893                 unsigned int sges_n;
1894
1895                 if (lro_on_queue && first_mb_free_size <
1896                     MLX5_MAX_LRO_HEADER_FIX) {
1897                         DRV_LOG(ERR, "Not enough space in the first segment(%u)"
1898                                 " to include the max header size(%u) for LRO",
1899                                 first_mb_free_size, MLX5_MAX_LRO_HEADER_FIX);
1900                         rte_errno = ENOTSUP;
1901                         goto error;
1902                 }
1903                 /*
1904                  * Determine the number of SGEs needed for a full packet
1905                  * and round it to the next power of two.
1906                  */
1907                 sges_n = log2above((size / mb_len) + !!(size % mb_len));
1908                 if (sges_n > MLX5_MAX_LOG_RQ_SEGS) {
1909                         DRV_LOG(ERR,
1910                                 "port %u too many SGEs (%u) needed to handle"
1911                                 " requested maximum packet size %u, the maximum"
1912                                 " supported are %u", dev->data->port_id,
1913                                 1 << sges_n, max_rx_pkt_len,
1914                                 1u << MLX5_MAX_LOG_RQ_SEGS);
1915                         rte_errno = ENOTSUP;
1916                         goto error;
1917                 }
1918                 tmpl->rxq.sges_n = sges_n;
1919                 max_lro_size = max_rx_pkt_len;
1920         }
1921         if (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))
1922                 DRV_LOG(WARNING,
1923                         "port %u MPRQ is requested but cannot be enabled\n"
1924                         " (requested: pkt_sz = %u, desc_num = %u,"
1925                         " rxq_num = %u, stride_sz = %u, stride_num = %u\n"
1926                         "  supported: min_rxqs_num = %u,"
1927                         " min_stride_sz = %u, max_stride_sz = %u).",
1928                         dev->data->port_id, non_scatter_min_mbuf_size,
1929                         desc, priv->rxqs_n,
1930                         config->mprq.stride_size_n ?
1931                                 (1U << config->mprq.stride_size_n) :
1932                                 (1U << mprq_stride_size),
1933                         config->mprq.stride_num_n ?
1934                                 (1U << config->mprq.stride_num_n) :
1935                                 (1U << mprq_stride_nums),
1936                         config->mprq.min_rxqs_num,
1937                         (1U << config->mprq.min_stride_size_n),
1938                         (1U << config->mprq.max_stride_size_n));
1939         DRV_LOG(DEBUG, "port %u maximum number of segments per packet: %u",
1940                 dev->data->port_id, 1 << tmpl->rxq.sges_n);
1941         if (desc % (1 << tmpl->rxq.sges_n)) {
1942                 DRV_LOG(ERR,
1943                         "port %u number of Rx queue descriptors (%u) is not a"
1944                         " multiple of SGEs per packet (%u)",
1945                         dev->data->port_id,
1946                         desc,
1947                         1 << tmpl->rxq.sges_n);
1948                 rte_errno = EINVAL;
1949                 goto error;
1950         }
1951         mlx5_max_lro_msg_size_adjust(dev, idx, max_lro_size);
1952         /* Toggle RX checksum offload if hardware supports it. */
1953         tmpl->rxq.csum = !!(offloads & DEV_RX_OFFLOAD_CHECKSUM);
1954         tmpl->rxq.hw_timestamp = !!(offloads & DEV_RX_OFFLOAD_TIMESTAMP);
1955         /* Configure VLAN stripping. */
1956         tmpl->rxq.vlan_strip = !!(offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
1957         /* By default, FCS (CRC) is stripped by hardware. */
1958         tmpl->rxq.crc_present = 0;
1959         tmpl->rxq.lro = lro_on_queue;
1960         if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
1961                 if (config->hw_fcs_strip) {
1962                         /*
1963                          * RQs used for LRO-enabled TIRs should not be
1964                          * configured to scatter the FCS.
1965                          */
1966                         if (lro_on_queue)
1967                                 DRV_LOG(WARNING,
1968                                         "port %u CRC stripping has been "
1969                                         "disabled but will still be performed "
1970                                         "by hardware, because LRO is enabled",
1971                                         dev->data->port_id);
1972                         else
1973                                 tmpl->rxq.crc_present = 1;
1974                 } else {
1975                         DRV_LOG(WARNING,
1976                                 "port %u CRC stripping has been disabled but will"
1977                                 " still be performed by hardware, make sure MLNX_OFED"
1978                                 " and firmware are up to date",
1979                                 dev->data->port_id);
1980                 }
1981         }
1982         DRV_LOG(DEBUG,
1983                 "port %u CRC stripping is %s, %u bytes will be subtracted from"
1984                 " incoming frames to hide it",
1985                 dev->data->port_id,
1986                 tmpl->rxq.crc_present ? "disabled" : "enabled",
1987                 tmpl->rxq.crc_present << 2);
1988         /* Save port ID. */
1989         tmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&
1990                 (!!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS));
1991         tmpl->rxq.port_id = dev->data->port_id;
1992         tmpl->priv = priv;
1993         tmpl->rxq.mp = mp;
1994         tmpl->rxq.elts_n = log2above(desc);
1995         tmpl->rxq.rq_repl_thresh =
1996                 MLX5_VPMD_RXQ_RPLNSH_THRESH(1 << tmpl->rxq.elts_n);
1997         tmpl->rxq.elts =
1998                 (struct rte_mbuf *(*)[1 << tmpl->rxq.elts_n])(tmpl + 1);
1999 #ifndef RTE_ARCH_64
2000         tmpl->rxq.uar_lock_cq = &priv->sh->uar_lock_cq;
2001 #endif
2002         tmpl->rxq.idx = idx;
2003         rte_atomic32_inc(&tmpl->refcnt);
2004         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2005         return tmpl;
2006 error:
2007         rte_free(tmpl);
2008         return NULL;
2009 }
2010
2011 /**
2012  * Create a DPDK Rx hairpin queue.
2013  *
2014  * @param dev
2015  *   Pointer to Ethernet device.
2016  * @param idx
2017  *   RX queue index.
2018  * @param desc
2019  *   Number of descriptors to configure in queue.
2020  * @param hairpin_conf
2021  *   The hairpin binding configuration.
2022  *
2023  * @return
2024  *   A DPDK queue object on success, NULL otherwise and rte_errno is set.
2025  */
2026 struct mlx5_rxq_ctrl *
2027 mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
2028                      const struct rte_eth_hairpin_conf *hairpin_conf)
2029 {
2030         struct mlx5_priv *priv = dev->data->dev_private;
2031         struct mlx5_rxq_ctrl *tmpl;
2032
2033         tmpl = rte_calloc_socket("RXQ", 1, sizeof(*tmpl), 0, SOCKET_ID_ANY);
2034         if (!tmpl) {
2035                 rte_errno = ENOMEM;
2036                 return NULL;
2037         }
2038         tmpl->type = MLX5_RXQ_TYPE_HAIRPIN;
2039         tmpl->socket = SOCKET_ID_ANY;
2040         tmpl->rxq.rss_hash = 0;
2041         tmpl->rxq.port_id = dev->data->port_id;
2042         tmpl->priv = priv;
2043         tmpl->rxq.mp = NULL;
2044         tmpl->rxq.elts_n = log2above(desc);
2045         tmpl->rxq.elts = NULL;
2046         tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };
2047         tmpl->hairpin_conf = *hairpin_conf;
2048         tmpl->rxq.idx = idx;
2049         rte_atomic32_inc(&tmpl->refcnt);
2050         LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);
2051         return tmpl;
2052 }
2053
2054 /**
2055  * Get a Rx queue.
2056  *
2057  * @param dev
2058  *   Pointer to Ethernet device.
2059  * @param idx
2060  *   RX queue index.
2061  *
2062  * @return
2063  *   A pointer to the queue if it exists, NULL otherwise.
2064  */
2065 struct mlx5_rxq_ctrl *
2066 mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx)
2067 {
2068         struct mlx5_priv *priv = dev->data->dev_private;
2069         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2070
2071         if ((*priv->rxqs)[idx]) {
2072                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2073                                         struct mlx5_rxq_ctrl,
2074                                         rxq);
2075                 mlx5_rxq_obj_get(dev, idx);
2076                 rte_atomic32_inc(&rxq_ctrl->refcnt);
2077         }
2078         return rxq_ctrl;
2079 }
2080
2081 /**
2082  * Release a Rx queue.
2083  *
2084  * @param dev
2085  *   Pointer to Ethernet device.
2086  * @param idx
2087  *   RX queue index.
2088  *
2089  * @return
2090  *   1 while a reference on it exists, 0 when freed.
2091  */
2092 int
2093 mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx)
2094 {
2095         struct mlx5_priv *priv = dev->data->dev_private;
2096         struct mlx5_rxq_ctrl *rxq_ctrl;
2097
2098         if (!(*priv->rxqs)[idx])
2099                 return 0;
2100         rxq_ctrl = container_of((*priv->rxqs)[idx], struct mlx5_rxq_ctrl, rxq);
2101         MLX5_ASSERT(rxq_ctrl->priv);
2102         if (rxq_ctrl->obj && !mlx5_rxq_obj_release(rxq_ctrl->obj))
2103                 rxq_ctrl->obj = NULL;
2104         if (rte_atomic32_dec_and_test(&rxq_ctrl->refcnt)) {
2105                 if (rxq_ctrl->dbr_umem_id_valid)
2106                         claim_zero(mlx5_release_dbr(&priv->dbrpgs,
2107                                                     rxq_ctrl->dbr_umem_id,
2108                                                     rxq_ctrl->dbr_offset));
2109                 if (rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD)
2110                         mlx5_mr_btree_free(&rxq_ctrl->rxq.mr_ctrl.cache_bh);
2111                 LIST_REMOVE(rxq_ctrl, next);
2112                 rte_free(rxq_ctrl);
2113                 (*priv->rxqs)[idx] = NULL;
2114                 return 0;
2115         }
2116         return 1;
2117 }
2118
2119 /**
2120  * Verify the Rx Queue list is empty
2121  *
2122  * @param dev
2123  *   Pointer to Ethernet device.
2124  *
2125  * @return
2126  *   The number of object not released.
2127  */
2128 int
2129 mlx5_rxq_verify(struct rte_eth_dev *dev)
2130 {
2131         struct mlx5_priv *priv = dev->data->dev_private;
2132         struct mlx5_rxq_ctrl *rxq_ctrl;
2133         int ret = 0;
2134
2135         LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) {
2136                 DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced",
2137                         dev->data->port_id, rxq_ctrl->rxq.idx);
2138                 ++ret;
2139         }
2140         return ret;
2141 }
2142
2143 /**
2144  * Get a Rx queue type.
2145  *
2146  * @param dev
2147  *   Pointer to Ethernet device.
2148  * @param idx
2149  *   Rx queue index.
2150  *
2151  * @return
2152  *   The Rx queue type.
2153  */
2154 enum mlx5_rxq_type
2155 mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx)
2156 {
2157         struct mlx5_priv *priv = dev->data->dev_private;
2158         struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
2159
2160         if (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {
2161                 rxq_ctrl = container_of((*priv->rxqs)[idx],
2162                                         struct mlx5_rxq_ctrl,
2163                                         rxq);
2164                 return rxq_ctrl->type;
2165         }
2166         return MLX5_RXQ_TYPE_UNDEFINED;
2167 }
2168
2169 /**
2170  * Create an indirection table.
2171  *
2172  * @param dev
2173  *   Pointer to Ethernet device.
2174  * @param queues
2175  *   Queues entering in the indirection table.
2176  * @param queues_n
2177  *   Number of queues in the array.
2178  *
2179  * @return
2180  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2181  */
2182 static struct mlx5_ind_table_obj *
2183 mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,
2184                        uint32_t queues_n, enum mlx5_ind_tbl_type type)
2185 {
2186         struct mlx5_priv *priv = dev->data->dev_private;
2187         struct mlx5_ind_table_obj *ind_tbl;
2188         unsigned int i = 0, j = 0, k = 0;
2189
2190         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl) +
2191                              queues_n * sizeof(uint16_t), 0);
2192         if (!ind_tbl) {
2193                 rte_errno = ENOMEM;
2194                 return NULL;
2195         }
2196         ind_tbl->type = type;
2197         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2198                 const unsigned int wq_n = rte_is_power_of_2(queues_n) ?
2199                         log2above(queues_n) :
2200                         log2above(priv->config.ind_table_max_size);
2201                 struct ibv_wq *wq[1 << wq_n];
2202
2203                 for (i = 0; i != queues_n; ++i) {
2204                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2205                                                                  queues[i]);
2206                         if (!rxq)
2207                                 goto error;
2208                         wq[i] = rxq->obj->wq;
2209                         ind_tbl->queues[i] = queues[i];
2210                 }
2211                 ind_tbl->queues_n = queues_n;
2212                 /* Finalise indirection table. */
2213                 k = i; /* Retain value of i for use in error case. */
2214                 for (j = 0; k != (unsigned int)(1 << wq_n); ++k, ++j)
2215                         wq[k] = wq[j];
2216                 ind_tbl->ind_table = mlx5_glue->create_rwq_ind_table
2217                         (priv->sh->ctx,
2218                          &(struct ibv_rwq_ind_table_init_attr){
2219                                 .log_ind_tbl_size = wq_n,
2220                                 .ind_tbl = wq,
2221                                 .comp_mask = 0,
2222                         });
2223                 if (!ind_tbl->ind_table) {
2224                         rte_errno = errno;
2225                         goto error;
2226                 }
2227         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2228                 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
2229                 const unsigned int rqt_n =
2230                         1 << (rte_is_power_of_2(queues_n) ?
2231                               log2above(queues_n) :
2232                               log2above(priv->config.ind_table_max_size));
2233
2234                 rqt_attr = rte_calloc(__func__, 1, sizeof(*rqt_attr) +
2235                                       rqt_n * sizeof(uint32_t), 0);
2236                 if (!rqt_attr) {
2237                         DRV_LOG(ERR, "port %u cannot allocate RQT resources",
2238                                 dev->data->port_id);
2239                         rte_errno = ENOMEM;
2240                         goto error;
2241                 }
2242                 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
2243                 rqt_attr->rqt_actual_size = rqt_n;
2244                 for (i = 0; i != queues_n; ++i) {
2245                         struct mlx5_rxq_ctrl *rxq = mlx5_rxq_get(dev,
2246                                                                  queues[i]);
2247                         if (!rxq)
2248                                 goto error;
2249                         rqt_attr->rq_list[i] = rxq->obj->rq->id;
2250                         ind_tbl->queues[i] = queues[i];
2251                 }
2252                 k = i; /* Retain value of i for use in error case. */
2253                 for (j = 0; k != rqt_n; ++k, ++j)
2254                         rqt_attr->rq_list[k] = rqt_attr->rq_list[j];
2255                 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->ctx,
2256                                                         rqt_attr);
2257                 rte_free(rqt_attr);
2258                 if (!ind_tbl->rqt) {
2259                         DRV_LOG(ERR, "port %u cannot create DevX RQT",
2260                                 dev->data->port_id);
2261                         rte_errno = errno;
2262                         goto error;
2263                 }
2264                 ind_tbl->queues_n = queues_n;
2265         }
2266         rte_atomic32_inc(&ind_tbl->refcnt);
2267         LIST_INSERT_HEAD(&priv->ind_tbls, ind_tbl, next);
2268         return ind_tbl;
2269 error:
2270         for (j = 0; j < i; j++)
2271                 mlx5_rxq_release(dev, ind_tbl->queues[j]);
2272         rte_free(ind_tbl);
2273         DEBUG("port %u cannot create indirection table", dev->data->port_id);
2274         return NULL;
2275 }
2276
2277 /**
2278  * Get an indirection table.
2279  *
2280  * @param dev
2281  *   Pointer to Ethernet device.
2282  * @param queues
2283  *   Queues entering in the indirection table.
2284  * @param queues_n
2285  *   Number of queues in the array.
2286  *
2287  * @return
2288  *   An indirection table if found.
2289  */
2290 static struct mlx5_ind_table_obj *
2291 mlx5_ind_table_obj_get(struct rte_eth_dev *dev, const uint16_t *queues,
2292                        uint32_t queues_n)
2293 {
2294         struct mlx5_priv *priv = dev->data->dev_private;
2295         struct mlx5_ind_table_obj *ind_tbl;
2296
2297         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2298                 if ((ind_tbl->queues_n == queues_n) &&
2299                     (memcmp(ind_tbl->queues, queues,
2300                             ind_tbl->queues_n * sizeof(ind_tbl->queues[0]))
2301                      == 0))
2302                         break;
2303         }
2304         if (ind_tbl) {
2305                 unsigned int i;
2306
2307                 rte_atomic32_inc(&ind_tbl->refcnt);
2308                 for (i = 0; i != ind_tbl->queues_n; ++i)
2309                         mlx5_rxq_get(dev, ind_tbl->queues[i]);
2310         }
2311         return ind_tbl;
2312 }
2313
2314 /**
2315  * Release an indirection table.
2316  *
2317  * @param dev
2318  *   Pointer to Ethernet device.
2319  * @param ind_table
2320  *   Indirection table to release.
2321  *
2322  * @return
2323  *   1 while a reference on it exists, 0 when freed.
2324  */
2325 static int
2326 mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
2327                            struct mlx5_ind_table_obj *ind_tbl)
2328 {
2329         unsigned int i;
2330
2331         if (rte_atomic32_dec_and_test(&ind_tbl->refcnt)) {
2332                 if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV)
2333                         claim_zero(mlx5_glue->destroy_rwq_ind_table
2334                                                         (ind_tbl->ind_table));
2335                 else if (ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX)
2336                         claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
2337         }
2338         for (i = 0; i != ind_tbl->queues_n; ++i)
2339                 claim_nonzero(mlx5_rxq_release(dev, ind_tbl->queues[i]));
2340         if (!rte_atomic32_read(&ind_tbl->refcnt)) {
2341                 LIST_REMOVE(ind_tbl, next);
2342                 rte_free(ind_tbl);
2343                 return 0;
2344         }
2345         return 1;
2346 }
2347
2348 /**
2349  * Verify the Rx Queue list is empty
2350  *
2351  * @param dev
2352  *   Pointer to Ethernet device.
2353  *
2354  * @return
2355  *   The number of object not released.
2356  */
2357 int
2358 mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)
2359 {
2360         struct mlx5_priv *priv = dev->data->dev_private;
2361         struct mlx5_ind_table_obj *ind_tbl;
2362         int ret = 0;
2363
2364         LIST_FOREACH(ind_tbl, &priv->ind_tbls, next) {
2365                 DRV_LOG(DEBUG,
2366                         "port %u indirection table obj %p still referenced",
2367                         dev->data->port_id, (void *)ind_tbl);
2368                 ++ret;
2369         }
2370         return ret;
2371 }
2372
2373 /**
2374  * Create an Rx Hash queue.
2375  *
2376  * @param dev
2377  *   Pointer to Ethernet device.
2378  * @param rss_key
2379  *   RSS key for the Rx hash queue.
2380  * @param rss_key_len
2381  *   RSS key length.
2382  * @param hash_fields
2383  *   Verbs protocol hash field to make the RSS on.
2384  * @param queues
2385  *   Queues entering in hash queue. In case of empty hash_fields only the
2386  *   first queue index will be taken for the indirection table.
2387  * @param queues_n
2388  *   Number of queues.
2389  * @param tunnel
2390  *   Tunnel type.
2391  *
2392  * @return
2393  *   The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
2394  */
2395 uint32_t
2396 mlx5_hrxq_new(struct rte_eth_dev *dev,
2397               const uint8_t *rss_key, uint32_t rss_key_len,
2398               uint64_t hash_fields,
2399               const uint16_t *queues, uint32_t queues_n,
2400               int tunnel __rte_unused)
2401 {
2402         struct mlx5_priv *priv = dev->data->dev_private;
2403         struct mlx5_hrxq *hrxq;
2404         uint32_t hrxq_idx = 0;
2405         struct ibv_qp *qp = NULL;
2406         struct mlx5_ind_table_obj *ind_tbl;
2407         int err;
2408         struct mlx5_devx_obj *tir = NULL;
2409         struct mlx5_rxq_data *rxq_data = (*priv->rxqs)[queues[0]];
2410         struct mlx5_rxq_ctrl *rxq_ctrl =
2411                 container_of(rxq_data, struct mlx5_rxq_ctrl, rxq);
2412
2413         queues_n = hash_fields ? queues_n : 1;
2414         ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2415         if (!ind_tbl) {
2416                 enum mlx5_ind_tbl_type type;
2417
2418                 type = rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV ?
2419                                 MLX5_IND_TBL_TYPE_IBV : MLX5_IND_TBL_TYPE_DEVX;
2420                 ind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n, type);
2421         }
2422         if (!ind_tbl) {
2423                 rte_errno = ENOMEM;
2424                 return 0;
2425         }
2426         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2427 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2428                 struct mlx5dv_qp_init_attr qp_init_attr;
2429
2430                 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
2431                 if (tunnel) {
2432                         qp_init_attr.comp_mask =
2433                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2434                         qp_init_attr.create_flags =
2435                                 MLX5DV_QP_CREATE_TUNNEL_OFFLOADS;
2436                 }
2437 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2438                 if (dev->data->dev_conf.lpbk_mode) {
2439                         /*
2440                          * Allow packet sent from NIC loop back
2441                          * w/o source MAC check.
2442                          */
2443                         qp_init_attr.comp_mask |=
2444                                 MLX5DV_QP_INIT_ATTR_MASK_QP_CREATE_FLAGS;
2445                         qp_init_attr.create_flags |=
2446                                 MLX5DV_QP_CREATE_TIR_ALLOW_SELF_LOOPBACK_UC;
2447                 }
2448 #endif
2449                 qp = mlx5_glue->dv_create_qp
2450                         (priv->sh->ctx,
2451                          &(struct ibv_qp_init_attr_ex){
2452                                 .qp_type = IBV_QPT_RAW_PACKET,
2453                                 .comp_mask =
2454                                         IBV_QP_INIT_ATTR_PD |
2455                                         IBV_QP_INIT_ATTR_IND_TABLE |
2456                                         IBV_QP_INIT_ATTR_RX_HASH,
2457                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2458                                         .rx_hash_function =
2459                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2460                                         .rx_hash_key_len = rss_key_len,
2461                                         .rx_hash_key =
2462                                                 (void *)(uintptr_t)rss_key,
2463                                         .rx_hash_fields_mask = hash_fields,
2464                                 },
2465                                 .rwq_ind_tbl = ind_tbl->ind_table,
2466                                 .pd = priv->sh->pd,
2467                           },
2468                           &qp_init_attr);
2469 #else
2470                 qp = mlx5_glue->create_qp_ex
2471                         (priv->sh->ctx,
2472                          &(struct ibv_qp_init_attr_ex){
2473                                 .qp_type = IBV_QPT_RAW_PACKET,
2474                                 .comp_mask =
2475                                         IBV_QP_INIT_ATTR_PD |
2476                                         IBV_QP_INIT_ATTR_IND_TABLE |
2477                                         IBV_QP_INIT_ATTR_RX_HASH,
2478                                 .rx_hash_conf = (struct ibv_rx_hash_conf){
2479                                         .rx_hash_function =
2480                                                 IBV_RX_HASH_FUNC_TOEPLITZ,
2481                                         .rx_hash_key_len = rss_key_len,
2482                                         .rx_hash_key =
2483                                                 (void *)(uintptr_t)rss_key,
2484                                         .rx_hash_fields_mask = hash_fields,
2485                                 },
2486                                 .rwq_ind_tbl = ind_tbl->ind_table,
2487                                 .pd = priv->sh->pd,
2488                          });
2489 #endif
2490                 if (!qp) {
2491                         rte_errno = errno;
2492                         goto error;
2493                 }
2494         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2495                 struct mlx5_devx_tir_attr tir_attr;
2496                 uint32_t i;
2497                 uint32_t lro = 1;
2498
2499                 /* Enable TIR LRO only if all the queues were configured for. */
2500                 for (i = 0; i < queues_n; ++i) {
2501                         if (!(*priv->rxqs)[queues[i]]->lro) {
2502                                 lro = 0;
2503                                 break;
2504                         }
2505                 }
2506                 memset(&tir_attr, 0, sizeof(tir_attr));
2507                 tir_attr.disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
2508                 tir_attr.rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
2509                 tir_attr.tunneled_offload_en = !!tunnel;
2510                 /* If needed, translate hash_fields bitmap to PRM format. */
2511                 if (hash_fields) {
2512 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2513                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2514                                         hash_fields & IBV_RX_HASH_INNER ?
2515                                         &tir_attr.rx_hash_field_selector_inner :
2516                                         &tir_attr.rx_hash_field_selector_outer;
2517 #else
2518                         struct mlx5_rx_hash_field_select *rx_hash_field_select =
2519                                         &tir_attr.rx_hash_field_selector_outer;
2520 #endif
2521
2522                         /* 1 bit: 0: IPv4, 1: IPv6. */
2523                         rx_hash_field_select->l3_prot_type =
2524                                 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
2525                         /* 1 bit: 0: TCP, 1: UDP. */
2526                         rx_hash_field_select->l4_prot_type =
2527                                 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
2528                         /* Bitmask which sets which fields to use in RX Hash. */
2529                         rx_hash_field_select->selected_fields =
2530                         ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
2531                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
2532                         (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
2533                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
2534                         (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
2535                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
2536                         (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
2537                          MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
2538                 }
2539                 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN)
2540                         tir_attr.transport_domain = priv->sh->td->id;
2541                 else
2542                         tir_attr.transport_domain = priv->sh->tdn;
2543                 memcpy(tir_attr.rx_hash_toeplitz_key, rss_key,
2544                        MLX5_RSS_HASH_KEY_LEN);
2545                 tir_attr.indirect_table = ind_tbl->rqt->id;
2546                 if (dev->data->dev_conf.lpbk_mode)
2547                         tir_attr.self_lb_block =
2548                                         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
2549                 if (lro) {
2550                         tir_attr.lro_timeout_period_usecs =
2551                                         priv->config.lro.timeout;
2552                         tir_attr.lro_max_msg_sz = priv->max_lro_msg_size;
2553                         tir_attr.lro_enable_mask =
2554                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2555                                         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
2556                 }
2557                 tir = mlx5_devx_cmd_create_tir(priv->sh->ctx, &tir_attr);
2558                 if (!tir) {
2559                         DRV_LOG(ERR, "port %u cannot create DevX TIR",
2560                                 dev->data->port_id);
2561                         rte_errno = errno;
2562                         goto error;
2563                 }
2564         }
2565         hrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);
2566         if (!hrxq)
2567                 goto error;
2568         hrxq->ind_table = ind_tbl;
2569         if (ind_tbl->type == MLX5_IND_TBL_TYPE_IBV) {
2570                 hrxq->qp = qp;
2571 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2572                 hrxq->action =
2573                         mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2574                 if (!hrxq->action) {
2575                         rte_errno = errno;
2576                         goto error;
2577                 }
2578 #endif
2579         } else { /* ind_tbl->type == MLX5_IND_TBL_TYPE_DEVX */
2580                 hrxq->tir = tir;
2581 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2582                 hrxq->action = mlx5_glue->dv_create_flow_action_dest_devx_tir
2583                                                         (hrxq->tir->obj);
2584                 if (!hrxq->action) {
2585                         rte_errno = errno;
2586                         goto error;
2587                 }
2588 #endif
2589         }
2590         hrxq->rss_key_len = rss_key_len;
2591         hrxq->hash_fields = hash_fields;
2592         memcpy(hrxq->rss_key, rss_key, rss_key_len);
2593         rte_atomic32_inc(&hrxq->refcnt);
2594         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs, hrxq_idx,
2595                      hrxq, next);
2596         return hrxq_idx;
2597 error:
2598         err = rte_errno; /* Save rte_errno before cleanup. */
2599         mlx5_ind_table_obj_release(dev, ind_tbl);
2600         if (qp)
2601                 claim_zero(mlx5_glue->destroy_qp(qp));
2602         else if (tir)
2603                 claim_zero(mlx5_devx_cmd_destroy(tir));
2604         rte_errno = err; /* Restore rte_errno. */
2605         return 0;
2606 }
2607
2608 /**
2609  * Get an Rx Hash queue.
2610  *
2611  * @param dev
2612  *   Pointer to Ethernet device.
2613  * @param rss_conf
2614  *   RSS configuration for the Rx hash queue.
2615  * @param queues
2616  *   Queues entering in hash queue. In case of empty hash_fields only the
2617  *   first queue index will be taken for the indirection table.
2618  * @param queues_n
2619  *   Number of queues.
2620  *
2621  * @return
2622  *   An hash Rx queue index on success.
2623  */
2624 uint32_t
2625 mlx5_hrxq_get(struct rte_eth_dev *dev,
2626               const uint8_t *rss_key, uint32_t rss_key_len,
2627               uint64_t hash_fields,
2628               const uint16_t *queues, uint32_t queues_n)
2629 {
2630         struct mlx5_priv *priv = dev->data->dev_private;
2631         struct mlx5_hrxq *hrxq;
2632         uint32_t idx;
2633
2634         queues_n = hash_fields ? queues_n : 1;
2635         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2636                       hrxq, next) {
2637                 struct mlx5_ind_table_obj *ind_tbl;
2638
2639                 if (hrxq->rss_key_len != rss_key_len)
2640                         continue;
2641                 if (memcmp(hrxq->rss_key, rss_key, rss_key_len))
2642                         continue;
2643                 if (hrxq->hash_fields != hash_fields)
2644                         continue;
2645                 ind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);
2646                 if (!ind_tbl)
2647                         continue;
2648                 if (ind_tbl != hrxq->ind_table) {
2649                         mlx5_ind_table_obj_release(dev, ind_tbl);
2650                         continue;
2651                 }
2652                 rte_atomic32_inc(&hrxq->refcnt);
2653                 return idx;
2654         }
2655         return 0;
2656 }
2657
2658 /**
2659  * Release the hash Rx queue.
2660  *
2661  * @param dev
2662  *   Pointer to Ethernet device.
2663  * @param hrxq
2664  *   Index to Hash Rx queue to release.
2665  *
2666  * @return
2667  *   1 while a reference on it exists, 0 when freed.
2668  */
2669 int
2670 mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hrxq_idx)
2671 {
2672         struct mlx5_priv *priv = dev->data->dev_private;
2673         struct mlx5_hrxq *hrxq;
2674
2675         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2676         if (!hrxq)
2677                 return 0;
2678         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2679 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2680                 mlx5_glue->destroy_flow_action(hrxq->action);
2681 #endif
2682                 if (hrxq->ind_table->type == MLX5_IND_TBL_TYPE_IBV)
2683                         claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2684                 else /* hrxq->ind_table->type == MLX5_IND_TBL_TYPE_DEVX */
2685                         claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
2686                 mlx5_ind_table_obj_release(dev, hrxq->ind_table);
2687                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_HRXQ], &priv->hrxqs,
2688                              hrxq_idx, hrxq, next);
2689                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);
2690                 return 0;
2691         }
2692         claim_nonzero(mlx5_ind_table_obj_release(dev, hrxq->ind_table));
2693         return 1;
2694 }
2695
2696 /**
2697  * Verify the Rx Queue list is empty
2698  *
2699  * @param dev
2700  *   Pointer to Ethernet device.
2701  *
2702  * @return
2703  *   The number of object not released.
2704  */
2705 int
2706 mlx5_hrxq_verify(struct rte_eth_dev *dev)
2707 {
2708         struct mlx5_priv *priv = dev->data->dev_private;
2709         struct mlx5_hrxq *hrxq;
2710         uint32_t idx;
2711         int ret = 0;
2712
2713         ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_HRXQ], priv->hrxqs, idx,
2714                       hrxq, next) {
2715                 DRV_LOG(DEBUG,
2716                         "port %u hash Rx queue %p still referenced",
2717                         dev->data->port_id, (void *)hrxq);
2718                 ++ret;
2719         }
2720         return ret;
2721 }
2722
2723 /**
2724  * Create a drop Rx queue Verbs/DevX object.
2725  *
2726  * @param dev
2727  *   Pointer to Ethernet device.
2728  *
2729  * @return
2730  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2731  */
2732 static struct mlx5_rxq_obj *
2733 mlx5_rxq_obj_drop_new(struct rte_eth_dev *dev)
2734 {
2735         struct mlx5_priv *priv = dev->data->dev_private;
2736         struct ibv_context *ctx = priv->sh->ctx;
2737         struct ibv_cq *cq;
2738         struct ibv_wq *wq = NULL;
2739         struct mlx5_rxq_obj *rxq;
2740
2741         if (priv->drop_queue.rxq)
2742                 return priv->drop_queue.rxq;
2743         cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
2744         if (!cq) {
2745                 DEBUG("port %u cannot allocate CQ for drop queue",
2746                       dev->data->port_id);
2747                 rte_errno = errno;
2748                 goto error;
2749         }
2750         wq = mlx5_glue->create_wq(ctx,
2751                  &(struct ibv_wq_init_attr){
2752                         .wq_type = IBV_WQT_RQ,
2753                         .max_wr = 1,
2754                         .max_sge = 1,
2755                         .pd = priv->sh->pd,
2756                         .cq = cq,
2757                  });
2758         if (!wq) {
2759                 DEBUG("port %u cannot allocate WQ for drop queue",
2760                       dev->data->port_id);
2761                 rte_errno = errno;
2762                 goto error;
2763         }
2764         rxq = rte_calloc(__func__, 1, sizeof(*rxq), 0);
2765         if (!rxq) {
2766                 DEBUG("port %u cannot allocate drop Rx queue memory",
2767                       dev->data->port_id);
2768                 rte_errno = ENOMEM;
2769                 goto error;
2770         }
2771         rxq->cq = cq;
2772         rxq->wq = wq;
2773         priv->drop_queue.rxq = rxq;
2774         return rxq;
2775 error:
2776         if (wq)
2777                 claim_zero(mlx5_glue->destroy_wq(wq));
2778         if (cq)
2779                 claim_zero(mlx5_glue->destroy_cq(cq));
2780         return NULL;
2781 }
2782
2783 /**
2784  * Release a drop Rx queue Verbs/DevX object.
2785  *
2786  * @param dev
2787  *   Pointer to Ethernet device.
2788  *
2789  * @return
2790  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2791  */
2792 static void
2793 mlx5_rxq_obj_drop_release(struct rte_eth_dev *dev)
2794 {
2795         struct mlx5_priv *priv = dev->data->dev_private;
2796         struct mlx5_rxq_obj *rxq = priv->drop_queue.rxq;
2797
2798         if (rxq->wq)
2799                 claim_zero(mlx5_glue->destroy_wq(rxq->wq));
2800         if (rxq->cq)
2801                 claim_zero(mlx5_glue->destroy_cq(rxq->cq));
2802         rte_free(rxq);
2803         priv->drop_queue.rxq = NULL;
2804 }
2805
2806 /**
2807  * Create a drop indirection table.
2808  *
2809  * @param dev
2810  *   Pointer to Ethernet device.
2811  *
2812  * @return
2813  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2814  */
2815 static struct mlx5_ind_table_obj *
2816 mlx5_ind_table_obj_drop_new(struct rte_eth_dev *dev)
2817 {
2818         struct mlx5_priv *priv = dev->data->dev_private;
2819         struct mlx5_ind_table_obj *ind_tbl;
2820         struct mlx5_rxq_obj *rxq;
2821         struct mlx5_ind_table_obj tmpl;
2822
2823         rxq = mlx5_rxq_obj_drop_new(dev);
2824         if (!rxq)
2825                 return NULL;
2826         tmpl.ind_table = mlx5_glue->create_rwq_ind_table
2827                 (priv->sh->ctx,
2828                  &(struct ibv_rwq_ind_table_init_attr){
2829                         .log_ind_tbl_size = 0,
2830                         .ind_tbl = &rxq->wq,
2831                         .comp_mask = 0,
2832                  });
2833         if (!tmpl.ind_table) {
2834                 DEBUG("port %u cannot allocate indirection table for drop"
2835                       " queue",
2836                       dev->data->port_id);
2837                 rte_errno = errno;
2838                 goto error;
2839         }
2840         ind_tbl = rte_calloc(__func__, 1, sizeof(*ind_tbl), 0);
2841         if (!ind_tbl) {
2842                 rte_errno = ENOMEM;
2843                 goto error;
2844         }
2845         ind_tbl->ind_table = tmpl.ind_table;
2846         return ind_tbl;
2847 error:
2848         mlx5_rxq_obj_drop_release(dev);
2849         return NULL;
2850 }
2851
2852 /**
2853  * Release a drop indirection table.
2854  *
2855  * @param dev
2856  *   Pointer to Ethernet device.
2857  */
2858 static void
2859 mlx5_ind_table_obj_drop_release(struct rte_eth_dev *dev)
2860 {
2861         struct mlx5_priv *priv = dev->data->dev_private;
2862         struct mlx5_ind_table_obj *ind_tbl = priv->drop_queue.hrxq->ind_table;
2863
2864         claim_zero(mlx5_glue->destroy_rwq_ind_table(ind_tbl->ind_table));
2865         mlx5_rxq_obj_drop_release(dev);
2866         rte_free(ind_tbl);
2867         priv->drop_queue.hrxq->ind_table = NULL;
2868 }
2869
2870 /**
2871  * Create a drop Rx Hash queue.
2872  *
2873  * @param dev
2874  *   Pointer to Ethernet device.
2875  *
2876  * @return
2877  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
2878  */
2879 struct mlx5_hrxq *
2880 mlx5_hrxq_drop_new(struct rte_eth_dev *dev)
2881 {
2882         struct mlx5_priv *priv = dev->data->dev_private;
2883         struct mlx5_ind_table_obj *ind_tbl = NULL;
2884         struct ibv_qp *qp = NULL;
2885         struct mlx5_hrxq *hrxq = NULL;
2886
2887         if (priv->drop_queue.hrxq) {
2888                 rte_atomic32_inc(&priv->drop_queue.hrxq->refcnt);
2889                 return priv->drop_queue.hrxq;
2890         }
2891         hrxq = rte_calloc(__func__, 1, sizeof(*hrxq), 0);
2892         if (!hrxq) {
2893                 DRV_LOG(WARNING,
2894                         "port %u cannot allocate memory for drop queue",
2895                         dev->data->port_id);
2896                 rte_errno = ENOMEM;
2897                 goto error;
2898         }
2899         priv->drop_queue.hrxq = hrxq;
2900         ind_tbl = mlx5_ind_table_obj_drop_new(dev);
2901         if (!ind_tbl)
2902                 goto error;
2903         hrxq->ind_table = ind_tbl;
2904         qp = mlx5_glue->create_qp_ex(priv->sh->ctx,
2905                  &(struct ibv_qp_init_attr_ex){
2906                         .qp_type = IBV_QPT_RAW_PACKET,
2907                         .comp_mask =
2908                                 IBV_QP_INIT_ATTR_PD |
2909                                 IBV_QP_INIT_ATTR_IND_TABLE |
2910                                 IBV_QP_INIT_ATTR_RX_HASH,
2911                         .rx_hash_conf = (struct ibv_rx_hash_conf){
2912                                 .rx_hash_function =
2913                                         IBV_RX_HASH_FUNC_TOEPLITZ,
2914                                 .rx_hash_key_len = MLX5_RSS_HASH_KEY_LEN,
2915                                 .rx_hash_key = rss_hash_default_key,
2916                                 .rx_hash_fields_mask = 0,
2917                                 },
2918                         .rwq_ind_tbl = ind_tbl->ind_table,
2919                         .pd = priv->sh->pd
2920                  });
2921         if (!qp) {
2922                 DEBUG("port %u cannot allocate QP for drop queue",
2923                       dev->data->port_id);
2924                 rte_errno = errno;
2925                 goto error;
2926         }
2927         hrxq->qp = qp;
2928 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2929         hrxq->action = mlx5_glue->dv_create_flow_action_dest_ibv_qp(hrxq->qp);
2930         if (!hrxq->action) {
2931                 rte_errno = errno;
2932                 goto error;
2933         }
2934 #endif
2935         rte_atomic32_set(&hrxq->refcnt, 1);
2936         return hrxq;
2937 error:
2938 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2939         if (hrxq && hrxq->action)
2940                 mlx5_glue->destroy_flow_action(hrxq->action);
2941 #endif
2942         if (qp)
2943                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2944         if (ind_tbl)
2945                 mlx5_ind_table_obj_drop_release(dev);
2946         if (hrxq) {
2947                 priv->drop_queue.hrxq = NULL;
2948                 rte_free(hrxq);
2949         }
2950         return NULL;
2951 }
2952
2953 /**
2954  * Release a drop hash Rx queue.
2955  *
2956  * @param dev
2957  *   Pointer to Ethernet device.
2958  */
2959 void
2960 mlx5_hrxq_drop_release(struct rte_eth_dev *dev)
2961 {
2962         struct mlx5_priv *priv = dev->data->dev_private;
2963         struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
2964
2965         if (rte_atomic32_dec_and_test(&hrxq->refcnt)) {
2966 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2967                 mlx5_glue->destroy_flow_action(hrxq->action);
2968 #endif
2969                 claim_zero(mlx5_glue->destroy_qp(hrxq->qp));
2970                 mlx5_ind_table_obj_drop_release(dev);
2971                 rte_free(hrxq);
2972                 priv->drop_queue.hrxq = NULL;
2973         }
2974 }
2975
2976
2977 /**
2978  * Set the Rx queue timestamp conversion parameters
2979  *
2980  * @param[in] dev
2981  *   Pointer to the Ethernet device structure.
2982  */
2983 void
2984 mlx5_rxq_timestamp_set(struct rte_eth_dev *dev)
2985 {
2986         struct mlx5_priv *priv = dev->data->dev_private;
2987         struct mlx5_dev_ctx_shared *sh = priv->sh;
2988         struct mlx5_rxq_data *data;
2989         unsigned int i;
2990
2991         for (i = 0; i != priv->rxqs_n; ++i) {
2992                 if (!(*priv->rxqs)[i])
2993                         continue;
2994                 data = (*priv->rxqs)[i];
2995                 data->sh = sh;
2996                 data->rt_timestamp = priv->config.rt_timestamp;
2997         }
2998 }