1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
82 static __rte_always_inline uint32_t
83 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
84 volatile struct mlx5_mini_cqe8 *mcqe);
86 static __rte_always_inline int
87 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
88 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
90 static __rte_always_inline uint32_t
91 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
93 static __rte_always_inline void
94 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
95 volatile struct mlx5_cqe *cqe,
96 volatile struct mlx5_mini_cqe8 *mcqe);
99 mlx5_queue_state_modify(struct rte_eth_dev *dev,
100 struct mlx5_mp_arg_queue_state_modify *sm);
103 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
104 volatile struct mlx5_cqe *__rte_restrict cqe,
105 uint32_t phcsum, uint8_t l4_type);
108 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
109 volatile struct mlx5_cqe *__rte_restrict cqe,
110 volatile struct mlx5_mini_cqe8 *mcqe,
111 struct mlx5_rxq_data *rxq, uint32_t len);
113 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
114 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
117 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
118 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
120 uint64_t rte_net_mlx5_dynf_inline_mask;
121 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
124 * Build a table to translate Rx completion flags to packet type.
126 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
129 mlx5_set_ptype_table(void)
132 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
134 /* Last entry must not be overwritten, reserved for errored packet. */
135 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
136 (*p)[i] = RTE_PTYPE_UNKNOWN;
138 * The index to the array should have:
139 * bit[1:0] = l3_hdr_type
140 * bit[4:2] = l4_hdr_type
143 * bit[7] = outer_l3_type
146 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
148 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_L4_NONFRAG;
150 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_L4_NONFRAG;
153 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 /* Repeat with outer_l3_type being set. Just in case. */
176 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_L4_NONFRAG;
178 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_L4_NONFRAG;
180 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
202 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L4_NONFRAG;
205 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
206 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L4_NONFRAG;
208 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
209 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_NONFRAG;
215 /* Tunneled - Fragmented */
216 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
222 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_FRAG;
225 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
272 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_UDP;
275 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_UDP;
281 * Build a table to translate packet to checksum type of Verbs.
284 mlx5_set_cksum_table(void)
290 * The index should have:
291 * bit[0] = PKT_TX_TCP_SEG
292 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
293 * bit[4] = PKT_TX_IP_CKSUM
294 * bit[8] = PKT_TX_OUTER_IP_CKSUM
297 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
300 /* Tunneled packet. */
301 if (i & (1 << 8)) /* Outer IP. */
302 v |= MLX5_ETH_WQE_L3_CSUM;
303 if (i & (1 << 4)) /* Inner IP. */
304 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
309 if (i & (1 << 4)) /* IP. */
310 v |= MLX5_ETH_WQE_L3_CSUM;
311 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
312 v |= MLX5_ETH_WQE_L4_CSUM;
314 mlx5_cksum_table[i] = v;
319 * Build a table to translate packet type of mbuf to SWP type of Verbs.
322 mlx5_set_swp_types_table(void)
328 * The index should have:
329 * bit[0:1] = PKT_TX_L4_MASK
330 * bit[4] = PKT_TX_IPV6
331 * bit[8] = PKT_TX_OUTER_IPV6
332 * bit[9] = PKT_TX_OUTER_UDP
334 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
337 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
339 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
341 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
342 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
343 v |= MLX5_ETH_WQE_L4_INNER_UDP;
344 mlx5_swp_types_table[i] = v;
349 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
350 * Flags must be preliminary initialized to zero.
353 * Pointer to burst routine local context.
355 * Pointer to store Software Parser flags
357 * Configured Tx offloads mask. It is fully defined at
358 * compile time and may be used for optimization.
361 * Software Parser offsets packed in dword.
362 * Software Parser flags are set by pointer.
364 static __rte_always_inline uint32_t
365 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
370 unsigned int idx, off;
373 if (!MLX5_TXOFF_CONFIG(SWP))
375 ol = loc->mbuf->ol_flags;
376 tunnel = ol & PKT_TX_TUNNEL_MASK;
378 * Check whether Software Parser is required.
379 * Only customized tunnels may ask for.
381 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
384 * The index should have:
385 * bit[0:1] = PKT_TX_L4_MASK
386 * bit[4] = PKT_TX_IPV6
387 * bit[8] = PKT_TX_OUTER_IPV6
388 * bit[9] = PKT_TX_OUTER_UDP
390 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
391 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
392 *swp_flags = mlx5_swp_types_table[idx];
394 * Set offsets for SW parser. Since ConnectX-5, SW parser just
395 * complements HW parser. SW parser starts to engage only if HW parser
396 * can't reach a header. For the older devices, HW parser will not kick
397 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
398 * should be set regardless of HW offload.
400 off = loc->mbuf->outer_l2_len;
401 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
402 off += sizeof(struct rte_vlan_hdr);
403 set = (off >> 1) << 8; /* Outer L3 offset. */
404 off += loc->mbuf->outer_l3_len;
405 if (tunnel == PKT_TX_TUNNEL_UDP)
406 set |= off >> 1; /* Outer L4 offset. */
407 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
408 const uint64_t csum = ol & PKT_TX_L4_MASK;
409 off += loc->mbuf->l2_len;
410 set |= (off >> 1) << 24; /* Inner L3 offset. */
411 if (csum == PKT_TX_TCP_CKSUM ||
412 csum == PKT_TX_UDP_CKSUM ||
413 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
414 off += loc->mbuf->l3_len;
415 set |= (off >> 1) << 16; /* Inner L4 offset. */
418 set = rte_cpu_to_le_32(set);
423 * Convert the Checksum offloads to Verbs.
426 * Pointer to the mbuf.
429 * Converted checksum flags.
431 static __rte_always_inline uint8_t
432 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
435 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
436 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
437 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
440 * The index should have:
441 * bit[0] = PKT_TX_TCP_SEG
442 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
443 * bit[4] = PKT_TX_IP_CKSUM
444 * bit[8] = PKT_TX_OUTER_IP_CKSUM
447 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
448 return mlx5_cksum_table[idx];
452 * Internal function to compute the number of used descriptors in an RX queue
458 * The number of used rx descriptor.
461 rx_queue_count(struct mlx5_rxq_data *rxq)
463 struct rxq_zip *zip = &rxq->zip;
464 volatile struct mlx5_cqe *cqe;
465 const unsigned int cqe_n = (1 << rxq->cqe_n);
466 const unsigned int cqe_cnt = cqe_n - 1;
467 unsigned int cq_ci, used;
469 /* if we are processing a compressed cqe */
471 used = zip->cqe_cnt - zip->ai;
477 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
478 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
482 op_own = cqe->op_own;
483 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
484 n = rte_be_to_cpu_32(cqe->byte_cnt);
489 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
491 used = RTE_MIN(used, cqe_n);
496 * DPDK callback to check the status of a rx descriptor.
501 * The index of the descriptor in the ring.
504 * The status of the tx descriptor.
507 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
509 struct mlx5_rxq_data *rxq = rx_queue;
510 struct mlx5_rxq_ctrl *rxq_ctrl =
511 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
512 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
514 if (dev->rx_pkt_burst == NULL ||
515 dev->rx_pkt_burst == removed_rx_burst) {
519 if (offset >= (1 << rxq->cqe_n)) {
523 if (offset < rx_queue_count(rxq))
524 return RTE_ETH_RX_DESC_DONE;
525 return RTE_ETH_RX_DESC_AVAIL;
529 * DPDK callback to get the RX queue information
532 * Pointer to the device structure.
535 * Rx queue identificator.
538 * Pointer to the RX queue information structure.
545 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
546 struct rte_eth_rxq_info *qinfo)
548 struct mlx5_priv *priv = dev->data->dev_private;
549 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
550 struct mlx5_rxq_ctrl *rxq_ctrl =
551 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
555 qinfo->mp = mlx5_rxq_mprq_enabled(rxq) ?
556 rxq->mprq_mp : rxq->mp;
557 qinfo->conf.rx_thresh.pthresh = 0;
558 qinfo->conf.rx_thresh.hthresh = 0;
559 qinfo->conf.rx_thresh.wthresh = 0;
560 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
561 qinfo->conf.rx_drop_en = 1;
562 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
563 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
564 qinfo->scattered_rx = dev->data->scattered_rx;
565 qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?
566 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
571 * DPDK callback to get the RX packet burst mode information
574 * Pointer to the device structure.
577 * Rx queue identificatior.
580 * Pointer to the burts mode information.
583 * 0 as success, -EINVAL as failure.
587 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
588 uint16_t rx_queue_id __rte_unused,
589 struct rte_eth_burst_mode *mode)
591 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
592 struct mlx5_priv *priv = dev->data->dev_private;
593 struct mlx5_rxq_data *rxq;
595 rxq = (*priv->rxqs)[rx_queue_id];
600 if (pkt_burst == mlx5_rx_burst) {
601 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
602 } else if (pkt_burst == mlx5_rx_burst_mprq) {
603 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
604 } else if (pkt_burst == mlx5_rx_burst_vec) {
605 #if defined RTE_ARCH_X86_64
606 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
607 #elif defined RTE_ARCH_ARM64
608 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
609 #elif defined RTE_ARCH_PPC_64
610 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
614 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
615 #if defined RTE_ARCH_X86_64
616 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
617 #elif defined RTE_ARCH_ARM64
618 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
619 #elif defined RTE_ARCH_PPC_64
620 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
631 * DPDK callback to get the number of used descriptors in a RX queue
634 * Pointer to the device structure.
640 * The number of used rx descriptor.
641 * -EINVAL if the queue is invalid
644 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
646 struct mlx5_priv *priv = dev->data->dev_private;
647 struct mlx5_rxq_data *rxq;
649 if (dev->rx_pkt_burst == NULL ||
650 dev->rx_pkt_burst == removed_rx_burst) {
654 rxq = (*priv->rxqs)[rx_queue_id];
659 return rx_queue_count(rxq);
662 #define MLX5_SYSTEM_LOG_DIR "/var/log"
664 * Dump debug information to log file.
669 * If not NULL this string is printed as a header to the output
670 * and the output will be in hexadecimal view.
672 * This is the buffer address to print out.
674 * The number of bytes to dump out.
677 mlx5_dump_debug_information(const char *fname, const char *hex_title,
678 const void *buf, unsigned int hex_len)
682 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
683 fd = fopen(path, "a+");
685 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
686 MKSTR(path2, "./%s", fname);
687 fd = fopen(path2, "a+");
689 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
692 DRV_LOG(INFO, "New debug dump in file %s", path2);
694 DRV_LOG(INFO, "New debug dump in file %s", path);
697 rte_hexdump(fd, hex_title, buf, hex_len);
699 fprintf(fd, "%s", (const char *)buf);
700 fprintf(fd, "\n\n\n");
705 * Move QP from error state to running state and initialize indexes.
708 * Pointer to TX queue control structure.
711 * 0 on success, else -1.
714 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
716 struct mlx5_mp_arg_queue_state_modify sm = {
718 .queue_id = txq_ctrl->txq.idx,
721 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
723 txq_ctrl->txq.wqe_ci = 0;
724 txq_ctrl->txq.wqe_pi = 0;
725 txq_ctrl->txq.elts_comp = 0;
729 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
731 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
733 static const uint8_t magic[] = "seen";
737 for (i = 0; i < sizeof(magic); ++i)
738 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
740 err_cqe->rsvd1[i] = magic[i];
749 * Pointer to TX queue structure.
751 * Pointer to the error CQE.
754 * Negative value if queue recovery failed, otherwise
755 * the error completion entry is handled successfully.
758 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
759 volatile struct mlx5_err_cqe *err_cqe)
761 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
762 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
763 struct mlx5_txq_ctrl *txq_ctrl =
764 container_of(txq, struct mlx5_txq_ctrl, txq);
765 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
766 int seen = check_err_cqe_seen(err_cqe);
768 if (!seen && txq_ctrl->dump_file_n <
769 txq_ctrl->priv->config.max_dump_files_num) {
770 MKSTR(err_str, "Unexpected CQE error syndrome "
771 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
772 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
773 txq->cqe_s, txq->qp_num_8s >> 8,
774 rte_be_to_cpu_16(err_cqe->wqe_counter),
775 txq->wqe_ci, txq->cq_ci);
776 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
777 PORT_ID(txq_ctrl->priv), txq->idx,
778 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
779 mlx5_dump_debug_information(name, NULL, err_str, 0);
780 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
781 (const void *)((uintptr_t)
785 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
786 (const void *)((uintptr_t)
790 txq_ctrl->dump_file_n++;
794 * Count errors in WQEs units.
795 * Later it can be improved to count error packets,
796 * for example, by SQ parsing to find how much packets
797 * should be counted for each WQE.
799 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
801 if (tx_recover_qp(txq_ctrl)) {
802 /* Recovering failed - retry later on the same WQE. */
805 /* Release all the remaining buffers. */
806 txq_free_elts(txq_ctrl);
812 * Translate RX completion flags to packet type.
815 * Pointer to RX queue structure.
819 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
822 * Packet type for struct rte_mbuf.
824 static inline uint32_t
825 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
826 volatile struct mlx5_mini_cqe8 *mcqe)
830 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
832 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
834 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
835 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
837 ptype = mcqe->hdr_type >> 2;
839 * The index to the array should have:
840 * bit[1:0] = l3_hdr_type
841 * bit[4:2] = l4_hdr_type
844 * bit[7] = outer_l3_type
847 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
851 * Initialize Rx WQ and indexes.
854 * Pointer to RX queue structure.
857 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
859 const unsigned int wqe_n = 1 << rxq->elts_n;
862 for (i = 0; (i != wqe_n); ++i) {
863 volatile struct mlx5_wqe_data_seg *scat;
867 if (mlx5_rxq_mprq_enabled(rxq)) {
868 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
870 scat = &((volatile struct mlx5_wqe_mprq *)
872 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
873 1 << rxq->strd_num_n);
874 byte_count = (1 << rxq->strd_sz_n) *
875 (1 << rxq->strd_num_n);
877 struct rte_mbuf *buf = (*rxq->elts)[i];
879 scat = &((volatile struct mlx5_wqe_data_seg *)
881 addr = rte_pktmbuf_mtod(buf, uintptr_t);
882 byte_count = DATA_LEN(buf);
884 /* scat->addr must be able to store a pointer. */
885 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
886 *scat = (struct mlx5_wqe_data_seg){
887 .addr = rte_cpu_to_be_64(addr),
888 .byte_count = rte_cpu_to_be_32(byte_count),
889 .lkey = mlx5_rx_addr2mr(rxq, addr),
892 rxq->consumed_strd = 0;
893 rxq->decompressed = 0;
895 rxq->zip = (struct rxq_zip){
898 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
899 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
900 /* Update doorbell counter. */
901 rxq->rq_ci = wqe_n >> rxq->sges_n;
903 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
907 * Modify a Verbs/DevX queue state.
908 * This must be called from the primary process.
911 * Pointer to Ethernet device.
913 * State modify request parameters.
916 * 0 in case of success else non-zero value and rte_errno is set.
919 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
920 const struct mlx5_mp_arg_queue_state_modify *sm)
923 struct mlx5_priv *priv = dev->data->dev_private;
926 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
927 struct mlx5_rxq_ctrl *rxq_ctrl =
928 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
930 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
932 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
933 sm->state, strerror(errno));
938 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
939 struct mlx5_txq_ctrl *txq_ctrl =
940 container_of(txq, struct mlx5_txq_ctrl, txq);
942 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
943 MLX5_TXQ_MOD_ERR2RDY,
944 (uint8_t)priv->dev_port);
952 * Modify a Verbs queue state.
955 * Pointer to Ethernet device.
957 * State modify request parameters.
960 * 0 in case of success else non-zero value.
963 mlx5_queue_state_modify(struct rte_eth_dev *dev,
964 struct mlx5_mp_arg_queue_state_modify *sm)
966 struct mlx5_priv *priv = dev->data->dev_private;
969 switch (rte_eal_process_type()) {
970 case RTE_PROC_PRIMARY:
971 ret = mlx5_queue_state_modify_primary(dev, sm);
973 case RTE_PROC_SECONDARY:
974 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
984 * The function inserts the RQ state to reset when the first error CQE is
985 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
986 * it moves the RQ state to ready and initializes the RQ.
987 * Next CQE identification and error counting are in the caller responsibility.
990 * Pointer to RX queue structure.
992 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
993 * 0 when called from non-vectorized Rx burst.
996 * -1 in case of recovery error, otherwise the CQE status.
999 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1001 const uint16_t cqe_n = 1 << rxq->cqe_n;
1002 const uint16_t cqe_mask = cqe_n - 1;
1003 const uint16_t wqe_n = 1 << rxq->elts_n;
1004 const uint16_t strd_n = 1 << rxq->strd_num_n;
1005 struct mlx5_rxq_ctrl *rxq_ctrl =
1006 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1008 volatile struct mlx5_cqe *cqe;
1009 volatile struct mlx5_err_cqe *err_cqe;
1011 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1013 struct mlx5_mp_arg_queue_state_modify sm;
1016 switch (rxq->err_state) {
1017 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1018 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1020 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1022 sm.queue_id = rxq->idx;
1023 sm.state = IBV_WQS_RESET;
1024 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1026 if (rxq_ctrl->dump_file_n <
1027 rxq_ctrl->priv->config.max_dump_files_num) {
1028 MKSTR(err_str, "Unexpected CQE error syndrome "
1029 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1030 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1031 rxq->cqn, rxq_ctrl->wqn,
1032 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1033 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1034 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1035 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1036 mlx5_dump_debug_information(name, NULL, err_str, 0);
1037 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1038 (const void *)((uintptr_t)
1040 sizeof(*u.cqe) * cqe_n);
1041 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1042 (const void *)((uintptr_t)
1045 rxq_ctrl->dump_file_n++;
1047 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1049 case MLX5_RXQ_ERR_STATE_NEED_READY:
1050 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1051 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1053 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1056 * The RQ consumer index must be zeroed while moving
1057 * from RESET state to RDY state.
1059 *rxq->rq_db = rte_cpu_to_be_32(0);
1062 sm.queue_id = rxq->idx;
1063 sm.state = IBV_WQS_RDY;
1064 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1068 const uint32_t elts_n =
1069 mlx5_rxq_mprq_enabled(rxq) ?
1070 wqe_n * strd_n : wqe_n;
1071 const uint32_t e_mask = elts_n - 1;
1073 mlx5_rxq_mprq_enabled(rxq) ?
1074 rxq->elts_ci : rxq->rq_ci;
1076 struct rte_mbuf **elt;
1078 unsigned int n = elts_n - (elts_ci -
1081 for (i = 0; i < (int)n; ++i) {
1082 elt_idx = (elts_ci + i) & e_mask;
1083 elt = &(*rxq->elts)[elt_idx];
1084 *elt = rte_mbuf_raw_alloc(rxq->mp);
1086 for (i--; i >= 0; --i) {
1087 elt_idx = (elts_ci +
1091 rte_pktmbuf_free_seg
1097 for (i = 0; i < (int)elts_n; ++i) {
1098 elt = &(*rxq->elts)[i];
1100 (uint16_t)((*elt)->buf_len -
1101 rte_pktmbuf_headroom(*elt));
1103 /* Padding with a fake mbuf for vec Rx. */
1104 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1105 (*rxq->elts)[elts_n + i] =
1108 mlx5_rxq_initialize(rxq);
1109 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1118 * Get size of the next packet for a given CQE. For compressed CQEs, the
1119 * consumer index is updated only once all packets of the current one have
1123 * Pointer to RX queue.
1127 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1131 * 0 in case of empty CQE, otherwise the packet size in bytes.
1134 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1135 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1137 struct rxq_zip *zip = &rxq->zip;
1138 uint16_t cqe_n = cqe_cnt + 1;
1144 /* Process compressed data in the CQE and mini arrays. */
1146 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1147 (volatile struct mlx5_mini_cqe8 (*)[8])
1148 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1150 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1152 *mcqe = &(*mc)[zip->ai & 7];
1153 if ((++zip->ai & 7) == 0) {
1154 /* Invalidate consumed CQEs */
1157 while (idx != end) {
1158 (*rxq->cqes)[idx & cqe_cnt].op_own =
1159 MLX5_CQE_INVALIDATE;
1163 * Increment consumer index to skip the number
1164 * of CQEs consumed. Hardware leaves holes in
1165 * the CQ ring for software use.
1170 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1171 /* Invalidate the rest */
1175 while (idx != end) {
1176 (*rxq->cqes)[idx & cqe_cnt].op_own =
1177 MLX5_CQE_INVALIDATE;
1180 rxq->cq_ci = zip->cq_ci;
1184 * No compressed data, get next CQE and verify if it is
1192 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1193 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1194 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1196 ret = mlx5_rx_err_handle(rxq, 0);
1197 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1205 * Introduce the local variable to have queue cq_ci
1206 * index in queue structure always consistent with
1207 * actual CQE boundary (not pointing to the middle
1208 * of compressed CQE session).
1210 cq_ci = rxq->cq_ci + 1;
1211 op_own = cqe->op_own;
1212 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1213 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1214 (volatile struct mlx5_mini_cqe8 (*)[8])
1215 (uintptr_t)(&(*rxq->cqes)
1216 [cq_ci & cqe_cnt].pkt_info);
1218 /* Fix endianness. */
1219 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1221 * Current mini array position is the one
1222 * returned by check_cqe64().
1224 * If completion comprises several mini arrays,
1225 * as a special case the second one is located
1226 * 7 CQEs after the initial CQE instead of 8
1227 * for subsequent ones.
1230 zip->na = zip->ca + 7;
1231 /* Compute the next non compressed CQE. */
1232 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1233 /* Get packet size to return. */
1234 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1238 /* Prefetch all to be invalidated */
1241 while (idx != end) {
1242 rte_prefetch0(&(*rxq->cqes)[(idx) &
1248 len = rte_be_to_cpu_32(cqe->byte_cnt);
1251 if (unlikely(rxq->err_state)) {
1252 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1253 ++rxq->stats.idropped;
1261 * Translate RX completion flags to offload flags.
1267 * Offload flags (ol_flags) for struct rte_mbuf.
1269 static inline uint32_t
1270 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1272 uint32_t ol_flags = 0;
1273 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1277 MLX5_CQE_RX_L3_HDR_VALID,
1278 PKT_RX_IP_CKSUM_GOOD) |
1280 MLX5_CQE_RX_L4_HDR_VALID,
1281 PKT_RX_L4_CKSUM_GOOD);
1286 * Fill in mbuf fields from RX completion flags.
1287 * Note that pkt->ol_flags should be initialized outside of this function.
1290 * Pointer to RX queue.
1295 * @param rss_hash_res
1296 * Packet RSS Hash result.
1299 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1300 volatile struct mlx5_cqe *cqe,
1301 volatile struct mlx5_mini_cqe8 *mcqe)
1303 /* Update packet information. */
1304 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1306 if (rxq->rss_hash) {
1307 uint32_t rss_hash_res = 0;
1309 /* If compressed, take hash result from mini-CQE. */
1311 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1312 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1314 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1316 pkt->hash.rss = rss_hash_res;
1317 pkt->ol_flags |= PKT_RX_RSS_HASH;
1323 /* If compressed, take flow tag from mini-CQE. */
1325 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1326 mark = cqe->sop_drop_qpn;
1328 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1329 (mcqe->flow_tag_high << 16);
1330 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1331 pkt->ol_flags |= PKT_RX_FDIR;
1332 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1333 pkt->ol_flags |= PKT_RX_FDIR_ID;
1334 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1338 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1339 pkt->ol_flags |= rxq->flow_meta_mask;
1340 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1341 cqe->flow_table_metadata;
1344 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1345 if (rxq->vlan_strip) {
1349 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1350 vlan_strip = cqe->hdr_type_etc &
1351 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1353 vlan_strip = mcqe->hdr_type &
1354 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1356 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1357 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1360 if (rxq->hw_timestamp) {
1361 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1363 if (rxq->rt_timestamp)
1364 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1365 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1366 pkt->ol_flags |= rxq->timestamp_rx_flag;
1371 * DPDK callback for RX.
1374 * Generic pointer to RX queue structure.
1376 * Array to store received packets.
1378 * Maximum number of packets in array.
1381 * Number of packets successfully received (<= pkts_n).
1384 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1386 struct mlx5_rxq_data *rxq = dpdk_rxq;
1387 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1388 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1389 const unsigned int sges_n = rxq->sges_n;
1390 struct rte_mbuf *pkt = NULL;
1391 struct rte_mbuf *seg = NULL;
1392 volatile struct mlx5_cqe *cqe =
1393 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1395 unsigned int rq_ci = rxq->rq_ci << sges_n;
1396 int len = 0; /* keep its value across iterations. */
1399 unsigned int idx = rq_ci & wqe_cnt;
1400 volatile struct mlx5_wqe_data_seg *wqe =
1401 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1402 struct rte_mbuf *rep = (*rxq->elts)[idx];
1403 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1411 /* Allocate the buf from the same pool. */
1412 rep = rte_mbuf_raw_alloc(seg->pool);
1413 if (unlikely(rep == NULL)) {
1414 ++rxq->stats.rx_nombuf;
1417 * no buffers before we even started,
1418 * bail out silently.
1422 while (pkt != seg) {
1423 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1427 rte_mbuf_raw_free(pkt);
1433 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1434 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1436 rte_mbuf_raw_free(rep);
1440 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1441 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1442 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1443 if (rxq->crc_present)
1444 len -= RTE_ETHER_CRC_LEN;
1446 if (cqe->lro_num_seg > 1) {
1448 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1450 pkt->ol_flags |= PKT_RX_LRO;
1451 pkt->tso_segsz = len / cqe->lro_num_seg;
1454 DATA_LEN(rep) = DATA_LEN(seg);
1455 PKT_LEN(rep) = PKT_LEN(seg);
1456 SET_DATA_OFF(rep, DATA_OFF(seg));
1457 PORT(rep) = PORT(seg);
1458 (*rxq->elts)[idx] = rep;
1460 * Fill NIC descriptor with the new buffer. The lkey and size
1461 * of the buffers are already known, only the buffer address
1464 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1465 /* If there's only one MR, no need to replace LKey in WQE. */
1466 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1467 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1468 if (len > DATA_LEN(seg)) {
1469 len -= DATA_LEN(seg);
1474 DATA_LEN(seg) = len;
1475 #ifdef MLX5_PMD_SOFT_COUNTERS
1476 /* Increment bytes counter. */
1477 rxq->stats.ibytes += PKT_LEN(pkt);
1479 /* Return packet. */
1484 /* Align consumer index to the next stride. */
1489 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1491 /* Update the consumer index. */
1492 rxq->rq_ci = rq_ci >> sges_n;
1494 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1496 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1497 #ifdef MLX5_PMD_SOFT_COUNTERS
1498 /* Increment packets counter. */
1499 rxq->stats.ipackets += i;
1505 * Update LRO packet TCP header.
1506 * The HW LRO feature doesn't update the TCP header after coalescing the
1507 * TCP segments but supplies information in CQE to fill it by SW.
1510 * Pointer to the TCP header.
1512 * Pointer to the completion entry..
1514 * The L3 pseudo-header checksum.
1517 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1518 volatile struct mlx5_cqe *__rte_restrict cqe,
1519 uint32_t phcsum, uint8_t l4_type)
1522 * The HW calculates only the TCP payload checksum, need to complete
1523 * the TCP header checksum and the L3 pseudo-header checksum.
1525 uint32_t csum = phcsum + cqe->csum;
1527 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1528 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1529 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1530 tcp->recv_ack = cqe->lro_ack_seq_num;
1531 tcp->rx_win = cqe->lro_tcp_win;
1533 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1534 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1536 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1537 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1538 csum = (~csum) & 0xffff;
1545 * Update LRO packet headers.
1546 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1547 * TCP segments but supply information in CQE to fill it by SW.
1550 * The packet address.
1552 * Pointer to the completion entry..
1554 * The packet length.
1557 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1558 volatile struct mlx5_cqe *__rte_restrict cqe,
1559 volatile struct mlx5_mini_cqe8 *mcqe,
1560 struct mlx5_rxq_data *rxq, uint32_t len)
1563 struct rte_ether_hdr *eth;
1564 struct rte_vlan_hdr *vlan;
1565 struct rte_ipv4_hdr *ipv4;
1566 struct rte_ipv6_hdr *ipv6;
1567 struct rte_tcp_hdr *tcp;
1572 uint16_t proto = h.eth->ether_type;
1577 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1578 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1579 proto = h.vlan->eth_proto;
1582 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1583 h.ipv4->time_to_live = cqe->lro_min_ttl;
1584 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1585 h.ipv4->hdr_checksum = 0;
1586 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1587 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1590 h.ipv6->hop_limits = cqe->lro_min_ttl;
1591 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1593 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1597 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1598 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1599 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1601 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1602 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1603 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1607 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1609 struct mlx5_mprq_buf *buf = opaque;
1611 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1612 rte_mempool_put(buf->mp, buf);
1613 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1614 __ATOMIC_RELAXED) == 0)) {
1615 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1616 rte_mempool_put(buf->mp, buf);
1621 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1623 mlx5_mprq_buf_free_cb(NULL, buf);
1627 * DPDK callback for RX with Multi-Packet RQ support.
1630 * Generic pointer to RX queue structure.
1632 * Array to store received packets.
1634 * Maximum number of packets in array.
1637 * Number of packets successfully received (<= pkts_n).
1640 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1642 struct mlx5_rxq_data *rxq = dpdk_rxq;
1643 const uint32_t strd_n = 1 << rxq->strd_num_n;
1644 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1645 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1646 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1647 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1649 uint32_t rq_ci = rxq->rq_ci;
1650 uint16_t consumed_strd = rxq->consumed_strd;
1651 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1653 while (i < pkts_n) {
1654 struct rte_mbuf *pkt;
1660 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1661 enum mlx5_rqx_code rxq_code;
1663 if (consumed_strd == strd_n) {
1664 /* Replace WQE if the buffer is still in use. */
1665 mprq_buf_replace(rxq, rq_ci & wq_mask);
1666 /* Advance to the next WQE. */
1669 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1671 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1672 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1676 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1677 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1678 if (rxq->crc_present)
1679 len -= RTE_ETHER_CRC_LEN;
1681 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1682 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1684 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1685 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1686 MLX5_ASSERT(strd_cnt);
1687 consumed_strd += strd_cnt;
1688 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1690 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1693 MLX5_ASSERT(strd_idx < strd_n);
1694 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1696 pkt = rte_pktmbuf_alloc(rxq->mp);
1697 if (unlikely(pkt == NULL)) {
1698 ++rxq->stats.rx_nombuf;
1701 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1702 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1703 if (rxq->crc_present)
1704 len -= RTE_ETHER_CRC_LEN;
1705 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1706 strd_idx, strd_cnt);
1707 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1708 rte_pktmbuf_free_seg(pkt);
1709 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1710 ++rxq->stats.idropped;
1713 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1714 ++rxq->stats.rx_nombuf;
1718 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1719 if (cqe->lro_num_seg > 1) {
1720 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1721 cqe, mcqe, rxq, len);
1722 pkt->ol_flags |= PKT_RX_LRO;
1723 pkt->tso_segsz = len / cqe->lro_num_seg;
1726 PORT(pkt) = rxq->port_id;
1727 #ifdef MLX5_PMD_SOFT_COUNTERS
1728 /* Increment bytes counter. */
1729 rxq->stats.ibytes += PKT_LEN(pkt);
1731 /* Return packet. */
1735 /* Update the consumer indexes. */
1736 rxq->consumed_strd = consumed_strd;
1738 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1739 if (rq_ci != rxq->rq_ci) {
1742 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1744 #ifdef MLX5_PMD_SOFT_COUNTERS
1745 /* Increment packets counter. */
1746 rxq->stats.ipackets += i;
1752 * Dummy DPDK callback for TX.
1754 * This function is used to temporarily replace the real callback during
1755 * unsafe control operations on the queue, or in case of error.
1758 * Generic pointer to TX queue structure.
1760 * Packets to transmit.
1762 * Number of packets in array.
1765 * Number of packets successfully transmitted (<= pkts_n).
1768 removed_tx_burst(void *dpdk_txq __rte_unused,
1769 struct rte_mbuf **pkts __rte_unused,
1770 uint16_t pkts_n __rte_unused)
1777 * Dummy DPDK callback for RX.
1779 * This function is used to temporarily replace the real callback during
1780 * unsafe control operations on the queue, or in case of error.
1783 * Generic pointer to RX queue structure.
1785 * Array to store received packets.
1787 * Maximum number of packets in array.
1790 * Number of packets successfully received (<= pkts_n).
1793 removed_rx_burst(void *dpdk_txq __rte_unused,
1794 struct rte_mbuf **pkts __rte_unused,
1795 uint16_t pkts_n __rte_unused)
1802 * Vectorized Rx/Tx routines are not compiled in when required vector
1803 * instructions are not supported on a target architecture. The following null
1804 * stubs are needed for linkage when those are not included outside of this file
1805 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1809 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1810 struct rte_mbuf **pkts __rte_unused,
1811 uint16_t pkts_n __rte_unused)
1817 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1818 struct rte_mbuf **pkts __rte_unused,
1819 uint16_t pkts_n __rte_unused)
1825 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1831 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1837 * Free the mbufs from the linear array of pointers.
1840 * Pointer to array of packets to be free.
1842 * Number of packets to be freed.
1844 * Configured Tx offloads mask. It is fully defined at
1845 * compile time and may be used for optimization.
1847 static __rte_always_inline void
1848 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1849 unsigned int pkts_n,
1850 unsigned int olx __rte_unused)
1852 struct rte_mempool *pool = NULL;
1853 struct rte_mbuf **p_free = NULL;
1854 struct rte_mbuf *mbuf;
1855 unsigned int n_free = 0;
1858 * The implemented algorithm eliminates
1859 * copying pointers to temporary array
1860 * for rte_mempool_put_bulk() calls.
1863 MLX5_ASSERT(pkts_n);
1867 * Decrement mbuf reference counter, detach
1868 * indirect and external buffers if needed.
1870 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1871 if (likely(mbuf != NULL)) {
1872 MLX5_ASSERT(mbuf == *pkts);
1873 if (likely(n_free != 0)) {
1874 if (unlikely(pool != mbuf->pool))
1875 /* From different pool. */
1878 /* Start new scan array. */
1885 if (unlikely(pkts_n == 0)) {
1891 * This happens if mbuf is still referenced.
1892 * We can't put it back to the pool, skip.
1896 if (unlikely(n_free != 0))
1897 /* There is some array to free.*/
1899 if (unlikely(pkts_n == 0))
1900 /* Last mbuf, nothing to free. */
1906 * This loop is implemented to avoid multiple
1907 * inlining of rte_mempool_put_bulk().
1910 MLX5_ASSERT(p_free);
1911 MLX5_ASSERT(n_free);
1913 * Free the array of pre-freed mbufs
1914 * belonging to the same memory pool.
1916 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1917 if (unlikely(mbuf != NULL)) {
1918 /* There is the request to start new scan. */
1923 if (likely(pkts_n != 0))
1926 * This is the last mbuf to be freed.
1927 * Do one more loop iteration to complete.
1928 * This is rare case of the last unique mbuf.
1933 if (likely(pkts_n == 0))
1942 * Free the mbuf from the elts ring buffer till new tail.
1945 * Pointer to Tx queue structure.
1947 * Index in elts to free up to, becomes new elts tail.
1949 * Configured Tx offloads mask. It is fully defined at
1950 * compile time and may be used for optimization.
1952 static __rte_always_inline void
1953 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
1955 unsigned int olx __rte_unused)
1957 uint16_t n_elts = tail - txq->elts_tail;
1959 MLX5_ASSERT(n_elts);
1960 MLX5_ASSERT(n_elts <= txq->elts_s);
1962 * Implement a loop to support ring buffer wraparound
1963 * with single inlining of mlx5_tx_free_mbuf().
1968 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1969 part = RTE_MIN(part, n_elts);
1971 MLX5_ASSERT(part <= txq->elts_s);
1972 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1974 txq->elts_tail += part;
1980 * Store the mbuf being sent into elts ring buffer.
1981 * On Tx completion these mbufs will be freed.
1984 * Pointer to Tx queue structure.
1986 * Pointer to array of packets to be stored.
1988 * Number of packets to be stored.
1990 * Configured Tx offloads mask. It is fully defined at
1991 * compile time and may be used for optimization.
1993 static __rte_always_inline void
1994 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
1995 struct rte_mbuf **__rte_restrict pkts,
1996 unsigned int pkts_n,
1997 unsigned int olx __rte_unused)
2000 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2003 MLX5_ASSERT(pkts_n);
2004 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2006 MLX5_ASSERT(part <= txq->elts_s);
2007 /* This code is a good candidate for vectorizing with SIMD. */
2008 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2010 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2011 txq->elts_head += pkts_n;
2012 if (unlikely(part < pkts_n))
2013 /* The copy is wrapping around the elts array. */
2014 rte_memcpy((void *)elts, (void *)(pkts + part),
2015 (pkts_n - part) * sizeof(struct rte_mbuf *));
2019 * Update completion queue consuming index via doorbell
2020 * and flush the completed data buffers.
2023 * Pointer to TX queue structure.
2024 * @param valid CQE pointer
2025 * if not NULL update txq->wqe_pi and flush the buffers
2027 * Configured Tx offloads mask. It is fully defined at
2028 * compile time and may be used for optimization.
2030 static __rte_always_inline void
2031 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2032 volatile struct mlx5_cqe *last_cqe,
2033 unsigned int olx __rte_unused)
2035 if (likely(last_cqe != NULL)) {
2038 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2039 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2040 if (likely(tail != txq->elts_tail)) {
2041 mlx5_tx_free_elts(txq, tail, olx);
2042 MLX5_ASSERT(tail == txq->elts_tail);
2048 * Manage TX completions. This routine checks the CQ for
2049 * arrived CQEs, deduces the last accomplished WQE in SQ,
2050 * updates SQ producing index and frees all completed mbufs.
2053 * Pointer to TX queue structure.
2055 * Configured Tx offloads mask. It is fully defined at
2056 * compile time and may be used for optimization.
2058 * NOTE: not inlined intentionally, it makes tx_burst
2059 * routine smaller, simple and faster - from experiments.
2062 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2063 unsigned int olx __rte_unused)
2065 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2066 volatile struct mlx5_cqe *last_cqe = NULL;
2067 bool ring_doorbell = false;
2070 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2071 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2073 volatile struct mlx5_cqe *cqe;
2075 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2076 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2077 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2078 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2079 /* No new CQEs in completion queue. */
2080 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2084 * Some error occurred, try to restart.
2085 * We have no barrier after WQE related Doorbell
2086 * written, make sure all writes are completed
2087 * here, before we might perform SQ reset.
2090 ret = mlx5_tx_error_cqe_handle
2091 (txq, (volatile struct mlx5_err_cqe *)cqe);
2092 if (unlikely(ret < 0)) {
2094 * Some error occurred on queue error
2095 * handling, we do not advance the index
2096 * here, allowing to retry on next call.
2101 * We are going to fetch all entries with
2102 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2103 * The send queue is supposed to be empty.
2105 ring_doorbell = true;
2107 txq->cq_pi = txq->cq_ci;
2111 /* Normal transmit completion. */
2112 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2113 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2115 ring_doorbell = true;
2119 * We have to restrict the amount of processed CQEs
2120 * in one tx_burst routine call. The CQ may be large
2121 * and many CQEs may be updated by the NIC in one
2122 * transaction. Buffers freeing is time consuming,
2123 * multiple iterations may introduce significant
2126 if (likely(--count == 0))
2129 if (likely(ring_doorbell)) {
2130 /* Ring doorbell to notify hardware. */
2131 rte_compiler_barrier();
2132 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2133 mlx5_tx_comp_flush(txq, last_cqe, olx);
2138 * Check if the completion request flag should be set in the last WQE.
2139 * Both pushed mbufs and WQEs are monitored and the completion request
2140 * flag is set if any of thresholds is reached.
2143 * Pointer to TX queue structure.
2145 * Pointer to burst routine local context.
2147 * Configured Tx offloads mask. It is fully defined at
2148 * compile time and may be used for optimization.
2150 static __rte_always_inline void
2151 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2152 struct mlx5_txq_local *__rte_restrict loc,
2155 uint16_t head = txq->elts_head;
2158 part = MLX5_TXOFF_CONFIG(INLINE) ?
2159 0 : loc->pkts_sent - loc->pkts_copy;
2161 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2162 (MLX5_TXOFF_CONFIG(INLINE) &&
2163 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2164 volatile struct mlx5_wqe *last = loc->wqe_last;
2167 txq->elts_comp = head;
2168 if (MLX5_TXOFF_CONFIG(INLINE))
2169 txq->wqe_comp = txq->wqe_ci;
2170 /* Request unconditional completion on last WQE. */
2171 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2172 MLX5_COMP_MODE_OFFSET);
2173 /* Save elts_head in dedicated free on completion queue. */
2174 #ifdef RTE_LIBRTE_MLX5_DEBUG
2175 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2176 (last->cseg.opcode >> 8) << 16;
2178 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2180 /* A CQE slot must always be available. */
2181 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2186 * DPDK callback to check the status of a tx descriptor.
2191 * The index of the descriptor in the ring.
2194 * The status of the tx descriptor.
2197 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2199 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2202 mlx5_tx_handle_completion(txq, 0);
2203 used = txq->elts_head - txq->elts_tail;
2205 return RTE_ETH_TX_DESC_FULL;
2206 return RTE_ETH_TX_DESC_DONE;
2210 * Build the Control Segment with specified opcode:
2211 * - MLX5_OPCODE_SEND
2212 * - MLX5_OPCODE_ENHANCED_MPSW
2216 * Pointer to TX queue structure.
2218 * Pointer to burst routine local context.
2220 * Pointer to WQE to fill with built Control Segment.
2222 * Supposed length of WQE in segments.
2224 * SQ WQE opcode to put into Control Segment.
2226 * Configured Tx offloads mask. It is fully defined at
2227 * compile time and may be used for optimization.
2229 static __rte_always_inline void
2230 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2231 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2232 struct mlx5_wqe *__rte_restrict wqe,
2234 unsigned int opcode,
2235 unsigned int olx __rte_unused)
2237 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2239 /* For legacy MPW replace the EMPW by TSO with modifier. */
2240 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2241 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2242 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2243 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2244 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2245 MLX5_COMP_MODE_OFFSET);
2246 cs->misc = RTE_BE32(0);
2250 * Build the Synchronize Queue Segment with specified completion index.
2253 * Pointer to TX queue structure.
2255 * Pointer to burst routine local context.
2257 * Pointer to WQE to fill with built Control Segment.
2259 * Completion index in Clock Queue to wait.
2261 * Configured Tx offloads mask. It is fully defined at
2262 * compile time and may be used for optimization.
2264 static __rte_always_inline void
2265 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2266 struct mlx5_txq_local *restrict loc __rte_unused,
2267 struct mlx5_wqe *restrict wqe,
2269 unsigned int olx __rte_unused)
2271 struct mlx5_wqe_qseg *qs;
2273 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2274 qs->max_index = rte_cpu_to_be_32(wci);
2275 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq->id);
2276 qs->reserved0 = RTE_BE32(0);
2277 qs->reserved1 = RTE_BE32(0);
2281 * Build the Ethernet Segment without inlined data.
2282 * Supports Software Parser, Checksums and VLAN
2283 * insertion Tx offload features.
2286 * Pointer to TX queue structure.
2288 * Pointer to burst routine local context.
2290 * Pointer to WQE to fill with built Ethernet Segment.
2292 * Configured Tx offloads mask. It is fully defined at
2293 * compile time and may be used for optimization.
2295 static __rte_always_inline void
2296 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2297 struct mlx5_txq_local *__rte_restrict loc,
2298 struct mlx5_wqe *__rte_restrict wqe,
2301 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2305 * Calculate and set check sum flags first, dword field
2306 * in segment may be shared with Software Parser flags.
2308 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2309 es->flags = rte_cpu_to_le_32(csum);
2311 * Calculate and set Software Parser offsets and flags.
2312 * These flags a set for custom UDP and IP tunnel packets.
2314 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2315 /* Fill metadata field if needed. */
2316 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2317 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2318 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2319 /* Engage VLAN tag insertion feature if requested. */
2320 if (MLX5_TXOFF_CONFIG(VLAN) &&
2321 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2323 * We should get here only if device support
2324 * this feature correctly.
2326 MLX5_ASSERT(txq->vlan_en);
2327 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2328 loc->mbuf->vlan_tci);
2330 es->inline_hdr = RTE_BE32(0);
2335 * Build the Ethernet Segment with minimal inlined data
2336 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2337 * used to fill the gap in single WQEBB WQEs.
2338 * Supports Software Parser, Checksums and VLAN
2339 * insertion Tx offload features.
2342 * Pointer to TX queue structure.
2344 * Pointer to burst routine local context.
2346 * Pointer to WQE to fill with built Ethernet Segment.
2348 * Length of VLAN tag insertion if any.
2350 * Configured Tx offloads mask. It is fully defined at
2351 * compile time and may be used for optimization.
2353 static __rte_always_inline void
2354 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2355 struct mlx5_txq_local *__rte_restrict loc,
2356 struct mlx5_wqe *__rte_restrict wqe,
2360 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2362 uint8_t *psrc, *pdst;
2365 * Calculate and set check sum flags first, dword field
2366 * in segment may be shared with Software Parser flags.
2368 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2369 es->flags = rte_cpu_to_le_32(csum);
2371 * Calculate and set Software Parser offsets and flags.
2372 * These flags a set for custom UDP and IP tunnel packets.
2374 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2375 /* Fill metadata field if needed. */
2376 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2377 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2378 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2379 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2381 sizeof(rte_v128u32_t)),
2382 "invalid Ethernet Segment data size");
2383 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2385 sizeof(struct rte_vlan_hdr) +
2386 2 * RTE_ETHER_ADDR_LEN),
2387 "invalid Ethernet Segment data size");
2388 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2389 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2390 es->inline_data = *(unaligned_uint16_t *)psrc;
2391 psrc += sizeof(uint16_t);
2392 pdst = (uint8_t *)(es + 1);
2393 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2394 /* Implement VLAN tag insertion as part inline data. */
2395 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2396 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2397 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2398 /* Insert VLAN ethertype + VLAN tag. */
2399 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2400 ((RTE_ETHER_TYPE_VLAN << 16) |
2401 loc->mbuf->vlan_tci);
2402 pdst += sizeof(struct rte_vlan_hdr);
2403 /* Copy the rest two bytes from packet data. */
2404 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2405 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2407 /* Fill the gap in the title WQEBB with inline data. */
2408 rte_mov16(pdst, psrc);
2413 * Build the Ethernet Segment with entire packet
2414 * data inlining. Checks the boundary of WQEBB and
2415 * ring buffer wrapping, supports Software Parser,
2416 * Checksums and VLAN insertion Tx offload features.
2419 * Pointer to TX queue structure.
2421 * Pointer to burst routine local context.
2423 * Pointer to WQE to fill with built Ethernet Segment.
2425 * Length of VLAN tag insertion if any.
2427 * Length of data to inline (VLAN included, if any).
2429 * TSO flag, set mss field from the packet.
2431 * Configured Tx offloads mask. It is fully defined at
2432 * compile time and may be used for optimization.
2435 * Pointer to the next Data Segment (aligned and wrapped around).
2437 static __rte_always_inline struct mlx5_wqe_dseg *
2438 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2439 struct mlx5_txq_local *__rte_restrict loc,
2440 struct mlx5_wqe *__rte_restrict wqe,
2446 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2448 uint8_t *psrc, *pdst;
2452 * Calculate and set check sum flags first, dword field
2453 * in segment may be shared with Software Parser flags.
2455 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2458 csum |= loc->mbuf->tso_segsz;
2459 es->flags = rte_cpu_to_be_32(csum);
2461 es->flags = rte_cpu_to_le_32(csum);
2464 * Calculate and set Software Parser offsets and flags.
2465 * These flags a set for custom UDP and IP tunnel packets.
2467 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2468 /* Fill metadata field if needed. */
2469 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2470 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2471 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2472 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2474 sizeof(rte_v128u32_t)),
2475 "invalid Ethernet Segment data size");
2476 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2478 sizeof(struct rte_vlan_hdr) +
2479 2 * RTE_ETHER_ADDR_LEN),
2480 "invalid Ethernet Segment data size");
2481 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2482 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2483 es->inline_data = *(unaligned_uint16_t *)psrc;
2484 psrc += sizeof(uint16_t);
2485 pdst = (uint8_t *)(es + 1);
2486 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2487 /* Implement VLAN tag insertion as part inline data. */
2488 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2489 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2490 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2491 /* Insert VLAN ethertype + VLAN tag. */
2492 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2493 ((RTE_ETHER_TYPE_VLAN << 16) |
2494 loc->mbuf->vlan_tci);
2495 pdst += sizeof(struct rte_vlan_hdr);
2496 /* Copy the rest two bytes from packet data. */
2497 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2498 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2499 psrc += sizeof(uint16_t);
2501 /* Fill the gap in the title WQEBB with inline data. */
2502 rte_mov16(pdst, psrc);
2503 psrc += sizeof(rte_v128u32_t);
2505 pdst = (uint8_t *)(es + 2);
2506 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2507 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2508 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2510 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2511 return (struct mlx5_wqe_dseg *)pdst;
2514 * The WQEBB space availability is checked by caller.
2515 * Here we should be aware of WQE ring buffer wraparound only.
2517 part = (uint8_t *)txq->wqes_end - pdst;
2518 part = RTE_MIN(part, inlen);
2520 rte_memcpy(pdst, psrc, part);
2522 if (likely(!inlen)) {
2524 * If return value is not used by the caller
2525 * the code below will be optimized out.
2528 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2529 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2530 pdst = (uint8_t *)txq->wqes;
2531 return (struct mlx5_wqe_dseg *)pdst;
2533 pdst = (uint8_t *)txq->wqes;
2540 * Copy data from chain of mbuf to the specified linear buffer.
2541 * Checksums and VLAN insertion Tx offload features. If data
2542 * from some mbuf copied completely this mbuf is freed. Local
2543 * structure is used to keep the byte stream state.
2546 * Pointer to the destination linear buffer.
2548 * Pointer to burst routine local context.
2550 * Length of data to be copied.
2552 * Length of data to be copied ignoring no inline hint.
2554 * Configured Tx offloads mask. It is fully defined at
2555 * compile time and may be used for optimization.
2558 * Number of actual copied data bytes. This is always greater than or
2559 * equal to must parameter and might be lesser than len in no inline
2560 * hint flag is encountered.
2562 static __rte_always_inline unsigned int
2563 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2564 struct mlx5_txq_local *__rte_restrict loc,
2567 unsigned int olx __rte_unused)
2569 struct rte_mbuf *mbuf;
2570 unsigned int part, dlen, copy = 0;
2574 MLX5_ASSERT(must <= len);
2576 /* Allow zero length packets, must check first. */
2577 dlen = rte_pktmbuf_data_len(loc->mbuf);
2578 if (dlen <= loc->mbuf_off) {
2579 /* Exhausted packet, just free. */
2581 loc->mbuf = mbuf->next;
2582 rte_pktmbuf_free_seg(mbuf);
2584 MLX5_ASSERT(loc->mbuf_nseg > 1);
2585 MLX5_ASSERT(loc->mbuf);
2587 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2592 * We already copied the minimal
2593 * requested amount of data.
2598 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2600 * Copy only the minimal required
2601 * part of the data buffer.
2608 dlen -= loc->mbuf_off;
2609 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2611 part = RTE_MIN(len, dlen);
2612 rte_memcpy(pdst, psrc, part);
2614 loc->mbuf_off += part;
2617 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2619 /* Exhausted packet, just free. */
2621 loc->mbuf = mbuf->next;
2622 rte_pktmbuf_free_seg(mbuf);
2624 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2634 * Build the Ethernet Segment with inlined data from
2635 * multi-segment packet. Checks the boundary of WQEBB
2636 * and ring buffer wrapping, supports Software Parser,
2637 * Checksums and VLAN insertion Tx offload features.
2640 * Pointer to TX queue structure.
2642 * Pointer to burst routine local context.
2644 * Pointer to WQE to fill with built Ethernet Segment.
2646 * Length of VLAN tag insertion if any.
2648 * Length of data to inline (VLAN included, if any).
2650 * TSO flag, set mss field from the packet.
2652 * Configured Tx offloads mask. It is fully defined at
2653 * compile time and may be used for optimization.
2656 * Pointer to the next Data Segment (aligned and
2657 * possible NOT wrapped around - caller should do
2658 * wrapping check on its own).
2660 static __rte_always_inline struct mlx5_wqe_dseg *
2661 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2662 struct mlx5_txq_local *__rte_restrict loc,
2663 struct mlx5_wqe *__rte_restrict wqe,
2669 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2672 unsigned int part, tlen = 0;
2675 * Calculate and set check sum flags first, uint32_t field
2676 * in segment may be shared with Software Parser flags.
2678 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2681 csum |= loc->mbuf->tso_segsz;
2682 es->flags = rte_cpu_to_be_32(csum);
2684 es->flags = rte_cpu_to_le_32(csum);
2687 * Calculate and set Software Parser offsets and flags.
2688 * These flags a set for custom UDP and IP tunnel packets.
2690 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2691 /* Fill metadata field if needed. */
2692 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2693 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2694 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2695 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2697 sizeof(rte_v128u32_t)),
2698 "invalid Ethernet Segment data size");
2699 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2701 sizeof(struct rte_vlan_hdr) +
2702 2 * RTE_ETHER_ADDR_LEN),
2703 "invalid Ethernet Segment data size");
2704 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2705 pdst = (uint8_t *)&es->inline_data;
2706 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2707 /* Implement VLAN tag insertion as part inline data. */
2708 mlx5_tx_mseg_memcpy(pdst, loc,
2709 2 * RTE_ETHER_ADDR_LEN,
2710 2 * RTE_ETHER_ADDR_LEN, olx);
2711 pdst += 2 * RTE_ETHER_ADDR_LEN;
2712 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2713 ((RTE_ETHER_TYPE_VLAN << 16) |
2714 loc->mbuf->vlan_tci);
2715 pdst += sizeof(struct rte_vlan_hdr);
2716 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2718 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2720 * The WQEBB space availability is checked by caller.
2721 * Here we should be aware of WQE ring buffer wraparound only.
2723 part = (uint8_t *)txq->wqes_end - pdst;
2724 part = RTE_MIN(part, inlen - tlen);
2730 * Copying may be interrupted inside the routine
2731 * if run into no inline hint flag.
2733 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2734 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2736 if (likely(inlen <= tlen) || copy < part) {
2737 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2739 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2740 return (struct mlx5_wqe_dseg *)pdst;
2742 pdst = (uint8_t *)txq->wqes;
2743 part = inlen - tlen;
2748 * Build the Data Segment of pointer type.
2751 * Pointer to TX queue structure.
2753 * Pointer to burst routine local context.
2755 * Pointer to WQE to fill with built Data Segment.
2757 * Data buffer to point.
2759 * Data buffer length.
2761 * Configured Tx offloads mask. It is fully defined at
2762 * compile time and may be used for optimization.
2764 static __rte_always_inline void
2765 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2766 struct mlx5_txq_local *__rte_restrict loc,
2767 struct mlx5_wqe_dseg *__rte_restrict dseg,
2770 unsigned int olx __rte_unused)
2774 dseg->bcount = rte_cpu_to_be_32(len);
2775 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2776 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2780 * Build the Data Segment of pointer type or inline
2781 * if data length is less than buffer in minimal
2782 * Data Segment size.
2785 * Pointer to TX queue structure.
2787 * Pointer to burst routine local context.
2789 * Pointer to WQE to fill with built Data Segment.
2791 * Data buffer to point.
2793 * Data buffer length.
2795 * Configured Tx offloads mask. It is fully defined at
2796 * compile time and may be used for optimization.
2798 static __rte_always_inline void
2799 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2800 struct mlx5_txq_local *__rte_restrict loc,
2801 struct mlx5_wqe_dseg *__rte_restrict dseg,
2804 unsigned int olx __rte_unused)
2810 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2811 dseg->bcount = rte_cpu_to_be_32(len);
2812 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2813 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2817 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2818 /* Unrolled implementation of generic rte_memcpy. */
2819 dst = (uintptr_t)&dseg->inline_data[0];
2820 src = (uintptr_t)buf;
2822 #ifdef RTE_ARCH_STRICT_ALIGN
2823 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2824 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2825 dst += sizeof(uint32_t);
2826 src += sizeof(uint32_t);
2827 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2828 dst += sizeof(uint32_t);
2829 src += sizeof(uint32_t);
2831 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2832 dst += sizeof(uint64_t);
2833 src += sizeof(uint64_t);
2837 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2838 dst += sizeof(uint32_t);
2839 src += sizeof(uint32_t);
2842 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2843 dst += sizeof(uint16_t);
2844 src += sizeof(uint16_t);
2847 *(uint8_t *)dst = *(uint8_t *)src;
2851 * Build the Data Segment of inlined data from single
2852 * segment packet, no VLAN insertion.
2855 * Pointer to TX queue structure.
2857 * Pointer to burst routine local context.
2859 * Pointer to WQE to fill with built Data Segment.
2861 * Data buffer to point.
2863 * Data buffer length.
2865 * Configured Tx offloads mask. It is fully defined at
2866 * compile time and may be used for optimization.
2869 * Pointer to the next Data Segment after inlined data.
2870 * Ring buffer wraparound check is needed. We do not
2871 * do it here because it may not be needed for the
2872 * last packet in the eMPW session.
2874 static __rte_always_inline struct mlx5_wqe_dseg *
2875 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2876 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2877 struct mlx5_wqe_dseg *__rte_restrict dseg,
2880 unsigned int olx __rte_unused)
2885 if (!MLX5_TXOFF_CONFIG(MPW)) {
2886 /* Store the descriptor byte counter for eMPW sessions. */
2887 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2888 pdst = &dseg->inline_data[0];
2890 /* The entire legacy MPW session counter is stored on close. */
2891 pdst = (uint8_t *)dseg;
2894 * The WQEBB space availability is checked by caller.
2895 * Here we should be aware of WQE ring buffer wraparound only.
2897 part = (uint8_t *)txq->wqes_end - pdst;
2898 part = RTE_MIN(part, len);
2900 rte_memcpy(pdst, buf, part);
2904 if (!MLX5_TXOFF_CONFIG(MPW))
2905 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2906 /* Note: no final wraparound check here. */
2907 return (struct mlx5_wqe_dseg *)pdst;
2909 pdst = (uint8_t *)txq->wqes;
2916 * Build the Data Segment of inlined data from single
2917 * segment packet with VLAN insertion.
2920 * Pointer to TX queue structure.
2922 * Pointer to burst routine local context.
2924 * Pointer to the dseg fill with built Data Segment.
2926 * Data buffer to point.
2928 * Data buffer length.
2930 * Configured Tx offloads mask. It is fully defined at
2931 * compile time and may be used for optimization.
2934 * Pointer to the next Data Segment after inlined data.
2935 * Ring buffer wraparound check is needed.
2937 static __rte_always_inline struct mlx5_wqe_dseg *
2938 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2939 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2940 struct mlx5_wqe_dseg *__rte_restrict dseg,
2943 unsigned int olx __rte_unused)
2949 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2950 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2951 (2 * RTE_ETHER_ADDR_LEN),
2952 "invalid Data Segment data size");
2953 if (!MLX5_TXOFF_CONFIG(MPW)) {
2954 /* Store the descriptor byte counter for eMPW sessions. */
2955 dseg->bcount = rte_cpu_to_be_32
2956 ((len + sizeof(struct rte_vlan_hdr)) |
2957 MLX5_ETH_WQE_DATA_INLINE);
2958 pdst = &dseg->inline_data[0];
2960 /* The entire legacy MPW session counter is stored on close. */
2961 pdst = (uint8_t *)dseg;
2963 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2964 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2965 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2966 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2967 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2968 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2969 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2970 pdst = (uint8_t *)txq->wqes;
2971 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2972 loc->mbuf->vlan_tci);
2973 pdst += sizeof(struct rte_vlan_hdr);
2975 * The WQEBB space availability is checked by caller.
2976 * Here we should be aware of WQE ring buffer wraparound only.
2978 part = (uint8_t *)txq->wqes_end - pdst;
2979 part = RTE_MIN(part, len);
2981 rte_memcpy(pdst, buf, part);
2985 if (!MLX5_TXOFF_CONFIG(MPW))
2986 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2987 /* Note: no final wraparound check here. */
2988 return (struct mlx5_wqe_dseg *)pdst;
2990 pdst = (uint8_t *)txq->wqes;
2997 * Build the Ethernet Segment with optionally inlined data with
2998 * VLAN insertion and following Data Segments (if any) from
2999 * multi-segment packet. Used by ordinary send and TSO.
3002 * Pointer to TX queue structure.
3004 * Pointer to burst routine local context.
3006 * Pointer to WQE to fill with built Ethernet/Data Segments.
3008 * Length of VLAN header to insert, 0 means no VLAN insertion.
3010 * Data length to inline. For TSO this parameter specifies
3011 * exact value, for ordinary send routine can be aligned by
3012 * caller to provide better WQE space saving and data buffer
3013 * start address alignment. This length includes VLAN header
3016 * Zero means ordinary send, inlined data can be extended,
3017 * otherwise this is TSO, inlined data length is fixed.
3019 * Configured Tx offloads mask. It is fully defined at
3020 * compile time and may be used for optimization.
3023 * Actual size of built WQE in segments.
3025 static __rte_always_inline unsigned int
3026 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3027 struct mlx5_txq_local *__rte_restrict loc,
3028 struct mlx5_wqe *__rte_restrict wqe,
3032 unsigned int olx __rte_unused)
3034 struct mlx5_wqe_dseg *__rte_restrict dseg;
3037 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3038 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3041 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3042 if (!loc->mbuf_nseg)
3045 * There are still some mbuf remaining, not inlined.
3046 * The first mbuf may be partially inlined and we
3047 * must process the possible non-zero data offset.
3049 if (loc->mbuf_off) {
3054 * Exhausted packets must be dropped before.
3055 * Non-zero offset means there are some data
3056 * remained in the packet.
3058 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3059 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3060 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3062 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3064 * Build the pointer/minimal data Data Segment.
3065 * Do ring buffer wrapping check in advance.
3067 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3068 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3069 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3070 /* Store the mbuf to be freed on completion. */
3071 MLX5_ASSERT(loc->elts_free);
3072 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3075 if (--loc->mbuf_nseg == 0)
3077 loc->mbuf = loc->mbuf->next;
3081 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3082 struct rte_mbuf *mbuf;
3084 /* Zero length segment found, just skip. */
3086 loc->mbuf = loc->mbuf->next;
3087 rte_pktmbuf_free_seg(mbuf);
3088 if (--loc->mbuf_nseg == 0)
3091 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3092 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3095 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3096 rte_pktmbuf_data_len(loc->mbuf), olx);
3097 MLX5_ASSERT(loc->elts_free);
3098 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3101 if (--loc->mbuf_nseg == 0)
3103 loc->mbuf = loc->mbuf->next;
3108 /* Calculate actual segments used from the dseg pointer. */
3109 if ((uintptr_t)wqe < (uintptr_t)dseg)
3110 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3112 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3113 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3118 * The routine checks timestamp flag in the current packet,
3119 * and push WAIT WQE into the queue if scheduling is required.
3122 * Pointer to TX queue structure.
3124 * Pointer to burst routine local context.
3126 * Configured Tx offloads mask. It is fully defined at
3127 * compile time and may be used for optimization.
3130 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3131 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3132 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3133 * Local context variables partially updated.
3135 static __rte_always_inline enum mlx5_txcmp_code
3136 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3137 struct mlx5_txq_local *restrict loc,
3140 if (MLX5_TXOFF_CONFIG(TXPP) &&
3141 loc->mbuf->ol_flags & txq->ts_mask) {
3142 struct mlx5_wqe *wqe;
3147 * Estimate the required space quickly and roughly.
3148 * We would like to ensure the packet can be pushed
3149 * to the queue and we won't get the orphan WAIT WQE.
3151 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3152 loc->elts_free < NB_SEGS(loc->mbuf))
3153 return MLX5_TXCMP_CODE_EXIT;
3154 /* Convert the timestamp into completion to wait. */
3155 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3156 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3157 if (unlikely(wci < 0))
3158 return MLX5_TXCMP_CODE_SINGLE;
3159 /* Build the WAIT WQE with specified completion. */
3160 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3161 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3162 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3165 return MLX5_TXCMP_CODE_MULTI;
3167 return MLX5_TXCMP_CODE_SINGLE;
3171 * Tx one packet function for multi-segment TSO. Supports all
3172 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3173 * sends one packet per WQE.
3175 * This routine is responsible for storing processed mbuf
3176 * into elts ring buffer and update elts_head.
3179 * Pointer to TX queue structure.
3181 * Pointer to burst routine local context.
3183 * Configured Tx offloads mask. It is fully defined at
3184 * compile time and may be used for optimization.
3187 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3188 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3189 * Local context variables partially updated.
3191 static __rte_always_inline enum mlx5_txcmp_code
3192 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3193 struct mlx5_txq_local *__rte_restrict loc,
3196 struct mlx5_wqe *__rte_restrict wqe;
3197 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3199 if (MLX5_TXOFF_CONFIG(TXPP)) {
3200 enum mlx5_txcmp_code wret;
3202 /* Generate WAIT for scheduling if requested. */
3203 wret = mlx5_tx_schedule_send(txq, loc, olx);
3204 if (wret == MLX5_TXCMP_CODE_EXIT)
3205 return MLX5_TXCMP_CODE_EXIT;
3206 if (wret == MLX5_TXCMP_CODE_ERROR)
3207 return MLX5_TXCMP_CODE_ERROR;
3210 * Calculate data length to be inlined to estimate
3211 * the required space in WQE ring buffer.
3213 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3214 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3215 vlan = sizeof(struct rte_vlan_hdr);
3216 inlen = loc->mbuf->l2_len + vlan +
3217 loc->mbuf->l3_len + loc->mbuf->l4_len;
3218 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3219 return MLX5_TXCMP_CODE_ERROR;
3220 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3221 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3222 /* Packet must contain all TSO headers. */
3223 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3224 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3225 inlen > (dlen + vlan)))
3226 return MLX5_TXCMP_CODE_ERROR;
3227 MLX5_ASSERT(inlen >= txq->inlen_mode);
3229 * Check whether there are enough free WQEBBs:
3231 * - Ethernet Segment
3232 * - First Segment of inlined Ethernet data
3233 * - ... data continued ...
3234 * - Data Segments of pointer/min inline type
3236 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3237 MLX5_ESEG_MIN_INLINE_SIZE +
3239 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3240 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3241 return MLX5_TXCMP_CODE_EXIT;
3242 /* Check for maximal WQE size. */
3243 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3244 return MLX5_TXCMP_CODE_ERROR;
3245 #ifdef MLX5_PMD_SOFT_COUNTERS
3246 /* Update sent data bytes/packets counters. */
3247 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3248 loc->mbuf->tso_segsz;
3250 * One will be added for mbuf itself
3251 * at the end of the mlx5_tx_burst from
3252 * loc->pkts_sent field.
3255 txq->stats.opackets += ntcp;
3256 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3258 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3259 loc->wqe_last = wqe;
3260 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3261 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3262 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3263 txq->wqe_ci += (ds + 3) / 4;
3264 loc->wqe_free -= (ds + 3) / 4;
3265 return MLX5_TXCMP_CODE_MULTI;
3269 * Tx one packet function for multi-segment SEND. Supports all
3270 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3271 * sends one packet per WQE, without any data inlining in
3274 * This routine is responsible for storing processed mbuf
3275 * into elts ring buffer and update elts_head.
3278 * Pointer to TX queue structure.
3280 * Pointer to burst routine local context.
3282 * Configured Tx offloads mask. It is fully defined at
3283 * compile time and may be used for optimization.
3286 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3287 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3288 * Local context variables partially updated.
3290 static __rte_always_inline enum mlx5_txcmp_code
3291 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3292 struct mlx5_txq_local *__rte_restrict loc,
3295 struct mlx5_wqe_dseg *__rte_restrict dseg;
3296 struct mlx5_wqe *__rte_restrict wqe;
3297 unsigned int ds, nseg;
3299 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3300 if (MLX5_TXOFF_CONFIG(TXPP)) {
3301 enum mlx5_txcmp_code wret;
3303 /* Generate WAIT for scheduling if requested. */
3304 wret = mlx5_tx_schedule_send(txq, loc, olx);
3305 if (wret == MLX5_TXCMP_CODE_EXIT)
3306 return MLX5_TXCMP_CODE_EXIT;
3307 if (wret == MLX5_TXCMP_CODE_ERROR)
3308 return MLX5_TXCMP_CODE_ERROR;
3311 * No inline at all, it means the CPU cycles saving
3312 * is prioritized at configuration, we should not
3313 * copy any packet data to WQE.
3315 nseg = NB_SEGS(loc->mbuf);
3317 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3318 return MLX5_TXCMP_CODE_EXIT;
3319 /* Check for maximal WQE size. */
3320 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3321 return MLX5_TXCMP_CODE_ERROR;
3323 * Some Tx offloads may cause an error if
3324 * packet is not long enough, check against
3325 * assumed minimal length.
3327 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3328 return MLX5_TXCMP_CODE_ERROR;
3329 #ifdef MLX5_PMD_SOFT_COUNTERS
3330 /* Update sent data bytes counter. */
3331 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3332 if (MLX5_TXOFF_CONFIG(VLAN) &&
3333 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3334 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3337 * SEND WQE, one WQEBB:
3338 * - Control Segment, SEND opcode
3339 * - Ethernet Segment, optional VLAN, no inline
3340 * - Data Segments, pointer only type
3342 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3343 loc->wqe_last = wqe;
3344 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3345 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3346 dseg = &wqe->dseg[0];
3348 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3349 struct rte_mbuf *mbuf;
3352 * Zero length segment found, have to
3353 * correct total size of WQE in segments.
3354 * It is supposed to be rare occasion, so
3355 * in normal case (no zero length segments)
3356 * we avoid extra writing to the Control
3360 wqe->cseg.sq_ds -= RTE_BE32(1);
3362 loc->mbuf = mbuf->next;
3363 rte_pktmbuf_free_seg(mbuf);
3369 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3370 rte_pktmbuf_data_len(loc->mbuf), olx);
3371 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3376 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3377 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3378 loc->mbuf = loc->mbuf->next;
3381 txq->wqe_ci += (ds + 3) / 4;
3382 loc->wqe_free -= (ds + 3) / 4;
3383 return MLX5_TXCMP_CODE_MULTI;
3387 * Tx one packet function for multi-segment SEND. Supports all
3388 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3389 * sends one packet per WQE, with data inlining in
3390 * Ethernet Segment and minimal Data Segments.
3392 * This routine is responsible for storing processed mbuf
3393 * into elts ring buffer and update elts_head.
3396 * Pointer to TX queue structure.
3398 * Pointer to burst routine local context.
3400 * Configured Tx offloads mask. It is fully defined at
3401 * compile time and may be used for optimization.
3404 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3405 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3406 * Local context variables partially updated.
3408 static __rte_always_inline enum mlx5_txcmp_code
3409 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3410 struct mlx5_txq_local *__rte_restrict loc,
3413 struct mlx5_wqe *__rte_restrict wqe;
3414 unsigned int ds, inlen, dlen, vlan = 0;
3416 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3417 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3418 if (MLX5_TXOFF_CONFIG(TXPP)) {
3419 enum mlx5_txcmp_code wret;
3421 /* Generate WAIT for scheduling if requested. */
3422 wret = mlx5_tx_schedule_send(txq, loc, olx);
3423 if (wret == MLX5_TXCMP_CODE_EXIT)
3424 return MLX5_TXCMP_CODE_EXIT;
3425 if (wret == MLX5_TXCMP_CODE_ERROR)
3426 return MLX5_TXCMP_CODE_ERROR;
3429 * First calculate data length to be inlined
3430 * to estimate the required space for WQE.
3432 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3433 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3434 vlan = sizeof(struct rte_vlan_hdr);
3435 inlen = dlen + vlan;
3436 /* Check against minimal length. */
3437 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3438 return MLX5_TXCMP_CODE_ERROR;
3439 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3440 if (inlen > txq->inlen_send ||
3441 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3442 struct rte_mbuf *mbuf;
3447 * Packet length exceeds the allowed inline
3448 * data length, check whether the minimal
3449 * inlining is required.
3451 if (txq->inlen_mode) {
3452 MLX5_ASSERT(txq->inlen_mode >=
3453 MLX5_ESEG_MIN_INLINE_SIZE);
3454 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3455 inlen = txq->inlen_mode;
3457 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3458 !vlan || txq->vlan_en) {
3460 * VLAN insertion will be done inside by HW.
3461 * It is not utmost effective - VLAN flag is
3462 * checked twice, but we should proceed the
3463 * inlining length correctly and take into
3464 * account the VLAN header being inserted.
3466 return mlx5_tx_packet_multi_send
3469 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3472 * Now we know the minimal amount of data is requested
3473 * to inline. Check whether we should inline the buffers
3474 * from the chain beginning to eliminate some mbufs.
3477 nxlen = rte_pktmbuf_data_len(mbuf);
3478 if (unlikely(nxlen <= txq->inlen_send)) {
3479 /* We can inline first mbuf at least. */
3480 if (nxlen < inlen) {
3483 /* Scan mbufs till inlen filled. */
3488 nxlen = rte_pktmbuf_data_len(mbuf);
3490 } while (unlikely(nxlen < inlen));
3491 if (unlikely(nxlen > txq->inlen_send)) {
3492 /* We cannot inline entire mbuf. */
3493 smlen = inlen - smlen;
3494 start = rte_pktmbuf_mtod_offset
3495 (mbuf, uintptr_t, smlen);
3502 /* There should be not end of packet. */
3504 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3505 } while (unlikely(nxlen < txq->inlen_send));
3507 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3509 * Check whether we can do inline to align start
3510 * address of data buffer to cacheline.
3513 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3514 if (unlikely(start)) {
3516 if (start <= txq->inlen_send)
3521 * Check whether there are enough free WQEBBs:
3523 * - Ethernet Segment
3524 * - First Segment of inlined Ethernet data
3525 * - ... data continued ...
3526 * - Data Segments of pointer/min inline type
3528 * Estimate the number of Data Segments conservatively,
3529 * supposing no any mbufs is being freed during inlining.
3531 MLX5_ASSERT(inlen <= txq->inlen_send);
3532 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3533 MLX5_ESEG_MIN_INLINE_SIZE +
3535 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3536 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3537 return MLX5_TXCMP_CODE_EXIT;
3538 /* Check for maximal WQE size. */
3539 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3540 return MLX5_TXCMP_CODE_ERROR;
3541 #ifdef MLX5_PMD_SOFT_COUNTERS
3542 /* Update sent data bytes/packets counters. */
3543 txq->stats.obytes += dlen + vlan;
3545 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3546 loc->wqe_last = wqe;
3547 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3548 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3549 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3550 txq->wqe_ci += (ds + 3) / 4;
3551 loc->wqe_free -= (ds + 3) / 4;
3552 return MLX5_TXCMP_CODE_MULTI;
3556 * Tx burst function for multi-segment packets. Supports all
3557 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3558 * sends one packet per WQE. Function stops sending if it
3559 * encounters the single-segment packet.
3561 * This routine is responsible for storing processed mbuf
3562 * into elts ring buffer and update elts_head.
3565 * Pointer to TX queue structure.
3567 * Packets to transmit.
3569 * Number of packets in array.
3571 * Pointer to burst routine local context.
3573 * Configured Tx offloads mask. It is fully defined at
3574 * compile time and may be used for optimization.
3577 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3578 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3579 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3580 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3581 * Local context variables updated.
3583 static __rte_always_inline enum mlx5_txcmp_code
3584 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3585 struct rte_mbuf **__rte_restrict pkts,
3586 unsigned int pkts_n,
3587 struct mlx5_txq_local *__rte_restrict loc,
3590 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3591 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3592 pkts += loc->pkts_sent + 1;
3593 pkts_n -= loc->pkts_sent;
3595 enum mlx5_txcmp_code ret;
3597 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3599 * Estimate the number of free elts quickly but
3600 * conservatively. Some segment may be fully inlined
3601 * and freed, ignore this here - precise estimation
3604 if (loc->elts_free < NB_SEGS(loc->mbuf))
3605 return MLX5_TXCMP_CODE_EXIT;
3606 if (MLX5_TXOFF_CONFIG(TSO) &&
3607 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3608 /* Proceed with multi-segment TSO. */
3609 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3610 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3611 /* Proceed with multi-segment SEND with inlining. */
3612 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3614 /* Proceed with multi-segment SEND w/o inlining. */
3615 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3617 if (ret == MLX5_TXCMP_CODE_EXIT)
3618 return MLX5_TXCMP_CODE_EXIT;
3619 if (ret == MLX5_TXCMP_CODE_ERROR)
3620 return MLX5_TXCMP_CODE_ERROR;
3621 /* WQE is built, go to the next packet. */
3624 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3625 return MLX5_TXCMP_CODE_EXIT;
3626 loc->mbuf = *pkts++;
3628 rte_prefetch0(*pkts);
3629 if (likely(NB_SEGS(loc->mbuf) > 1))
3631 /* Here ends the series of multi-segment packets. */
3632 if (MLX5_TXOFF_CONFIG(TSO) &&
3633 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3634 return MLX5_TXCMP_CODE_TSO;
3635 return MLX5_TXCMP_CODE_SINGLE;
3641 * Tx burst function for single-segment packets with TSO.
3642 * Supports all types of Tx offloads, except multi-packets.
3643 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3644 * Function stops sending if it encounters the multi-segment
3645 * packet or packet without TSO requested.
3647 * The routine is responsible for storing processed mbuf
3648 * into elts ring buffer and update elts_head if inline
3649 * offloads is requested due to possible early freeing
3650 * of the inlined mbufs (can not store pkts array in elts
3654 * Pointer to TX queue structure.
3656 * Packets to transmit.
3658 * Number of packets in array.
3660 * Pointer to burst routine local context.
3662 * Configured Tx offloads mask. It is fully defined at
3663 * compile time and may be used for optimization.
3666 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3667 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3668 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3669 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3670 * Local context variables updated.
3672 static __rte_always_inline enum mlx5_txcmp_code
3673 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3674 struct rte_mbuf **__rte_restrict pkts,
3675 unsigned int pkts_n,
3676 struct mlx5_txq_local *__rte_restrict loc,
3679 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3680 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3681 pkts += loc->pkts_sent + 1;
3682 pkts_n -= loc->pkts_sent;
3684 struct mlx5_wqe_dseg *__rte_restrict dseg;
3685 struct mlx5_wqe *__rte_restrict wqe;
3686 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3689 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3690 if (MLX5_TXOFF_CONFIG(TXPP)) {
3691 enum mlx5_txcmp_code wret;
3693 /* Generate WAIT for scheduling if requested. */
3694 wret = mlx5_tx_schedule_send(txq, loc, olx);
3695 if (wret == MLX5_TXCMP_CODE_EXIT)
3696 return MLX5_TXCMP_CODE_EXIT;
3697 if (wret == MLX5_TXCMP_CODE_ERROR)
3698 return MLX5_TXCMP_CODE_ERROR;
3700 dlen = rte_pktmbuf_data_len(loc->mbuf);
3701 if (MLX5_TXOFF_CONFIG(VLAN) &&
3702 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3703 vlan = sizeof(struct rte_vlan_hdr);
3706 * First calculate the WQE size to check
3707 * whether we have enough space in ring buffer.
3709 hlen = loc->mbuf->l2_len + vlan +
3710 loc->mbuf->l3_len + loc->mbuf->l4_len;
3711 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3712 return MLX5_TXCMP_CODE_ERROR;
3713 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3714 hlen += loc->mbuf->outer_l2_len +
3715 loc->mbuf->outer_l3_len;
3716 /* Segment must contain all TSO headers. */
3717 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3718 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3719 hlen > (dlen + vlan)))
3720 return MLX5_TXCMP_CODE_ERROR;
3722 * Check whether there are enough free WQEBBs:
3724 * - Ethernet Segment
3725 * - First Segment of inlined Ethernet data
3726 * - ... data continued ...
3727 * - Finishing Data Segment of pointer type
3729 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3730 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3731 if (loc->wqe_free < ((ds + 3) / 4))
3732 return MLX5_TXCMP_CODE_EXIT;
3733 #ifdef MLX5_PMD_SOFT_COUNTERS
3734 /* Update sent data bytes/packets counters. */
3735 ntcp = (dlen + vlan - hlen +
3736 loc->mbuf->tso_segsz - 1) /
3737 loc->mbuf->tso_segsz;
3739 * One will be added for mbuf itself at the end
3740 * of the mlx5_tx_burst from loc->pkts_sent field.
3743 txq->stats.opackets += ntcp;
3744 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3747 * Build the TSO WQE:
3749 * - Ethernet Segment with hlen bytes inlined
3750 * - Data Segment of pointer type
3752 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3753 loc->wqe_last = wqe;
3754 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3755 MLX5_OPCODE_TSO, olx);
3756 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3757 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3758 dlen -= hlen - vlan;
3759 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3761 * WQE is built, update the loop parameters
3762 * and go to the next packet.
3764 txq->wqe_ci += (ds + 3) / 4;
3765 loc->wqe_free -= (ds + 3) / 4;
3766 if (MLX5_TXOFF_CONFIG(INLINE))
3767 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3771 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3772 return MLX5_TXCMP_CODE_EXIT;
3773 loc->mbuf = *pkts++;
3775 rte_prefetch0(*pkts);
3776 if (MLX5_TXOFF_CONFIG(MULTI) &&
3777 unlikely(NB_SEGS(loc->mbuf) > 1))
3778 return MLX5_TXCMP_CODE_MULTI;
3779 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3780 return MLX5_TXCMP_CODE_SINGLE;
3781 /* Continue with the next TSO packet. */
3787 * Analyze the packet and select the best method to send.
3790 * Pointer to TX queue structure.
3792 * Pointer to burst routine local context.
3794 * Configured Tx offloads mask. It is fully defined at
3795 * compile time and may be used for optimization.
3797 * The predefined flag whether do complete check for
3798 * multi-segment packets and TSO.
3801 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3802 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3803 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3804 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3806 static __rte_always_inline enum mlx5_txcmp_code
3807 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3808 struct mlx5_txq_local *__rte_restrict loc,
3812 /* Check for multi-segment packet. */
3814 MLX5_TXOFF_CONFIG(MULTI) &&
3815 unlikely(NB_SEGS(loc->mbuf) > 1))
3816 return MLX5_TXCMP_CODE_MULTI;
3817 /* Check for TSO packet. */
3819 MLX5_TXOFF_CONFIG(TSO) &&
3820 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3821 return MLX5_TXCMP_CODE_TSO;
3822 /* Check if eMPW is enabled at all. */
3823 if (!MLX5_TXOFF_CONFIG(EMPW))
3824 return MLX5_TXCMP_CODE_SINGLE;
3825 /* Check if eMPW can be engaged. */
3826 if (MLX5_TXOFF_CONFIG(VLAN) &&
3827 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3828 (!MLX5_TXOFF_CONFIG(INLINE) ||
3829 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3830 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3832 * eMPW does not support VLAN insertion offload,
3833 * we have to inline the entire packet but
3834 * packet is too long for inlining.
3836 return MLX5_TXCMP_CODE_SINGLE;
3838 return MLX5_TXCMP_CODE_EMPW;
3842 * Check the next packet attributes to match with the eMPW batch ones.
3843 * In addition, for legacy MPW the packet length is checked either.
3846 * Pointer to TX queue structure.
3848 * Pointer to Ethernet Segment of eMPW batch.
3850 * Pointer to burst routine local context.
3852 * Length of previous packet in MPW descriptor.
3854 * Configured Tx offloads mask. It is fully defined at
3855 * compile time and may be used for optimization.
3858 * true - packet match with eMPW batch attributes.
3859 * false - no match, eMPW should be restarted.
3861 static __rte_always_inline bool
3862 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3863 struct mlx5_wqe_eseg *__rte_restrict es,
3864 struct mlx5_txq_local *__rte_restrict loc,
3868 uint8_t swp_flags = 0;
3870 /* Compare the checksum flags, if any. */
3871 if (MLX5_TXOFF_CONFIG(CSUM) &&
3872 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3874 /* Compare the Software Parser offsets and flags. */
3875 if (MLX5_TXOFF_CONFIG(SWP) &&
3876 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3877 es->swp_flags != swp_flags))
3879 /* Fill metadata field if needed. */
3880 if (MLX5_TXOFF_CONFIG(METADATA) &&
3881 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3882 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3884 /* Legacy MPW can send packets with the same lengt only. */
3885 if (MLX5_TXOFF_CONFIG(MPW) &&
3886 dlen != rte_pktmbuf_data_len(loc->mbuf))
3888 /* There must be no VLAN packets in eMPW loop. */
3889 if (MLX5_TXOFF_CONFIG(VLAN))
3890 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3891 /* Check if the scheduling is requested. */
3892 if (MLX5_TXOFF_CONFIG(TXPP) &&
3893 loc->mbuf->ol_flags & txq->ts_mask)
3899 * Update send loop variables and WQE for eMPW loop
3900 * without data inlining. Number of Data Segments is
3901 * equal to the number of sent packets.
3904 * Pointer to TX queue structure.
3906 * Pointer to burst routine local context.
3908 * Number of packets/Data Segments/Packets.
3910 * Accumulated statistics, bytes sent
3912 * Configured Tx offloads mask. It is fully defined at
3913 * compile time and may be used for optimization.
3916 * true - packet match with eMPW batch attributes.
3917 * false - no match, eMPW should be restarted.
3919 static __rte_always_inline void
3920 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3921 struct mlx5_txq_local *__rte_restrict loc,
3924 unsigned int olx __rte_unused)
3926 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3927 #ifdef MLX5_PMD_SOFT_COUNTERS
3928 /* Update sent data bytes counter. */
3929 txq->stats.obytes += slen;
3933 loc->elts_free -= ds;
3934 loc->pkts_sent += ds;
3936 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3937 txq->wqe_ci += (ds + 3) / 4;
3938 loc->wqe_free -= (ds + 3) / 4;
3942 * Update send loop variables and WQE for eMPW loop
3943 * with data inlining. Gets the size of pushed descriptors
3944 * and data to the WQE.
3947 * Pointer to TX queue structure.
3949 * Pointer to burst routine local context.
3951 * Total size of descriptor/data in bytes.
3953 * Accumulated statistics, data bytes sent.
3955 * The base WQE for the eMPW/MPW descriptor.
3957 * Configured Tx offloads mask. It is fully defined at
3958 * compile time and may be used for optimization.
3961 * true - packet match with eMPW batch attributes.
3962 * false - no match, eMPW should be restarted.
3964 static __rte_always_inline void
3965 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
3966 struct mlx5_txq_local *__rte_restrict loc,
3969 struct mlx5_wqe *__rte_restrict wqem,
3970 unsigned int olx __rte_unused)
3972 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
3974 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3975 #ifdef MLX5_PMD_SOFT_COUNTERS
3976 /* Update sent data bytes counter. */
3977 txq->stats.obytes += slen;
3981 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
3983 * If the legacy MPW session contains the inline packets
3984 * we should set the only inline data segment length
3985 * and align the total length to the segment size.
3987 MLX5_ASSERT(len > sizeof(dseg->bcount));
3988 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
3989 MLX5_ETH_WQE_DATA_INLINE);
3990 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
3993 * The session is not legacy MPW or contains the
3994 * data buffer pointer segments.
3996 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
3997 len = len / MLX5_WSEG_SIZE + 2;
3999 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4000 txq->wqe_ci += (len + 3) / 4;
4001 loc->wqe_free -= (len + 3) / 4;
4002 loc->wqe_last = wqem;
4006 * The set of Tx burst functions for single-segment packets
4007 * without TSO and with Multi-Packet Writing feature support.
4008 * Supports all types of Tx offloads, except multi-packets
4011 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4012 * as many packet per WQE as it can. If eMPW is not configured
4013 * or packet can not be sent with eMPW (VLAN insertion) the
4014 * ordinary SEND opcode is used and only one packet placed
4017 * Functions stop sending if it encounters the multi-segment
4018 * packet or packet with TSO requested.
4020 * The routines are responsible for storing processed mbuf
4021 * into elts ring buffer and update elts_head if inlining
4022 * offload is requested. Otherwise the copying mbufs to elts
4023 * can be postponed and completed at the end of burst routine.
4026 * Pointer to TX queue structure.
4028 * Packets to transmit.
4030 * Number of packets in array.
4032 * Pointer to burst routine local context.
4034 * Configured Tx offloads mask. It is fully defined at
4035 * compile time and may be used for optimization.
4038 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4039 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4040 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4041 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4042 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4043 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4045 * Local context variables updated.
4048 * The routine sends packets with MLX5_OPCODE_EMPW
4049 * without inlining, this is dedicated optimized branch.
4050 * No VLAN insertion is supported.
4052 static __rte_always_inline enum mlx5_txcmp_code
4053 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4054 struct rte_mbuf **__rte_restrict pkts,
4055 unsigned int pkts_n,
4056 struct mlx5_txq_local *__rte_restrict loc,
4060 * Subroutine is the part of mlx5_tx_burst_single()
4061 * and sends single-segment packet with eMPW opcode
4062 * without data inlining.
4064 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4065 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4066 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4067 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4068 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4069 pkts += loc->pkts_sent + 1;
4070 pkts_n -= loc->pkts_sent;
4072 struct mlx5_wqe_dseg *__rte_restrict dseg;
4073 struct mlx5_wqe_eseg *__rte_restrict eseg;
4074 enum mlx5_txcmp_code ret;
4075 unsigned int part, loop;
4076 unsigned int slen = 0;
4079 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4080 if (MLX5_TXOFF_CONFIG(TXPP)) {
4081 enum mlx5_txcmp_code wret;
4083 /* Generate WAIT for scheduling if requested. */
4084 wret = mlx5_tx_schedule_send(txq, loc, olx);
4085 if (wret == MLX5_TXCMP_CODE_EXIT)
4086 return MLX5_TXCMP_CODE_EXIT;
4087 if (wret == MLX5_TXCMP_CODE_ERROR)
4088 return MLX5_TXCMP_CODE_ERROR;
4090 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4091 MLX5_MPW_MAX_PACKETS :
4092 MLX5_EMPW_MAX_PACKETS);
4093 if (unlikely(loc->elts_free < part)) {
4094 /* We have no enough elts to save all mbufs. */
4095 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4096 return MLX5_TXCMP_CODE_EXIT;
4097 /* But we still able to send at least minimal eMPW. */
4098 part = loc->elts_free;
4100 /* Check whether we have enough WQEs */
4101 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4102 if (unlikely(loc->wqe_free <
4103 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4104 return MLX5_TXCMP_CODE_EXIT;
4105 part = (loc->wqe_free * 4) - 2;
4107 if (likely(part > 1))
4108 rte_prefetch0(*pkts);
4109 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4111 * Build eMPW title WQEBB:
4112 * - Control Segment, eMPW opcode
4113 * - Ethernet Segment, no inline
4115 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4116 MLX5_OPCODE_ENHANCED_MPSW, olx);
4117 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4118 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4119 eseg = &loc->wqe_last->eseg;
4120 dseg = &loc->wqe_last->dseg[0];
4122 /* Store the packet length for legacy MPW. */
4123 if (MLX5_TXOFF_CONFIG(MPW))
4124 eseg->mss = rte_cpu_to_be_16
4125 (rte_pktmbuf_data_len(loc->mbuf));
4127 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4128 #ifdef MLX5_PMD_SOFT_COUNTERS
4129 /* Update sent data bytes counter. */
4134 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4136 if (unlikely(--loop == 0))
4138 loc->mbuf = *pkts++;
4139 if (likely(loop > 1))
4140 rte_prefetch0(*pkts);
4141 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4143 * Unroll the completion code to avoid
4144 * returning variable value - it results in
4145 * unoptimized sequent checking in caller.
4147 if (ret == MLX5_TXCMP_CODE_MULTI) {
4149 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4150 if (unlikely(!loc->elts_free ||
4152 return MLX5_TXCMP_CODE_EXIT;
4153 return MLX5_TXCMP_CODE_MULTI;
4155 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4156 if (ret == MLX5_TXCMP_CODE_TSO) {
4158 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4159 if (unlikely(!loc->elts_free ||
4161 return MLX5_TXCMP_CODE_EXIT;
4162 return MLX5_TXCMP_CODE_TSO;
4164 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4166 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4167 if (unlikely(!loc->elts_free ||
4169 return MLX5_TXCMP_CODE_EXIT;
4170 return MLX5_TXCMP_CODE_SINGLE;
4172 if (ret != MLX5_TXCMP_CODE_EMPW) {
4175 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4176 return MLX5_TXCMP_CODE_ERROR;
4179 * Check whether packet parameters coincide
4180 * within assumed eMPW batch:
4181 * - check sum settings
4183 * - software parser settings
4184 * - packets length (legacy MPW only)
4185 * - scheduling is not required
4187 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4190 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4191 if (unlikely(!loc->elts_free ||
4193 return MLX5_TXCMP_CODE_EXIT;
4197 /* Packet attributes match, continue the same eMPW. */
4199 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4200 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4202 /* eMPW is built successfully, update loop parameters. */
4204 MLX5_ASSERT(pkts_n >= part);
4205 #ifdef MLX5_PMD_SOFT_COUNTERS
4206 /* Update sent data bytes counter. */
4207 txq->stats.obytes += slen;
4209 loc->elts_free -= part;
4210 loc->pkts_sent += part;
4211 txq->wqe_ci += (2 + part + 3) / 4;
4212 loc->wqe_free -= (2 + part + 3) / 4;
4214 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4215 return MLX5_TXCMP_CODE_EXIT;
4216 loc->mbuf = *pkts++;
4217 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4218 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4220 /* Continue sending eMPW batches. */
4226 * The routine sends packets with MLX5_OPCODE_EMPW
4227 * with inlining, optionally supports VLAN insertion.
4229 static __rte_always_inline enum mlx5_txcmp_code
4230 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4231 struct rte_mbuf **__rte_restrict pkts,
4232 unsigned int pkts_n,
4233 struct mlx5_txq_local *__rte_restrict loc,
4237 * Subroutine is the part of mlx5_tx_burst_single()
4238 * and sends single-segment packet with eMPW opcode
4239 * with data inlining.
4241 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4242 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4243 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4244 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4245 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4246 pkts += loc->pkts_sent + 1;
4247 pkts_n -= loc->pkts_sent;
4249 struct mlx5_wqe_dseg *__rte_restrict dseg;
4250 struct mlx5_wqe *__rte_restrict wqem;
4251 enum mlx5_txcmp_code ret;
4252 unsigned int room, part, nlim;
4253 unsigned int slen = 0;
4255 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4256 if (MLX5_TXOFF_CONFIG(TXPP)) {
4257 enum mlx5_txcmp_code wret;
4259 /* Generate WAIT for scheduling if requested. */
4260 wret = mlx5_tx_schedule_send(txq, loc, olx);
4261 if (wret == MLX5_TXCMP_CODE_EXIT)
4262 return MLX5_TXCMP_CODE_EXIT;
4263 if (wret == MLX5_TXCMP_CODE_ERROR)
4264 return MLX5_TXCMP_CODE_ERROR;
4267 * Limits the amount of packets in one WQE
4268 * to improve CQE latency generation.
4270 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4271 MLX5_MPW_INLINE_MAX_PACKETS :
4272 MLX5_EMPW_MAX_PACKETS);
4273 /* Check whether we have minimal amount WQEs */
4274 if (unlikely(loc->wqe_free <
4275 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4276 return MLX5_TXCMP_CODE_EXIT;
4277 if (likely(pkts_n > 1))
4278 rte_prefetch0(*pkts);
4279 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4281 * Build eMPW title WQEBB:
4282 * - Control Segment, eMPW opcode, zero DS
4283 * - Ethernet Segment, no inline
4285 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4286 MLX5_OPCODE_ENHANCED_MPSW, olx);
4287 mlx5_tx_eseg_none(txq, loc, wqem,
4288 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4289 dseg = &wqem->dseg[0];
4290 /* Store the packet length for legacy MPW. */
4291 if (MLX5_TXOFF_CONFIG(MPW))
4292 wqem->eseg.mss = rte_cpu_to_be_16
4293 (rte_pktmbuf_data_len(loc->mbuf));
4294 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4295 loc->wqe_free) * MLX5_WQE_SIZE -
4296 MLX5_WQE_CSEG_SIZE -
4298 /* Limit the room for legacy MPW sessions for performance. */
4299 if (MLX5_TXOFF_CONFIG(MPW))
4300 room = RTE_MIN(room,
4301 RTE_MAX(txq->inlen_empw +
4302 sizeof(dseg->bcount) +
4303 (MLX5_TXOFF_CONFIG(VLAN) ?
4304 sizeof(struct rte_vlan_hdr) : 0),
4305 MLX5_MPW_INLINE_MAX_PACKETS *
4306 MLX5_WQE_DSEG_SIZE));
4307 /* Build WQE till we have space, packets and resources. */
4310 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4311 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4314 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4315 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4316 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4318 * Some Tx offloads may cause an error if
4319 * packet is not long enough, check against
4320 * assumed minimal length.
4322 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4324 if (unlikely(!part))
4325 return MLX5_TXCMP_CODE_ERROR;
4327 * We have some successfully built
4328 * packet Data Segments to send.
4330 mlx5_tx_idone_empw(txq, loc, part,
4332 return MLX5_TXCMP_CODE_ERROR;
4334 /* Inline or not inline - that's the Question. */
4335 if (dlen > txq->inlen_empw ||
4336 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4338 if (MLX5_TXOFF_CONFIG(MPW)) {
4339 if (dlen > txq->inlen_send)
4343 /* Open new inline MPW session. */
4344 tlen += sizeof(dseg->bcount);
4345 dseg->bcount = RTE_BE32(0);
4347 (dseg, sizeof(dseg->bcount));
4350 * No pointer and inline descriptor
4351 * intermix for legacy MPW sessions.
4353 if (wqem->dseg[0].bcount)
4357 tlen = sizeof(dseg->bcount) + dlen;
4359 /* Inline entire packet, optional VLAN insertion. */
4360 if (MLX5_TXOFF_CONFIG(VLAN) &&
4361 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4363 * The packet length must be checked in
4364 * mlx5_tx_able_to_empw() and packet
4365 * fits into inline length guaranteed.
4368 sizeof(struct rte_vlan_hdr)) <=
4370 tlen += sizeof(struct rte_vlan_hdr);
4373 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4375 #ifdef MLX5_PMD_SOFT_COUNTERS
4376 /* Update sent data bytes counter. */
4377 slen += sizeof(struct rte_vlan_hdr);
4382 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4385 if (!MLX5_TXOFF_CONFIG(MPW))
4386 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4387 MLX5_ASSERT(room >= tlen);
4390 * Packet data are completely inlined,
4391 * free the packet immediately.
4393 rte_pktmbuf_free_seg(loc->mbuf);
4397 * No pointer and inline descriptor
4398 * intermix for legacy MPW sessions.
4400 if (MLX5_TXOFF_CONFIG(MPW) &&
4402 wqem->dseg[0].bcount == RTE_BE32(0))
4405 * Not inlinable VLAN packets are
4406 * proceeded outside of this routine.
4408 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4409 if (MLX5_TXOFF_CONFIG(VLAN))
4410 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4412 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4413 /* We have to store mbuf in elts.*/
4414 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4415 room -= MLX5_WQE_DSEG_SIZE;
4416 /* Ring buffer wraparound is checked at the loop end.*/
4419 #ifdef MLX5_PMD_SOFT_COUNTERS
4420 /* Update sent data bytes counter. */
4426 if (unlikely(!pkts_n || !loc->elts_free)) {
4428 * We have no resources/packets to
4429 * continue build descriptors.
4432 mlx5_tx_idone_empw(txq, loc, part,
4434 return MLX5_TXCMP_CODE_EXIT;
4436 loc->mbuf = *pkts++;
4437 if (likely(pkts_n > 1))
4438 rte_prefetch0(*pkts);
4439 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4441 * Unroll the completion code to avoid
4442 * returning variable value - it results in
4443 * unoptimized sequent checking in caller.
4445 if (ret == MLX5_TXCMP_CODE_MULTI) {
4447 mlx5_tx_idone_empw(txq, loc, part,
4449 if (unlikely(!loc->elts_free ||
4451 return MLX5_TXCMP_CODE_EXIT;
4452 return MLX5_TXCMP_CODE_MULTI;
4454 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4455 if (ret == MLX5_TXCMP_CODE_TSO) {
4457 mlx5_tx_idone_empw(txq, loc, part,
4459 if (unlikely(!loc->elts_free ||
4461 return MLX5_TXCMP_CODE_EXIT;
4462 return MLX5_TXCMP_CODE_TSO;
4464 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4466 mlx5_tx_idone_empw(txq, loc, part,
4468 if (unlikely(!loc->elts_free ||
4470 return MLX5_TXCMP_CODE_EXIT;
4471 return MLX5_TXCMP_CODE_SINGLE;
4473 if (ret != MLX5_TXCMP_CODE_EMPW) {
4476 mlx5_tx_idone_empw(txq, loc, part,
4478 return MLX5_TXCMP_CODE_ERROR;
4480 /* Check if we have minimal room left. */
4482 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4485 * Check whether packet parameters coincide
4486 * within assumed eMPW batch:
4487 * - check sum settings
4489 * - software parser settings
4490 * - packets length (legacy MPW only)
4491 * - scheduling is not required
4493 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4496 /* Packet attributes match, continue the same eMPW. */
4497 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4498 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4501 * We get here to close an existing eMPW
4502 * session and start the new one.
4504 MLX5_ASSERT(pkts_n);
4506 if (unlikely(!part))
4507 return MLX5_TXCMP_CODE_EXIT;
4508 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4509 if (unlikely(!loc->elts_free ||
4511 return MLX5_TXCMP_CODE_EXIT;
4512 /* Continue the loop with new eMPW session. */
4518 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4519 * Data inlining and VLAN insertion are supported.
4521 static __rte_always_inline enum mlx5_txcmp_code
4522 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4523 struct rte_mbuf **__rte_restrict pkts,
4524 unsigned int pkts_n,
4525 struct mlx5_txq_local *__rte_restrict loc,
4529 * Subroutine is the part of mlx5_tx_burst_single()
4530 * and sends single-segment packet with SEND opcode.
4532 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4533 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4534 pkts += loc->pkts_sent + 1;
4535 pkts_n -= loc->pkts_sent;
4537 struct mlx5_wqe *__rte_restrict wqe;
4538 enum mlx5_txcmp_code ret;
4540 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4541 if (MLX5_TXOFF_CONFIG(TXPP)) {
4542 enum mlx5_txcmp_code wret;
4544 /* Generate WAIT for scheduling if requested. */
4545 wret = mlx5_tx_schedule_send(txq, loc, olx);
4546 if (wret == MLX5_TXCMP_CODE_EXIT)
4547 return MLX5_TXCMP_CODE_EXIT;
4548 if (wret == MLX5_TXCMP_CODE_ERROR)
4549 return MLX5_TXCMP_CODE_ERROR;
4551 if (MLX5_TXOFF_CONFIG(INLINE)) {
4552 unsigned int inlen, vlan = 0;
4554 inlen = rte_pktmbuf_data_len(loc->mbuf);
4555 if (MLX5_TXOFF_CONFIG(VLAN) &&
4556 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4557 vlan = sizeof(struct rte_vlan_hdr);
4559 static_assert((sizeof(struct rte_vlan_hdr) +
4560 sizeof(struct rte_ether_hdr)) ==
4561 MLX5_ESEG_MIN_INLINE_SIZE,
4562 "invalid min inline data size");
4565 * If inlining is enabled at configuration time
4566 * the limit must be not less than minimal size.
4567 * Otherwise we would do extra check for data
4568 * size to avoid crashes due to length overflow.
4570 MLX5_ASSERT(txq->inlen_send >=
4571 MLX5_ESEG_MIN_INLINE_SIZE);
4572 if (inlen <= txq->inlen_send) {
4573 unsigned int seg_n, wqe_n;
4575 rte_prefetch0(rte_pktmbuf_mtod
4576 (loc->mbuf, uint8_t *));
4577 /* Check against minimal length. */
4578 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4579 return MLX5_TXCMP_CODE_ERROR;
4580 if (loc->mbuf->ol_flags &
4581 PKT_TX_DYNF_NOINLINE) {
4583 * The hint flag not to inline packet
4584 * data is set. Check whether we can
4587 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4589 (MLX5_TXOFF_CONFIG(MPW) &&
4591 if (inlen <= txq->inlen_send)
4594 * The hardware requires the
4595 * minimal inline data header.
4597 goto single_min_inline;
4599 if (MLX5_TXOFF_CONFIG(VLAN) &&
4600 vlan && !txq->vlan_en) {
4602 * We must insert VLAN tag
4603 * by software means.
4605 goto single_part_inline;
4607 goto single_no_inline;
4611 * Completely inlined packet data WQE:
4612 * - Control Segment, SEND opcode
4613 * - Ethernet Segment, no VLAN insertion
4614 * - Data inlined, VLAN optionally inserted
4615 * - Alignment to MLX5_WSEG_SIZE
4616 * Have to estimate amount of WQEBBs
4618 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4619 MLX5_ESEG_MIN_INLINE_SIZE +
4620 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4621 /* Check if there are enough WQEBBs. */
4622 wqe_n = (seg_n + 3) / 4;
4623 if (wqe_n > loc->wqe_free)
4624 return MLX5_TXCMP_CODE_EXIT;
4625 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4626 loc->wqe_last = wqe;
4627 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4628 MLX5_OPCODE_SEND, olx);
4629 mlx5_tx_eseg_data(txq, loc, wqe,
4630 vlan, inlen, 0, olx);
4631 txq->wqe_ci += wqe_n;
4632 loc->wqe_free -= wqe_n;
4634 * Packet data are completely inlined,
4635 * free the packet immediately.
4637 rte_pktmbuf_free_seg(loc->mbuf);
4638 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4639 MLX5_TXOFF_CONFIG(MPW)) &&
4642 * If minimal inlining is requested the eMPW
4643 * feature should be disabled due to data is
4644 * inlined into Ethernet Segment, which can
4645 * not contain inlined data for eMPW due to
4646 * segment shared for all packets.
4648 struct mlx5_wqe_dseg *__rte_restrict dseg;
4653 * The inline-mode settings require
4654 * to inline the specified amount of
4655 * data bytes to the Ethernet Segment.
4656 * We should check the free space in
4657 * WQE ring buffer to inline partially.
4660 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4661 MLX5_ASSERT(inlen > txq->inlen_mode);
4662 MLX5_ASSERT(txq->inlen_mode >=
4663 MLX5_ESEG_MIN_INLINE_SIZE);
4665 * Check whether there are enough free WQEBBs:
4667 * - Ethernet Segment
4668 * - First Segment of inlined Ethernet data
4669 * - ... data continued ...
4670 * - Finishing Data Segment of pointer type
4672 ds = (MLX5_WQE_CSEG_SIZE +
4673 MLX5_WQE_ESEG_SIZE +
4674 MLX5_WQE_DSEG_SIZE +
4676 MLX5_ESEG_MIN_INLINE_SIZE +
4677 MLX5_WQE_DSEG_SIZE +
4678 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4679 if (loc->wqe_free < ((ds + 3) / 4))
4680 return MLX5_TXCMP_CODE_EXIT;
4682 * Build the ordinary SEND WQE:
4684 * - Ethernet Segment, inline inlen_mode bytes
4685 * - Data Segment of pointer type
4687 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4688 loc->wqe_last = wqe;
4689 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4690 MLX5_OPCODE_SEND, olx);
4691 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4694 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4695 txq->inlen_mode - vlan;
4696 inlen -= txq->inlen_mode;
4697 mlx5_tx_dseg_ptr(txq, loc, dseg,
4700 * WQE is built, update the loop parameters
4701 * and got to the next packet.
4703 txq->wqe_ci += (ds + 3) / 4;
4704 loc->wqe_free -= (ds + 3) / 4;
4705 /* We have to store mbuf in elts.*/
4706 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4707 txq->elts[txq->elts_head++ & txq->elts_m] =
4715 * Partially inlined packet data WQE, we have
4716 * some space in title WQEBB, we can fill it
4717 * with some packet data. It takes one WQEBB,
4718 * it is available, no extra space check:
4719 * - Control Segment, SEND opcode
4720 * - Ethernet Segment, no VLAN insertion
4721 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4722 * - Data Segment, pointer type
4724 * We also get here if VLAN insertion is not
4725 * supported by HW, the inline is enabled.
4728 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4729 loc->wqe_last = wqe;
4730 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4731 MLX5_OPCODE_SEND, olx);
4732 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4733 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4734 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4736 * The length check is performed above, by
4737 * comparing with txq->inlen_send. We should
4738 * not get overflow here.
4740 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4741 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4742 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4746 /* We have to store mbuf in elts.*/
4747 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4748 txq->elts[txq->elts_head++ & txq->elts_m] =
4752 #ifdef MLX5_PMD_SOFT_COUNTERS
4753 /* Update sent data bytes counter. */
4754 txq->stats.obytes += vlan +
4755 rte_pktmbuf_data_len(loc->mbuf);
4759 * No inline at all, it means the CPU cycles saving
4760 * is prioritized at configuration, we should not
4761 * copy any packet data to WQE.
4763 * SEND WQE, one WQEBB:
4764 * - Control Segment, SEND opcode
4765 * - Ethernet Segment, optional VLAN, no inline
4766 * - Data Segment, pointer type
4769 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4770 loc->wqe_last = wqe;
4771 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4772 MLX5_OPCODE_SEND, olx);
4773 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4775 (txq, loc, &wqe->dseg[0],
4776 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4777 rte_pktmbuf_data_len(loc->mbuf), olx);
4781 * We should not store mbuf pointer in elts
4782 * if no inlining is configured, this is done
4783 * by calling routine in a batch copy.
4785 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4787 #ifdef MLX5_PMD_SOFT_COUNTERS
4788 /* Update sent data bytes counter. */
4789 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4790 if (MLX5_TXOFF_CONFIG(VLAN) &&
4791 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4792 txq->stats.obytes +=
4793 sizeof(struct rte_vlan_hdr);
4798 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4799 return MLX5_TXCMP_CODE_EXIT;
4800 loc->mbuf = *pkts++;
4802 rte_prefetch0(*pkts);
4803 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4804 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4810 static __rte_always_inline enum mlx5_txcmp_code
4811 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4812 struct rte_mbuf **__rte_restrict pkts,
4813 unsigned int pkts_n,
4814 struct mlx5_txq_local *__rte_restrict loc,
4817 enum mlx5_txcmp_code ret;
4819 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4820 if (ret == MLX5_TXCMP_CODE_SINGLE)
4822 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4824 /* Optimize for inline/no inline eMPW send. */
4825 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4826 mlx5_tx_burst_empw_inline
4827 (txq, pkts, pkts_n, loc, olx) :
4828 mlx5_tx_burst_empw_simple
4829 (txq, pkts, pkts_n, loc, olx);
4830 if (ret != MLX5_TXCMP_CODE_SINGLE)
4832 /* The resources to send one packet should remain. */
4833 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4835 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4836 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4837 if (ret != MLX5_TXCMP_CODE_EMPW)
4839 /* The resources to send one packet should remain. */
4840 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4845 * DPDK Tx callback template. This is configured template
4846 * used to generate routines optimized for specified offload setup.
4847 * One of this generated functions is chosen at SQ configuration
4851 * Generic pointer to TX queue structure.
4853 * Packets to transmit.
4855 * Number of packets in array.
4857 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4858 * values. Should be static to take compile time static configuration
4862 * Number of packets successfully transmitted (<= pkts_n).
4864 static __rte_always_inline uint16_t
4865 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4866 struct rte_mbuf **__rte_restrict pkts,
4870 struct mlx5_txq_local loc;
4871 enum mlx5_txcmp_code ret;
4874 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4875 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4876 if (unlikely(!pkts_n))
4880 loc.wqe_last = NULL;
4883 loc.pkts_loop = loc.pkts_sent;
4885 * Check if there are some CQEs, if any:
4886 * - process an encountered errors
4887 * - process the completed WQEs
4888 * - free related mbufs
4889 * - doorbell the NIC about processed CQEs
4891 rte_prefetch0(*(pkts + loc.pkts_sent));
4892 mlx5_tx_handle_completion(txq, olx);
4894 * Calculate the number of available resources - elts and WQEs.
4895 * There are two possible different scenarios:
4896 * - no data inlining into WQEs, one WQEBB may contains up to
4897 * four packets, in this case elts become scarce resource
4898 * - data inlining into WQEs, one packet may require multiple
4899 * WQEBBs, the WQEs become the limiting factor.
4901 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4902 loc.elts_free = txq->elts_s -
4903 (uint16_t)(txq->elts_head - txq->elts_tail);
4904 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4905 loc.wqe_free = txq->wqe_s -
4906 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4907 if (unlikely(!loc.elts_free || !loc.wqe_free))
4911 * Fetch the packet from array. Usually this is
4912 * the first packet in series of multi/single
4915 loc.mbuf = *(pkts + loc.pkts_sent);
4916 /* Dedicated branch for multi-segment packets. */
4917 if (MLX5_TXOFF_CONFIG(MULTI) &&
4918 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4920 * Multi-segment packet encountered.
4921 * Hardware is able to process it only
4922 * with SEND/TSO opcodes, one packet
4923 * per WQE, do it in dedicated routine.
4926 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4927 part = loc.pkts_sent - loc.pkts_copy;
4928 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4930 * There are some single-segment mbufs not
4931 * stored in elts. The mbufs must be in the
4932 * same order as WQEs, so we must copy the
4933 * mbufs to elts here, before the coming
4934 * multi-segment packet mbufs is appended.
4936 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4938 loc.pkts_copy = loc.pkts_sent;
4940 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4941 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4942 if (!MLX5_TXOFF_CONFIG(INLINE))
4943 loc.pkts_copy = loc.pkts_sent;
4945 * These returned code checks are supposed
4946 * to be optimized out due to routine inlining.
4948 if (ret == MLX5_TXCMP_CODE_EXIT) {
4950 * The routine returns this code when
4951 * all packets are sent or there is no
4952 * enough resources to complete request.
4956 if (ret == MLX5_TXCMP_CODE_ERROR) {
4958 * The routine returns this code when
4959 * some error in the incoming packets
4962 txq->stats.oerrors++;
4965 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4967 * The single-segment packet was encountered
4968 * in the array, try to send it with the
4969 * best optimized way, possible engaging eMPW.
4971 goto enter_send_single;
4973 if (MLX5_TXOFF_CONFIG(TSO) &&
4974 ret == MLX5_TXCMP_CODE_TSO) {
4976 * The single-segment TSO packet was
4977 * encountered in the array.
4979 goto enter_send_tso;
4981 /* We must not get here. Something is going wrong. */
4983 txq->stats.oerrors++;
4986 /* Dedicated branch for single-segment TSO packets. */
4987 if (MLX5_TXOFF_CONFIG(TSO) &&
4988 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4990 * TSO might require special way for inlining
4991 * (dedicated parameters) and is sent with
4992 * MLX5_OPCODE_TSO opcode only, provide this
4993 * in dedicated branch.
4996 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4997 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4998 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
5000 * These returned code checks are supposed
5001 * to be optimized out due to routine inlining.
5003 if (ret == MLX5_TXCMP_CODE_EXIT)
5005 if (ret == MLX5_TXCMP_CODE_ERROR) {
5006 txq->stats.oerrors++;
5009 if (ret == MLX5_TXCMP_CODE_SINGLE)
5010 goto enter_send_single;
5011 if (MLX5_TXOFF_CONFIG(MULTI) &&
5012 ret == MLX5_TXCMP_CODE_MULTI) {
5014 * The multi-segment packet was
5015 * encountered in the array.
5017 goto enter_send_multi;
5019 /* We must not get here. Something is going wrong. */
5021 txq->stats.oerrors++;
5025 * The dedicated branch for the single-segment packets
5026 * without TSO. Often these ones can be sent using
5027 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5028 * The routine builds the WQEs till it encounters
5029 * the TSO or multi-segment packet (in case if these
5030 * offloads are requested at SQ configuration time).
5033 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5034 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5036 * These returned code checks are supposed
5037 * to be optimized out due to routine inlining.
5039 if (ret == MLX5_TXCMP_CODE_EXIT)
5041 if (ret == MLX5_TXCMP_CODE_ERROR) {
5042 txq->stats.oerrors++;
5045 if (MLX5_TXOFF_CONFIG(MULTI) &&
5046 ret == MLX5_TXCMP_CODE_MULTI) {
5048 * The multi-segment packet was
5049 * encountered in the array.
5051 goto enter_send_multi;
5053 if (MLX5_TXOFF_CONFIG(TSO) &&
5054 ret == MLX5_TXCMP_CODE_TSO) {
5056 * The single-segment TSO packet was
5057 * encountered in the array.
5059 goto enter_send_tso;
5061 /* We must not get here. Something is going wrong. */
5063 txq->stats.oerrors++;
5067 * Main Tx loop is completed, do the rest:
5068 * - set completion request if thresholds are reached
5069 * - doorbell the hardware
5070 * - copy the rest of mbufs to elts (if any)
5072 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5073 loc.pkts_sent >= loc.pkts_copy);
5074 /* Take a shortcut if nothing is sent. */
5075 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5077 /* Request CQE generation if limits are reached. */
5078 mlx5_tx_request_completion(txq, &loc, olx);
5080 * Ring QP doorbell immediately after WQE building completion
5081 * to improve latencies. The pure software related data treatment
5082 * can be completed after doorbell. Tx CQEs for this SQ are
5083 * processed in this thread only by the polling.
5085 * The rdma core library can map doorbell register in two ways,
5086 * depending on the environment variable "MLX5_SHUT_UP_BF":
5088 * - as regular cached memory, the variable is either missing or
5089 * set to zero. This type of mapping may cause the significant
5090 * doorbell register writing latency and requires explicit
5091 * memory write barrier to mitigate this issue and prevent
5094 * - as non-cached memory, the variable is present and set to
5095 * not "0" value. This type of mapping may cause performance
5096 * impact under heavy loading conditions but the explicit write
5097 * memory barrier is not required and it may improve core
5100 * - the legacy behaviour (prior 19.08 release) was to use some
5101 * heuristics to decide whether write memory barrier should
5102 * be performed. This behavior is supported with specifying
5103 * tx_db_nc=2, write barrier is skipped if application
5104 * provides the full recommended burst of packets, it
5105 * supposes the next packets are coming and the write barrier
5106 * will be issued on the next burst (after descriptor writing,
5109 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5110 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5111 /* Not all of the mbufs may be stored into elts yet. */
5112 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5113 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5115 * There are some single-segment mbufs not stored in elts.
5116 * It can be only if the last packet was single-segment.
5117 * The copying is gathered into one place due to it is
5118 * a good opportunity to optimize that with SIMD.
5119 * Unfortunately if inlining is enabled the gaps in
5120 * pointer array may happen due to early freeing of the
5123 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5124 loc.pkts_copy = loc.pkts_sent;
5126 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5127 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5128 if (pkts_n > loc.pkts_sent) {
5130 * If burst size is large there might be no enough CQE
5131 * fetched from completion queue and no enough resources
5132 * freed to send all the packets.
5137 #ifdef MLX5_PMD_SOFT_COUNTERS
5138 /* Increment sent packets counter. */
5139 txq->stats.opackets += loc.pkts_sent;
5141 return loc.pkts_sent;
5144 /* Generate routines with Enhanced Multi-Packet Write support. */
5145 MLX5_TXOFF_DECL(full_empw,
5146 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5148 MLX5_TXOFF_DECL(none_empw,
5149 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5151 MLX5_TXOFF_DECL(md_empw,
5152 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5154 MLX5_TXOFF_DECL(mt_empw,
5155 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5156 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5158 MLX5_TXOFF_DECL(mtsc_empw,
5159 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5160 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5161 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5163 MLX5_TXOFF_DECL(mti_empw,
5164 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5165 MLX5_TXOFF_CONFIG_INLINE |
5166 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5168 MLX5_TXOFF_DECL(mtv_empw,
5169 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5170 MLX5_TXOFF_CONFIG_VLAN |
5171 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5173 MLX5_TXOFF_DECL(mtiv_empw,
5174 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5175 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5176 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5178 MLX5_TXOFF_DECL(sc_empw,
5179 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5180 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5182 MLX5_TXOFF_DECL(sci_empw,
5183 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5184 MLX5_TXOFF_CONFIG_INLINE |
5185 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5187 MLX5_TXOFF_DECL(scv_empw,
5188 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5189 MLX5_TXOFF_CONFIG_VLAN |
5190 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5192 MLX5_TXOFF_DECL(sciv_empw,
5193 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5194 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5195 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5197 MLX5_TXOFF_DECL(i_empw,
5198 MLX5_TXOFF_CONFIG_INLINE |
5199 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5201 MLX5_TXOFF_DECL(v_empw,
5202 MLX5_TXOFF_CONFIG_VLAN |
5203 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5205 MLX5_TXOFF_DECL(iv_empw,
5206 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5207 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5209 /* Generate routines without Enhanced Multi-Packet Write support. */
5210 MLX5_TXOFF_DECL(full,
5211 MLX5_TXOFF_CONFIG_FULL)
5213 MLX5_TXOFF_DECL(none,
5214 MLX5_TXOFF_CONFIG_NONE)
5217 MLX5_TXOFF_CONFIG_METADATA)
5220 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5221 MLX5_TXOFF_CONFIG_METADATA)
5223 MLX5_TXOFF_DECL(mtsc,
5224 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5225 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5226 MLX5_TXOFF_CONFIG_METADATA)
5228 MLX5_TXOFF_DECL(mti,
5229 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5230 MLX5_TXOFF_CONFIG_INLINE |
5231 MLX5_TXOFF_CONFIG_METADATA)
5234 MLX5_TXOFF_DECL(mtv,
5235 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5236 MLX5_TXOFF_CONFIG_VLAN |
5237 MLX5_TXOFF_CONFIG_METADATA)
5240 MLX5_TXOFF_DECL(mtiv,
5241 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5242 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5243 MLX5_TXOFF_CONFIG_METADATA)
5246 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5247 MLX5_TXOFF_CONFIG_METADATA)
5249 MLX5_TXOFF_DECL(sci,
5250 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_INLINE |
5252 MLX5_TXOFF_CONFIG_METADATA)
5255 MLX5_TXOFF_DECL(scv,
5256 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5257 MLX5_TXOFF_CONFIG_VLAN |
5258 MLX5_TXOFF_CONFIG_METADATA)
5261 MLX5_TXOFF_DECL(sciv,
5262 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5263 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5264 MLX5_TXOFF_CONFIG_METADATA)
5267 MLX5_TXOFF_CONFIG_INLINE |
5268 MLX5_TXOFF_CONFIG_METADATA)
5271 MLX5_TXOFF_CONFIG_VLAN |
5272 MLX5_TXOFF_CONFIG_METADATA)
5275 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5276 MLX5_TXOFF_CONFIG_METADATA)
5278 /* Generate routines with timestamp scheduling. */
5279 MLX5_TXOFF_DECL(full_ts_nompw,
5280 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5282 MLX5_TXOFF_DECL(full_ts_nompwi,
5283 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5284 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5285 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5286 MLX5_TXOFF_CONFIG_TXPP)
5288 MLX5_TXOFF_DECL(full_ts,
5289 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5290 MLX5_TXOFF_CONFIG_EMPW)
5292 MLX5_TXOFF_DECL(full_ts_noi,
5293 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5294 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5295 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5296 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5298 MLX5_TXOFF_DECL(none_ts,
5299 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5300 MLX5_TXOFF_CONFIG_EMPW)
5302 MLX5_TXOFF_DECL(mdi_ts,
5303 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5304 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5306 MLX5_TXOFF_DECL(mti_ts,
5307 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5308 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5309 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5311 MLX5_TXOFF_DECL(mtiv_ts,
5312 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5313 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5314 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5315 MLX5_TXOFF_CONFIG_EMPW)
5318 * Generate routines with Legacy Multi-Packet Write support.
5319 * This mode is supported by ConnectX-4 Lx only and imposes
5320 * offload limitations, not supported:
5321 * - ACL/Flows (metadata are becoming meaningless)
5322 * - WQE Inline headers
5323 * - SRIOV (E-Switch offloads)
5325 * - tunnel encapsulation/decapsulation
5328 MLX5_TXOFF_DECL(none_mpw,
5329 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5330 MLX5_TXOFF_CONFIG_MPW)
5332 MLX5_TXOFF_DECL(mci_mpw,
5333 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5334 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5335 MLX5_TXOFF_CONFIG_MPW)
5337 MLX5_TXOFF_DECL(mc_mpw,
5338 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5339 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5341 MLX5_TXOFF_DECL(i_mpw,
5342 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5343 MLX5_TXOFF_CONFIG_MPW)
5346 * Array of declared and compiled Tx burst function and corresponding
5347 * supported offloads set. The array is used to select the Tx burst
5348 * function for specified offloads set at Tx queue configuration time.
5351 eth_tx_burst_t func;
5354 MLX5_TXOFF_INFO(full_empw,
5355 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5356 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5357 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5358 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5360 MLX5_TXOFF_INFO(none_empw,
5361 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5363 MLX5_TXOFF_INFO(md_empw,
5364 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5366 MLX5_TXOFF_INFO(mt_empw,
5367 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5368 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5370 MLX5_TXOFF_INFO(mtsc_empw,
5371 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5372 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5373 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5375 MLX5_TXOFF_INFO(mti_empw,
5376 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5377 MLX5_TXOFF_CONFIG_INLINE |
5378 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5380 MLX5_TXOFF_INFO(mtv_empw,
5381 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5382 MLX5_TXOFF_CONFIG_VLAN |
5383 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5385 MLX5_TXOFF_INFO(mtiv_empw,
5386 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5387 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5388 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5390 MLX5_TXOFF_INFO(sc_empw,
5391 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5392 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5394 MLX5_TXOFF_INFO(sci_empw,
5395 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5396 MLX5_TXOFF_CONFIG_INLINE |
5397 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5399 MLX5_TXOFF_INFO(scv_empw,
5400 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5401 MLX5_TXOFF_CONFIG_VLAN |
5402 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5404 MLX5_TXOFF_INFO(sciv_empw,
5405 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5406 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5407 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5409 MLX5_TXOFF_INFO(i_empw,
5410 MLX5_TXOFF_CONFIG_INLINE |
5411 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5413 MLX5_TXOFF_INFO(v_empw,
5414 MLX5_TXOFF_CONFIG_VLAN |
5415 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5417 MLX5_TXOFF_INFO(iv_empw,
5418 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5419 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5421 MLX5_TXOFF_INFO(full_ts_nompw,
5422 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5424 MLX5_TXOFF_INFO(full_ts_nompwi,
5425 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5426 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5427 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5428 MLX5_TXOFF_CONFIG_TXPP)
5430 MLX5_TXOFF_INFO(full_ts,
5431 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5432 MLX5_TXOFF_CONFIG_EMPW)
5434 MLX5_TXOFF_INFO(full_ts_noi,
5435 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5436 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5437 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5438 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5440 MLX5_TXOFF_INFO(none_ts,
5441 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5442 MLX5_TXOFF_CONFIG_EMPW)
5444 MLX5_TXOFF_INFO(mdi_ts,
5445 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5446 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5448 MLX5_TXOFF_INFO(mti_ts,
5449 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5450 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5451 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5453 MLX5_TXOFF_INFO(mtiv_ts,
5454 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5455 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5456 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5457 MLX5_TXOFF_CONFIG_EMPW)
5459 MLX5_TXOFF_INFO(full,
5460 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5461 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5462 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5463 MLX5_TXOFF_CONFIG_METADATA)
5465 MLX5_TXOFF_INFO(none,
5466 MLX5_TXOFF_CONFIG_NONE)
5469 MLX5_TXOFF_CONFIG_METADATA)
5472 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5473 MLX5_TXOFF_CONFIG_METADATA)
5475 MLX5_TXOFF_INFO(mtsc,
5476 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5477 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5478 MLX5_TXOFF_CONFIG_METADATA)
5480 MLX5_TXOFF_INFO(mti,
5481 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5482 MLX5_TXOFF_CONFIG_INLINE |
5483 MLX5_TXOFF_CONFIG_METADATA)
5485 MLX5_TXOFF_INFO(mtv,
5486 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5487 MLX5_TXOFF_CONFIG_VLAN |
5488 MLX5_TXOFF_CONFIG_METADATA)
5490 MLX5_TXOFF_INFO(mtiv,
5491 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5492 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5493 MLX5_TXOFF_CONFIG_METADATA)
5496 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5497 MLX5_TXOFF_CONFIG_METADATA)
5499 MLX5_TXOFF_INFO(sci,
5500 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5501 MLX5_TXOFF_CONFIG_INLINE |
5502 MLX5_TXOFF_CONFIG_METADATA)
5504 MLX5_TXOFF_INFO(scv,
5505 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5506 MLX5_TXOFF_CONFIG_VLAN |
5507 MLX5_TXOFF_CONFIG_METADATA)
5509 MLX5_TXOFF_INFO(sciv,
5510 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5511 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5512 MLX5_TXOFF_CONFIG_METADATA)
5515 MLX5_TXOFF_CONFIG_INLINE |
5516 MLX5_TXOFF_CONFIG_METADATA)
5519 MLX5_TXOFF_CONFIG_VLAN |
5520 MLX5_TXOFF_CONFIG_METADATA)
5523 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5524 MLX5_TXOFF_CONFIG_METADATA)
5526 MLX5_TXOFF_INFO(none_mpw,
5527 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5528 MLX5_TXOFF_CONFIG_MPW)
5530 MLX5_TXOFF_INFO(mci_mpw,
5531 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5532 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5533 MLX5_TXOFF_CONFIG_MPW)
5535 MLX5_TXOFF_INFO(mc_mpw,
5536 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5537 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5539 MLX5_TXOFF_INFO(i_mpw,
5540 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5541 MLX5_TXOFF_CONFIG_MPW)
5545 * Configure the Tx function to use. The routine checks configured
5546 * Tx offloads for the device and selects appropriate Tx burst
5547 * routine. There are multiple Tx burst routines compiled from
5548 * the same template in the most optimal way for the dedicated
5552 * Pointer to private data structure.
5555 * Pointer to selected Tx burst function.
5558 mlx5_select_tx_function(struct rte_eth_dev *dev)
5560 struct mlx5_priv *priv = dev->data->dev_private;
5561 struct mlx5_dev_config *config = &priv->config;
5562 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5563 unsigned int diff = 0, olx = 0, i, m;
5565 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5566 MLX5_DSEG_MAX, "invalid WQE max size");
5567 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5568 "invalid WQE Control Segment size");
5569 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5570 "invalid WQE Ethernet Segment size");
5571 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5572 "invalid WQE Data Segment size");
5573 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5574 "invalid WQE size");
5576 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5577 /* We should support Multi-Segment Packets. */
5578 olx |= MLX5_TXOFF_CONFIG_MULTI;
5580 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5581 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5582 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5583 DEV_TX_OFFLOAD_IP_TNL_TSO |
5584 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5585 /* We should support TCP Send Offload. */
5586 olx |= MLX5_TXOFF_CONFIG_TSO;
5588 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5589 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5590 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5591 /* We should support Software Parser for Tunnels. */
5592 olx |= MLX5_TXOFF_CONFIG_SWP;
5594 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5595 DEV_TX_OFFLOAD_UDP_CKSUM |
5596 DEV_TX_OFFLOAD_TCP_CKSUM |
5597 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5598 /* We should support IP/TCP/UDP Checksums. */
5599 olx |= MLX5_TXOFF_CONFIG_CSUM;
5601 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5602 /* We should support VLAN insertion. */
5603 olx |= MLX5_TXOFF_CONFIG_VLAN;
5605 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5606 rte_mbuf_dynflag_lookup
5607 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5608 rte_mbuf_dynfield_lookup
5609 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5610 /* Offload configured, dynamic entities registered. */
5611 olx |= MLX5_TXOFF_CONFIG_TXPP;
5613 if (priv->txqs_n && (*priv->txqs)[0]) {
5614 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5616 if (txd->inlen_send) {
5618 * Check the data inline requirements. Data inline
5619 * is enabled on per device basis, we can check
5620 * the first Tx queue only.
5622 * If device does not support VLAN insertion in WQE
5623 * and some queues are requested to perform VLAN
5624 * insertion offload than inline must be enabled.
5626 olx |= MLX5_TXOFF_CONFIG_INLINE;
5629 if (config->mps == MLX5_MPW_ENHANCED &&
5630 config->txq_inline_min <= 0) {
5632 * The NIC supports Enhanced Multi-Packet Write
5633 * and does not require minimal inline data.
5635 olx |= MLX5_TXOFF_CONFIG_EMPW;
5637 if (rte_flow_dynf_metadata_avail()) {
5638 /* We should support Flow metadata. */
5639 olx |= MLX5_TXOFF_CONFIG_METADATA;
5641 if (config->mps == MLX5_MPW) {
5643 * The NIC supports Legacy Multi-Packet Write.
5644 * The MLX5_TXOFF_CONFIG_MPW controls the
5645 * descriptor building method in combination
5646 * with MLX5_TXOFF_CONFIG_EMPW.
5648 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5649 MLX5_TXOFF_CONFIG_SWP |
5650 MLX5_TXOFF_CONFIG_VLAN |
5651 MLX5_TXOFF_CONFIG_METADATA)))
5652 olx |= MLX5_TXOFF_CONFIG_EMPW |
5653 MLX5_TXOFF_CONFIG_MPW;
5656 * Scan the routines table to find the minimal
5657 * satisfying routine with requested offloads.
5659 m = RTE_DIM(txoff_func);
5660 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5663 tmp = txoff_func[i].olx;
5665 /* Meets requested offloads exactly.*/
5669 if ((tmp & olx) != olx) {
5670 /* Does not meet requested offloads at all. */
5673 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5674 /* Do not enable legacy MPW if not configured. */
5676 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5677 /* Do not enable eMPW if not configured. */
5679 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5680 /* Do not enable inlining if not configured. */
5682 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5683 /* Do not enable scheduling if not configured. */
5686 * Some routine meets the requirements.
5687 * Check whether it has minimal amount
5688 * of not requested offloads.
5690 tmp = __builtin_popcountl(tmp & ~olx);
5691 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5692 /* First or better match, save and continue. */
5698 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5699 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5700 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5701 /* Lighter not requested offload. */
5706 if (m >= RTE_DIM(txoff_func)) {
5707 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5708 " for requested offloads %04X",
5709 dev->data->port_id, olx);
5712 DRV_LOG(DEBUG, "port %u has selected Tx function"
5713 " supporting offloads %04X/%04X",
5714 dev->data->port_id, olx, txoff_func[m].olx);
5715 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5716 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5717 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5718 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5719 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5720 DRV_LOG(DEBUG, "\tSWP (software parser)");
5721 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5722 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5723 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5724 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5725 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5726 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5727 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5728 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5729 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5730 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5731 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5732 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5733 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5735 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5737 return txoff_func[m].func;
5741 * DPDK callback to get the TX queue information
5744 * Pointer to the device structure.
5746 * @param tx_queue_id
5747 * Tx queue identificator.
5750 * Pointer to the TX queue information structure.
5757 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5758 struct rte_eth_txq_info *qinfo)
5760 struct mlx5_priv *priv = dev->data->dev_private;
5761 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5762 struct mlx5_txq_ctrl *txq_ctrl =
5763 container_of(txq, struct mlx5_txq_ctrl, txq);
5767 qinfo->nb_desc = txq->elts_s;
5768 qinfo->conf.tx_thresh.pthresh = 0;
5769 qinfo->conf.tx_thresh.hthresh = 0;
5770 qinfo->conf.tx_thresh.wthresh = 0;
5771 qinfo->conf.tx_rs_thresh = 0;
5772 qinfo->conf.tx_free_thresh = 0;
5773 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5774 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5778 * DPDK callback to get the TX packet burst mode information
5781 * Pointer to the device structure.
5783 * @param tx_queue_id
5784 * Tx queue identificatior.
5787 * Pointer to the burts mode information.
5790 * 0 as success, -EINVAL as failure.
5794 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5795 uint16_t tx_queue_id __rte_unused,
5796 struct rte_eth_burst_mode *mode)
5798 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5799 unsigned int i, olx;
5801 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5802 if (pkt_burst == txoff_func[i].func) {
5803 olx = txoff_func[i].olx;
5804 snprintf(mode->info, sizeof(mode->info),
5805 "%s%s%s%s%s%s%s%s%s",
5806 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5807 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5808 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5809 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5811 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5813 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5815 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5817 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5819 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5821 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5823 (olx & MLX5_TXOFF_CONFIG_TXPP) ?