1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/verbs.h>
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_mempool.h>
23 #include <rte_prefetch.h>
24 #include <rte_common.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_ether.h>
27 #include <rte_cycles.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_common.h>
34 #include "mlx5_defs.h"
37 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
41 /* TX burst subroutines return codes. */
42 enum mlx5_txcmp_code {
43 MLX5_TXCMP_CODE_EXIT = 0,
44 MLX5_TXCMP_CODE_ERROR,
45 MLX5_TXCMP_CODE_SINGLE,
46 MLX5_TXCMP_CODE_MULTI,
52 * These defines are used to configure Tx burst routine option set
53 * supported at compile time. The not specified options are optimized out
54 * out due to if conditions can be explicitly calculated at compile time.
55 * The offloads with bigger runtime check (require more CPU cycles to
56 * skip) overhead should have the bigger index - this is needed to
57 * select the better matching routine function if no exact match and
58 * some offloads are not actually requested.
60 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
61 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
62 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
63 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
64 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
65 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
66 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
67 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
68 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
69 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
71 /* The most common offloads groups. */
72 #define MLX5_TXOFF_CONFIG_NONE 0
73 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
74 MLX5_TXOFF_CONFIG_TSO | \
75 MLX5_TXOFF_CONFIG_SWP | \
76 MLX5_TXOFF_CONFIG_CSUM | \
77 MLX5_TXOFF_CONFIG_INLINE | \
78 MLX5_TXOFF_CONFIG_VLAN | \
79 MLX5_TXOFF_CONFIG_METADATA)
81 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
83 #define MLX5_TXOFF_DECL(func, olx) \
84 static uint16_t mlx5_tx_burst_##func(void *txq, \
85 struct rte_mbuf **pkts, \
88 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
89 pkts, pkts_n, (olx)); \
92 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
94 static __rte_always_inline uint32_t
95 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
97 static __rte_always_inline int
98 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
99 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
101 static __rte_always_inline uint32_t
102 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
104 static __rte_always_inline void
105 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
106 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
108 static __rte_always_inline void
109 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
110 const unsigned int strd_n);
113 mlx5_queue_state_modify(struct rte_eth_dev *dev,
114 struct mlx5_mp_arg_queue_state_modify *sm);
117 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
118 volatile struct mlx5_cqe *__rte_restrict cqe,
122 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
123 volatile struct mlx5_cqe *__rte_restrict cqe,
126 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
127 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
130 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
131 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
133 uint64_t rte_net_mlx5_dynf_inline_mask;
134 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
137 * Build a table to translate Rx completion flags to packet type.
139 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
142 mlx5_set_ptype_table(void)
145 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
147 /* Last entry must not be overwritten, reserved for errored packet. */
148 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
149 (*p)[i] = RTE_PTYPE_UNKNOWN;
151 * The index to the array should have:
152 * bit[1:0] = l3_hdr_type
153 * bit[4:2] = l4_hdr_type
156 * bit[7] = outer_l3_type
159 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
161 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 RTE_PTYPE_L4_NONFRAG;
163 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_L4_NONFRAG;
166 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
181 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 /* Repeat with outer_l3_type being set. Just in case. */
189 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 RTE_PTYPE_L4_NONFRAG;
191 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_L4_NONFRAG;
193 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
195 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
199 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
203 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
209 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
211 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
215 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
216 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L4_NONFRAG;
218 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L4_NONFRAG;
221 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
222 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_NONFRAG;
225 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_NONFRAG;
228 /* Tunneled - Fragmented */
229 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_FRAG;
232 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_FRAG;
235 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_FRAG;
238 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_FRAG;
242 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_TCP;
245 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
247 RTE_PTYPE_INNER_L4_TCP;
248 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_TCP;
251 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L4_TCP;
254 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L4_TCP;
257 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_TCP;
263 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_TCP;
269 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_TCP;
272 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_TCP;
275 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_TCP;
279 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_UDP;
282 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
284 RTE_PTYPE_INNER_L4_UDP;
285 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
286 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
287 RTE_PTYPE_INNER_L4_UDP;
288 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
290 RTE_PTYPE_INNER_L4_UDP;
294 * Build a table to translate packet to checksum type of Verbs.
297 mlx5_set_cksum_table(void)
303 * The index should have:
304 * bit[0] = PKT_TX_TCP_SEG
305 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
306 * bit[4] = PKT_TX_IP_CKSUM
307 * bit[8] = PKT_TX_OUTER_IP_CKSUM
310 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
313 /* Tunneled packet. */
314 if (i & (1 << 8)) /* Outer IP. */
315 v |= MLX5_ETH_WQE_L3_CSUM;
316 if (i & (1 << 4)) /* Inner IP. */
317 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
318 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
319 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
322 if (i & (1 << 4)) /* IP. */
323 v |= MLX5_ETH_WQE_L3_CSUM;
324 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
325 v |= MLX5_ETH_WQE_L4_CSUM;
327 mlx5_cksum_table[i] = v;
332 * Build a table to translate packet type of mbuf to SWP type of Verbs.
335 mlx5_set_swp_types_table(void)
341 * The index should have:
342 * bit[0:1] = PKT_TX_L4_MASK
343 * bit[4] = PKT_TX_IPV6
344 * bit[8] = PKT_TX_OUTER_IPV6
345 * bit[9] = PKT_TX_OUTER_UDP
347 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
350 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
352 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
354 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
355 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
356 v |= MLX5_ETH_WQE_L4_INNER_UDP;
357 mlx5_swp_types_table[i] = v;
362 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
363 * Flags must be preliminary initialized to zero.
366 * Pointer to burst routine local context.
368 * Pointer to store Software Parser flags
370 * Configured Tx offloads mask. It is fully defined at
371 * compile time and may be used for optimization.
374 * Software Parser offsets packed in dword.
375 * Software Parser flags are set by pointer.
377 static __rte_always_inline uint32_t
378 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
383 unsigned int idx, off;
386 if (!MLX5_TXOFF_CONFIG(SWP))
388 ol = loc->mbuf->ol_flags;
389 tunnel = ol & PKT_TX_TUNNEL_MASK;
391 * Check whether Software Parser is required.
392 * Only customized tunnels may ask for.
394 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
397 * The index should have:
398 * bit[0:1] = PKT_TX_L4_MASK
399 * bit[4] = PKT_TX_IPV6
400 * bit[8] = PKT_TX_OUTER_IPV6
401 * bit[9] = PKT_TX_OUTER_UDP
403 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
404 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
405 *swp_flags = mlx5_swp_types_table[idx];
407 * Set offsets for SW parser. Since ConnectX-5, SW parser just
408 * complements HW parser. SW parser starts to engage only if HW parser
409 * can't reach a header. For the older devices, HW parser will not kick
410 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
411 * should be set regardless of HW offload.
413 off = loc->mbuf->outer_l2_len;
414 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
415 off += sizeof(struct rte_vlan_hdr);
416 set = (off >> 1) << 8; /* Outer L3 offset. */
417 off += loc->mbuf->outer_l3_len;
418 if (tunnel == PKT_TX_TUNNEL_UDP)
419 set |= off >> 1; /* Outer L4 offset. */
420 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
421 const uint64_t csum = ol & PKT_TX_L4_MASK;
422 off += loc->mbuf->l2_len;
423 set |= (off >> 1) << 24; /* Inner L3 offset. */
424 if (csum == PKT_TX_TCP_CKSUM ||
425 csum == PKT_TX_UDP_CKSUM ||
426 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
427 off += loc->mbuf->l3_len;
428 set |= (off >> 1) << 16; /* Inner L4 offset. */
431 set = rte_cpu_to_le_32(set);
436 * Convert the Checksum offloads to Verbs.
439 * Pointer to the mbuf.
442 * Converted checksum flags.
444 static __rte_always_inline uint8_t
445 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
448 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
449 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
450 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
453 * The index should have:
454 * bit[0] = PKT_TX_TCP_SEG
455 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
456 * bit[4] = PKT_TX_IP_CKSUM
457 * bit[8] = PKT_TX_OUTER_IP_CKSUM
460 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
461 return mlx5_cksum_table[idx];
465 * Internal function to compute the number of used descriptors in an RX queue
471 * The number of used rx descriptor.
474 rx_queue_count(struct mlx5_rxq_data *rxq)
476 struct rxq_zip *zip = &rxq->zip;
477 volatile struct mlx5_cqe *cqe;
478 const unsigned int cqe_n = (1 << rxq->cqe_n);
479 const unsigned int cqe_cnt = cqe_n - 1;
483 /* if we are processing a compressed cqe */
485 used = zip->cqe_cnt - zip->ca;
491 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
492 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
496 op_own = cqe->op_own;
497 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
498 n = rte_be_to_cpu_32(cqe->byte_cnt);
503 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
505 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
510 * DPDK callback to check the status of a rx descriptor.
515 * The index of the descriptor in the ring.
518 * The status of the tx descriptor.
521 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
523 struct mlx5_rxq_data *rxq = rx_queue;
524 struct mlx5_rxq_ctrl *rxq_ctrl =
525 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
526 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
528 if (dev->rx_pkt_burst != mlx5_rx_burst) {
532 if (offset >= (1 << rxq->elts_n)) {
536 if (offset < rx_queue_count(rxq))
537 return RTE_ETH_RX_DESC_DONE;
538 return RTE_ETH_RX_DESC_AVAIL;
542 * DPDK callback to get the RX queue information
545 * Pointer to the device structure.
548 * Rx queue identificator.
551 * Pointer to the RX queue information structure.
558 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
559 struct rte_eth_rxq_info *qinfo)
561 struct mlx5_priv *priv = dev->data->dev_private;
562 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
563 struct mlx5_rxq_ctrl *rxq_ctrl =
564 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
568 qinfo->mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
569 rxq->mprq_mp : rxq->mp;
570 qinfo->conf.rx_thresh.pthresh = 0;
571 qinfo->conf.rx_thresh.hthresh = 0;
572 qinfo->conf.rx_thresh.wthresh = 0;
573 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
574 qinfo->conf.rx_drop_en = 1;
575 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
576 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
577 qinfo->scattered_rx = dev->data->scattered_rx;
578 qinfo->nb_desc = 1 << rxq->elts_n;
582 * DPDK callback to get the RX packet burst mode information
585 * Pointer to the device structure.
588 * Rx queue identificatior.
591 * Pointer to the burts mode information.
594 * 0 as success, -EINVAL as failure.
598 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
599 uint16_t rx_queue_id __rte_unused,
600 struct rte_eth_burst_mode *mode)
602 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
604 if (pkt_burst == mlx5_rx_burst) {
605 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
606 } else if (pkt_burst == mlx5_rx_burst_mprq) {
607 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
608 } else if (pkt_burst == mlx5_rx_burst_vec) {
609 #if defined RTE_ARCH_X86_64
610 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
611 #elif defined RTE_ARCH_ARM64
612 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
613 #elif defined RTE_ARCH_PPC_64
614 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
625 * DPDK callback to get the number of used descriptors in a RX queue
628 * Pointer to the device structure.
634 * The number of used rx descriptor.
635 * -EINVAL if the queue is invalid
638 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
640 struct mlx5_priv *priv = dev->data->dev_private;
641 struct mlx5_rxq_data *rxq;
643 if (dev->rx_pkt_burst != mlx5_rx_burst) {
647 rxq = (*priv->rxqs)[rx_queue_id];
652 return rx_queue_count(rxq);
655 #define MLX5_SYSTEM_LOG_DIR "/var/log"
657 * Dump debug information to log file.
662 * If not NULL this string is printed as a header to the output
663 * and the output will be in hexadecimal view.
665 * This is the buffer address to print out.
667 * The number of bytes to dump out.
670 mlx5_dump_debug_information(const char *fname, const char *hex_title,
671 const void *buf, unsigned int hex_len)
675 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
676 fd = fopen(path, "a+");
678 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
679 MKSTR(path2, "./%s", fname);
680 fd = fopen(path2, "a+");
682 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
685 DRV_LOG(INFO, "New debug dump in file %s", path2);
687 DRV_LOG(INFO, "New debug dump in file %s", path);
690 rte_hexdump(fd, hex_title, buf, hex_len);
692 fprintf(fd, "%s", (const char *)buf);
693 fprintf(fd, "\n\n\n");
698 * Move QP from error state to running state and initialize indexes.
701 * Pointer to TX queue control structure.
704 * 0 on success, else -1.
707 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
709 struct mlx5_mp_arg_queue_state_modify sm = {
711 .queue_id = txq_ctrl->txq.idx,
714 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
716 txq_ctrl->txq.wqe_ci = 0;
717 txq_ctrl->txq.wqe_pi = 0;
718 txq_ctrl->txq.elts_comp = 0;
722 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
724 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
726 static const uint8_t magic[] = "seen";
730 for (i = 0; i < sizeof(magic); ++i)
731 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
733 err_cqe->rsvd1[i] = magic[i];
742 * Pointer to TX queue structure.
744 * Pointer to the error CQE.
747 * Negative value if queue recovery failed, otherwise
748 * the error completion entry is handled successfully.
751 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
752 volatile struct mlx5_err_cqe *err_cqe)
754 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
755 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
756 struct mlx5_txq_ctrl *txq_ctrl =
757 container_of(txq, struct mlx5_txq_ctrl, txq);
758 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
759 int seen = check_err_cqe_seen(err_cqe);
761 if (!seen && txq_ctrl->dump_file_n <
762 txq_ctrl->priv->config.max_dump_files_num) {
763 MKSTR(err_str, "Unexpected CQE error syndrome "
764 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
765 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
766 txq->cqe_s, txq->qp_num_8s >> 8,
767 rte_be_to_cpu_16(err_cqe->wqe_counter),
768 txq->wqe_ci, txq->cq_ci);
769 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
770 PORT_ID(txq_ctrl->priv), txq->idx,
771 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
772 mlx5_dump_debug_information(name, NULL, err_str, 0);
773 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
774 (const void *)((uintptr_t)
778 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
779 (const void *)((uintptr_t)
783 txq_ctrl->dump_file_n++;
787 * Count errors in WQEs units.
788 * Later it can be improved to count error packets,
789 * for example, by SQ parsing to find how much packets
790 * should be counted for each WQE.
792 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
794 if (tx_recover_qp(txq_ctrl)) {
795 /* Recovering failed - retry later on the same WQE. */
798 /* Release all the remaining buffers. */
799 txq_free_elts(txq_ctrl);
805 * Translate RX completion flags to packet type.
808 * Pointer to RX queue structure.
812 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
815 * Packet type for struct rte_mbuf.
817 static inline uint32_t
818 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
821 uint8_t pinfo = cqe->pkt_info;
822 uint16_t ptype = cqe->hdr_type_etc;
825 * The index to the array should have:
826 * bit[1:0] = l3_hdr_type
827 * bit[4:2] = l4_hdr_type
830 * bit[7] = outer_l3_type
832 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
833 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
837 * Initialize Rx WQ and indexes.
840 * Pointer to RX queue structure.
843 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
845 const unsigned int wqe_n = 1 << rxq->elts_n;
848 for (i = 0; (i != wqe_n); ++i) {
849 volatile struct mlx5_wqe_data_seg *scat;
853 if (mlx5_rxq_mprq_enabled(rxq)) {
854 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
856 scat = &((volatile struct mlx5_wqe_mprq *)
858 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
859 1 << rxq->strd_num_n);
860 byte_count = (1 << rxq->strd_sz_n) *
861 (1 << rxq->strd_num_n);
863 struct rte_mbuf *buf = (*rxq->elts)[i];
865 scat = &((volatile struct mlx5_wqe_data_seg *)
867 addr = rte_pktmbuf_mtod(buf, uintptr_t);
868 byte_count = DATA_LEN(buf);
870 /* scat->addr must be able to store a pointer. */
871 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
872 *scat = (struct mlx5_wqe_data_seg){
873 .addr = rte_cpu_to_be_64(addr),
874 .byte_count = rte_cpu_to_be_32(byte_count),
875 .lkey = mlx5_rx_addr2mr(rxq, addr),
878 rxq->consumed_strd = 0;
879 rxq->decompressed = 0;
881 rxq->zip = (struct rxq_zip){
884 /* Update doorbell counter. */
885 rxq->rq_ci = wqe_n >> rxq->sges_n;
887 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
891 * Modify a Verbs/DevX queue state.
892 * This must be called from the primary process.
895 * Pointer to Ethernet device.
897 * State modify request parameters.
900 * 0 in case of success else non-zero value and rte_errno is set.
903 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
904 const struct mlx5_mp_arg_queue_state_modify *sm)
907 struct mlx5_priv *priv = dev->data->dev_private;
910 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
911 struct mlx5_rxq_ctrl *rxq_ctrl =
912 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
914 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
915 struct ibv_wq_attr mod = {
916 .attr_mask = IBV_WQ_ATTR_STATE,
917 .wq_state = sm->state,
920 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
921 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
922 struct mlx5_devx_modify_rq_attr rq_attr;
924 memset(&rq_attr, 0, sizeof(rq_attr));
925 if (sm->state == IBV_WQS_RESET) {
926 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
927 rq_attr.state = MLX5_RQC_STATE_RST;
928 } else if (sm->state == IBV_WQS_RDY) {
929 rq_attr.rq_state = MLX5_RQC_STATE_RST;
930 rq_attr.state = MLX5_RQC_STATE_RDY;
931 } else if (sm->state == IBV_WQS_ERR) {
932 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
933 rq_attr.state = MLX5_RQC_STATE_ERR;
935 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
939 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
940 sm->state, strerror(errno));
945 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
946 struct mlx5_txq_ctrl *txq_ctrl =
947 container_of(txq, struct mlx5_txq_ctrl, txq);
949 if (txq_ctrl->obj->type == MLX5_TXQ_OBJ_TYPE_DEVX_SQ) {
950 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
952 /* Change queue state to reset. */
953 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
954 msq_attr.state = MLX5_SQC_STATE_RST;
955 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq_devx,
958 DRV_LOG(ERR, "Cannot change the "
959 "Tx QP state to RESET %s",
964 /* Change queue state to ready. */
965 msq_attr.sq_state = MLX5_SQC_STATE_RST;
966 msq_attr.state = MLX5_SQC_STATE_RDY;
967 ret = mlx5_devx_cmd_modify_sq(txq_ctrl->obj->sq_devx,
970 DRV_LOG(ERR, "Cannot change the "
971 "Tx QP state to READY %s",
977 struct ibv_qp_attr mod = {
978 .qp_state = IBV_QPS_RESET,
979 .port_num = (uint8_t)priv->dev_port,
981 struct ibv_qp *qp = txq_ctrl->obj->qp;
984 (txq_ctrl->obj->type == MLX5_TXQ_OBJ_TYPE_IBV);
986 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
988 DRV_LOG(ERR, "Cannot change the "
989 "Tx QP state to RESET %s",
994 mod.qp_state = IBV_QPS_INIT;
995 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
997 DRV_LOG(ERR, "Cannot change the "
998 "Tx QP state to INIT %s",
1003 mod.qp_state = IBV_QPS_RTR;
1004 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
1006 DRV_LOG(ERR, "Cannot change the "
1007 "Tx QP state to RTR %s",
1012 mod.qp_state = IBV_QPS_RTS;
1013 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
1015 DRV_LOG(ERR, "Cannot change the "
1016 "Tx QP state to RTS %s",
1027 * Modify a Verbs queue state.
1030 * Pointer to Ethernet device.
1032 * State modify request parameters.
1035 * 0 in case of success else non-zero value.
1038 mlx5_queue_state_modify(struct rte_eth_dev *dev,
1039 struct mlx5_mp_arg_queue_state_modify *sm)
1041 struct mlx5_priv *priv = dev->data->dev_private;
1044 switch (rte_eal_process_type()) {
1045 case RTE_PROC_PRIMARY:
1046 ret = mlx5_queue_state_modify_primary(dev, sm);
1048 case RTE_PROC_SECONDARY:
1049 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
1058 * Handle a Rx error.
1059 * The function inserts the RQ state to reset when the first error CQE is
1060 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1061 * it moves the RQ state to ready and initializes the RQ.
1062 * Next CQE identification and error counting are in the caller responsibility.
1065 * Pointer to RX queue structure.
1067 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
1068 * 0 when called from non-vectorized Rx burst.
1071 * -1 in case of recovery error, otherwise the CQE status.
1074 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1076 const uint16_t cqe_n = 1 << rxq->cqe_n;
1077 const uint16_t cqe_mask = cqe_n - 1;
1078 const unsigned int wqe_n = 1 << rxq->elts_n;
1079 struct mlx5_rxq_ctrl *rxq_ctrl =
1080 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1082 volatile struct mlx5_cqe *cqe;
1083 volatile struct mlx5_err_cqe *err_cqe;
1085 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1087 struct mlx5_mp_arg_queue_state_modify sm;
1090 switch (rxq->err_state) {
1091 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1092 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1094 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1096 sm.queue_id = rxq->idx;
1097 sm.state = IBV_WQS_RESET;
1098 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1100 if (rxq_ctrl->dump_file_n <
1101 rxq_ctrl->priv->config.max_dump_files_num) {
1102 MKSTR(err_str, "Unexpected CQE error syndrome "
1103 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1104 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1105 rxq->cqn, rxq_ctrl->wqn,
1106 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1107 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1108 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1109 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1110 mlx5_dump_debug_information(name, NULL, err_str, 0);
1111 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1112 (const void *)((uintptr_t)
1114 sizeof(*u.cqe) * cqe_n);
1115 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1116 (const void *)((uintptr_t)
1119 rxq_ctrl->dump_file_n++;
1121 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1123 case MLX5_RXQ_ERR_STATE_NEED_READY:
1124 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1125 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1127 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1130 * The RQ consumer index must be zeroed while moving
1131 * from RESET state to RDY state.
1133 *rxq->rq_db = rte_cpu_to_be_32(0);
1136 sm.queue_id = rxq->idx;
1137 sm.state = IBV_WQS_RDY;
1138 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1142 const uint16_t q_mask = wqe_n - 1;
1144 struct rte_mbuf **elt;
1146 unsigned int n = wqe_n - (rxq->rq_ci -
1149 for (i = 0; i < (int)n; ++i) {
1150 elt_idx = (rxq->rq_ci + i) & q_mask;
1151 elt = &(*rxq->elts)[elt_idx];
1152 *elt = rte_mbuf_raw_alloc(rxq->mp);
1154 for (i--; i >= 0; --i) {
1155 elt_idx = (rxq->rq_ci +
1159 rte_pktmbuf_free_seg
1165 for (i = 0; i < (int)wqe_n; ++i) {
1166 elt = &(*rxq->elts)[i];
1168 (uint16_t)((*elt)->buf_len -
1169 rte_pktmbuf_headroom(*elt));
1171 /* Padding with a fake mbuf for vec Rx. */
1172 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1173 (*rxq->elts)[wqe_n + i] =
1176 mlx5_rxq_initialize(rxq);
1177 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1186 * Get size of the next packet for a given CQE. For compressed CQEs, the
1187 * consumer index is updated only once all packets of the current one have
1191 * Pointer to RX queue.
1195 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1199 * 0 in case of empty CQE, otherwise the packet size in bytes.
1202 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1203 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1205 struct rxq_zip *zip = &rxq->zip;
1206 uint16_t cqe_n = cqe_cnt + 1;
1212 /* Process compressed data in the CQE and mini arrays. */
1214 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1215 (volatile struct mlx5_mini_cqe8 (*)[8])
1216 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1219 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1220 *mcqe = &(*mc)[zip->ai & 7];
1221 if ((++zip->ai & 7) == 0) {
1222 /* Invalidate consumed CQEs */
1225 while (idx != end) {
1226 (*rxq->cqes)[idx & cqe_cnt].op_own =
1227 MLX5_CQE_INVALIDATE;
1231 * Increment consumer index to skip the number
1232 * of CQEs consumed. Hardware leaves holes in
1233 * the CQ ring for software use.
1238 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1239 /* Invalidate the rest */
1243 while (idx != end) {
1244 (*rxq->cqes)[idx & cqe_cnt].op_own =
1245 MLX5_CQE_INVALIDATE;
1248 rxq->cq_ci = zip->cq_ci;
1252 * No compressed data, get next CQE and verify if it is
1259 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1260 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1261 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1263 ret = mlx5_rx_err_handle(rxq, 0);
1264 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1272 op_own = cqe->op_own;
1273 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1274 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1275 (volatile struct mlx5_mini_cqe8 (*)[8])
1276 (uintptr_t)(&(*rxq->cqes)
1280 /* Fix endianness. */
1281 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1283 * Current mini array position is the one
1284 * returned by check_cqe64().
1286 * If completion comprises several mini arrays,
1287 * as a special case the second one is located
1288 * 7 CQEs after the initial CQE instead of 8
1289 * for subsequent ones.
1291 zip->ca = rxq->cq_ci;
1292 zip->na = zip->ca + 7;
1293 /* Compute the next non compressed CQE. */
1295 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1296 /* Get packet size to return. */
1297 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1300 /* Prefetch all to be invalidated */
1303 while (idx != end) {
1304 rte_prefetch0(&(*rxq->cqes)[(idx) &
1309 len = rte_be_to_cpu_32(cqe->byte_cnt);
1312 if (unlikely(rxq->err_state)) {
1313 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1314 ++rxq->stats.idropped;
1322 * Translate RX completion flags to offload flags.
1328 * Offload flags (ol_flags) for struct rte_mbuf.
1330 static inline uint32_t
1331 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1333 uint32_t ol_flags = 0;
1334 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1338 MLX5_CQE_RX_L3_HDR_VALID,
1339 PKT_RX_IP_CKSUM_GOOD) |
1341 MLX5_CQE_RX_L4_HDR_VALID,
1342 PKT_RX_L4_CKSUM_GOOD);
1347 * Fill in mbuf fields from RX completion flags.
1348 * Note that pkt->ol_flags should be initialized outside of this function.
1351 * Pointer to RX queue.
1356 * @param rss_hash_res
1357 * Packet RSS Hash result.
1360 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1361 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1363 /* Update packet information. */
1364 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1365 if (rss_hash_res && rxq->rss_hash) {
1366 pkt->hash.rss = rss_hash_res;
1367 pkt->ol_flags |= PKT_RX_RSS_HASH;
1369 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1370 pkt->ol_flags |= PKT_RX_FDIR;
1371 if (cqe->sop_drop_qpn !=
1372 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1373 uint32_t mark = cqe->sop_drop_qpn;
1375 pkt->ol_flags |= PKT_RX_FDIR_ID;
1376 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1379 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1380 pkt->ol_flags |= rxq->flow_meta_mask;
1381 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1382 cqe->flow_table_metadata;
1385 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1386 if (rxq->vlan_strip &&
1387 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1388 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1389 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1391 if (rxq->hw_timestamp) {
1392 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1393 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1398 * DPDK callback for RX.
1401 * Generic pointer to RX queue structure.
1403 * Array to store received packets.
1405 * Maximum number of packets in array.
1408 * Number of packets successfully received (<= pkts_n).
1411 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1413 struct mlx5_rxq_data *rxq = dpdk_rxq;
1414 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1415 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1416 const unsigned int sges_n = rxq->sges_n;
1417 struct rte_mbuf *pkt = NULL;
1418 struct rte_mbuf *seg = NULL;
1419 volatile struct mlx5_cqe *cqe =
1420 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1422 unsigned int rq_ci = rxq->rq_ci << sges_n;
1423 int len = 0; /* keep its value across iterations. */
1426 unsigned int idx = rq_ci & wqe_cnt;
1427 volatile struct mlx5_wqe_data_seg *wqe =
1428 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1429 struct rte_mbuf *rep = (*rxq->elts)[idx];
1430 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1431 uint32_t rss_hash_res;
1439 rep = rte_mbuf_raw_alloc(rxq->mp);
1440 if (unlikely(rep == NULL)) {
1441 ++rxq->stats.rx_nombuf;
1444 * no buffers before we even started,
1445 * bail out silently.
1449 while (pkt != seg) {
1450 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1454 rte_mbuf_raw_free(pkt);
1460 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1461 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1463 rte_mbuf_raw_free(rep);
1467 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1468 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1469 /* If compressed, take hash result from mini-CQE. */
1470 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1472 mcqe->rx_hash_result);
1473 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1474 if (rxq->crc_present)
1475 len -= RTE_ETHER_CRC_LEN;
1477 if (cqe->lro_num_seg > 1) {
1479 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1481 pkt->ol_flags |= PKT_RX_LRO;
1482 pkt->tso_segsz = len / cqe->lro_num_seg;
1485 DATA_LEN(rep) = DATA_LEN(seg);
1486 PKT_LEN(rep) = PKT_LEN(seg);
1487 SET_DATA_OFF(rep, DATA_OFF(seg));
1488 PORT(rep) = PORT(seg);
1489 (*rxq->elts)[idx] = rep;
1491 * Fill NIC descriptor with the new buffer. The lkey and size
1492 * of the buffers are already known, only the buffer address
1495 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1496 /* If there's only one MR, no need to replace LKey in WQE. */
1497 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1498 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1499 if (len > DATA_LEN(seg)) {
1500 len -= DATA_LEN(seg);
1505 DATA_LEN(seg) = len;
1506 #ifdef MLX5_PMD_SOFT_COUNTERS
1507 /* Increment bytes counter. */
1508 rxq->stats.ibytes += PKT_LEN(pkt);
1510 /* Return packet. */
1515 /* Align consumer index to the next stride. */
1520 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1522 /* Update the consumer index. */
1523 rxq->rq_ci = rq_ci >> sges_n;
1525 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1527 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1528 #ifdef MLX5_PMD_SOFT_COUNTERS
1529 /* Increment packets counter. */
1530 rxq->stats.ipackets += i;
1536 * Update LRO packet TCP header.
1537 * The HW LRO feature doesn't update the TCP header after coalescing the
1538 * TCP segments but supplies information in CQE to fill it by SW.
1541 * Pointer to the TCP header.
1543 * Pointer to the completion entry..
1545 * The L3 pseudo-header checksum.
1548 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1549 volatile struct mlx5_cqe *__rte_restrict cqe,
1552 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1553 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1555 * The HW calculates only the TCP payload checksum, need to complete
1556 * the TCP header checksum and the L3 pseudo-header checksum.
1558 uint32_t csum = phcsum + cqe->csum;
1560 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1561 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1562 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1563 tcp->recv_ack = cqe->lro_ack_seq_num;
1564 tcp->rx_win = cqe->lro_tcp_win;
1566 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1567 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1569 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1570 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1571 csum = (~csum) & 0xffff;
1578 * Update LRO packet headers.
1579 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1580 * TCP segments but supply information in CQE to fill it by SW.
1583 * The packet address.
1585 * Pointer to the completion entry..
1587 * The packet length.
1590 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1591 volatile struct mlx5_cqe *__rte_restrict cqe,
1595 struct rte_ether_hdr *eth;
1596 struct rte_vlan_hdr *vlan;
1597 struct rte_ipv4_hdr *ipv4;
1598 struct rte_ipv6_hdr *ipv6;
1599 struct rte_tcp_hdr *tcp;
1604 uint16_t proto = h.eth->ether_type;
1608 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1609 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1610 proto = h.vlan->eth_proto;
1613 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1614 h.ipv4->time_to_live = cqe->lro_min_ttl;
1615 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1616 h.ipv4->hdr_checksum = 0;
1617 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1618 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1621 h.ipv6->hop_limits = cqe->lro_min_ttl;
1622 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1624 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1627 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1631 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1633 struct mlx5_mprq_buf *buf = opaque;
1635 if (rte_atomic16_read(&buf->refcnt) == 1) {
1636 rte_mempool_put(buf->mp, buf);
1637 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1638 rte_atomic16_set(&buf->refcnt, 1);
1639 rte_mempool_put(buf->mp, buf);
1644 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1646 mlx5_mprq_buf_free_cb(NULL, buf);
1650 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1651 const unsigned int strd_n)
1653 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1654 volatile struct mlx5_wqe_data_seg *wqe =
1655 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1658 MLX5_ASSERT(rep != NULL);
1659 /* Replace MPRQ buf. */
1660 (*rxq->mprq_bufs)[rq_idx] = rep;
1662 addr = mlx5_mprq_buf_addr(rep, strd_n);
1663 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1664 /* If there's only one MR, no need to replace LKey in WQE. */
1665 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1666 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1667 /* Stash a mbuf for next replacement. */
1668 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1669 rxq->mprq_repl = rep;
1671 rxq->mprq_repl = NULL;
1675 * DPDK callback for RX with Multi-Packet RQ support.
1678 * Generic pointer to RX queue structure.
1680 * Array to store received packets.
1682 * Maximum number of packets in array.
1685 * Number of packets successfully received (<= pkts_n).
1688 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1690 struct mlx5_rxq_data *rxq = dpdk_rxq;
1691 const unsigned int strd_n = 1 << rxq->strd_num_n;
1692 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1693 const unsigned int strd_shift =
1694 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1695 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1696 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1697 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1699 uint32_t rq_ci = rxq->rq_ci;
1700 uint16_t consumed_strd = rxq->consumed_strd;
1701 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1703 while (i < pkts_n) {
1704 struct rte_mbuf *pkt;
1712 int32_t hdrm_overlap;
1713 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1714 uint32_t rss_hash_res = 0;
1716 if (consumed_strd == strd_n) {
1717 /* Replace WQE only if the buffer is still in use. */
1718 if (rte_atomic16_read(&buf->refcnt) > 1) {
1719 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1720 /* Release the old buffer. */
1721 mlx5_mprq_buf_free(buf);
1722 } else if (unlikely(rxq->mprq_repl == NULL)) {
1723 struct mlx5_mprq_buf *rep;
1726 * Currently, the MPRQ mempool is out of buffer
1727 * and doing memcpy regardless of the size of Rx
1728 * packet. Retry allocation to get back to
1731 if (!rte_mempool_get(rxq->mprq_mp,
1733 rxq->mprq_repl = rep;
1735 /* Advance to the next WQE. */
1738 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1740 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1741 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1745 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1746 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1747 MLX5_ASSERT(strd_cnt);
1748 consumed_strd += strd_cnt;
1749 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1752 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1753 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1755 /* mini-CQE for MPRQ doesn't have hash result. */
1756 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1758 MLX5_ASSERT(strd_idx < strd_n);
1759 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1761 pkt = rte_pktmbuf_alloc(rxq->mp);
1762 if (unlikely(pkt == NULL)) {
1763 ++rxq->stats.rx_nombuf;
1766 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1767 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1768 if (rxq->crc_present)
1769 len -= RTE_ETHER_CRC_LEN;
1770 offset = strd_idx * strd_sz + strd_shift;
1771 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1772 hdrm_overlap = len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
1774 * Memcpy packets to the target mbuf if:
1775 * - The size of packet is smaller than mprq_max_memcpy_len.
1776 * - Out of buffer in the Mempool for Multi-Packet RQ.
1777 * - The packet's stride overlaps a headroom and scatter is off.
1779 if (len <= rxq->mprq_max_memcpy_len ||
1780 rxq->mprq_repl == NULL ||
1781 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
1782 if (likely(rte_pktmbuf_tailroom(pkt) >= len)) {
1783 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
1785 DATA_LEN(pkt) = len;
1786 } else if (rxq->strd_scatter_en) {
1787 struct rte_mbuf *prev = pkt;
1789 RTE_MIN(rte_pktmbuf_tailroom(pkt), len);
1790 uint32_t rem_len = len - seg_len;
1792 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
1794 DATA_LEN(pkt) = seg_len;
1796 struct rte_mbuf *next =
1797 rte_pktmbuf_alloc(rxq->mp);
1799 if (unlikely(next == NULL)) {
1800 rte_pktmbuf_free(pkt);
1801 ++rxq->stats.rx_nombuf;
1805 SET_DATA_OFF(next, 0);
1806 addr = RTE_PTR_ADD(addr, seg_len);
1808 (rte_pktmbuf_tailroom(next),
1811 (rte_pktmbuf_mtod(next, void *),
1813 DATA_LEN(next) = seg_len;
1819 rte_pktmbuf_free_seg(pkt);
1820 ++rxq->stats.idropped;
1824 rte_iova_t buf_iova;
1825 struct rte_mbuf_ext_shared_info *shinfo;
1826 uint16_t buf_len = strd_cnt * strd_sz;
1829 /* Increment the refcnt of the whole chunk. */
1830 rte_atomic16_add_return(&buf->refcnt, 1);
1831 MLX5_ASSERT((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1833 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
1835 * MLX5 device doesn't use iova but it is necessary in a
1836 * case where the Rx packet is transmitted via a
1839 buf_iova = rte_mempool_virt2iova(buf) +
1840 RTE_PTR_DIFF(buf_addr, buf);
1841 shinfo = &buf->shinfos[strd_idx];
1842 rte_mbuf_ext_refcnt_set(shinfo, 1);
1844 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1845 * attaching the stride to mbuf and more offload flags
1846 * will be added below by calling rxq_cq_to_mbuf().
1847 * Other fields will be overwritten.
1849 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1851 /* Set mbuf head-room. */
1852 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
1853 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
1854 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
1855 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
1856 DATA_LEN(pkt) = len;
1858 * Copy the last fragment of a packet (up to headroom
1859 * size bytes) in case there is a stride overlap with
1860 * a next packet's headroom. Allocate a separate mbuf
1861 * to store this fragment and link it. Scatter is on.
1863 if (hdrm_overlap > 0) {
1864 MLX5_ASSERT(rxq->strd_scatter_en);
1865 struct rte_mbuf *seg =
1866 rte_pktmbuf_alloc(rxq->mp);
1868 if (unlikely(seg == NULL)) {
1869 rte_pktmbuf_free_seg(pkt);
1870 ++rxq->stats.rx_nombuf;
1873 SET_DATA_OFF(seg, 0);
1874 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
1875 RTE_PTR_ADD(addr, len - hdrm_overlap),
1877 DATA_LEN(seg) = hdrm_overlap;
1878 DATA_LEN(pkt) = len - hdrm_overlap;
1883 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1884 if (cqe->lro_num_seg > 1) {
1885 mlx5_lro_update_hdr(addr, cqe, len);
1886 pkt->ol_flags |= PKT_RX_LRO;
1887 pkt->tso_segsz = len / cqe->lro_num_seg;
1890 PORT(pkt) = rxq->port_id;
1891 #ifdef MLX5_PMD_SOFT_COUNTERS
1892 /* Increment bytes counter. */
1893 rxq->stats.ibytes += PKT_LEN(pkt);
1895 /* Return packet. */
1900 /* Update the consumer indexes. */
1901 rxq->consumed_strd = consumed_strd;
1903 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1904 if (rq_ci != rxq->rq_ci) {
1907 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1909 #ifdef MLX5_PMD_SOFT_COUNTERS
1910 /* Increment packets counter. */
1911 rxq->stats.ipackets += i;
1917 * Dummy DPDK callback for TX.
1919 * This function is used to temporarily replace the real callback during
1920 * unsafe control operations on the queue, or in case of error.
1923 * Generic pointer to TX queue structure.
1925 * Packets to transmit.
1927 * Number of packets in array.
1930 * Number of packets successfully transmitted (<= pkts_n).
1933 removed_tx_burst(void *dpdk_txq __rte_unused,
1934 struct rte_mbuf **pkts __rte_unused,
1935 uint16_t pkts_n __rte_unused)
1942 * Dummy DPDK callback for RX.
1944 * This function is used to temporarily replace the real callback during
1945 * unsafe control operations on the queue, or in case of error.
1948 * Generic pointer to RX queue structure.
1950 * Array to store received packets.
1952 * Maximum number of packets in array.
1955 * Number of packets successfully received (<= pkts_n).
1958 removed_rx_burst(void *dpdk_txq __rte_unused,
1959 struct rte_mbuf **pkts __rte_unused,
1960 uint16_t pkts_n __rte_unused)
1967 * Vectorized Rx/Tx routines are not compiled in when required vector
1968 * instructions are not supported on a target architecture. The following null
1969 * stubs are needed for linkage when those are not included outside of this file
1970 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1974 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1975 struct rte_mbuf **pkts __rte_unused,
1976 uint16_t pkts_n __rte_unused)
1982 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1988 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1994 * Free the mbufs from the linear array of pointers.
1997 * Pointer to array of packets to be free.
1999 * Number of packets to be freed.
2001 * Configured Tx offloads mask. It is fully defined at
2002 * compile time and may be used for optimization.
2004 static __rte_always_inline void
2005 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
2006 unsigned int pkts_n,
2007 unsigned int olx __rte_unused)
2009 struct rte_mempool *pool = NULL;
2010 struct rte_mbuf **p_free = NULL;
2011 struct rte_mbuf *mbuf;
2012 unsigned int n_free = 0;
2015 * The implemented algorithm eliminates
2016 * copying pointers to temporary array
2017 * for rte_mempool_put_bulk() calls.
2020 MLX5_ASSERT(pkts_n);
2024 * Decrement mbuf reference counter, detach
2025 * indirect and external buffers if needed.
2027 mbuf = rte_pktmbuf_prefree_seg(*pkts);
2028 if (likely(mbuf != NULL)) {
2029 MLX5_ASSERT(mbuf == *pkts);
2030 if (likely(n_free != 0)) {
2031 if (unlikely(pool != mbuf->pool))
2032 /* From different pool. */
2035 /* Start new scan array. */
2042 if (unlikely(pkts_n == 0)) {
2048 * This happens if mbuf is still referenced.
2049 * We can't put it back to the pool, skip.
2053 if (unlikely(n_free != 0))
2054 /* There is some array to free.*/
2056 if (unlikely(pkts_n == 0))
2057 /* Last mbuf, nothing to free. */
2063 * This loop is implemented to avoid multiple
2064 * inlining of rte_mempool_put_bulk().
2067 MLX5_ASSERT(p_free);
2068 MLX5_ASSERT(n_free);
2070 * Free the array of pre-freed mbufs
2071 * belonging to the same memory pool.
2073 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
2074 if (unlikely(mbuf != NULL)) {
2075 /* There is the request to start new scan. */
2080 if (likely(pkts_n != 0))
2083 * This is the last mbuf to be freed.
2084 * Do one more loop iteration to complete.
2085 * This is rare case of the last unique mbuf.
2090 if (likely(pkts_n == 0))
2099 * Free the mbuf from the elts ring buffer till new tail.
2102 * Pointer to Tx queue structure.
2104 * Index in elts to free up to, becomes new elts tail.
2106 * Configured Tx offloads mask. It is fully defined at
2107 * compile time and may be used for optimization.
2109 static __rte_always_inline void
2110 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
2112 unsigned int olx __rte_unused)
2114 uint16_t n_elts = tail - txq->elts_tail;
2116 MLX5_ASSERT(n_elts);
2117 MLX5_ASSERT(n_elts <= txq->elts_s);
2119 * Implement a loop to support ring buffer wraparound
2120 * with single inlining of mlx5_tx_free_mbuf().
2125 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
2126 part = RTE_MIN(part, n_elts);
2128 MLX5_ASSERT(part <= txq->elts_s);
2129 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
2131 txq->elts_tail += part;
2137 * Store the mbuf being sent into elts ring buffer.
2138 * On Tx completion these mbufs will be freed.
2141 * Pointer to Tx queue structure.
2143 * Pointer to array of packets to be stored.
2145 * Number of packets to be stored.
2147 * Configured Tx offloads mask. It is fully defined at
2148 * compile time and may be used for optimization.
2150 static __rte_always_inline void
2151 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
2152 struct rte_mbuf **__rte_restrict pkts,
2153 unsigned int pkts_n,
2154 unsigned int olx __rte_unused)
2157 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2160 MLX5_ASSERT(pkts_n);
2161 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2163 MLX5_ASSERT(part <= txq->elts_s);
2164 /* This code is a good candidate for vectorizing with SIMD. */
2165 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2167 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2168 txq->elts_head += pkts_n;
2169 if (unlikely(part < pkts_n))
2170 /* The copy is wrapping around the elts array. */
2171 rte_memcpy((void *)elts, (void *)(pkts + part),
2172 (pkts_n - part) * sizeof(struct rte_mbuf *));
2176 * Update completion queue consuming index via doorbell
2177 * and flush the completed data buffers.
2180 * Pointer to TX queue structure.
2181 * @param valid CQE pointer
2182 * if not NULL update txq->wqe_pi and flush the buffers
2184 * Configured Tx offloads mask. It is fully defined at
2185 * compile time and may be used for optimization.
2187 static __rte_always_inline void
2188 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2189 volatile struct mlx5_cqe *last_cqe,
2190 unsigned int olx __rte_unused)
2192 if (likely(last_cqe != NULL)) {
2195 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2196 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2197 if (likely(tail != txq->elts_tail)) {
2198 mlx5_tx_free_elts(txq, tail, olx);
2199 MLX5_ASSERT(tail == txq->elts_tail);
2205 * Manage TX completions. This routine checks the CQ for
2206 * arrived CQEs, deduces the last accomplished WQE in SQ,
2207 * updates SQ producing index and frees all completed mbufs.
2210 * Pointer to TX queue structure.
2212 * Configured Tx offloads mask. It is fully defined at
2213 * compile time and may be used for optimization.
2215 * NOTE: not inlined intentionally, it makes tx_burst
2216 * routine smaller, simple and faster - from experiments.
2219 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2220 unsigned int olx __rte_unused)
2222 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2223 volatile struct mlx5_cqe *last_cqe = NULL;
2224 bool ring_doorbell = false;
2227 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2228 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2230 volatile struct mlx5_cqe *cqe;
2232 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2233 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2234 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2235 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2236 /* No new CQEs in completion queue. */
2237 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2241 * Some error occurred, try to restart.
2242 * We have no barrier after WQE related Doorbell
2243 * written, make sure all writes are completed
2244 * here, before we might perform SQ reset.
2247 ret = mlx5_tx_error_cqe_handle
2248 (txq, (volatile struct mlx5_err_cqe *)cqe);
2249 if (unlikely(ret < 0)) {
2251 * Some error occurred on queue error
2252 * handling, we do not advance the index
2253 * here, allowing to retry on next call.
2258 * We are going to fetch all entries with
2259 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2260 * The send queue is supposed to be empty.
2262 ring_doorbell = true;
2264 txq->cq_pi = txq->cq_ci;
2268 /* Normal transmit completion. */
2269 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2270 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2272 ring_doorbell = true;
2276 * We have to restrict the amount of processed CQEs
2277 * in one tx_burst routine call. The CQ may be large
2278 * and many CQEs may be updated by the NIC in one
2279 * transaction. Buffers freeing is time consuming,
2280 * multiple iterations may introduce significant
2283 if (likely(--count == 0))
2286 if (likely(ring_doorbell)) {
2287 /* Ring doorbell to notify hardware. */
2288 rte_compiler_barrier();
2289 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2290 mlx5_tx_comp_flush(txq, last_cqe, olx);
2295 * Check if the completion request flag should be set in the last WQE.
2296 * Both pushed mbufs and WQEs are monitored and the completion request
2297 * flag is set if any of thresholds is reached.
2300 * Pointer to TX queue structure.
2302 * Pointer to burst routine local context.
2304 * Configured Tx offloads mask. It is fully defined at
2305 * compile time and may be used for optimization.
2307 static __rte_always_inline void
2308 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2309 struct mlx5_txq_local *__rte_restrict loc,
2312 uint16_t head = txq->elts_head;
2315 part = MLX5_TXOFF_CONFIG(INLINE) ?
2316 0 : loc->pkts_sent - loc->pkts_copy;
2318 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2319 (MLX5_TXOFF_CONFIG(INLINE) &&
2320 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2321 volatile struct mlx5_wqe *last = loc->wqe_last;
2324 txq->elts_comp = head;
2325 if (MLX5_TXOFF_CONFIG(INLINE))
2326 txq->wqe_comp = txq->wqe_ci;
2327 /* Request unconditional completion on last WQE. */
2328 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2329 MLX5_COMP_MODE_OFFSET);
2330 /* Save elts_head in dedicated free on completion queue. */
2331 #ifdef RTE_LIBRTE_MLX5_DEBUG
2332 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2333 (last->cseg.opcode >> 8) << 16;
2335 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2337 /* A CQE slot must always be available. */
2338 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2343 * DPDK callback to check the status of a tx descriptor.
2348 * The index of the descriptor in the ring.
2351 * The status of the tx descriptor.
2354 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2356 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2359 mlx5_tx_handle_completion(txq, 0);
2360 used = txq->elts_head - txq->elts_tail;
2362 return RTE_ETH_TX_DESC_FULL;
2363 return RTE_ETH_TX_DESC_DONE;
2367 * Build the Control Segment with specified opcode:
2368 * - MLX5_OPCODE_SEND
2369 * - MLX5_OPCODE_ENHANCED_MPSW
2373 * Pointer to TX queue structure.
2375 * Pointer to burst routine local context.
2377 * Pointer to WQE to fill with built Control Segment.
2379 * Supposed length of WQE in segments.
2381 * SQ WQE opcode to put into Control Segment.
2383 * Configured Tx offloads mask. It is fully defined at
2384 * compile time and may be used for optimization.
2386 static __rte_always_inline void
2387 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2388 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2389 struct mlx5_wqe *__rte_restrict wqe,
2391 unsigned int opcode,
2392 unsigned int olx __rte_unused)
2394 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2396 /* For legacy MPW replace the EMPW by TSO with modifier. */
2397 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2398 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2399 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2400 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2401 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2402 MLX5_COMP_MODE_OFFSET);
2403 cs->misc = RTE_BE32(0);
2407 * Build the Ethernet Segment without inlined data.
2408 * Supports Software Parser, Checksums and VLAN
2409 * insertion Tx offload features.
2412 * Pointer to TX queue structure.
2414 * Pointer to burst routine local context.
2416 * Pointer to WQE to fill with built Ethernet Segment.
2418 * Configured Tx offloads mask. It is fully defined at
2419 * compile time and may be used for optimization.
2421 static __rte_always_inline void
2422 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2423 struct mlx5_txq_local *__rte_restrict loc,
2424 struct mlx5_wqe *__rte_restrict wqe,
2427 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2431 * Calculate and set check sum flags first, dword field
2432 * in segment may be shared with Software Parser flags.
2434 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2435 es->flags = rte_cpu_to_le_32(csum);
2437 * Calculate and set Software Parser offsets and flags.
2438 * These flags a set for custom UDP and IP tunnel packets.
2440 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2441 /* Fill metadata field if needed. */
2442 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2443 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2444 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2445 /* Engage VLAN tag insertion feature if requested. */
2446 if (MLX5_TXOFF_CONFIG(VLAN) &&
2447 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2449 * We should get here only if device support
2450 * this feature correctly.
2452 MLX5_ASSERT(txq->vlan_en);
2453 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2454 loc->mbuf->vlan_tci);
2456 es->inline_hdr = RTE_BE32(0);
2461 * Build the Ethernet Segment with minimal inlined data
2462 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2463 * used to fill the gap in single WQEBB WQEs.
2464 * Supports Software Parser, Checksums and VLAN
2465 * insertion Tx offload features.
2468 * Pointer to TX queue structure.
2470 * Pointer to burst routine local context.
2472 * Pointer to WQE to fill with built Ethernet Segment.
2474 * Length of VLAN tag insertion if any.
2476 * Configured Tx offloads mask. It is fully defined at
2477 * compile time and may be used for optimization.
2479 static __rte_always_inline void
2480 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2481 struct mlx5_txq_local *__rte_restrict loc,
2482 struct mlx5_wqe *__rte_restrict wqe,
2486 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2488 uint8_t *psrc, *pdst;
2491 * Calculate and set check sum flags first, dword field
2492 * in segment may be shared with Software Parser flags.
2494 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2495 es->flags = rte_cpu_to_le_32(csum);
2497 * Calculate and set Software Parser offsets and flags.
2498 * These flags a set for custom UDP and IP tunnel packets.
2500 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2501 /* Fill metadata field if needed. */
2502 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2503 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2504 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2505 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2507 sizeof(rte_v128u32_t)),
2508 "invalid Ethernet Segment data size");
2509 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2511 sizeof(struct rte_vlan_hdr) +
2512 2 * RTE_ETHER_ADDR_LEN),
2513 "invalid Ethernet Segment data size");
2514 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2515 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2516 es->inline_data = *(unaligned_uint16_t *)psrc;
2517 psrc += sizeof(uint16_t);
2518 pdst = (uint8_t *)(es + 1);
2519 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2520 /* Implement VLAN tag insertion as part inline data. */
2521 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2522 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2523 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2524 /* Insert VLAN ethertype + VLAN tag. */
2525 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2526 ((RTE_ETHER_TYPE_VLAN << 16) |
2527 loc->mbuf->vlan_tci);
2528 pdst += sizeof(struct rte_vlan_hdr);
2529 /* Copy the rest two bytes from packet data. */
2530 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2531 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2533 /* Fill the gap in the title WQEBB with inline data. */
2534 rte_mov16(pdst, psrc);
2539 * Build the Ethernet Segment with entire packet
2540 * data inlining. Checks the boundary of WQEBB and
2541 * ring buffer wrapping, supports Software Parser,
2542 * Checksums and VLAN insertion Tx offload features.
2545 * Pointer to TX queue structure.
2547 * Pointer to burst routine local context.
2549 * Pointer to WQE to fill with built Ethernet Segment.
2551 * Length of VLAN tag insertion if any.
2553 * Length of data to inline (VLAN included, if any).
2555 * TSO flag, set mss field from the packet.
2557 * Configured Tx offloads mask. It is fully defined at
2558 * compile time and may be used for optimization.
2561 * Pointer to the next Data Segment (aligned and wrapped around).
2563 static __rte_always_inline struct mlx5_wqe_dseg *
2564 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2565 struct mlx5_txq_local *__rte_restrict loc,
2566 struct mlx5_wqe *__rte_restrict wqe,
2572 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2574 uint8_t *psrc, *pdst;
2578 * Calculate and set check sum flags first, dword field
2579 * in segment may be shared with Software Parser flags.
2581 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2584 csum |= loc->mbuf->tso_segsz;
2585 es->flags = rte_cpu_to_be_32(csum);
2587 es->flags = rte_cpu_to_le_32(csum);
2590 * Calculate and set Software Parser offsets and flags.
2591 * These flags a set for custom UDP and IP tunnel packets.
2593 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2594 /* Fill metadata field if needed. */
2595 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2596 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2597 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2598 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2600 sizeof(rte_v128u32_t)),
2601 "invalid Ethernet Segment data size");
2602 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2604 sizeof(struct rte_vlan_hdr) +
2605 2 * RTE_ETHER_ADDR_LEN),
2606 "invalid Ethernet Segment data size");
2607 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2608 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2609 es->inline_data = *(unaligned_uint16_t *)psrc;
2610 psrc += sizeof(uint16_t);
2611 pdst = (uint8_t *)(es + 1);
2612 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2613 /* Implement VLAN tag insertion as part inline data. */
2614 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2615 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2616 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2617 /* Insert VLAN ethertype + VLAN tag. */
2618 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2619 ((RTE_ETHER_TYPE_VLAN << 16) |
2620 loc->mbuf->vlan_tci);
2621 pdst += sizeof(struct rte_vlan_hdr);
2622 /* Copy the rest two bytes from packet data. */
2623 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2624 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2625 psrc += sizeof(uint16_t);
2627 /* Fill the gap in the title WQEBB with inline data. */
2628 rte_mov16(pdst, psrc);
2629 psrc += sizeof(rte_v128u32_t);
2631 pdst = (uint8_t *)(es + 2);
2632 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2633 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2634 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2636 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2637 return (struct mlx5_wqe_dseg *)pdst;
2640 * The WQEBB space availability is checked by caller.
2641 * Here we should be aware of WQE ring buffer wraparound only.
2643 part = (uint8_t *)txq->wqes_end - pdst;
2644 part = RTE_MIN(part, inlen);
2646 rte_memcpy(pdst, psrc, part);
2648 if (likely(!inlen)) {
2650 * If return value is not used by the caller
2651 * the code below will be optimized out.
2654 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2655 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2656 pdst = (uint8_t *)txq->wqes;
2657 return (struct mlx5_wqe_dseg *)pdst;
2659 pdst = (uint8_t *)txq->wqes;
2666 * Copy data from chain of mbuf to the specified linear buffer.
2667 * Checksums and VLAN insertion Tx offload features. If data
2668 * from some mbuf copied completely this mbuf is freed. Local
2669 * structure is used to keep the byte stream state.
2672 * Pointer to the destination linear buffer.
2674 * Pointer to burst routine local context.
2676 * Length of data to be copied.
2678 * Length of data to be copied ignoring no inline hint.
2680 * Configured Tx offloads mask. It is fully defined at
2681 * compile time and may be used for optimization.
2684 * Number of actual copied data bytes. This is always greater than or
2685 * equal to must parameter and might be lesser than len in no inline
2686 * hint flag is encountered.
2688 static __rte_always_inline unsigned int
2689 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2690 struct mlx5_txq_local *__rte_restrict loc,
2693 unsigned int olx __rte_unused)
2695 struct rte_mbuf *mbuf;
2696 unsigned int part, dlen, copy = 0;
2700 MLX5_ASSERT(must <= len);
2702 /* Allow zero length packets, must check first. */
2703 dlen = rte_pktmbuf_data_len(loc->mbuf);
2704 if (dlen <= loc->mbuf_off) {
2705 /* Exhausted packet, just free. */
2707 loc->mbuf = mbuf->next;
2708 rte_pktmbuf_free_seg(mbuf);
2710 MLX5_ASSERT(loc->mbuf_nseg > 1);
2711 MLX5_ASSERT(loc->mbuf);
2713 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2718 * We already copied the minimal
2719 * requested amount of data.
2724 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2726 * Copy only the minimal required
2727 * part of the data buffer.
2734 dlen -= loc->mbuf_off;
2735 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2737 part = RTE_MIN(len, dlen);
2738 rte_memcpy(pdst, psrc, part);
2740 loc->mbuf_off += part;
2743 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2745 /* Exhausted packet, just free. */
2747 loc->mbuf = mbuf->next;
2748 rte_pktmbuf_free_seg(mbuf);
2750 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2760 * Build the Ethernet Segment with inlined data from
2761 * multi-segment packet. Checks the boundary of WQEBB
2762 * and ring buffer wrapping, supports Software Parser,
2763 * Checksums and VLAN insertion Tx offload features.
2766 * Pointer to TX queue structure.
2768 * Pointer to burst routine local context.
2770 * Pointer to WQE to fill with built Ethernet Segment.
2772 * Length of VLAN tag insertion if any.
2774 * Length of data to inline (VLAN included, if any).
2776 * TSO flag, set mss field from the packet.
2778 * Configured Tx offloads mask. It is fully defined at
2779 * compile time and may be used for optimization.
2782 * Pointer to the next Data Segment (aligned and
2783 * possible NOT wrapped around - caller should do
2784 * wrapping check on its own).
2786 static __rte_always_inline struct mlx5_wqe_dseg *
2787 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2788 struct mlx5_txq_local *__rte_restrict loc,
2789 struct mlx5_wqe *__rte_restrict wqe,
2795 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2798 unsigned int part, tlen = 0;
2801 * Calculate and set check sum flags first, uint32_t field
2802 * in segment may be shared with Software Parser flags.
2804 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2807 csum |= loc->mbuf->tso_segsz;
2808 es->flags = rte_cpu_to_be_32(csum);
2810 es->flags = rte_cpu_to_le_32(csum);
2813 * Calculate and set Software Parser offsets and flags.
2814 * These flags a set for custom UDP and IP tunnel packets.
2816 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2817 /* Fill metadata field if needed. */
2818 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2819 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2820 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2821 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2823 sizeof(rte_v128u32_t)),
2824 "invalid Ethernet Segment data size");
2825 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2827 sizeof(struct rte_vlan_hdr) +
2828 2 * RTE_ETHER_ADDR_LEN),
2829 "invalid Ethernet Segment data size");
2830 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2831 pdst = (uint8_t *)&es->inline_data;
2832 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2833 /* Implement VLAN tag insertion as part inline data. */
2834 mlx5_tx_mseg_memcpy(pdst, loc,
2835 2 * RTE_ETHER_ADDR_LEN,
2836 2 * RTE_ETHER_ADDR_LEN, olx);
2837 pdst += 2 * RTE_ETHER_ADDR_LEN;
2838 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2839 ((RTE_ETHER_TYPE_VLAN << 16) |
2840 loc->mbuf->vlan_tci);
2841 pdst += sizeof(struct rte_vlan_hdr);
2842 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2844 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2846 * The WQEBB space availability is checked by caller.
2847 * Here we should be aware of WQE ring buffer wraparound only.
2849 part = (uint8_t *)txq->wqes_end - pdst;
2850 part = RTE_MIN(part, inlen - tlen);
2856 * Copying may be interrupted inside the routine
2857 * if run into no inline hint flag.
2859 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2860 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2862 if (likely(inlen <= tlen) || copy < part) {
2863 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2865 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2866 return (struct mlx5_wqe_dseg *)pdst;
2868 pdst = (uint8_t *)txq->wqes;
2869 part = inlen - tlen;
2874 * Build the Data Segment of pointer type.
2877 * Pointer to TX queue structure.
2879 * Pointer to burst routine local context.
2881 * Pointer to WQE to fill with built Data Segment.
2883 * Data buffer to point.
2885 * Data buffer length.
2887 * Configured Tx offloads mask. It is fully defined at
2888 * compile time and may be used for optimization.
2890 static __rte_always_inline void
2891 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2892 struct mlx5_txq_local *__rte_restrict loc,
2893 struct mlx5_wqe_dseg *__rte_restrict dseg,
2896 unsigned int olx __rte_unused)
2900 dseg->bcount = rte_cpu_to_be_32(len);
2901 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2902 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2906 * Build the Data Segment of pointer type or inline
2907 * if data length is less than buffer in minimal
2908 * Data Segment size.
2911 * Pointer to TX queue structure.
2913 * Pointer to burst routine local context.
2915 * Pointer to WQE to fill with built Data Segment.
2917 * Data buffer to point.
2919 * Data buffer length.
2921 * Configured Tx offloads mask. It is fully defined at
2922 * compile time and may be used for optimization.
2924 static __rte_always_inline void
2925 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2926 struct mlx5_txq_local *__rte_restrict loc,
2927 struct mlx5_wqe_dseg *__rte_restrict dseg,
2930 unsigned int olx __rte_unused)
2936 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2937 dseg->bcount = rte_cpu_to_be_32(len);
2938 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2939 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2943 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2944 /* Unrolled implementation of generic rte_memcpy. */
2945 dst = (uintptr_t)&dseg->inline_data[0];
2946 src = (uintptr_t)buf;
2948 #ifdef RTE_ARCH_STRICT_ALIGN
2949 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2950 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2951 dst += sizeof(uint32_t);
2952 src += sizeof(uint32_t);
2953 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2954 dst += sizeof(uint32_t);
2955 src += sizeof(uint32_t);
2957 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2958 dst += sizeof(uint64_t);
2959 src += sizeof(uint64_t);
2963 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2964 dst += sizeof(uint32_t);
2965 src += sizeof(uint32_t);
2968 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2969 dst += sizeof(uint16_t);
2970 src += sizeof(uint16_t);
2973 *(uint8_t *)dst = *(uint8_t *)src;
2977 * Build the Data Segment of inlined data from single
2978 * segment packet, no VLAN insertion.
2981 * Pointer to TX queue structure.
2983 * Pointer to burst routine local context.
2985 * Pointer to WQE to fill with built Data Segment.
2987 * Data buffer to point.
2989 * Data buffer length.
2991 * Configured Tx offloads mask. It is fully defined at
2992 * compile time and may be used for optimization.
2995 * Pointer to the next Data Segment after inlined data.
2996 * Ring buffer wraparound check is needed. We do not
2997 * do it here because it may not be needed for the
2998 * last packet in the eMPW session.
3000 static __rte_always_inline struct mlx5_wqe_dseg *
3001 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
3002 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
3003 struct mlx5_wqe_dseg *__rte_restrict dseg,
3006 unsigned int olx __rte_unused)
3011 if (!MLX5_TXOFF_CONFIG(MPW)) {
3012 /* Store the descriptor byte counter for eMPW sessions. */
3013 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
3014 pdst = &dseg->inline_data[0];
3016 /* The entire legacy MPW session counter is stored on close. */
3017 pdst = (uint8_t *)dseg;
3020 * The WQEBB space availability is checked by caller.
3021 * Here we should be aware of WQE ring buffer wraparound only.
3023 part = (uint8_t *)txq->wqes_end - pdst;
3024 part = RTE_MIN(part, len);
3026 rte_memcpy(pdst, buf, part);
3030 if (!MLX5_TXOFF_CONFIG(MPW))
3031 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3032 /* Note: no final wraparound check here. */
3033 return (struct mlx5_wqe_dseg *)pdst;
3035 pdst = (uint8_t *)txq->wqes;
3042 * Build the Data Segment of inlined data from single
3043 * segment packet with VLAN insertion.
3046 * Pointer to TX queue structure.
3048 * Pointer to burst routine local context.
3050 * Pointer to the dseg fill with built Data Segment.
3052 * Data buffer to point.
3054 * Data buffer length.
3056 * Configured Tx offloads mask. It is fully defined at
3057 * compile time and may be used for optimization.
3060 * Pointer to the next Data Segment after inlined data.
3061 * Ring buffer wraparound check is needed.
3063 static __rte_always_inline struct mlx5_wqe_dseg *
3064 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
3065 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
3066 struct mlx5_wqe_dseg *__rte_restrict dseg,
3069 unsigned int olx __rte_unused)
3075 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
3076 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
3077 (2 * RTE_ETHER_ADDR_LEN),
3078 "invalid Data Segment data size");
3079 if (!MLX5_TXOFF_CONFIG(MPW)) {
3080 /* Store the descriptor byte counter for eMPW sessions. */
3081 dseg->bcount = rte_cpu_to_be_32
3082 ((len + sizeof(struct rte_vlan_hdr)) |
3083 MLX5_ETH_WQE_DATA_INLINE);
3084 pdst = &dseg->inline_data[0];
3086 /* The entire legacy MPW session counter is stored on close. */
3087 pdst = (uint8_t *)dseg;
3089 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
3090 buf += MLX5_DSEG_MIN_INLINE_SIZE;
3091 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
3092 len -= MLX5_DSEG_MIN_INLINE_SIZE;
3093 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
3094 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
3095 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
3096 pdst = (uint8_t *)txq->wqes;
3097 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
3098 loc->mbuf->vlan_tci);
3099 pdst += sizeof(struct rte_vlan_hdr);
3101 * The WQEBB space availability is checked by caller.
3102 * Here we should be aware of WQE ring buffer wraparound only.
3104 part = (uint8_t *)txq->wqes_end - pdst;
3105 part = RTE_MIN(part, len);
3107 rte_memcpy(pdst, buf, part);
3111 if (!MLX5_TXOFF_CONFIG(MPW))
3112 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3113 /* Note: no final wraparound check here. */
3114 return (struct mlx5_wqe_dseg *)pdst;
3116 pdst = (uint8_t *)txq->wqes;
3123 * Build the Ethernet Segment with optionally inlined data with
3124 * VLAN insertion and following Data Segments (if any) from
3125 * multi-segment packet. Used by ordinary send and TSO.
3128 * Pointer to TX queue structure.
3130 * Pointer to burst routine local context.
3132 * Pointer to WQE to fill with built Ethernet/Data Segments.
3134 * Length of VLAN header to insert, 0 means no VLAN insertion.
3136 * Data length to inline. For TSO this parameter specifies
3137 * exact value, for ordinary send routine can be aligned by
3138 * caller to provide better WQE space saving and data buffer
3139 * start address alignment. This length includes VLAN header
3142 * Zero means ordinary send, inlined data can be extended,
3143 * otherwise this is TSO, inlined data length is fixed.
3145 * Configured Tx offloads mask. It is fully defined at
3146 * compile time and may be used for optimization.
3149 * Actual size of built WQE in segments.
3151 static __rte_always_inline unsigned int
3152 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3153 struct mlx5_txq_local *__rte_restrict loc,
3154 struct mlx5_wqe *__rte_restrict wqe,
3158 unsigned int olx __rte_unused)
3160 struct mlx5_wqe_dseg *__rte_restrict dseg;
3163 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3164 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3167 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3168 if (!loc->mbuf_nseg)
3171 * There are still some mbuf remaining, not inlined.
3172 * The first mbuf may be partially inlined and we
3173 * must process the possible non-zero data offset.
3175 if (loc->mbuf_off) {
3180 * Exhausted packets must be dropped before.
3181 * Non-zero offset means there are some data
3182 * remained in the packet.
3184 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3185 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3186 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3188 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3190 * Build the pointer/minimal data Data Segment.
3191 * Do ring buffer wrapping check in advance.
3193 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3194 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3195 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3196 /* Store the mbuf to be freed on completion. */
3197 MLX5_ASSERT(loc->elts_free);
3198 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3201 if (--loc->mbuf_nseg == 0)
3203 loc->mbuf = loc->mbuf->next;
3207 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3208 struct rte_mbuf *mbuf;
3210 /* Zero length segment found, just skip. */
3212 loc->mbuf = loc->mbuf->next;
3213 rte_pktmbuf_free_seg(mbuf);
3214 if (--loc->mbuf_nseg == 0)
3217 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3218 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3221 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3222 rte_pktmbuf_data_len(loc->mbuf), olx);
3223 MLX5_ASSERT(loc->elts_free);
3224 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3227 if (--loc->mbuf_nseg == 0)
3229 loc->mbuf = loc->mbuf->next;
3234 /* Calculate actual segments used from the dseg pointer. */
3235 if ((uintptr_t)wqe < (uintptr_t)dseg)
3236 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3238 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3239 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3244 * Tx one packet function for multi-segment TSO. Supports all
3245 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3246 * sends one packet per WQE.
3248 * This routine is responsible for storing processed mbuf
3249 * into elts ring buffer and update elts_head.
3252 * Pointer to TX queue structure.
3254 * Pointer to burst routine local context.
3256 * Configured Tx offloads mask. It is fully defined at
3257 * compile time and may be used for optimization.
3260 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3261 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3262 * Local context variables partially updated.
3264 static __rte_always_inline enum mlx5_txcmp_code
3265 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3266 struct mlx5_txq_local *__rte_restrict loc,
3269 struct mlx5_wqe *__rte_restrict wqe;
3270 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3273 * Calculate data length to be inlined to estimate
3274 * the required space in WQE ring buffer.
3276 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3277 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3278 vlan = sizeof(struct rte_vlan_hdr);
3279 inlen = loc->mbuf->l2_len + vlan +
3280 loc->mbuf->l3_len + loc->mbuf->l4_len;
3281 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3282 return MLX5_TXCMP_CODE_ERROR;
3283 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3284 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3285 /* Packet must contain all TSO headers. */
3286 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3287 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3288 inlen > (dlen + vlan)))
3289 return MLX5_TXCMP_CODE_ERROR;
3290 MLX5_ASSERT(inlen >= txq->inlen_mode);
3292 * Check whether there are enough free WQEBBs:
3294 * - Ethernet Segment
3295 * - First Segment of inlined Ethernet data
3296 * - ... data continued ...
3297 * - Data Segments of pointer/min inline type
3299 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3300 MLX5_ESEG_MIN_INLINE_SIZE +
3302 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3303 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3304 return MLX5_TXCMP_CODE_EXIT;
3305 /* Check for maximal WQE size. */
3306 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3307 return MLX5_TXCMP_CODE_ERROR;
3308 #ifdef MLX5_PMD_SOFT_COUNTERS
3309 /* Update sent data bytes/packets counters. */
3310 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3311 loc->mbuf->tso_segsz;
3313 * One will be added for mbuf itself
3314 * at the end of the mlx5_tx_burst from
3315 * loc->pkts_sent field.
3318 txq->stats.opackets += ntcp;
3319 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3321 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3322 loc->wqe_last = wqe;
3323 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3324 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3325 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3326 txq->wqe_ci += (ds + 3) / 4;
3327 loc->wqe_free -= (ds + 3) / 4;
3328 return MLX5_TXCMP_CODE_MULTI;
3332 * Tx one packet function for multi-segment SEND. Supports all
3333 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3334 * sends one packet per WQE, without any data inlining in
3337 * This routine is responsible for storing processed mbuf
3338 * into elts ring buffer and update elts_head.
3341 * Pointer to TX queue structure.
3343 * Pointer to burst routine local context.
3345 * Configured Tx offloads mask. It is fully defined at
3346 * compile time and may be used for optimization.
3349 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3350 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3351 * Local context variables partially updated.
3353 static __rte_always_inline enum mlx5_txcmp_code
3354 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3355 struct mlx5_txq_local *__rte_restrict loc,
3358 struct mlx5_wqe_dseg *__rte_restrict dseg;
3359 struct mlx5_wqe *__rte_restrict wqe;
3360 unsigned int ds, nseg;
3362 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3364 * No inline at all, it means the CPU cycles saving
3365 * is prioritized at configuration, we should not
3366 * copy any packet data to WQE.
3368 nseg = NB_SEGS(loc->mbuf);
3370 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3371 return MLX5_TXCMP_CODE_EXIT;
3372 /* Check for maximal WQE size. */
3373 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3374 return MLX5_TXCMP_CODE_ERROR;
3376 * Some Tx offloads may cause an error if
3377 * packet is not long enough, check against
3378 * assumed minimal length.
3380 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3381 return MLX5_TXCMP_CODE_ERROR;
3382 #ifdef MLX5_PMD_SOFT_COUNTERS
3383 /* Update sent data bytes counter. */
3384 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3385 if (MLX5_TXOFF_CONFIG(VLAN) &&
3386 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3387 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3390 * SEND WQE, one WQEBB:
3391 * - Control Segment, SEND opcode
3392 * - Ethernet Segment, optional VLAN, no inline
3393 * - Data Segments, pointer only type
3395 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3396 loc->wqe_last = wqe;
3397 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3398 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3399 dseg = &wqe->dseg[0];
3401 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3402 struct rte_mbuf *mbuf;
3405 * Zero length segment found, have to
3406 * correct total size of WQE in segments.
3407 * It is supposed to be rare occasion, so
3408 * in normal case (no zero length segments)
3409 * we avoid extra writing to the Control
3413 wqe->cseg.sq_ds -= RTE_BE32(1);
3415 loc->mbuf = mbuf->next;
3416 rte_pktmbuf_free_seg(mbuf);
3422 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3423 rte_pktmbuf_data_len(loc->mbuf), olx);
3424 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3429 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3430 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3431 loc->mbuf = loc->mbuf->next;
3434 txq->wqe_ci += (ds + 3) / 4;
3435 loc->wqe_free -= (ds + 3) / 4;
3436 return MLX5_TXCMP_CODE_MULTI;
3440 * Tx one packet function for multi-segment SEND. Supports all
3441 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3442 * sends one packet per WQE, with data inlining in
3443 * Ethernet Segment and minimal Data Segments.
3445 * This routine is responsible for storing processed mbuf
3446 * into elts ring buffer and update elts_head.
3449 * Pointer to TX queue structure.
3451 * Pointer to burst routine local context.
3453 * Configured Tx offloads mask. It is fully defined at
3454 * compile time and may be used for optimization.
3457 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3458 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3459 * Local context variables partially updated.
3461 static __rte_always_inline enum mlx5_txcmp_code
3462 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3463 struct mlx5_txq_local *__rte_restrict loc,
3466 struct mlx5_wqe *__rte_restrict wqe;
3467 unsigned int ds, inlen, dlen, vlan = 0;
3469 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3470 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3472 * First calculate data length to be inlined
3473 * to estimate the required space for WQE.
3475 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3476 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3477 vlan = sizeof(struct rte_vlan_hdr);
3478 inlen = dlen + vlan;
3479 /* Check against minimal length. */
3480 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3481 return MLX5_TXCMP_CODE_ERROR;
3482 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3483 if (inlen > txq->inlen_send ||
3484 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3485 struct rte_mbuf *mbuf;
3490 * Packet length exceeds the allowed inline
3491 * data length, check whether the minimal
3492 * inlining is required.
3494 if (txq->inlen_mode) {
3495 MLX5_ASSERT(txq->inlen_mode >=
3496 MLX5_ESEG_MIN_INLINE_SIZE);
3497 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3498 inlen = txq->inlen_mode;
3500 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3501 !vlan || txq->vlan_en) {
3503 * VLAN insertion will be done inside by HW.
3504 * It is not utmost effective - VLAN flag is
3505 * checked twice, but we should proceed the
3506 * inlining length correctly and take into
3507 * account the VLAN header being inserted.
3509 return mlx5_tx_packet_multi_send
3512 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3515 * Now we know the minimal amount of data is requested
3516 * to inline. Check whether we should inline the buffers
3517 * from the chain beginning to eliminate some mbufs.
3520 nxlen = rte_pktmbuf_data_len(mbuf);
3521 if (unlikely(nxlen <= txq->inlen_send)) {
3522 /* We can inline first mbuf at least. */
3523 if (nxlen < inlen) {
3526 /* Scan mbufs till inlen filled. */
3531 nxlen = rte_pktmbuf_data_len(mbuf);
3533 } while (unlikely(nxlen < inlen));
3534 if (unlikely(nxlen > txq->inlen_send)) {
3535 /* We cannot inline entire mbuf. */
3536 smlen = inlen - smlen;
3537 start = rte_pktmbuf_mtod_offset
3538 (mbuf, uintptr_t, smlen);
3545 /* There should be not end of packet. */
3547 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3548 } while (unlikely(nxlen < txq->inlen_send));
3550 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3552 * Check whether we can do inline to align start
3553 * address of data buffer to cacheline.
3556 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3557 if (unlikely(start)) {
3559 if (start <= txq->inlen_send)
3564 * Check whether there are enough free WQEBBs:
3566 * - Ethernet Segment
3567 * - First Segment of inlined Ethernet data
3568 * - ... data continued ...
3569 * - Data Segments of pointer/min inline type
3571 * Estimate the number of Data Segments conservatively,
3572 * supposing no any mbufs is being freed during inlining.
3574 MLX5_ASSERT(inlen <= txq->inlen_send);
3575 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3576 MLX5_ESEG_MIN_INLINE_SIZE +
3578 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3579 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3580 return MLX5_TXCMP_CODE_EXIT;
3581 /* Check for maximal WQE size. */
3582 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3583 return MLX5_TXCMP_CODE_ERROR;
3584 #ifdef MLX5_PMD_SOFT_COUNTERS
3585 /* Update sent data bytes/packets counters. */
3586 txq->stats.obytes += dlen + vlan;
3588 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3589 loc->wqe_last = wqe;
3590 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3591 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3592 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3593 txq->wqe_ci += (ds + 3) / 4;
3594 loc->wqe_free -= (ds + 3) / 4;
3595 return MLX5_TXCMP_CODE_MULTI;
3599 * Tx burst function for multi-segment packets. Supports all
3600 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3601 * sends one packet per WQE. Function stops sending if it
3602 * encounters the single-segment packet.
3604 * This routine is responsible for storing processed mbuf
3605 * into elts ring buffer and update elts_head.
3608 * Pointer to TX queue structure.
3610 * Packets to transmit.
3612 * Number of packets in array.
3614 * Pointer to burst routine local context.
3616 * Configured Tx offloads mask. It is fully defined at
3617 * compile time and may be used for optimization.
3620 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3621 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3622 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3623 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3624 * Local context variables updated.
3626 static __rte_always_inline enum mlx5_txcmp_code
3627 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3628 struct rte_mbuf **__rte_restrict pkts,
3629 unsigned int pkts_n,
3630 struct mlx5_txq_local *__rte_restrict loc,
3633 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3634 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3635 pkts += loc->pkts_sent + 1;
3636 pkts_n -= loc->pkts_sent;
3638 enum mlx5_txcmp_code ret;
3640 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3642 * Estimate the number of free elts quickly but
3643 * conservatively. Some segment may be fully inlined
3644 * and freed, ignore this here - precise estimation
3647 if (loc->elts_free < NB_SEGS(loc->mbuf))
3648 return MLX5_TXCMP_CODE_EXIT;
3649 if (MLX5_TXOFF_CONFIG(TSO) &&
3650 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3651 /* Proceed with multi-segment TSO. */
3652 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3653 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3654 /* Proceed with multi-segment SEND with inlining. */
3655 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3657 /* Proceed with multi-segment SEND w/o inlining. */
3658 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3660 if (ret == MLX5_TXCMP_CODE_EXIT)
3661 return MLX5_TXCMP_CODE_EXIT;
3662 if (ret == MLX5_TXCMP_CODE_ERROR)
3663 return MLX5_TXCMP_CODE_ERROR;
3664 /* WQE is built, go to the next packet. */
3667 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3668 return MLX5_TXCMP_CODE_EXIT;
3669 loc->mbuf = *pkts++;
3671 rte_prefetch0(*pkts);
3672 if (likely(NB_SEGS(loc->mbuf) > 1))
3674 /* Here ends the series of multi-segment packets. */
3675 if (MLX5_TXOFF_CONFIG(TSO) &&
3676 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3677 return MLX5_TXCMP_CODE_TSO;
3678 return MLX5_TXCMP_CODE_SINGLE;
3684 * Tx burst function for single-segment packets with TSO.
3685 * Supports all types of Tx offloads, except multi-packets.
3686 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3687 * Function stops sending if it encounters the multi-segment
3688 * packet or packet without TSO requested.
3690 * The routine is responsible for storing processed mbuf
3691 * into elts ring buffer and update elts_head if inline
3692 * offloads is requested due to possible early freeing
3693 * of the inlined mbufs (can not store pkts array in elts
3697 * Pointer to TX queue structure.
3699 * Packets to transmit.
3701 * Number of packets in array.
3703 * Pointer to burst routine local context.
3705 * Configured Tx offloads mask. It is fully defined at
3706 * compile time and may be used for optimization.
3709 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3710 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3711 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3712 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3713 * Local context variables updated.
3715 static __rte_always_inline enum mlx5_txcmp_code
3716 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3717 struct rte_mbuf **__rte_restrict pkts,
3718 unsigned int pkts_n,
3719 struct mlx5_txq_local *__rte_restrict loc,
3722 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3723 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3724 pkts += loc->pkts_sent + 1;
3725 pkts_n -= loc->pkts_sent;
3727 struct mlx5_wqe_dseg *__rte_restrict dseg;
3728 struct mlx5_wqe *__rte_restrict wqe;
3729 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3732 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3733 dlen = rte_pktmbuf_data_len(loc->mbuf);
3734 if (MLX5_TXOFF_CONFIG(VLAN) &&
3735 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3736 vlan = sizeof(struct rte_vlan_hdr);
3739 * First calculate the WQE size to check
3740 * whether we have enough space in ring buffer.
3742 hlen = loc->mbuf->l2_len + vlan +
3743 loc->mbuf->l3_len + loc->mbuf->l4_len;
3744 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3745 return MLX5_TXCMP_CODE_ERROR;
3746 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3747 hlen += loc->mbuf->outer_l2_len +
3748 loc->mbuf->outer_l3_len;
3749 /* Segment must contain all TSO headers. */
3750 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3751 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3752 hlen > (dlen + vlan)))
3753 return MLX5_TXCMP_CODE_ERROR;
3755 * Check whether there are enough free WQEBBs:
3757 * - Ethernet Segment
3758 * - First Segment of inlined Ethernet data
3759 * - ... data continued ...
3760 * - Finishing Data Segment of pointer type
3762 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3763 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3764 if (loc->wqe_free < ((ds + 3) / 4))
3765 return MLX5_TXCMP_CODE_EXIT;
3766 #ifdef MLX5_PMD_SOFT_COUNTERS
3767 /* Update sent data bytes/packets counters. */
3768 ntcp = (dlen + vlan - hlen +
3769 loc->mbuf->tso_segsz - 1) /
3770 loc->mbuf->tso_segsz;
3772 * One will be added for mbuf itself at the end
3773 * of the mlx5_tx_burst from loc->pkts_sent field.
3776 txq->stats.opackets += ntcp;
3777 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3780 * Build the TSO WQE:
3782 * - Ethernet Segment with hlen bytes inlined
3783 * - Data Segment of pointer type
3785 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3786 loc->wqe_last = wqe;
3787 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3788 MLX5_OPCODE_TSO, olx);
3789 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3790 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3791 dlen -= hlen - vlan;
3792 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3794 * WQE is built, update the loop parameters
3795 * and go to the next packet.
3797 txq->wqe_ci += (ds + 3) / 4;
3798 loc->wqe_free -= (ds + 3) / 4;
3799 if (MLX5_TXOFF_CONFIG(INLINE))
3800 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3804 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3805 return MLX5_TXCMP_CODE_EXIT;
3806 loc->mbuf = *pkts++;
3808 rte_prefetch0(*pkts);
3809 if (MLX5_TXOFF_CONFIG(MULTI) &&
3810 unlikely(NB_SEGS(loc->mbuf) > 1))
3811 return MLX5_TXCMP_CODE_MULTI;
3812 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3813 return MLX5_TXCMP_CODE_SINGLE;
3814 /* Continue with the next TSO packet. */
3820 * Analyze the packet and select the best method to send.
3823 * Pointer to TX queue structure.
3825 * Pointer to burst routine local context.
3827 * Configured Tx offloads mask. It is fully defined at
3828 * compile time and may be used for optimization.
3830 * The predefined flag whether do complete check for
3831 * multi-segment packets and TSO.
3834 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3835 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3836 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3837 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3839 static __rte_always_inline enum mlx5_txcmp_code
3840 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3841 struct mlx5_txq_local *__rte_restrict loc,
3845 /* Check for multi-segment packet. */
3847 MLX5_TXOFF_CONFIG(MULTI) &&
3848 unlikely(NB_SEGS(loc->mbuf) > 1))
3849 return MLX5_TXCMP_CODE_MULTI;
3850 /* Check for TSO packet. */
3852 MLX5_TXOFF_CONFIG(TSO) &&
3853 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3854 return MLX5_TXCMP_CODE_TSO;
3855 /* Check if eMPW is enabled at all. */
3856 if (!MLX5_TXOFF_CONFIG(EMPW))
3857 return MLX5_TXCMP_CODE_SINGLE;
3858 /* Check if eMPW can be engaged. */
3859 if (MLX5_TXOFF_CONFIG(VLAN) &&
3860 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3861 (!MLX5_TXOFF_CONFIG(INLINE) ||
3862 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3863 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3865 * eMPW does not support VLAN insertion offload,
3866 * we have to inline the entire packet but
3867 * packet is too long for inlining.
3869 return MLX5_TXCMP_CODE_SINGLE;
3871 return MLX5_TXCMP_CODE_EMPW;
3875 * Check the next packet attributes to match with the eMPW batch ones.
3876 * In addition, for legacy MPW the packet length is checked either.
3879 * Pointer to TX queue structure.
3881 * Pointer to Ethernet Segment of eMPW batch.
3883 * Pointer to burst routine local context.
3885 * Length of previous packet in MPW descriptor.
3887 * Configured Tx offloads mask. It is fully defined at
3888 * compile time and may be used for optimization.
3891 * true - packet match with eMPW batch attributes.
3892 * false - no match, eMPW should be restarted.
3894 static __rte_always_inline bool
3895 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
3896 struct mlx5_wqe_eseg *__rte_restrict es,
3897 struct mlx5_txq_local *__rte_restrict loc,
3901 uint8_t swp_flags = 0;
3903 /* Compare the checksum flags, if any. */
3904 if (MLX5_TXOFF_CONFIG(CSUM) &&
3905 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3907 /* Compare the Software Parser offsets and flags. */
3908 if (MLX5_TXOFF_CONFIG(SWP) &&
3909 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3910 es->swp_flags != swp_flags))
3912 /* Fill metadata field if needed. */
3913 if (MLX5_TXOFF_CONFIG(METADATA) &&
3914 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3915 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3917 /* Legacy MPW can send packets with the same lengt only. */
3918 if (MLX5_TXOFF_CONFIG(MPW) &&
3919 dlen != rte_pktmbuf_data_len(loc->mbuf))
3921 /* There must be no VLAN packets in eMPW loop. */
3922 if (MLX5_TXOFF_CONFIG(VLAN))
3923 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3928 * Update send loop variables and WQE for eMPW loop
3929 * without data inlining. Number of Data Segments is
3930 * equal to the number of sent packets.
3933 * Pointer to TX queue structure.
3935 * Pointer to burst routine local context.
3937 * Number of packets/Data Segments/Packets.
3939 * Accumulated statistics, bytes sent
3941 * Configured Tx offloads mask. It is fully defined at
3942 * compile time and may be used for optimization.
3945 * true - packet match with eMPW batch attributes.
3946 * false - no match, eMPW should be restarted.
3948 static __rte_always_inline void
3949 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3950 struct mlx5_txq_local *__rte_restrict loc,
3953 unsigned int olx __rte_unused)
3955 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3956 #ifdef MLX5_PMD_SOFT_COUNTERS
3957 /* Update sent data bytes counter. */
3958 txq->stats.obytes += slen;
3962 loc->elts_free -= ds;
3963 loc->pkts_sent += ds;
3965 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3966 txq->wqe_ci += (ds + 3) / 4;
3967 loc->wqe_free -= (ds + 3) / 4;
3971 * Update send loop variables and WQE for eMPW loop
3972 * with data inlining. Gets the size of pushed descriptors
3973 * and data to the WQE.
3976 * Pointer to TX queue structure.
3978 * Pointer to burst routine local context.
3980 * Total size of descriptor/data in bytes.
3982 * Accumulated statistics, data bytes sent.
3984 * The base WQE for the eMPW/MPW descriptor.
3986 * Configured Tx offloads mask. It is fully defined at
3987 * compile time and may be used for optimization.
3990 * true - packet match with eMPW batch attributes.
3991 * false - no match, eMPW should be restarted.
3993 static __rte_always_inline void
3994 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
3995 struct mlx5_txq_local *__rte_restrict loc,
3998 struct mlx5_wqe *__rte_restrict wqem,
3999 unsigned int olx __rte_unused)
4001 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
4003 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4004 #ifdef MLX5_PMD_SOFT_COUNTERS
4005 /* Update sent data bytes counter. */
4006 txq->stats.obytes += slen;
4010 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
4012 * If the legacy MPW session contains the inline packets
4013 * we should set the only inline data segment length
4014 * and align the total length to the segment size.
4016 MLX5_ASSERT(len > sizeof(dseg->bcount));
4017 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
4018 MLX5_ETH_WQE_DATA_INLINE);
4019 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
4022 * The session is not legacy MPW or contains the
4023 * data buffer pointer segments.
4025 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
4026 len = len / MLX5_WSEG_SIZE + 2;
4028 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4029 txq->wqe_ci += (len + 3) / 4;
4030 loc->wqe_free -= (len + 3) / 4;
4031 loc->wqe_last = wqem;
4035 * The set of Tx burst functions for single-segment packets
4036 * without TSO and with Multi-Packet Writing feature support.
4037 * Supports all types of Tx offloads, except multi-packets
4040 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4041 * as many packet per WQE as it can. If eMPW is not configured
4042 * or packet can not be sent with eMPW (VLAN insertion) the
4043 * ordinary SEND opcode is used and only one packet placed
4046 * Functions stop sending if it encounters the multi-segment
4047 * packet or packet with TSO requested.
4049 * The routines are responsible for storing processed mbuf
4050 * into elts ring buffer and update elts_head if inlining
4051 * offload is requested. Otherwise the copying mbufs to elts
4052 * can be postponed and completed at the end of burst routine.
4055 * Pointer to TX queue structure.
4057 * Packets to transmit.
4059 * Number of packets in array.
4061 * Pointer to burst routine local context.
4063 * Configured Tx offloads mask. It is fully defined at
4064 * compile time and may be used for optimization.
4067 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4068 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4069 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4070 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4071 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4072 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4074 * Local context variables updated.
4077 * The routine sends packets with MLX5_OPCODE_EMPW
4078 * without inlining, this is dedicated optimized branch.
4079 * No VLAN insertion is supported.
4081 static __rte_always_inline enum mlx5_txcmp_code
4082 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4083 struct rte_mbuf **__rte_restrict pkts,
4084 unsigned int pkts_n,
4085 struct mlx5_txq_local *__rte_restrict loc,
4089 * Subroutine is the part of mlx5_tx_burst_single()
4090 * and sends single-segment packet with eMPW opcode
4091 * without data inlining.
4093 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4094 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4095 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4096 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4097 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4098 pkts += loc->pkts_sent + 1;
4099 pkts_n -= loc->pkts_sent;
4101 struct mlx5_wqe_dseg *__rte_restrict dseg;
4102 struct mlx5_wqe_eseg *__rte_restrict eseg;
4103 enum mlx5_txcmp_code ret;
4104 unsigned int part, loop;
4105 unsigned int slen = 0;
4108 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4109 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4110 MLX5_MPW_MAX_PACKETS :
4111 MLX5_EMPW_MAX_PACKETS);
4112 if (unlikely(loc->elts_free < part)) {
4113 /* We have no enough elts to save all mbufs. */
4114 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4115 return MLX5_TXCMP_CODE_EXIT;
4116 /* But we still able to send at least minimal eMPW. */
4117 part = loc->elts_free;
4119 /* Check whether we have enough WQEs */
4120 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4121 if (unlikely(loc->wqe_free <
4122 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4123 return MLX5_TXCMP_CODE_EXIT;
4124 part = (loc->wqe_free * 4) - 2;
4126 if (likely(part > 1))
4127 rte_prefetch0(*pkts);
4128 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4130 * Build eMPW title WQEBB:
4131 * - Control Segment, eMPW opcode
4132 * - Ethernet Segment, no inline
4134 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4135 MLX5_OPCODE_ENHANCED_MPSW, olx);
4136 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4137 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4138 eseg = &loc->wqe_last->eseg;
4139 dseg = &loc->wqe_last->dseg[0];
4141 /* Store the packet length for legacy MPW. */
4142 if (MLX5_TXOFF_CONFIG(MPW))
4143 eseg->mss = rte_cpu_to_be_16
4144 (rte_pktmbuf_data_len(loc->mbuf));
4146 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4147 #ifdef MLX5_PMD_SOFT_COUNTERS
4148 /* Update sent data bytes counter. */
4153 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4155 if (unlikely(--loop == 0))
4157 loc->mbuf = *pkts++;
4158 if (likely(loop > 1))
4159 rte_prefetch0(*pkts);
4160 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4162 * Unroll the completion code to avoid
4163 * returning variable value - it results in
4164 * unoptimized sequent checking in caller.
4166 if (ret == MLX5_TXCMP_CODE_MULTI) {
4168 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4169 if (unlikely(!loc->elts_free ||
4171 return MLX5_TXCMP_CODE_EXIT;
4172 return MLX5_TXCMP_CODE_MULTI;
4174 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4175 if (ret == MLX5_TXCMP_CODE_TSO) {
4177 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4178 if (unlikely(!loc->elts_free ||
4180 return MLX5_TXCMP_CODE_EXIT;
4181 return MLX5_TXCMP_CODE_TSO;
4183 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4185 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4186 if (unlikely(!loc->elts_free ||
4188 return MLX5_TXCMP_CODE_EXIT;
4189 return MLX5_TXCMP_CODE_SINGLE;
4191 if (ret != MLX5_TXCMP_CODE_EMPW) {
4194 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4195 return MLX5_TXCMP_CODE_ERROR;
4198 * Check whether packet parameters coincide
4199 * within assumed eMPW batch:
4200 * - check sum settings
4202 * - software parser settings
4203 * - packets length (legacy MPW only)
4205 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4208 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4209 if (unlikely(!loc->elts_free ||
4211 return MLX5_TXCMP_CODE_EXIT;
4215 /* Packet attributes match, continue the same eMPW. */
4217 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4218 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4220 /* eMPW is built successfully, update loop parameters. */
4222 MLX5_ASSERT(pkts_n >= part);
4223 #ifdef MLX5_PMD_SOFT_COUNTERS
4224 /* Update sent data bytes counter. */
4225 txq->stats.obytes += slen;
4227 loc->elts_free -= part;
4228 loc->pkts_sent += part;
4229 txq->wqe_ci += (2 + part + 3) / 4;
4230 loc->wqe_free -= (2 + part + 3) / 4;
4232 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4233 return MLX5_TXCMP_CODE_EXIT;
4234 loc->mbuf = *pkts++;
4235 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4236 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4238 /* Continue sending eMPW batches. */
4244 * The routine sends packets with MLX5_OPCODE_EMPW
4245 * with inlining, optionally supports VLAN insertion.
4247 static __rte_always_inline enum mlx5_txcmp_code
4248 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4249 struct rte_mbuf **__rte_restrict pkts,
4250 unsigned int pkts_n,
4251 struct mlx5_txq_local *__rte_restrict loc,
4255 * Subroutine is the part of mlx5_tx_burst_single()
4256 * and sends single-segment packet with eMPW opcode
4257 * with data inlining.
4259 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4260 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4261 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4262 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4263 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4264 pkts += loc->pkts_sent + 1;
4265 pkts_n -= loc->pkts_sent;
4267 struct mlx5_wqe_dseg *__rte_restrict dseg;
4268 struct mlx5_wqe *__rte_restrict wqem;
4269 enum mlx5_txcmp_code ret;
4270 unsigned int room, part, nlim;
4271 unsigned int slen = 0;
4273 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4275 * Limits the amount of packets in one WQE
4276 * to improve CQE latency generation.
4278 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4279 MLX5_MPW_INLINE_MAX_PACKETS :
4280 MLX5_EMPW_MAX_PACKETS);
4281 /* Check whether we have minimal amount WQEs */
4282 if (unlikely(loc->wqe_free <
4283 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4284 return MLX5_TXCMP_CODE_EXIT;
4285 if (likely(pkts_n > 1))
4286 rte_prefetch0(*pkts);
4287 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4289 * Build eMPW title WQEBB:
4290 * - Control Segment, eMPW opcode, zero DS
4291 * - Ethernet Segment, no inline
4293 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4294 MLX5_OPCODE_ENHANCED_MPSW, olx);
4295 mlx5_tx_eseg_none(txq, loc, wqem,
4296 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4297 dseg = &wqem->dseg[0];
4298 /* Store the packet length for legacy MPW. */
4299 if (MLX5_TXOFF_CONFIG(MPW))
4300 wqem->eseg.mss = rte_cpu_to_be_16
4301 (rte_pktmbuf_data_len(loc->mbuf));
4302 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4303 loc->wqe_free) * MLX5_WQE_SIZE -
4304 MLX5_WQE_CSEG_SIZE -
4306 /* Limit the room for legacy MPW sessions for performance. */
4307 if (MLX5_TXOFF_CONFIG(MPW))
4308 room = RTE_MIN(room,
4309 RTE_MAX(txq->inlen_empw +
4310 sizeof(dseg->bcount) +
4311 (MLX5_TXOFF_CONFIG(VLAN) ?
4312 sizeof(struct rte_vlan_hdr) : 0),
4313 MLX5_MPW_INLINE_MAX_PACKETS *
4314 MLX5_WQE_DSEG_SIZE));
4315 /* Build WQE till we have space, packets and resources. */
4318 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4319 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4322 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4323 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4324 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4326 * Some Tx offloads may cause an error if
4327 * packet is not long enough, check against
4328 * assumed minimal length.
4330 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4332 if (unlikely(!part))
4333 return MLX5_TXCMP_CODE_ERROR;
4335 * We have some successfully built
4336 * packet Data Segments to send.
4338 mlx5_tx_idone_empw(txq, loc, part,
4340 return MLX5_TXCMP_CODE_ERROR;
4342 /* Inline or not inline - that's the Question. */
4343 if (dlen > txq->inlen_empw ||
4344 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4346 if (MLX5_TXOFF_CONFIG(MPW)) {
4347 if (dlen > txq->inlen_send)
4351 /* Open new inline MPW session. */
4352 tlen += sizeof(dseg->bcount);
4353 dseg->bcount = RTE_BE32(0);
4355 (dseg, sizeof(dseg->bcount));
4358 * No pointer and inline descriptor
4359 * intermix for legacy MPW sessions.
4361 if (wqem->dseg[0].bcount)
4365 tlen = sizeof(dseg->bcount) + dlen;
4367 /* Inline entire packet, optional VLAN insertion. */
4368 if (MLX5_TXOFF_CONFIG(VLAN) &&
4369 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4371 * The packet length must be checked in
4372 * mlx5_tx_able_to_empw() and packet
4373 * fits into inline length guaranteed.
4376 sizeof(struct rte_vlan_hdr)) <=
4378 tlen += sizeof(struct rte_vlan_hdr);
4381 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4383 #ifdef MLX5_PMD_SOFT_COUNTERS
4384 /* Update sent data bytes counter. */
4385 slen += sizeof(struct rte_vlan_hdr);
4390 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4393 if (!MLX5_TXOFF_CONFIG(MPW))
4394 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4395 MLX5_ASSERT(room >= tlen);
4398 * Packet data are completely inlined,
4399 * free the packet immediately.
4401 rte_pktmbuf_free_seg(loc->mbuf);
4405 * No pointer and inline descriptor
4406 * intermix for legacy MPW sessions.
4408 if (MLX5_TXOFF_CONFIG(MPW) &&
4410 wqem->dseg[0].bcount == RTE_BE32(0))
4413 * Not inlinable VLAN packets are
4414 * proceeded outside of this routine.
4416 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4417 if (MLX5_TXOFF_CONFIG(VLAN))
4418 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4420 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4421 /* We have to store mbuf in elts.*/
4422 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4423 room -= MLX5_WQE_DSEG_SIZE;
4424 /* Ring buffer wraparound is checked at the loop end.*/
4427 #ifdef MLX5_PMD_SOFT_COUNTERS
4428 /* Update sent data bytes counter. */
4434 if (unlikely(!pkts_n || !loc->elts_free)) {
4436 * We have no resources/packets to
4437 * continue build descriptors.
4440 mlx5_tx_idone_empw(txq, loc, part,
4442 return MLX5_TXCMP_CODE_EXIT;
4444 loc->mbuf = *pkts++;
4445 if (likely(pkts_n > 1))
4446 rte_prefetch0(*pkts);
4447 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4449 * Unroll the completion code to avoid
4450 * returning variable value - it results in
4451 * unoptimized sequent checking in caller.
4453 if (ret == MLX5_TXCMP_CODE_MULTI) {
4455 mlx5_tx_idone_empw(txq, loc, part,
4457 if (unlikely(!loc->elts_free ||
4459 return MLX5_TXCMP_CODE_EXIT;
4460 return MLX5_TXCMP_CODE_MULTI;
4462 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4463 if (ret == MLX5_TXCMP_CODE_TSO) {
4465 mlx5_tx_idone_empw(txq, loc, part,
4467 if (unlikely(!loc->elts_free ||
4469 return MLX5_TXCMP_CODE_EXIT;
4470 return MLX5_TXCMP_CODE_TSO;
4472 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4474 mlx5_tx_idone_empw(txq, loc, part,
4476 if (unlikely(!loc->elts_free ||
4478 return MLX5_TXCMP_CODE_EXIT;
4479 return MLX5_TXCMP_CODE_SINGLE;
4481 if (ret != MLX5_TXCMP_CODE_EMPW) {
4484 mlx5_tx_idone_empw(txq, loc, part,
4486 return MLX5_TXCMP_CODE_ERROR;
4488 /* Check if we have minimal room left. */
4490 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4493 * Check whether packet parameters coincide
4494 * within assumed eMPW batch:
4495 * - check sum settings
4497 * - software parser settings
4498 * - packets length (legacy MPW only)
4500 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4503 /* Packet attributes match, continue the same eMPW. */
4504 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4505 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4508 * We get here to close an existing eMPW
4509 * session and start the new one.
4511 MLX5_ASSERT(pkts_n);
4513 if (unlikely(!part))
4514 return MLX5_TXCMP_CODE_EXIT;
4515 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4516 if (unlikely(!loc->elts_free ||
4518 return MLX5_TXCMP_CODE_EXIT;
4519 /* Continue the loop with new eMPW session. */
4525 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4526 * Data inlining and VLAN insertion are supported.
4528 static __rte_always_inline enum mlx5_txcmp_code
4529 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4530 struct rte_mbuf **__rte_restrict pkts,
4531 unsigned int pkts_n,
4532 struct mlx5_txq_local *__rte_restrict loc,
4536 * Subroutine is the part of mlx5_tx_burst_single()
4537 * and sends single-segment packet with SEND opcode.
4539 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4540 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4541 pkts += loc->pkts_sent + 1;
4542 pkts_n -= loc->pkts_sent;
4544 struct mlx5_wqe *__rte_restrict wqe;
4545 enum mlx5_txcmp_code ret;
4547 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4548 if (MLX5_TXOFF_CONFIG(INLINE)) {
4549 unsigned int inlen, vlan = 0;
4551 inlen = rte_pktmbuf_data_len(loc->mbuf);
4552 if (MLX5_TXOFF_CONFIG(VLAN) &&
4553 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4554 vlan = sizeof(struct rte_vlan_hdr);
4556 static_assert((sizeof(struct rte_vlan_hdr) +
4557 sizeof(struct rte_ether_hdr)) ==
4558 MLX5_ESEG_MIN_INLINE_SIZE,
4559 "invalid min inline data size");
4562 * If inlining is enabled at configuration time
4563 * the limit must be not less than minimal size.
4564 * Otherwise we would do extra check for data
4565 * size to avoid crashes due to length overflow.
4567 MLX5_ASSERT(txq->inlen_send >=
4568 MLX5_ESEG_MIN_INLINE_SIZE);
4569 if (inlen <= txq->inlen_send) {
4570 unsigned int seg_n, wqe_n;
4572 rte_prefetch0(rte_pktmbuf_mtod
4573 (loc->mbuf, uint8_t *));
4574 /* Check against minimal length. */
4575 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4576 return MLX5_TXCMP_CODE_ERROR;
4577 if (loc->mbuf->ol_flags &
4578 PKT_TX_DYNF_NOINLINE) {
4580 * The hint flag not to inline packet
4581 * data is set. Check whether we can
4584 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4586 (MLX5_TXOFF_CONFIG(MPW) &&
4589 * The hardware requires the
4590 * minimal inline data header.
4592 goto single_min_inline;
4594 if (MLX5_TXOFF_CONFIG(VLAN) &&
4595 vlan && !txq->vlan_en) {
4597 * We must insert VLAN tag
4598 * by software means.
4600 goto single_part_inline;
4602 goto single_no_inline;
4605 * Completely inlined packet data WQE:
4606 * - Control Segment, SEND opcode
4607 * - Ethernet Segment, no VLAN insertion
4608 * - Data inlined, VLAN optionally inserted
4609 * - Alignment to MLX5_WSEG_SIZE
4610 * Have to estimate amount of WQEBBs
4612 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4613 MLX5_ESEG_MIN_INLINE_SIZE +
4614 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4615 /* Check if there are enough WQEBBs. */
4616 wqe_n = (seg_n + 3) / 4;
4617 if (wqe_n > loc->wqe_free)
4618 return MLX5_TXCMP_CODE_EXIT;
4619 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4620 loc->wqe_last = wqe;
4621 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4622 MLX5_OPCODE_SEND, olx);
4623 mlx5_tx_eseg_data(txq, loc, wqe,
4624 vlan, inlen, 0, olx);
4625 txq->wqe_ci += wqe_n;
4626 loc->wqe_free -= wqe_n;
4628 * Packet data are completely inlined,
4629 * free the packet immediately.
4631 rte_pktmbuf_free_seg(loc->mbuf);
4632 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4633 MLX5_TXOFF_CONFIG(MPW)) &&
4636 * If minimal inlining is requested the eMPW
4637 * feature should be disabled due to data is
4638 * inlined into Ethernet Segment, which can
4639 * not contain inlined data for eMPW due to
4640 * segment shared for all packets.
4642 struct mlx5_wqe_dseg *__rte_restrict dseg;
4647 * The inline-mode settings require
4648 * to inline the specified amount of
4649 * data bytes to the Ethernet Segment.
4650 * We should check the free space in
4651 * WQE ring buffer to inline partially.
4654 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4655 MLX5_ASSERT(inlen > txq->inlen_mode);
4656 MLX5_ASSERT(txq->inlen_mode >=
4657 MLX5_ESEG_MIN_INLINE_SIZE);
4659 * Check whether there are enough free WQEBBs:
4661 * - Ethernet Segment
4662 * - First Segment of inlined Ethernet data
4663 * - ... data continued ...
4664 * - Finishing Data Segment of pointer type
4666 ds = (MLX5_WQE_CSEG_SIZE +
4667 MLX5_WQE_ESEG_SIZE +
4668 MLX5_WQE_DSEG_SIZE +
4670 MLX5_ESEG_MIN_INLINE_SIZE +
4671 MLX5_WQE_DSEG_SIZE +
4672 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4673 if (loc->wqe_free < ((ds + 3) / 4))
4674 return MLX5_TXCMP_CODE_EXIT;
4676 * Build the ordinary SEND WQE:
4678 * - Ethernet Segment, inline inlen_mode bytes
4679 * - Data Segment of pointer type
4681 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4682 loc->wqe_last = wqe;
4683 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4684 MLX5_OPCODE_SEND, olx);
4685 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4688 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4689 txq->inlen_mode - vlan;
4690 inlen -= txq->inlen_mode;
4691 mlx5_tx_dseg_ptr(txq, loc, dseg,
4694 * WQE is built, update the loop parameters
4695 * and got to the next packet.
4697 txq->wqe_ci += (ds + 3) / 4;
4698 loc->wqe_free -= (ds + 3) / 4;
4699 /* We have to store mbuf in elts.*/
4700 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4701 txq->elts[txq->elts_head++ & txq->elts_m] =
4709 * Partially inlined packet data WQE, we have
4710 * some space in title WQEBB, we can fill it
4711 * with some packet data. It takes one WQEBB,
4712 * it is available, no extra space check:
4713 * - Control Segment, SEND opcode
4714 * - Ethernet Segment, no VLAN insertion
4715 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4716 * - Data Segment, pointer type
4718 * We also get here if VLAN insertion is not
4719 * supported by HW, the inline is enabled.
4722 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4723 loc->wqe_last = wqe;
4724 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4725 MLX5_OPCODE_SEND, olx);
4726 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4727 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4728 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4730 * The length check is performed above, by
4731 * comparing with txq->inlen_send. We should
4732 * not get overflow here.
4734 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4735 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4736 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4740 /* We have to store mbuf in elts.*/
4741 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4742 txq->elts[txq->elts_head++ & txq->elts_m] =
4746 #ifdef MLX5_PMD_SOFT_COUNTERS
4747 /* Update sent data bytes counter. */
4748 txq->stats.obytes += vlan +
4749 rte_pktmbuf_data_len(loc->mbuf);
4753 * No inline at all, it means the CPU cycles saving
4754 * is prioritized at configuration, we should not
4755 * copy any packet data to WQE.
4757 * SEND WQE, one WQEBB:
4758 * - Control Segment, SEND opcode
4759 * - Ethernet Segment, optional VLAN, no inline
4760 * - Data Segment, pointer type
4763 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4764 loc->wqe_last = wqe;
4765 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4766 MLX5_OPCODE_SEND, olx);
4767 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4769 (txq, loc, &wqe->dseg[0],
4770 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4771 rte_pktmbuf_data_len(loc->mbuf), olx);
4775 * We should not store mbuf pointer in elts
4776 * if no inlining is configured, this is done
4777 * by calling routine in a batch copy.
4779 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4781 #ifdef MLX5_PMD_SOFT_COUNTERS
4782 /* Update sent data bytes counter. */
4783 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4784 if (MLX5_TXOFF_CONFIG(VLAN) &&
4785 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4786 txq->stats.obytes +=
4787 sizeof(struct rte_vlan_hdr);
4792 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4793 return MLX5_TXCMP_CODE_EXIT;
4794 loc->mbuf = *pkts++;
4796 rte_prefetch0(*pkts);
4797 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4798 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4804 static __rte_always_inline enum mlx5_txcmp_code
4805 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4806 struct rte_mbuf **__rte_restrict pkts,
4807 unsigned int pkts_n,
4808 struct mlx5_txq_local *__rte_restrict loc,
4811 enum mlx5_txcmp_code ret;
4813 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4814 if (ret == MLX5_TXCMP_CODE_SINGLE)
4816 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4818 /* Optimize for inline/no inline eMPW send. */
4819 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4820 mlx5_tx_burst_empw_inline
4821 (txq, pkts, pkts_n, loc, olx) :
4822 mlx5_tx_burst_empw_simple
4823 (txq, pkts, pkts_n, loc, olx);
4824 if (ret != MLX5_TXCMP_CODE_SINGLE)
4826 /* The resources to send one packet should remain. */
4827 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4829 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4830 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4831 if (ret != MLX5_TXCMP_CODE_EMPW)
4833 /* The resources to send one packet should remain. */
4834 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4839 * DPDK Tx callback template. This is configured template
4840 * used to generate routines optimized for specified offload setup.
4841 * One of this generated functions is chosen at SQ configuration
4845 * Generic pointer to TX queue structure.
4847 * Packets to transmit.
4849 * Number of packets in array.
4851 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4852 * values. Should be static to take compile time static configuration
4856 * Number of packets successfully transmitted (<= pkts_n).
4858 static __rte_always_inline uint16_t
4859 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4860 struct rte_mbuf **__rte_restrict pkts,
4864 struct mlx5_txq_local loc;
4865 enum mlx5_txcmp_code ret;
4868 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4869 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4870 if (unlikely(!pkts_n))
4874 loc.wqe_last = NULL;
4877 loc.pkts_loop = loc.pkts_sent;
4879 * Check if there are some CQEs, if any:
4880 * - process an encountered errors
4881 * - process the completed WQEs
4882 * - free related mbufs
4883 * - doorbell the NIC about processed CQEs
4885 rte_prefetch0(*(pkts + loc.pkts_sent));
4886 mlx5_tx_handle_completion(txq, olx);
4888 * Calculate the number of available resources - elts and WQEs.
4889 * There are two possible different scenarios:
4890 * - no data inlining into WQEs, one WQEBB may contains up to
4891 * four packets, in this case elts become scarce resource
4892 * - data inlining into WQEs, one packet may require multiple
4893 * WQEBBs, the WQEs become the limiting factor.
4895 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4896 loc.elts_free = txq->elts_s -
4897 (uint16_t)(txq->elts_head - txq->elts_tail);
4898 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4899 loc.wqe_free = txq->wqe_s -
4900 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4901 if (unlikely(!loc.elts_free || !loc.wqe_free))
4905 * Fetch the packet from array. Usually this is
4906 * the first packet in series of multi/single
4909 loc.mbuf = *(pkts + loc.pkts_sent);
4910 /* Dedicated branch for multi-segment packets. */
4911 if (MLX5_TXOFF_CONFIG(MULTI) &&
4912 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4914 * Multi-segment packet encountered.
4915 * Hardware is able to process it only
4916 * with SEND/TSO opcodes, one packet
4917 * per WQE, do it in dedicated routine.
4920 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4921 part = loc.pkts_sent - loc.pkts_copy;
4922 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4924 * There are some single-segment mbufs not
4925 * stored in elts. The mbufs must be in the
4926 * same order as WQEs, so we must copy the
4927 * mbufs to elts here, before the coming
4928 * multi-segment packet mbufs is appended.
4930 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4932 loc.pkts_copy = loc.pkts_sent;
4934 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4935 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4936 if (!MLX5_TXOFF_CONFIG(INLINE))
4937 loc.pkts_copy = loc.pkts_sent;
4939 * These returned code checks are supposed
4940 * to be optimized out due to routine inlining.
4942 if (ret == MLX5_TXCMP_CODE_EXIT) {
4944 * The routine returns this code when
4945 * all packets are sent or there is no
4946 * enough resources to complete request.
4950 if (ret == MLX5_TXCMP_CODE_ERROR) {
4952 * The routine returns this code when
4953 * some error in the incoming packets
4956 txq->stats.oerrors++;
4959 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4961 * The single-segment packet was encountered
4962 * in the array, try to send it with the
4963 * best optimized way, possible engaging eMPW.
4965 goto enter_send_single;
4967 if (MLX5_TXOFF_CONFIG(TSO) &&
4968 ret == MLX5_TXCMP_CODE_TSO) {
4970 * The single-segment TSO packet was
4971 * encountered in the array.
4973 goto enter_send_tso;
4975 /* We must not get here. Something is going wrong. */
4977 txq->stats.oerrors++;
4980 /* Dedicated branch for single-segment TSO packets. */
4981 if (MLX5_TXOFF_CONFIG(TSO) &&
4982 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4984 * TSO might require special way for inlining
4985 * (dedicated parameters) and is sent with
4986 * MLX5_OPCODE_TSO opcode only, provide this
4987 * in dedicated branch.
4990 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4991 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4992 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4994 * These returned code checks are supposed
4995 * to be optimized out due to routine inlining.
4997 if (ret == MLX5_TXCMP_CODE_EXIT)
4999 if (ret == MLX5_TXCMP_CODE_ERROR) {
5000 txq->stats.oerrors++;
5003 if (ret == MLX5_TXCMP_CODE_SINGLE)
5004 goto enter_send_single;
5005 if (MLX5_TXOFF_CONFIG(MULTI) &&
5006 ret == MLX5_TXCMP_CODE_MULTI) {
5008 * The multi-segment packet was
5009 * encountered in the array.
5011 goto enter_send_multi;
5013 /* We must not get here. Something is going wrong. */
5015 txq->stats.oerrors++;
5019 * The dedicated branch for the single-segment packets
5020 * without TSO. Often these ones can be sent using
5021 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5022 * The routine builds the WQEs till it encounters
5023 * the TSO or multi-segment packet (in case if these
5024 * offloads are requested at SQ configuration time).
5027 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5028 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5030 * These returned code checks are supposed
5031 * to be optimized out due to routine inlining.
5033 if (ret == MLX5_TXCMP_CODE_EXIT)
5035 if (ret == MLX5_TXCMP_CODE_ERROR) {
5036 txq->stats.oerrors++;
5039 if (MLX5_TXOFF_CONFIG(MULTI) &&
5040 ret == MLX5_TXCMP_CODE_MULTI) {
5042 * The multi-segment packet was
5043 * encountered in the array.
5045 goto enter_send_multi;
5047 if (MLX5_TXOFF_CONFIG(TSO) &&
5048 ret == MLX5_TXCMP_CODE_TSO) {
5050 * The single-segment TSO packet was
5051 * encountered in the array.
5053 goto enter_send_tso;
5055 /* We must not get here. Something is going wrong. */
5057 txq->stats.oerrors++;
5061 * Main Tx loop is completed, do the rest:
5062 * - set completion request if thresholds are reached
5063 * - doorbell the hardware
5064 * - copy the rest of mbufs to elts (if any)
5066 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5067 loc.pkts_sent >= loc.pkts_copy);
5068 /* Take a shortcut if nothing is sent. */
5069 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5071 /* Request CQE generation if limits are reached. */
5072 mlx5_tx_request_completion(txq, &loc, olx);
5074 * Ring QP doorbell immediately after WQE building completion
5075 * to improve latencies. The pure software related data treatment
5076 * can be completed after doorbell. Tx CQEs for this SQ are
5077 * processed in this thread only by the polling.
5079 * The rdma core library can map doorbell register in two ways,
5080 * depending on the environment variable "MLX5_SHUT_UP_BF":
5082 * - as regular cached memory, the variable is either missing or
5083 * set to zero. This type of mapping may cause the significant
5084 * doorbell register writing latency and requires explicit
5085 * memory write barrier to mitigate this issue and prevent
5088 * - as non-cached memory, the variable is present and set to
5089 * not "0" value. This type of mapping may cause performance
5090 * impact under heavy loading conditions but the explicit write
5091 * memory barrier is not required and it may improve core
5094 * - the legacy behaviour (prior 19.08 release) was to use some
5095 * heuristics to decide whether write memory barrier should
5096 * be performed. This behavior is supported with specifying
5097 * tx_db_nc=2, write barrier is skipped if application
5098 * provides the full recommended burst of packets, it
5099 * supposes the next packets are coming and the write barrier
5100 * will be issued on the next burst (after descriptor writing,
5103 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5104 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5105 /* Not all of the mbufs may be stored into elts yet. */
5106 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5107 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5109 * There are some single-segment mbufs not stored in elts.
5110 * It can be only if the last packet was single-segment.
5111 * The copying is gathered into one place due to it is
5112 * a good opportunity to optimize that with SIMD.
5113 * Unfortunately if inlining is enabled the gaps in
5114 * pointer array may happen due to early freeing of the
5117 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5118 loc.pkts_copy = loc.pkts_sent;
5120 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5121 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5122 if (pkts_n > loc.pkts_sent) {
5124 * If burst size is large there might be no enough CQE
5125 * fetched from completion queue and no enough resources
5126 * freed to send all the packets.
5131 #ifdef MLX5_PMD_SOFT_COUNTERS
5132 /* Increment sent packets counter. */
5133 txq->stats.opackets += loc.pkts_sent;
5135 return loc.pkts_sent;
5138 /* Generate routines with Enhanced Multi-Packet Write support. */
5139 MLX5_TXOFF_DECL(full_empw,
5140 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5142 MLX5_TXOFF_DECL(none_empw,
5143 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5145 MLX5_TXOFF_DECL(md_empw,
5146 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5148 MLX5_TXOFF_DECL(mt_empw,
5149 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5150 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5152 MLX5_TXOFF_DECL(mtsc_empw,
5153 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5154 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5155 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5157 MLX5_TXOFF_DECL(mti_empw,
5158 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5159 MLX5_TXOFF_CONFIG_INLINE |
5160 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5162 MLX5_TXOFF_DECL(mtv_empw,
5163 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5164 MLX5_TXOFF_CONFIG_VLAN |
5165 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5167 MLX5_TXOFF_DECL(mtiv_empw,
5168 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5169 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5170 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5172 MLX5_TXOFF_DECL(sc_empw,
5173 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5174 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5176 MLX5_TXOFF_DECL(sci_empw,
5177 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5178 MLX5_TXOFF_CONFIG_INLINE |
5179 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5181 MLX5_TXOFF_DECL(scv_empw,
5182 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5183 MLX5_TXOFF_CONFIG_VLAN |
5184 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5186 MLX5_TXOFF_DECL(sciv_empw,
5187 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5188 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5189 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5191 MLX5_TXOFF_DECL(i_empw,
5192 MLX5_TXOFF_CONFIG_INLINE |
5193 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5195 MLX5_TXOFF_DECL(v_empw,
5196 MLX5_TXOFF_CONFIG_VLAN |
5197 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5199 MLX5_TXOFF_DECL(iv_empw,
5200 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5201 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5203 /* Generate routines without Enhanced Multi-Packet Write support. */
5204 MLX5_TXOFF_DECL(full,
5205 MLX5_TXOFF_CONFIG_FULL)
5207 MLX5_TXOFF_DECL(none,
5208 MLX5_TXOFF_CONFIG_NONE)
5211 MLX5_TXOFF_CONFIG_METADATA)
5214 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5215 MLX5_TXOFF_CONFIG_METADATA)
5217 MLX5_TXOFF_DECL(mtsc,
5218 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5219 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5220 MLX5_TXOFF_CONFIG_METADATA)
5222 MLX5_TXOFF_DECL(mti,
5223 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5224 MLX5_TXOFF_CONFIG_INLINE |
5225 MLX5_TXOFF_CONFIG_METADATA)
5228 MLX5_TXOFF_DECL(mtv,
5229 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5230 MLX5_TXOFF_CONFIG_VLAN |
5231 MLX5_TXOFF_CONFIG_METADATA)
5234 MLX5_TXOFF_DECL(mtiv,
5235 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5236 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5237 MLX5_TXOFF_CONFIG_METADATA)
5240 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5241 MLX5_TXOFF_CONFIG_METADATA)
5243 MLX5_TXOFF_DECL(sci,
5244 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5245 MLX5_TXOFF_CONFIG_INLINE |
5246 MLX5_TXOFF_CONFIG_METADATA)
5249 MLX5_TXOFF_DECL(scv,
5250 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_VLAN |
5252 MLX5_TXOFF_CONFIG_METADATA)
5255 MLX5_TXOFF_DECL(sciv,
5256 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5257 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5258 MLX5_TXOFF_CONFIG_METADATA)
5261 MLX5_TXOFF_CONFIG_INLINE |
5262 MLX5_TXOFF_CONFIG_METADATA)
5265 MLX5_TXOFF_CONFIG_VLAN |
5266 MLX5_TXOFF_CONFIG_METADATA)
5269 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5270 MLX5_TXOFF_CONFIG_METADATA)
5272 /* Generate routines with timestamp scheduling. */
5273 MLX5_TXOFF_DECL(full_ts_nompw,
5274 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5276 MLX5_TXOFF_DECL(full_ts_nompwi,
5277 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5278 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5279 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5280 MLX5_TXOFF_CONFIG_TXPP)
5282 MLX5_TXOFF_DECL(full_ts,
5283 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5284 MLX5_TXOFF_CONFIG_EMPW)
5286 MLX5_TXOFF_DECL(full_ts_noi,
5287 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5288 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5289 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5290 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5292 MLX5_TXOFF_DECL(none_ts,
5293 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5294 MLX5_TXOFF_CONFIG_EMPW)
5296 MLX5_TXOFF_DECL(mdi_ts,
5297 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5298 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5300 MLX5_TXOFF_DECL(mti_ts,
5301 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5302 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5303 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5305 MLX5_TXOFF_DECL(mtiv_ts,
5306 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5307 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5308 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5309 MLX5_TXOFF_CONFIG_EMPW)
5312 * Generate routines with Legacy Multi-Packet Write support.
5313 * This mode is supported by ConnectX-4 Lx only and imposes
5314 * offload limitations, not supported:
5315 * - ACL/Flows (metadata are becoming meaningless)
5316 * - WQE Inline headers
5317 * - SRIOV (E-Switch offloads)
5319 * - tunnel encapsulation/decapsulation
5322 MLX5_TXOFF_DECL(none_mpw,
5323 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5324 MLX5_TXOFF_CONFIG_MPW)
5326 MLX5_TXOFF_DECL(mci_mpw,
5327 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5328 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5329 MLX5_TXOFF_CONFIG_MPW)
5331 MLX5_TXOFF_DECL(mc_mpw,
5332 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5333 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5335 MLX5_TXOFF_DECL(i_mpw,
5336 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5337 MLX5_TXOFF_CONFIG_MPW)
5340 * Array of declared and compiled Tx burst function and corresponding
5341 * supported offloads set. The array is used to select the Tx burst
5342 * function for specified offloads set at Tx queue configuration time.
5345 eth_tx_burst_t func;
5348 MLX5_TXOFF_INFO(full_empw,
5349 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5350 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5351 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5352 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5354 MLX5_TXOFF_INFO(none_empw,
5355 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5357 MLX5_TXOFF_INFO(md_empw,
5358 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5360 MLX5_TXOFF_INFO(mt_empw,
5361 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5362 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5364 MLX5_TXOFF_INFO(mtsc_empw,
5365 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5366 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5367 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5369 MLX5_TXOFF_INFO(mti_empw,
5370 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5371 MLX5_TXOFF_CONFIG_INLINE |
5372 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5374 MLX5_TXOFF_INFO(mtv_empw,
5375 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5376 MLX5_TXOFF_CONFIG_VLAN |
5377 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5379 MLX5_TXOFF_INFO(mtiv_empw,
5380 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5381 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5382 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5384 MLX5_TXOFF_INFO(sc_empw,
5385 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5386 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5388 MLX5_TXOFF_INFO(sci_empw,
5389 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5390 MLX5_TXOFF_CONFIG_INLINE |
5391 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5393 MLX5_TXOFF_INFO(scv_empw,
5394 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5395 MLX5_TXOFF_CONFIG_VLAN |
5396 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5398 MLX5_TXOFF_INFO(sciv_empw,
5399 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5400 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5401 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5403 MLX5_TXOFF_INFO(i_empw,
5404 MLX5_TXOFF_CONFIG_INLINE |
5405 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5407 MLX5_TXOFF_INFO(v_empw,
5408 MLX5_TXOFF_CONFIG_VLAN |
5409 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5411 MLX5_TXOFF_INFO(iv_empw,
5412 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5413 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5415 MLX5_TXOFF_INFO(full_ts_nompw,
5416 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5418 MLX5_TXOFF_INFO(full_ts_nompwi,
5419 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5420 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5421 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5422 MLX5_TXOFF_CONFIG_TXPP)
5424 MLX5_TXOFF_INFO(full_ts,
5425 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5426 MLX5_TXOFF_CONFIG_EMPW)
5428 MLX5_TXOFF_INFO(full_ts_noi,
5429 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5430 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5431 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5432 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5434 MLX5_TXOFF_INFO(none_ts,
5435 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5436 MLX5_TXOFF_CONFIG_EMPW)
5438 MLX5_TXOFF_INFO(mdi_ts,
5439 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5440 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5442 MLX5_TXOFF_INFO(mti_ts,
5443 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5444 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5445 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5447 MLX5_TXOFF_INFO(mtiv_ts,
5448 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5449 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5450 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5451 MLX5_TXOFF_CONFIG_EMPW)
5453 MLX5_TXOFF_INFO(full,
5454 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5455 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5456 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5457 MLX5_TXOFF_CONFIG_METADATA)
5459 MLX5_TXOFF_INFO(none,
5460 MLX5_TXOFF_CONFIG_NONE)
5463 MLX5_TXOFF_CONFIG_METADATA)
5466 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5467 MLX5_TXOFF_CONFIG_METADATA)
5469 MLX5_TXOFF_INFO(mtsc,
5470 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5471 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5472 MLX5_TXOFF_CONFIG_METADATA)
5474 MLX5_TXOFF_INFO(mti,
5475 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5476 MLX5_TXOFF_CONFIG_INLINE |
5477 MLX5_TXOFF_CONFIG_METADATA)
5479 MLX5_TXOFF_INFO(mtv,
5480 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5481 MLX5_TXOFF_CONFIG_VLAN |
5482 MLX5_TXOFF_CONFIG_METADATA)
5484 MLX5_TXOFF_INFO(mtiv,
5485 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5486 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5487 MLX5_TXOFF_CONFIG_METADATA)
5490 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5491 MLX5_TXOFF_CONFIG_METADATA)
5493 MLX5_TXOFF_INFO(sci,
5494 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5495 MLX5_TXOFF_CONFIG_INLINE |
5496 MLX5_TXOFF_CONFIG_METADATA)
5498 MLX5_TXOFF_INFO(scv,
5499 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5500 MLX5_TXOFF_CONFIG_VLAN |
5501 MLX5_TXOFF_CONFIG_METADATA)
5503 MLX5_TXOFF_INFO(sciv,
5504 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5505 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5506 MLX5_TXOFF_CONFIG_METADATA)
5509 MLX5_TXOFF_CONFIG_INLINE |
5510 MLX5_TXOFF_CONFIG_METADATA)
5513 MLX5_TXOFF_CONFIG_VLAN |
5514 MLX5_TXOFF_CONFIG_METADATA)
5517 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5518 MLX5_TXOFF_CONFIG_METADATA)
5520 MLX5_TXOFF_INFO(none_mpw,
5521 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5522 MLX5_TXOFF_CONFIG_MPW)
5524 MLX5_TXOFF_INFO(mci_mpw,
5525 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5526 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5527 MLX5_TXOFF_CONFIG_MPW)
5529 MLX5_TXOFF_INFO(mc_mpw,
5530 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5531 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5533 MLX5_TXOFF_INFO(i_mpw,
5534 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5535 MLX5_TXOFF_CONFIG_MPW)
5539 * Configure the Tx function to use. The routine checks configured
5540 * Tx offloads for the device and selects appropriate Tx burst
5541 * routine. There are multiple Tx burst routines compiled from
5542 * the same template in the most optimal way for the dedicated
5546 * Pointer to private data structure.
5549 * Pointer to selected Tx burst function.
5552 mlx5_select_tx_function(struct rte_eth_dev *dev)
5554 struct mlx5_priv *priv = dev->data->dev_private;
5555 struct mlx5_dev_config *config = &priv->config;
5556 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5557 unsigned int diff = 0, olx = 0, i, m;
5559 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5560 MLX5_DSEG_MAX, "invalid WQE max size");
5561 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5562 "invalid WQE Control Segment size");
5563 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5564 "invalid WQE Ethernet Segment size");
5565 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5566 "invalid WQE Data Segment size");
5567 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5568 "invalid WQE size");
5570 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5571 /* We should support Multi-Segment Packets. */
5572 olx |= MLX5_TXOFF_CONFIG_MULTI;
5574 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5575 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5576 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5577 DEV_TX_OFFLOAD_IP_TNL_TSO |
5578 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5579 /* We should support TCP Send Offload. */
5580 olx |= MLX5_TXOFF_CONFIG_TSO;
5582 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5583 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5584 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5585 /* We should support Software Parser for Tunnels. */
5586 olx |= MLX5_TXOFF_CONFIG_SWP;
5588 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5589 DEV_TX_OFFLOAD_UDP_CKSUM |
5590 DEV_TX_OFFLOAD_TCP_CKSUM |
5591 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5592 /* We should support IP/TCP/UDP Checksums. */
5593 olx |= MLX5_TXOFF_CONFIG_CSUM;
5595 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5596 /* We should support VLAN insertion. */
5597 olx |= MLX5_TXOFF_CONFIG_VLAN;
5599 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5600 rte_mbuf_dynflag_lookup
5601 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) > 0 &&
5602 rte_mbuf_dynfield_lookup
5603 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) > 0) {
5604 /* Offload configured, dynamic entities registered. */
5605 olx |= MLX5_TXOFF_CONFIG_TXPP;
5607 if (priv->txqs_n && (*priv->txqs)[0]) {
5608 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5610 if (txd->inlen_send) {
5612 * Check the data inline requirements. Data inline
5613 * is enabled on per device basis, we can check
5614 * the first Tx queue only.
5616 * If device does not support VLAN insertion in WQE
5617 * and some queues are requested to perform VLAN
5618 * insertion offload than inline must be enabled.
5620 olx |= MLX5_TXOFF_CONFIG_INLINE;
5623 if (config->mps == MLX5_MPW_ENHANCED &&
5624 config->txq_inline_min <= 0) {
5626 * The NIC supports Enhanced Multi-Packet Write
5627 * and does not require minimal inline data.
5629 olx |= MLX5_TXOFF_CONFIG_EMPW;
5631 if (rte_flow_dynf_metadata_avail()) {
5632 /* We should support Flow metadata. */
5633 olx |= MLX5_TXOFF_CONFIG_METADATA;
5635 if (config->mps == MLX5_MPW) {
5637 * The NIC supports Legacy Multi-Packet Write.
5638 * The MLX5_TXOFF_CONFIG_MPW controls the
5639 * descriptor building method in combination
5640 * with MLX5_TXOFF_CONFIG_EMPW.
5642 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5643 MLX5_TXOFF_CONFIG_SWP |
5644 MLX5_TXOFF_CONFIG_VLAN |
5645 MLX5_TXOFF_CONFIG_METADATA)))
5646 olx |= MLX5_TXOFF_CONFIG_EMPW |
5647 MLX5_TXOFF_CONFIG_MPW;
5650 * Scan the routines table to find the minimal
5651 * satisfying routine with requested offloads.
5653 m = RTE_DIM(txoff_func);
5654 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5657 tmp = txoff_func[i].olx;
5659 /* Meets requested offloads exactly.*/
5663 if ((tmp & olx) != olx) {
5664 /* Does not meet requested offloads at all. */
5667 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5668 /* Do not enable legacy MPW if not configured. */
5670 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5671 /* Do not enable eMPW if not configured. */
5673 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5674 /* Do not enable inlining if not configured. */
5676 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5677 /* Do not enable scheduling if not configured. */
5680 * Some routine meets the requirements.
5681 * Check whether it has minimal amount
5682 * of not requested offloads.
5684 tmp = __builtin_popcountl(tmp & ~olx);
5685 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5686 /* First or better match, save and continue. */
5692 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5693 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5694 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5695 /* Lighter not requested offload. */
5700 if (m >= RTE_DIM(txoff_func)) {
5701 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5702 " for requested offloads %04X",
5703 dev->data->port_id, olx);
5706 DRV_LOG(DEBUG, "port %u has selected Tx function"
5707 " supporting offloads %04X/%04X",
5708 dev->data->port_id, olx, txoff_func[m].olx);
5709 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5710 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5711 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5712 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5713 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5714 DRV_LOG(DEBUG, "\tSWP (software parser)");
5715 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5716 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5717 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5718 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5719 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5720 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5721 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5722 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5723 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5724 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5725 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5726 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5727 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5729 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5731 return txoff_func[m].func;
5735 * DPDK callback to get the TX queue information
5738 * Pointer to the device structure.
5740 * @param tx_queue_id
5741 * Tx queue identificator.
5744 * Pointer to the TX queue information structure.
5751 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5752 struct rte_eth_txq_info *qinfo)
5754 struct mlx5_priv *priv = dev->data->dev_private;
5755 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5756 struct mlx5_txq_ctrl *txq_ctrl =
5757 container_of(txq, struct mlx5_txq_ctrl, txq);
5761 qinfo->nb_desc = txq->elts_s;
5762 qinfo->conf.tx_thresh.pthresh = 0;
5763 qinfo->conf.tx_thresh.hthresh = 0;
5764 qinfo->conf.tx_thresh.wthresh = 0;
5765 qinfo->conf.tx_rs_thresh = 0;
5766 qinfo->conf.tx_free_thresh = 0;
5767 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5768 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5772 * DPDK callback to get the TX packet burst mode information
5775 * Pointer to the device structure.
5777 * @param tx_queue_id
5778 * Tx queue identificatior.
5781 * Pointer to the burts mode information.
5784 * 0 as success, -EINVAL as failure.
5788 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5789 uint16_t tx_queue_id __rte_unused,
5790 struct rte_eth_burst_mode *mode)
5792 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5793 unsigned int i, olx;
5795 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5796 if (pkt_burst == txoff_func[i].func) {
5797 olx = txoff_func[i].olx;
5798 snprintf(mode->info, sizeof(mode->info),
5799 "%s%s%s%s%s%s%s%s%s",
5800 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5801 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5802 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5803 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5805 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5807 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5809 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5811 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5813 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5815 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5817 (olx & MLX5_TXOFF_CONFIG_TXPP) ?