drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Manage TX completions.
 199  *
 200  * When sending a burst, mlx5_tx_burst() posts several WRs.
 201  *
 202  * @param txq
 203  *   Pointer to TX queue structure.
 204  */
 205 static inline void
 206 txq_complete(struct txq *txq)
 207 {
 208         const unsigned int elts_n = 1 << txq->elts_n;
 209         const unsigned int cqe_n = 1 << txq->cqe_n;
 210         const unsigned int cqe_cnt = cqe_n - 1;
 211         uint16_t elts_free = txq->elts_tail;
 212         uint16_t elts_tail;
 213         uint16_t cq_ci = txq->cq_ci;
 214         volatile struct mlx5_cqe *cqe = NULL;
 215         volatile struct mlx5_wqe_ctrl *ctrl;
 216
 217         do {
 218                 volatile struct mlx5_cqe *tmp;
 219
 220                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 221                 if (check_cqe(tmp, cqe_n, cq_ci))
 222                         break;
 223                 cqe = tmp;
 224 #ifndef NDEBUG
 225                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 226                         if (!check_cqe_seen(cqe))
 227                                 ERROR("unexpected compressed CQE, TX stopped");
 228                         return;
 229                 }
 230                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 231                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 232                         if (!check_cqe_seen(cqe))
 233                                 ERROR("unexpected error CQE, TX stopped");
 234                         return;
 235                 }
 236 #endif /* NDEBUG */
 237                 ++cq_ci;
 238         } while (1);
 239         if (unlikely(cqe == NULL))
 240                 return;
 241         txq->wqe_pi = ntohs(cqe->wqe_counter);
 242         ctrl = (volatile struct mlx5_wqe_ctrl *)
 243                 tx_mlx5_wqe(txq, txq->wqe_pi);
 244         elts_tail = ctrl->ctrl3;
 245         assert(elts_tail < (1 << txq->wqe_n));
 246         /* Free buffers. */
 247         while (elts_free != elts_tail) {
 248                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 249                 unsigned int elts_free_next =
 250                         (elts_free + 1) & (elts_n - 1);
 251                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 252
 253 #ifndef NDEBUG
 254                 /* Poisoning. */
 255                 memset(&(*txq->elts)[elts_free],
 256                        0x66,
 257                        sizeof((*txq->elts)[elts_free]));
 258 #endif
 259                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 260                 /* Only one segment needs to be freed. */
 261                 rte_pktmbuf_free_seg(elt);
 262                 elts_free = elts_free_next;
 263         }
 264         txq->cq_ci = cq_ci;
 265         txq->elts_tail = elts_tail;
 266         /* Update the consumer index. */
 267         rte_wmb();
 268         *txq->cq_db = htonl(cq_ci);
 269 }
 270
 271 /**
 272  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 273  * the cloned mbuf is allocated is returned instead.
 274  *
 275  * @param buf
 276  *   Pointer to mbuf.
 277  *
 278  * @return
 279  *   Memory pool where data is located for given mbuf.
 280  */
 281 static struct rte_mempool *
 282 txq_mb2mp(struct rte_mbuf *buf)
 283 {
 284         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 285                 return rte_mbuf_from_indirect(buf)->pool;
 286         return buf->pool;
 287 }
 288
 289 /**
 290  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 291  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 292  * remove an entry first.
 293  *
 294  * @param txq
 295  *   Pointer to TX queue structure.
 296  * @param[in] mp
 297  *   Memory Pool for which a Memory Region lkey must be returned.
 298  *
 299  * @return
 300  *   mr->lkey on success, (uint32_t)-1 on failure.
 301  */
 302 static inline uint32_t
 303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 304 {
 305         unsigned int i;
 306         uint32_t lkey = (uint32_t)-1;
 307
 308         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 309                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 310                         /* Unknown MP, add a new MR for it. */
 311                         break;
 312                 }
 313                 if (txq->mp2mr[i].mp == mp) {
 314                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 315                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 316                                txq->mp2mr[i].lkey);
 317                         lkey = txq->mp2mr[i].lkey;
 318                         break;
 319                 }
 320         }
 321         if (unlikely(lkey == (uint32_t)-1))
 322                 lkey = txq_mp2mr_reg(txq, mp, i);
 323         return lkey;
 324 }
 325
 326 /**
 327  * Ring TX queue doorbell.
 328  *
 329  * @param txq
 330  *   Pointer to TX queue structure.
 331  * @param wqe
 332  *   Pointer to the last WQE posted in the NIC.
 333  */
 334 static inline void
 335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 336 {
 337         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 338         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 339
 340         rte_wmb();
 341         *txq->qp_db = htonl(txq->wqe_ci);
 342         /* Ensure ordering between DB record and BF copy. */
 343         rte_wmb();
 344         *dst = *src;
 345 }
 346
 347 /**
 348  * DPDK callback to check the status of a tx descriptor.
 349  *
 350  * @param tx_queue
 351  *   The tx queue.
 352  * @param[in] offset
 353  *   The index of the descriptor in the ring.
 354  *
 355  * @return
 356  *   The status of the tx descriptor.
 357  */
 358 int
 359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 360 {
 361         struct txq *txq = tx_queue;
 362         const unsigned int elts_n = 1 << txq->elts_n;
 363         const unsigned int elts_cnt = elts_n - 1;
 364         unsigned int used;
 365
 366         txq_complete(txq);
 367         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 368         if (offset < used)
 369                 return RTE_ETH_TX_DESC_FULL;
 370         return RTE_ETH_TX_DESC_DONE;
 371 }
 372
 373 /**
 374  * DPDK callback to check the status of a rx descriptor.
 375  *
 376  * @param rx_queue
 377  *   The rx queue.
 378  * @param[in] offset
 379  *   The index of the descriptor in the ring.
 380  *
 381  * @return
 382  *   The status of the tx descriptor.
 383  */
 384 int
 385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 386 {
 387         struct rxq *rxq = rx_queue;
 388         struct rxq_zip *zip = &rxq->zip;
 389         volatile struct mlx5_cqe *cqe;
 390         const unsigned int cqe_n = (1 << rxq->cqe_n);
 391         const unsigned int cqe_cnt = cqe_n - 1;
 392         unsigned int cq_ci;
 393         unsigned int used;
 394
 395         /* if we are processing a compressed cqe */
 396         if (zip->ai) {
 397                 used = zip->cqe_cnt - zip->ca;
 398                 cq_ci = zip->cq_ci;
 399         } else {
 400                 used = 0;
 401                 cq_ci = rxq->cq_ci;
 402         }
 403         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 404         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 405                 int8_t op_own;
 406                 unsigned int n;
 407
 408                 op_own = cqe->op_own;
 409                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 410                         n = ntohl(cqe->byte_cnt);
 411                 else
 412                         n = 1;
 413                 cq_ci += n;
 414                 used += n;
 415                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 416         }
 417         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 418         if (offset < used)
 419                 return RTE_ETH_RX_DESC_DONE;
 420         return RTE_ETH_RX_DESC_AVAIL;
 421 }
 422
 423 /**
 424  * DPDK callback for TX.
 425  *
 426  * @param dpdk_txq
 427  *   Generic pointer to TX queue structure.
 428  * @param[in] pkts
 429  *   Packets to transmit.
 430  * @param pkts_n
 431  *   Number of packets in array.
 432  *
 433  * @return
 434  *   Number of packets successfully transmitted (<= pkts_n).
 435  */
 436 uint16_t
 437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 438 {
 439         struct txq *txq = (struct txq *)dpdk_txq;
 440         uint16_t elts_head = txq->elts_head;
 441         const unsigned int elts_n = 1 << txq->elts_n;
 442         unsigned int i = 0;
 443         unsigned int j = 0;
 444         unsigned int k = 0;
 445         unsigned int max;
 446         uint16_t max_wqe;
 447         unsigned int comp;
 448         volatile struct mlx5_wqe_v *wqe = NULL;
 449         unsigned int segs_n = 0;
 450         struct rte_mbuf *buf = NULL;
 451         uint8_t *raw;
 452
 453         if (unlikely(!pkts_n))
 454                 return 0;
 455         /* Prefetch first packet cacheline. */
 456         rte_prefetch0(*pkts);
 457         /* Start processing. */
 458         txq_complete(txq);
 459         max = (elts_n - (elts_head - txq->elts_tail));
 460         if (max > elts_n)
 461                 max -= elts_n;
 462         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 463         if (unlikely(!max_wqe))
 464                 return 0;
 465         do {
 466                 volatile rte_v128u32_t *dseg = NULL;
 467                 uint32_t length;
 468                 unsigned int ds = 0;
 469                 uintptr_t addr;
 470                 uint64_t naddr;
 471                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 472                 uint16_t tso_header_sz = 0;
 473                 uint16_t ehdr;
 474                 uint8_t cs_flags = 0;
 475                 uint64_t tso = 0;
 476 #ifdef MLX5_PMD_SOFT_COUNTERS
 477                 uint32_t total_length = 0;
 478 #endif
 479
 480                 /* first_seg */
 481                 buf = *(pkts++);
 482                 segs_n = buf->nb_segs;
 483                 /*
 484                  * Make sure there is enough room to store this packet and
 485                  * that one ring entry remains unused.
 486                  */
 487                 assert(segs_n);
 488                 if (max < segs_n + 1)
 489                         break;
 490                 max -= segs_n;
 491                 --segs_n;
 492                 if (!segs_n)
 493                         --pkts_n;
 494                 if (unlikely(--max_wqe == 0))
 495                         break;
 496                 wqe = (volatile struct mlx5_wqe_v *)
 497                         tx_mlx5_wqe(txq, txq->wqe_ci);
 498                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 499                 if (pkts_n > 1)
 500                         rte_prefetch0(*pkts);
 501                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 502                 length = DATA_LEN(buf);
 503                 ehdr = (((uint8_t *)addr)[1] << 8) |
 504                        ((uint8_t *)addr)[0];
 505 #ifdef MLX5_PMD_SOFT_COUNTERS
 506                 total_length = length;
 507 #endif
 508                 assert(length >= MLX5_WQE_DWORD_SIZE);
 509                 /* Update element. */
 510                 (*txq->elts)[elts_head] = buf;
 511                 elts_head = (elts_head + 1) & (elts_n - 1);
 512                 /* Prefetch next buffer data. */
 513                 if (pkts_n > 1) {
 514                         volatile void *pkt_addr;
 515
 516                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 517                         rte_prefetch0(pkt_addr);
 518                 }
 519                 /* Should we enable HW CKSUM offload */
 520                 if (buf->ol_flags &
 521                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 522                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 523                 }
 524                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 525                 /* Replace the Ethernet type by the VLAN if necessary. */
 526                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 527                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 528                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 529
 530                         addr += 2;
 531                         length -= 2;
 532                         /* Copy Destination and source mac address. */
 533                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 534                         /* Copy VLAN. */
 535                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 536                         /* Copy missing two bytes to end the DSeg. */
 537                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 538                                ((uint8_t *)addr) + len, 2);
 539                         addr += len + 2;
 540                         length -= (len + 2);
 541                 } else {
 542                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 543                                MLX5_WQE_DWORD_SIZE);
 544                         length -= pkt_inline_sz;
 545                         addr += pkt_inline_sz;
 546                 }
 547                 if (txq->tso_en) {
 548                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 549                         if (tso) {
 550                                 uintptr_t end = (uintptr_t)
 551                                                 (((uintptr_t)txq->wqes) +
 552                                                 (1 << txq->wqe_n) *
 553                                                 MLX5_WQE_SIZE);
 554                                 unsigned int copy_b;
 555                                 uint8_t vlan_sz = (buf->ol_flags &
 556                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 557
 558                                 tso_header_sz = buf->l2_len + vlan_sz +
 559                                                 buf->l3_len + buf->l4_len;
 560
 561                                 if (unlikely(tso_header_sz >
 562                                              MLX5_MAX_TSO_HEADER))
 563                                         break;
 564                                 copy_b = tso_header_sz - pkt_inline_sz;
 565                                 /* First seg must contain all headers. */
 566                                 assert(copy_b <= length);
 567                                 raw += MLX5_WQE_DWORD_SIZE;
 568                                 if (copy_b &&
 569                                    ((end - (uintptr_t)raw) > copy_b)) {
 570                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 571                                                       1 + 3) / 4;
 572
 573                                         if (unlikely(max_wqe < n))
 574                                                 break;
 575                                         max_wqe -= n;
 576                                         rte_memcpy((void *)raw,
 577                                                    (void *)addr, copy_b);
 578                                         addr += copy_b;
 579                                         length -= copy_b;
 580                                         pkt_inline_sz += copy_b;
 581                                         /*
 582                                          * Another DWORD will be added
 583                                          * in the inline part.
 584                                          */
 585                                         raw += MLX5_WQE_DS(copy_b) *
 586                                                MLX5_WQE_DWORD_SIZE -
 587                                                MLX5_WQE_DWORD_SIZE;
 588                                 } else {
 589                                         /* NOP WQE. */
 590                                         wqe->ctrl = (rte_v128u32_t){
 591                                                      htonl(txq->wqe_ci << 8),
 592                                                      htonl(txq->qp_num_8s | 1),
 593                                                      0,
 594                                                      0,
 595                                         };
 596                                         ds = 1;
 597                                         total_length = 0;
 598                                         pkts--;
 599                                         pkts_n++;
 600                                         elts_head = (elts_head - 1) &
 601                                                     (elts_n - 1);
 602                                         k++;
 603                                         goto next_wqe;
 604                                 }
 605                         }
 606                 }
 607                 /* Inline if enough room. */
 608                 if (txq->inline_en || tso) {
 609                         uintptr_t end = (uintptr_t)
 610                                 (((uintptr_t)txq->wqes) +
 611                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 612                         unsigned int max_inline = txq->max_inline *
 613                                                   RTE_CACHE_LINE_SIZE -
 614                                                   (pkt_inline_sz - 2);
 615                         uintptr_t addr_end = (addr + max_inline) &
 616                                              ~(RTE_CACHE_LINE_SIZE - 1);
 617                         unsigned int copy_b = (addr_end > addr) ?
 618                                 RTE_MIN((addr_end - addr), length) :
 619                                 0;
 620
 621                         raw += MLX5_WQE_DWORD_SIZE;
 622                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 623                                 /*
 624                                  * One Dseg remains in the current WQE.  To
 625                                  * keep the computation positive, it is
 626                                  * removed after the bytes to Dseg conversion.
 627                                  */
 628                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 629
 630                                 if (unlikely(max_wqe < n))
 631                                         break;
 632                                 max_wqe -= n;
 633                                 if (tso) {
 634                                         uint32_t inl =
 635                                                 htonl(copy_b | MLX5_INLINE_SEG);
 636
 637                                         pkt_inline_sz =
 638                                                 MLX5_WQE_DS(tso_header_sz) *
 639                                                 MLX5_WQE_DWORD_SIZE;
 640                                         rte_memcpy((void *)raw,
 641                                                    (void *)&inl, sizeof(inl));
 642                                         raw += sizeof(inl);
 643                                         pkt_inline_sz += sizeof(inl);
 644                                 }
 645                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 646                                 addr += copy_b;
 647                                 length -= copy_b;
 648                                 pkt_inline_sz += copy_b;
 649                         }
 650                         /*
 651                          * 2 DWORDs consumed by the WQE header + ETH segment +
 652                          * the size of the inline part of the packet.
 653                          */
 654                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 655                         if (length > 0) {
 656                                 if (ds % (MLX5_WQE_SIZE /
 657                                           MLX5_WQE_DWORD_SIZE) == 0) {
 658                                         if (unlikely(--max_wqe == 0))
 659                                                 break;
 660                                         dseg = (volatile rte_v128u32_t *)
 661                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 662                                                            ds / 4);
 663                                 } else {
 664                                         dseg = (volatile rte_v128u32_t *)
 665                                                 ((uintptr_t)wqe +
 666                                                  (ds * MLX5_WQE_DWORD_SIZE));
 667                                 }
 668                                 goto use_dseg;
 669                         } else if (!segs_n) {
 670                                 goto next_pkt;
 671                         } else {
 672                                 /* dseg will be advance as part of next_seg */
 673                                 dseg = (volatile rte_v128u32_t *)
 674                                         ((uintptr_t)wqe +
 675                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 676                                 goto next_seg;
 677                         }
 678                 } else {
 679                         /*
 680                          * No inline has been done in the packet, only the
 681                          * Ethernet Header as been stored.
 682                          */
 683                         dseg = (volatile rte_v128u32_t *)
 684                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 685                         ds = 3;
 686 use_dseg:
 687                         /* Add the remaining packet as a simple ds. */
 688                         naddr = htonll(addr);
 689                         *dseg = (rte_v128u32_t){
 690                                 htonl(length),
 691                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 692                                 naddr,
 693                                 naddr >> 32,
 694                         };
 695                         ++ds;
 696                         if (!segs_n)
 697                                 goto next_pkt;
 698                 }
 699 next_seg:
 700                 assert(buf);
 701                 assert(ds);
 702                 assert(wqe);
 703                 /*
 704                  * Spill on next WQE when the current one does not have
 705                  * enough room left. Size of WQE must a be a multiple
 706                  * of data segment size.
 707                  */
 708                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 709                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 710                         if (unlikely(--max_wqe == 0))
 711                                 break;
 712                         dseg = (volatile rte_v128u32_t *)
 713                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 714                         rte_prefetch0(tx_mlx5_wqe(txq,
 715                                                   txq->wqe_ci + ds / 4 + 1));
 716                 } else {
 717                         ++dseg;
 718                 }
 719                 ++ds;
 720                 buf = buf->next;
 721                 assert(buf);
 722                 length = DATA_LEN(buf);
 723 #ifdef MLX5_PMD_SOFT_COUNTERS
 724                 total_length += length;
 725 #endif
 726                 /* Store segment information. */
 727                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 728                 *dseg = (rte_v128u32_t){
 729                         htonl(length),
 730                         txq_mp2mr(txq, txq_mb2mp(buf)),
 731                         naddr,
 732                         naddr >> 32,
 733                 };
 734                 (*txq->elts)[elts_head] = buf;
 735                 elts_head = (elts_head + 1) & (elts_n - 1);
 736                 ++j;
 737                 --segs_n;
 738                 if (segs_n)
 739                         goto next_seg;
 740                 else
 741                         --pkts_n;
 742 next_pkt:
 743                 ++i;
 744                 /* Initialize known and common part of the WQE structure. */
 745                 if (tso) {
 746                         wqe->ctrl = (rte_v128u32_t){
 747                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 748                                 htonl(txq->qp_num_8s | ds),
 749                                 0,
 750                                 0,
 751                         };
 752                         wqe->eseg = (rte_v128u32_t){
 753                                 0,
 754                                 cs_flags | (htons(buf->tso_segsz) << 16),
 755                                 0,
 756                                 (ehdr << 16) | htons(tso_header_sz),
 757                         };
 758                 } else {
 759                         wqe->ctrl = (rte_v128u32_t){
 760                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 761                                 htonl(txq->qp_num_8s | ds),
 762                                 0,
 763                                 0,
 764                         };
 765                         wqe->eseg = (rte_v128u32_t){
 766                                 0,
 767                                 cs_flags,
 768                                 0,
 769                                 (ehdr << 16) | htons(pkt_inline_sz),
 770                         };
 771                 }
 772 next_wqe:
 773                 txq->wqe_ci += (ds + 3) / 4;
 774 #ifdef MLX5_PMD_SOFT_COUNTERS
 775                 /* Increment sent bytes counter. */
 776                 txq->stats.obytes += total_length;
 777 #endif
 778         } while (pkts_n);
 779         /* Take a shortcut if nothing must be sent. */
 780         if (unlikely((i + k) == 0))
 781                 return 0;
 782         /* Check whether completion threshold has been reached. */
 783         comp = txq->elts_comp + i + j + k;
 784         if (comp >= MLX5_TX_COMP_THRESH) {
 785                 volatile struct mlx5_wqe_ctrl *w =
 786                         (volatile struct mlx5_wqe_ctrl *)wqe;
 787
 788                 /* Request completion on last WQE. */
 789                 w->ctrl2 = htonl(8);
 790                 /* Save elts_head in unused "immediate" field of WQE. */
 791                 w->ctrl3 = elts_head;
 792                 txq->elts_comp = 0;
 793         } else {
 794                 txq->elts_comp = comp;
 795         }
 796 #ifdef MLX5_PMD_SOFT_COUNTERS
 797         /* Increment sent packets counter. */
 798         txq->stats.opackets += i;
 799 #endif
 800         /* Ring QP doorbell. */
 801         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 802         txq->elts_head = elts_head;
 803         return i;
 804 }
 805
 806 /**
 807  * Open a MPW session.
 808  *
 809  * @param txq
 810  *   Pointer to TX queue structure.
 811  * @param mpw
 812  *   Pointer to MPW session structure.
 813  * @param length
 814  *   Packet length.
 815  */
 816 static inline void
 817 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 818 {
 819         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 820         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 821                 (volatile struct mlx5_wqe_data_seg (*)[])
 822                 tx_mlx5_wqe(txq, idx + 1);
 823
 824         mpw->state = MLX5_MPW_STATE_OPENED;
 825         mpw->pkts_n = 0;
 826         mpw->len = length;
 827         mpw->total_len = 0;
 828         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 829         mpw->wqe->eseg.mss = htons(length);
 830         mpw->wqe->eseg.inline_hdr_sz = 0;
 831         mpw->wqe->eseg.rsvd0 = 0;
 832         mpw->wqe->eseg.rsvd1 = 0;
 833         mpw->wqe->eseg.rsvd2 = 0;
 834         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 835                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 836         mpw->wqe->ctrl[2] = 0;
 837         mpw->wqe->ctrl[3] = 0;
 838         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 839                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 840         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 841                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 842         mpw->data.dseg[2] = &(*dseg)[0];
 843         mpw->data.dseg[3] = &(*dseg)[1];
 844         mpw->data.dseg[4] = &(*dseg)[2];
 845 }
 846
 847 /**
 848  * Close a MPW session.
 849  *
 850  * @param txq
 851  *   Pointer to TX queue structure.
 852  * @param mpw
 853  *   Pointer to MPW session structure.
 854  */
 855 static inline void
 856 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 857 {
 858         unsigned int num = mpw->pkts_n;
 859
 860         /*
 861          * Store size in multiple of 16 bytes. Control and Ethernet segments
 862          * count as 2.
 863          */
 864         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 865         mpw->state = MLX5_MPW_STATE_CLOSED;
 866         if (num < 3)
 867                 ++txq->wqe_ci;
 868         else
 869                 txq->wqe_ci += 2;
 870         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 871         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 872 }
 873
 874 /**
 875  * DPDK callback for TX with MPW support.
 876  *
 877  * @param dpdk_txq
 878  *   Generic pointer to TX queue structure.
 879  * @param[in] pkts
 880  *   Packets to transmit.
 881  * @param pkts_n
 882  *   Number of packets in array.
 883  *
 884  * @return
 885  *   Number of packets successfully transmitted (<= pkts_n).
 886  */
 887 uint16_t
 888 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 889 {
 890         struct txq *txq = (struct txq *)dpdk_txq;
 891         uint16_t elts_head = txq->elts_head;
 892         const unsigned int elts_n = 1 << txq->elts_n;
 893         unsigned int i = 0;
 894         unsigned int j = 0;
 895         unsigned int max;
 896         uint16_t max_wqe;
 897         unsigned int comp;
 898         struct mlx5_mpw mpw = {
 899                 .state = MLX5_MPW_STATE_CLOSED,
 900         };
 901
 902         if (unlikely(!pkts_n))
 903                 return 0;
 904         /* Prefetch first packet cacheline. */
 905         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 906         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 907         /* Start processing. */
 908         txq_complete(txq);
 909         max = (elts_n - (elts_head - txq->elts_tail));
 910         if (max > elts_n)
 911                 max -= elts_n;
 912         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 913         if (unlikely(!max_wqe))
 914                 return 0;
 915         do {
 916                 struct rte_mbuf *buf = *(pkts++);
 917                 unsigned int elts_head_next;
 918                 uint32_t length;
 919                 unsigned int segs_n = buf->nb_segs;
 920                 uint32_t cs_flags = 0;
 921
 922                 /*
 923                  * Make sure there is enough room to store this packet and
 924                  * that one ring entry remains unused.
 925                  */
 926                 assert(segs_n);
 927                 if (max < segs_n + 1)
 928                         break;
 929                 /* Do not bother with large packets MPW cannot handle. */
 930                 if (segs_n > MLX5_MPW_DSEG_MAX)
 931                         break;
 932                 max -= segs_n;
 933                 --pkts_n;
 934                 /* Should we enable HW CKSUM offload */
 935                 if (buf->ol_flags &
 936                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 937                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 938                 /* Retrieve packet information. */
 939                 length = PKT_LEN(buf);
 940                 assert(length);
 941                 /* Start new session if packet differs. */
 942                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 943                     ((mpw.len != length) ||
 944                      (segs_n != 1) ||
 945                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 946                         mlx5_mpw_close(txq, &mpw);
 947                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 948                         /*
 949                          * Multi-Packet WQE consumes at most two WQE.
 950                          * mlx5_mpw_new() expects to be able to use such
 951                          * resources.
 952                          */
 953                         if (unlikely(max_wqe < 2))
 954                                 break;
 955                         max_wqe -= 2;
 956                         mlx5_mpw_new(txq, &mpw, length);
 957                         mpw.wqe->eseg.cs_flags = cs_flags;
 958                 }
 959                 /* Multi-segment packets must be alone in their MPW. */
 960                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 961 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 962                 length = 0;
 963 #endif
 964                 do {
 965                         volatile struct mlx5_wqe_data_seg *dseg;
 966                         uintptr_t addr;
 967
 968                         elts_head_next = (elts_head + 1) & (elts_n - 1);
 969                         assert(buf);
 970                         (*txq->elts)[elts_head] = buf;
 971                         dseg = mpw.data.dseg[mpw.pkts_n];
 972                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 973                         *dseg = (struct mlx5_wqe_data_seg){
 974                                 .byte_count = htonl(DATA_LEN(buf)),
 975                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
 976                                 .addr = htonll(addr),
 977                         };
 978                         elts_head = elts_head_next;
 979 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 980                         length += DATA_LEN(buf);
 981 #endif
 982                         buf = buf->next;
 983                         ++mpw.pkts_n;
 984                         ++j;
 985                 } while (--segs_n);
 986                 assert(length == mpw.len);
 987                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 988                         mlx5_mpw_close(txq, &mpw);
 989                 elts_head = elts_head_next;
 990 #ifdef MLX5_PMD_SOFT_COUNTERS
 991                 /* Increment sent bytes counter. */
 992                 txq->stats.obytes += length;
 993 #endif
 994                 ++i;
 995         } while (pkts_n);
 996         /* Take a shortcut if nothing must be sent. */
 997         if (unlikely(i == 0))
 998                 return 0;
 999         /* Check whether completion threshold has been reached. */
1000         /* "j" includes both packets and segments. */
1001         comp = txq->elts_comp + j;
1002         if (comp >= MLX5_TX_COMP_THRESH) {
1003                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1004
1005                 /* Request completion on last WQE. */
1006                 wqe->ctrl[2] = htonl(8);
1007                 /* Save elts_head in unused "immediate" field of WQE. */
1008                 wqe->ctrl[3] = elts_head;
1009                 txq->elts_comp = 0;
1010         } else {
1011                 txq->elts_comp = comp;
1012         }
1013 #ifdef MLX5_PMD_SOFT_COUNTERS
1014         /* Increment sent packets counter. */
1015         txq->stats.opackets += i;
1016 #endif
1017         /* Ring QP doorbell. */
1018         if (mpw.state == MLX5_MPW_STATE_OPENED)
1019                 mlx5_mpw_close(txq, &mpw);
1020         mlx5_tx_dbrec(txq, mpw.wqe);
1021         txq->elts_head = elts_head;
1022         return i;
1023 }
1024
1025 /**
1026  * Open a MPW inline session.
1027  *
1028  * @param txq
1029  *   Pointer to TX queue structure.
1030  * @param mpw
1031  *   Pointer to MPW session structure.
1032  * @param length
1033  *   Packet length.
1034  */
1035 static inline void
1036 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1037 {
1038         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1039         struct mlx5_wqe_inl_small *inl;
1040
1041         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1042         mpw->pkts_n = 0;
1043         mpw->len = length;
1044         mpw->total_len = 0;
1045         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1046         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1047                                   (txq->wqe_ci << 8) |
1048                                   MLX5_OPCODE_TSO);
1049         mpw->wqe->ctrl[2] = 0;
1050         mpw->wqe->ctrl[3] = 0;
1051         mpw->wqe->eseg.mss = htons(length);
1052         mpw->wqe->eseg.inline_hdr_sz = 0;
1053         mpw->wqe->eseg.cs_flags = 0;
1054         mpw->wqe->eseg.rsvd0 = 0;
1055         mpw->wqe->eseg.rsvd1 = 0;
1056         mpw->wqe->eseg.rsvd2 = 0;
1057         inl = (struct mlx5_wqe_inl_small *)
1058                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1059         mpw->data.raw = (uint8_t *)&inl->raw;
1060 }
1061
1062 /**
1063  * Close a MPW inline session.
1064  *
1065  * @param txq
1066  *   Pointer to TX queue structure.
1067  * @param mpw
1068  *   Pointer to MPW session structure.
1069  */
1070 static inline void
1071 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1072 {
1073         unsigned int size;
1074         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1075                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1076
1077         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1078         /*
1079          * Store size in multiple of 16 bytes. Control and Ethernet segments
1080          * count as 2.
1081          */
1082         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1083         mpw->state = MLX5_MPW_STATE_CLOSED;
1084         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1085         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1086 }
1087
1088 /**
1089  * DPDK callback for TX with MPW inline support.
1090  *
1091  * @param dpdk_txq
1092  *   Generic pointer to TX queue structure.
1093  * @param[in] pkts
1094  *   Packets to transmit.
1095  * @param pkts_n
1096  *   Number of packets in array.
1097  *
1098  * @return
1099  *   Number of packets successfully transmitted (<= pkts_n).
1100  */
1101 uint16_t
1102 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1103                          uint16_t pkts_n)
1104 {
1105         struct txq *txq = (struct txq *)dpdk_txq;
1106         uint16_t elts_head = txq->elts_head;
1107         const unsigned int elts_n = 1 << txq->elts_n;
1108         unsigned int i = 0;
1109         unsigned int j = 0;
1110         unsigned int max;
1111         uint16_t max_wqe;
1112         unsigned int comp;
1113         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1114         struct mlx5_mpw mpw = {
1115                 .state = MLX5_MPW_STATE_CLOSED,
1116         };
1117         /*
1118          * Compute the maximum number of WQE which can be consumed by inline
1119          * code.
1120          * - 2 DSEG for:
1121          *   - 1 control segment,
1122          *   - 1 Ethernet segment,
1123          * - N Dseg from the inline request.
1124          */
1125         const unsigned int wqe_inl_n =
1126                 ((2 * MLX5_WQE_DWORD_SIZE +
1127                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1128                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1129
1130         if (unlikely(!pkts_n))
1131                 return 0;
1132         /* Prefetch first packet cacheline. */
1133         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1134         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1135         /* Start processing. */
1136         txq_complete(txq);
1137         max = (elts_n - (elts_head - txq->elts_tail));
1138         if (max > elts_n)
1139                 max -= elts_n;
1140         do {
1141                 struct rte_mbuf *buf = *(pkts++);
1142                 unsigned int elts_head_next;
1143                 uintptr_t addr;
1144                 uint32_t length;
1145                 unsigned int segs_n = buf->nb_segs;
1146                 uint32_t cs_flags = 0;
1147
1148                 /*
1149                  * Make sure there is enough room to store this packet and
1150                  * that one ring entry remains unused.
1151                  */
1152                 assert(segs_n);
1153                 if (max < segs_n + 1)
1154                         break;
1155                 /* Do not bother with large packets MPW cannot handle. */
1156                 if (segs_n > MLX5_MPW_DSEG_MAX)
1157                         break;
1158                 max -= segs_n;
1159                 --pkts_n;
1160                 /*
1161                  * Compute max_wqe in case less WQE were consumed in previous
1162                  * iteration.
1163                  */
1164                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1165                 /* Should we enable HW CKSUM offload */
1166                 if (buf->ol_flags &
1167                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1168                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1169                 /* Retrieve packet information. */
1170                 length = PKT_LEN(buf);
1171                 /* Start new session if packet differs. */
1172                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1173                         if ((mpw.len != length) ||
1174                             (segs_n != 1) ||
1175                             (mpw.wqe->eseg.cs_flags != cs_flags))
1176                                 mlx5_mpw_close(txq, &mpw);
1177                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1178                         if ((mpw.len != length) ||
1179                             (segs_n != 1) ||
1180                             (length > inline_room) ||
1181                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1182                                 mlx5_mpw_inline_close(txq, &mpw);
1183                                 inline_room =
1184                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1185                         }
1186                 }
1187                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1188                         if ((segs_n != 1) ||
1189                             (length > inline_room)) {
1190                                 /*
1191                                  * Multi-Packet WQE consumes at most two WQE.
1192                                  * mlx5_mpw_new() expects to be able to use
1193                                  * such resources.
1194                                  */
1195                                 if (unlikely(max_wqe < 2))
1196                                         break;
1197                                 max_wqe -= 2;
1198                                 mlx5_mpw_new(txq, &mpw, length);
1199                                 mpw.wqe->eseg.cs_flags = cs_flags;
1200                         } else {
1201                                 if (unlikely(max_wqe < wqe_inl_n))
1202                                         break;
1203                                 max_wqe -= wqe_inl_n;
1204                                 mlx5_mpw_inline_new(txq, &mpw, length);
1205                                 mpw.wqe->eseg.cs_flags = cs_flags;
1206                         }
1207                 }
1208                 /* Multi-segment packets must be alone in their MPW. */
1209                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1210                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1211                         assert(inline_room ==
1212                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1213 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1214                         length = 0;
1215 #endif
1216                         do {
1217                                 volatile struct mlx5_wqe_data_seg *dseg;
1218
1219                                 elts_head_next =
1220                                         (elts_head + 1) & (elts_n - 1);
1221                                 assert(buf);
1222                                 (*txq->elts)[elts_head] = buf;
1223                                 dseg = mpw.data.dseg[mpw.pkts_n];
1224                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1225                                 *dseg = (struct mlx5_wqe_data_seg){
1226                                         .byte_count = htonl(DATA_LEN(buf)),
1227                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1228                                         .addr = htonll(addr),
1229                                 };
1230                                 elts_head = elts_head_next;
1231 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1232                                 length += DATA_LEN(buf);
1233 #endif
1234                                 buf = buf->next;
1235                                 ++mpw.pkts_n;
1236                                 ++j;
1237                         } while (--segs_n);
1238                         assert(length == mpw.len);
1239                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1240                                 mlx5_mpw_close(txq, &mpw);
1241                 } else {
1242                         unsigned int max;
1243
1244                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1245                         assert(length <= inline_room);
1246                         assert(length == DATA_LEN(buf));
1247                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1248                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1249                         (*txq->elts)[elts_head] = buf;
1250                         /* Maximum number of bytes before wrapping. */
1251                         max = ((((uintptr_t)(txq->wqes)) +
1252                                 (1 << txq->wqe_n) *
1253                                 MLX5_WQE_SIZE) -
1254                                (uintptr_t)mpw.data.raw);
1255                         if (length > max) {
1256                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1257                                            (void *)addr,
1258                                            max);
1259                                 mpw.data.raw = (volatile void *)txq->wqes;
1260                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1261                                            (void *)(addr + max),
1262                                            length - max);
1263                                 mpw.data.raw += length - max;
1264                         } else {
1265                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1266                                            (void *)addr,
1267                                            length);
1268
1269                                 if (length == max)
1270                                         mpw.data.raw =
1271                                                 (volatile void *)txq->wqes;
1272                                 else
1273                                         mpw.data.raw += length;
1274                         }
1275                         ++mpw.pkts_n;
1276                         mpw.total_len += length;
1277                         ++j;
1278                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1279                                 mlx5_mpw_inline_close(txq, &mpw);
1280                                 inline_room =
1281                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1282                         } else {
1283                                 inline_room -= length;
1284                         }
1285                 }
1286                 elts_head = elts_head_next;
1287 #ifdef MLX5_PMD_SOFT_COUNTERS
1288                 /* Increment sent bytes counter. */
1289                 txq->stats.obytes += length;
1290 #endif
1291                 ++i;
1292         } while (pkts_n);
1293         /* Take a shortcut if nothing must be sent. */
1294         if (unlikely(i == 0))
1295                 return 0;
1296         /* Check whether completion threshold has been reached. */
1297         /* "j" includes both packets and segments. */
1298         comp = txq->elts_comp + j;
1299         if (comp >= MLX5_TX_COMP_THRESH) {
1300                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1301
1302                 /* Request completion on last WQE. */
1303                 wqe->ctrl[2] = htonl(8);
1304                 /* Save elts_head in unused "immediate" field of WQE. */
1305                 wqe->ctrl[3] = elts_head;
1306                 txq->elts_comp = 0;
1307         } else {
1308                 txq->elts_comp = comp;
1309         }
1310 #ifdef MLX5_PMD_SOFT_COUNTERS
1311         /* Increment sent packets counter. */
1312         txq->stats.opackets += i;
1313 #endif
1314         /* Ring QP doorbell. */
1315         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1316                 mlx5_mpw_inline_close(txq, &mpw);
1317         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1318                 mlx5_mpw_close(txq, &mpw);
1319         mlx5_tx_dbrec(txq, mpw.wqe);
1320         txq->elts_head = elts_head;
1321         return i;
1322 }
1323
1324 /**
1325  * Translate RX completion flags to packet type.
1326  *
1327  * @param[in] cqe
1328  *   Pointer to CQE.
1329  *
1330  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1331  *
1332  * @return
1333  *   Packet type for struct rte_mbuf.
1334  */
1335 static inline uint32_t
1336 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1337 {
1338         uint32_t pkt_type;
1339         uint16_t flags = ntohs(cqe->hdr_type_etc);
1340
1341         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1342                 pkt_type =
1343                         TRANSPOSE(flags,
1344                                   MLX5_CQE_RX_IPV4_PACKET,
1345                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1346                         TRANSPOSE(flags,
1347                                   MLX5_CQE_RX_IPV6_PACKET,
1348                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1349                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1350                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1351                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1352         } else {
1353                 pkt_type =
1354                         TRANSPOSE(flags,
1355                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1356                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1357                         TRANSPOSE(flags,
1358                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1359                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1360         }
1361         return pkt_type;
1362 }
1363
1364 /**
1365  * Get size of the next packet for a given CQE. For compressed CQEs, the
1366  * consumer index is updated only once all packets of the current one have
1367  * been processed.
1368  *
1369  * @param rxq
1370  *   Pointer to RX queue.
1371  * @param cqe
1372  *   CQE to process.
1373  * @param[out] rss_hash
1374  *   Packet RSS Hash result.
1375  *
1376  * @return
1377  *   Packet size in bytes (0 if there is none), -1 in case of completion
1378  *   with error.
1379  */
1380 static inline int
1381 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1382                  uint16_t cqe_cnt, uint32_t *rss_hash)
1383 {
1384         struct rxq_zip *zip = &rxq->zip;
1385         uint16_t cqe_n = cqe_cnt + 1;
1386         int len = 0;
1387         uint16_t idx, end;
1388
1389         /* Process compressed data in the CQE and mini arrays. */
1390         if (zip->ai) {
1391                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1392                         (volatile struct mlx5_mini_cqe8 (*)[8])
1393                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1394
1395                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1396                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1397                 if ((++zip->ai & 7) == 0) {
1398                         /* Invalidate consumed CQEs */
1399                         idx = zip->ca;
1400                         end = zip->na;
1401                         while (idx != end) {
1402                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1403                                         MLX5_CQE_INVALIDATE;
1404                                 ++idx;
1405                         }
1406                         /*
1407                          * Increment consumer index to skip the number of
1408                          * CQEs consumed. Hardware leaves holes in the CQ
1409                          * ring for software use.
1410                          */
1411                         zip->ca = zip->na;
1412                         zip->na += 8;
1413                 }
1414                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1415                         /* Invalidate the rest */
1416                         idx = zip->ca;
1417                         end = zip->cq_ci;
1418
1419                         while (idx != end) {
1420                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1421                                         MLX5_CQE_INVALIDATE;
1422                                 ++idx;
1423                         }
1424                         rxq->cq_ci = zip->cq_ci;
1425                         zip->ai = 0;
1426                 }
1427         /* No compressed data, get next CQE and verify if it is compressed. */
1428         } else {
1429                 int ret;
1430                 int8_t op_own;
1431
1432                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1433                 if (unlikely(ret == 1))
1434                         return 0;
1435                 ++rxq->cq_ci;
1436                 op_own = cqe->op_own;
1437                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1438                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1439                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1440                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1441                                                           cqe_cnt]);
1442
1443                         /* Fix endianness. */
1444                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1445                         /*
1446                          * Current mini array position is the one returned by
1447                          * check_cqe64().
1448                          *
1449                          * If completion comprises several mini arrays, as a
1450                          * special case the second one is located 7 CQEs after
1451                          * the initial CQE instead of 8 for subsequent ones.
1452                          */
1453                         zip->ca = rxq->cq_ci;
1454                         zip->na = zip->ca + 7;
1455                         /* Compute the next non compressed CQE. */
1456                         --rxq->cq_ci;
1457                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1458                         /* Get packet size to return. */
1459                         len = ntohl((*mc)[0].byte_cnt);
1460                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1461                         zip->ai = 1;
1462                         /* Prefetch all the entries to be invalidated */
1463                         idx = zip->ca;
1464                         end = zip->cq_ci;
1465                         while (idx != end) {
1466                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1467                                 ++idx;
1468                         }
1469                 } else {
1470                         len = ntohl(cqe->byte_cnt);
1471                         *rss_hash = ntohl(cqe->rx_hash_res);
1472                 }
1473                 /* Error while receiving packet. */
1474                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1475                         return -1;
1476         }
1477         return len;
1478 }
1479
1480 /**
1481  * Translate RX completion flags to offload flags.
1482  *
1483  * @param[in] rxq
1484  *   Pointer to RX queue structure.
1485  * @param[in] cqe
1486  *   Pointer to CQE.
1487  *
1488  * @return
1489  *   Offload flags (ol_flags) for struct rte_mbuf.
1490  */
1491 static inline uint32_t
1492 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1493 {
1494         uint32_t ol_flags = 0;
1495         uint16_t flags = ntohs(cqe->hdr_type_etc);
1496
1497         ol_flags =
1498                 TRANSPOSE(flags,
1499                           MLX5_CQE_RX_L3_HDR_VALID,
1500                           PKT_RX_IP_CKSUM_GOOD) |
1501                 TRANSPOSE(flags,
1502                           MLX5_CQE_RX_L4_HDR_VALID,
1503                           PKT_RX_L4_CKSUM_GOOD);
1504         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1505                 ol_flags |=
1506                         TRANSPOSE(flags,
1507                                   MLX5_CQE_RX_L3_HDR_VALID,
1508                                   PKT_RX_IP_CKSUM_GOOD) |
1509                         TRANSPOSE(flags,
1510                                   MLX5_CQE_RX_L4_HDR_VALID,
1511                                   PKT_RX_L4_CKSUM_GOOD);
1512         return ol_flags;
1513 }
1514
1515 /**
1516  * DPDK callback for RX.
1517  *
1518  * @param dpdk_rxq
1519  *   Generic pointer to RX queue structure.
1520  * @param[out] pkts
1521  *   Array to store received packets.
1522  * @param pkts_n
1523  *   Maximum number of packets in array.
1524  *
1525  * @return
1526  *   Number of packets successfully received (<= pkts_n).
1527  */
1528 uint16_t
1529 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1530 {
1531         struct rxq *rxq = dpdk_rxq;
1532         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1533         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1534         const unsigned int sges_n = rxq->sges_n;
1535         struct rte_mbuf *pkt = NULL;
1536         struct rte_mbuf *seg = NULL;
1537         volatile struct mlx5_cqe *cqe =
1538                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1539         unsigned int i = 0;
1540         unsigned int rq_ci = rxq->rq_ci << sges_n;
1541         int len; /* keep its value across iterations. */
1542
1543         while (pkts_n) {
1544                 unsigned int idx = rq_ci & wqe_cnt;
1545                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1546                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1547                 uint32_t rss_hash_res = 0;
1548
1549                 if (pkt)
1550                         NEXT(seg) = rep;
1551                 seg = rep;
1552                 rte_prefetch0(seg);
1553                 rte_prefetch0(cqe);
1554                 rte_prefetch0(wqe);
1555                 rep = rte_mbuf_raw_alloc(rxq->mp);
1556                 if (unlikely(rep == NULL)) {
1557                         ++rxq->stats.rx_nombuf;
1558                         if (!pkt) {
1559                                 /*
1560                                  * no buffers before we even started,
1561                                  * bail out silently.
1562                                  */
1563                                 break;
1564                         }
1565                         while (pkt != seg) {
1566                                 assert(pkt != (*rxq->elts)[idx]);
1567                                 rep = NEXT(pkt);
1568                                 rte_mbuf_refcnt_set(pkt, 0);
1569                                 __rte_mbuf_raw_free(pkt);
1570                                 pkt = rep;
1571                         }
1572                         break;
1573                 }
1574                 if (!pkt) {
1575                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1576                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1577                                                &rss_hash_res);
1578                         if (!len) {
1579                                 rte_mbuf_refcnt_set(rep, 0);
1580                                 __rte_mbuf_raw_free(rep);
1581                                 break;
1582                         }
1583                         if (unlikely(len == -1)) {
1584                                 /* RX error, packet is likely too large. */
1585                                 rte_mbuf_refcnt_set(rep, 0);
1586                                 __rte_mbuf_raw_free(rep);
1587                                 ++rxq->stats.idropped;
1588                                 goto skip;
1589                         }
1590                         pkt = seg;
1591                         assert(len >= (rxq->crc_present << 2));
1592                         /* Update packet information. */
1593                         pkt->packet_type = 0;
1594                         pkt->ol_flags = 0;
1595                         if (rss_hash_res && rxq->rss_hash) {
1596                                 pkt->hash.rss = rss_hash_res;
1597                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1598                         }
1599                         if (rxq->mark && (cqe->sop_drop_qpn !=
1600                                           htonl(MLX5_FLOW_MARK_INVALID))) {
1601                                 pkt->ol_flags |= PKT_RX_FDIR;
1602                                 if (cqe->sop_drop_qpn !=
1603                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1604                                         uint32_t mark = cqe->sop_drop_qpn;
1605
1606                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1607                                         pkt->hash.fdir.hi =
1608                                                 mlx5_flow_mark_get(mark);
1609                                 }
1610                         }
1611                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1612                             rxq->crc_present) {
1613                                 if (rxq->csum) {
1614                                         pkt->packet_type =
1615                                                 rxq_cq_to_pkt_type(cqe);
1616                                         pkt->ol_flags |=
1617                                                 rxq_cq_to_ol_flags(rxq, cqe);
1618                                 }
1619                                 if (ntohs(cqe->hdr_type_etc) &
1620                                     MLX5_CQE_VLAN_STRIPPED) {
1621                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
1622                                                 PKT_RX_VLAN_STRIPPED;
1623                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
1624                                 }
1625                                 if (rxq->crc_present)
1626                                         len -= ETHER_CRC_LEN;
1627                         }
1628                         PKT_LEN(pkt) = len;
1629                 }
1630                 DATA_LEN(rep) = DATA_LEN(seg);
1631                 PKT_LEN(rep) = PKT_LEN(seg);
1632                 SET_DATA_OFF(rep, DATA_OFF(seg));
1633                 NB_SEGS(rep) = NB_SEGS(seg);
1634                 PORT(rep) = PORT(seg);
1635                 NEXT(rep) = NULL;
1636                 (*rxq->elts)[idx] = rep;
1637                 /*
1638                  * Fill NIC descriptor with the new buffer.  The lkey and size
1639                  * of the buffers are already known, only the buffer address
1640                  * changes.
1641                  */
1642                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1643                 if (len > DATA_LEN(seg)) {
1644                         len -= DATA_LEN(seg);
1645                         ++NB_SEGS(pkt);
1646                         ++rq_ci;
1647                         continue;
1648                 }
1649                 DATA_LEN(seg) = len;
1650 #ifdef MLX5_PMD_SOFT_COUNTERS
1651                 /* Increment bytes counter. */
1652                 rxq->stats.ibytes += PKT_LEN(pkt);
1653 #endif
1654                 /* Return packet. */
1655                 *(pkts++) = pkt;
1656                 pkt = NULL;
1657                 --pkts_n;
1658                 ++i;
1659 skip:
1660                 /* Align consumer index to the next stride. */
1661                 rq_ci >>= sges_n;
1662                 ++rq_ci;
1663                 rq_ci <<= sges_n;
1664         }
1665         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1666                 return 0;
1667         /* Update the consumer index. */
1668         rxq->rq_ci = rq_ci >> sges_n;
1669         rte_wmb();
1670         *rxq->cq_db = htonl(rxq->cq_ci);
1671         rte_wmb();
1672         *rxq->rq_db = htonl(rxq->rq_ci);
1673 #ifdef MLX5_PMD_SOFT_COUNTERS
1674         /* Increment packets counter. */
1675         rxq->stats.ipackets += i;
1676 #endif
1677         return i;
1678 }
1679
1680 /**
1681  * Dummy DPDK callback for TX.
1682  *
1683  * This function is used to temporarily replace the real callback during
1684  * unsafe control operations on the queue, or in case of error.
1685  *
1686  * @param dpdk_txq
1687  *   Generic pointer to TX queue structure.
1688  * @param[in] pkts
1689  *   Packets to transmit.
1690  * @param pkts_n
1691  *   Number of packets in array.
1692  *
1693  * @return
1694  *   Number of packets successfully transmitted (<= pkts_n).
1695  */
1696 uint16_t
1697 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1698 {
1699         (void)dpdk_txq;
1700         (void)pkts;
1701         (void)pkts_n;
1702         return 0;
1703 }
1704
1705 /**
1706  * Dummy DPDK callback for RX.
1707  *
1708  * This function is used to temporarily replace the real callback during
1709  * unsafe control operations on the queue, or in case of error.
1710  *
1711  * @param dpdk_rxq
1712  *   Generic pointer to RX queue structure.
1713  * @param[out] pkts
1714  *   Array to store received packets.
1715  * @param pkts_n
1716  *   Maximum number of packets in array.
1717  *
1718  * @return
1719  *   Number of packets successfully received (<= pkts_n).
1720  */
1721 uint16_t
1722 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1723 {
1724         (void)dpdk_rxq;
1725         (void)pkts;
1726         (void)pkts_n;
1727         return 0;
1728 }