4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq) __attribute__((always_inline));
87 static inline uint32_t
88 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
89 __attribute__((always_inline));
92 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, uint32_t *rss_hash)
94 __attribute__((always_inline));
96 static inline uint32_t
97 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
98 __attribute__((always_inline));
103 * Verify or set magic value in CQE.
112 check_cqe_seen(volatile struct mlx5_cqe *cqe)
114 static const uint8_t magic[] = "seen";
115 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
119 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
120 if (!ret || (*buf)[i] != magic[i]) {
122 (*buf)[i] = magic[i];
130 * Check whether CQE is valid.
135 * Size of completion queue.
140 * 0 on success, 1 on failure.
143 check_cqe(volatile struct mlx5_cqe *cqe,
144 unsigned int cqes_n, const uint16_t ci)
146 uint16_t idx = ci & cqes_n;
147 uint8_t op_own = cqe->op_own;
148 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
149 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
151 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
152 return 1; /* No CQE. */
154 if ((op_code == MLX5_CQE_RESP_ERR) ||
155 (op_code == MLX5_CQE_REQ_ERR)) {
156 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
157 uint8_t syndrome = err_cqe->syndrome;
159 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
160 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
162 if (!check_cqe_seen(cqe))
163 ERROR("unexpected CQE error %u (0x%02x)"
165 op_code, op_code, syndrome);
167 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
168 (op_code != MLX5_CQE_REQ)) {
169 if (!check_cqe_seen(cqe))
170 ERROR("unexpected CQE opcode %u (0x%02x)",
179 * Return the address of the WQE.
182 * Pointer to TX queue structure.
184 * WQE consumer index.
189 static inline uintptr_t *
190 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
192 ci &= ((1 << txq->wqe_n) - 1);
193 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
197 * Manage TX completions.
199 * When sending a burst, mlx5_tx_burst() posts several WRs.
202 * Pointer to TX queue structure.
205 txq_complete(struct txq *txq)
207 const unsigned int elts_n = 1 << txq->elts_n;
208 const unsigned int cqe_n = 1 << txq->cqe_n;
209 const unsigned int cqe_cnt = cqe_n - 1;
210 uint16_t elts_free = txq->elts_tail;
212 uint16_t cq_ci = txq->cq_ci;
213 volatile struct mlx5_cqe *cqe = NULL;
214 volatile struct mlx5_wqe_ctrl *ctrl;
217 volatile struct mlx5_cqe *tmp;
219 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
220 if (check_cqe(tmp, cqe_n, cq_ci))
224 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
225 if (!check_cqe_seen(cqe))
226 ERROR("unexpected compressed CQE, TX stopped");
229 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
230 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
231 if (!check_cqe_seen(cqe))
232 ERROR("unexpected error CQE, TX stopped");
238 if (unlikely(cqe == NULL))
240 ctrl = (volatile struct mlx5_wqe_ctrl *)
241 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
242 elts_tail = ctrl->ctrl3;
243 assert(elts_tail < (1 << txq->wqe_n));
245 while (elts_free != elts_tail) {
246 struct rte_mbuf *elt = (*txq->elts)[elts_free];
247 unsigned int elts_free_next =
248 (elts_free + 1) & (elts_n - 1);
249 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
253 memset(&(*txq->elts)[elts_free],
255 sizeof((*txq->elts)[elts_free]));
257 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
258 /* Only one segment needs to be freed. */
259 rte_pktmbuf_free_seg(elt);
260 elts_free = elts_free_next;
263 txq->elts_tail = elts_tail;
264 /* Update the consumer index. */
266 *txq->cq_db = htonl(cq_ci);
270 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
271 * the cloned mbuf is allocated is returned instead.
277 * Memory pool where data is located for given mbuf.
279 static struct rte_mempool *
280 txq_mb2mp(struct rte_mbuf *buf)
282 if (unlikely(RTE_MBUF_INDIRECT(buf)))
283 return rte_mbuf_from_indirect(buf)->pool;
288 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
289 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
290 * remove an entry first.
293 * Pointer to TX queue structure.
295 * Memory Pool for which a Memory Region lkey must be returned.
298 * mr->lkey on success, (uint32_t)-1 on failure.
300 static inline uint32_t
301 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
304 uint32_t lkey = (uint32_t)-1;
306 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
307 if (unlikely(txq->mp2mr[i].mp == NULL)) {
308 /* Unknown MP, add a new MR for it. */
311 if (txq->mp2mr[i].mp == mp) {
312 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
313 assert(htonl(txq->mp2mr[i].mr->lkey) ==
315 lkey = txq->mp2mr[i].lkey;
319 if (unlikely(lkey == (uint32_t)-1))
320 lkey = txq_mp2mr_reg(txq, mp, i);
325 * Ring TX queue doorbell.
328 * Pointer to TX queue structure.
331 mlx5_tx_dbrec(struct txq *txq)
333 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
335 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
336 htonl(txq->qp_num_8s),
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
344 memcpy(dst, (uint8_t *)data, 16);
345 txq->bf_offset ^= (1 << txq->bf_buf_size);
349 * DPDK callback for TX.
352 * Generic pointer to TX queue structure.
354 * Packets to transmit.
356 * Number of packets in array.
359 * Number of packets successfully transmitted (<= pkts_n).
362 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
364 struct txq *txq = (struct txq *)dpdk_txq;
365 uint16_t elts_head = txq->elts_head;
366 const unsigned int elts_n = 1 << txq->elts_n;
371 volatile struct mlx5_wqe_v *wqe = NULL;
372 unsigned int segs_n = 0;
373 struct rte_mbuf *buf = NULL;
376 if (unlikely(!pkts_n))
378 /* Prefetch first packet cacheline. */
379 rte_prefetch0(*pkts);
380 /* Start processing. */
382 max = (elts_n - (elts_head - txq->elts_tail));
386 volatile rte_v128u32_t *dseg = NULL;
391 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
393 uint8_t cs_flags = 0;
394 #ifdef MLX5_PMD_SOFT_COUNTERS
395 uint32_t total_length = 0;
400 segs_n = buf->nb_segs;
402 * Make sure there is enough room to store this packet and
403 * that one ring entry remains unused.
406 if (max < segs_n + 1)
412 wqe = (volatile struct mlx5_wqe_v *)
413 tx_mlx5_wqe(txq, txq->wqe_ci);
414 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
416 rte_prefetch0(*pkts);
417 addr = rte_pktmbuf_mtod(buf, uintptr_t);
418 length = DATA_LEN(buf);
419 ehdr = (((uint8_t *)addr)[1] << 8) |
420 ((uint8_t *)addr)[0];
421 #ifdef MLX5_PMD_SOFT_COUNTERS
422 total_length = length;
424 assert(length >= MLX5_WQE_DWORD_SIZE);
425 /* Update element. */
426 (*txq->elts)[elts_head] = buf;
427 elts_head = (elts_head + 1) & (elts_n - 1);
428 /* Prefetch next buffer data. */
430 volatile void *pkt_addr;
432 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
433 rte_prefetch0(pkt_addr);
435 /* Should we enable HW CKSUM offload */
437 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
438 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
440 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
442 * Start by copying the Ethernet header minus the first two
443 * bytes which will be appended at the end of the Ethernet
446 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
447 length -= MLX5_WQE_DWORD_SIZE;
448 addr += MLX5_WQE_DWORD_SIZE;
449 /* Replace the Ethernet type by the VLAN if necessary. */
450 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
451 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
453 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
455 &vlan, sizeof(vlan));
456 addr -= sizeof(vlan);
457 length += sizeof(vlan);
459 /* Inline if enough room. */
460 if (txq->max_inline != 0) {
461 uintptr_t end = (uintptr_t)
462 (((uintptr_t)txq->wqes) +
463 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
464 uint16_t max_inline =
465 txq->max_inline * RTE_CACHE_LINE_SIZE;
469 * raw starts two bytes before the boundary to
470 * continue the above copy of packet data.
472 raw += MLX5_WQE_DWORD_SIZE - 2;
473 room = end - (uintptr_t)raw;
474 if (room > max_inline) {
475 uintptr_t addr_end = (addr + max_inline) &
476 ~(RTE_CACHE_LINE_SIZE - 1);
477 uint16_t copy_b = ((addr_end - addr) > length) ?
481 rte_memcpy((void *)raw, (void *)addr, copy_b);
484 pkt_inline_sz += copy_b;
486 assert(addr <= addr_end);
489 * 2 DWORDs consumed by the WQE header + 1 DSEG +
490 * the size of the inline part of the packet.
492 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
494 dseg = (volatile rte_v128u32_t *)
496 (ds * MLX5_WQE_DWORD_SIZE));
497 if ((uintptr_t)dseg >= end)
498 dseg = (volatile rte_v128u32_t *)
501 } else if (!segs_n) {
508 * No inline has been done in the packet, only the
509 * Ethernet Header as been stored.
511 dseg = (volatile rte_v128u32_t *)
512 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
515 /* Add the remaining packet as a simple ds. */
516 naddr = htonll(addr);
517 *dseg = (rte_v128u32_t){
519 txq_mp2mr(txq, txq_mb2mp(buf)),
532 * Spill on next WQE when the current one does not have
533 * enough room left. Size of WQE must a be a multiple
534 * of data segment size.
536 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
537 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
538 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
539 ((1 << txq->wqe_n) - 1);
541 dseg = (volatile rte_v128u32_t *)
543 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
550 length = DATA_LEN(buf);
551 #ifdef MLX5_PMD_SOFT_COUNTERS
552 total_length += length;
554 /* Store segment information. */
555 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
556 *dseg = (rte_v128u32_t){
558 txq_mp2mr(txq, txq_mb2mp(buf)),
562 (*txq->elts)[elts_head] = buf;
563 elts_head = (elts_head + 1) & (elts_n - 1);
572 /* Initialize known and common part of the WQE structure. */
573 wqe->ctrl = (rte_v128u32_t){
574 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
575 htonl(txq->qp_num_8s | ds),
579 wqe->eseg = (rte_v128u32_t){
583 (ehdr << 16) | htons(pkt_inline_sz),
585 txq->wqe_ci += (ds + 3) / 4;
586 #ifdef MLX5_PMD_SOFT_COUNTERS
587 /* Increment sent bytes counter. */
588 txq->stats.obytes += total_length;
591 /* Take a shortcut if nothing must be sent. */
592 if (unlikely(i == 0))
594 /* Check whether completion threshold has been reached. */
595 comp = txq->elts_comp + i + j;
596 if (comp >= MLX5_TX_COMP_THRESH) {
597 volatile struct mlx5_wqe_ctrl *w =
598 (volatile struct mlx5_wqe_ctrl *)wqe;
600 /* Request completion on last WQE. */
602 /* Save elts_head in unused "immediate" field of WQE. */
603 w->ctrl3 = elts_head;
606 txq->elts_comp = comp;
608 #ifdef MLX5_PMD_SOFT_COUNTERS
609 /* Increment sent packets counter. */
610 txq->stats.opackets += i;
612 /* Ring QP doorbell. */
614 txq->elts_head = elts_head;
619 * Open a MPW session.
622 * Pointer to TX queue structure.
624 * Pointer to MPW session structure.
629 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
631 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
632 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
633 (volatile struct mlx5_wqe_data_seg (*)[])
634 tx_mlx5_wqe(txq, idx + 1);
636 mpw->state = MLX5_MPW_STATE_OPENED;
640 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
641 mpw->wqe->eseg.mss = htons(length);
642 mpw->wqe->eseg.inline_hdr_sz = 0;
643 mpw->wqe->eseg.rsvd0 = 0;
644 mpw->wqe->eseg.rsvd1 = 0;
645 mpw->wqe->eseg.rsvd2 = 0;
646 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
647 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
648 mpw->wqe->ctrl[2] = 0;
649 mpw->wqe->ctrl[3] = 0;
650 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
651 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
652 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
653 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
654 mpw->data.dseg[2] = &(*dseg)[0];
655 mpw->data.dseg[3] = &(*dseg)[1];
656 mpw->data.dseg[4] = &(*dseg)[2];
660 * Close a MPW session.
663 * Pointer to TX queue structure.
665 * Pointer to MPW session structure.
668 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
670 unsigned int num = mpw->pkts_n;
673 * Store size in multiple of 16 bytes. Control and Ethernet segments
676 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
677 mpw->state = MLX5_MPW_STATE_CLOSED;
682 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
683 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
687 * DPDK callback for TX with MPW support.
690 * Generic pointer to TX queue structure.
692 * Packets to transmit.
694 * Number of packets in array.
697 * Number of packets successfully transmitted (<= pkts_n).
700 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
702 struct txq *txq = (struct txq *)dpdk_txq;
703 uint16_t elts_head = txq->elts_head;
704 const unsigned int elts_n = 1 << txq->elts_n;
709 struct mlx5_mpw mpw = {
710 .state = MLX5_MPW_STATE_CLOSED,
713 if (unlikely(!pkts_n))
715 /* Prefetch first packet cacheline. */
716 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
717 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
718 /* Start processing. */
720 max = (elts_n - (elts_head - txq->elts_tail));
724 struct rte_mbuf *buf = *(pkts++);
725 unsigned int elts_head_next;
727 unsigned int segs_n = buf->nb_segs;
728 uint32_t cs_flags = 0;
731 * Make sure there is enough room to store this packet and
732 * that one ring entry remains unused.
735 if (max < segs_n + 1)
737 /* Do not bother with large packets MPW cannot handle. */
738 if (segs_n > MLX5_MPW_DSEG_MAX)
742 /* Should we enable HW CKSUM offload */
744 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
745 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
746 /* Retrieve packet information. */
747 length = PKT_LEN(buf);
749 /* Start new session if packet differs. */
750 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
751 ((mpw.len != length) ||
753 (mpw.wqe->eseg.cs_flags != cs_flags)))
754 mlx5_mpw_close(txq, &mpw);
755 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
756 mlx5_mpw_new(txq, &mpw, length);
757 mpw.wqe->eseg.cs_flags = cs_flags;
759 /* Multi-segment packets must be alone in their MPW. */
760 assert((segs_n == 1) || (mpw.pkts_n == 0));
761 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
765 volatile struct mlx5_wqe_data_seg *dseg;
768 elts_head_next = (elts_head + 1) & (elts_n - 1);
770 (*txq->elts)[elts_head] = buf;
771 dseg = mpw.data.dseg[mpw.pkts_n];
772 addr = rte_pktmbuf_mtod(buf, uintptr_t);
773 *dseg = (struct mlx5_wqe_data_seg){
774 .byte_count = htonl(DATA_LEN(buf)),
775 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
776 .addr = htonll(addr),
778 elts_head = elts_head_next;
779 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
780 length += DATA_LEN(buf);
786 assert(length == mpw.len);
787 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
788 mlx5_mpw_close(txq, &mpw);
789 elts_head = elts_head_next;
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 /* Increment sent bytes counter. */
792 txq->stats.obytes += length;
796 /* Take a shortcut if nothing must be sent. */
797 if (unlikely(i == 0))
799 /* Check whether completion threshold has been reached. */
800 /* "j" includes both packets and segments. */
801 comp = txq->elts_comp + j;
802 if (comp >= MLX5_TX_COMP_THRESH) {
803 volatile struct mlx5_wqe *wqe = mpw.wqe;
805 /* Request completion on last WQE. */
806 wqe->ctrl[2] = htonl(8);
807 /* Save elts_head in unused "immediate" field of WQE. */
808 wqe->ctrl[3] = elts_head;
811 txq->elts_comp = comp;
813 #ifdef MLX5_PMD_SOFT_COUNTERS
814 /* Increment sent packets counter. */
815 txq->stats.opackets += i;
817 /* Ring QP doorbell. */
818 if (mpw.state == MLX5_MPW_STATE_OPENED)
819 mlx5_mpw_close(txq, &mpw);
821 txq->elts_head = elts_head;
826 * Open a MPW inline session.
829 * Pointer to TX queue structure.
831 * Pointer to MPW session structure.
836 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
838 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
839 struct mlx5_wqe_inl_small *inl;
841 mpw->state = MLX5_MPW_INL_STATE_OPENED;
845 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
846 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
849 mpw->wqe->ctrl[2] = 0;
850 mpw->wqe->ctrl[3] = 0;
851 mpw->wqe->eseg.mss = htons(length);
852 mpw->wqe->eseg.inline_hdr_sz = 0;
853 mpw->wqe->eseg.cs_flags = 0;
854 mpw->wqe->eseg.rsvd0 = 0;
855 mpw->wqe->eseg.rsvd1 = 0;
856 mpw->wqe->eseg.rsvd2 = 0;
857 inl = (struct mlx5_wqe_inl_small *)
858 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
859 mpw->data.raw = (uint8_t *)&inl->raw;
863 * Close a MPW inline session.
866 * Pointer to TX queue structure.
868 * Pointer to MPW session structure.
871 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
874 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
875 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
877 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
879 * Store size in multiple of 16 bytes. Control and Ethernet segments
882 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
883 mpw->state = MLX5_MPW_STATE_CLOSED;
884 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
885 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
889 * DPDK callback for TX with MPW inline support.
892 * Generic pointer to TX queue structure.
894 * Packets to transmit.
896 * Number of packets in array.
899 * Number of packets successfully transmitted (<= pkts_n).
902 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
905 struct txq *txq = (struct txq *)dpdk_txq;
906 uint16_t elts_head = txq->elts_head;
907 const unsigned int elts_n = 1 << txq->elts_n;
912 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
913 struct mlx5_mpw mpw = {
914 .state = MLX5_MPW_STATE_CLOSED,
917 if (unlikely(!pkts_n))
919 /* Prefetch first packet cacheline. */
920 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
921 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
922 /* Start processing. */
924 max = (elts_n - (elts_head - txq->elts_tail));
928 struct rte_mbuf *buf = *(pkts++);
929 unsigned int elts_head_next;
932 unsigned int segs_n = buf->nb_segs;
933 uint32_t cs_flags = 0;
936 * Make sure there is enough room to store this packet and
937 * that one ring entry remains unused.
940 if (max < segs_n + 1)
942 /* Do not bother with large packets MPW cannot handle. */
943 if (segs_n > MLX5_MPW_DSEG_MAX)
947 /* Should we enable HW CKSUM offload */
949 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
950 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
951 /* Retrieve packet information. */
952 length = PKT_LEN(buf);
953 /* Start new session if packet differs. */
954 if (mpw.state == MLX5_MPW_STATE_OPENED) {
955 if ((mpw.len != length) ||
957 (mpw.wqe->eseg.cs_flags != cs_flags))
958 mlx5_mpw_close(txq, &mpw);
959 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
960 if ((mpw.len != length) ||
962 (length > inline_room) ||
963 (mpw.wqe->eseg.cs_flags != cs_flags)) {
964 mlx5_mpw_inline_close(txq, &mpw);
966 txq->max_inline * RTE_CACHE_LINE_SIZE;
969 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
971 (length > inline_room)) {
972 mlx5_mpw_new(txq, &mpw, length);
973 mpw.wqe->eseg.cs_flags = cs_flags;
975 mlx5_mpw_inline_new(txq, &mpw, length);
976 mpw.wqe->eseg.cs_flags = cs_flags;
979 /* Multi-segment packets must be alone in their MPW. */
980 assert((segs_n == 1) || (mpw.pkts_n == 0));
981 if (mpw.state == MLX5_MPW_STATE_OPENED) {
982 assert(inline_room ==
983 txq->max_inline * RTE_CACHE_LINE_SIZE);
984 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
988 volatile struct mlx5_wqe_data_seg *dseg;
991 (elts_head + 1) & (elts_n - 1);
993 (*txq->elts)[elts_head] = buf;
994 dseg = mpw.data.dseg[mpw.pkts_n];
995 addr = rte_pktmbuf_mtod(buf, uintptr_t);
996 *dseg = (struct mlx5_wqe_data_seg){
997 .byte_count = htonl(DATA_LEN(buf)),
998 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
999 .addr = htonll(addr),
1001 elts_head = elts_head_next;
1002 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1003 length += DATA_LEN(buf);
1009 assert(length == mpw.len);
1010 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1011 mlx5_mpw_close(txq, &mpw);
1015 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1016 assert(length <= inline_room);
1017 assert(length == DATA_LEN(buf));
1018 elts_head_next = (elts_head + 1) & (elts_n - 1);
1019 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1020 (*txq->elts)[elts_head] = buf;
1021 /* Maximum number of bytes before wrapping. */
1022 max = ((((uintptr_t)(txq->wqes)) +
1025 (uintptr_t)mpw.data.raw);
1027 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1030 mpw.data.raw = (volatile void *)txq->wqes;
1031 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1032 (void *)(addr + max),
1034 mpw.data.raw += length - max;
1036 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1039 mpw.data.raw += length;
1041 if ((uintptr_t)mpw.data.raw ==
1042 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1043 mpw.data.raw = (volatile void *)txq->wqes;
1046 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1047 mlx5_mpw_inline_close(txq, &mpw);
1049 txq->max_inline * RTE_CACHE_LINE_SIZE;
1051 inline_room -= length;
1054 mpw.total_len += length;
1055 elts_head = elts_head_next;
1056 #ifdef MLX5_PMD_SOFT_COUNTERS
1057 /* Increment sent bytes counter. */
1058 txq->stats.obytes += length;
1062 /* Take a shortcut if nothing must be sent. */
1063 if (unlikely(i == 0))
1065 /* Check whether completion threshold has been reached. */
1066 /* "j" includes both packets and segments. */
1067 comp = txq->elts_comp + j;
1068 if (comp >= MLX5_TX_COMP_THRESH) {
1069 volatile struct mlx5_wqe *wqe = mpw.wqe;
1071 /* Request completion on last WQE. */
1072 wqe->ctrl[2] = htonl(8);
1073 /* Save elts_head in unused "immediate" field of WQE. */
1074 wqe->ctrl[3] = elts_head;
1077 txq->elts_comp = comp;
1079 #ifdef MLX5_PMD_SOFT_COUNTERS
1080 /* Increment sent packets counter. */
1081 txq->stats.opackets += i;
1083 /* Ring QP doorbell. */
1084 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1085 mlx5_mpw_inline_close(txq, &mpw);
1086 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1087 mlx5_mpw_close(txq, &mpw);
1089 txq->elts_head = elts_head;
1094 * Translate RX completion flags to packet type.
1099 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1102 * Packet type for struct rte_mbuf.
1104 static inline uint32_t
1105 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1108 uint8_t flags = cqe->l4_hdr_type_etc;
1110 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1113 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1114 RTE_PTYPE_L3_IPV4) |
1116 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1117 RTE_PTYPE_L3_IPV6) |
1119 MLX5_CQE_RX_IPV4_PACKET,
1120 RTE_PTYPE_INNER_L3_IPV4) |
1122 MLX5_CQE_RX_IPV6_PACKET,
1123 RTE_PTYPE_INNER_L3_IPV6);
1127 MLX5_CQE_L3_HDR_TYPE_IPV6,
1128 RTE_PTYPE_L3_IPV6) |
1130 MLX5_CQE_L3_HDR_TYPE_IPV4,
1136 * Get size of the next packet for a given CQE. For compressed CQEs, the
1137 * consumer index is updated only once all packets of the current one have
1141 * Pointer to RX queue.
1144 * @param[out] rss_hash
1145 * Packet RSS Hash result.
1148 * Packet size in bytes (0 if there is none), -1 in case of completion
1152 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1153 uint16_t cqe_cnt, uint32_t *rss_hash)
1155 struct rxq_zip *zip = &rxq->zip;
1156 uint16_t cqe_n = cqe_cnt + 1;
1159 /* Process compressed data in the CQE and mini arrays. */
1161 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1162 (volatile struct mlx5_mini_cqe8 (*)[8])
1163 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1165 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1166 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1167 if ((++zip->ai & 7) == 0) {
1169 * Increment consumer index to skip the number of
1170 * CQEs consumed. Hardware leaves holes in the CQ
1171 * ring for software use.
1176 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1177 uint16_t idx = rxq->cq_ci + 1;
1178 uint16_t end = zip->cq_ci;
1180 while (idx != end) {
1181 (*rxq->cqes)[idx & cqe_cnt].op_own =
1182 MLX5_CQE_INVALIDATE;
1185 rxq->cq_ci = zip->cq_ci;
1188 /* No compressed data, get next CQE and verify if it is compressed. */
1193 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1194 if (unlikely(ret == 1))
1197 op_own = cqe->op_own;
1198 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1199 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1200 (volatile struct mlx5_mini_cqe8 (*)[8])
1201 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1204 /* Fix endianness. */
1205 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1207 * Current mini array position is the one returned by
1210 * If completion comprises several mini arrays, as a
1211 * special case the second one is located 7 CQEs after
1212 * the initial CQE instead of 8 for subsequent ones.
1214 zip->ca = rxq->cq_ci & cqe_cnt;
1215 zip->na = zip->ca + 7;
1216 /* Compute the next non compressed CQE. */
1218 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1219 /* Get packet size to return. */
1220 len = ntohl((*mc)[0].byte_cnt);
1221 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1224 len = ntohl(cqe->byte_cnt);
1225 *rss_hash = ntohl(cqe->rx_hash_res);
1227 /* Error while receiving packet. */
1228 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1235 * Translate RX completion flags to offload flags.
1238 * Pointer to RX queue structure.
1243 * Offload flags (ol_flags) for struct rte_mbuf.
1245 static inline uint32_t
1246 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1248 uint32_t ol_flags = 0;
1249 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1250 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1252 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1253 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1254 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1256 PKT_RX_IP_CKSUM_GOOD);
1257 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1258 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1259 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1260 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1261 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1263 PKT_RX_L4_CKSUM_GOOD);
1264 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1266 TRANSPOSE(cqe->l4_hdr_type_etc,
1267 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1268 PKT_RX_IP_CKSUM_GOOD) |
1269 TRANSPOSE(cqe->l4_hdr_type_etc,
1270 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1271 PKT_RX_L4_CKSUM_GOOD);
1276 * DPDK callback for RX.
1279 * Generic pointer to RX queue structure.
1281 * Array to store received packets.
1283 * Maximum number of packets in array.
1286 * Number of packets successfully received (<= pkts_n).
1289 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1291 struct rxq *rxq = dpdk_rxq;
1292 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1293 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1294 const unsigned int sges_n = rxq->sges_n;
1295 struct rte_mbuf *pkt = NULL;
1296 struct rte_mbuf *seg = NULL;
1297 volatile struct mlx5_cqe *cqe =
1298 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1300 unsigned int rq_ci = rxq->rq_ci << sges_n;
1301 int len; /* keep its value across iterations. */
1304 unsigned int idx = rq_ci & wqe_cnt;
1305 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1306 struct rte_mbuf *rep = (*rxq->elts)[idx];
1307 uint32_t rss_hash_res = 0;
1315 rep = rte_mbuf_raw_alloc(rxq->mp);
1316 if (unlikely(rep == NULL)) {
1317 ++rxq->stats.rx_nombuf;
1320 * no buffers before we even started,
1321 * bail out silently.
1325 while (pkt != seg) {
1326 assert(pkt != (*rxq->elts)[idx]);
1328 rte_mbuf_refcnt_set(pkt, 0);
1329 __rte_mbuf_raw_free(pkt);
1335 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1336 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1339 rte_mbuf_refcnt_set(rep, 0);
1340 __rte_mbuf_raw_free(rep);
1343 if (unlikely(len == -1)) {
1344 /* RX error, packet is likely too large. */
1345 rte_mbuf_refcnt_set(rep, 0);
1346 __rte_mbuf_raw_free(rep);
1347 ++rxq->stats.idropped;
1351 assert(len >= (rxq->crc_present << 2));
1352 /* Update packet information. */
1353 pkt->packet_type = 0;
1355 if (rss_hash_res && rxq->rss_hash) {
1356 pkt->hash.rss = rss_hash_res;
1357 pkt->ol_flags = PKT_RX_RSS_HASH;
1360 ((cqe->sop_drop_qpn !=
1361 htonl(MLX5_FLOW_MARK_INVALID)) ||
1362 (cqe->sop_drop_qpn !=
1363 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1365 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1366 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1367 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1369 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1373 rxq_cq_to_pkt_type(cqe);
1375 rxq_cq_to_ol_flags(rxq, cqe);
1377 if (cqe->l4_hdr_type_etc &
1378 MLX5_CQE_VLAN_STRIPPED) {
1379 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1380 PKT_RX_VLAN_STRIPPED;
1381 pkt->vlan_tci = ntohs(cqe->vlan_info);
1383 if (rxq->crc_present)
1384 len -= ETHER_CRC_LEN;
1388 DATA_LEN(rep) = DATA_LEN(seg);
1389 PKT_LEN(rep) = PKT_LEN(seg);
1390 SET_DATA_OFF(rep, DATA_OFF(seg));
1391 NB_SEGS(rep) = NB_SEGS(seg);
1392 PORT(rep) = PORT(seg);
1394 (*rxq->elts)[idx] = rep;
1396 * Fill NIC descriptor with the new buffer. The lkey and size
1397 * of the buffers are already known, only the buffer address
1400 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1401 if (len > DATA_LEN(seg)) {
1402 len -= DATA_LEN(seg);
1407 DATA_LEN(seg) = len;
1408 #ifdef MLX5_PMD_SOFT_COUNTERS
1409 /* Increment bytes counter. */
1410 rxq->stats.ibytes += PKT_LEN(pkt);
1412 /* Return packet. */
1418 /* Align consumer index to the next stride. */
1423 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1425 /* Update the consumer index. */
1426 rxq->rq_ci = rq_ci >> sges_n;
1428 *rxq->cq_db = htonl(rxq->cq_ci);
1430 *rxq->rq_db = htonl(rxq->rq_ci);
1431 #ifdef MLX5_PMD_SOFT_COUNTERS
1432 /* Increment packets counter. */
1433 rxq->stats.ipackets += i;
1439 * Dummy DPDK callback for TX.
1441 * This function is used to temporarily replace the real callback during
1442 * unsafe control operations on the queue, or in case of error.
1445 * Generic pointer to TX queue structure.
1447 * Packets to transmit.
1449 * Number of packets in array.
1452 * Number of packets successfully transmitted (<= pkts_n).
1455 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1464 * Dummy DPDK callback for RX.
1466 * This function is used to temporarily replace the real callback during
1467 * unsafe control operations on the queue, or in case of error.
1470 * Generic pointer to RX queue structure.
1472 * Array to store received packets.
1474 * Maximum number of packets in array.
1477 * Number of packets successfully received (<= pkts_n).
1480 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)