drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 #include <rte_mbuf.h>
  52 #include <rte_mempool.h>
  53 #include <rte_prefetch.h>
  54 #include <rte_common.h>
  55 #include <rte_branch_prediction.h>
  56 #include <rte_ether.h>
  57
  58 #include "mlx5.h"
  59 #include "mlx5_utils.h"
  60 #include "mlx5_rxtx.h"
  61 #include "mlx5_autoconf.h"
  62 #include "mlx5_defs.h"
  63 #include "mlx5_prm.h"
  64
  65 static __rte_always_inline uint32_t
  66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  67
  68 static __rte_always_inline int
  69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  70                  uint16_t cqe_cnt, uint32_t *rss_hash);
  71
  72 static __rte_always_inline uint32_t
  73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  74
  75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  76         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  77 };
  78
  79 /**
  80  * Build a table to translate Rx completion flags to packet type.
  81  *
  82  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  83  */
  84 void
  85 mlx5_set_ptype_table(void)
  86 {
  87         unsigned int i;
  88         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  89
  90         /* Last entry must not be overwritten, reserved for errored packet. */
  91         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  92                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  93         /*
  94          * The index to the array should have:
  95          * bit[1:0] = l3_hdr_type
  96          * bit[4:2] = l4_hdr_type
  97          * bit[5] = ip_frag
  98          * bit[6] = tunneled
  99          * bit[7] = outer_l3_type
 100          */
 101         /* L3 */
 102         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_NONFRAG;
 104         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_NONFRAG;
 106         /* Fragmented */
 107         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_FRAG;
 109         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_FRAG;
 111         /* TCP */
 112         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_TCP;
 114         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_TCP;
 116         /* UDP */
 117         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_UDP;
 119         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_UDP;
 121         /* Repeat with outer_l3_type being set. Just in case. */
 122         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_NONFRAG;
 124         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_NONFRAG;
 126         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_FRAG;
 128         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_FRAG;
 130         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L4_NONFRAG;
 148         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L4_NONFRAG;
 151         /* Tunneled - Fragmented */
 152         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 153                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L4_FRAG;
 155         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L4_FRAG;
 158         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L4_FRAG;
 161         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L4_FRAG;
 164         /* Tunneled - TCP */
 165         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 166                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 167                      RTE_PTYPE_L4_TCP;
 168         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_L4_TCP;
 171         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_L4_TCP;
 174         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_L4_TCP;
 177         /* Tunneled - UDP */
 178         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_L4_UDP;
 181         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_L4_UDP;
 184         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_L4_UDP;
 187         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_L4_UDP;
 190 }
 191
 192 /**
 193  * Return the size of tailroom of WQ.
 194  *
 195  * @param txq
 196  *   Pointer to TX queue structure.
 197  * @param addr
 198  *   Pointer to tail of WQ.
 199  *
 200  * @return
 201  *   Size of tailroom.
 202  */
 203 static inline size_t
 204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 205 {
 206         size_t tailroom;
 207         tailroom = (uintptr_t)(txq->wqes) +
 208                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 209                    (uintptr_t)addr;
 210         return tailroom;
 211 }
 212
 213 /**
 214  * Copy data to tailroom of circular queue.
 215  *
 216  * @param dst
 217  *   Pointer to destination.
 218  * @param src
 219  *   Pointer to source.
 220  * @param n
 221  *   Number of bytes to copy.
 222  * @param base
 223  *   Pointer to head of queue.
 224  * @param tailroom
 225  *   Size of tailroom from dst.
 226  *
 227  * @return
 228  *   Pointer after copied data.
 229  */
 230 static inline void *
 231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 232                 void *base, size_t tailroom)
 233 {
 234         void *ret;
 235
 236         if (n > tailroom) {
 237                 rte_memcpy(dst, src, tailroom);
 238                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 239                            n - tailroom);
 240                 ret = (uint8_t *)base + n - tailroom;
 241         } else {
 242                 rte_memcpy(dst, src, n);
 243                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 244         }
 245         return ret;
 246 }
 247
 248 /**
 249  * DPDK callback to check the status of a tx descriptor.
 250  *
 251  * @param tx_queue
 252  *   The tx queue.
 253  * @param[in] offset
 254  *   The index of the descriptor in the ring.
 255  *
 256  * @return
 257  *   The status of the tx descriptor.
 258  */
 259 int
 260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 261 {
 262         struct txq *txq = tx_queue;
 263         uint16_t used;
 264
 265         mlx5_tx_complete(txq);
 266         used = txq->elts_head - txq->elts_tail;
 267         if (offset < used)
 268                 return RTE_ETH_TX_DESC_FULL;
 269         return RTE_ETH_TX_DESC_DONE;
 270 }
 271
 272 /**
 273  * DPDK callback to check the status of a rx descriptor.
 274  *
 275  * @param rx_queue
 276  *   The rx queue.
 277  * @param[in] offset
 278  *   The index of the descriptor in the ring.
 279  *
 280  * @return
 281  *   The status of the tx descriptor.
 282  */
 283 int
 284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 285 {
 286         struct rxq *rxq = rx_queue;
 287         struct rxq_zip *zip = &rxq->zip;
 288         volatile struct mlx5_cqe *cqe;
 289         const unsigned int cqe_n = (1 << rxq->cqe_n);
 290         const unsigned int cqe_cnt = cqe_n - 1;
 291         unsigned int cq_ci;
 292         unsigned int used;
 293
 294         /* if we are processing a compressed cqe */
 295         if (zip->ai) {
 296                 used = zip->cqe_cnt - zip->ca;
 297                 cq_ci = zip->cq_ci;
 298         } else {
 299                 used = 0;
 300                 cq_ci = rxq->cq_ci;
 301         }
 302         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 303         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 304                 int8_t op_own;
 305                 unsigned int n;
 306
 307                 op_own = cqe->op_own;
 308                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 309                         n = ntohl(cqe->byte_cnt);
 310                 else
 311                         n = 1;
 312                 cq_ci += n;
 313                 used += n;
 314                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 315         }
 316         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 317         if (offset < used)
 318                 return RTE_ETH_RX_DESC_DONE;
 319         return RTE_ETH_RX_DESC_AVAIL;
 320 }
 321
 322 /**
 323  * DPDK callback for TX.
 324  *
 325  * @param dpdk_txq
 326  *   Generic pointer to TX queue structure.
 327  * @param[in] pkts
 328  *   Packets to transmit.
 329  * @param pkts_n
 330  *   Number of packets in array.
 331  *
 332  * @return
 333  *   Number of packets successfully transmitted (<= pkts_n).
 334  */
 335 uint16_t
 336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 337 {
 338         struct txq *txq = (struct txq *)dpdk_txq;
 339         uint16_t elts_head = txq->elts_head;
 340         const uint16_t elts_n = 1 << txq->elts_n;
 341         const uint16_t elts_m = elts_n - 1;
 342         unsigned int i = 0;
 343         unsigned int j = 0;
 344         unsigned int k = 0;
 345         uint16_t max_elts;
 346         unsigned int max_inline = txq->max_inline;
 347         const unsigned int inline_en = !!max_inline && txq->inline_en;
 348         uint16_t max_wqe;
 349         unsigned int comp;
 350         volatile struct mlx5_wqe_v *wqe = NULL;
 351         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 352         unsigned int segs_n = 0;
 353         struct rte_mbuf *buf = NULL;
 354         uint8_t *raw;
 355
 356         if (unlikely(!pkts_n))
 357                 return 0;
 358         /* Prefetch first packet cacheline. */
 359         rte_prefetch0(*pkts);
 360         /* Start processing. */
 361         mlx5_tx_complete(txq);
 362         max_elts = (elts_n - (elts_head - txq->elts_tail));
 363         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 364         if (unlikely(!max_wqe))
 365                 return 0;
 366         do {
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint64_t naddr;
 373                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 374                 uint16_t tso_header_sz = 0;
 375                 uint16_t ehdr;
 376                 uint8_t cs_flags = 0;
 377                 uint64_t tso = 0;
 378                 uint16_t tso_segsz = 0;
 379 #ifdef MLX5_PMD_SOFT_COUNTERS
 380                 uint32_t total_length = 0;
 381 #endif
 382
 383                 /* first_seg */
 384                 buf = *pkts;
 385                 segs_n = buf->nb_segs;
 386                 /*
 387                  * Make sure there is enough room to store this packet and
 388                  * that one ring entry remains unused.
 389                  */
 390                 assert(segs_n);
 391                 if (max_elts < segs_n)
 392                         break;
 393                 max_elts -= segs_n;
 394                 --segs_n;
 395                 if (unlikely(--max_wqe == 0))
 396                         break;
 397                 wqe = (volatile struct mlx5_wqe_v *)
 398                         tx_mlx5_wqe(txq, txq->wqe_ci);
 399                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 400                 if (pkts_n - i > 1)
 401                         rte_prefetch0(*(pkts + 1));
 402                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 403                 length = DATA_LEN(buf);
 404                 ehdr = (((uint8_t *)addr)[1] << 8) |
 405                        ((uint8_t *)addr)[0];
 406 #ifdef MLX5_PMD_SOFT_COUNTERS
 407                 total_length = length;
 408 #endif
 409                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 410                         txq->stats.oerrors++;
 411                         break;
 412                 }
 413                 /* Update element. */
 414                 (*txq->elts)[elts_head & elts_m] = buf;
 415                 /* Prefetch next buffer data. */
 416                 if (pkts_n - i > 1)
 417                         rte_prefetch0(
 418                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 419                 /* Should we enable HW CKSUM offload */
 420                 if (buf->ol_flags &
 421                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 422                         const uint64_t is_tunneled = buf->ol_flags &
 423                                                      (PKT_TX_TUNNEL_GRE |
 424                                                       PKT_TX_TUNNEL_VXLAN);
 425
 426                         if (is_tunneled && txq->tunnel_en) {
 427                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 428                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 429                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 430                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 431                         } else {
 432                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 433                                            MLX5_ETH_WQE_L4_CSUM;
 434                         }
 435                 }
 436                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 437                 /* Replace the Ethernet type by the VLAN if necessary. */
 438                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 439                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 440                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 441
 442                         addr += 2;
 443                         length -= 2;
 444                         /* Copy Destination and source mac address. */
 445                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 446                         /* Copy VLAN. */
 447                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 448                         /* Copy missing two bytes to end the DSeg. */
 449                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 450                                ((uint8_t *)addr) + len, 2);
 451                         addr += len + 2;
 452                         length -= (len + 2);
 453                 } else {
 454                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 455                                MLX5_WQE_DWORD_SIZE);
 456                         length -= pkt_inline_sz;
 457                         addr += pkt_inline_sz;
 458                 }
 459                 raw += MLX5_WQE_DWORD_SIZE;
 460                 if (txq->tso_en) {
 461                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 462                         if (tso) {
 463                                 uintptr_t end = (uintptr_t)
 464                                                 (((uintptr_t)txq->wqes) +
 465                                                 (1 << txq->wqe_n) *
 466                                                 MLX5_WQE_SIZE);
 467                                 unsigned int copy_b;
 468                                 uint8_t vlan_sz = (buf->ol_flags &
 469                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 470                                 const uint64_t is_tunneled =
 471                                                         buf->ol_flags &
 472                                                         (PKT_TX_TUNNEL_GRE |
 473                                                          PKT_TX_TUNNEL_VXLAN);
 474
 475                                 tso_header_sz = buf->l2_len + vlan_sz +
 476                                                 buf->l3_len + buf->l4_len;
 477                                 tso_segsz = buf->tso_segsz;
 478
 479                                 if (is_tunneled && txq->tunnel_en) {
 480                                         tso_header_sz += buf->outer_l2_len +
 481                                                          buf->outer_l3_len;
 482                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 483                                 } else {
 484                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 485                                 }
 486                                 if (unlikely(tso_header_sz >
 487                                              MLX5_MAX_TSO_HEADER)) {
 488                                         txq->stats.oerrors++;
 489                                         break;
 490                                 }
 491                                 copy_b = tso_header_sz - pkt_inline_sz;
 492                                 /* First seg must contain all headers. */
 493                                 assert(copy_b <= length);
 494                                 if (copy_b &&
 495                                    ((end - (uintptr_t)raw) > copy_b)) {
 496                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 497                                                       1 + 3) / 4;
 498
 499                                         if (unlikely(max_wqe < n))
 500                                                 break;
 501                                         max_wqe -= n;
 502                                         rte_memcpy((void *)raw,
 503                                                    (void *)addr, copy_b);
 504                                         addr += copy_b;
 505                                         length -= copy_b;
 506                                         /* Include padding for TSO header. */
 507                                         copy_b = MLX5_WQE_DS(copy_b) *
 508                                                  MLX5_WQE_DWORD_SIZE;
 509                                         pkt_inline_sz += copy_b;
 510                                         raw += copy_b;
 511                                 } else {
 512                                         /* NOP WQE. */
 513                                         wqe->ctrl = (rte_v128u32_t){
 514                                                      htonl(txq->wqe_ci << 8),
 515                                                      htonl(txq->qp_num_8s | 1),
 516                                                      0,
 517                                                      0,
 518                                         };
 519                                         ds = 1;
 520                                         total_length = 0;
 521                                         k++;
 522                                         goto next_wqe;
 523                                 }
 524                         }
 525                 }
 526                 /* Inline if enough room. */
 527                 if (inline_en || tso) {
 528                         uint32_t inl;
 529                         uintptr_t end = (uintptr_t)
 530                                 (((uintptr_t)txq->wqes) +
 531                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 532                         unsigned int inline_room = max_inline *
 533                                                    RTE_CACHE_LINE_SIZE -
 534                                                    (pkt_inline_sz - 2) -
 535                                                    !!tso * sizeof(inl);
 536                         uintptr_t addr_end = (addr + inline_room) &
 537                                              ~(RTE_CACHE_LINE_SIZE - 1);
 538                         unsigned int copy_b = (addr_end > addr) ?
 539                                 RTE_MIN((addr_end - addr), length) :
 540                                 0;
 541
 542                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 543                                 /*
 544                                  * One Dseg remains in the current WQE.  To
 545                                  * keep the computation positive, it is
 546                                  * removed after the bytes to Dseg conversion.
 547                                  */
 548                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 549
 550                                 if (unlikely(max_wqe < n))
 551                                         break;
 552                                 max_wqe -= n;
 553                                 if (tso) {
 554                                         inl = htonl(copy_b | MLX5_INLINE_SEG);
 555                                         rte_memcpy((void *)raw,
 556                                                    (void *)&inl, sizeof(inl));
 557                                         raw += sizeof(inl);
 558                                         pkt_inline_sz += sizeof(inl);
 559                                 }
 560                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 561                                 addr += copy_b;
 562                                 length -= copy_b;
 563                                 pkt_inline_sz += copy_b;
 564                         }
 565                         /*
 566                          * 2 DWORDs consumed by the WQE header + ETH segment +
 567                          * the size of the inline part of the packet.
 568                          */
 569                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 570                         if (length > 0) {
 571                                 if (ds % (MLX5_WQE_SIZE /
 572                                           MLX5_WQE_DWORD_SIZE) == 0) {
 573                                         if (unlikely(--max_wqe == 0))
 574                                                 break;
 575                                         dseg = (volatile rte_v128u32_t *)
 576                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 577                                                            ds / 4);
 578                                 } else {
 579                                         dseg = (volatile rte_v128u32_t *)
 580                                                 ((uintptr_t)wqe +
 581                                                  (ds * MLX5_WQE_DWORD_SIZE));
 582                                 }
 583                                 goto use_dseg;
 584                         } else if (!segs_n) {
 585                                 goto next_pkt;
 586                         } else {
 587                                 /* dseg will be advance as part of next_seg */
 588                                 dseg = (volatile rte_v128u32_t *)
 589                                         ((uintptr_t)wqe +
 590                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 591                                 goto next_seg;
 592                         }
 593                 } else {
 594                         /*
 595                          * No inline has been done in the packet, only the
 596                          * Ethernet Header as been stored.
 597                          */
 598                         dseg = (volatile rte_v128u32_t *)
 599                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 600                         ds = 3;
 601 use_dseg:
 602                         /* Add the remaining packet as a simple ds. */
 603                         naddr = htonll(addr);
 604                         *dseg = (rte_v128u32_t){
 605                                 htonl(length),
 606                                 mlx5_tx_mb2mr(txq, buf),
 607                                 naddr,
 608                                 naddr >> 32,
 609                         };
 610                         ++ds;
 611                         if (!segs_n)
 612                                 goto next_pkt;
 613                 }
 614 next_seg:
 615                 assert(buf);
 616                 assert(ds);
 617                 assert(wqe);
 618                 /*
 619                  * Spill on next WQE when the current one does not have
 620                  * enough room left. Size of WQE must a be a multiple
 621                  * of data segment size.
 622                  */
 623                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 624                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 625                         if (unlikely(--max_wqe == 0))
 626                                 break;
 627                         dseg = (volatile rte_v128u32_t *)
 628                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 629                         rte_prefetch0(tx_mlx5_wqe(txq,
 630                                                   txq->wqe_ci + ds / 4 + 1));
 631                 } else {
 632                         ++dseg;
 633                 }
 634                 ++ds;
 635                 buf = buf->next;
 636                 assert(buf);
 637                 length = DATA_LEN(buf);
 638 #ifdef MLX5_PMD_SOFT_COUNTERS
 639                 total_length += length;
 640 #endif
 641                 /* Store segment information. */
 642                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 643                 *dseg = (rte_v128u32_t){
 644                         htonl(length),
 645                         mlx5_tx_mb2mr(txq, buf),
 646                         naddr,
 647                         naddr >> 32,
 648                 };
 649                 (*txq->elts)[++elts_head & elts_m] = buf;
 650                 ++sg;
 651                 /* Advance counter only if all segs are successfully posted. */
 652                 if (sg < segs_n)
 653                         goto next_seg;
 654                 else
 655                         j += sg;
 656 next_pkt:
 657                 ++elts_head;
 658                 ++pkts;
 659                 ++i;
 660                 /* Initialize known and common part of the WQE structure. */
 661                 if (tso) {
 662                         wqe->ctrl = (rte_v128u32_t){
 663                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 664                                 htonl(txq->qp_num_8s | ds),
 665                                 0,
 666                                 0,
 667                         };
 668                         wqe->eseg = (rte_v128u32_t){
 669                                 0,
 670                                 cs_flags | (htons(tso_segsz) << 16),
 671                                 0,
 672                                 (ehdr << 16) | htons(tso_header_sz),
 673                         };
 674                 } else {
 675                         wqe->ctrl = (rte_v128u32_t){
 676                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 677                                 htonl(txq->qp_num_8s | ds),
 678                                 0,
 679                                 0,
 680                         };
 681                         wqe->eseg = (rte_v128u32_t){
 682                                 0,
 683                                 cs_flags,
 684                                 0,
 685                                 (ehdr << 16) | htons(pkt_inline_sz),
 686                         };
 687                 }
 688 next_wqe:
 689                 txq->wqe_ci += (ds + 3) / 4;
 690                 /* Save the last successful WQE for completion request */
 691                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 692 #ifdef MLX5_PMD_SOFT_COUNTERS
 693                 /* Increment sent bytes counter. */
 694                 txq->stats.obytes += total_length;
 695 #endif
 696         } while (i < pkts_n);
 697         /* Take a shortcut if nothing must be sent. */
 698         if (unlikely((i + k) == 0))
 699                 return 0;
 700         txq->elts_head += (i + j);
 701         /* Check whether completion threshold has been reached. */
 702         comp = txq->elts_comp + i + j + k;
 703         if (comp >= MLX5_TX_COMP_THRESH) {
 704                 /* Request completion on last WQE. */
 705                 last_wqe->ctrl2 = htonl(8);
 706                 /* Save elts_head in unused "immediate" field of WQE. */
 707                 last_wqe->ctrl3 = txq->elts_head;
 708                 txq->elts_comp = 0;
 709         } else {
 710                 txq->elts_comp = comp;
 711         }
 712 #ifdef MLX5_PMD_SOFT_COUNTERS
 713         /* Increment sent packets counter. */
 714         txq->stats.opackets += i;
 715 #endif
 716         /* Ring QP doorbell. */
 717         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 718         return i;
 719 }
 720
 721 /**
 722  * Open a MPW session.
 723  *
 724  * @param txq
 725  *   Pointer to TX queue structure.
 726  * @param mpw
 727  *   Pointer to MPW session structure.
 728  * @param length
 729  *   Packet length.
 730  */
 731 static inline void
 732 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 733 {
 734         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 735         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 736                 (volatile struct mlx5_wqe_data_seg (*)[])
 737                 tx_mlx5_wqe(txq, idx + 1);
 738
 739         mpw->state = MLX5_MPW_STATE_OPENED;
 740         mpw->pkts_n = 0;
 741         mpw->len = length;
 742         mpw->total_len = 0;
 743         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 744         mpw->wqe->eseg.mss = htons(length);
 745         mpw->wqe->eseg.inline_hdr_sz = 0;
 746         mpw->wqe->eseg.rsvd0 = 0;
 747         mpw->wqe->eseg.rsvd1 = 0;
 748         mpw->wqe->eseg.rsvd2 = 0;
 749         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 750                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 751         mpw->wqe->ctrl[2] = 0;
 752         mpw->wqe->ctrl[3] = 0;
 753         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 754                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 755         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 756                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 757         mpw->data.dseg[2] = &(*dseg)[0];
 758         mpw->data.dseg[3] = &(*dseg)[1];
 759         mpw->data.dseg[4] = &(*dseg)[2];
 760 }
 761
 762 /**
 763  * Close a MPW session.
 764  *
 765  * @param txq
 766  *   Pointer to TX queue structure.
 767  * @param mpw
 768  *   Pointer to MPW session structure.
 769  */
 770 static inline void
 771 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 772 {
 773         unsigned int num = mpw->pkts_n;
 774
 775         /*
 776          * Store size in multiple of 16 bytes. Control and Ethernet segments
 777          * count as 2.
 778          */
 779         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 780         mpw->state = MLX5_MPW_STATE_CLOSED;
 781         if (num < 3)
 782                 ++txq->wqe_ci;
 783         else
 784                 txq->wqe_ci += 2;
 785         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 786         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 787 }
 788
 789 /**
 790  * DPDK callback for TX with MPW support.
 791  *
 792  * @param dpdk_txq
 793  *   Generic pointer to TX queue structure.
 794  * @param[in] pkts
 795  *   Packets to transmit.
 796  * @param pkts_n
 797  *   Number of packets in array.
 798  *
 799  * @return
 800  *   Number of packets successfully transmitted (<= pkts_n).
 801  */
 802 uint16_t
 803 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 804 {
 805         struct txq *txq = (struct txq *)dpdk_txq;
 806         uint16_t elts_head = txq->elts_head;
 807         const uint16_t elts_n = 1 << txq->elts_n;
 808         const uint16_t elts_m = elts_n - 1;
 809         unsigned int i = 0;
 810         unsigned int j = 0;
 811         uint16_t max_elts;
 812         uint16_t max_wqe;
 813         unsigned int comp;
 814         struct mlx5_mpw mpw = {
 815                 .state = MLX5_MPW_STATE_CLOSED,
 816         };
 817
 818         if (unlikely(!pkts_n))
 819                 return 0;
 820         /* Prefetch first packet cacheline. */
 821         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 822         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 823         /* Start processing. */
 824         mlx5_tx_complete(txq);
 825         max_elts = (elts_n - (elts_head - txq->elts_tail));
 826         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 827         if (unlikely(!max_wqe))
 828                 return 0;
 829         do {
 830                 struct rte_mbuf *buf = *(pkts++);
 831                 uint32_t length;
 832                 unsigned int segs_n = buf->nb_segs;
 833                 uint32_t cs_flags = 0;
 834
 835                 /*
 836                  * Make sure there is enough room to store this packet and
 837                  * that one ring entry remains unused.
 838                  */
 839                 assert(segs_n);
 840                 if (max_elts < segs_n)
 841                         break;
 842                 /* Do not bother with large packets MPW cannot handle. */
 843                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 844                         txq->stats.oerrors++;
 845                         break;
 846                 }
 847                 max_elts -= segs_n;
 848                 --pkts_n;
 849                 /* Should we enable HW CKSUM offload */
 850                 if (buf->ol_flags &
 851                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 852                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 853                 /* Retrieve packet information. */
 854                 length = PKT_LEN(buf);
 855                 assert(length);
 856                 /* Start new session if packet differs. */
 857                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 858                     ((mpw.len != length) ||
 859                      (segs_n != 1) ||
 860                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 861                         mlx5_mpw_close(txq, &mpw);
 862                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 863                         /*
 864                          * Multi-Packet WQE consumes at most two WQE.
 865                          * mlx5_mpw_new() expects to be able to use such
 866                          * resources.
 867                          */
 868                         if (unlikely(max_wqe < 2))
 869                                 break;
 870                         max_wqe -= 2;
 871                         mlx5_mpw_new(txq, &mpw, length);
 872                         mpw.wqe->eseg.cs_flags = cs_flags;
 873                 }
 874                 /* Multi-segment packets must be alone in their MPW. */
 875                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 876 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 877                 length = 0;
 878 #endif
 879                 do {
 880                         volatile struct mlx5_wqe_data_seg *dseg;
 881                         uintptr_t addr;
 882
 883                         assert(buf);
 884                         (*txq->elts)[elts_head++ & elts_m] = buf;
 885                         dseg = mpw.data.dseg[mpw.pkts_n];
 886                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 887                         *dseg = (struct mlx5_wqe_data_seg){
 888                                 .byte_count = htonl(DATA_LEN(buf)),
 889                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 890                                 .addr = htonll(addr),
 891                         };
 892 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 893                         length += DATA_LEN(buf);
 894 #endif
 895                         buf = buf->next;
 896                         ++mpw.pkts_n;
 897                         ++j;
 898                 } while (--segs_n);
 899                 assert(length == mpw.len);
 900                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 901                         mlx5_mpw_close(txq, &mpw);
 902 #ifdef MLX5_PMD_SOFT_COUNTERS
 903                 /* Increment sent bytes counter. */
 904                 txq->stats.obytes += length;
 905 #endif
 906                 ++i;
 907         } while (pkts_n);
 908         /* Take a shortcut if nothing must be sent. */
 909         if (unlikely(i == 0))
 910                 return 0;
 911         /* Check whether completion threshold has been reached. */
 912         /* "j" includes both packets and segments. */
 913         comp = txq->elts_comp + j;
 914         if (comp >= MLX5_TX_COMP_THRESH) {
 915                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 916
 917                 /* Request completion on last WQE. */
 918                 wqe->ctrl[2] = htonl(8);
 919                 /* Save elts_head in unused "immediate" field of WQE. */
 920                 wqe->ctrl[3] = elts_head;
 921                 txq->elts_comp = 0;
 922         } else {
 923                 txq->elts_comp = comp;
 924         }
 925 #ifdef MLX5_PMD_SOFT_COUNTERS
 926         /* Increment sent packets counter. */
 927         txq->stats.opackets += i;
 928 #endif
 929         /* Ring QP doorbell. */
 930         if (mpw.state == MLX5_MPW_STATE_OPENED)
 931                 mlx5_mpw_close(txq, &mpw);
 932         mlx5_tx_dbrec(txq, mpw.wqe);
 933         txq->elts_head = elts_head;
 934         return i;
 935 }
 936
 937 /**
 938  * Open a MPW inline session.
 939  *
 940  * @param txq
 941  *   Pointer to TX queue structure.
 942  * @param mpw
 943  *   Pointer to MPW session structure.
 944  * @param length
 945  *   Packet length.
 946  */
 947 static inline void
 948 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 949 {
 950         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 951         struct mlx5_wqe_inl_small *inl;
 952
 953         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 954         mpw->pkts_n = 0;
 955         mpw->len = length;
 956         mpw->total_len = 0;
 957         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 958         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 959                                   (txq->wqe_ci << 8) |
 960                                   MLX5_OPCODE_TSO);
 961         mpw->wqe->ctrl[2] = 0;
 962         mpw->wqe->ctrl[3] = 0;
 963         mpw->wqe->eseg.mss = htons(length);
 964         mpw->wqe->eseg.inline_hdr_sz = 0;
 965         mpw->wqe->eseg.cs_flags = 0;
 966         mpw->wqe->eseg.rsvd0 = 0;
 967         mpw->wqe->eseg.rsvd1 = 0;
 968         mpw->wqe->eseg.rsvd2 = 0;
 969         inl = (struct mlx5_wqe_inl_small *)
 970                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 971         mpw->data.raw = (uint8_t *)&inl->raw;
 972 }
 973
 974 /**
 975  * Close a MPW inline session.
 976  *
 977  * @param txq
 978  *   Pointer to TX queue structure.
 979  * @param mpw
 980  *   Pointer to MPW session structure.
 981  */
 982 static inline void
 983 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
 984 {
 985         unsigned int size;
 986         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 987                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 988
 989         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 990         /*
 991          * Store size in multiple of 16 bytes. Control and Ethernet segments
 992          * count as 2.
 993          */
 994         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
 995         mpw->state = MLX5_MPW_STATE_CLOSED;
 996         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
 997         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 998 }
 999
1000 /**
1001  * DPDK callback for TX with MPW inline support.
1002  *
1003  * @param dpdk_txq
1004  *   Generic pointer to TX queue structure.
1005  * @param[in] pkts
1006  *   Packets to transmit.
1007  * @param pkts_n
1008  *   Number of packets in array.
1009  *
1010  * @return
1011  *   Number of packets successfully transmitted (<= pkts_n).
1012  */
1013 uint16_t
1014 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1015                          uint16_t pkts_n)
1016 {
1017         struct txq *txq = (struct txq *)dpdk_txq;
1018         uint16_t elts_head = txq->elts_head;
1019         const uint16_t elts_n = 1 << txq->elts_n;
1020         const uint16_t elts_m = elts_n - 1;
1021         unsigned int i = 0;
1022         unsigned int j = 0;
1023         uint16_t max_elts;
1024         uint16_t max_wqe;
1025         unsigned int comp;
1026         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1027         struct mlx5_mpw mpw = {
1028                 .state = MLX5_MPW_STATE_CLOSED,
1029         };
1030         /*
1031          * Compute the maximum number of WQE which can be consumed by inline
1032          * code.
1033          * - 2 DSEG for:
1034          *   - 1 control segment,
1035          *   - 1 Ethernet segment,
1036          * - N Dseg from the inline request.
1037          */
1038         const unsigned int wqe_inl_n =
1039                 ((2 * MLX5_WQE_DWORD_SIZE +
1040                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1041                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1042
1043         if (unlikely(!pkts_n))
1044                 return 0;
1045         /* Prefetch first packet cacheline. */
1046         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1047         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1048         /* Start processing. */
1049         mlx5_tx_complete(txq);
1050         max_elts = (elts_n - (elts_head - txq->elts_tail));
1051         do {
1052                 struct rte_mbuf *buf = *(pkts++);
1053                 uintptr_t addr;
1054                 uint32_t length;
1055                 unsigned int segs_n = buf->nb_segs;
1056                 uint32_t cs_flags = 0;
1057
1058                 /*
1059                  * Make sure there is enough room to store this packet and
1060                  * that one ring entry remains unused.
1061                  */
1062                 assert(segs_n);
1063                 if (max_elts < segs_n)
1064                         break;
1065                 /* Do not bother with large packets MPW cannot handle. */
1066                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1067                         txq->stats.oerrors++;
1068                         break;
1069                 }
1070                 max_elts -= segs_n;
1071                 --pkts_n;
1072                 /*
1073                  * Compute max_wqe in case less WQE were consumed in previous
1074                  * iteration.
1075                  */
1076                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1077                 /* Should we enable HW CKSUM offload */
1078                 if (buf->ol_flags &
1079                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1080                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1081                 /* Retrieve packet information. */
1082                 length = PKT_LEN(buf);
1083                 /* Start new session if packet differs. */
1084                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1085                         if ((mpw.len != length) ||
1086                             (segs_n != 1) ||
1087                             (mpw.wqe->eseg.cs_flags != cs_flags))
1088                                 mlx5_mpw_close(txq, &mpw);
1089                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1090                         if ((mpw.len != length) ||
1091                             (segs_n != 1) ||
1092                             (length > inline_room) ||
1093                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1094                                 mlx5_mpw_inline_close(txq, &mpw);
1095                                 inline_room =
1096                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1097                         }
1098                 }
1099                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1100                         if ((segs_n != 1) ||
1101                             (length > inline_room)) {
1102                                 /*
1103                                  * Multi-Packet WQE consumes at most two WQE.
1104                                  * mlx5_mpw_new() expects to be able to use
1105                                  * such resources.
1106                                  */
1107                                 if (unlikely(max_wqe < 2))
1108                                         break;
1109                                 max_wqe -= 2;
1110                                 mlx5_mpw_new(txq, &mpw, length);
1111                                 mpw.wqe->eseg.cs_flags = cs_flags;
1112                         } else {
1113                                 if (unlikely(max_wqe < wqe_inl_n))
1114                                         break;
1115                                 max_wqe -= wqe_inl_n;
1116                                 mlx5_mpw_inline_new(txq, &mpw, length);
1117                                 mpw.wqe->eseg.cs_flags = cs_flags;
1118                         }
1119                 }
1120                 /* Multi-segment packets must be alone in their MPW. */
1121                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1122                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1123                         assert(inline_room ==
1124                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1125 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1126                         length = 0;
1127 #endif
1128                         do {
1129                                 volatile struct mlx5_wqe_data_seg *dseg;
1130
1131                                 assert(buf);
1132                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1133                                 dseg = mpw.data.dseg[mpw.pkts_n];
1134                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1135                                 *dseg = (struct mlx5_wqe_data_seg){
1136                                         .byte_count = htonl(DATA_LEN(buf)),
1137                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1138                                         .addr = htonll(addr),
1139                                 };
1140 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1141                                 length += DATA_LEN(buf);
1142 #endif
1143                                 buf = buf->next;
1144                                 ++mpw.pkts_n;
1145                                 ++j;
1146                         } while (--segs_n);
1147                         assert(length == mpw.len);
1148                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1149                                 mlx5_mpw_close(txq, &mpw);
1150                 } else {
1151                         unsigned int max;
1152
1153                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1154                         assert(length <= inline_room);
1155                         assert(length == DATA_LEN(buf));
1156                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1157                         (*txq->elts)[elts_head++ & elts_m] = buf;
1158                         /* Maximum number of bytes before wrapping. */
1159                         max = ((((uintptr_t)(txq->wqes)) +
1160                                 (1 << txq->wqe_n) *
1161                                 MLX5_WQE_SIZE) -
1162                                (uintptr_t)mpw.data.raw);
1163                         if (length > max) {
1164                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1165                                            (void *)addr,
1166                                            max);
1167                                 mpw.data.raw = (volatile void *)txq->wqes;
1168                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1169                                            (void *)(addr + max),
1170                                            length - max);
1171                                 mpw.data.raw += length - max;
1172                         } else {
1173                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1174                                            (void *)addr,
1175                                            length);
1176
1177                                 if (length == max)
1178                                         mpw.data.raw =
1179                                                 (volatile void *)txq->wqes;
1180                                 else
1181                                         mpw.data.raw += length;
1182                         }
1183                         ++mpw.pkts_n;
1184                         mpw.total_len += length;
1185                         ++j;
1186                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1187                                 mlx5_mpw_inline_close(txq, &mpw);
1188                                 inline_room =
1189                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1190                         } else {
1191                                 inline_room -= length;
1192                         }
1193                 }
1194 #ifdef MLX5_PMD_SOFT_COUNTERS
1195                 /* Increment sent bytes counter. */
1196                 txq->stats.obytes += length;
1197 #endif
1198                 ++i;
1199         } while (pkts_n);
1200         /* Take a shortcut if nothing must be sent. */
1201         if (unlikely(i == 0))
1202                 return 0;
1203         /* Check whether completion threshold has been reached. */
1204         /* "j" includes both packets and segments. */
1205         comp = txq->elts_comp + j;
1206         if (comp >= MLX5_TX_COMP_THRESH) {
1207                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1208
1209                 /* Request completion on last WQE. */
1210                 wqe->ctrl[2] = htonl(8);
1211                 /* Save elts_head in unused "immediate" field of WQE. */
1212                 wqe->ctrl[3] = elts_head;
1213                 txq->elts_comp = 0;
1214         } else {
1215                 txq->elts_comp = comp;
1216         }
1217 #ifdef MLX5_PMD_SOFT_COUNTERS
1218         /* Increment sent packets counter. */
1219         txq->stats.opackets += i;
1220 #endif
1221         /* Ring QP doorbell. */
1222         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1223                 mlx5_mpw_inline_close(txq, &mpw);
1224         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1225                 mlx5_mpw_close(txq, &mpw);
1226         mlx5_tx_dbrec(txq, mpw.wqe);
1227         txq->elts_head = elts_head;
1228         return i;
1229 }
1230
1231 /**
1232  * Open an Enhanced MPW session.
1233  *
1234  * @param txq
1235  *   Pointer to TX queue structure.
1236  * @param mpw
1237  *   Pointer to MPW session structure.
1238  * @param length
1239  *   Packet length.
1240  */
1241 static inline void
1242 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1243 {
1244         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1245
1246         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1247         mpw->pkts_n = 0;
1248         mpw->total_len = sizeof(struct mlx5_wqe);
1249         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1250         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1251                                   (txq->wqe_ci << 8) |
1252                                   MLX5_OPCODE_ENHANCED_MPSW);
1253         mpw->wqe->ctrl[2] = 0;
1254         mpw->wqe->ctrl[3] = 0;
1255         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1256         if (unlikely(padding)) {
1257                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1258
1259                 /* Pad the first 2 DWORDs with zero-length inline header. */
1260                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1261                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1262                         htonl(MLX5_INLINE_SEG);
1263                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1264                 /* Start from the next WQEBB. */
1265                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1266         } else {
1267                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1268         }
1269 }
1270
1271 /**
1272  * Close an Enhanced MPW session.
1273  *
1274  * @param txq
1275  *   Pointer to TX queue structure.
1276  * @param mpw
1277  *   Pointer to MPW session structure.
1278  *
1279  * @return
1280  *   Number of consumed WQEs.
1281  */
1282 static inline uint16_t
1283 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1284 {
1285         uint16_t ret;
1286
1287         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1288          * count as 2.
1289          */
1290         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1291         mpw->state = MLX5_MPW_STATE_CLOSED;
1292         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1293         txq->wqe_ci += ret;
1294         return ret;
1295 }
1296
1297 /**
1298  * DPDK callback for TX with Enhanced MPW support.
1299  *
1300  * @param dpdk_txq
1301  *   Generic pointer to TX queue structure.
1302  * @param[in] pkts
1303  *   Packets to transmit.
1304  * @param pkts_n
1305  *   Number of packets in array.
1306  *
1307  * @return
1308  *   Number of packets successfully transmitted (<= pkts_n).
1309  */
1310 uint16_t
1311 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1312 {
1313         struct txq *txq = (struct txq *)dpdk_txq;
1314         uint16_t elts_head = txq->elts_head;
1315         const uint16_t elts_n = 1 << txq->elts_n;
1316         const uint16_t elts_m = elts_n - 1;
1317         unsigned int i = 0;
1318         unsigned int j = 0;
1319         uint16_t max_elts;
1320         uint16_t max_wqe;
1321         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1322         unsigned int mpw_room = 0;
1323         unsigned int inl_pad = 0;
1324         uint32_t inl_hdr;
1325         struct mlx5_mpw mpw = {
1326                 .state = MLX5_MPW_STATE_CLOSED,
1327         };
1328
1329         if (unlikely(!pkts_n))
1330                 return 0;
1331         /* Start processing. */
1332         mlx5_tx_complete(txq);
1333         max_elts = (elts_n - (elts_head - txq->elts_tail));
1334         /* A CQE slot must always be available. */
1335         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1336         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1337         if (unlikely(!max_wqe))
1338                 return 0;
1339         do {
1340                 struct rte_mbuf *buf = *(pkts++);
1341                 uintptr_t addr;
1342                 uint64_t naddr;
1343                 unsigned int n;
1344                 unsigned int do_inline = 0; /* Whether inline is possible. */
1345                 uint32_t length;
1346                 unsigned int segs_n = buf->nb_segs;
1347                 uint32_t cs_flags = 0;
1348
1349                 /*
1350                  * Make sure there is enough room to store this packet and
1351                  * that one ring entry remains unused.
1352                  */
1353                 assert(segs_n);
1354                 if (max_elts - j < segs_n)
1355                         break;
1356                 /* Do not bother with large packets MPW cannot handle. */
1357                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1358                         txq->stats.oerrors++;
1359                         break;
1360                 }
1361                 /* Should we enable HW CKSUM offload. */
1362                 if (buf->ol_flags &
1363                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1364                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1365                 /* Retrieve packet information. */
1366                 length = PKT_LEN(buf);
1367                 /* Start new session if:
1368                  * - multi-segment packet
1369                  * - no space left even for a dseg
1370                  * - next packet can be inlined with a new WQE
1371                  * - cs_flag differs
1372                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1373                  * segmented packet.
1374                  */
1375                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1376                         if ((segs_n != 1) ||
1377                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1378                               mpw_room) ||
1379                             (length <= txq->inline_max_packet_sz &&
1380                              inl_pad + sizeof(inl_hdr) + length >
1381                               mpw_room) ||
1382                             (mpw.wqe->eseg.cs_flags != cs_flags))
1383                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1384                 }
1385                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1386                         if (unlikely(segs_n != 1)) {
1387                                 /* Fall back to legacy MPW.
1388                                  * A MPW session consumes 2 WQEs at most to
1389                                  * include MLX5_MPW_DSEG_MAX pointers.
1390                                  */
1391                                 if (unlikely(max_wqe < 2))
1392                                         break;
1393                                 mlx5_mpw_new(txq, &mpw, length);
1394                         } else {
1395                                 /* In Enhanced MPW, inline as much as the budget
1396                                  * is allowed. The remaining space is to be
1397                                  * filled with dsegs. If the title WQEBB isn't
1398                                  * padded, it will have 2 dsegs there.
1399                                  */
1400                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1401                                             (max_inline ? max_inline :
1402                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1403                                             MLX5_WQE_SIZE);
1404                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1405                                               mpw_room))
1406                                         break;
1407                                 /* Don't pad the title WQEBB to not waste WQ. */
1408                                 mlx5_empw_new(txq, &mpw, 0);
1409                                 mpw_room -= mpw.total_len;
1410                                 inl_pad = 0;
1411                                 do_inline =
1412                                         length <= txq->inline_max_packet_sz &&
1413                                         sizeof(inl_hdr) + length <= mpw_room &&
1414                                         !txq->mpw_hdr_dseg;
1415                         }
1416                         mpw.wqe->eseg.cs_flags = cs_flags;
1417                 } else {
1418                         /* Evaluate whether the next packet can be inlined.
1419                          * Inlininig is possible when:
1420                          * - length is less than configured value
1421                          * - length fits for remaining space
1422                          * - not required to fill the title WQEBB with dsegs
1423                          */
1424                         do_inline =
1425                                 length <= txq->inline_max_packet_sz &&
1426                                 inl_pad + sizeof(inl_hdr) + length <=
1427                                  mpw_room &&
1428                                 (!txq->mpw_hdr_dseg ||
1429                                  mpw.total_len >= MLX5_WQE_SIZE);
1430                 }
1431                 /* Multi-segment packets must be alone in their MPW. */
1432                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1433                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1434 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1435                         length = 0;
1436 #endif
1437                         do {
1438                                 volatile struct mlx5_wqe_data_seg *dseg;
1439
1440                                 assert(buf);
1441                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1442                                 dseg = mpw.data.dseg[mpw.pkts_n];
1443                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1444                                 *dseg = (struct mlx5_wqe_data_seg){
1445                                         .byte_count = htonl(DATA_LEN(buf)),
1446                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1447                                         .addr = htonll(addr),
1448                                 };
1449 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1450                                 length += DATA_LEN(buf);
1451 #endif
1452                                 buf = buf->next;
1453                                 ++j;
1454                                 ++mpw.pkts_n;
1455                         } while (--segs_n);
1456                         /* A multi-segmented packet takes one MPW session.
1457                          * TODO: Pack more multi-segmented packets if possible.
1458                          */
1459                         mlx5_mpw_close(txq, &mpw);
1460                         if (mpw.pkts_n < 3)
1461                                 max_wqe--;
1462                         else
1463                                 max_wqe -= 2;
1464                 } else if (do_inline) {
1465                         /* Inline packet into WQE. */
1466                         unsigned int max;
1467
1468                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1469                         assert(length == DATA_LEN(buf));
1470                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1471                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1472                         mpw.data.raw = (volatile void *)
1473                                 ((uintptr_t)mpw.data.raw + inl_pad);
1474                         max = tx_mlx5_wq_tailroom(txq,
1475                                         (void *)(uintptr_t)mpw.data.raw);
1476                         /* Copy inline header. */
1477                         mpw.data.raw = (volatile void *)
1478                                 mlx5_copy_to_wq(
1479                                           (void *)(uintptr_t)mpw.data.raw,
1480                                           &inl_hdr,
1481                                           sizeof(inl_hdr),
1482                                           (void *)(uintptr_t)txq->wqes,
1483                                           max);
1484                         max = tx_mlx5_wq_tailroom(txq,
1485                                         (void *)(uintptr_t)mpw.data.raw);
1486                         /* Copy packet data. */
1487                         mpw.data.raw = (volatile void *)
1488                                 mlx5_copy_to_wq(
1489                                           (void *)(uintptr_t)mpw.data.raw,
1490                                           (void *)addr,
1491                                           length,
1492                                           (void *)(uintptr_t)txq->wqes,
1493                                           max);
1494                         ++mpw.pkts_n;
1495                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1496                         /* No need to get completion as the entire packet is
1497                          * copied to WQ. Free the buf right away.
1498                          */
1499                         rte_pktmbuf_free_seg(buf);
1500                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1501                         /* Add pad in the next packet if any. */
1502                         inl_pad = (((uintptr_t)mpw.data.raw +
1503                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1504                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1505                                   (uintptr_t)mpw.data.raw;
1506                 } else {
1507                         /* No inline. Load a dseg of packet pointer. */
1508                         volatile rte_v128u32_t *dseg;
1509
1510                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1511                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1512                         assert(length == DATA_LEN(buf));
1513                         if (!tx_mlx5_wq_tailroom(txq,
1514                                         (void *)((uintptr_t)mpw.data.raw
1515                                                 + inl_pad)))
1516                                 dseg = (volatile void *)txq->wqes;
1517                         else
1518                                 dseg = (volatile void *)
1519                                         ((uintptr_t)mpw.data.raw +
1520                                          inl_pad);
1521                         (*txq->elts)[elts_head++ & elts_m] = buf;
1522                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1523                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1524                                 rte_prefetch2((void *)(addr +
1525                                                 n * RTE_CACHE_LINE_SIZE));
1526                         naddr = htonll(addr);
1527                         *dseg = (rte_v128u32_t) {
1528                                 htonl(length),
1529                                 mlx5_tx_mb2mr(txq, buf),
1530                                 naddr,
1531                                 naddr >> 32,
1532                         };
1533                         mpw.data.raw = (volatile void *)(dseg + 1);
1534                         mpw.total_len += (inl_pad + sizeof(*dseg));
1535                         ++j;
1536                         ++mpw.pkts_n;
1537                         mpw_room -= (inl_pad + sizeof(*dseg));
1538                         inl_pad = 0;
1539                 }
1540 #ifdef MLX5_PMD_SOFT_COUNTERS
1541                 /* Increment sent bytes counter. */
1542                 txq->stats.obytes += length;
1543 #endif
1544                 ++i;
1545         } while (i < pkts_n);
1546         /* Take a shortcut if nothing must be sent. */
1547         if (unlikely(i == 0))
1548                 return 0;
1549         /* Check whether completion threshold has been reached. */
1550         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1551                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1552                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1553                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1554
1555                 /* Request completion on last WQE. */
1556                 wqe->ctrl[2] = htonl(8);
1557                 /* Save elts_head in unused "immediate" field of WQE. */
1558                 wqe->ctrl[3] = elts_head;
1559                 txq->elts_comp = 0;
1560                 txq->mpw_comp = txq->wqe_ci;
1561                 txq->cq_pi++;
1562         } else {
1563                 txq->elts_comp += j;
1564         }
1565 #ifdef MLX5_PMD_SOFT_COUNTERS
1566         /* Increment sent packets counter. */
1567         txq->stats.opackets += i;
1568 #endif
1569         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1570                 mlx5_empw_close(txq, &mpw);
1571         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1572                 mlx5_mpw_close(txq, &mpw);
1573         /* Ring QP doorbell. */
1574         mlx5_tx_dbrec(txq, mpw.wqe);
1575         txq->elts_head = elts_head;
1576         return i;
1577 }
1578
1579 /**
1580  * Translate RX completion flags to packet type.
1581  *
1582  * @param[in] cqe
1583  *   Pointer to CQE.
1584  *
1585  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1586  *
1587  * @return
1588  *   Packet type for struct rte_mbuf.
1589  */
1590 static inline uint32_t
1591 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1592 {
1593         uint8_t idx;
1594         uint8_t pinfo = cqe->pkt_info;
1595         uint16_t ptype = cqe->hdr_type_etc;
1596
1597         /*
1598          * The index to the array should have:
1599          * bit[1:0] = l3_hdr_type
1600          * bit[4:2] = l4_hdr_type
1601          * bit[5] = ip_frag
1602          * bit[6] = tunneled
1603          * bit[7] = outer_l3_type
1604          */
1605         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1606         return mlx5_ptype_table[idx];
1607 }
1608
1609 /**
1610  * Get size of the next packet for a given CQE. For compressed CQEs, the
1611  * consumer index is updated only once all packets of the current one have
1612  * been processed.
1613  *
1614  * @param rxq
1615  *   Pointer to RX queue.
1616  * @param cqe
1617  *   CQE to process.
1618  * @param[out] rss_hash
1619  *   Packet RSS Hash result.
1620  *
1621  * @return
1622  *   Packet size in bytes (0 if there is none), -1 in case of completion
1623  *   with error.
1624  */
1625 static inline int
1626 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1627                  uint16_t cqe_cnt, uint32_t *rss_hash)
1628 {
1629         struct rxq_zip *zip = &rxq->zip;
1630         uint16_t cqe_n = cqe_cnt + 1;
1631         int len = 0;
1632         uint16_t idx, end;
1633
1634         /* Process compressed data in the CQE and mini arrays. */
1635         if (zip->ai) {
1636                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1637                         (volatile struct mlx5_mini_cqe8 (*)[8])
1638                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1639
1640                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1641                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1642                 if ((++zip->ai & 7) == 0) {
1643                         /* Invalidate consumed CQEs */
1644                         idx = zip->ca;
1645                         end = zip->na;
1646                         while (idx != end) {
1647                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1648                                         MLX5_CQE_INVALIDATE;
1649                                 ++idx;
1650                         }
1651                         /*
1652                          * Increment consumer index to skip the number of
1653                          * CQEs consumed. Hardware leaves holes in the CQ
1654                          * ring for software use.
1655                          */
1656                         zip->ca = zip->na;
1657                         zip->na += 8;
1658                 }
1659                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1660                         /* Invalidate the rest */
1661                         idx = zip->ca;
1662                         end = zip->cq_ci;
1663
1664                         while (idx != end) {
1665                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1666                                         MLX5_CQE_INVALIDATE;
1667                                 ++idx;
1668                         }
1669                         rxq->cq_ci = zip->cq_ci;
1670                         zip->ai = 0;
1671                 }
1672         /* No compressed data, get next CQE and verify if it is compressed. */
1673         } else {
1674                 int ret;
1675                 int8_t op_own;
1676
1677                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1678                 if (unlikely(ret == 1))
1679                         return 0;
1680                 ++rxq->cq_ci;
1681                 op_own = cqe->op_own;
1682                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1683                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1684                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1685                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1686                                                           cqe_cnt].pkt_info);
1687
1688                         /* Fix endianness. */
1689                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1690                         /*
1691                          * Current mini array position is the one returned by
1692                          * check_cqe64().
1693                          *
1694                          * If completion comprises several mini arrays, as a
1695                          * special case the second one is located 7 CQEs after
1696                          * the initial CQE instead of 8 for subsequent ones.
1697                          */
1698                         zip->ca = rxq->cq_ci;
1699                         zip->na = zip->ca + 7;
1700                         /* Compute the next non compressed CQE. */
1701                         --rxq->cq_ci;
1702                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1703                         /* Get packet size to return. */
1704                         len = ntohl((*mc)[0].byte_cnt);
1705                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1706                         zip->ai = 1;
1707                         /* Prefetch all the entries to be invalidated */
1708                         idx = zip->ca;
1709                         end = zip->cq_ci;
1710                         while (idx != end) {
1711                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1712                                 ++idx;
1713                         }
1714                 } else {
1715                         len = ntohl(cqe->byte_cnt);
1716                         *rss_hash = ntohl(cqe->rx_hash_res);
1717                 }
1718                 /* Error while receiving packet. */
1719                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1720                         return -1;
1721         }
1722         return len;
1723 }
1724
1725 /**
1726  * Translate RX completion flags to offload flags.
1727  *
1728  * @param[in] rxq
1729  *   Pointer to RX queue structure.
1730  * @param[in] cqe
1731  *   Pointer to CQE.
1732  *
1733  * @return
1734  *   Offload flags (ol_flags) for struct rte_mbuf.
1735  */
1736 static inline uint32_t
1737 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1738 {
1739         uint32_t ol_flags = 0;
1740         uint16_t flags = ntohs(cqe->hdr_type_etc);
1741
1742         ol_flags =
1743                 TRANSPOSE(flags,
1744                           MLX5_CQE_RX_L3_HDR_VALID,
1745                           PKT_RX_IP_CKSUM_GOOD) |
1746                 TRANSPOSE(flags,
1747                           MLX5_CQE_RX_L4_HDR_VALID,
1748                           PKT_RX_L4_CKSUM_GOOD);
1749         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1750                 ol_flags |=
1751                         TRANSPOSE(flags,
1752                                   MLX5_CQE_RX_L3_HDR_VALID,
1753                                   PKT_RX_IP_CKSUM_GOOD) |
1754                         TRANSPOSE(flags,
1755                                   MLX5_CQE_RX_L4_HDR_VALID,
1756                                   PKT_RX_L4_CKSUM_GOOD);
1757         return ol_flags;
1758 }
1759
1760 /**
1761  * DPDK callback for RX.
1762  *
1763  * @param dpdk_rxq
1764  *   Generic pointer to RX queue structure.
1765  * @param[out] pkts
1766  *   Array to store received packets.
1767  * @param pkts_n
1768  *   Maximum number of packets in array.
1769  *
1770  * @return
1771  *   Number of packets successfully received (<= pkts_n).
1772  */
1773 uint16_t
1774 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1775 {
1776         struct rxq *rxq = dpdk_rxq;
1777         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1778         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1779         const unsigned int sges_n = rxq->sges_n;
1780         struct rte_mbuf *pkt = NULL;
1781         struct rte_mbuf *seg = NULL;
1782         volatile struct mlx5_cqe *cqe =
1783                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1784         unsigned int i = 0;
1785         unsigned int rq_ci = rxq->rq_ci << sges_n;
1786         int len = 0; /* keep its value across iterations. */
1787
1788         while (pkts_n) {
1789                 unsigned int idx = rq_ci & wqe_cnt;
1790                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1791                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1792                 uint32_t rss_hash_res = 0;
1793
1794                 if (pkt)
1795                         NEXT(seg) = rep;
1796                 seg = rep;
1797                 rte_prefetch0(seg);
1798                 rte_prefetch0(cqe);
1799                 rte_prefetch0(wqe);
1800                 rep = rte_mbuf_raw_alloc(rxq->mp);
1801                 if (unlikely(rep == NULL)) {
1802                         ++rxq->stats.rx_nombuf;
1803                         if (!pkt) {
1804                                 /*
1805                                  * no buffers before we even started,
1806                                  * bail out silently.
1807                                  */
1808                                 break;
1809                         }
1810                         while (pkt != seg) {
1811                                 assert(pkt != (*rxq->elts)[idx]);
1812                                 rep = NEXT(pkt);
1813                                 NEXT(pkt) = NULL;
1814                                 NB_SEGS(pkt) = 1;
1815                                 rte_mbuf_raw_free(pkt);
1816                                 pkt = rep;
1817                         }
1818                         break;
1819                 }
1820                 if (!pkt) {
1821                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1822                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1823                                                &rss_hash_res);
1824                         if (!len) {
1825                                 rte_mbuf_raw_free(rep);
1826                                 break;
1827                         }
1828                         if (unlikely(len == -1)) {
1829                                 /* RX error, packet is likely too large. */
1830                                 rte_mbuf_raw_free(rep);
1831                                 ++rxq->stats.idropped;
1832                                 goto skip;
1833                         }
1834                         pkt = seg;
1835                         assert(len >= (rxq->crc_present << 2));
1836                         /* Update packet information. */
1837                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1838                         pkt->ol_flags = 0;
1839                         if (rss_hash_res && rxq->rss_hash) {
1840                                 pkt->hash.rss = rss_hash_res;
1841                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1842                         }
1843                         if (rxq->mark &&
1844                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1845                                 pkt->ol_flags |= PKT_RX_FDIR;
1846                                 if (cqe->sop_drop_qpn !=
1847                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1848                                         uint32_t mark = cqe->sop_drop_qpn;
1849
1850                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1851                                         pkt->hash.fdir.hi =
1852                                                 mlx5_flow_mark_get(mark);
1853                                 }
1854                         }
1855                         if (rxq->csum | rxq->csum_l2tun)
1856                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1857                         if (rxq->vlan_strip &&
1858                             (cqe->hdr_type_etc &
1859                              htons(MLX5_CQE_VLAN_STRIPPED))) {
1860                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1861                                         PKT_RX_VLAN_STRIPPED;
1862                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
1863                         }
1864                         if (rxq->crc_present)
1865                                 len -= ETHER_CRC_LEN;
1866                         PKT_LEN(pkt) = len;
1867                 }
1868                 DATA_LEN(rep) = DATA_LEN(seg);
1869                 PKT_LEN(rep) = PKT_LEN(seg);
1870                 SET_DATA_OFF(rep, DATA_OFF(seg));
1871                 PORT(rep) = PORT(seg);
1872                 (*rxq->elts)[idx] = rep;
1873                 /*
1874                  * Fill NIC descriptor with the new buffer.  The lkey and size
1875                  * of the buffers are already known, only the buffer address
1876                  * changes.
1877                  */
1878                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1879                 if (len > DATA_LEN(seg)) {
1880                         len -= DATA_LEN(seg);
1881                         ++NB_SEGS(pkt);
1882                         ++rq_ci;
1883                         continue;
1884                 }
1885                 DATA_LEN(seg) = len;
1886 #ifdef MLX5_PMD_SOFT_COUNTERS
1887                 /* Increment bytes counter. */
1888                 rxq->stats.ibytes += PKT_LEN(pkt);
1889 #endif
1890                 /* Return packet. */
1891                 *(pkts++) = pkt;
1892                 pkt = NULL;
1893                 --pkts_n;
1894                 ++i;
1895 skip:
1896                 /* Align consumer index to the next stride. */
1897                 rq_ci >>= sges_n;
1898                 ++rq_ci;
1899                 rq_ci <<= sges_n;
1900         }
1901         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1902                 return 0;
1903         /* Update the consumer index. */
1904         rxq->rq_ci = rq_ci >> sges_n;
1905         rte_wmb();
1906         *rxq->cq_db = htonl(rxq->cq_ci);
1907         rte_wmb();
1908         *rxq->rq_db = htonl(rxq->rq_ci);
1909 #ifdef MLX5_PMD_SOFT_COUNTERS
1910         /* Increment packets counter. */
1911         rxq->stats.ipackets += i;
1912 #endif
1913         return i;
1914 }
1915
1916 /**
1917  * Dummy DPDK callback for TX.
1918  *
1919  * This function is used to temporarily replace the real callback during
1920  * unsafe control operations on the queue, or in case of error.
1921  *
1922  * @param dpdk_txq
1923  *   Generic pointer to TX queue structure.
1924  * @param[in] pkts
1925  *   Packets to transmit.
1926  * @param pkts_n
1927  *   Number of packets in array.
1928  *
1929  * @return
1930  *   Number of packets successfully transmitted (<= pkts_n).
1931  */
1932 uint16_t
1933 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1934 {
1935         (void)dpdk_txq;
1936         (void)pkts;
1937         (void)pkts_n;
1938         return 0;
1939 }
1940
1941 /**
1942  * Dummy DPDK callback for RX.
1943  *
1944  * This function is used to temporarily replace the real callback during
1945  * unsafe control operations on the queue, or in case of error.
1946  *
1947  * @param dpdk_rxq
1948  *   Generic pointer to RX queue structure.
1949  * @param[out] pkts
1950  *   Array to store received packets.
1951  * @param pkts_n
1952  *   Maximum number of packets in array.
1953  *
1954  * @return
1955  *   Number of packets successfully received (<= pkts_n).
1956  */
1957 uint16_t
1958 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1959 {
1960         (void)dpdk_rxq;
1961         (void)pkts;
1962         (void)pkts_n;
1963         return 0;
1964 }
1965
1966 /*
1967  * Vectorized Rx/Tx routines are not compiled in when required vector
1968  * instructions are not supported on a target architecture. The following null
1969  * stubs are needed for linkage when those are not included outside of this file
1970  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1971  */
1972
1973 uint16_t __attribute__((weak))
1974 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1975 {
1976         (void)dpdk_txq;
1977         (void)pkts;
1978         (void)pkts_n;
1979         return 0;
1980 }
1981
1982 uint16_t __attribute__((weak))
1983 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1984 {
1985         (void)dpdk_txq;
1986         (void)pkts;
1987         (void)pkts_n;
1988         return 0;
1989 }
1990
1991 uint16_t __attribute__((weak))
1992 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1993 {
1994         (void)dpdk_rxq;
1995         (void)pkts;
1996         (void)pkts_n;
1997         return 0;
1998 }
1999
2000 int __attribute__((weak))
2001 priv_check_raw_vec_tx_support(struct priv *priv)
2002 {
2003         (void)priv;
2004         return -ENOTSUP;
2005 }
2006
2007 int __attribute__((weak))
2008 priv_check_vec_tx_support(struct priv *priv)
2009 {
2010         (void)priv;
2011         return -ENOTSUP;
2012 }
2013
2014 int __attribute__((weak))
2015 rxq_check_vec_support(struct rxq *rxq)
2016 {
2017         (void)rxq;
2018         return -ENOTSUP;
2019 }
2020
2021 int __attribute__((weak))
2022 priv_check_vec_rx_support(struct priv *priv)
2023 {
2024         (void)priv;
2025         return -ENOTSUP;
2026 }