drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Manage TX completions.
 199  *
 200  * When sending a burst, mlx5_tx_burst() posts several WRs.
 201  *
 202  * @param txq
 203  *   Pointer to TX queue structure.
 204  */
 205 static inline void
 206 txq_complete(struct txq *txq)
 207 {
 208         const unsigned int elts_n = 1 << txq->elts_n;
 209         const unsigned int cqe_n = 1 << txq->cqe_n;
 210         const unsigned int cqe_cnt = cqe_n - 1;
 211         uint16_t elts_free = txq->elts_tail;
 212         uint16_t elts_tail;
 213         uint16_t cq_ci = txq->cq_ci;
 214         volatile struct mlx5_cqe *cqe = NULL;
 215         volatile struct mlx5_wqe_ctrl *ctrl;
 216
 217         do {
 218                 volatile struct mlx5_cqe *tmp;
 219
 220                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 221                 if (check_cqe(tmp, cqe_n, cq_ci))
 222                         break;
 223                 cqe = tmp;
 224 #ifndef NDEBUG
 225                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 226                         if (!check_cqe_seen(cqe))
 227                                 ERROR("unexpected compressed CQE, TX stopped");
 228                         return;
 229                 }
 230                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 231                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 232                         if (!check_cqe_seen(cqe))
 233                                 ERROR("unexpected error CQE, TX stopped");
 234                         return;
 235                 }
 236 #endif /* NDEBUG */
 237                 ++cq_ci;
 238         } while (1);
 239         if (unlikely(cqe == NULL))
 240                 return;
 241         txq->wqe_pi = ntohs(cqe->wqe_counter);
 242         ctrl = (volatile struct mlx5_wqe_ctrl *)
 243                 tx_mlx5_wqe(txq, txq->wqe_pi);
 244         elts_tail = ctrl->ctrl3;
 245         assert(elts_tail < (1 << txq->wqe_n));
 246         /* Free buffers. */
 247         while (elts_free != elts_tail) {
 248                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 249                 unsigned int elts_free_next =
 250                         (elts_free + 1) & (elts_n - 1);
 251                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 252
 253 #ifndef NDEBUG
 254                 /* Poisoning. */
 255                 memset(&(*txq->elts)[elts_free],
 256                        0x66,
 257                        sizeof((*txq->elts)[elts_free]));
 258 #endif
 259                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 260                 /* Only one segment needs to be freed. */
 261                 rte_pktmbuf_free_seg(elt);
 262                 elts_free = elts_free_next;
 263         }
 264         txq->cq_ci = cq_ci;
 265         txq->elts_tail = elts_tail;
 266         /* Update the consumer index. */
 267         rte_wmb();
 268         *txq->cq_db = htonl(cq_ci);
 269 }
 270
 271 /**
 272  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 273  * the cloned mbuf is allocated is returned instead.
 274  *
 275  * @param buf
 276  *   Pointer to mbuf.
 277  *
 278  * @return
 279  *   Memory pool where data is located for given mbuf.
 280  */
 281 static struct rte_mempool *
 282 txq_mb2mp(struct rte_mbuf *buf)
 283 {
 284         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 285                 return rte_mbuf_from_indirect(buf)->pool;
 286         return buf->pool;
 287 }
 288
 289 /**
 290  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 291  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 292  * remove an entry first.
 293  *
 294  * @param txq
 295  *   Pointer to TX queue structure.
 296  * @param[in] mp
 297  *   Memory Pool for which a Memory Region lkey must be returned.
 298  *
 299  * @return
 300  *   mr->lkey on success, (uint32_t)-1 on failure.
 301  */
 302 static inline uint32_t
 303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 304 {
 305         unsigned int i;
 306         uint32_t lkey = (uint32_t)-1;
 307
 308         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 309                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 310                         /* Unknown MP, add a new MR for it. */
 311                         break;
 312                 }
 313                 if (txq->mp2mr[i].mp == mp) {
 314                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 315                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 316                                txq->mp2mr[i].lkey);
 317                         lkey = txq->mp2mr[i].lkey;
 318                         break;
 319                 }
 320         }
 321         if (unlikely(lkey == (uint32_t)-1))
 322                 lkey = txq_mp2mr_reg(txq, mp, i);
 323         return lkey;
 324 }
 325
 326 /**
 327  * Ring TX queue doorbell.
 328  *
 329  * @param txq
 330  *   Pointer to TX queue structure.
 331  * @param wqe
 332  *   Pointer to the last WQE posted in the NIC.
 333  */
 334 static inline void
 335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 336 {
 337         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 338         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 339
 340         rte_wmb();
 341         *txq->qp_db = htonl(txq->wqe_ci);
 342         /* Ensure ordering between DB record and BF copy. */
 343         rte_wmb();
 344         *dst = *src;
 345 }
 346
 347 /**
 348  * DPDK callback to check the status of a tx descriptor.
 349  *
 350  * @param tx_queue
 351  *   The tx queue.
 352  * @param[in] offset
 353  *   The index of the descriptor in the ring.
 354  *
 355  * @return
 356  *   The status of the tx descriptor.
 357  */
 358 int
 359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 360 {
 361         struct txq *txq = tx_queue;
 362         const unsigned int elts_n = 1 << txq->elts_n;
 363         const unsigned int elts_cnt = elts_n - 1;
 364         unsigned int used;
 365
 366         txq_complete(txq);
 367         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 368         if (offset < used)
 369                 return RTE_ETH_TX_DESC_FULL;
 370         return RTE_ETH_TX_DESC_DONE;
 371 }
 372
 373 /**
 374  * DPDK callback to check the status of a rx descriptor.
 375  *
 376  * @param rx_queue
 377  *   The rx queue.
 378  * @param[in] offset
 379  *   The index of the descriptor in the ring.
 380  *
 381  * @return
 382  *   The status of the tx descriptor.
 383  */
 384 int
 385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 386 {
 387         struct rxq *rxq = rx_queue;
 388         struct rxq_zip *zip = &rxq->zip;
 389         volatile struct mlx5_cqe *cqe;
 390         const unsigned int cqe_n = (1 << rxq->cqe_n);
 391         const unsigned int cqe_cnt = cqe_n - 1;
 392         unsigned int cq_ci;
 393         unsigned int used;
 394
 395         /* if we are processing a compressed cqe */
 396         if (zip->ai) {
 397                 used = zip->cqe_cnt - zip->ca;
 398                 cq_ci = zip->cq_ci;
 399         } else {
 400                 used = 0;
 401                 cq_ci = rxq->cq_ci;
 402         }
 403         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 404         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 405                 int8_t op_own;
 406                 unsigned int n;
 407
 408                 op_own = cqe->op_own;
 409                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 410                         n = ntohl(cqe->byte_cnt);
 411                 else
 412                         n = 1;
 413                 cq_ci += n;
 414                 used += n;
 415                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 416         }
 417         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 418         if (offset < used)
 419                 return RTE_ETH_RX_DESC_DONE;
 420         return RTE_ETH_RX_DESC_AVAIL;
 421 }
 422
 423 /**
 424  * DPDK callback for TX.
 425  *
 426  * @param dpdk_txq
 427  *   Generic pointer to TX queue structure.
 428  * @param[in] pkts
 429  *   Packets to transmit.
 430  * @param pkts_n
 431  *   Number of packets in array.
 432  *
 433  * @return
 434  *   Number of packets successfully transmitted (<= pkts_n).
 435  */
 436 uint16_t
 437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 438 {
 439         struct txq *txq = (struct txq *)dpdk_txq;
 440         uint16_t elts_head = txq->elts_head;
 441         const unsigned int elts_n = 1 << txq->elts_n;
 442         unsigned int i = 0;
 443         unsigned int j = 0;
 444         unsigned int k = 0;
 445         unsigned int max;
 446         uint16_t max_wqe;
 447         unsigned int comp;
 448         volatile struct mlx5_wqe_v *wqe = NULL;
 449         unsigned int segs_n = 0;
 450         struct rte_mbuf *buf = NULL;
 451         uint8_t *raw;
 452
 453         if (unlikely(!pkts_n))
 454                 return 0;
 455         /* Prefetch first packet cacheline. */
 456         rte_prefetch0(*pkts);
 457         /* Start processing. */
 458         txq_complete(txq);
 459         max = (elts_n - (elts_head - txq->elts_tail));
 460         if (max > elts_n)
 461                 max -= elts_n;
 462         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 463         if (unlikely(!max_wqe))
 464                 return 0;
 465         do {
 466                 volatile rte_v128u32_t *dseg = NULL;
 467                 uint32_t length;
 468                 unsigned int ds = 0;
 469                 uintptr_t addr;
 470                 uint64_t naddr;
 471                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 472                 uint16_t tso_header_sz = 0;
 473                 uint16_t ehdr;
 474                 uint8_t cs_flags = 0;
 475                 uint64_t tso = 0;
 476 #ifdef MLX5_PMD_SOFT_COUNTERS
 477                 uint32_t total_length = 0;
 478 #endif
 479
 480                 /* first_seg */
 481                 buf = *(pkts++);
 482                 segs_n = buf->nb_segs;
 483                 /*
 484                  * Make sure there is enough room to store this packet and
 485                  * that one ring entry remains unused.
 486                  */
 487                 assert(segs_n);
 488                 if (max < segs_n + 1)
 489                         break;
 490                 max -= segs_n;
 491                 --segs_n;
 492                 if (!segs_n)
 493                         --pkts_n;
 494                 if (unlikely(--max_wqe == 0))
 495                         break;
 496                 wqe = (volatile struct mlx5_wqe_v *)
 497                         tx_mlx5_wqe(txq, txq->wqe_ci);
 498                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 499                 if (pkts_n > 1)
 500                         rte_prefetch0(*pkts);
 501                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 502                 length = DATA_LEN(buf);
 503                 ehdr = (((uint8_t *)addr)[1] << 8) |
 504                        ((uint8_t *)addr)[0];
 505 #ifdef MLX5_PMD_SOFT_COUNTERS
 506                 total_length = length;
 507 #endif
 508                 assert(length >= MLX5_WQE_DWORD_SIZE);
 509                 /* Update element. */
 510                 (*txq->elts)[elts_head] = buf;
 511                 elts_head = (elts_head + 1) & (elts_n - 1);
 512                 /* Prefetch next buffer data. */
 513                 if (pkts_n > 1) {
 514                         volatile void *pkt_addr;
 515
 516                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 517                         rte_prefetch0(pkt_addr);
 518                 }
 519                 /* Should we enable HW CKSUM offload */
 520                 if (buf->ol_flags &
 521                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 522                         const uint64_t is_tunneled = buf->ol_flags &
 523                                                      (PKT_TX_TUNNEL_GRE |
 524                                                       PKT_TX_TUNNEL_VXLAN);
 525
 526                         if (is_tunneled && txq->tunnel_en) {
 527                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 528                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 529                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 530                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 531                         } else {
 532                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 533                                            MLX5_ETH_WQE_L4_CSUM;
 534                         }
 535                 }
 536                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 537                 /* Replace the Ethernet type by the VLAN if necessary. */
 538                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 539                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 540                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 541
 542                         addr += 2;
 543                         length -= 2;
 544                         /* Copy Destination and source mac address. */
 545                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 546                         /* Copy VLAN. */
 547                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 548                         /* Copy missing two bytes to end the DSeg. */
 549                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 550                                ((uint8_t *)addr) + len, 2);
 551                         addr += len + 2;
 552                         length -= (len + 2);
 553                 } else {
 554                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 555                                MLX5_WQE_DWORD_SIZE);
 556                         length -= pkt_inline_sz;
 557                         addr += pkt_inline_sz;
 558                 }
 559                 if (txq->tso_en) {
 560                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 561                         if (tso) {
 562                                 uintptr_t end = (uintptr_t)
 563                                                 (((uintptr_t)txq->wqes) +
 564                                                 (1 << txq->wqe_n) *
 565                                                 MLX5_WQE_SIZE);
 566                                 unsigned int copy_b;
 567                                 uint8_t vlan_sz = (buf->ol_flags &
 568                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 569                                 const uint64_t is_tunneled =
 570                                                         buf->ol_flags &
 571                                                         (PKT_TX_TUNNEL_GRE |
 572                                                          PKT_TX_TUNNEL_VXLAN);
 573
 574                                 tso_header_sz = buf->l2_len + vlan_sz +
 575                                                 buf->l3_len + buf->l4_len;
 576
 577                                 if (is_tunneled && txq->tunnel_en) {
 578                                         tso_header_sz += buf->outer_l2_len +
 579                                                          buf->outer_l3_len;
 580                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 581                                 } else {
 582                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 583                                 }
 584                                 if (unlikely(tso_header_sz >
 585                                              MLX5_MAX_TSO_HEADER))
 586                                         break;
 587                                 copy_b = tso_header_sz - pkt_inline_sz;
 588                                 /* First seg must contain all headers. */
 589                                 assert(copy_b <= length);
 590                                 raw += MLX5_WQE_DWORD_SIZE;
 591                                 if (copy_b &&
 592                                    ((end - (uintptr_t)raw) > copy_b)) {
 593                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 594                                                       1 + 3) / 4;
 595
 596                                         if (unlikely(max_wqe < n))
 597                                                 break;
 598                                         max_wqe -= n;
 599                                         rte_memcpy((void *)raw,
 600                                                    (void *)addr, copy_b);
 601                                         addr += copy_b;
 602                                         length -= copy_b;
 603                                         pkt_inline_sz += copy_b;
 604                                         /*
 605                                          * Another DWORD will be added
 606                                          * in the inline part.
 607                                          */
 608                                         raw += MLX5_WQE_DS(copy_b) *
 609                                                MLX5_WQE_DWORD_SIZE -
 610                                                MLX5_WQE_DWORD_SIZE;
 611                                 } else {
 612                                         /* NOP WQE. */
 613                                         wqe->ctrl = (rte_v128u32_t){
 614                                                      htonl(txq->wqe_ci << 8),
 615                                                      htonl(txq->qp_num_8s | 1),
 616                                                      0,
 617                                                      0,
 618                                         };
 619                                         ds = 1;
 620                                         total_length = 0;
 621                                         pkts--;
 622                                         pkts_n++;
 623                                         elts_head = (elts_head - 1) &
 624                                                     (elts_n - 1);
 625                                         k++;
 626                                         goto next_wqe;
 627                                 }
 628                         }
 629                 }
 630                 /* Inline if enough room. */
 631                 if (txq->inline_en || tso) {
 632                         uintptr_t end = (uintptr_t)
 633                                 (((uintptr_t)txq->wqes) +
 634                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 635                         unsigned int max_inline = txq->max_inline *
 636                                                   RTE_CACHE_LINE_SIZE -
 637                                                   (pkt_inline_sz - 2);
 638                         uintptr_t addr_end = (addr + max_inline) &
 639                                              ~(RTE_CACHE_LINE_SIZE - 1);
 640                         unsigned int copy_b = (addr_end > addr) ?
 641                                 RTE_MIN((addr_end - addr), length) :
 642                                 0;
 643
 644                         raw += MLX5_WQE_DWORD_SIZE;
 645                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 646                                 /*
 647                                  * One Dseg remains in the current WQE.  To
 648                                  * keep the computation positive, it is
 649                                  * removed after the bytes to Dseg conversion.
 650                                  */
 651                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 652
 653                                 if (unlikely(max_wqe < n))
 654                                         break;
 655                                 max_wqe -= n;
 656                                 if (tso) {
 657                                         uint32_t inl =
 658                                                 htonl(copy_b | MLX5_INLINE_SEG);
 659
 660                                         pkt_inline_sz =
 661                                                 MLX5_WQE_DS(tso_header_sz) *
 662                                                 MLX5_WQE_DWORD_SIZE;
 663                                         rte_memcpy((void *)raw,
 664                                                    (void *)&inl, sizeof(inl));
 665                                         raw += sizeof(inl);
 666                                         pkt_inline_sz += sizeof(inl);
 667                                 }
 668                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 669                                 addr += copy_b;
 670                                 length -= copy_b;
 671                                 pkt_inline_sz += copy_b;
 672                         }
 673                         /*
 674                          * 2 DWORDs consumed by the WQE header + ETH segment +
 675                          * the size of the inline part of the packet.
 676                          */
 677                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 678                         if (length > 0) {
 679                                 if (ds % (MLX5_WQE_SIZE /
 680                                           MLX5_WQE_DWORD_SIZE) == 0) {
 681                                         if (unlikely(--max_wqe == 0))
 682                                                 break;
 683                                         dseg = (volatile rte_v128u32_t *)
 684                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 685                                                            ds / 4);
 686                                 } else {
 687                                         dseg = (volatile rte_v128u32_t *)
 688                                                 ((uintptr_t)wqe +
 689                                                  (ds * MLX5_WQE_DWORD_SIZE));
 690                                 }
 691                                 goto use_dseg;
 692                         } else if (!segs_n) {
 693                                 goto next_pkt;
 694                         } else {
 695                                 /* dseg will be advance as part of next_seg */
 696                                 dseg = (volatile rte_v128u32_t *)
 697                                         ((uintptr_t)wqe +
 698                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 699                                 goto next_seg;
 700                         }
 701                 } else {
 702                         /*
 703                          * No inline has been done in the packet, only the
 704                          * Ethernet Header as been stored.
 705                          */
 706                         dseg = (volatile rte_v128u32_t *)
 707                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 708                         ds = 3;
 709 use_dseg:
 710                         /* Add the remaining packet as a simple ds. */
 711                         naddr = htonll(addr);
 712                         *dseg = (rte_v128u32_t){
 713                                 htonl(length),
 714                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 715                                 naddr,
 716                                 naddr >> 32,
 717                         };
 718                         ++ds;
 719                         if (!segs_n)
 720                                 goto next_pkt;
 721                 }
 722 next_seg:
 723                 assert(buf);
 724                 assert(ds);
 725                 assert(wqe);
 726                 /*
 727                  * Spill on next WQE when the current one does not have
 728                  * enough room left. Size of WQE must a be a multiple
 729                  * of data segment size.
 730                  */
 731                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 732                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 733                         if (unlikely(--max_wqe == 0))
 734                                 break;
 735                         dseg = (volatile rte_v128u32_t *)
 736                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 737                         rte_prefetch0(tx_mlx5_wqe(txq,
 738                                                   txq->wqe_ci + ds / 4 + 1));
 739                 } else {
 740                         ++dseg;
 741                 }
 742                 ++ds;
 743                 buf = buf->next;
 744                 assert(buf);
 745                 length = DATA_LEN(buf);
 746 #ifdef MLX5_PMD_SOFT_COUNTERS
 747                 total_length += length;
 748 #endif
 749                 /* Store segment information. */
 750                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 751                 *dseg = (rte_v128u32_t){
 752                         htonl(length),
 753                         txq_mp2mr(txq, txq_mb2mp(buf)),
 754                         naddr,
 755                         naddr >> 32,
 756                 };
 757                 (*txq->elts)[elts_head] = buf;
 758                 elts_head = (elts_head + 1) & (elts_n - 1);
 759                 ++j;
 760                 --segs_n;
 761                 if (segs_n)
 762                         goto next_seg;
 763                 else
 764                         --pkts_n;
 765 next_pkt:
 766                 ++i;
 767                 /* Initialize known and common part of the WQE structure. */
 768                 if (tso) {
 769                         wqe->ctrl = (rte_v128u32_t){
 770                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 771                                 htonl(txq->qp_num_8s | ds),
 772                                 0,
 773                                 0,
 774                         };
 775                         wqe->eseg = (rte_v128u32_t){
 776                                 0,
 777                                 cs_flags | (htons(buf->tso_segsz) << 16),
 778                                 0,
 779                                 (ehdr << 16) | htons(tso_header_sz),
 780                         };
 781                 } else {
 782                         wqe->ctrl = (rte_v128u32_t){
 783                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 784                                 htonl(txq->qp_num_8s | ds),
 785                                 0,
 786                                 0,
 787                         };
 788                         wqe->eseg = (rte_v128u32_t){
 789                                 0,
 790                                 cs_flags,
 791                                 0,
 792                                 (ehdr << 16) | htons(pkt_inline_sz),
 793                         };
 794                 }
 795 next_wqe:
 796                 txq->wqe_ci += (ds + 3) / 4;
 797 #ifdef MLX5_PMD_SOFT_COUNTERS
 798                 /* Increment sent bytes counter. */
 799                 txq->stats.obytes += total_length;
 800 #endif
 801         } while (pkts_n);
 802         /* Take a shortcut if nothing must be sent. */
 803         if (unlikely((i + k) == 0))
 804                 return 0;
 805         /* Check whether completion threshold has been reached. */
 806         comp = txq->elts_comp + i + j + k;
 807         if (comp >= MLX5_TX_COMP_THRESH) {
 808                 volatile struct mlx5_wqe_ctrl *w =
 809                         (volatile struct mlx5_wqe_ctrl *)wqe;
 810
 811                 /* Request completion on last WQE. */
 812                 w->ctrl2 = htonl(8);
 813                 /* Save elts_head in unused "immediate" field of WQE. */
 814                 w->ctrl3 = elts_head;
 815                 txq->elts_comp = 0;
 816         } else {
 817                 txq->elts_comp = comp;
 818         }
 819 #ifdef MLX5_PMD_SOFT_COUNTERS
 820         /* Increment sent packets counter. */
 821         txq->stats.opackets += i;
 822 #endif
 823         /* Ring QP doorbell. */
 824         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 825         txq->elts_head = elts_head;
 826         return i;
 827 }
 828
 829 /**
 830  * Open a MPW session.
 831  *
 832  * @param txq
 833  *   Pointer to TX queue structure.
 834  * @param mpw
 835  *   Pointer to MPW session structure.
 836  * @param length
 837  *   Packet length.
 838  */
 839 static inline void
 840 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 841 {
 842         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 843         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 844                 (volatile struct mlx5_wqe_data_seg (*)[])
 845                 tx_mlx5_wqe(txq, idx + 1);
 846
 847         mpw->state = MLX5_MPW_STATE_OPENED;
 848         mpw->pkts_n = 0;
 849         mpw->len = length;
 850         mpw->total_len = 0;
 851         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 852         mpw->wqe->eseg.mss = htons(length);
 853         mpw->wqe->eseg.inline_hdr_sz = 0;
 854         mpw->wqe->eseg.rsvd0 = 0;
 855         mpw->wqe->eseg.rsvd1 = 0;
 856         mpw->wqe->eseg.rsvd2 = 0;
 857         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 858                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 859         mpw->wqe->ctrl[2] = 0;
 860         mpw->wqe->ctrl[3] = 0;
 861         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 862                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 863         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 864                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 865         mpw->data.dseg[2] = &(*dseg)[0];
 866         mpw->data.dseg[3] = &(*dseg)[1];
 867         mpw->data.dseg[4] = &(*dseg)[2];
 868 }
 869
 870 /**
 871  * Close a MPW session.
 872  *
 873  * @param txq
 874  *   Pointer to TX queue structure.
 875  * @param mpw
 876  *   Pointer to MPW session structure.
 877  */
 878 static inline void
 879 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 880 {
 881         unsigned int num = mpw->pkts_n;
 882
 883         /*
 884          * Store size in multiple of 16 bytes. Control and Ethernet segments
 885          * count as 2.
 886          */
 887         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 888         mpw->state = MLX5_MPW_STATE_CLOSED;
 889         if (num < 3)
 890                 ++txq->wqe_ci;
 891         else
 892                 txq->wqe_ci += 2;
 893         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 894         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 895 }
 896
 897 /**
 898  * DPDK callback for TX with MPW support.
 899  *
 900  * @param dpdk_txq
 901  *   Generic pointer to TX queue structure.
 902  * @param[in] pkts
 903  *   Packets to transmit.
 904  * @param pkts_n
 905  *   Number of packets in array.
 906  *
 907  * @return
 908  *   Number of packets successfully transmitted (<= pkts_n).
 909  */
 910 uint16_t
 911 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 912 {
 913         struct txq *txq = (struct txq *)dpdk_txq;
 914         uint16_t elts_head = txq->elts_head;
 915         const unsigned int elts_n = 1 << txq->elts_n;
 916         unsigned int i = 0;
 917         unsigned int j = 0;
 918         unsigned int max;
 919         uint16_t max_wqe;
 920         unsigned int comp;
 921         struct mlx5_mpw mpw = {
 922                 .state = MLX5_MPW_STATE_CLOSED,
 923         };
 924
 925         if (unlikely(!pkts_n))
 926                 return 0;
 927         /* Prefetch first packet cacheline. */
 928         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 929         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 930         /* Start processing. */
 931         txq_complete(txq);
 932         max = (elts_n - (elts_head - txq->elts_tail));
 933         if (max > elts_n)
 934                 max -= elts_n;
 935         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 936         if (unlikely(!max_wqe))
 937                 return 0;
 938         do {
 939                 struct rte_mbuf *buf = *(pkts++);
 940                 unsigned int elts_head_next;
 941                 uint32_t length;
 942                 unsigned int segs_n = buf->nb_segs;
 943                 uint32_t cs_flags = 0;
 944
 945                 /*
 946                  * Make sure there is enough room to store this packet and
 947                  * that one ring entry remains unused.
 948                  */
 949                 assert(segs_n);
 950                 if (max < segs_n + 1)
 951                         break;
 952                 /* Do not bother with large packets MPW cannot handle. */
 953                 if (segs_n > MLX5_MPW_DSEG_MAX)
 954                         break;
 955                 max -= segs_n;
 956                 --pkts_n;
 957                 /* Should we enable HW CKSUM offload */
 958                 if (buf->ol_flags &
 959                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
 960                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
 961                 /* Retrieve packet information. */
 962                 length = PKT_LEN(buf);
 963                 assert(length);
 964                 /* Start new session if packet differs. */
 965                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 966                     ((mpw.len != length) ||
 967                      (segs_n != 1) ||
 968                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 969                         mlx5_mpw_close(txq, &mpw);
 970                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 971                         /*
 972                          * Multi-Packet WQE consumes at most two WQE.
 973                          * mlx5_mpw_new() expects to be able to use such
 974                          * resources.
 975                          */
 976                         if (unlikely(max_wqe < 2))
 977                                 break;
 978                         max_wqe -= 2;
 979                         mlx5_mpw_new(txq, &mpw, length);
 980                         mpw.wqe->eseg.cs_flags = cs_flags;
 981                 }
 982                 /* Multi-segment packets must be alone in their MPW. */
 983                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 984 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 985                 length = 0;
 986 #endif
 987                 do {
 988                         volatile struct mlx5_wqe_data_seg *dseg;
 989                         uintptr_t addr;
 990
 991                         elts_head_next = (elts_head + 1) & (elts_n - 1);
 992                         assert(buf);
 993                         (*txq->elts)[elts_head] = buf;
 994                         dseg = mpw.data.dseg[mpw.pkts_n];
 995                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 996                         *dseg = (struct mlx5_wqe_data_seg){
 997                                 .byte_count = htonl(DATA_LEN(buf)),
 998                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
 999                                 .addr = htonll(addr),
1000                         };
1001                         elts_head = elts_head_next;
1002 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1003                         length += DATA_LEN(buf);
1004 #endif
1005                         buf = buf->next;
1006                         ++mpw.pkts_n;
1007                         ++j;
1008                 } while (--segs_n);
1009                 assert(length == mpw.len);
1010                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1011                         mlx5_mpw_close(txq, &mpw);
1012                 elts_head = elts_head_next;
1013 #ifdef MLX5_PMD_SOFT_COUNTERS
1014                 /* Increment sent bytes counter. */
1015                 txq->stats.obytes += length;
1016 #endif
1017                 ++i;
1018         } while (pkts_n);
1019         /* Take a shortcut if nothing must be sent. */
1020         if (unlikely(i == 0))
1021                 return 0;
1022         /* Check whether completion threshold has been reached. */
1023         /* "j" includes both packets and segments. */
1024         comp = txq->elts_comp + j;
1025         if (comp >= MLX5_TX_COMP_THRESH) {
1026                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1027
1028                 /* Request completion on last WQE. */
1029                 wqe->ctrl[2] = htonl(8);
1030                 /* Save elts_head in unused "immediate" field of WQE. */
1031                 wqe->ctrl[3] = elts_head;
1032                 txq->elts_comp = 0;
1033         } else {
1034                 txq->elts_comp = comp;
1035         }
1036 #ifdef MLX5_PMD_SOFT_COUNTERS
1037         /* Increment sent packets counter. */
1038         txq->stats.opackets += i;
1039 #endif
1040         /* Ring QP doorbell. */
1041         if (mpw.state == MLX5_MPW_STATE_OPENED)
1042                 mlx5_mpw_close(txq, &mpw);
1043         mlx5_tx_dbrec(txq, mpw.wqe);
1044         txq->elts_head = elts_head;
1045         return i;
1046 }
1047
1048 /**
1049  * Open a MPW inline session.
1050  *
1051  * @param txq
1052  *   Pointer to TX queue structure.
1053  * @param mpw
1054  *   Pointer to MPW session structure.
1055  * @param length
1056  *   Packet length.
1057  */
1058 static inline void
1059 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1060 {
1061         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1062         struct mlx5_wqe_inl_small *inl;
1063
1064         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1065         mpw->pkts_n = 0;
1066         mpw->len = length;
1067         mpw->total_len = 0;
1068         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1069         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1070                                   (txq->wqe_ci << 8) |
1071                                   MLX5_OPCODE_TSO);
1072         mpw->wqe->ctrl[2] = 0;
1073         mpw->wqe->ctrl[3] = 0;
1074         mpw->wqe->eseg.mss = htons(length);
1075         mpw->wqe->eseg.inline_hdr_sz = 0;
1076         mpw->wqe->eseg.cs_flags = 0;
1077         mpw->wqe->eseg.rsvd0 = 0;
1078         mpw->wqe->eseg.rsvd1 = 0;
1079         mpw->wqe->eseg.rsvd2 = 0;
1080         inl = (struct mlx5_wqe_inl_small *)
1081                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1082         mpw->data.raw = (uint8_t *)&inl->raw;
1083 }
1084
1085 /**
1086  * Close a MPW inline session.
1087  *
1088  * @param txq
1089  *   Pointer to TX queue structure.
1090  * @param mpw
1091  *   Pointer to MPW session structure.
1092  */
1093 static inline void
1094 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1095 {
1096         unsigned int size;
1097         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1098                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1099
1100         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1101         /*
1102          * Store size in multiple of 16 bytes. Control and Ethernet segments
1103          * count as 2.
1104          */
1105         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1106         mpw->state = MLX5_MPW_STATE_CLOSED;
1107         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1108         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1109 }
1110
1111 /**
1112  * DPDK callback for TX with MPW inline support.
1113  *
1114  * @param dpdk_txq
1115  *   Generic pointer to TX queue structure.
1116  * @param[in] pkts
1117  *   Packets to transmit.
1118  * @param pkts_n
1119  *   Number of packets in array.
1120  *
1121  * @return
1122  *   Number of packets successfully transmitted (<= pkts_n).
1123  */
1124 uint16_t
1125 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1126                          uint16_t pkts_n)
1127 {
1128         struct txq *txq = (struct txq *)dpdk_txq;
1129         uint16_t elts_head = txq->elts_head;
1130         const unsigned int elts_n = 1 << txq->elts_n;
1131         unsigned int i = 0;
1132         unsigned int j = 0;
1133         unsigned int max;
1134         uint16_t max_wqe;
1135         unsigned int comp;
1136         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1137         struct mlx5_mpw mpw = {
1138                 .state = MLX5_MPW_STATE_CLOSED,
1139         };
1140         /*
1141          * Compute the maximum number of WQE which can be consumed by inline
1142          * code.
1143          * - 2 DSEG for:
1144          *   - 1 control segment,
1145          *   - 1 Ethernet segment,
1146          * - N Dseg from the inline request.
1147          */
1148         const unsigned int wqe_inl_n =
1149                 ((2 * MLX5_WQE_DWORD_SIZE +
1150                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1151                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1152
1153         if (unlikely(!pkts_n))
1154                 return 0;
1155         /* Prefetch first packet cacheline. */
1156         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1157         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1158         /* Start processing. */
1159         txq_complete(txq);
1160         max = (elts_n - (elts_head - txq->elts_tail));
1161         if (max > elts_n)
1162                 max -= elts_n;
1163         do {
1164                 struct rte_mbuf *buf = *(pkts++);
1165                 unsigned int elts_head_next;
1166                 uintptr_t addr;
1167                 uint32_t length;
1168                 unsigned int segs_n = buf->nb_segs;
1169                 uint32_t cs_flags = 0;
1170
1171                 /*
1172                  * Make sure there is enough room to store this packet and
1173                  * that one ring entry remains unused.
1174                  */
1175                 assert(segs_n);
1176                 if (max < segs_n + 1)
1177                         break;
1178                 /* Do not bother with large packets MPW cannot handle. */
1179                 if (segs_n > MLX5_MPW_DSEG_MAX)
1180                         break;
1181                 max -= segs_n;
1182                 --pkts_n;
1183                 /*
1184                  * Compute max_wqe in case less WQE were consumed in previous
1185                  * iteration.
1186                  */
1187                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1188                 /* Should we enable HW CKSUM offload */
1189                 if (buf->ol_flags &
1190                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1191                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1192                 /* Retrieve packet information. */
1193                 length = PKT_LEN(buf);
1194                 /* Start new session if packet differs. */
1195                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1196                         if ((mpw.len != length) ||
1197                             (segs_n != 1) ||
1198                             (mpw.wqe->eseg.cs_flags != cs_flags))
1199                                 mlx5_mpw_close(txq, &mpw);
1200                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1201                         if ((mpw.len != length) ||
1202                             (segs_n != 1) ||
1203                             (length > inline_room) ||
1204                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1205                                 mlx5_mpw_inline_close(txq, &mpw);
1206                                 inline_room =
1207                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1208                         }
1209                 }
1210                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1211                         if ((segs_n != 1) ||
1212                             (length > inline_room)) {
1213                                 /*
1214                                  * Multi-Packet WQE consumes at most two WQE.
1215                                  * mlx5_mpw_new() expects to be able to use
1216                                  * such resources.
1217                                  */
1218                                 if (unlikely(max_wqe < 2))
1219                                         break;
1220                                 max_wqe -= 2;
1221                                 mlx5_mpw_new(txq, &mpw, length);
1222                                 mpw.wqe->eseg.cs_flags = cs_flags;
1223                         } else {
1224                                 if (unlikely(max_wqe < wqe_inl_n))
1225                                         break;
1226                                 max_wqe -= wqe_inl_n;
1227                                 mlx5_mpw_inline_new(txq, &mpw, length);
1228                                 mpw.wqe->eseg.cs_flags = cs_flags;
1229                         }
1230                 }
1231                 /* Multi-segment packets must be alone in their MPW. */
1232                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1233                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1234                         assert(inline_room ==
1235                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1236 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1237                         length = 0;
1238 #endif
1239                         do {
1240                                 volatile struct mlx5_wqe_data_seg *dseg;
1241
1242                                 elts_head_next =
1243                                         (elts_head + 1) & (elts_n - 1);
1244                                 assert(buf);
1245                                 (*txq->elts)[elts_head] = buf;
1246                                 dseg = mpw.data.dseg[mpw.pkts_n];
1247                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1248                                 *dseg = (struct mlx5_wqe_data_seg){
1249                                         .byte_count = htonl(DATA_LEN(buf)),
1250                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1251                                         .addr = htonll(addr),
1252                                 };
1253                                 elts_head = elts_head_next;
1254 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1255                                 length += DATA_LEN(buf);
1256 #endif
1257                                 buf = buf->next;
1258                                 ++mpw.pkts_n;
1259                                 ++j;
1260                         } while (--segs_n);
1261                         assert(length == mpw.len);
1262                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1263                                 mlx5_mpw_close(txq, &mpw);
1264                 } else {
1265                         unsigned int max;
1266
1267                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1268                         assert(length <= inline_room);
1269                         assert(length == DATA_LEN(buf));
1270                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1271                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1272                         (*txq->elts)[elts_head] = buf;
1273                         /* Maximum number of bytes before wrapping. */
1274                         max = ((((uintptr_t)(txq->wqes)) +
1275                                 (1 << txq->wqe_n) *
1276                                 MLX5_WQE_SIZE) -
1277                                (uintptr_t)mpw.data.raw);
1278                         if (length > max) {
1279                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1280                                            (void *)addr,
1281                                            max);
1282                                 mpw.data.raw = (volatile void *)txq->wqes;
1283                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1284                                            (void *)(addr + max),
1285                                            length - max);
1286                                 mpw.data.raw += length - max;
1287                         } else {
1288                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1289                                            (void *)addr,
1290                                            length);
1291
1292                                 if (length == max)
1293                                         mpw.data.raw =
1294                                                 (volatile void *)txq->wqes;
1295                                 else
1296                                         mpw.data.raw += length;
1297                         }
1298                         ++mpw.pkts_n;
1299                         mpw.total_len += length;
1300                         ++j;
1301                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1302                                 mlx5_mpw_inline_close(txq, &mpw);
1303                                 inline_room =
1304                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1305                         } else {
1306                                 inline_room -= length;
1307                         }
1308                 }
1309                 elts_head = elts_head_next;
1310 #ifdef MLX5_PMD_SOFT_COUNTERS
1311                 /* Increment sent bytes counter. */
1312                 txq->stats.obytes += length;
1313 #endif
1314                 ++i;
1315         } while (pkts_n);
1316         /* Take a shortcut if nothing must be sent. */
1317         if (unlikely(i == 0))
1318                 return 0;
1319         /* Check whether completion threshold has been reached. */
1320         /* "j" includes both packets and segments. */
1321         comp = txq->elts_comp + j;
1322         if (comp >= MLX5_TX_COMP_THRESH) {
1323                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1324
1325                 /* Request completion on last WQE. */
1326                 wqe->ctrl[2] = htonl(8);
1327                 /* Save elts_head in unused "immediate" field of WQE. */
1328                 wqe->ctrl[3] = elts_head;
1329                 txq->elts_comp = 0;
1330         } else {
1331                 txq->elts_comp = comp;
1332         }
1333 #ifdef MLX5_PMD_SOFT_COUNTERS
1334         /* Increment sent packets counter. */
1335         txq->stats.opackets += i;
1336 #endif
1337         /* Ring QP doorbell. */
1338         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1339                 mlx5_mpw_inline_close(txq, &mpw);
1340         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1341                 mlx5_mpw_close(txq, &mpw);
1342         mlx5_tx_dbrec(txq, mpw.wqe);
1343         txq->elts_head = elts_head;
1344         return i;
1345 }
1346
1347 /**
1348  * Translate RX completion flags to packet type.
1349  *
1350  * @param[in] cqe
1351  *   Pointer to CQE.
1352  *
1353  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1354  *
1355  * @return
1356  *   Packet type for struct rte_mbuf.
1357  */
1358 static inline uint32_t
1359 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1360 {
1361         uint32_t pkt_type;
1362         uint16_t flags = ntohs(cqe->hdr_type_etc);
1363
1364         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1365                 pkt_type =
1366                         TRANSPOSE(flags,
1367                                   MLX5_CQE_RX_IPV4_PACKET,
1368                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1369                         TRANSPOSE(flags,
1370                                   MLX5_CQE_RX_IPV6_PACKET,
1371                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1372                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1373                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1374                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1375         } else {
1376                 pkt_type =
1377                         TRANSPOSE(flags,
1378                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1379                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1380                         TRANSPOSE(flags,
1381                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1382                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1383         }
1384         return pkt_type;
1385 }
1386
1387 /**
1388  * Get size of the next packet for a given CQE. For compressed CQEs, the
1389  * consumer index is updated only once all packets of the current one have
1390  * been processed.
1391  *
1392  * @param rxq
1393  *   Pointer to RX queue.
1394  * @param cqe
1395  *   CQE to process.
1396  * @param[out] rss_hash
1397  *   Packet RSS Hash result.
1398  *
1399  * @return
1400  *   Packet size in bytes (0 if there is none), -1 in case of completion
1401  *   with error.
1402  */
1403 static inline int
1404 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1405                  uint16_t cqe_cnt, uint32_t *rss_hash)
1406 {
1407         struct rxq_zip *zip = &rxq->zip;
1408         uint16_t cqe_n = cqe_cnt + 1;
1409         int len = 0;
1410         uint16_t idx, end;
1411
1412         /* Process compressed data in the CQE and mini arrays. */
1413         if (zip->ai) {
1414                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1415                         (volatile struct mlx5_mini_cqe8 (*)[8])
1416                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1417
1418                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1419                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1420                 if ((++zip->ai & 7) == 0) {
1421                         /* Invalidate consumed CQEs */
1422                         idx = zip->ca;
1423                         end = zip->na;
1424                         while (idx != end) {
1425                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1426                                         MLX5_CQE_INVALIDATE;
1427                                 ++idx;
1428                         }
1429                         /*
1430                          * Increment consumer index to skip the number of
1431                          * CQEs consumed. Hardware leaves holes in the CQ
1432                          * ring for software use.
1433                          */
1434                         zip->ca = zip->na;
1435                         zip->na += 8;
1436                 }
1437                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1438                         /* Invalidate the rest */
1439                         idx = zip->ca;
1440                         end = zip->cq_ci;
1441
1442                         while (idx != end) {
1443                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1444                                         MLX5_CQE_INVALIDATE;
1445                                 ++idx;
1446                         }
1447                         rxq->cq_ci = zip->cq_ci;
1448                         zip->ai = 0;
1449                 }
1450         /* No compressed data, get next CQE and verify if it is compressed. */
1451         } else {
1452                 int ret;
1453                 int8_t op_own;
1454
1455                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1456                 if (unlikely(ret == 1))
1457                         return 0;
1458                 ++rxq->cq_ci;
1459                 op_own = cqe->op_own;
1460                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1461                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1462                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1463                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1464                                                           cqe_cnt]);
1465
1466                         /* Fix endianness. */
1467                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1468                         /*
1469                          * Current mini array position is the one returned by
1470                          * check_cqe64().
1471                          *
1472                          * If completion comprises several mini arrays, as a
1473                          * special case the second one is located 7 CQEs after
1474                          * the initial CQE instead of 8 for subsequent ones.
1475                          */
1476                         zip->ca = rxq->cq_ci;
1477                         zip->na = zip->ca + 7;
1478                         /* Compute the next non compressed CQE. */
1479                         --rxq->cq_ci;
1480                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1481                         /* Get packet size to return. */
1482                         len = ntohl((*mc)[0].byte_cnt);
1483                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1484                         zip->ai = 1;
1485                         /* Prefetch all the entries to be invalidated */
1486                         idx = zip->ca;
1487                         end = zip->cq_ci;
1488                         while (idx != end) {
1489                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1490                                 ++idx;
1491                         }
1492                 } else {
1493                         len = ntohl(cqe->byte_cnt);
1494                         *rss_hash = ntohl(cqe->rx_hash_res);
1495                 }
1496                 /* Error while receiving packet. */
1497                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1498                         return -1;
1499         }
1500         return len;
1501 }
1502
1503 /**
1504  * Translate RX completion flags to offload flags.
1505  *
1506  * @param[in] rxq
1507  *   Pointer to RX queue structure.
1508  * @param[in] cqe
1509  *   Pointer to CQE.
1510  *
1511  * @return
1512  *   Offload flags (ol_flags) for struct rte_mbuf.
1513  */
1514 static inline uint32_t
1515 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1516 {
1517         uint32_t ol_flags = 0;
1518         uint16_t flags = ntohs(cqe->hdr_type_etc);
1519
1520         ol_flags =
1521                 TRANSPOSE(flags,
1522                           MLX5_CQE_RX_L3_HDR_VALID,
1523                           PKT_RX_IP_CKSUM_GOOD) |
1524                 TRANSPOSE(flags,
1525                           MLX5_CQE_RX_L4_HDR_VALID,
1526                           PKT_RX_L4_CKSUM_GOOD);
1527         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1528                 ol_flags |=
1529                         TRANSPOSE(flags,
1530                                   MLX5_CQE_RX_L3_HDR_VALID,
1531                                   PKT_RX_IP_CKSUM_GOOD) |
1532                         TRANSPOSE(flags,
1533                                   MLX5_CQE_RX_L4_HDR_VALID,
1534                                   PKT_RX_L4_CKSUM_GOOD);
1535         return ol_flags;
1536 }
1537
1538 /**
1539  * DPDK callback for RX.
1540  *
1541  * @param dpdk_rxq
1542  *   Generic pointer to RX queue structure.
1543  * @param[out] pkts
1544  *   Array to store received packets.
1545  * @param pkts_n
1546  *   Maximum number of packets in array.
1547  *
1548  * @return
1549  *   Number of packets successfully received (<= pkts_n).
1550  */
1551 uint16_t
1552 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1553 {
1554         struct rxq *rxq = dpdk_rxq;
1555         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1556         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1557         const unsigned int sges_n = rxq->sges_n;
1558         struct rte_mbuf *pkt = NULL;
1559         struct rte_mbuf *seg = NULL;
1560         volatile struct mlx5_cqe *cqe =
1561                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1562         unsigned int i = 0;
1563         unsigned int rq_ci = rxq->rq_ci << sges_n;
1564         int len; /* keep its value across iterations. */
1565
1566         while (pkts_n) {
1567                 unsigned int idx = rq_ci & wqe_cnt;
1568                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1569                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1570                 uint32_t rss_hash_res = 0;
1571
1572                 if (pkt)
1573                         NEXT(seg) = rep;
1574                 seg = rep;
1575                 rte_prefetch0(seg);
1576                 rte_prefetch0(cqe);
1577                 rte_prefetch0(wqe);
1578                 rep = rte_mbuf_raw_alloc(rxq->mp);
1579                 if (unlikely(rep == NULL)) {
1580                         ++rxq->stats.rx_nombuf;
1581                         if (!pkt) {
1582                                 /*
1583                                  * no buffers before we even started,
1584                                  * bail out silently.
1585                                  */
1586                                 break;
1587                         }
1588                         while (pkt != seg) {
1589                                 assert(pkt != (*rxq->elts)[idx]);
1590                                 rep = NEXT(pkt);
1591                                 rte_mbuf_refcnt_set(pkt, 0);
1592                                 __rte_mbuf_raw_free(pkt);
1593                                 pkt = rep;
1594                         }
1595                         break;
1596                 }
1597                 if (!pkt) {
1598                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1599                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1600                                                &rss_hash_res);
1601                         if (!len) {
1602                                 rte_mbuf_refcnt_set(rep, 0);
1603                                 __rte_mbuf_raw_free(rep);
1604                                 break;
1605                         }
1606                         if (unlikely(len == -1)) {
1607                                 /* RX error, packet is likely too large. */
1608                                 rte_mbuf_refcnt_set(rep, 0);
1609                                 __rte_mbuf_raw_free(rep);
1610                                 ++rxq->stats.idropped;
1611                                 goto skip;
1612                         }
1613                         pkt = seg;
1614                         assert(len >= (rxq->crc_present << 2));
1615                         /* Update packet information. */
1616                         pkt->packet_type = 0;
1617                         pkt->ol_flags = 0;
1618                         if (rss_hash_res && rxq->rss_hash) {
1619                                 pkt->hash.rss = rss_hash_res;
1620                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1621                         }
1622                         if (rxq->mark && (cqe->sop_drop_qpn !=
1623                                           htonl(MLX5_FLOW_MARK_INVALID))) {
1624                                 pkt->ol_flags |= PKT_RX_FDIR;
1625                                 if (cqe->sop_drop_qpn !=
1626                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
1627                                         uint32_t mark = cqe->sop_drop_qpn;
1628
1629                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1630                                         pkt->hash.fdir.hi =
1631                                                 mlx5_flow_mark_get(mark);
1632                                 }
1633                         }
1634                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1635                             rxq->crc_present) {
1636                                 if (rxq->csum) {
1637                                         pkt->packet_type =
1638                                                 rxq_cq_to_pkt_type(cqe);
1639                                         pkt->ol_flags |=
1640                                                 rxq_cq_to_ol_flags(rxq, cqe);
1641                                 }
1642                                 if (ntohs(cqe->hdr_type_etc) &
1643                                     MLX5_CQE_VLAN_STRIPPED) {
1644                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
1645                                                 PKT_RX_VLAN_STRIPPED;
1646                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
1647                                 }
1648                                 if (rxq->crc_present)
1649                                         len -= ETHER_CRC_LEN;
1650                         }
1651                         PKT_LEN(pkt) = len;
1652                 }
1653                 DATA_LEN(rep) = DATA_LEN(seg);
1654                 PKT_LEN(rep) = PKT_LEN(seg);
1655                 SET_DATA_OFF(rep, DATA_OFF(seg));
1656                 NB_SEGS(rep) = NB_SEGS(seg);
1657                 PORT(rep) = PORT(seg);
1658                 NEXT(rep) = NULL;
1659                 (*rxq->elts)[idx] = rep;
1660                 /*
1661                  * Fill NIC descriptor with the new buffer.  The lkey and size
1662                  * of the buffers are already known, only the buffer address
1663                  * changes.
1664                  */
1665                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1666                 if (len > DATA_LEN(seg)) {
1667                         len -= DATA_LEN(seg);
1668                         ++NB_SEGS(pkt);
1669                         ++rq_ci;
1670                         continue;
1671                 }
1672                 DATA_LEN(seg) = len;
1673 #ifdef MLX5_PMD_SOFT_COUNTERS
1674                 /* Increment bytes counter. */
1675                 rxq->stats.ibytes += PKT_LEN(pkt);
1676 #endif
1677                 /* Return packet. */
1678                 *(pkts++) = pkt;
1679                 pkt = NULL;
1680                 --pkts_n;
1681                 ++i;
1682 skip:
1683                 /* Align consumer index to the next stride. */
1684                 rq_ci >>= sges_n;
1685                 ++rq_ci;
1686                 rq_ci <<= sges_n;
1687         }
1688         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1689                 return 0;
1690         /* Update the consumer index. */
1691         rxq->rq_ci = rq_ci >> sges_n;
1692         rte_wmb();
1693         *rxq->cq_db = htonl(rxq->cq_ci);
1694         rte_wmb();
1695         *rxq->rq_db = htonl(rxq->rq_ci);
1696 #ifdef MLX5_PMD_SOFT_COUNTERS
1697         /* Increment packets counter. */
1698         rxq->stats.ipackets += i;
1699 #endif
1700         return i;
1701 }
1702
1703 /**
1704  * Dummy DPDK callback for TX.
1705  *
1706  * This function is used to temporarily replace the real callback during
1707  * unsafe control operations on the queue, or in case of error.
1708  *
1709  * @param dpdk_txq
1710  *   Generic pointer to TX queue structure.
1711  * @param[in] pkts
1712  *   Packets to transmit.
1713  * @param pkts_n
1714  *   Number of packets in array.
1715  *
1716  * @return
1717  *   Number of packets successfully transmitted (<= pkts_n).
1718  */
1719 uint16_t
1720 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1721 {
1722         (void)dpdk_txq;
1723         (void)pkts;
1724         (void)pkts_n;
1725         return 0;
1726 }
1727
1728 /**
1729  * Dummy DPDK callback for RX.
1730  *
1731  * This function is used to temporarily replace the real callback during
1732  * unsafe control operations on the queue, or in case of error.
1733  *
1734  * @param dpdk_rxq
1735  *   Generic pointer to RX queue structure.
1736  * @param[out] pkts
1737  *   Array to store received packets.
1738  * @param pkts_n
1739  *   Maximum number of packets in array.
1740  *
1741  * @return
1742  *   Number of packets successfully received (<= pkts_n).
1743  */
1744 uint16_t
1745 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1746 {
1747         (void)dpdk_rxq;
1748         (void)pkts;
1749         (void)pkts_n;
1750         return 0;
1751 }