drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         /* UDP */
 118         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_UDP;
 120         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_UDP;
 122         /* Repeat with outer_l3_type being set. Just in case. */
 123         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_NONFRAG;
 125         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_NONFRAG;
 127         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_FRAG;
 129         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_FRAG;
 131         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_TCP;
 135         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_UDP;
 139         /* Tunneled - L3 */
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         /* Tunneled - UDP */
 179         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_UDP;
 182         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_UDP;
 185         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_UDP;
 188         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_UDP;
 191 }
 192
 193 /**
 194  * Return the size of tailroom of WQ.
 195  *
 196  * @param txq
 197  *   Pointer to TX queue structure.
 198  * @param addr
 199  *   Pointer to tail of WQ.
 200  *
 201  * @return
 202  *   Size of tailroom.
 203  */
 204 static inline size_t
 205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 206 {
 207         size_t tailroom;
 208         tailroom = (uintptr_t)(txq->wqes) +
 209                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 210                    (uintptr_t)addr;
 211         return tailroom;
 212 }
 213
 214 /**
 215  * Copy data to tailroom of circular queue.
 216  *
 217  * @param dst
 218  *   Pointer to destination.
 219  * @param src
 220  *   Pointer to source.
 221  * @param n
 222  *   Number of bytes to copy.
 223  * @param base
 224  *   Pointer to head of queue.
 225  * @param tailroom
 226  *   Size of tailroom from dst.
 227  *
 228  * @return
 229  *   Pointer after copied data.
 230  */
 231 static inline void *
 232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 233                 void *base, size_t tailroom)
 234 {
 235         void *ret;
 236
 237         if (n > tailroom) {
 238                 rte_memcpy(dst, src, tailroom);
 239                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 240                            n - tailroom);
 241                 ret = (uint8_t *)base + n - tailroom;
 242         } else {
 243                 rte_memcpy(dst, src, n);
 244                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 245         }
 246         return ret;
 247 }
 248
 249 /**
 250  * DPDK callback to check the status of a tx descriptor.
 251  *
 252  * @param tx_queue
 253  *   The tx queue.
 254  * @param[in] offset
 255  *   The index of the descriptor in the ring.
 256  *
 257  * @return
 258  *   The status of the tx descriptor.
 259  */
 260 int
 261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 262 {
 263         struct mlx5_txq_data *txq = tx_queue;
 264         uint16_t used;
 265
 266         mlx5_tx_complete(txq);
 267         used = txq->elts_head - txq->elts_tail;
 268         if (offset < used)
 269                 return RTE_ETH_TX_DESC_FULL;
 270         return RTE_ETH_TX_DESC_DONE;
 271 }
 272
 273 /**
 274  * DPDK callback to check the status of a rx descriptor.
 275  *
 276  * @param rx_queue
 277  *   The rx queue.
 278  * @param[in] offset
 279  *   The index of the descriptor in the ring.
 280  *
 281  * @return
 282  *   The status of the tx descriptor.
 283  */
 284 int
 285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 286 {
 287         struct mlx5_rxq_data *rxq = rx_queue;
 288         struct rxq_zip *zip = &rxq->zip;
 289         volatile struct mlx5_cqe *cqe;
 290         const unsigned int cqe_n = (1 << rxq->cqe_n);
 291         const unsigned int cqe_cnt = cqe_n - 1;
 292         unsigned int cq_ci;
 293         unsigned int used;
 294
 295         /* if we are processing a compressed cqe */
 296         if (zip->ai) {
 297                 used = zip->cqe_cnt - zip->ca;
 298                 cq_ci = zip->cq_ci;
 299         } else {
 300                 used = 0;
 301                 cq_ci = rxq->cq_ci;
 302         }
 303         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 304         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 305                 int8_t op_own;
 306                 unsigned int n;
 307
 308                 op_own = cqe->op_own;
 309                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 310                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 311                 else
 312                         n = 1;
 313                 cq_ci += n;
 314                 used += n;
 315                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 316         }
 317         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 318         if (offset < used)
 319                 return RTE_ETH_RX_DESC_DONE;
 320         return RTE_ETH_RX_DESC_AVAIL;
 321 }
 322
 323 /**
 324  * DPDK callback for TX.
 325  *
 326  * @param dpdk_txq
 327  *   Generic pointer to TX queue structure.
 328  * @param[in] pkts
 329  *   Packets to transmit.
 330  * @param pkts_n
 331  *   Number of packets in array.
 332  *
 333  * @return
 334  *   Number of packets successfully transmitted (<= pkts_n).
 335  */
 336 uint16_t
 337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 338 {
 339         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 340         uint16_t elts_head = txq->elts_head;
 341         const uint16_t elts_n = 1 << txq->elts_n;
 342         const uint16_t elts_m = elts_n - 1;
 343         unsigned int i = 0;
 344         unsigned int j = 0;
 345         unsigned int k = 0;
 346         uint16_t max_elts;
 347         uint16_t max_wqe;
 348         unsigned int comp;
 349         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 350         unsigned int segs_n = 0;
 351         const unsigned int max_inline = txq->max_inline;
 352
 353         if (unlikely(!pkts_n))
 354                 return 0;
 355         /* Prefetch first packet cacheline. */
 356         rte_prefetch0(*pkts);
 357         /* Start processing. */
 358         mlx5_tx_complete(txq);
 359         max_elts = (elts_n - (elts_head - txq->elts_tail));
 360         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 361         if (unlikely(!max_wqe))
 362                 return 0;
 363         do {
 364                 struct rte_mbuf *buf = NULL;
 365                 uint8_t *raw;
 366                 volatile struct mlx5_wqe_v *wqe = NULL;
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 373                 uint16_t tso_header_sz = 0;
 374                 uint16_t ehdr;
 375                 uint8_t cs_flags;
 376                 uint64_t tso = 0;
 377                 uint16_t tso_segsz = 0;
 378 #ifdef MLX5_PMD_SOFT_COUNTERS
 379                 uint32_t total_length = 0;
 380 #endif
 381
 382                 /* first_seg */
 383                 buf = *pkts;
 384                 segs_n = buf->nb_segs;
 385                 /*
 386                  * Make sure there is enough room to store this packet and
 387                  * that one ring entry remains unused.
 388                  */
 389                 assert(segs_n);
 390                 if (max_elts < segs_n)
 391                         break;
 392                 max_elts -= segs_n;
 393                 sg = --segs_n;
 394                 if (unlikely(--max_wqe == 0))
 395                         break;
 396                 wqe = (volatile struct mlx5_wqe_v *)
 397                         tx_mlx5_wqe(txq, txq->wqe_ci);
 398                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 399                 if (pkts_n - i > 1)
 400                         rte_prefetch0(*(pkts + 1));
 401                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 402                 length = DATA_LEN(buf);
 403                 ehdr = (((uint8_t *)addr)[1] << 8) |
 404                        ((uint8_t *)addr)[0];
 405 #ifdef MLX5_PMD_SOFT_COUNTERS
 406                 total_length = length;
 407 #endif
 408                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 409                         txq->stats.oerrors++;
 410                         break;
 411                 }
 412                 /* Update element. */
 413                 (*txq->elts)[elts_head & elts_m] = buf;
 414                 /* Prefetch next buffer data. */
 415                 if (pkts_n - i > 1)
 416                         rte_prefetch0(
 417                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 418                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 419                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 420                 /* Replace the Ethernet type by the VLAN if necessary. */
 421                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 422                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 423                                                          buf->vlan_tci);
 424                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 425
 426                         addr += 2;
 427                         length -= 2;
 428                         /* Copy Destination and source mac address. */
 429                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 430                         /* Copy VLAN. */
 431                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 432                         /* Copy missing two bytes to end the DSeg. */
 433                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 434                                ((uint8_t *)addr) + len, 2);
 435                         addr += len + 2;
 436                         length -= (len + 2);
 437                 } else {
 438                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 439                                MLX5_WQE_DWORD_SIZE);
 440                         length -= pkt_inline_sz;
 441                         addr += pkt_inline_sz;
 442                 }
 443                 raw += MLX5_WQE_DWORD_SIZE;
 444                 tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 445                 if (tso) {
 446                         uintptr_t end =
 447                                 (uintptr_t)(((uintptr_t)txq->wqes) +
 448                                             (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 449                         unsigned int copy_b;
 450                         uint8_t vlan_sz =
 451                                 (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 452                         const uint64_t is_tunneled =
 453                                 buf->ol_flags & (PKT_TX_TUNNEL_GRE |
 454                                                  PKT_TX_TUNNEL_VXLAN);
 455
 456                         tso_header_sz = buf->l2_len + vlan_sz +
 457                                         buf->l3_len + buf->l4_len;
 458                         tso_segsz = buf->tso_segsz;
 459                         if (unlikely(tso_segsz == 0)) {
 460                                 txq->stats.oerrors++;
 461                                 break;
 462                         }
 463                         if (is_tunneled && txq->tunnel_en) {
 464                                 tso_header_sz += buf->outer_l2_len +
 465                                                  buf->outer_l3_len;
 466                                 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 467                         } else {
 468                                 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 469                         }
 470                         if (unlikely(tso_header_sz > MLX5_MAX_TSO_HEADER)) {
 471                                 txq->stats.oerrors++;
 472                                 break;
 473                         }
 474                         copy_b = tso_header_sz - pkt_inline_sz;
 475                         /* First seg must contain all headers. */
 476                         assert(copy_b <= length);
 477                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 478                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 479
 480                                 if (unlikely(max_wqe < n))
 481                                         break;
 482                                 max_wqe -= n;
 483                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 484                                 addr += copy_b;
 485                                 length -= copy_b;
 486                                 /* Include padding for TSO header. */
 487                                 copy_b = MLX5_WQE_DS(copy_b) *
 488                                          MLX5_WQE_DWORD_SIZE;
 489                                 pkt_inline_sz += copy_b;
 490                                 raw += copy_b;
 491                         } else {
 492                                 /* NOP WQE. */
 493                                 wqe->ctrl = (rte_v128u32_t){
 494                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 495                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 496                                         0,
 497                                         0,
 498                                 };
 499                                 ds = 1;
 500 #ifdef MLX5_PMD_SOFT_COUNTERS
 501                                 total_length = 0;
 502 #endif
 503                                 k++;
 504                                 goto next_wqe;
 505                         }
 506                 }
 507                 /* Inline if enough room. */
 508                 if (max_inline || tso) {
 509                         uint32_t inl = 0;
 510                         uintptr_t end = (uintptr_t)
 511                                 (((uintptr_t)txq->wqes) +
 512                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 513                         unsigned int inline_room = max_inline *
 514                                                    RTE_CACHE_LINE_SIZE -
 515                                                    (pkt_inline_sz - 2) -
 516                                                    !!tso * sizeof(inl);
 517                         uintptr_t addr_end;
 518                         unsigned int copy_b;
 519
 520 pkt_inline:
 521                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 522                                                    RTE_CACHE_LINE_SIZE);
 523                         copy_b = (addr_end > addr) ?
 524                                  RTE_MIN((addr_end - addr), length) : 0;
 525                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 526                                 /*
 527                                  * One Dseg remains in the current WQE.  To
 528                                  * keep the computation positive, it is
 529                                  * removed after the bytes to Dseg conversion.
 530                                  */
 531                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 532
 533                                 if (unlikely(max_wqe < n))
 534                                         break;
 535                                 max_wqe -= n;
 536                                 if (tso && !inl) {
 537                                         inl = rte_cpu_to_be_32(copy_b |
 538                                                                MLX5_INLINE_SEG);
 539                                         rte_memcpy((void *)raw,
 540                                                    (void *)&inl, sizeof(inl));
 541                                         raw += sizeof(inl);
 542                                         pkt_inline_sz += sizeof(inl);
 543                                 }
 544                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 545                                 addr += copy_b;
 546                                 length -= copy_b;
 547                                 pkt_inline_sz += copy_b;
 548                         }
 549                         /*
 550                          * 2 DWORDs consumed by the WQE header + ETH segment +
 551                          * the size of the inline part of the packet.
 552                          */
 553                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 554                         if (length > 0) {
 555                                 if (ds % (MLX5_WQE_SIZE /
 556                                           MLX5_WQE_DWORD_SIZE) == 0) {
 557                                         if (unlikely(--max_wqe == 0))
 558                                                 break;
 559                                         dseg = (volatile rte_v128u32_t *)
 560                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 561                                                            ds / 4);
 562                                 } else {
 563                                         dseg = (volatile rte_v128u32_t *)
 564                                                 ((uintptr_t)wqe +
 565                                                  (ds * MLX5_WQE_DWORD_SIZE));
 566                                 }
 567                                 goto use_dseg;
 568                         } else if (!segs_n) {
 569                                 goto next_pkt;
 570                         } else {
 571                                 raw += copy_b;
 572                                 inline_room -= copy_b;
 573                                 --segs_n;
 574                                 buf = buf->next;
 575                                 assert(buf);
 576                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 577                                 length = DATA_LEN(buf);
 578 #ifdef MLX5_PMD_SOFT_COUNTERS
 579                                 total_length += length;
 580 #endif
 581                                 (*txq->elts)[++elts_head & elts_m] = buf;
 582                                 goto pkt_inline;
 583                         }
 584                 } else {
 585                         /*
 586                          * No inline has been done in the packet, only the
 587                          * Ethernet Header as been stored.
 588                          */
 589                         dseg = (volatile rte_v128u32_t *)
 590                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 591                         ds = 3;
 592 use_dseg:
 593                         /* Add the remaining packet as a simple ds. */
 594                         addr = rte_cpu_to_be_64(addr);
 595                         *dseg = (rte_v128u32_t){
 596                                 rte_cpu_to_be_32(length),
 597                                 mlx5_tx_mb2mr(txq, buf),
 598                                 addr,
 599                                 addr >> 32,
 600                         };
 601                         ++ds;
 602                         if (!segs_n)
 603                                 goto next_pkt;
 604                 }
 605 next_seg:
 606                 assert(buf);
 607                 assert(ds);
 608                 assert(wqe);
 609                 /*
 610                  * Spill on next WQE when the current one does not have
 611                  * enough room left. Size of WQE must a be a multiple
 612                  * of data segment size.
 613                  */
 614                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 615                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 616                         if (unlikely(--max_wqe == 0))
 617                                 break;
 618                         dseg = (volatile rte_v128u32_t *)
 619                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 620                         rte_prefetch0(tx_mlx5_wqe(txq,
 621                                                   txq->wqe_ci + ds / 4 + 1));
 622                 } else {
 623                         ++dseg;
 624                 }
 625                 ++ds;
 626                 buf = buf->next;
 627                 assert(buf);
 628                 length = DATA_LEN(buf);
 629 #ifdef MLX5_PMD_SOFT_COUNTERS
 630                 total_length += length;
 631 #endif
 632                 /* Store segment information. */
 633                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 634                 *dseg = (rte_v128u32_t){
 635                         rte_cpu_to_be_32(length),
 636                         mlx5_tx_mb2mr(txq, buf),
 637                         addr,
 638                         addr >> 32,
 639                 };
 640                 (*txq->elts)[++elts_head & elts_m] = buf;
 641                 if (--segs_n)
 642                         goto next_seg;
 643 next_pkt:
 644                 if (ds > MLX5_DSEG_MAX) {
 645                         txq->stats.oerrors++;
 646                         break;
 647                 }
 648                 ++elts_head;
 649                 ++pkts;
 650                 ++i;
 651                 j += sg;
 652                 /* Initialize known and common part of the WQE structure. */
 653                 if (tso) {
 654                         wqe->ctrl = (rte_v128u32_t){
 655                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 656                                                  MLX5_OPCODE_TSO),
 657                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 658                                 0,
 659                                 0,
 660                         };
 661                         wqe->eseg = (rte_v128u32_t){
 662                                 0,
 663                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 664                                 0,
 665                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 666                         };
 667                 } else {
 668                         wqe->ctrl = (rte_v128u32_t){
 669                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 670                                                  MLX5_OPCODE_SEND),
 671                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 672                                 0,
 673                                 0,
 674                         };
 675                         wqe->eseg = (rte_v128u32_t){
 676                                 0,
 677                                 cs_flags,
 678                                 0,
 679                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 680                         };
 681                 }
 682 next_wqe:
 683                 txq->wqe_ci += (ds + 3) / 4;
 684                 /* Save the last successful WQE for completion request */
 685                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 686 #ifdef MLX5_PMD_SOFT_COUNTERS
 687                 /* Increment sent bytes counter. */
 688                 txq->stats.obytes += total_length;
 689 #endif
 690         } while (i < pkts_n);
 691         /* Take a shortcut if nothing must be sent. */
 692         if (unlikely((i + k) == 0))
 693                 return 0;
 694         txq->elts_head += (i + j);
 695         /* Check whether completion threshold has been reached. */
 696         comp = txq->elts_comp + i + j + k;
 697         if (comp >= MLX5_TX_COMP_THRESH) {
 698                 /* Request completion on last WQE. */
 699                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 700                 /* Save elts_head in unused "immediate" field of WQE. */
 701                 last_wqe->ctrl3 = txq->elts_head;
 702                 txq->elts_comp = 0;
 703         } else {
 704                 txq->elts_comp = comp;
 705         }
 706 #ifdef MLX5_PMD_SOFT_COUNTERS
 707         /* Increment sent packets counter. */
 708         txq->stats.opackets += i;
 709 #endif
 710         /* Ring QP doorbell. */
 711         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 712         return i;
 713 }
 714
 715 /**
 716  * Open a MPW session.
 717  *
 718  * @param txq
 719  *   Pointer to TX queue structure.
 720  * @param mpw
 721  *   Pointer to MPW session structure.
 722  * @param length
 723  *   Packet length.
 724  */
 725 static inline void
 726 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 727 {
 728         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 729         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 730                 (volatile struct mlx5_wqe_data_seg (*)[])
 731                 tx_mlx5_wqe(txq, idx + 1);
 732
 733         mpw->state = MLX5_MPW_STATE_OPENED;
 734         mpw->pkts_n = 0;
 735         mpw->len = length;
 736         mpw->total_len = 0;
 737         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 738         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 739         mpw->wqe->eseg.inline_hdr_sz = 0;
 740         mpw->wqe->eseg.rsvd0 = 0;
 741         mpw->wqe->eseg.rsvd1 = 0;
 742         mpw->wqe->eseg.rsvd2 = 0;
 743         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 744                                              (txq->wqe_ci << 8) |
 745                                              MLX5_OPCODE_TSO);
 746         mpw->wqe->ctrl[2] = 0;
 747         mpw->wqe->ctrl[3] = 0;
 748         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 749                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 750         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 751                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 752         mpw->data.dseg[2] = &(*dseg)[0];
 753         mpw->data.dseg[3] = &(*dseg)[1];
 754         mpw->data.dseg[4] = &(*dseg)[2];
 755 }
 756
 757 /**
 758  * Close a MPW session.
 759  *
 760  * @param txq
 761  *   Pointer to TX queue structure.
 762  * @param mpw
 763  *   Pointer to MPW session structure.
 764  */
 765 static inline void
 766 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 767 {
 768         unsigned int num = mpw->pkts_n;
 769
 770         /*
 771          * Store size in multiple of 16 bytes. Control and Ethernet segments
 772          * count as 2.
 773          */
 774         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 775         mpw->state = MLX5_MPW_STATE_CLOSED;
 776         if (num < 3)
 777                 ++txq->wqe_ci;
 778         else
 779                 txq->wqe_ci += 2;
 780         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 781         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 782 }
 783
 784 /**
 785  * DPDK callback for TX with MPW support.
 786  *
 787  * @param dpdk_txq
 788  *   Generic pointer to TX queue structure.
 789  * @param[in] pkts
 790  *   Packets to transmit.
 791  * @param pkts_n
 792  *   Number of packets in array.
 793  *
 794  * @return
 795  *   Number of packets successfully transmitted (<= pkts_n).
 796  */
 797 uint16_t
 798 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 799 {
 800         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 801         uint16_t elts_head = txq->elts_head;
 802         const uint16_t elts_n = 1 << txq->elts_n;
 803         const uint16_t elts_m = elts_n - 1;
 804         unsigned int i = 0;
 805         unsigned int j = 0;
 806         uint16_t max_elts;
 807         uint16_t max_wqe;
 808         unsigned int comp;
 809         struct mlx5_mpw mpw = {
 810                 .state = MLX5_MPW_STATE_CLOSED,
 811         };
 812
 813         if (unlikely(!pkts_n))
 814                 return 0;
 815         /* Prefetch first packet cacheline. */
 816         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 817         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 818         /* Start processing. */
 819         mlx5_tx_complete(txq);
 820         max_elts = (elts_n - (elts_head - txq->elts_tail));
 821         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 822         if (unlikely(!max_wqe))
 823                 return 0;
 824         do {
 825                 struct rte_mbuf *buf = *(pkts++);
 826                 uint32_t length;
 827                 unsigned int segs_n = buf->nb_segs;
 828                 uint32_t cs_flags;
 829
 830                 /*
 831                  * Make sure there is enough room to store this packet and
 832                  * that one ring entry remains unused.
 833                  */
 834                 assert(segs_n);
 835                 if (max_elts < segs_n)
 836                         break;
 837                 /* Do not bother with large packets MPW cannot handle. */
 838                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 839                         txq->stats.oerrors++;
 840                         break;
 841                 }
 842                 max_elts -= segs_n;
 843                 --pkts_n;
 844                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 845                 /* Retrieve packet information. */
 846                 length = PKT_LEN(buf);
 847                 assert(length);
 848                 /* Start new session if packet differs. */
 849                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 850                     ((mpw.len != length) ||
 851                      (segs_n != 1) ||
 852                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 853                         mlx5_mpw_close(txq, &mpw);
 854                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 855                         /*
 856                          * Multi-Packet WQE consumes at most two WQE.
 857                          * mlx5_mpw_new() expects to be able to use such
 858                          * resources.
 859                          */
 860                         if (unlikely(max_wqe < 2))
 861                                 break;
 862                         max_wqe -= 2;
 863                         mlx5_mpw_new(txq, &mpw, length);
 864                         mpw.wqe->eseg.cs_flags = cs_flags;
 865                 }
 866                 /* Multi-segment packets must be alone in their MPW. */
 867                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 868 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 869                 length = 0;
 870 #endif
 871                 do {
 872                         volatile struct mlx5_wqe_data_seg *dseg;
 873                         uintptr_t addr;
 874
 875                         assert(buf);
 876                         (*txq->elts)[elts_head++ & elts_m] = buf;
 877                         dseg = mpw.data.dseg[mpw.pkts_n];
 878                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 879                         *dseg = (struct mlx5_wqe_data_seg){
 880                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 881                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 882                                 .addr = rte_cpu_to_be_64(addr),
 883                         };
 884 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 885                         length += DATA_LEN(buf);
 886 #endif
 887                         buf = buf->next;
 888                         ++mpw.pkts_n;
 889                         ++j;
 890                 } while (--segs_n);
 891                 assert(length == mpw.len);
 892                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 893                         mlx5_mpw_close(txq, &mpw);
 894 #ifdef MLX5_PMD_SOFT_COUNTERS
 895                 /* Increment sent bytes counter. */
 896                 txq->stats.obytes += length;
 897 #endif
 898                 ++i;
 899         } while (pkts_n);
 900         /* Take a shortcut if nothing must be sent. */
 901         if (unlikely(i == 0))
 902                 return 0;
 903         /* Check whether completion threshold has been reached. */
 904         /* "j" includes both packets and segments. */
 905         comp = txq->elts_comp + j;
 906         if (comp >= MLX5_TX_COMP_THRESH) {
 907                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 908
 909                 /* Request completion on last WQE. */
 910                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 911                 /* Save elts_head in unused "immediate" field of WQE. */
 912                 wqe->ctrl[3] = elts_head;
 913                 txq->elts_comp = 0;
 914         } else {
 915                 txq->elts_comp = comp;
 916         }
 917 #ifdef MLX5_PMD_SOFT_COUNTERS
 918         /* Increment sent packets counter. */
 919         txq->stats.opackets += i;
 920 #endif
 921         /* Ring QP doorbell. */
 922         if (mpw.state == MLX5_MPW_STATE_OPENED)
 923                 mlx5_mpw_close(txq, &mpw);
 924         mlx5_tx_dbrec(txq, mpw.wqe);
 925         txq->elts_head = elts_head;
 926         return i;
 927 }
 928
 929 /**
 930  * Open a MPW inline session.
 931  *
 932  * @param txq
 933  *   Pointer to TX queue structure.
 934  * @param mpw
 935  *   Pointer to MPW session structure.
 936  * @param length
 937  *   Packet length.
 938  */
 939 static inline void
 940 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 941                     uint32_t length)
 942 {
 943         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 944         struct mlx5_wqe_inl_small *inl;
 945
 946         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 947         mpw->pkts_n = 0;
 948         mpw->len = length;
 949         mpw->total_len = 0;
 950         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 951         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 952                                              (txq->wqe_ci << 8) |
 953                                              MLX5_OPCODE_TSO);
 954         mpw->wqe->ctrl[2] = 0;
 955         mpw->wqe->ctrl[3] = 0;
 956         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 957         mpw->wqe->eseg.inline_hdr_sz = 0;
 958         mpw->wqe->eseg.cs_flags = 0;
 959         mpw->wqe->eseg.rsvd0 = 0;
 960         mpw->wqe->eseg.rsvd1 = 0;
 961         mpw->wqe->eseg.rsvd2 = 0;
 962         inl = (struct mlx5_wqe_inl_small *)
 963                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 964         mpw->data.raw = (uint8_t *)&inl->raw;
 965 }
 966
 967 /**
 968  * Close a MPW inline session.
 969  *
 970  * @param txq
 971  *   Pointer to TX queue structure.
 972  * @param mpw
 973  *   Pointer to MPW session structure.
 974  */
 975 static inline void
 976 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 977 {
 978         unsigned int size;
 979         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 980                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 981
 982         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 983         /*
 984          * Store size in multiple of 16 bytes. Control and Ethernet segments
 985          * count as 2.
 986          */
 987         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
 988                                              MLX5_WQE_DS(size));
 989         mpw->state = MLX5_MPW_STATE_CLOSED;
 990         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
 991         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 992 }
 993
 994 /**
 995  * DPDK callback for TX with MPW inline support.
 996  *
 997  * @param dpdk_txq
 998  *   Generic pointer to TX queue structure.
 999  * @param[in] pkts
1000  *   Packets to transmit.
1001  * @param pkts_n
1002  *   Number of packets in array.
1003  *
1004  * @return
1005  *   Number of packets successfully transmitted (<= pkts_n).
1006  */
1007 uint16_t
1008 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1009                          uint16_t pkts_n)
1010 {
1011         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1012         uint16_t elts_head = txq->elts_head;
1013         const uint16_t elts_n = 1 << txq->elts_n;
1014         const uint16_t elts_m = elts_n - 1;
1015         unsigned int i = 0;
1016         unsigned int j = 0;
1017         uint16_t max_elts;
1018         uint16_t max_wqe;
1019         unsigned int comp;
1020         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1021         struct mlx5_mpw mpw = {
1022                 .state = MLX5_MPW_STATE_CLOSED,
1023         };
1024         /*
1025          * Compute the maximum number of WQE which can be consumed by inline
1026          * code.
1027          * - 2 DSEG for:
1028          *   - 1 control segment,
1029          *   - 1 Ethernet segment,
1030          * - N Dseg from the inline request.
1031          */
1032         const unsigned int wqe_inl_n =
1033                 ((2 * MLX5_WQE_DWORD_SIZE +
1034                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1035                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1036
1037         if (unlikely(!pkts_n))
1038                 return 0;
1039         /* Prefetch first packet cacheline. */
1040         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1041         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1042         /* Start processing. */
1043         mlx5_tx_complete(txq);
1044         max_elts = (elts_n - (elts_head - txq->elts_tail));
1045         do {
1046                 struct rte_mbuf *buf = *(pkts++);
1047                 uintptr_t addr;
1048                 uint32_t length;
1049                 unsigned int segs_n = buf->nb_segs;
1050                 uint8_t cs_flags;
1051
1052                 /*
1053                  * Make sure there is enough room to store this packet and
1054                  * that one ring entry remains unused.
1055                  */
1056                 assert(segs_n);
1057                 if (max_elts < segs_n)
1058                         break;
1059                 /* Do not bother with large packets MPW cannot handle. */
1060                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1061                         txq->stats.oerrors++;
1062                         break;
1063                 }
1064                 max_elts -= segs_n;
1065                 --pkts_n;
1066                 /*
1067                  * Compute max_wqe in case less WQE were consumed in previous
1068                  * iteration.
1069                  */
1070                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1071                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1072                 /* Retrieve packet information. */
1073                 length = PKT_LEN(buf);
1074                 /* Start new session if packet differs. */
1075                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1076                         if ((mpw.len != length) ||
1077                             (segs_n != 1) ||
1078                             (mpw.wqe->eseg.cs_flags != cs_flags))
1079                                 mlx5_mpw_close(txq, &mpw);
1080                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1081                         if ((mpw.len != length) ||
1082                             (segs_n != 1) ||
1083                             (length > inline_room) ||
1084                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1085                                 mlx5_mpw_inline_close(txq, &mpw);
1086                                 inline_room =
1087                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1088                         }
1089                 }
1090                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1091                         if ((segs_n != 1) ||
1092                             (length > inline_room)) {
1093                                 /*
1094                                  * Multi-Packet WQE consumes at most two WQE.
1095                                  * mlx5_mpw_new() expects to be able to use
1096                                  * such resources.
1097                                  */
1098                                 if (unlikely(max_wqe < 2))
1099                                         break;
1100                                 max_wqe -= 2;
1101                                 mlx5_mpw_new(txq, &mpw, length);
1102                                 mpw.wqe->eseg.cs_flags = cs_flags;
1103                         } else {
1104                                 if (unlikely(max_wqe < wqe_inl_n))
1105                                         break;
1106                                 max_wqe -= wqe_inl_n;
1107                                 mlx5_mpw_inline_new(txq, &mpw, length);
1108                                 mpw.wqe->eseg.cs_flags = cs_flags;
1109                         }
1110                 }
1111                 /* Multi-segment packets must be alone in their MPW. */
1112                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1113                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1114                         assert(inline_room ==
1115                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1116 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1117                         length = 0;
1118 #endif
1119                         do {
1120                                 volatile struct mlx5_wqe_data_seg *dseg;
1121
1122                                 assert(buf);
1123                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1124                                 dseg = mpw.data.dseg[mpw.pkts_n];
1125                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1126                                 *dseg = (struct mlx5_wqe_data_seg){
1127                                         .byte_count =
1128                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1129                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1130                                         .addr = rte_cpu_to_be_64(addr),
1131                                 };
1132 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1133                                 length += DATA_LEN(buf);
1134 #endif
1135                                 buf = buf->next;
1136                                 ++mpw.pkts_n;
1137                                 ++j;
1138                         } while (--segs_n);
1139                         assert(length == mpw.len);
1140                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1141                                 mlx5_mpw_close(txq, &mpw);
1142                 } else {
1143                         unsigned int max;
1144
1145                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1146                         assert(length <= inline_room);
1147                         assert(length == DATA_LEN(buf));
1148                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1149                         (*txq->elts)[elts_head++ & elts_m] = buf;
1150                         /* Maximum number of bytes before wrapping. */
1151                         max = ((((uintptr_t)(txq->wqes)) +
1152                                 (1 << txq->wqe_n) *
1153                                 MLX5_WQE_SIZE) -
1154                                (uintptr_t)mpw.data.raw);
1155                         if (length > max) {
1156                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1157                                            (void *)addr,
1158                                            max);
1159                                 mpw.data.raw = (volatile void *)txq->wqes;
1160                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1161                                            (void *)(addr + max),
1162                                            length - max);
1163                                 mpw.data.raw += length - max;
1164                         } else {
1165                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1166                                            (void *)addr,
1167                                            length);
1168
1169                                 if (length == max)
1170                                         mpw.data.raw =
1171                                                 (volatile void *)txq->wqes;
1172                                 else
1173                                         mpw.data.raw += length;
1174                         }
1175                         ++mpw.pkts_n;
1176                         mpw.total_len += length;
1177                         ++j;
1178                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1179                                 mlx5_mpw_inline_close(txq, &mpw);
1180                                 inline_room =
1181                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1182                         } else {
1183                                 inline_room -= length;
1184                         }
1185                 }
1186 #ifdef MLX5_PMD_SOFT_COUNTERS
1187                 /* Increment sent bytes counter. */
1188                 txq->stats.obytes += length;
1189 #endif
1190                 ++i;
1191         } while (pkts_n);
1192         /* Take a shortcut if nothing must be sent. */
1193         if (unlikely(i == 0))
1194                 return 0;
1195         /* Check whether completion threshold has been reached. */
1196         /* "j" includes both packets and segments. */
1197         comp = txq->elts_comp + j;
1198         if (comp >= MLX5_TX_COMP_THRESH) {
1199                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1200
1201                 /* Request completion on last WQE. */
1202                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1203                 /* Save elts_head in unused "immediate" field of WQE. */
1204                 wqe->ctrl[3] = elts_head;
1205                 txq->elts_comp = 0;
1206         } else {
1207                 txq->elts_comp = comp;
1208         }
1209 #ifdef MLX5_PMD_SOFT_COUNTERS
1210         /* Increment sent packets counter. */
1211         txq->stats.opackets += i;
1212 #endif
1213         /* Ring QP doorbell. */
1214         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1215                 mlx5_mpw_inline_close(txq, &mpw);
1216         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1217                 mlx5_mpw_close(txq, &mpw);
1218         mlx5_tx_dbrec(txq, mpw.wqe);
1219         txq->elts_head = elts_head;
1220         return i;
1221 }
1222
1223 /**
1224  * Open an Enhanced MPW session.
1225  *
1226  * @param txq
1227  *   Pointer to TX queue structure.
1228  * @param mpw
1229  *   Pointer to MPW session structure.
1230  * @param length
1231  *   Packet length.
1232  */
1233 static inline void
1234 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1235 {
1236         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1237
1238         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1239         mpw->pkts_n = 0;
1240         mpw->total_len = sizeof(struct mlx5_wqe);
1241         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1242         mpw->wqe->ctrl[0] =
1243                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1244                                  (txq->wqe_ci << 8) |
1245                                  MLX5_OPCODE_ENHANCED_MPSW);
1246         mpw->wqe->ctrl[2] = 0;
1247         mpw->wqe->ctrl[3] = 0;
1248         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1249         if (unlikely(padding)) {
1250                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1251
1252                 /* Pad the first 2 DWORDs with zero-length inline header. */
1253                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1254                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1255                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1256                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1257                 /* Start from the next WQEBB. */
1258                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1259         } else {
1260                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1261         }
1262 }
1263
1264 /**
1265  * Close an Enhanced MPW session.
1266  *
1267  * @param txq
1268  *   Pointer to TX queue structure.
1269  * @param mpw
1270  *   Pointer to MPW session structure.
1271  *
1272  * @return
1273  *   Number of consumed WQEs.
1274  */
1275 static inline uint16_t
1276 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1277 {
1278         uint16_t ret;
1279
1280         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1281          * count as 2.
1282          */
1283         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1284                                              MLX5_WQE_DS(mpw->total_len));
1285         mpw->state = MLX5_MPW_STATE_CLOSED;
1286         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1287         txq->wqe_ci += ret;
1288         return ret;
1289 }
1290
1291 /**
1292  * DPDK callback for TX with Enhanced MPW support.
1293  *
1294  * @param dpdk_txq
1295  *   Generic pointer to TX queue structure.
1296  * @param[in] pkts
1297  *   Packets to transmit.
1298  * @param pkts_n
1299  *   Number of packets in array.
1300  *
1301  * @return
1302  *   Number of packets successfully transmitted (<= pkts_n).
1303  */
1304 uint16_t
1305 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1306 {
1307         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1308         uint16_t elts_head = txq->elts_head;
1309         const uint16_t elts_n = 1 << txq->elts_n;
1310         const uint16_t elts_m = elts_n - 1;
1311         unsigned int i = 0;
1312         unsigned int j = 0;
1313         uint16_t max_elts;
1314         uint16_t max_wqe;
1315         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1316         unsigned int mpw_room = 0;
1317         unsigned int inl_pad = 0;
1318         uint32_t inl_hdr;
1319         struct mlx5_mpw mpw = {
1320                 .state = MLX5_MPW_STATE_CLOSED,
1321         };
1322
1323         if (unlikely(!pkts_n))
1324                 return 0;
1325         /* Start processing. */
1326         mlx5_tx_complete(txq);
1327         max_elts = (elts_n - (elts_head - txq->elts_tail));
1328         /* A CQE slot must always be available. */
1329         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1330         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1331         if (unlikely(!max_wqe))
1332                 return 0;
1333         do {
1334                 struct rte_mbuf *buf = *(pkts++);
1335                 uintptr_t addr;
1336                 unsigned int n;
1337                 unsigned int do_inline = 0; /* Whether inline is possible. */
1338                 uint32_t length;
1339                 unsigned int segs_n = buf->nb_segs;
1340                 uint8_t cs_flags;
1341
1342                 /*
1343                  * Make sure there is enough room to store this packet and
1344                  * that one ring entry remains unused.
1345                  */
1346                 assert(segs_n);
1347                 if (max_elts - j < segs_n)
1348                         break;
1349                 /* Do not bother with large packets MPW cannot handle. */
1350                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1351                         txq->stats.oerrors++;
1352                         break;
1353                 }
1354                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1355                 /* Retrieve packet information. */
1356                 length = PKT_LEN(buf);
1357                 /* Start new session if:
1358                  * - multi-segment packet
1359                  * - no space left even for a dseg
1360                  * - next packet can be inlined with a new WQE
1361                  * - cs_flag differs
1362                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1363                  * segmented packet.
1364                  */
1365                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1366                         if ((segs_n != 1) ||
1367                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1368                               mpw_room) ||
1369                             (length <= txq->inline_max_packet_sz &&
1370                              inl_pad + sizeof(inl_hdr) + length >
1371                               mpw_room) ||
1372                             (mpw.wqe->eseg.cs_flags != cs_flags))
1373                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1374                 }
1375                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1376                         if (unlikely(segs_n != 1)) {
1377                                 /* Fall back to legacy MPW.
1378                                  * A MPW session consumes 2 WQEs at most to
1379                                  * include MLX5_MPW_DSEG_MAX pointers.
1380                                  */
1381                                 if (unlikely(max_wqe < 2))
1382                                         break;
1383                                 mlx5_mpw_new(txq, &mpw, length);
1384                         } else {
1385                                 /* In Enhanced MPW, inline as much as the budget
1386                                  * is allowed. The remaining space is to be
1387                                  * filled with dsegs. If the title WQEBB isn't
1388                                  * padded, it will have 2 dsegs there.
1389                                  */
1390                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1391                                             (max_inline ? max_inline :
1392                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1393                                             MLX5_WQE_SIZE);
1394                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1395                                               mpw_room))
1396                                         break;
1397                                 /* Don't pad the title WQEBB to not waste WQ. */
1398                                 mlx5_empw_new(txq, &mpw, 0);
1399                                 mpw_room -= mpw.total_len;
1400                                 inl_pad = 0;
1401                                 do_inline =
1402                                         length <= txq->inline_max_packet_sz &&
1403                                         sizeof(inl_hdr) + length <= mpw_room &&
1404                                         !txq->mpw_hdr_dseg;
1405                         }
1406                         mpw.wqe->eseg.cs_flags = cs_flags;
1407                 } else {
1408                         /* Evaluate whether the next packet can be inlined.
1409                          * Inlininig is possible when:
1410                          * - length is less than configured value
1411                          * - length fits for remaining space
1412                          * - not required to fill the title WQEBB with dsegs
1413                          */
1414                         do_inline =
1415                                 length <= txq->inline_max_packet_sz &&
1416                                 inl_pad + sizeof(inl_hdr) + length <=
1417                                  mpw_room &&
1418                                 (!txq->mpw_hdr_dseg ||
1419                                  mpw.total_len >= MLX5_WQE_SIZE);
1420                 }
1421                 /* Multi-segment packets must be alone in their MPW. */
1422                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1423                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1424 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1425                         length = 0;
1426 #endif
1427                         do {
1428                                 volatile struct mlx5_wqe_data_seg *dseg;
1429
1430                                 assert(buf);
1431                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1432                                 dseg = mpw.data.dseg[mpw.pkts_n];
1433                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1434                                 *dseg = (struct mlx5_wqe_data_seg){
1435                                         .byte_count = rte_cpu_to_be_32(
1436                                                                 DATA_LEN(buf)),
1437                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1438                                         .addr = rte_cpu_to_be_64(addr),
1439                                 };
1440 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1441                                 length += DATA_LEN(buf);
1442 #endif
1443                                 buf = buf->next;
1444                                 ++j;
1445                                 ++mpw.pkts_n;
1446                         } while (--segs_n);
1447                         /* A multi-segmented packet takes one MPW session.
1448                          * TODO: Pack more multi-segmented packets if possible.
1449                          */
1450                         mlx5_mpw_close(txq, &mpw);
1451                         if (mpw.pkts_n < 3)
1452                                 max_wqe--;
1453                         else
1454                                 max_wqe -= 2;
1455                 } else if (do_inline) {
1456                         /* Inline packet into WQE. */
1457                         unsigned int max;
1458
1459                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1460                         assert(length == DATA_LEN(buf));
1461                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1462                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1463                         mpw.data.raw = (volatile void *)
1464                                 ((uintptr_t)mpw.data.raw + inl_pad);
1465                         max = tx_mlx5_wq_tailroom(txq,
1466                                         (void *)(uintptr_t)mpw.data.raw);
1467                         /* Copy inline header. */
1468                         mpw.data.raw = (volatile void *)
1469                                 mlx5_copy_to_wq(
1470                                           (void *)(uintptr_t)mpw.data.raw,
1471                                           &inl_hdr,
1472                                           sizeof(inl_hdr),
1473                                           (void *)(uintptr_t)txq->wqes,
1474                                           max);
1475                         max = tx_mlx5_wq_tailroom(txq,
1476                                         (void *)(uintptr_t)mpw.data.raw);
1477                         /* Copy packet data. */
1478                         mpw.data.raw = (volatile void *)
1479                                 mlx5_copy_to_wq(
1480                                           (void *)(uintptr_t)mpw.data.raw,
1481                                           (void *)addr,
1482                                           length,
1483                                           (void *)(uintptr_t)txq->wqes,
1484                                           max);
1485                         ++mpw.pkts_n;
1486                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1487                         /* No need to get completion as the entire packet is
1488                          * copied to WQ. Free the buf right away.
1489                          */
1490                         rte_pktmbuf_free_seg(buf);
1491                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1492                         /* Add pad in the next packet if any. */
1493                         inl_pad = (((uintptr_t)mpw.data.raw +
1494                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1495                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1496                                   (uintptr_t)mpw.data.raw;
1497                 } else {
1498                         /* No inline. Load a dseg of packet pointer. */
1499                         volatile rte_v128u32_t *dseg;
1500
1501                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1502                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1503                         assert(length == DATA_LEN(buf));
1504                         if (!tx_mlx5_wq_tailroom(txq,
1505                                         (void *)((uintptr_t)mpw.data.raw
1506                                                 + inl_pad)))
1507                                 dseg = (volatile void *)txq->wqes;
1508                         else
1509                                 dseg = (volatile void *)
1510                                         ((uintptr_t)mpw.data.raw +
1511                                          inl_pad);
1512                         (*txq->elts)[elts_head++ & elts_m] = buf;
1513                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1514                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1515                                 rte_prefetch2((void *)(addr +
1516                                                 n * RTE_CACHE_LINE_SIZE));
1517                         addr = rte_cpu_to_be_64(addr);
1518                         *dseg = (rte_v128u32_t) {
1519                                 rte_cpu_to_be_32(length),
1520                                 mlx5_tx_mb2mr(txq, buf),
1521                                 addr,
1522                                 addr >> 32,
1523                         };
1524                         mpw.data.raw = (volatile void *)(dseg + 1);
1525                         mpw.total_len += (inl_pad + sizeof(*dseg));
1526                         ++j;
1527                         ++mpw.pkts_n;
1528                         mpw_room -= (inl_pad + sizeof(*dseg));
1529                         inl_pad = 0;
1530                 }
1531 #ifdef MLX5_PMD_SOFT_COUNTERS
1532                 /* Increment sent bytes counter. */
1533                 txq->stats.obytes += length;
1534 #endif
1535                 ++i;
1536         } while (i < pkts_n);
1537         /* Take a shortcut if nothing must be sent. */
1538         if (unlikely(i == 0))
1539                 return 0;
1540         /* Check whether completion threshold has been reached. */
1541         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1542                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1543                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1544                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1545
1546                 /* Request completion on last WQE. */
1547                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1548                 /* Save elts_head in unused "immediate" field of WQE. */
1549                 wqe->ctrl[3] = elts_head;
1550                 txq->elts_comp = 0;
1551                 txq->mpw_comp = txq->wqe_ci;
1552                 txq->cq_pi++;
1553         } else {
1554                 txq->elts_comp += j;
1555         }
1556 #ifdef MLX5_PMD_SOFT_COUNTERS
1557         /* Increment sent packets counter. */
1558         txq->stats.opackets += i;
1559 #endif
1560         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1561                 mlx5_empw_close(txq, &mpw);
1562         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1563                 mlx5_mpw_close(txq, &mpw);
1564         /* Ring QP doorbell. */
1565         mlx5_tx_dbrec(txq, mpw.wqe);
1566         txq->elts_head = elts_head;
1567         return i;
1568 }
1569
1570 /**
1571  * Translate RX completion flags to packet type.
1572  *
1573  * @param[in] cqe
1574  *   Pointer to CQE.
1575  *
1576  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1577  *
1578  * @return
1579  *   Packet type for struct rte_mbuf.
1580  */
1581 static inline uint32_t
1582 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1583 {
1584         uint8_t idx;
1585         uint8_t pinfo = cqe->pkt_info;
1586         uint16_t ptype = cqe->hdr_type_etc;
1587
1588         /*
1589          * The index to the array should have:
1590          * bit[1:0] = l3_hdr_type
1591          * bit[4:2] = l4_hdr_type
1592          * bit[5] = ip_frag
1593          * bit[6] = tunneled
1594          * bit[7] = outer_l3_type
1595          */
1596         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1597         return mlx5_ptype_table[idx];
1598 }
1599
1600 /**
1601  * Get size of the next packet for a given CQE. For compressed CQEs, the
1602  * consumer index is updated only once all packets of the current one have
1603  * been processed.
1604  *
1605  * @param rxq
1606  *   Pointer to RX queue.
1607  * @param cqe
1608  *   CQE to process.
1609  * @param[out] rss_hash
1610  *   Packet RSS Hash result.
1611  *
1612  * @return
1613  *   Packet size in bytes (0 if there is none), -1 in case of completion
1614  *   with error.
1615  */
1616 static inline int
1617 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1618                  uint16_t cqe_cnt, uint32_t *rss_hash)
1619 {
1620         struct rxq_zip *zip = &rxq->zip;
1621         uint16_t cqe_n = cqe_cnt + 1;
1622         int len = 0;
1623         uint16_t idx, end;
1624
1625         /* Process compressed data in the CQE and mini arrays. */
1626         if (zip->ai) {
1627                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1628                         (volatile struct mlx5_mini_cqe8 (*)[8])
1629                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1630
1631                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1632                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1633                 if ((++zip->ai & 7) == 0) {
1634                         /* Invalidate consumed CQEs */
1635                         idx = zip->ca;
1636                         end = zip->na;
1637                         while (idx != end) {
1638                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1639                                         MLX5_CQE_INVALIDATE;
1640                                 ++idx;
1641                         }
1642                         /*
1643                          * Increment consumer index to skip the number of
1644                          * CQEs consumed. Hardware leaves holes in the CQ
1645                          * ring for software use.
1646                          */
1647                         zip->ca = zip->na;
1648                         zip->na += 8;
1649                 }
1650                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1651                         /* Invalidate the rest */
1652                         idx = zip->ca;
1653                         end = zip->cq_ci;
1654
1655                         while (idx != end) {
1656                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1657                                         MLX5_CQE_INVALIDATE;
1658                                 ++idx;
1659                         }
1660                         rxq->cq_ci = zip->cq_ci;
1661                         zip->ai = 0;
1662                 }
1663         /* No compressed data, get next CQE and verify if it is compressed. */
1664         } else {
1665                 int ret;
1666                 int8_t op_own;
1667
1668                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1669                 if (unlikely(ret == 1))
1670                         return 0;
1671                 ++rxq->cq_ci;
1672                 op_own = cqe->op_own;
1673                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1674                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1675                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1676                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1677                                                           cqe_cnt].pkt_info);
1678
1679                         /* Fix endianness. */
1680                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1681                         /*
1682                          * Current mini array position is the one returned by
1683                          * check_cqe64().
1684                          *
1685                          * If completion comprises several mini arrays, as a
1686                          * special case the second one is located 7 CQEs after
1687                          * the initial CQE instead of 8 for subsequent ones.
1688                          */
1689                         zip->ca = rxq->cq_ci;
1690                         zip->na = zip->ca + 7;
1691                         /* Compute the next non compressed CQE. */
1692                         --rxq->cq_ci;
1693                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1694                         /* Get packet size to return. */
1695                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1696                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1697                         zip->ai = 1;
1698                         /* Prefetch all the entries to be invalidated */
1699                         idx = zip->ca;
1700                         end = zip->cq_ci;
1701                         while (idx != end) {
1702                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1703                                 ++idx;
1704                         }
1705                 } else {
1706                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1707                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1708                 }
1709                 /* Error while receiving packet. */
1710                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1711                         return -1;
1712         }
1713         return len;
1714 }
1715
1716 /**
1717  * Translate RX completion flags to offload flags.
1718  *
1719  * @param[in] rxq
1720  *   Pointer to RX queue structure.
1721  * @param[in] cqe
1722  *   Pointer to CQE.
1723  *
1724  * @return
1725  *   Offload flags (ol_flags) for struct rte_mbuf.
1726  */
1727 static inline uint32_t
1728 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1729 {
1730         uint32_t ol_flags = 0;
1731         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1732
1733         ol_flags =
1734                 TRANSPOSE(flags,
1735                           MLX5_CQE_RX_L3_HDR_VALID,
1736                           PKT_RX_IP_CKSUM_GOOD) |
1737                 TRANSPOSE(flags,
1738                           MLX5_CQE_RX_L4_HDR_VALID,
1739                           PKT_RX_L4_CKSUM_GOOD);
1740         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1741                 ol_flags |=
1742                         TRANSPOSE(flags,
1743                                   MLX5_CQE_RX_L3_HDR_VALID,
1744                                   PKT_RX_IP_CKSUM_GOOD) |
1745                         TRANSPOSE(flags,
1746                                   MLX5_CQE_RX_L4_HDR_VALID,
1747                                   PKT_RX_L4_CKSUM_GOOD);
1748         return ol_flags;
1749 }
1750
1751 /**
1752  * DPDK callback for RX.
1753  *
1754  * @param dpdk_rxq
1755  *   Generic pointer to RX queue structure.
1756  * @param[out] pkts
1757  *   Array to store received packets.
1758  * @param pkts_n
1759  *   Maximum number of packets in array.
1760  *
1761  * @return
1762  *   Number of packets successfully received (<= pkts_n).
1763  */
1764 uint16_t
1765 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1766 {
1767         struct mlx5_rxq_data *rxq = dpdk_rxq;
1768         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1769         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1770         const unsigned int sges_n = rxq->sges_n;
1771         struct rte_mbuf *pkt = NULL;
1772         struct rte_mbuf *seg = NULL;
1773         volatile struct mlx5_cqe *cqe =
1774                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1775         unsigned int i = 0;
1776         unsigned int rq_ci = rxq->rq_ci << sges_n;
1777         int len = 0; /* keep its value across iterations. */
1778
1779         while (pkts_n) {
1780                 unsigned int idx = rq_ci & wqe_cnt;
1781                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1782                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1783                 uint32_t rss_hash_res = 0;
1784
1785                 if (pkt)
1786                         NEXT(seg) = rep;
1787                 seg = rep;
1788                 rte_prefetch0(seg);
1789                 rte_prefetch0(cqe);
1790                 rte_prefetch0(wqe);
1791                 rep = rte_mbuf_raw_alloc(rxq->mp);
1792                 if (unlikely(rep == NULL)) {
1793                         ++rxq->stats.rx_nombuf;
1794                         if (!pkt) {
1795                                 /*
1796                                  * no buffers before we even started,
1797                                  * bail out silently.
1798                                  */
1799                                 break;
1800                         }
1801                         while (pkt != seg) {
1802                                 assert(pkt != (*rxq->elts)[idx]);
1803                                 rep = NEXT(pkt);
1804                                 NEXT(pkt) = NULL;
1805                                 NB_SEGS(pkt) = 1;
1806                                 rte_mbuf_raw_free(pkt);
1807                                 pkt = rep;
1808                         }
1809                         break;
1810                 }
1811                 if (!pkt) {
1812                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1813                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1814                                                &rss_hash_res);
1815                         if (!len) {
1816                                 rte_mbuf_raw_free(rep);
1817                                 break;
1818                         }
1819                         if (unlikely(len == -1)) {
1820                                 /* RX error, packet is likely too large. */
1821                                 rte_mbuf_raw_free(rep);
1822                                 ++rxq->stats.idropped;
1823                                 goto skip;
1824                         }
1825                         pkt = seg;
1826                         assert(len >= (rxq->crc_present << 2));
1827                         /* Update packet information. */
1828                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1829                         pkt->ol_flags = 0;
1830                         if (rss_hash_res && rxq->rss_hash) {
1831                                 pkt->hash.rss = rss_hash_res;
1832                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1833                         }
1834                         if (rxq->mark &&
1835                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1836                                 pkt->ol_flags |= PKT_RX_FDIR;
1837                                 if (cqe->sop_drop_qpn !=
1838                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1839                                         uint32_t mark = cqe->sop_drop_qpn;
1840
1841                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1842                                         pkt->hash.fdir.hi =
1843                                                 mlx5_flow_mark_get(mark);
1844                                 }
1845                         }
1846                         if (rxq->csum | rxq->csum_l2tun)
1847                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1848                         if (rxq->vlan_strip &&
1849                             (cqe->hdr_type_etc &
1850                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1851                                 pkt->ol_flags |= PKT_RX_VLAN |
1852                                         PKT_RX_VLAN_STRIPPED;
1853                                 pkt->vlan_tci =
1854                                         rte_be_to_cpu_16(cqe->vlan_info);
1855                         }
1856                         if (rxq->hw_timestamp) {
1857                                 pkt->timestamp =
1858                                         rte_be_to_cpu_64(cqe->timestamp);
1859                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1860                         }
1861                         if (rxq->crc_present)
1862                                 len -= ETHER_CRC_LEN;
1863                         PKT_LEN(pkt) = len;
1864                 }
1865                 DATA_LEN(rep) = DATA_LEN(seg);
1866                 PKT_LEN(rep) = PKT_LEN(seg);
1867                 SET_DATA_OFF(rep, DATA_OFF(seg));
1868                 PORT(rep) = PORT(seg);
1869                 (*rxq->elts)[idx] = rep;
1870                 /*
1871                  * Fill NIC descriptor with the new buffer.  The lkey and size
1872                  * of the buffers are already known, only the buffer address
1873                  * changes.
1874                  */
1875                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1876                 if (len > DATA_LEN(seg)) {
1877                         len -= DATA_LEN(seg);
1878                         ++NB_SEGS(pkt);
1879                         ++rq_ci;
1880                         continue;
1881                 }
1882                 DATA_LEN(seg) = len;
1883 #ifdef MLX5_PMD_SOFT_COUNTERS
1884                 /* Increment bytes counter. */
1885                 rxq->stats.ibytes += PKT_LEN(pkt);
1886 #endif
1887                 /* Return packet. */
1888                 *(pkts++) = pkt;
1889                 pkt = NULL;
1890                 --pkts_n;
1891                 ++i;
1892 skip:
1893                 /* Align consumer index to the next stride. */
1894                 rq_ci >>= sges_n;
1895                 ++rq_ci;
1896                 rq_ci <<= sges_n;
1897         }
1898         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1899                 return 0;
1900         /* Update the consumer index. */
1901         rxq->rq_ci = rq_ci >> sges_n;
1902         rte_io_wmb();
1903         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1904         rte_io_wmb();
1905         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1906 #ifdef MLX5_PMD_SOFT_COUNTERS
1907         /* Increment packets counter. */
1908         rxq->stats.ipackets += i;
1909 #endif
1910         return i;
1911 }
1912
1913 /**
1914  * Dummy DPDK callback for TX.
1915  *
1916  * This function is used to temporarily replace the real callback during
1917  * unsafe control operations on the queue, or in case of error.
1918  *
1919  * @param dpdk_txq
1920  *   Generic pointer to TX queue structure.
1921  * @param[in] pkts
1922  *   Packets to transmit.
1923  * @param pkts_n
1924  *   Number of packets in array.
1925  *
1926  * @return
1927  *   Number of packets successfully transmitted (<= pkts_n).
1928  */
1929 uint16_t
1930 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1931 {
1932         (void)dpdk_txq;
1933         (void)pkts;
1934         (void)pkts_n;
1935         return 0;
1936 }
1937
1938 /**
1939  * Dummy DPDK callback for RX.
1940  *
1941  * This function is used to temporarily replace the real callback during
1942  * unsafe control operations on the queue, or in case of error.
1943  *
1944  * @param dpdk_rxq
1945  *   Generic pointer to RX queue structure.
1946  * @param[out] pkts
1947  *   Array to store received packets.
1948  * @param pkts_n
1949  *   Maximum number of packets in array.
1950  *
1951  * @return
1952  *   Number of packets successfully received (<= pkts_n).
1953  */
1954 uint16_t
1955 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1956 {
1957         (void)dpdk_rxq;
1958         (void)pkts;
1959         (void)pkts_n;
1960         return 0;
1961 }
1962
1963 /*
1964  * Vectorized Rx/Tx routines are not compiled in when required vector
1965  * instructions are not supported on a target architecture. The following null
1966  * stubs are needed for linkage when those are not included outside of this file
1967  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1968  */
1969
1970 uint16_t __attribute__((weak))
1971 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1972 {
1973         (void)dpdk_txq;
1974         (void)pkts;
1975         (void)pkts_n;
1976         return 0;
1977 }
1978
1979 uint16_t __attribute__((weak))
1980 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1981 {
1982         (void)dpdk_txq;
1983         (void)pkts;
1984         (void)pkts_n;
1985         return 0;
1986 }
1987
1988 uint16_t __attribute__((weak))
1989 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1990 {
1991         (void)dpdk_rxq;
1992         (void)pkts;
1993         (void)pkts_n;
1994         return 0;
1995 }
1996
1997 int __attribute__((weak))
1998 priv_check_raw_vec_tx_support(struct priv *priv)
1999 {
2000         (void)priv;
2001         return -ENOTSUP;
2002 }
2003
2004 int __attribute__((weak))
2005 priv_check_vec_tx_support(struct priv *priv)
2006 {
2007         (void)priv;
2008         return -ENOTSUP;
2009 }
2010
2011 int __attribute__((weak))
2012 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2013 {
2014         (void)rxq;
2015         return -ENOTSUP;
2016 }
2017
2018 int __attribute__((weak))
2019 priv_check_vec_rx_support(struct priv *priv)
2020 {
2021         (void)priv;
2022         return -ENOTSUP;
2023 }