drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, uint32_t *rss_hash);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  45
  46 static __rte_always_inline void
  47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  48                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  49
  50 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  51         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  52 };
  53
  54 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  55 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  56
  57 /**
  58  * Build a table to translate Rx completion flags to packet type.
  59  *
  60  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  61  */
  62 void
  63 mlx5_set_ptype_table(void)
  64 {
  65         unsigned int i;
  66         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  67
  68         /* Last entry must not be overwritten, reserved for errored packet. */
  69         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  70                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  71         /*
  72          * The index to the array should have:
  73          * bit[1:0] = l3_hdr_type
  74          * bit[4:2] = l4_hdr_type
  75          * bit[5] = ip_frag
  76          * bit[6] = tunneled
  77          * bit[7] = outer_l3_type
  78          */
  79         /* L2 */
  80         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  81         /* L3 */
  82         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  83                      RTE_PTYPE_L4_NONFRAG;
  84         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  85                      RTE_PTYPE_L4_NONFRAG;
  86         /* Fragmented */
  87         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_FRAG;
  89         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  90                      RTE_PTYPE_L4_FRAG;
  91         /* TCP */
  92         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_TCP;
  94         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  95                      RTE_PTYPE_L4_TCP;
  96         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  97                      RTE_PTYPE_L4_TCP;
  98         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  99                      RTE_PTYPE_L4_TCP;
 100         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP;
 102         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP;
 104         /* UDP */
 105         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_UDP;
 107         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_UDP;
 109         /* Repeat with outer_l3_type being set. Just in case. */
 110         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_NONFRAG;
 112         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 113                      RTE_PTYPE_L4_NONFRAG;
 114         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_FRAG;
 116         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_FRAG;
 118         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_TCP;
 120         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_TCP;
 122         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_TCP;
 124         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_TCP;
 126         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_TCP;
 128         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_TCP;
 130         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_UDP;
 132         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_UDP;
 134         /* Tunneled - L3 */
 135         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 136         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 138                      RTE_PTYPE_INNER_L4_NONFRAG;
 139         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 143         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         /* Tunneled - Fragmented */
 150         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG;
 153         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         /* Tunneled - TCP */
 163         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L4_TCP;
 166         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L4_TCP;
 196         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 197                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L4_TCP;
 199         /* Tunneled - UDP */
 200         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_UDP;
 203         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_UDP;
 209         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_UDP;
 212 }
 213
 214 /**
 215  * Build a table to translate packet to checksum type of Verbs.
 216  */
 217 void
 218 mlx5_set_cksum_table(void)
 219 {
 220         unsigned int i;
 221         uint8_t v;
 222
 223         /*
 224          * The index should have:
 225          * bit[0] = PKT_TX_TCP_SEG
 226          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 227          * bit[4] = PKT_TX_IP_CKSUM
 228          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 229          * bit[9] = tunnel
 230          */
 231         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 232                 v = 0;
 233                 if (i & (1 << 9)) {
 234                         /* Tunneled packet. */
 235                         if (i & (1 << 8)) /* Outer IP. */
 236                                 v |= MLX5_ETH_WQE_L3_CSUM;
 237                         if (i & (1 << 4)) /* Inner IP. */
 238                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 239                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 240                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 241                 } else {
 242                         /* No tunnel. */
 243                         if (i & (1 << 4)) /* IP. */
 244                                 v |= MLX5_ETH_WQE_L3_CSUM;
 245                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 246                                 v |= MLX5_ETH_WQE_L4_CSUM;
 247                 }
 248                 mlx5_cksum_table[i] = v;
 249         }
 250 }
 251
 252 /**
 253  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 254  */
 255 void
 256 mlx5_set_swp_types_table(void)
 257 {
 258         unsigned int i;
 259         uint8_t v;
 260
 261         /*
 262          * The index should have:
 263          * bit[0:1] = PKT_TX_L4_MASK
 264          * bit[4] = PKT_TX_IPV6
 265          * bit[8] = PKT_TX_OUTER_IPV6
 266          * bit[9] = PKT_TX_OUTER_UDP
 267          */
 268         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 269                 v = 0;
 270                 if (i & (1 << 8))
 271                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 272                 if (i & (1 << 9))
 273                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 274                 if (i & (1 << 4))
 275                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 276                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 277                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 278                 mlx5_swp_types_table[i] = v;
 279         }
 280 }
 281
 282 /**
 283  * Return the size of tailroom of WQ.
 284  *
 285  * @param txq
 286  *   Pointer to TX queue structure.
 287  * @param addr
 288  *   Pointer to tail of WQ.
 289  *
 290  * @return
 291  *   Size of tailroom.
 292  */
 293 static inline size_t
 294 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 295 {
 296         size_t tailroom;
 297         tailroom = (uintptr_t)(txq->wqes) +
 298                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 299                    (uintptr_t)addr;
 300         return tailroom;
 301 }
 302
 303 /**
 304  * Copy data to tailroom of circular queue.
 305  *
 306  * @param dst
 307  *   Pointer to destination.
 308  * @param src
 309  *   Pointer to source.
 310  * @param n
 311  *   Number of bytes to copy.
 312  * @param base
 313  *   Pointer to head of queue.
 314  * @param tailroom
 315  *   Size of tailroom from dst.
 316  *
 317  * @return
 318  *   Pointer after copied data.
 319  */
 320 static inline void *
 321 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 322                 void *base, size_t tailroom)
 323 {
 324         void *ret;
 325
 326         if (n > tailroom) {
 327                 rte_memcpy(dst, src, tailroom);
 328                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 329                            n - tailroom);
 330                 ret = (uint8_t *)base + n - tailroom;
 331         } else {
 332                 rte_memcpy(dst, src, n);
 333                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 334         }
 335         return ret;
 336 }
 337
 338 /**
 339  * Inline TSO headers into WQE.
 340  *
 341  * @return
 342  *   0 on success, negative errno value on failure.
 343  */
 344 static int
 345 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 346            uint32_t *length,
 347            uintptr_t *addr,
 348            uint16_t *pkt_inline_sz,
 349            uint8_t **raw,
 350            uint16_t *max_wqe,
 351            uint16_t *tso_segsz,
 352            uint16_t *tso_header_sz)
 353 {
 354         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 355                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 356         unsigned int copy_b;
 357         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 358         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 359                                  PKT_TX_TUNNEL_MASK);
 360         uint16_t n_wqe;
 361
 362         *tso_segsz = buf->tso_segsz;
 363         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 364         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 365                 txq->stats.oerrors++;
 366                 return -EINVAL;
 367         }
 368         if (tunneled)
 369                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 370         /* First seg must contain all TSO headers. */
 371         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 372                      *tso_header_sz > DATA_LEN(buf)) {
 373                 txq->stats.oerrors++;
 374                 return -EINVAL;
 375         }
 376         copy_b = *tso_header_sz - *pkt_inline_sz;
 377         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 378                 return -EAGAIN;
 379         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 380         if (unlikely(*max_wqe < n_wqe))
 381                 return -EINVAL;
 382         *max_wqe -= n_wqe;
 383         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 384         *length -= copy_b;
 385         *addr += copy_b;
 386         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 387         *pkt_inline_sz += copy_b;
 388         *raw += copy_b;
 389         return 0;
 390 }
 391
 392 /**
 393  * DPDK callback to check the status of a tx descriptor.
 394  *
 395  * @param tx_queue
 396  *   The tx queue.
 397  * @param[in] offset
 398  *   The index of the descriptor in the ring.
 399  *
 400  * @return
 401  *   The status of the tx descriptor.
 402  */
 403 int
 404 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 405 {
 406         struct mlx5_txq_data *txq = tx_queue;
 407         uint16_t used;
 408
 409         mlx5_tx_complete(txq);
 410         used = txq->elts_head - txq->elts_tail;
 411         if (offset < used)
 412                 return RTE_ETH_TX_DESC_FULL;
 413         return RTE_ETH_TX_DESC_DONE;
 414 }
 415
 416 /**
 417  * DPDK callback to check the status of a rx descriptor.
 418  *
 419  * @param rx_queue
 420  *   The rx queue.
 421  * @param[in] offset
 422  *   The index of the descriptor in the ring.
 423  *
 424  * @return
 425  *   The status of the tx descriptor.
 426  */
 427 int
 428 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 429 {
 430         struct mlx5_rxq_data *rxq = rx_queue;
 431         struct rxq_zip *zip = &rxq->zip;
 432         volatile struct mlx5_cqe *cqe;
 433         const unsigned int cqe_n = (1 << rxq->cqe_n);
 434         const unsigned int cqe_cnt = cqe_n - 1;
 435         unsigned int cq_ci;
 436         unsigned int used;
 437
 438         /* if we are processing a compressed cqe */
 439         if (zip->ai) {
 440                 used = zip->cqe_cnt - zip->ca;
 441                 cq_ci = zip->cq_ci;
 442         } else {
 443                 used = 0;
 444                 cq_ci = rxq->cq_ci;
 445         }
 446         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 447         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 448                 int8_t op_own;
 449                 unsigned int n;
 450
 451                 op_own = cqe->op_own;
 452                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 453                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 454                 else
 455                         n = 1;
 456                 cq_ci += n;
 457                 used += n;
 458                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 459         }
 460         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 461         if (offset < used)
 462                 return RTE_ETH_RX_DESC_DONE;
 463         return RTE_ETH_RX_DESC_AVAIL;
 464 }
 465
 466 /**
 467  * DPDK callback for TX.
 468  *
 469  * @param dpdk_txq
 470  *   Generic pointer to TX queue structure.
 471  * @param[in] pkts
 472  *   Packets to transmit.
 473  * @param pkts_n
 474  *   Number of packets in array.
 475  *
 476  * @return
 477  *   Number of packets successfully transmitted (<= pkts_n).
 478  */
 479 uint16_t
 480 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 481 {
 482         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 483         uint16_t elts_head = txq->elts_head;
 484         const uint16_t elts_n = 1 << txq->elts_n;
 485         const uint16_t elts_m = elts_n - 1;
 486         unsigned int i = 0;
 487         unsigned int j = 0;
 488         unsigned int k = 0;
 489         uint16_t max_elts;
 490         uint16_t max_wqe;
 491         unsigned int comp;
 492         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 493         unsigned int segs_n = 0;
 494         const unsigned int max_inline = txq->max_inline;
 495
 496         if (unlikely(!pkts_n))
 497                 return 0;
 498         /* Prefetch first packet cacheline. */
 499         rte_prefetch0(*pkts);
 500         /* Start processing. */
 501         mlx5_tx_complete(txq);
 502         max_elts = (elts_n - (elts_head - txq->elts_tail));
 503         /* A CQE slot must always be available. */
 504         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 505         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 506         if (unlikely(!max_wqe))
 507                 return 0;
 508         do {
 509                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 510                 uint8_t *raw;
 511                 volatile struct mlx5_wqe_v *wqe = NULL;
 512                 volatile rte_v128u32_t *dseg = NULL;
 513                 uint32_t length;
 514                 unsigned int ds = 0;
 515                 unsigned int sg = 0; /* counter of additional segs attached. */
 516                 uintptr_t addr;
 517                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 518                 uint16_t tso_header_sz = 0;
 519                 uint16_t ehdr;
 520                 uint8_t cs_flags;
 521                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 522                 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
 523                 uint32_t swp_offsets = 0;
 524                 uint8_t swp_types = 0;
 525                 uint16_t tso_segsz = 0;
 526 #ifdef MLX5_PMD_SOFT_COUNTERS
 527                 uint32_t total_length = 0;
 528 #endif
 529                 int ret;
 530
 531                 segs_n = buf->nb_segs;
 532                 /*
 533                  * Make sure there is enough room to store this packet and
 534                  * that one ring entry remains unused.
 535                  */
 536                 assert(segs_n);
 537                 if (max_elts < segs_n)
 538                         break;
 539                 max_elts -= segs_n;
 540                 sg = --segs_n;
 541                 if (unlikely(--max_wqe == 0))
 542                         break;
 543                 wqe = (volatile struct mlx5_wqe_v *)
 544                         tx_mlx5_wqe(txq, txq->wqe_ci);
 545                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 546                 if (pkts_n - i > 1)
 547                         rte_prefetch0(*(pkts + 1));
 548                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 549                 length = DATA_LEN(buf);
 550                 ehdr = (((uint8_t *)addr)[1] << 8) |
 551                        ((uint8_t *)addr)[0];
 552 #ifdef MLX5_PMD_SOFT_COUNTERS
 553                 total_length = length;
 554 #endif
 555                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 556                         txq->stats.oerrors++;
 557                         break;
 558                 }
 559                 /* Update element. */
 560                 (*txq->elts)[elts_head & elts_m] = buf;
 561                 /* Prefetch next buffer data. */
 562                 if (pkts_n - i > 1)
 563                         rte_prefetch0(
 564                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 565                 cs_flags = txq_ol_cksum_to_cs(buf);
 566                 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
 567                                 (uint8_t *)&swp_offsets, &swp_types);
 568                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 569                 /* Replace the Ethernet type by the VLAN if necessary. */
 570                 if (is_vlan) {
 571                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 572                                                          buf->vlan_tci);
 573                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 574
 575                         addr += 2;
 576                         length -= 2;
 577                         /* Copy Destination and source mac address. */
 578                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 579                         /* Copy VLAN. */
 580                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 581                         /* Copy missing two bytes to end the DSeg. */
 582                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 583                                ((uint8_t *)addr) + len, 2);
 584                         addr += len + 2;
 585                         length -= (len + 2);
 586                 } else {
 587                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 588                                MLX5_WQE_DWORD_SIZE);
 589                         length -= pkt_inline_sz;
 590                         addr += pkt_inline_sz;
 591                 }
 592                 raw += MLX5_WQE_DWORD_SIZE;
 593                 if (tso) {
 594                         ret = inline_tso(txq, buf, &length,
 595                                          &addr, &pkt_inline_sz,
 596                                          &raw, &max_wqe,
 597                                          &tso_segsz, &tso_header_sz);
 598                         if (ret == -EINVAL) {
 599                                 break;
 600                         } else if (ret == -EAGAIN) {
 601                                 /* NOP WQE. */
 602                                 wqe->ctrl = (rte_v128u32_t){
 603                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 604                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 605                                         0,
 606                                         0,
 607                                 };
 608                                 ds = 1;
 609 #ifdef MLX5_PMD_SOFT_COUNTERS
 610                                 total_length = 0;
 611 #endif
 612                                 k++;
 613                                 goto next_wqe;
 614                         }
 615                 }
 616                 /* Inline if enough room. */
 617                 if (max_inline || tso) {
 618                         uint32_t inl = 0;
 619                         uintptr_t end = (uintptr_t)
 620                                 (((uintptr_t)txq->wqes) +
 621                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 622                         unsigned int inline_room = max_inline *
 623                                                    RTE_CACHE_LINE_SIZE -
 624                                                    (pkt_inline_sz - 2) -
 625                                                    !!tso * sizeof(inl);
 626                         uintptr_t addr_end;
 627                         unsigned int copy_b;
 628
 629 pkt_inline:
 630                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 631                                                    RTE_CACHE_LINE_SIZE);
 632                         copy_b = (addr_end > addr) ?
 633                                  RTE_MIN((addr_end - addr), length) : 0;
 634                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 635                                 /*
 636                                  * One Dseg remains in the current WQE.  To
 637                                  * keep the computation positive, it is
 638                                  * removed after the bytes to Dseg conversion.
 639                                  */
 640                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 641
 642                                 if (unlikely(max_wqe < n))
 643                                         break;
 644                                 max_wqe -= n;
 645                                 if (tso && !inl) {
 646                                         inl = rte_cpu_to_be_32(copy_b |
 647                                                                MLX5_INLINE_SEG);
 648                                         rte_memcpy((void *)raw,
 649                                                    (void *)&inl, sizeof(inl));
 650                                         raw += sizeof(inl);
 651                                         pkt_inline_sz += sizeof(inl);
 652                                 }
 653                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 654                                 addr += copy_b;
 655                                 length -= copy_b;
 656                                 pkt_inline_sz += copy_b;
 657                         }
 658                         /*
 659                          * 2 DWORDs consumed by the WQE header + ETH segment +
 660                          * the size of the inline part of the packet.
 661                          */
 662                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 663                         if (length > 0) {
 664                                 if (ds % (MLX5_WQE_SIZE /
 665                                           MLX5_WQE_DWORD_SIZE) == 0) {
 666                                         if (unlikely(--max_wqe == 0))
 667                                                 break;
 668                                         dseg = (volatile rte_v128u32_t *)
 669                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 670                                                            ds / 4);
 671                                 } else {
 672                                         dseg = (volatile rte_v128u32_t *)
 673                                                 ((uintptr_t)wqe +
 674                                                  (ds * MLX5_WQE_DWORD_SIZE));
 675                                 }
 676                                 goto use_dseg;
 677                         } else if (!segs_n) {
 678                                 goto next_pkt;
 679                         } else {
 680                                 raw += copy_b;
 681                                 inline_room -= copy_b;
 682                                 --segs_n;
 683                                 buf = buf->next;
 684                                 assert(buf);
 685                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 686                                 length = DATA_LEN(buf);
 687 #ifdef MLX5_PMD_SOFT_COUNTERS
 688                                 total_length += length;
 689 #endif
 690                                 (*txq->elts)[++elts_head & elts_m] = buf;
 691                                 goto pkt_inline;
 692                         }
 693                 } else {
 694                         /*
 695                          * No inline has been done in the packet, only the
 696                          * Ethernet Header as been stored.
 697                          */
 698                         dseg = (volatile rte_v128u32_t *)
 699                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 700                         ds = 3;
 701 use_dseg:
 702                         /* Add the remaining packet as a simple ds. */
 703                         addr = rte_cpu_to_be_64(addr);
 704                         *dseg = (rte_v128u32_t){
 705                                 rte_cpu_to_be_32(length),
 706                                 mlx5_tx_mb2mr(txq, buf),
 707                                 addr,
 708                                 addr >> 32,
 709                         };
 710                         ++ds;
 711                         if (!segs_n)
 712                                 goto next_pkt;
 713                 }
 714 next_seg:
 715                 assert(buf);
 716                 assert(ds);
 717                 assert(wqe);
 718                 /*
 719                  * Spill on next WQE when the current one does not have
 720                  * enough room left. Size of WQE must a be a multiple
 721                  * of data segment size.
 722                  */
 723                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 724                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 725                         if (unlikely(--max_wqe == 0))
 726                                 break;
 727                         dseg = (volatile rte_v128u32_t *)
 728                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 729                         rte_prefetch0(tx_mlx5_wqe(txq,
 730                                                   txq->wqe_ci + ds / 4 + 1));
 731                 } else {
 732                         ++dseg;
 733                 }
 734                 ++ds;
 735                 buf = buf->next;
 736                 assert(buf);
 737                 length = DATA_LEN(buf);
 738 #ifdef MLX5_PMD_SOFT_COUNTERS
 739                 total_length += length;
 740 #endif
 741                 /* Store segment information. */
 742                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 743                 *dseg = (rte_v128u32_t){
 744                         rte_cpu_to_be_32(length),
 745                         mlx5_tx_mb2mr(txq, buf),
 746                         addr,
 747                         addr >> 32,
 748                 };
 749                 (*txq->elts)[++elts_head & elts_m] = buf;
 750                 if (--segs_n)
 751                         goto next_seg;
 752 next_pkt:
 753                 if (ds > MLX5_DSEG_MAX) {
 754                         txq->stats.oerrors++;
 755                         break;
 756                 }
 757                 ++elts_head;
 758                 ++pkts;
 759                 ++i;
 760                 j += sg;
 761                 /* Initialize known and common part of the WQE structure. */
 762                 if (tso) {
 763                         wqe->ctrl = (rte_v128u32_t){
 764                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 765                                                  MLX5_OPCODE_TSO),
 766                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 767                                 0,
 768                                 0,
 769                         };
 770                         wqe->eseg = (rte_v128u32_t){
 771                                 swp_offsets,
 772                                 cs_flags | (swp_types << 8) |
 773                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 774                                 0,
 775                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 776                         };
 777                 } else {
 778                         wqe->ctrl = (rte_v128u32_t){
 779                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 780                                                  MLX5_OPCODE_SEND),
 781                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 782                                 0,
 783                                 0,
 784                         };
 785                         wqe->eseg = (rte_v128u32_t){
 786                                 swp_offsets,
 787                                 cs_flags | (swp_types << 8),
 788                                 0,
 789                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 790                         };
 791                 }
 792 next_wqe:
 793                 txq->wqe_ci += (ds + 3) / 4;
 794                 /* Save the last successful WQE for completion request */
 795                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 796 #ifdef MLX5_PMD_SOFT_COUNTERS
 797                 /* Increment sent bytes counter. */
 798                 txq->stats.obytes += total_length;
 799 #endif
 800         } while (i < pkts_n);
 801         /* Take a shortcut if nothing must be sent. */
 802         if (unlikely((i + k) == 0))
 803                 return 0;
 804         txq->elts_head += (i + j);
 805         /* Check whether completion threshold has been reached. */
 806         comp = txq->elts_comp + i + j + k;
 807         if (comp >= MLX5_TX_COMP_THRESH) {
 808                 /* Request completion on last WQE. */
 809                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 810                 /* Save elts_head in unused "immediate" field of WQE. */
 811                 last_wqe->ctrl3 = txq->elts_head;
 812                 txq->elts_comp = 0;
 813 #ifndef NDEBUG
 814                 ++txq->cq_pi;
 815 #endif
 816         } else {
 817                 txq->elts_comp = comp;
 818         }
 819 #ifdef MLX5_PMD_SOFT_COUNTERS
 820         /* Increment sent packets counter. */
 821         txq->stats.opackets += i;
 822 #endif
 823         /* Ring QP doorbell. */
 824         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 825         return i;
 826 }
 827
 828 /**
 829  * Open a MPW session.
 830  *
 831  * @param txq
 832  *   Pointer to TX queue structure.
 833  * @param mpw
 834  *   Pointer to MPW session structure.
 835  * @param length
 836  *   Packet length.
 837  */
 838 static inline void
 839 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 840 {
 841         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 842         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 843                 (volatile struct mlx5_wqe_data_seg (*)[])
 844                 tx_mlx5_wqe(txq, idx + 1);
 845
 846         mpw->state = MLX5_MPW_STATE_OPENED;
 847         mpw->pkts_n = 0;
 848         mpw->len = length;
 849         mpw->total_len = 0;
 850         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 851         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 852         mpw->wqe->eseg.inline_hdr_sz = 0;
 853         mpw->wqe->eseg.rsvd0 = 0;
 854         mpw->wqe->eseg.rsvd1 = 0;
 855         mpw->wqe->eseg.rsvd2 = 0;
 856         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 857                                              (txq->wqe_ci << 8) |
 858                                              MLX5_OPCODE_TSO);
 859         mpw->wqe->ctrl[2] = 0;
 860         mpw->wqe->ctrl[3] = 0;
 861         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 862                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 863         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 864                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 865         mpw->data.dseg[2] = &(*dseg)[0];
 866         mpw->data.dseg[3] = &(*dseg)[1];
 867         mpw->data.dseg[4] = &(*dseg)[2];
 868 }
 869
 870 /**
 871  * Close a MPW session.
 872  *
 873  * @param txq
 874  *   Pointer to TX queue structure.
 875  * @param mpw
 876  *   Pointer to MPW session structure.
 877  */
 878 static inline void
 879 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 880 {
 881         unsigned int num = mpw->pkts_n;
 882
 883         /*
 884          * Store size in multiple of 16 bytes. Control and Ethernet segments
 885          * count as 2.
 886          */
 887         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 888         mpw->state = MLX5_MPW_STATE_CLOSED;
 889         if (num < 3)
 890                 ++txq->wqe_ci;
 891         else
 892                 txq->wqe_ci += 2;
 893         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 894         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 895 }
 896
 897 /**
 898  * DPDK callback for TX with MPW support.
 899  *
 900  * @param dpdk_txq
 901  *   Generic pointer to TX queue structure.
 902  * @param[in] pkts
 903  *   Packets to transmit.
 904  * @param pkts_n
 905  *   Number of packets in array.
 906  *
 907  * @return
 908  *   Number of packets successfully transmitted (<= pkts_n).
 909  */
 910 uint16_t
 911 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 912 {
 913         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 914         uint16_t elts_head = txq->elts_head;
 915         const uint16_t elts_n = 1 << txq->elts_n;
 916         const uint16_t elts_m = elts_n - 1;
 917         unsigned int i = 0;
 918         unsigned int j = 0;
 919         uint16_t max_elts;
 920         uint16_t max_wqe;
 921         unsigned int comp;
 922         struct mlx5_mpw mpw = {
 923                 .state = MLX5_MPW_STATE_CLOSED,
 924         };
 925
 926         if (unlikely(!pkts_n))
 927                 return 0;
 928         /* Prefetch first packet cacheline. */
 929         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 930         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 931         /* Start processing. */
 932         mlx5_tx_complete(txq);
 933         max_elts = (elts_n - (elts_head - txq->elts_tail));
 934         /* A CQE slot must always be available. */
 935         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 936         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 937         if (unlikely(!max_wqe))
 938                 return 0;
 939         do {
 940                 struct rte_mbuf *buf = *(pkts++);
 941                 uint32_t length;
 942                 unsigned int segs_n = buf->nb_segs;
 943                 uint32_t cs_flags;
 944
 945                 /*
 946                  * Make sure there is enough room to store this packet and
 947                  * that one ring entry remains unused.
 948                  */
 949                 assert(segs_n);
 950                 if (max_elts < segs_n)
 951                         break;
 952                 /* Do not bother with large packets MPW cannot handle. */
 953                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 954                         txq->stats.oerrors++;
 955                         break;
 956                 }
 957                 max_elts -= segs_n;
 958                 --pkts_n;
 959                 cs_flags = txq_ol_cksum_to_cs(buf);
 960                 /* Retrieve packet information. */
 961                 length = PKT_LEN(buf);
 962                 assert(length);
 963                 /* Start new session if packet differs. */
 964                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 965                     ((mpw.len != length) ||
 966                      (segs_n != 1) ||
 967                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 968                         mlx5_mpw_close(txq, &mpw);
 969                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 970                         /*
 971                          * Multi-Packet WQE consumes at most two WQE.
 972                          * mlx5_mpw_new() expects to be able to use such
 973                          * resources.
 974                          */
 975                         if (unlikely(max_wqe < 2))
 976                                 break;
 977                         max_wqe -= 2;
 978                         mlx5_mpw_new(txq, &mpw, length);
 979                         mpw.wqe->eseg.cs_flags = cs_flags;
 980                 }
 981                 /* Multi-segment packets must be alone in their MPW. */
 982                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 983 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 984                 length = 0;
 985 #endif
 986                 do {
 987                         volatile struct mlx5_wqe_data_seg *dseg;
 988                         uintptr_t addr;
 989
 990                         assert(buf);
 991                         (*txq->elts)[elts_head++ & elts_m] = buf;
 992                         dseg = mpw.data.dseg[mpw.pkts_n];
 993                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 994                         *dseg = (struct mlx5_wqe_data_seg){
 995                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 996                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 997                                 .addr = rte_cpu_to_be_64(addr),
 998                         };
 999 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1000                         length += DATA_LEN(buf);
1001 #endif
1002                         buf = buf->next;
1003                         ++mpw.pkts_n;
1004                         ++j;
1005                 } while (--segs_n);
1006                 assert(length == mpw.len);
1007                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1008                         mlx5_mpw_close(txq, &mpw);
1009 #ifdef MLX5_PMD_SOFT_COUNTERS
1010                 /* Increment sent bytes counter. */
1011                 txq->stats.obytes += length;
1012 #endif
1013                 ++i;
1014         } while (pkts_n);
1015         /* Take a shortcut if nothing must be sent. */
1016         if (unlikely(i == 0))
1017                 return 0;
1018         /* Check whether completion threshold has been reached. */
1019         /* "j" includes both packets and segments. */
1020         comp = txq->elts_comp + j;
1021         if (comp >= MLX5_TX_COMP_THRESH) {
1022                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1023
1024                 /* Request completion on last WQE. */
1025                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1026                 /* Save elts_head in unused "immediate" field of WQE. */
1027                 wqe->ctrl[3] = elts_head;
1028                 txq->elts_comp = 0;
1029 #ifndef NDEBUG
1030                 ++txq->cq_pi;
1031 #endif
1032         } else {
1033                 txq->elts_comp = comp;
1034         }
1035 #ifdef MLX5_PMD_SOFT_COUNTERS
1036         /* Increment sent packets counter. */
1037         txq->stats.opackets += i;
1038 #endif
1039         /* Ring QP doorbell. */
1040         if (mpw.state == MLX5_MPW_STATE_OPENED)
1041                 mlx5_mpw_close(txq, &mpw);
1042         mlx5_tx_dbrec(txq, mpw.wqe);
1043         txq->elts_head = elts_head;
1044         return i;
1045 }
1046
1047 /**
1048  * Open a MPW inline session.
1049  *
1050  * @param txq
1051  *   Pointer to TX queue structure.
1052  * @param mpw
1053  *   Pointer to MPW session structure.
1054  * @param length
1055  *   Packet length.
1056  */
1057 static inline void
1058 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1059                     uint32_t length)
1060 {
1061         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1062         struct mlx5_wqe_inl_small *inl;
1063
1064         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1065         mpw->pkts_n = 0;
1066         mpw->len = length;
1067         mpw->total_len = 0;
1068         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1069         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1070                                              (txq->wqe_ci << 8) |
1071                                              MLX5_OPCODE_TSO);
1072         mpw->wqe->ctrl[2] = 0;
1073         mpw->wqe->ctrl[3] = 0;
1074         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1075         mpw->wqe->eseg.inline_hdr_sz = 0;
1076         mpw->wqe->eseg.cs_flags = 0;
1077         mpw->wqe->eseg.rsvd0 = 0;
1078         mpw->wqe->eseg.rsvd1 = 0;
1079         mpw->wqe->eseg.rsvd2 = 0;
1080         inl = (struct mlx5_wqe_inl_small *)
1081                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1082         mpw->data.raw = (uint8_t *)&inl->raw;
1083 }
1084
1085 /**
1086  * Close a MPW inline session.
1087  *
1088  * @param txq
1089  *   Pointer to TX queue structure.
1090  * @param mpw
1091  *   Pointer to MPW session structure.
1092  */
1093 static inline void
1094 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1095 {
1096         unsigned int size;
1097         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1098                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1099
1100         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1101         /*
1102          * Store size in multiple of 16 bytes. Control and Ethernet segments
1103          * count as 2.
1104          */
1105         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1106                                              MLX5_WQE_DS(size));
1107         mpw->state = MLX5_MPW_STATE_CLOSED;
1108         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1109         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1110 }
1111
1112 /**
1113  * DPDK callback for TX with MPW inline support.
1114  *
1115  * @param dpdk_txq
1116  *   Generic pointer to TX queue structure.
1117  * @param[in] pkts
1118  *   Packets to transmit.
1119  * @param pkts_n
1120  *   Number of packets in array.
1121  *
1122  * @return
1123  *   Number of packets successfully transmitted (<= pkts_n).
1124  */
1125 uint16_t
1126 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1127                          uint16_t pkts_n)
1128 {
1129         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1130         uint16_t elts_head = txq->elts_head;
1131         const uint16_t elts_n = 1 << txq->elts_n;
1132         const uint16_t elts_m = elts_n - 1;
1133         unsigned int i = 0;
1134         unsigned int j = 0;
1135         uint16_t max_elts;
1136         uint16_t max_wqe;
1137         unsigned int comp;
1138         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1139         struct mlx5_mpw mpw = {
1140                 .state = MLX5_MPW_STATE_CLOSED,
1141         };
1142         /*
1143          * Compute the maximum number of WQE which can be consumed by inline
1144          * code.
1145          * - 2 DSEG for:
1146          *   - 1 control segment,
1147          *   - 1 Ethernet segment,
1148          * - N Dseg from the inline request.
1149          */
1150         const unsigned int wqe_inl_n =
1151                 ((2 * MLX5_WQE_DWORD_SIZE +
1152                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1153                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1154
1155         if (unlikely(!pkts_n))
1156                 return 0;
1157         /* Prefetch first packet cacheline. */
1158         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1159         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1160         /* Start processing. */
1161         mlx5_tx_complete(txq);
1162         max_elts = (elts_n - (elts_head - txq->elts_tail));
1163         /* A CQE slot must always be available. */
1164         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1165         do {
1166                 struct rte_mbuf *buf = *(pkts++);
1167                 uintptr_t addr;
1168                 uint32_t length;
1169                 unsigned int segs_n = buf->nb_segs;
1170                 uint8_t cs_flags;
1171
1172                 /*
1173                  * Make sure there is enough room to store this packet and
1174                  * that one ring entry remains unused.
1175                  */
1176                 assert(segs_n);
1177                 if (max_elts < segs_n)
1178                         break;
1179                 /* Do not bother with large packets MPW cannot handle. */
1180                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1181                         txq->stats.oerrors++;
1182                         break;
1183                 }
1184                 max_elts -= segs_n;
1185                 --pkts_n;
1186                 /*
1187                  * Compute max_wqe in case less WQE were consumed in previous
1188                  * iteration.
1189                  */
1190                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1191                 cs_flags = txq_ol_cksum_to_cs(buf);
1192                 /* Retrieve packet information. */
1193                 length = PKT_LEN(buf);
1194                 /* Start new session if packet differs. */
1195                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1196                         if ((mpw.len != length) ||
1197                             (segs_n != 1) ||
1198                             (mpw.wqe->eseg.cs_flags != cs_flags))
1199                                 mlx5_mpw_close(txq, &mpw);
1200                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1201                         if ((mpw.len != length) ||
1202                             (segs_n != 1) ||
1203                             (length > inline_room) ||
1204                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1205                                 mlx5_mpw_inline_close(txq, &mpw);
1206                                 inline_room =
1207                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1208                         }
1209                 }
1210                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1211                         if ((segs_n != 1) ||
1212                             (length > inline_room)) {
1213                                 /*
1214                                  * Multi-Packet WQE consumes at most two WQE.
1215                                  * mlx5_mpw_new() expects to be able to use
1216                                  * such resources.
1217                                  */
1218                                 if (unlikely(max_wqe < 2))
1219                                         break;
1220                                 max_wqe -= 2;
1221                                 mlx5_mpw_new(txq, &mpw, length);
1222                                 mpw.wqe->eseg.cs_flags = cs_flags;
1223                         } else {
1224                                 if (unlikely(max_wqe < wqe_inl_n))
1225                                         break;
1226                                 max_wqe -= wqe_inl_n;
1227                                 mlx5_mpw_inline_new(txq, &mpw, length);
1228                                 mpw.wqe->eseg.cs_flags = cs_flags;
1229                         }
1230                 }
1231                 /* Multi-segment packets must be alone in their MPW. */
1232                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1233                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1234                         assert(inline_room ==
1235                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1236 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1237                         length = 0;
1238 #endif
1239                         do {
1240                                 volatile struct mlx5_wqe_data_seg *dseg;
1241
1242                                 assert(buf);
1243                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1244                                 dseg = mpw.data.dseg[mpw.pkts_n];
1245                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1246                                 *dseg = (struct mlx5_wqe_data_seg){
1247                                         .byte_count =
1248                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1249                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1250                                         .addr = rte_cpu_to_be_64(addr),
1251                                 };
1252 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1253                                 length += DATA_LEN(buf);
1254 #endif
1255                                 buf = buf->next;
1256                                 ++mpw.pkts_n;
1257                                 ++j;
1258                         } while (--segs_n);
1259                         assert(length == mpw.len);
1260                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1261                                 mlx5_mpw_close(txq, &mpw);
1262                 } else {
1263                         unsigned int max;
1264
1265                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1266                         assert(length <= inline_room);
1267                         assert(length == DATA_LEN(buf));
1268                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1269                         (*txq->elts)[elts_head++ & elts_m] = buf;
1270                         /* Maximum number of bytes before wrapping. */
1271                         max = ((((uintptr_t)(txq->wqes)) +
1272                                 (1 << txq->wqe_n) *
1273                                 MLX5_WQE_SIZE) -
1274                                (uintptr_t)mpw.data.raw);
1275                         if (length > max) {
1276                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1277                                            (void *)addr,
1278                                            max);
1279                                 mpw.data.raw = (volatile void *)txq->wqes;
1280                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1281                                            (void *)(addr + max),
1282                                            length - max);
1283                                 mpw.data.raw += length - max;
1284                         } else {
1285                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1286                                            (void *)addr,
1287                                            length);
1288
1289                                 if (length == max)
1290                                         mpw.data.raw =
1291                                                 (volatile void *)txq->wqes;
1292                                 else
1293                                         mpw.data.raw += length;
1294                         }
1295                         ++mpw.pkts_n;
1296                         mpw.total_len += length;
1297                         ++j;
1298                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1299                                 mlx5_mpw_inline_close(txq, &mpw);
1300                                 inline_room =
1301                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1302                         } else {
1303                                 inline_room -= length;
1304                         }
1305                 }
1306 #ifdef MLX5_PMD_SOFT_COUNTERS
1307                 /* Increment sent bytes counter. */
1308                 txq->stats.obytes += length;
1309 #endif
1310                 ++i;
1311         } while (pkts_n);
1312         /* Take a shortcut if nothing must be sent. */
1313         if (unlikely(i == 0))
1314                 return 0;
1315         /* Check whether completion threshold has been reached. */
1316         /* "j" includes both packets and segments. */
1317         comp = txq->elts_comp + j;
1318         if (comp >= MLX5_TX_COMP_THRESH) {
1319                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1320
1321                 /* Request completion on last WQE. */
1322                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1323                 /* Save elts_head in unused "immediate" field of WQE. */
1324                 wqe->ctrl[3] = elts_head;
1325                 txq->elts_comp = 0;
1326 #ifndef NDEBUG
1327                 ++txq->cq_pi;
1328 #endif
1329         } else {
1330                 txq->elts_comp = comp;
1331         }
1332 #ifdef MLX5_PMD_SOFT_COUNTERS
1333         /* Increment sent packets counter. */
1334         txq->stats.opackets += i;
1335 #endif
1336         /* Ring QP doorbell. */
1337         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1338                 mlx5_mpw_inline_close(txq, &mpw);
1339         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1340                 mlx5_mpw_close(txq, &mpw);
1341         mlx5_tx_dbrec(txq, mpw.wqe);
1342         txq->elts_head = elts_head;
1343         return i;
1344 }
1345
1346 /**
1347  * Open an Enhanced MPW session.
1348  *
1349  * @param txq
1350  *   Pointer to TX queue structure.
1351  * @param mpw
1352  *   Pointer to MPW session structure.
1353  * @param length
1354  *   Packet length.
1355  */
1356 static inline void
1357 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1358 {
1359         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1360
1361         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1362         mpw->pkts_n = 0;
1363         mpw->total_len = sizeof(struct mlx5_wqe);
1364         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1365         mpw->wqe->ctrl[0] =
1366                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1367                                  (txq->wqe_ci << 8) |
1368                                  MLX5_OPCODE_ENHANCED_MPSW);
1369         mpw->wqe->ctrl[2] = 0;
1370         mpw->wqe->ctrl[3] = 0;
1371         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1372         if (unlikely(padding)) {
1373                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1374
1375                 /* Pad the first 2 DWORDs with zero-length inline header. */
1376                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1377                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1378                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1379                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1380                 /* Start from the next WQEBB. */
1381                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1382         } else {
1383                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1384         }
1385 }
1386
1387 /**
1388  * Close an Enhanced MPW session.
1389  *
1390  * @param txq
1391  *   Pointer to TX queue structure.
1392  * @param mpw
1393  *   Pointer to MPW session structure.
1394  *
1395  * @return
1396  *   Number of consumed WQEs.
1397  */
1398 static inline uint16_t
1399 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1400 {
1401         uint16_t ret;
1402
1403         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1404          * count as 2.
1405          */
1406         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1407                                              MLX5_WQE_DS(mpw->total_len));
1408         mpw->state = MLX5_MPW_STATE_CLOSED;
1409         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1410         txq->wqe_ci += ret;
1411         return ret;
1412 }
1413
1414 /**
1415  * TX with Enhanced MPW support.
1416  *
1417  * @param txq
1418  *   Pointer to TX queue structure.
1419  * @param[in] pkts
1420  *   Packets to transmit.
1421  * @param pkts_n
1422  *   Number of packets in array.
1423  *
1424  * @return
1425  *   Number of packets successfully transmitted (<= pkts_n).
1426  */
1427 static inline uint16_t
1428 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1429                uint16_t pkts_n)
1430 {
1431         uint16_t elts_head = txq->elts_head;
1432         const uint16_t elts_n = 1 << txq->elts_n;
1433         const uint16_t elts_m = elts_n - 1;
1434         unsigned int i = 0;
1435         unsigned int j = 0;
1436         uint16_t max_elts;
1437         uint16_t max_wqe;
1438         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1439         unsigned int mpw_room = 0;
1440         unsigned int inl_pad = 0;
1441         uint32_t inl_hdr;
1442         struct mlx5_mpw mpw = {
1443                 .state = MLX5_MPW_STATE_CLOSED,
1444         };
1445
1446         if (unlikely(!pkts_n))
1447                 return 0;
1448         /* Start processing. */
1449         mlx5_tx_complete(txq);
1450         max_elts = (elts_n - (elts_head - txq->elts_tail));
1451         /* A CQE slot must always be available. */
1452         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1453         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1454         if (unlikely(!max_wqe))
1455                 return 0;
1456         do {
1457                 struct rte_mbuf *buf = *(pkts++);
1458                 uintptr_t addr;
1459                 unsigned int do_inline = 0; /* Whether inline is possible. */
1460                 uint32_t length;
1461                 uint8_t cs_flags;
1462
1463                 /* Multi-segmented packet is handled in slow-path outside. */
1464                 assert(NB_SEGS(buf) == 1);
1465                 /* Make sure there is enough room to store this packet. */
1466                 if (max_elts - j == 0)
1467                         break;
1468                 cs_flags = txq_ol_cksum_to_cs(buf);
1469                 /* Retrieve packet information. */
1470                 length = PKT_LEN(buf);
1471                 /* Start new session if:
1472                  * - multi-segment packet
1473                  * - no space left even for a dseg
1474                  * - next packet can be inlined with a new WQE
1475                  * - cs_flag differs
1476                  */
1477                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1478                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1479                              mpw_room) ||
1480                             (length <= txq->inline_max_packet_sz &&
1481                              inl_pad + sizeof(inl_hdr) + length >
1482                              mpw_room) ||
1483                             (mpw.wqe->eseg.cs_flags != cs_flags))
1484                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1485                 }
1486                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1487                         /* In Enhanced MPW, inline as much as the budget is
1488                          * allowed. The remaining space is to be filled with
1489                          * dsegs. If the title WQEBB isn't padded, it will have
1490                          * 2 dsegs there.
1491                          */
1492                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1493                                            (max_inline ? max_inline :
1494                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1495                                            MLX5_WQE_SIZE);
1496                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1497                                 break;
1498                         /* Don't pad the title WQEBB to not waste WQ. */
1499                         mlx5_empw_new(txq, &mpw, 0);
1500                         mpw_room -= mpw.total_len;
1501                         inl_pad = 0;
1502                         do_inline = length <= txq->inline_max_packet_sz &&
1503                                     sizeof(inl_hdr) + length <= mpw_room &&
1504                                     !txq->mpw_hdr_dseg;
1505                         mpw.wqe->eseg.cs_flags = cs_flags;
1506                 } else {
1507                         /* Evaluate whether the next packet can be inlined.
1508                          * Inlininig is possible when:
1509                          * - length is less than configured value
1510                          * - length fits for remaining space
1511                          * - not required to fill the title WQEBB with dsegs
1512                          */
1513                         do_inline =
1514                                 length <= txq->inline_max_packet_sz &&
1515                                 inl_pad + sizeof(inl_hdr) + length <=
1516                                  mpw_room &&
1517                                 (!txq->mpw_hdr_dseg ||
1518                                  mpw.total_len >= MLX5_WQE_SIZE);
1519                 }
1520                 if (max_inline && do_inline) {
1521                         /* Inline packet into WQE. */
1522                         unsigned int max;
1523
1524                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1525                         assert(length == DATA_LEN(buf));
1526                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1527                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1528                         mpw.data.raw = (volatile void *)
1529                                 ((uintptr_t)mpw.data.raw + inl_pad);
1530                         max = tx_mlx5_wq_tailroom(txq,
1531                                         (void *)(uintptr_t)mpw.data.raw);
1532                         /* Copy inline header. */
1533                         mpw.data.raw = (volatile void *)
1534                                 mlx5_copy_to_wq(
1535                                           (void *)(uintptr_t)mpw.data.raw,
1536                                           &inl_hdr,
1537                                           sizeof(inl_hdr),
1538                                           (void *)(uintptr_t)txq->wqes,
1539                                           max);
1540                         max = tx_mlx5_wq_tailroom(txq,
1541                                         (void *)(uintptr_t)mpw.data.raw);
1542                         /* Copy packet data. */
1543                         mpw.data.raw = (volatile void *)
1544                                 mlx5_copy_to_wq(
1545                                           (void *)(uintptr_t)mpw.data.raw,
1546                                           (void *)addr,
1547                                           length,
1548                                           (void *)(uintptr_t)txq->wqes,
1549                                           max);
1550                         ++mpw.pkts_n;
1551                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1552                         /* No need to get completion as the entire packet is
1553                          * copied to WQ. Free the buf right away.
1554                          */
1555                         rte_pktmbuf_free_seg(buf);
1556                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1557                         /* Add pad in the next packet if any. */
1558                         inl_pad = (((uintptr_t)mpw.data.raw +
1559                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1560                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1561                                   (uintptr_t)mpw.data.raw;
1562                 } else {
1563                         /* No inline. Load a dseg of packet pointer. */
1564                         volatile rte_v128u32_t *dseg;
1565
1566                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1567                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1568                         assert(length == DATA_LEN(buf));
1569                         if (!tx_mlx5_wq_tailroom(txq,
1570                                         (void *)((uintptr_t)mpw.data.raw
1571                                                 + inl_pad)))
1572                                 dseg = (volatile void *)txq->wqes;
1573                         else
1574                                 dseg = (volatile void *)
1575                                         ((uintptr_t)mpw.data.raw +
1576                                          inl_pad);
1577                         (*txq->elts)[elts_head++ & elts_m] = buf;
1578                         addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1579                                                                  uintptr_t));
1580                         *dseg = (rte_v128u32_t) {
1581                                 rte_cpu_to_be_32(length),
1582                                 mlx5_tx_mb2mr(txq, buf),
1583                                 addr,
1584                                 addr >> 32,
1585                         };
1586                         mpw.data.raw = (volatile void *)(dseg + 1);
1587                         mpw.total_len += (inl_pad + sizeof(*dseg));
1588                         ++j;
1589                         ++mpw.pkts_n;
1590                         mpw_room -= (inl_pad + sizeof(*dseg));
1591                         inl_pad = 0;
1592                 }
1593 #ifdef MLX5_PMD_SOFT_COUNTERS
1594                 /* Increment sent bytes counter. */
1595                 txq->stats.obytes += length;
1596 #endif
1597                 ++i;
1598         } while (i < pkts_n);
1599         /* Take a shortcut if nothing must be sent. */
1600         if (unlikely(i == 0))
1601                 return 0;
1602         /* Check whether completion threshold has been reached. */
1603         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1604                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1605                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1606                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1607
1608                 /* Request completion on last WQE. */
1609                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1610                 /* Save elts_head in unused "immediate" field of WQE. */
1611                 wqe->ctrl[3] = elts_head;
1612                 txq->elts_comp = 0;
1613                 txq->mpw_comp = txq->wqe_ci;
1614 #ifndef NDEBUG
1615                 ++txq->cq_pi;
1616 #endif
1617         } else {
1618                 txq->elts_comp += j;
1619         }
1620 #ifdef MLX5_PMD_SOFT_COUNTERS
1621         /* Increment sent packets counter. */
1622         txq->stats.opackets += i;
1623 #endif
1624         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1625                 mlx5_empw_close(txq, &mpw);
1626         /* Ring QP doorbell. */
1627         mlx5_tx_dbrec(txq, mpw.wqe);
1628         txq->elts_head = elts_head;
1629         return i;
1630 }
1631
1632 /**
1633  * DPDK callback for TX with Enhanced MPW support.
1634  *
1635  * @param dpdk_txq
1636  *   Generic pointer to TX queue structure.
1637  * @param[in] pkts
1638  *   Packets to transmit.
1639  * @param pkts_n
1640  *   Number of packets in array.
1641  *
1642  * @return
1643  *   Number of packets successfully transmitted (<= pkts_n).
1644  */
1645 uint16_t
1646 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1647 {
1648         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1649         uint16_t nb_tx = 0;
1650
1651         while (pkts_n > nb_tx) {
1652                 uint16_t n;
1653                 uint16_t ret;
1654
1655                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1656                 if (n) {
1657                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1658                         if (!ret)
1659                                 break;
1660                         nb_tx += ret;
1661                 }
1662                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1663                 if (n) {
1664                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1665                         if (!ret)
1666                                 break;
1667                         nb_tx += ret;
1668                 }
1669         }
1670         return nb_tx;
1671 }
1672
1673 /**
1674  * Translate RX completion flags to packet type.
1675  *
1676  * @param[in] rxq
1677  *   Pointer to RX queue structure.
1678  * @param[in] cqe
1679  *   Pointer to CQE.
1680  *
1681  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1682  *
1683  * @return
1684  *   Packet type for struct rte_mbuf.
1685  */
1686 static inline uint32_t
1687 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1688 {
1689         uint8_t idx;
1690         uint8_t pinfo = cqe->pkt_info;
1691         uint16_t ptype = cqe->hdr_type_etc;
1692
1693         /*
1694          * The index to the array should have:
1695          * bit[1:0] = l3_hdr_type
1696          * bit[4:2] = l4_hdr_type
1697          * bit[5] = ip_frag
1698          * bit[6] = tunneled
1699          * bit[7] = outer_l3_type
1700          */
1701         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1702         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1703 }
1704
1705 /**
1706  * Get size of the next packet for a given CQE. For compressed CQEs, the
1707  * consumer index is updated only once all packets of the current one have
1708  * been processed.
1709  *
1710  * @param rxq
1711  *   Pointer to RX queue.
1712  * @param cqe
1713  *   CQE to process.
1714  * @param[out] rss_hash
1715  *   Packet RSS Hash result.
1716  *
1717  * @return
1718  *   Packet size in bytes (0 if there is none), -1 in case of completion
1719  *   with error.
1720  */
1721 static inline int
1722 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1723                  uint16_t cqe_cnt, uint32_t *rss_hash)
1724 {
1725         struct rxq_zip *zip = &rxq->zip;
1726         uint16_t cqe_n = cqe_cnt + 1;
1727         int len = 0;
1728         uint16_t idx, end;
1729
1730         /* Process compressed data in the CQE and mini arrays. */
1731         if (zip->ai) {
1732                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1733                         (volatile struct mlx5_mini_cqe8 (*)[8])
1734                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1735
1736                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1737                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1738                 if ((++zip->ai & 7) == 0) {
1739                         /* Invalidate consumed CQEs */
1740                         idx = zip->ca;
1741                         end = zip->na;
1742                         while (idx != end) {
1743                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1744                                         MLX5_CQE_INVALIDATE;
1745                                 ++idx;
1746                         }
1747                         /*
1748                          * Increment consumer index to skip the number of
1749                          * CQEs consumed. Hardware leaves holes in the CQ
1750                          * ring for software use.
1751                          */
1752                         zip->ca = zip->na;
1753                         zip->na += 8;
1754                 }
1755                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1756                         /* Invalidate the rest */
1757                         idx = zip->ca;
1758                         end = zip->cq_ci;
1759
1760                         while (idx != end) {
1761                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1762                                         MLX5_CQE_INVALIDATE;
1763                                 ++idx;
1764                         }
1765                         rxq->cq_ci = zip->cq_ci;
1766                         zip->ai = 0;
1767                 }
1768         /* No compressed data, get next CQE and verify if it is compressed. */
1769         } else {
1770                 int ret;
1771                 int8_t op_own;
1772
1773                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1774                 if (unlikely(ret == 1))
1775                         return 0;
1776                 ++rxq->cq_ci;
1777                 op_own = cqe->op_own;
1778                 rte_cio_rmb();
1779                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1780                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1781                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1782                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1783                                                           cqe_cnt].pkt_info);
1784
1785                         /* Fix endianness. */
1786                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1787                         /*
1788                          * Current mini array position is the one returned by
1789                          * check_cqe64().
1790                          *
1791                          * If completion comprises several mini arrays, as a
1792                          * special case the second one is located 7 CQEs after
1793                          * the initial CQE instead of 8 for subsequent ones.
1794                          */
1795                         zip->ca = rxq->cq_ci;
1796                         zip->na = zip->ca + 7;
1797                         /* Compute the next non compressed CQE. */
1798                         --rxq->cq_ci;
1799                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1800                         /* Get packet size to return. */
1801                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1802                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1803                         zip->ai = 1;
1804                         /* Prefetch all the entries to be invalidated */
1805                         idx = zip->ca;
1806                         end = zip->cq_ci;
1807                         while (idx != end) {
1808                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1809                                 ++idx;
1810                         }
1811                 } else {
1812                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1813                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1814                 }
1815                 /* Error while receiving packet. */
1816                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1817                         return -1;
1818         }
1819         return len;
1820 }
1821
1822 /**
1823  * Translate RX completion flags to offload flags.
1824  *
1825  * @param[in] cqe
1826  *   Pointer to CQE.
1827  *
1828  * @return
1829  *   Offload flags (ol_flags) for struct rte_mbuf.
1830  */
1831 static inline uint32_t
1832 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1833 {
1834         uint32_t ol_flags = 0;
1835         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1836
1837         ol_flags =
1838                 TRANSPOSE(flags,
1839                           MLX5_CQE_RX_L3_HDR_VALID,
1840                           PKT_RX_IP_CKSUM_GOOD) |
1841                 TRANSPOSE(flags,
1842                           MLX5_CQE_RX_L4_HDR_VALID,
1843                           PKT_RX_L4_CKSUM_GOOD);
1844         return ol_flags;
1845 }
1846
1847 /**
1848  * Fill in mbuf fields from RX completion flags.
1849  * Note that pkt->ol_flags should be initialized outside of this function.
1850  *
1851  * @param rxq
1852  *   Pointer to RX queue.
1853  * @param pkt
1854  *   mbuf to fill.
1855  * @param cqe
1856  *   CQE to process.
1857  * @param rss_hash_res
1858  *   Packet RSS Hash result.
1859  */
1860 static inline void
1861 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1862                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1863 {
1864         /* Update packet information. */
1865         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1866         if (rss_hash_res && rxq->rss_hash) {
1867                 pkt->hash.rss = rss_hash_res;
1868                 pkt->ol_flags |= PKT_RX_RSS_HASH;
1869         }
1870         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1871                 pkt->ol_flags |= PKT_RX_FDIR;
1872                 if (cqe->sop_drop_qpn !=
1873                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1874                         uint32_t mark = cqe->sop_drop_qpn;
1875
1876                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1877                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1878                 }
1879         }
1880         if (rxq->csum)
1881                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1882         if (rxq->vlan_strip &&
1883             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1884                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1885                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1886         }
1887         if (rxq->hw_timestamp) {
1888                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1889                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1890         }
1891 }
1892
1893 /**
1894  * DPDK callback for RX.
1895  *
1896  * @param dpdk_rxq
1897  *   Generic pointer to RX queue structure.
1898  * @param[out] pkts
1899  *   Array to store received packets.
1900  * @param pkts_n
1901  *   Maximum number of packets in array.
1902  *
1903  * @return
1904  *   Number of packets successfully received (<= pkts_n).
1905  */
1906 uint16_t
1907 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1908 {
1909         struct mlx5_rxq_data *rxq = dpdk_rxq;
1910         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1911         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1912         const unsigned int sges_n = rxq->sges_n;
1913         struct rte_mbuf *pkt = NULL;
1914         struct rte_mbuf *seg = NULL;
1915         volatile struct mlx5_cqe *cqe =
1916                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1917         unsigned int i = 0;
1918         unsigned int rq_ci = rxq->rq_ci << sges_n;
1919         int len = 0; /* keep its value across iterations. */
1920
1921         while (pkts_n) {
1922                 unsigned int idx = rq_ci & wqe_cnt;
1923                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1924                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1925                 uint32_t rss_hash_res = 0;
1926
1927                 if (pkt)
1928                         NEXT(seg) = rep;
1929                 seg = rep;
1930                 rte_prefetch0(seg);
1931                 rte_prefetch0(cqe);
1932                 rte_prefetch0(wqe);
1933                 rep = rte_mbuf_raw_alloc(rxq->mp);
1934                 if (unlikely(rep == NULL)) {
1935                         ++rxq->stats.rx_nombuf;
1936                         if (!pkt) {
1937                                 /*
1938                                  * no buffers before we even started,
1939                                  * bail out silently.
1940                                  */
1941                                 break;
1942                         }
1943                         while (pkt != seg) {
1944                                 assert(pkt != (*rxq->elts)[idx]);
1945                                 rep = NEXT(pkt);
1946                                 NEXT(pkt) = NULL;
1947                                 NB_SEGS(pkt) = 1;
1948                                 rte_mbuf_raw_free(pkt);
1949                                 pkt = rep;
1950                         }
1951                         break;
1952                 }
1953                 if (!pkt) {
1954                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1955                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1956                                                &rss_hash_res);
1957                         if (!len) {
1958                                 rte_mbuf_raw_free(rep);
1959                                 break;
1960                         }
1961                         if (unlikely(len == -1)) {
1962                                 /* RX error, packet is likely too large. */
1963                                 rte_mbuf_raw_free(rep);
1964                                 ++rxq->stats.idropped;
1965                                 goto skip;
1966                         }
1967                         pkt = seg;
1968                         assert(len >= (rxq->crc_present << 2));
1969                         pkt->ol_flags = 0;
1970                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1971                         if (rxq->crc_present)
1972                                 len -= ETHER_CRC_LEN;
1973                         PKT_LEN(pkt) = len;
1974                 }
1975                 DATA_LEN(rep) = DATA_LEN(seg);
1976                 PKT_LEN(rep) = PKT_LEN(seg);
1977                 SET_DATA_OFF(rep, DATA_OFF(seg));
1978                 PORT(rep) = PORT(seg);
1979                 (*rxq->elts)[idx] = rep;
1980                 /*
1981                  * Fill NIC descriptor with the new buffer.  The lkey and size
1982                  * of the buffers are already known, only the buffer address
1983                  * changes.
1984                  */
1985                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1986                 /* If there's only one MR, no need to replace LKey in WQE. */
1987                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1988                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1989                 if (len > DATA_LEN(seg)) {
1990                         len -= DATA_LEN(seg);
1991                         ++NB_SEGS(pkt);
1992                         ++rq_ci;
1993                         continue;
1994                 }
1995                 DATA_LEN(seg) = len;
1996 #ifdef MLX5_PMD_SOFT_COUNTERS
1997                 /* Increment bytes counter. */
1998                 rxq->stats.ibytes += PKT_LEN(pkt);
1999 #endif
2000                 /* Return packet. */
2001                 *(pkts++) = pkt;
2002                 pkt = NULL;
2003                 --pkts_n;
2004                 ++i;
2005 skip:
2006                 /* Align consumer index to the next stride. */
2007                 rq_ci >>= sges_n;
2008                 ++rq_ci;
2009                 rq_ci <<= sges_n;
2010         }
2011         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2012                 return 0;
2013         /* Update the consumer index. */
2014         rxq->rq_ci = rq_ci >> sges_n;
2015         rte_cio_wmb();
2016         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2017         rte_cio_wmb();
2018         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2019 #ifdef MLX5_PMD_SOFT_COUNTERS
2020         /* Increment packets counter. */
2021         rxq->stats.ipackets += i;
2022 #endif
2023         return i;
2024 }
2025
2026 /**
2027  * Dummy DPDK callback for TX.
2028  *
2029  * This function is used to temporarily replace the real callback during
2030  * unsafe control operations on the queue, or in case of error.
2031  *
2032  * @param dpdk_txq
2033  *   Generic pointer to TX queue structure.
2034  * @param[in] pkts
2035  *   Packets to transmit.
2036  * @param pkts_n
2037  *   Number of packets in array.
2038  *
2039  * @return
2040  *   Number of packets successfully transmitted (<= pkts_n).
2041  */
2042 uint16_t
2043 removed_tx_burst(void *dpdk_txq __rte_unused,
2044                  struct rte_mbuf **pkts __rte_unused,
2045                  uint16_t pkts_n __rte_unused)
2046 {
2047         return 0;
2048 }
2049
2050 /**
2051  * Dummy DPDK callback for RX.
2052  *
2053  * This function is used to temporarily replace the real callback during
2054  * unsafe control operations on the queue, or in case of error.
2055  *
2056  * @param dpdk_rxq
2057  *   Generic pointer to RX queue structure.
2058  * @param[out] pkts
2059  *   Array to store received packets.
2060  * @param pkts_n
2061  *   Maximum number of packets in array.
2062  *
2063  * @return
2064  *   Number of packets successfully received (<= pkts_n).
2065  */
2066 uint16_t
2067 removed_rx_burst(void *dpdk_txq __rte_unused,
2068                  struct rte_mbuf **pkts __rte_unused,
2069                  uint16_t pkts_n __rte_unused)
2070 {
2071         return 0;
2072 }
2073
2074 /*
2075  * Vectorized Rx/Tx routines are not compiled in when required vector
2076  * instructions are not supported on a target architecture. The following null
2077  * stubs are needed for linkage when those are not included outside of this file
2078  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2079  */
2080
2081 uint16_t __attribute__((weak))
2082 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2083                       struct rte_mbuf **pkts __rte_unused,
2084                       uint16_t pkts_n __rte_unused)
2085 {
2086         return 0;
2087 }
2088
2089 uint16_t __attribute__((weak))
2090 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2091                   struct rte_mbuf **pkts __rte_unused,
2092                   uint16_t pkts_n __rte_unused)
2093 {
2094         return 0;
2095 }
2096
2097 uint16_t __attribute__((weak))
2098 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2099                   struct rte_mbuf **pkts __rte_unused,
2100                   uint16_t pkts_n __rte_unused)
2101 {
2102         return 0;
2103 }
2104
2105 int __attribute__((weak))
2106 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2107 {
2108         return -ENOTSUP;
2109 }
2110
2111 int __attribute__((weak))
2112 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2113 {
2114         return -ENOTSUP;
2115 }
2116
2117 int __attribute__((weak))
2118 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2119 {
2120         return -ENOTSUP;
2121 }
2122
2123 int __attribute__((weak))
2124 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2125 {
2126         return -ENOTSUP;
2127 }