drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5dv.h>
  46 #ifdef PEDANTIC
  47 #pragma GCC diagnostic error "-Wpedantic"
  48 #endif
  49
  50 #include <rte_mbuf.h>
  51 #include <rte_mempool.h>
  52 #include <rte_prefetch.h>
  53 #include <rte_common.h>
  54 #include <rte_branch_prediction.h>
  55 #include <rte_ether.h>
  56
  57 #include "mlx5.h"
  58 #include "mlx5_utils.h"
  59 #include "mlx5_rxtx.h"
  60 #include "mlx5_autoconf.h"
  61 #include "mlx5_defs.h"
  62 #include "mlx5_prm.h"
  63
  64 static __rte_always_inline uint32_t
  65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  66
  67 static __rte_always_inline int
  68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  69                  uint16_t cqe_cnt, uint32_t *rss_hash);
  70
  71 static __rte_always_inline uint32_t
  72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  73
  74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  75         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  76 };
  77
  78 /**
  79  * Build a table to translate Rx completion flags to packet type.
  80  *
  81  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  82  */
  83 void
  84 mlx5_set_ptype_table(void)
  85 {
  86         unsigned int i;
  87         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  88
  89         /* Last entry must not be overwritten, reserved for errored packet. */
  90         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  91                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  92         /*
  93          * The index to the array should have:
  94          * bit[1:0] = l3_hdr_type
  95          * bit[4:2] = l4_hdr_type
  96          * bit[5] = ip_frag
  97          * bit[6] = tunneled
  98          * bit[7] = outer_l3_type
  99          */
 100         /* L2 */
 101         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
 102         /* L3 */
 103         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         /* Fragmented */
 108         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_FRAG;
 110         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_FRAG;
 112         /* TCP */
 113         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         /* UDP */
 118         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_UDP;
 120         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_UDP;
 122         /* Repeat with outer_l3_type being set. Just in case. */
 123         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_NONFRAG;
 125         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_NONFRAG;
 127         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_FRAG;
 129         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_FRAG;
 131         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_TCP;
 135         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 138                      RTE_PTYPE_L4_UDP;
 139         /* Tunneled - L3 */
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         /* Tunneled - UDP */
 179         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_UDP;
 182         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_UDP;
 185         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_UDP;
 188         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_UDP;
 191 }
 192
 193 /**
 194  * Return the size of tailroom of WQ.
 195  *
 196  * @param txq
 197  *   Pointer to TX queue structure.
 198  * @param addr
 199  *   Pointer to tail of WQ.
 200  *
 201  * @return
 202  *   Size of tailroom.
 203  */
 204 static inline size_t
 205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 206 {
 207         size_t tailroom;
 208         tailroom = (uintptr_t)(txq->wqes) +
 209                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 210                    (uintptr_t)addr;
 211         return tailroom;
 212 }
 213
 214 /**
 215  * Copy data to tailroom of circular queue.
 216  *
 217  * @param dst
 218  *   Pointer to destination.
 219  * @param src
 220  *   Pointer to source.
 221  * @param n
 222  *   Number of bytes to copy.
 223  * @param base
 224  *   Pointer to head of queue.
 225  * @param tailroom
 226  *   Size of tailroom from dst.
 227  *
 228  * @return
 229  *   Pointer after copied data.
 230  */
 231 static inline void *
 232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 233                 void *base, size_t tailroom)
 234 {
 235         void *ret;
 236
 237         if (n > tailroom) {
 238                 rte_memcpy(dst, src, tailroom);
 239                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 240                            n - tailroom);
 241                 ret = (uint8_t *)base + n - tailroom;
 242         } else {
 243                 rte_memcpy(dst, src, n);
 244                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 245         }
 246         return ret;
 247 }
 248
 249 /**
 250  * DPDK callback to check the status of a tx descriptor.
 251  *
 252  * @param tx_queue
 253  *   The tx queue.
 254  * @param[in] offset
 255  *   The index of the descriptor in the ring.
 256  *
 257  * @return
 258  *   The status of the tx descriptor.
 259  */
 260 int
 261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 262 {
 263         struct mlx5_txq_data *txq = tx_queue;
 264         uint16_t used;
 265
 266         mlx5_tx_complete(txq);
 267         used = txq->elts_head - txq->elts_tail;
 268         if (offset < used)
 269                 return RTE_ETH_TX_DESC_FULL;
 270         return RTE_ETH_TX_DESC_DONE;
 271 }
 272
 273 /**
 274  * DPDK callback to check the status of a rx descriptor.
 275  *
 276  * @param rx_queue
 277  *   The rx queue.
 278  * @param[in] offset
 279  *   The index of the descriptor in the ring.
 280  *
 281  * @return
 282  *   The status of the tx descriptor.
 283  */
 284 int
 285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 286 {
 287         struct mlx5_rxq_data *rxq = rx_queue;
 288         struct rxq_zip *zip = &rxq->zip;
 289         volatile struct mlx5_cqe *cqe;
 290         const unsigned int cqe_n = (1 << rxq->cqe_n);
 291         const unsigned int cqe_cnt = cqe_n - 1;
 292         unsigned int cq_ci;
 293         unsigned int used;
 294
 295         /* if we are processing a compressed cqe */
 296         if (zip->ai) {
 297                 used = zip->cqe_cnt - zip->ca;
 298                 cq_ci = zip->cq_ci;
 299         } else {
 300                 used = 0;
 301                 cq_ci = rxq->cq_ci;
 302         }
 303         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 304         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 305                 int8_t op_own;
 306                 unsigned int n;
 307
 308                 op_own = cqe->op_own;
 309                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 310                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 311                 else
 312                         n = 1;
 313                 cq_ci += n;
 314                 used += n;
 315                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 316         }
 317         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 318         if (offset < used)
 319                 return RTE_ETH_RX_DESC_DONE;
 320         return RTE_ETH_RX_DESC_AVAIL;
 321 }
 322
 323 /**
 324  * DPDK callback for TX.
 325  *
 326  * @param dpdk_txq
 327  *   Generic pointer to TX queue structure.
 328  * @param[in] pkts
 329  *   Packets to transmit.
 330  * @param pkts_n
 331  *   Number of packets in array.
 332  *
 333  * @return
 334  *   Number of packets successfully transmitted (<= pkts_n).
 335  */
 336 uint16_t
 337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 338 {
 339         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 340         uint16_t elts_head = txq->elts_head;
 341         const uint16_t elts_n = 1 << txq->elts_n;
 342         const uint16_t elts_m = elts_n - 1;
 343         unsigned int i = 0;
 344         unsigned int j = 0;
 345         unsigned int k = 0;
 346         uint16_t max_elts;
 347         uint16_t max_wqe;
 348         unsigned int comp;
 349         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 350         unsigned int segs_n = 0;
 351         const unsigned int max_inline = txq->max_inline;
 352
 353         if (unlikely(!pkts_n))
 354                 return 0;
 355         /* Prefetch first packet cacheline. */
 356         rte_prefetch0(*pkts);
 357         /* Start processing. */
 358         mlx5_tx_complete(txq);
 359         max_elts = (elts_n - (elts_head - txq->elts_tail));
 360         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 361         if (unlikely(!max_wqe))
 362                 return 0;
 363         do {
 364                 struct rte_mbuf *buf = NULL;
 365                 uint8_t *raw;
 366                 volatile struct mlx5_wqe_v *wqe = NULL;
 367                 volatile rte_v128u32_t *dseg = NULL;
 368                 uint32_t length;
 369                 unsigned int ds = 0;
 370                 unsigned int sg = 0; /* counter of additional segs attached. */
 371                 uintptr_t addr;
 372                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 373                 uint16_t tso_header_sz = 0;
 374                 uint16_t ehdr;
 375                 uint8_t cs_flags;
 376                 uint64_t tso = 0;
 377                 uint16_t tso_segsz = 0;
 378 #ifdef MLX5_PMD_SOFT_COUNTERS
 379                 uint32_t total_length = 0;
 380 #endif
 381
 382                 /* first_seg */
 383                 buf = *pkts;
 384                 segs_n = buf->nb_segs;
 385                 /*
 386                  * Make sure there is enough room to store this packet and
 387                  * that one ring entry remains unused.
 388                  */
 389                 assert(segs_n);
 390                 if (max_elts < segs_n)
 391                         break;
 392                 max_elts -= segs_n;
 393                 --segs_n;
 394                 if (unlikely(--max_wqe == 0))
 395                         break;
 396                 wqe = (volatile struct mlx5_wqe_v *)
 397                         tx_mlx5_wqe(txq, txq->wqe_ci);
 398                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 399                 if (pkts_n - i > 1)
 400                         rte_prefetch0(*(pkts + 1));
 401                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 402                 length = DATA_LEN(buf);
 403                 ehdr = (((uint8_t *)addr)[1] << 8) |
 404                        ((uint8_t *)addr)[0];
 405 #ifdef MLX5_PMD_SOFT_COUNTERS
 406                 total_length = length;
 407 #endif
 408                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 409                         txq->stats.oerrors++;
 410                         break;
 411                 }
 412                 /* Update element. */
 413                 (*txq->elts)[elts_head & elts_m] = buf;
 414                 /* Prefetch next buffer data. */
 415                 if (pkts_n - i > 1)
 416                         rte_prefetch0(
 417                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 418                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 419                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 420                 /* Replace the Ethernet type by the VLAN if necessary. */
 421                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 422                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 423                                                          buf->vlan_tci);
 424                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 425
 426                         addr += 2;
 427                         length -= 2;
 428                         /* Copy Destination and source mac address. */
 429                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 430                         /* Copy VLAN. */
 431                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 432                         /* Copy missing two bytes to end the DSeg. */
 433                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 434                                ((uint8_t *)addr) + len, 2);
 435                         addr += len + 2;
 436                         length -= (len + 2);
 437                 } else {
 438                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 439                                MLX5_WQE_DWORD_SIZE);
 440                         length -= pkt_inline_sz;
 441                         addr += pkt_inline_sz;
 442                 }
 443                 raw += MLX5_WQE_DWORD_SIZE;
 444                 if (txq->tso_en) {
 445                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 446                         if (tso) {
 447                                 uintptr_t end = (uintptr_t)
 448                                                 (((uintptr_t)txq->wqes) +
 449                                                 (1 << txq->wqe_n) *
 450                                                 MLX5_WQE_SIZE);
 451                                 unsigned int copy_b;
 452                                 uint8_t vlan_sz = (buf->ol_flags &
 453                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 454                                 const uint64_t is_tunneled =
 455                                                         buf->ol_flags &
 456                                                         (PKT_TX_TUNNEL_GRE |
 457                                                          PKT_TX_TUNNEL_VXLAN);
 458
 459                                 tso_header_sz = buf->l2_len + vlan_sz +
 460                                                 buf->l3_len + buf->l4_len;
 461                                 tso_segsz = buf->tso_segsz;
 462                                 if (unlikely(tso_segsz == 0)) {
 463                                         txq->stats.oerrors++;
 464                                         break;
 465                                 }
 466                                 if (is_tunneled && txq->tunnel_en) {
 467                                         tso_header_sz += buf->outer_l2_len +
 468                                                          buf->outer_l3_len;
 469                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 470                                 } else {
 471                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 472                                 }
 473                                 if (unlikely(tso_header_sz >
 474                                              MLX5_MAX_TSO_HEADER)) {
 475                                         txq->stats.oerrors++;
 476                                         break;
 477                                 }
 478                                 copy_b = tso_header_sz - pkt_inline_sz;
 479                                 /* First seg must contain all headers. */
 480                                 assert(copy_b <= length);
 481                                 if (copy_b &&
 482                                    ((end - (uintptr_t)raw) > copy_b)) {
 483                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 484                                                       1 + 3) / 4;
 485
 486                                         if (unlikely(max_wqe < n))
 487                                                 break;
 488                                         max_wqe -= n;
 489                                         rte_memcpy((void *)raw,
 490                                                    (void *)addr, copy_b);
 491                                         addr += copy_b;
 492                                         length -= copy_b;
 493                                         /* Include padding for TSO header. */
 494                                         copy_b = MLX5_WQE_DS(copy_b) *
 495                                                  MLX5_WQE_DWORD_SIZE;
 496                                         pkt_inline_sz += copy_b;
 497                                         raw += copy_b;
 498                                 } else {
 499                                         /* NOP WQE. */
 500                                         wqe->ctrl = (rte_v128u32_t){
 501                                                      rte_cpu_to_be_32(
 502                                                         txq->wqe_ci << 8),
 503                                                      rte_cpu_to_be_32(
 504                                                         txq->qp_num_8s | 1),
 505                                                      0,
 506                                                      0,
 507                                         };
 508                                         ds = 1;
 509 #ifdef MLX5_PMD_SOFT_COUNTERS
 510                                         total_length = 0;
 511 #endif
 512                                         k++;
 513                                         goto next_wqe;
 514                                 }
 515                         }
 516                 }
 517                 /* Inline if enough room. */
 518                 if (max_inline || tso) {
 519                         uint32_t inl;
 520                         uintptr_t end = (uintptr_t)
 521                                 (((uintptr_t)txq->wqes) +
 522                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 523                         unsigned int inline_room = max_inline *
 524                                                    RTE_CACHE_LINE_SIZE -
 525                                                    (pkt_inline_sz - 2) -
 526                                                    !!tso * sizeof(inl);
 527                         uintptr_t addr_end = (addr + inline_room) &
 528                                              ~(RTE_CACHE_LINE_SIZE - 1);
 529                         unsigned int copy_b = (addr_end > addr) ?
 530                                 RTE_MIN((addr_end - addr), length) :
 531                                 0;
 532
 533                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 534                                 /*
 535                                  * One Dseg remains in the current WQE.  To
 536                                  * keep the computation positive, it is
 537                                  * removed after the bytes to Dseg conversion.
 538                                  */
 539                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 540
 541                                 if (unlikely(max_wqe < n))
 542                                         break;
 543                                 max_wqe -= n;
 544                                 if (tso) {
 545                                         inl = rte_cpu_to_be_32(copy_b |
 546                                                                MLX5_INLINE_SEG);
 547                                         rte_memcpy((void *)raw,
 548                                                    (void *)&inl, sizeof(inl));
 549                                         raw += sizeof(inl);
 550                                         pkt_inline_sz += sizeof(inl);
 551                                 }
 552                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 553                                 addr += copy_b;
 554                                 length -= copy_b;
 555                                 pkt_inline_sz += copy_b;
 556                         }
 557                         /*
 558                          * 2 DWORDs consumed by the WQE header + ETH segment +
 559                          * the size of the inline part of the packet.
 560                          */
 561                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 562                         if (length > 0) {
 563                                 if (ds % (MLX5_WQE_SIZE /
 564                                           MLX5_WQE_DWORD_SIZE) == 0) {
 565                                         if (unlikely(--max_wqe == 0))
 566                                                 break;
 567                                         dseg = (volatile rte_v128u32_t *)
 568                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 569                                                            ds / 4);
 570                                 } else {
 571                                         dseg = (volatile rte_v128u32_t *)
 572                                                 ((uintptr_t)wqe +
 573                                                  (ds * MLX5_WQE_DWORD_SIZE));
 574                                 }
 575                                 goto use_dseg;
 576                         } else if (!segs_n) {
 577                                 goto next_pkt;
 578                         } else {
 579                                 /* dseg will be advance as part of next_seg */
 580                                 dseg = (volatile rte_v128u32_t *)
 581                                         ((uintptr_t)wqe +
 582                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 583                                 goto next_seg;
 584                         }
 585                 } else {
 586                         /*
 587                          * No inline has been done in the packet, only the
 588                          * Ethernet Header as been stored.
 589                          */
 590                         dseg = (volatile rte_v128u32_t *)
 591                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 592                         ds = 3;
 593 use_dseg:
 594                         /* Add the remaining packet as a simple ds. */
 595                         addr = rte_cpu_to_be_64(addr);
 596                         *dseg = (rte_v128u32_t){
 597                                 rte_cpu_to_be_32(length),
 598                                 mlx5_tx_mb2mr(txq, buf),
 599                                 addr,
 600                                 addr >> 32,
 601                         };
 602                         ++ds;
 603                         if (!segs_n)
 604                                 goto next_pkt;
 605                 }
 606 next_seg:
 607                 assert(buf);
 608                 assert(ds);
 609                 assert(wqe);
 610                 /*
 611                  * Spill on next WQE when the current one does not have
 612                  * enough room left. Size of WQE must a be a multiple
 613                  * of data segment size.
 614                  */
 615                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 616                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 617                         if (unlikely(--max_wqe == 0))
 618                                 break;
 619                         dseg = (volatile rte_v128u32_t *)
 620                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 621                         rte_prefetch0(tx_mlx5_wqe(txq,
 622                                                   txq->wqe_ci + ds / 4 + 1));
 623                 } else {
 624                         ++dseg;
 625                 }
 626                 ++ds;
 627                 buf = buf->next;
 628                 assert(buf);
 629                 length = DATA_LEN(buf);
 630 #ifdef MLX5_PMD_SOFT_COUNTERS
 631                 total_length += length;
 632 #endif
 633                 /* Store segment information. */
 634                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 635                 *dseg = (rte_v128u32_t){
 636                         rte_cpu_to_be_32(length),
 637                         mlx5_tx_mb2mr(txq, buf),
 638                         addr,
 639                         addr >> 32,
 640                 };
 641                 (*txq->elts)[++elts_head & elts_m] = buf;
 642                 ++sg;
 643                 /* Advance counter only if all segs are successfully posted. */
 644                 if (sg < segs_n)
 645                         goto next_seg;
 646                 else
 647                         j += sg;
 648 next_pkt:
 649                 if (ds > MLX5_DSEG_MAX) {
 650                         txq->stats.oerrors++;
 651                         break;
 652                 }
 653                 ++elts_head;
 654                 ++pkts;
 655                 ++i;
 656                 /* Initialize known and common part of the WQE structure. */
 657                 if (tso) {
 658                         wqe->ctrl = (rte_v128u32_t){
 659                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 660                                                  MLX5_OPCODE_TSO),
 661                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 662                                 0,
 663                                 0,
 664                         };
 665                         wqe->eseg = (rte_v128u32_t){
 666                                 0,
 667                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 668                                 0,
 669                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 670                         };
 671                 } else {
 672                         wqe->ctrl = (rte_v128u32_t){
 673                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 674                                                  MLX5_OPCODE_SEND),
 675                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 676                                 0,
 677                                 0,
 678                         };
 679                         wqe->eseg = (rte_v128u32_t){
 680                                 0,
 681                                 cs_flags,
 682                                 0,
 683                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 684                         };
 685                 }
 686 next_wqe:
 687                 txq->wqe_ci += (ds + 3) / 4;
 688                 /* Save the last successful WQE for completion request */
 689                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 690 #ifdef MLX5_PMD_SOFT_COUNTERS
 691                 /* Increment sent bytes counter. */
 692                 txq->stats.obytes += total_length;
 693 #endif
 694         } while (i < pkts_n);
 695         /* Take a shortcut if nothing must be sent. */
 696         if (unlikely((i + k) == 0))
 697                 return 0;
 698         txq->elts_head += (i + j);
 699         /* Check whether completion threshold has been reached. */
 700         comp = txq->elts_comp + i + j + k;
 701         if (comp >= MLX5_TX_COMP_THRESH) {
 702                 /* Request completion on last WQE. */
 703                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 704                 /* Save elts_head in unused "immediate" field of WQE. */
 705                 last_wqe->ctrl3 = txq->elts_head;
 706                 txq->elts_comp = 0;
 707         } else {
 708                 txq->elts_comp = comp;
 709         }
 710 #ifdef MLX5_PMD_SOFT_COUNTERS
 711         /* Increment sent packets counter. */
 712         txq->stats.opackets += i;
 713 #endif
 714         /* Ring QP doorbell. */
 715         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 716         return i;
 717 }
 718
 719 /**
 720  * Open a MPW session.
 721  *
 722  * @param txq
 723  *   Pointer to TX queue structure.
 724  * @param mpw
 725  *   Pointer to MPW session structure.
 726  * @param length
 727  *   Packet length.
 728  */
 729 static inline void
 730 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 731 {
 732         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 733         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 734                 (volatile struct mlx5_wqe_data_seg (*)[])
 735                 tx_mlx5_wqe(txq, idx + 1);
 736
 737         mpw->state = MLX5_MPW_STATE_OPENED;
 738         mpw->pkts_n = 0;
 739         mpw->len = length;
 740         mpw->total_len = 0;
 741         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 742         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 743         mpw->wqe->eseg.inline_hdr_sz = 0;
 744         mpw->wqe->eseg.rsvd0 = 0;
 745         mpw->wqe->eseg.rsvd1 = 0;
 746         mpw->wqe->eseg.rsvd2 = 0;
 747         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 748                                              (txq->wqe_ci << 8) |
 749                                              MLX5_OPCODE_TSO);
 750         mpw->wqe->ctrl[2] = 0;
 751         mpw->wqe->ctrl[3] = 0;
 752         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 753                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 754         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 755                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 756         mpw->data.dseg[2] = &(*dseg)[0];
 757         mpw->data.dseg[3] = &(*dseg)[1];
 758         mpw->data.dseg[4] = &(*dseg)[2];
 759 }
 760
 761 /**
 762  * Close a MPW session.
 763  *
 764  * @param txq
 765  *   Pointer to TX queue structure.
 766  * @param mpw
 767  *   Pointer to MPW session structure.
 768  */
 769 static inline void
 770 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 771 {
 772         unsigned int num = mpw->pkts_n;
 773
 774         /*
 775          * Store size in multiple of 16 bytes. Control and Ethernet segments
 776          * count as 2.
 777          */
 778         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 779         mpw->state = MLX5_MPW_STATE_CLOSED;
 780         if (num < 3)
 781                 ++txq->wqe_ci;
 782         else
 783                 txq->wqe_ci += 2;
 784         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 785         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 786 }
 787
 788 /**
 789  * DPDK callback for TX with MPW support.
 790  *
 791  * @param dpdk_txq
 792  *   Generic pointer to TX queue structure.
 793  * @param[in] pkts
 794  *   Packets to transmit.
 795  * @param pkts_n
 796  *   Number of packets in array.
 797  *
 798  * @return
 799  *   Number of packets successfully transmitted (<= pkts_n).
 800  */
 801 uint16_t
 802 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 803 {
 804         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 805         uint16_t elts_head = txq->elts_head;
 806         const uint16_t elts_n = 1 << txq->elts_n;
 807         const uint16_t elts_m = elts_n - 1;
 808         unsigned int i = 0;
 809         unsigned int j = 0;
 810         uint16_t max_elts;
 811         uint16_t max_wqe;
 812         unsigned int comp;
 813         struct mlx5_mpw mpw = {
 814                 .state = MLX5_MPW_STATE_CLOSED,
 815         };
 816
 817         if (unlikely(!pkts_n))
 818                 return 0;
 819         /* Prefetch first packet cacheline. */
 820         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 821         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 822         /* Start processing. */
 823         mlx5_tx_complete(txq);
 824         max_elts = (elts_n - (elts_head - txq->elts_tail));
 825         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 826         if (unlikely(!max_wqe))
 827                 return 0;
 828         do {
 829                 struct rte_mbuf *buf = *(pkts++);
 830                 uint32_t length;
 831                 unsigned int segs_n = buf->nb_segs;
 832                 uint32_t cs_flags;
 833
 834                 /*
 835                  * Make sure there is enough room to store this packet and
 836                  * that one ring entry remains unused.
 837                  */
 838                 assert(segs_n);
 839                 if (max_elts < segs_n)
 840                         break;
 841                 /* Do not bother with large packets MPW cannot handle. */
 842                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 843                         txq->stats.oerrors++;
 844                         break;
 845                 }
 846                 max_elts -= segs_n;
 847                 --pkts_n;
 848                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 849                 /* Retrieve packet information. */
 850                 length = PKT_LEN(buf);
 851                 assert(length);
 852                 /* Start new session if packet differs. */
 853                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 854                     ((mpw.len != length) ||
 855                      (segs_n != 1) ||
 856                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 857                         mlx5_mpw_close(txq, &mpw);
 858                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 859                         /*
 860                          * Multi-Packet WQE consumes at most two WQE.
 861                          * mlx5_mpw_new() expects to be able to use such
 862                          * resources.
 863                          */
 864                         if (unlikely(max_wqe < 2))
 865                                 break;
 866                         max_wqe -= 2;
 867                         mlx5_mpw_new(txq, &mpw, length);
 868                         mpw.wqe->eseg.cs_flags = cs_flags;
 869                 }
 870                 /* Multi-segment packets must be alone in their MPW. */
 871                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 872 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 873                 length = 0;
 874 #endif
 875                 do {
 876                         volatile struct mlx5_wqe_data_seg *dseg;
 877                         uintptr_t addr;
 878
 879                         assert(buf);
 880                         (*txq->elts)[elts_head++ & elts_m] = buf;
 881                         dseg = mpw.data.dseg[mpw.pkts_n];
 882                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 883                         *dseg = (struct mlx5_wqe_data_seg){
 884                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 885                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 886                                 .addr = rte_cpu_to_be_64(addr),
 887                         };
 888 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 889                         length += DATA_LEN(buf);
 890 #endif
 891                         buf = buf->next;
 892                         ++mpw.pkts_n;
 893                         ++j;
 894                 } while (--segs_n);
 895                 assert(length == mpw.len);
 896                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 897                         mlx5_mpw_close(txq, &mpw);
 898 #ifdef MLX5_PMD_SOFT_COUNTERS
 899                 /* Increment sent bytes counter. */
 900                 txq->stats.obytes += length;
 901 #endif
 902                 ++i;
 903         } while (pkts_n);
 904         /* Take a shortcut if nothing must be sent. */
 905         if (unlikely(i == 0))
 906                 return 0;
 907         /* Check whether completion threshold has been reached. */
 908         /* "j" includes both packets and segments. */
 909         comp = txq->elts_comp + j;
 910         if (comp >= MLX5_TX_COMP_THRESH) {
 911                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 912
 913                 /* Request completion on last WQE. */
 914                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 915                 /* Save elts_head in unused "immediate" field of WQE. */
 916                 wqe->ctrl[3] = elts_head;
 917                 txq->elts_comp = 0;
 918         } else {
 919                 txq->elts_comp = comp;
 920         }
 921 #ifdef MLX5_PMD_SOFT_COUNTERS
 922         /* Increment sent packets counter. */
 923         txq->stats.opackets += i;
 924 #endif
 925         /* Ring QP doorbell. */
 926         if (mpw.state == MLX5_MPW_STATE_OPENED)
 927                 mlx5_mpw_close(txq, &mpw);
 928         mlx5_tx_dbrec(txq, mpw.wqe);
 929         txq->elts_head = elts_head;
 930         return i;
 931 }
 932
 933 /**
 934  * Open a MPW inline session.
 935  *
 936  * @param txq
 937  *   Pointer to TX queue structure.
 938  * @param mpw
 939  *   Pointer to MPW session structure.
 940  * @param length
 941  *   Packet length.
 942  */
 943 static inline void
 944 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 945                     uint32_t length)
 946 {
 947         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 948         struct mlx5_wqe_inl_small *inl;
 949
 950         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 951         mpw->pkts_n = 0;
 952         mpw->len = length;
 953         mpw->total_len = 0;
 954         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 955         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 956                                              (txq->wqe_ci << 8) |
 957                                              MLX5_OPCODE_TSO);
 958         mpw->wqe->ctrl[2] = 0;
 959         mpw->wqe->ctrl[3] = 0;
 960         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 961         mpw->wqe->eseg.inline_hdr_sz = 0;
 962         mpw->wqe->eseg.cs_flags = 0;
 963         mpw->wqe->eseg.rsvd0 = 0;
 964         mpw->wqe->eseg.rsvd1 = 0;
 965         mpw->wqe->eseg.rsvd2 = 0;
 966         inl = (struct mlx5_wqe_inl_small *)
 967                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
 968         mpw->data.raw = (uint8_t *)&inl->raw;
 969 }
 970
 971 /**
 972  * Close a MPW inline session.
 973  *
 974  * @param txq
 975  *   Pointer to TX queue structure.
 976  * @param mpw
 977  *   Pointer to MPW session structure.
 978  */
 979 static inline void
 980 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 981 {
 982         unsigned int size;
 983         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
 984                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 985
 986         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
 987         /*
 988          * Store size in multiple of 16 bytes. Control and Ethernet segments
 989          * count as 2.
 990          */
 991         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
 992                                              MLX5_WQE_DS(size));
 993         mpw->state = MLX5_MPW_STATE_CLOSED;
 994         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
 995         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
 996 }
 997
 998 /**
 999  * DPDK callback for TX with MPW inline support.
1000  *
1001  * @param dpdk_txq
1002  *   Generic pointer to TX queue structure.
1003  * @param[in] pkts
1004  *   Packets to transmit.
1005  * @param pkts_n
1006  *   Number of packets in array.
1007  *
1008  * @return
1009  *   Number of packets successfully transmitted (<= pkts_n).
1010  */
1011 uint16_t
1012 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1013                          uint16_t pkts_n)
1014 {
1015         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1016         uint16_t elts_head = txq->elts_head;
1017         const uint16_t elts_n = 1 << txq->elts_n;
1018         const uint16_t elts_m = elts_n - 1;
1019         unsigned int i = 0;
1020         unsigned int j = 0;
1021         uint16_t max_elts;
1022         uint16_t max_wqe;
1023         unsigned int comp;
1024         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1025         struct mlx5_mpw mpw = {
1026                 .state = MLX5_MPW_STATE_CLOSED,
1027         };
1028         /*
1029          * Compute the maximum number of WQE which can be consumed by inline
1030          * code.
1031          * - 2 DSEG for:
1032          *   - 1 control segment,
1033          *   - 1 Ethernet segment,
1034          * - N Dseg from the inline request.
1035          */
1036         const unsigned int wqe_inl_n =
1037                 ((2 * MLX5_WQE_DWORD_SIZE +
1038                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1039                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1040
1041         if (unlikely(!pkts_n))
1042                 return 0;
1043         /* Prefetch first packet cacheline. */
1044         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1045         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1046         /* Start processing. */
1047         mlx5_tx_complete(txq);
1048         max_elts = (elts_n - (elts_head - txq->elts_tail));
1049         do {
1050                 struct rte_mbuf *buf = *(pkts++);
1051                 uintptr_t addr;
1052                 uint32_t length;
1053                 unsigned int segs_n = buf->nb_segs;
1054                 uint8_t cs_flags;
1055
1056                 /*
1057                  * Make sure there is enough room to store this packet and
1058                  * that one ring entry remains unused.
1059                  */
1060                 assert(segs_n);
1061                 if (max_elts < segs_n)
1062                         break;
1063                 /* Do not bother with large packets MPW cannot handle. */
1064                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1065                         txq->stats.oerrors++;
1066                         break;
1067                 }
1068                 max_elts -= segs_n;
1069                 --pkts_n;
1070                 /*
1071                  * Compute max_wqe in case less WQE were consumed in previous
1072                  * iteration.
1073                  */
1074                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1075                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1076                 /* Retrieve packet information. */
1077                 length = PKT_LEN(buf);
1078                 /* Start new session if packet differs. */
1079                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1080                         if ((mpw.len != length) ||
1081                             (segs_n != 1) ||
1082                             (mpw.wqe->eseg.cs_flags != cs_flags))
1083                                 mlx5_mpw_close(txq, &mpw);
1084                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1085                         if ((mpw.len != length) ||
1086                             (segs_n != 1) ||
1087                             (length > inline_room) ||
1088                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1089                                 mlx5_mpw_inline_close(txq, &mpw);
1090                                 inline_room =
1091                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1092                         }
1093                 }
1094                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1095                         if ((segs_n != 1) ||
1096                             (length > inline_room)) {
1097                                 /*
1098                                  * Multi-Packet WQE consumes at most two WQE.
1099                                  * mlx5_mpw_new() expects to be able to use
1100                                  * such resources.
1101                                  */
1102                                 if (unlikely(max_wqe < 2))
1103                                         break;
1104                                 max_wqe -= 2;
1105                                 mlx5_mpw_new(txq, &mpw, length);
1106                                 mpw.wqe->eseg.cs_flags = cs_flags;
1107                         } else {
1108                                 if (unlikely(max_wqe < wqe_inl_n))
1109                                         break;
1110                                 max_wqe -= wqe_inl_n;
1111                                 mlx5_mpw_inline_new(txq, &mpw, length);
1112                                 mpw.wqe->eseg.cs_flags = cs_flags;
1113                         }
1114                 }
1115                 /* Multi-segment packets must be alone in their MPW. */
1116                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1117                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1118                         assert(inline_room ==
1119                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1120 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1121                         length = 0;
1122 #endif
1123                         do {
1124                                 volatile struct mlx5_wqe_data_seg *dseg;
1125
1126                                 assert(buf);
1127                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1128                                 dseg = mpw.data.dseg[mpw.pkts_n];
1129                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1130                                 *dseg = (struct mlx5_wqe_data_seg){
1131                                         .byte_count =
1132                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1133                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1134                                         .addr = rte_cpu_to_be_64(addr),
1135                                 };
1136 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1137                                 length += DATA_LEN(buf);
1138 #endif
1139                                 buf = buf->next;
1140                                 ++mpw.pkts_n;
1141                                 ++j;
1142                         } while (--segs_n);
1143                         assert(length == mpw.len);
1144                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1145                                 mlx5_mpw_close(txq, &mpw);
1146                 } else {
1147                         unsigned int max;
1148
1149                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1150                         assert(length <= inline_room);
1151                         assert(length == DATA_LEN(buf));
1152                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1153                         (*txq->elts)[elts_head++ & elts_m] = buf;
1154                         /* Maximum number of bytes before wrapping. */
1155                         max = ((((uintptr_t)(txq->wqes)) +
1156                                 (1 << txq->wqe_n) *
1157                                 MLX5_WQE_SIZE) -
1158                                (uintptr_t)mpw.data.raw);
1159                         if (length > max) {
1160                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1161                                            (void *)addr,
1162                                            max);
1163                                 mpw.data.raw = (volatile void *)txq->wqes;
1164                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1165                                            (void *)(addr + max),
1166                                            length - max);
1167                                 mpw.data.raw += length - max;
1168                         } else {
1169                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1170                                            (void *)addr,
1171                                            length);
1172
1173                                 if (length == max)
1174                                         mpw.data.raw =
1175                                                 (volatile void *)txq->wqes;
1176                                 else
1177                                         mpw.data.raw += length;
1178                         }
1179                         ++mpw.pkts_n;
1180                         mpw.total_len += length;
1181                         ++j;
1182                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1183                                 mlx5_mpw_inline_close(txq, &mpw);
1184                                 inline_room =
1185                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1186                         } else {
1187                                 inline_room -= length;
1188                         }
1189                 }
1190 #ifdef MLX5_PMD_SOFT_COUNTERS
1191                 /* Increment sent bytes counter. */
1192                 txq->stats.obytes += length;
1193 #endif
1194                 ++i;
1195         } while (pkts_n);
1196         /* Take a shortcut if nothing must be sent. */
1197         if (unlikely(i == 0))
1198                 return 0;
1199         /* Check whether completion threshold has been reached. */
1200         /* "j" includes both packets and segments. */
1201         comp = txq->elts_comp + j;
1202         if (comp >= MLX5_TX_COMP_THRESH) {
1203                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1204
1205                 /* Request completion on last WQE. */
1206                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1207                 /* Save elts_head in unused "immediate" field of WQE. */
1208                 wqe->ctrl[3] = elts_head;
1209                 txq->elts_comp = 0;
1210         } else {
1211                 txq->elts_comp = comp;
1212         }
1213 #ifdef MLX5_PMD_SOFT_COUNTERS
1214         /* Increment sent packets counter. */
1215         txq->stats.opackets += i;
1216 #endif
1217         /* Ring QP doorbell. */
1218         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1219                 mlx5_mpw_inline_close(txq, &mpw);
1220         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1221                 mlx5_mpw_close(txq, &mpw);
1222         mlx5_tx_dbrec(txq, mpw.wqe);
1223         txq->elts_head = elts_head;
1224         return i;
1225 }
1226
1227 /**
1228  * Open an Enhanced MPW session.
1229  *
1230  * @param txq
1231  *   Pointer to TX queue structure.
1232  * @param mpw
1233  *   Pointer to MPW session structure.
1234  * @param length
1235  *   Packet length.
1236  */
1237 static inline void
1238 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1239 {
1240         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1241
1242         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1243         mpw->pkts_n = 0;
1244         mpw->total_len = sizeof(struct mlx5_wqe);
1245         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1246         mpw->wqe->ctrl[0] =
1247                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1248                                  (txq->wqe_ci << 8) |
1249                                  MLX5_OPCODE_ENHANCED_MPSW);
1250         mpw->wqe->ctrl[2] = 0;
1251         mpw->wqe->ctrl[3] = 0;
1252         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1253         if (unlikely(padding)) {
1254                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1255
1256                 /* Pad the first 2 DWORDs with zero-length inline header. */
1257                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1258                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1259                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1260                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1261                 /* Start from the next WQEBB. */
1262                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1263         } else {
1264                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1265         }
1266 }
1267
1268 /**
1269  * Close an Enhanced MPW session.
1270  *
1271  * @param txq
1272  *   Pointer to TX queue structure.
1273  * @param mpw
1274  *   Pointer to MPW session structure.
1275  *
1276  * @return
1277  *   Number of consumed WQEs.
1278  */
1279 static inline uint16_t
1280 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1281 {
1282         uint16_t ret;
1283
1284         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1285          * count as 2.
1286          */
1287         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1288                                              MLX5_WQE_DS(mpw->total_len));
1289         mpw->state = MLX5_MPW_STATE_CLOSED;
1290         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1291         txq->wqe_ci += ret;
1292         return ret;
1293 }
1294
1295 /**
1296  * DPDK callback for TX with Enhanced MPW support.
1297  *
1298  * @param dpdk_txq
1299  *   Generic pointer to TX queue structure.
1300  * @param[in] pkts
1301  *   Packets to transmit.
1302  * @param pkts_n
1303  *   Number of packets in array.
1304  *
1305  * @return
1306  *   Number of packets successfully transmitted (<= pkts_n).
1307  */
1308 uint16_t
1309 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1310 {
1311         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1312         uint16_t elts_head = txq->elts_head;
1313         const uint16_t elts_n = 1 << txq->elts_n;
1314         const uint16_t elts_m = elts_n - 1;
1315         unsigned int i = 0;
1316         unsigned int j = 0;
1317         uint16_t max_elts;
1318         uint16_t max_wqe;
1319         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1320         unsigned int mpw_room = 0;
1321         unsigned int inl_pad = 0;
1322         uint32_t inl_hdr;
1323         struct mlx5_mpw mpw = {
1324                 .state = MLX5_MPW_STATE_CLOSED,
1325         };
1326
1327         if (unlikely(!pkts_n))
1328                 return 0;
1329         /* Start processing. */
1330         mlx5_tx_complete(txq);
1331         max_elts = (elts_n - (elts_head - txq->elts_tail));
1332         /* A CQE slot must always be available. */
1333         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1334         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1335         if (unlikely(!max_wqe))
1336                 return 0;
1337         do {
1338                 struct rte_mbuf *buf = *(pkts++);
1339                 uintptr_t addr;
1340                 unsigned int n;
1341                 unsigned int do_inline = 0; /* Whether inline is possible. */
1342                 uint32_t length;
1343                 unsigned int segs_n = buf->nb_segs;
1344                 uint8_t cs_flags;
1345
1346                 /*
1347                  * Make sure there is enough room to store this packet and
1348                  * that one ring entry remains unused.
1349                  */
1350                 assert(segs_n);
1351                 if (max_elts - j < segs_n)
1352                         break;
1353                 /* Do not bother with large packets MPW cannot handle. */
1354                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1355                         txq->stats.oerrors++;
1356                         break;
1357                 }
1358                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1359                 /* Retrieve packet information. */
1360                 length = PKT_LEN(buf);
1361                 /* Start new session if:
1362                  * - multi-segment packet
1363                  * - no space left even for a dseg
1364                  * - next packet can be inlined with a new WQE
1365                  * - cs_flag differs
1366                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1367                  * segmented packet.
1368                  */
1369                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1370                         if ((segs_n != 1) ||
1371                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1372                               mpw_room) ||
1373                             (length <= txq->inline_max_packet_sz &&
1374                              inl_pad + sizeof(inl_hdr) + length >
1375                               mpw_room) ||
1376                             (mpw.wqe->eseg.cs_flags != cs_flags))
1377                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1378                 }
1379                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1380                         if (unlikely(segs_n != 1)) {
1381                                 /* Fall back to legacy MPW.
1382                                  * A MPW session consumes 2 WQEs at most to
1383                                  * include MLX5_MPW_DSEG_MAX pointers.
1384                                  */
1385                                 if (unlikely(max_wqe < 2))
1386                                         break;
1387                                 mlx5_mpw_new(txq, &mpw, length);
1388                         } else {
1389                                 /* In Enhanced MPW, inline as much as the budget
1390                                  * is allowed. The remaining space is to be
1391                                  * filled with dsegs. If the title WQEBB isn't
1392                                  * padded, it will have 2 dsegs there.
1393                                  */
1394                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1395                                             (max_inline ? max_inline :
1396                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1397                                             MLX5_WQE_SIZE);
1398                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1399                                               mpw_room))
1400                                         break;
1401                                 /* Don't pad the title WQEBB to not waste WQ. */
1402                                 mlx5_empw_new(txq, &mpw, 0);
1403                                 mpw_room -= mpw.total_len;
1404                                 inl_pad = 0;
1405                                 do_inline =
1406                                         length <= txq->inline_max_packet_sz &&
1407                                         sizeof(inl_hdr) + length <= mpw_room &&
1408                                         !txq->mpw_hdr_dseg;
1409                         }
1410                         mpw.wqe->eseg.cs_flags = cs_flags;
1411                 } else {
1412                         /* Evaluate whether the next packet can be inlined.
1413                          * Inlininig is possible when:
1414                          * - length is less than configured value
1415                          * - length fits for remaining space
1416                          * - not required to fill the title WQEBB with dsegs
1417                          */
1418                         do_inline =
1419                                 length <= txq->inline_max_packet_sz &&
1420                                 inl_pad + sizeof(inl_hdr) + length <=
1421                                  mpw_room &&
1422                                 (!txq->mpw_hdr_dseg ||
1423                                  mpw.total_len >= MLX5_WQE_SIZE);
1424                 }
1425                 /* Multi-segment packets must be alone in their MPW. */
1426                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1427                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1428 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1429                         length = 0;
1430 #endif
1431                         do {
1432                                 volatile struct mlx5_wqe_data_seg *dseg;
1433
1434                                 assert(buf);
1435                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1436                                 dseg = mpw.data.dseg[mpw.pkts_n];
1437                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1438                                 *dseg = (struct mlx5_wqe_data_seg){
1439                                         .byte_count = rte_cpu_to_be_32(
1440                                                                 DATA_LEN(buf)),
1441                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1442                                         .addr = rte_cpu_to_be_64(addr),
1443                                 };
1444 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1445                                 length += DATA_LEN(buf);
1446 #endif
1447                                 buf = buf->next;
1448                                 ++j;
1449                                 ++mpw.pkts_n;
1450                         } while (--segs_n);
1451                         /* A multi-segmented packet takes one MPW session.
1452                          * TODO: Pack more multi-segmented packets if possible.
1453                          */
1454                         mlx5_mpw_close(txq, &mpw);
1455                         if (mpw.pkts_n < 3)
1456                                 max_wqe--;
1457                         else
1458                                 max_wqe -= 2;
1459                 } else if (do_inline) {
1460                         /* Inline packet into WQE. */
1461                         unsigned int max;
1462
1463                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1464                         assert(length == DATA_LEN(buf));
1465                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1466                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1467                         mpw.data.raw = (volatile void *)
1468                                 ((uintptr_t)mpw.data.raw + inl_pad);
1469                         max = tx_mlx5_wq_tailroom(txq,
1470                                         (void *)(uintptr_t)mpw.data.raw);
1471                         /* Copy inline header. */
1472                         mpw.data.raw = (volatile void *)
1473                                 mlx5_copy_to_wq(
1474                                           (void *)(uintptr_t)mpw.data.raw,
1475                                           &inl_hdr,
1476                                           sizeof(inl_hdr),
1477                                           (void *)(uintptr_t)txq->wqes,
1478                                           max);
1479                         max = tx_mlx5_wq_tailroom(txq,
1480                                         (void *)(uintptr_t)mpw.data.raw);
1481                         /* Copy packet data. */
1482                         mpw.data.raw = (volatile void *)
1483                                 mlx5_copy_to_wq(
1484                                           (void *)(uintptr_t)mpw.data.raw,
1485                                           (void *)addr,
1486                                           length,
1487                                           (void *)(uintptr_t)txq->wqes,
1488                                           max);
1489                         ++mpw.pkts_n;
1490                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1491                         /* No need to get completion as the entire packet is
1492                          * copied to WQ. Free the buf right away.
1493                          */
1494                         rte_pktmbuf_free_seg(buf);
1495                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1496                         /* Add pad in the next packet if any. */
1497                         inl_pad = (((uintptr_t)mpw.data.raw +
1498                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1499                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1500                                   (uintptr_t)mpw.data.raw;
1501                 } else {
1502                         /* No inline. Load a dseg of packet pointer. */
1503                         volatile rte_v128u32_t *dseg;
1504
1505                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1506                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1507                         assert(length == DATA_LEN(buf));
1508                         if (!tx_mlx5_wq_tailroom(txq,
1509                                         (void *)((uintptr_t)mpw.data.raw
1510                                                 + inl_pad)))
1511                                 dseg = (volatile void *)txq->wqes;
1512                         else
1513                                 dseg = (volatile void *)
1514                                         ((uintptr_t)mpw.data.raw +
1515                                          inl_pad);
1516                         (*txq->elts)[elts_head++ & elts_m] = buf;
1517                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1518                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1519                                 rte_prefetch2((void *)(addr +
1520                                                 n * RTE_CACHE_LINE_SIZE));
1521                         addr = rte_cpu_to_be_64(addr);
1522                         *dseg = (rte_v128u32_t) {
1523                                 rte_cpu_to_be_32(length),
1524                                 mlx5_tx_mb2mr(txq, buf),
1525                                 addr,
1526                                 addr >> 32,
1527                         };
1528                         mpw.data.raw = (volatile void *)(dseg + 1);
1529                         mpw.total_len += (inl_pad + sizeof(*dseg));
1530                         ++j;
1531                         ++mpw.pkts_n;
1532                         mpw_room -= (inl_pad + sizeof(*dseg));
1533                         inl_pad = 0;
1534                 }
1535 #ifdef MLX5_PMD_SOFT_COUNTERS
1536                 /* Increment sent bytes counter. */
1537                 txq->stats.obytes += length;
1538 #endif
1539                 ++i;
1540         } while (i < pkts_n);
1541         /* Take a shortcut if nothing must be sent. */
1542         if (unlikely(i == 0))
1543                 return 0;
1544         /* Check whether completion threshold has been reached. */
1545         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1546                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1547                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1548                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1549
1550                 /* Request completion on last WQE. */
1551                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1552                 /* Save elts_head in unused "immediate" field of WQE. */
1553                 wqe->ctrl[3] = elts_head;
1554                 txq->elts_comp = 0;
1555                 txq->mpw_comp = txq->wqe_ci;
1556                 txq->cq_pi++;
1557         } else {
1558                 txq->elts_comp += j;
1559         }
1560 #ifdef MLX5_PMD_SOFT_COUNTERS
1561         /* Increment sent packets counter. */
1562         txq->stats.opackets += i;
1563 #endif
1564         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1565                 mlx5_empw_close(txq, &mpw);
1566         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1567                 mlx5_mpw_close(txq, &mpw);
1568         /* Ring QP doorbell. */
1569         mlx5_tx_dbrec(txq, mpw.wqe);
1570         txq->elts_head = elts_head;
1571         return i;
1572 }
1573
1574 /**
1575  * Translate RX completion flags to packet type.
1576  *
1577  * @param[in] cqe
1578  *   Pointer to CQE.
1579  *
1580  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1581  *
1582  * @return
1583  *   Packet type for struct rte_mbuf.
1584  */
1585 static inline uint32_t
1586 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1587 {
1588         uint8_t idx;
1589         uint8_t pinfo = cqe->pkt_info;
1590         uint16_t ptype = cqe->hdr_type_etc;
1591
1592         /*
1593          * The index to the array should have:
1594          * bit[1:0] = l3_hdr_type
1595          * bit[4:2] = l4_hdr_type
1596          * bit[5] = ip_frag
1597          * bit[6] = tunneled
1598          * bit[7] = outer_l3_type
1599          */
1600         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1601         return mlx5_ptype_table[idx];
1602 }
1603
1604 /**
1605  * Get size of the next packet for a given CQE. For compressed CQEs, the
1606  * consumer index is updated only once all packets of the current one have
1607  * been processed.
1608  *
1609  * @param rxq
1610  *   Pointer to RX queue.
1611  * @param cqe
1612  *   CQE to process.
1613  * @param[out] rss_hash
1614  *   Packet RSS Hash result.
1615  *
1616  * @return
1617  *   Packet size in bytes (0 if there is none), -1 in case of completion
1618  *   with error.
1619  */
1620 static inline int
1621 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1622                  uint16_t cqe_cnt, uint32_t *rss_hash)
1623 {
1624         struct rxq_zip *zip = &rxq->zip;
1625         uint16_t cqe_n = cqe_cnt + 1;
1626         int len = 0;
1627         uint16_t idx, end;
1628
1629         /* Process compressed data in the CQE and mini arrays. */
1630         if (zip->ai) {
1631                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1632                         (volatile struct mlx5_mini_cqe8 (*)[8])
1633                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1634
1635                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1636                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1637                 if ((++zip->ai & 7) == 0) {
1638                         /* Invalidate consumed CQEs */
1639                         idx = zip->ca;
1640                         end = zip->na;
1641                         while (idx != end) {
1642                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1643                                         MLX5_CQE_INVALIDATE;
1644                                 ++idx;
1645                         }
1646                         /*
1647                          * Increment consumer index to skip the number of
1648                          * CQEs consumed. Hardware leaves holes in the CQ
1649                          * ring for software use.
1650                          */
1651                         zip->ca = zip->na;
1652                         zip->na += 8;
1653                 }
1654                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1655                         /* Invalidate the rest */
1656                         idx = zip->ca;
1657                         end = zip->cq_ci;
1658
1659                         while (idx != end) {
1660                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1661                                         MLX5_CQE_INVALIDATE;
1662                                 ++idx;
1663                         }
1664                         rxq->cq_ci = zip->cq_ci;
1665                         zip->ai = 0;
1666                 }
1667         /* No compressed data, get next CQE and verify if it is compressed. */
1668         } else {
1669                 int ret;
1670                 int8_t op_own;
1671
1672                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1673                 if (unlikely(ret == 1))
1674                         return 0;
1675                 ++rxq->cq_ci;
1676                 op_own = cqe->op_own;
1677                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1678                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1679                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1680                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1681                                                           cqe_cnt].pkt_info);
1682
1683                         /* Fix endianness. */
1684                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1685                         /*
1686                          * Current mini array position is the one returned by
1687                          * check_cqe64().
1688                          *
1689                          * If completion comprises several mini arrays, as a
1690                          * special case the second one is located 7 CQEs after
1691                          * the initial CQE instead of 8 for subsequent ones.
1692                          */
1693                         zip->ca = rxq->cq_ci;
1694                         zip->na = zip->ca + 7;
1695                         /* Compute the next non compressed CQE. */
1696                         --rxq->cq_ci;
1697                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1698                         /* Get packet size to return. */
1699                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1700                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1701                         zip->ai = 1;
1702                         /* Prefetch all the entries to be invalidated */
1703                         idx = zip->ca;
1704                         end = zip->cq_ci;
1705                         while (idx != end) {
1706                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1707                                 ++idx;
1708                         }
1709                 } else {
1710                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1711                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1712                 }
1713                 /* Error while receiving packet. */
1714                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1715                         return -1;
1716         }
1717         return len;
1718 }
1719
1720 /**
1721  * Translate RX completion flags to offload flags.
1722  *
1723  * @param[in] rxq
1724  *   Pointer to RX queue structure.
1725  * @param[in] cqe
1726  *   Pointer to CQE.
1727  *
1728  * @return
1729  *   Offload flags (ol_flags) for struct rte_mbuf.
1730  */
1731 static inline uint32_t
1732 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1733 {
1734         uint32_t ol_flags = 0;
1735         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1736
1737         ol_flags =
1738                 TRANSPOSE(flags,
1739                           MLX5_CQE_RX_L3_HDR_VALID,
1740                           PKT_RX_IP_CKSUM_GOOD) |
1741                 TRANSPOSE(flags,
1742                           MLX5_CQE_RX_L4_HDR_VALID,
1743                           PKT_RX_L4_CKSUM_GOOD);
1744         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1745                 ol_flags |=
1746                         TRANSPOSE(flags,
1747                                   MLX5_CQE_RX_L3_HDR_VALID,
1748                                   PKT_RX_IP_CKSUM_GOOD) |
1749                         TRANSPOSE(flags,
1750                                   MLX5_CQE_RX_L4_HDR_VALID,
1751                                   PKT_RX_L4_CKSUM_GOOD);
1752         return ol_flags;
1753 }
1754
1755 /**
1756  * DPDK callback for RX.
1757  *
1758  * @param dpdk_rxq
1759  *   Generic pointer to RX queue structure.
1760  * @param[out] pkts
1761  *   Array to store received packets.
1762  * @param pkts_n
1763  *   Maximum number of packets in array.
1764  *
1765  * @return
1766  *   Number of packets successfully received (<= pkts_n).
1767  */
1768 uint16_t
1769 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1770 {
1771         struct mlx5_rxq_data *rxq = dpdk_rxq;
1772         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1773         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1774         const unsigned int sges_n = rxq->sges_n;
1775         struct rte_mbuf *pkt = NULL;
1776         struct rte_mbuf *seg = NULL;
1777         volatile struct mlx5_cqe *cqe =
1778                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1779         unsigned int i = 0;
1780         unsigned int rq_ci = rxq->rq_ci << sges_n;
1781         int len = 0; /* keep its value across iterations. */
1782
1783         while (pkts_n) {
1784                 unsigned int idx = rq_ci & wqe_cnt;
1785                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1786                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1787                 uint32_t rss_hash_res = 0;
1788
1789                 if (pkt)
1790                         NEXT(seg) = rep;
1791                 seg = rep;
1792                 rte_prefetch0(seg);
1793                 rte_prefetch0(cqe);
1794                 rte_prefetch0(wqe);
1795                 rep = rte_mbuf_raw_alloc(rxq->mp);
1796                 if (unlikely(rep == NULL)) {
1797                         ++rxq->stats.rx_nombuf;
1798                         if (!pkt) {
1799                                 /*
1800                                  * no buffers before we even started,
1801                                  * bail out silently.
1802                                  */
1803                                 break;
1804                         }
1805                         while (pkt != seg) {
1806                                 assert(pkt != (*rxq->elts)[idx]);
1807                                 rep = NEXT(pkt);
1808                                 NEXT(pkt) = NULL;
1809                                 NB_SEGS(pkt) = 1;
1810                                 rte_mbuf_raw_free(pkt);
1811                                 pkt = rep;
1812                         }
1813                         break;
1814                 }
1815                 if (!pkt) {
1816                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1817                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1818                                                &rss_hash_res);
1819                         if (!len) {
1820                                 rte_mbuf_raw_free(rep);
1821                                 break;
1822                         }
1823                         if (unlikely(len == -1)) {
1824                                 /* RX error, packet is likely too large. */
1825                                 rte_mbuf_raw_free(rep);
1826                                 ++rxq->stats.idropped;
1827                                 goto skip;
1828                         }
1829                         pkt = seg;
1830                         assert(len >= (rxq->crc_present << 2));
1831                         /* Update packet information. */
1832                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1833                         pkt->ol_flags = 0;
1834                         if (rss_hash_res && rxq->rss_hash) {
1835                                 pkt->hash.rss = rss_hash_res;
1836                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1837                         }
1838                         if (rxq->mark &&
1839                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1840                                 pkt->ol_flags |= PKT_RX_FDIR;
1841                                 if (cqe->sop_drop_qpn !=
1842                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1843                                         uint32_t mark = cqe->sop_drop_qpn;
1844
1845                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1846                                         pkt->hash.fdir.hi =
1847                                                 mlx5_flow_mark_get(mark);
1848                                 }
1849                         }
1850                         if (rxq->csum | rxq->csum_l2tun)
1851                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1852                         if (rxq->vlan_strip &&
1853                             (cqe->hdr_type_etc &
1854                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1855                                 pkt->ol_flags |= PKT_RX_VLAN |
1856                                         PKT_RX_VLAN_STRIPPED;
1857                                 pkt->vlan_tci =
1858                                         rte_be_to_cpu_16(cqe->vlan_info);
1859                         }
1860                         if (rxq->hw_timestamp) {
1861                                 pkt->timestamp =
1862                                         rte_be_to_cpu_64(cqe->timestamp);
1863                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1864                         }
1865                         if (rxq->crc_present)
1866                                 len -= ETHER_CRC_LEN;
1867                         PKT_LEN(pkt) = len;
1868                 }
1869                 DATA_LEN(rep) = DATA_LEN(seg);
1870                 PKT_LEN(rep) = PKT_LEN(seg);
1871                 SET_DATA_OFF(rep, DATA_OFF(seg));
1872                 PORT(rep) = PORT(seg);
1873                 (*rxq->elts)[idx] = rep;
1874                 /*
1875                  * Fill NIC descriptor with the new buffer.  The lkey and size
1876                  * of the buffers are already known, only the buffer address
1877                  * changes.
1878                  */
1879                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1880                 if (len > DATA_LEN(seg)) {
1881                         len -= DATA_LEN(seg);
1882                         ++NB_SEGS(pkt);
1883                         ++rq_ci;
1884                         continue;
1885                 }
1886                 DATA_LEN(seg) = len;
1887 #ifdef MLX5_PMD_SOFT_COUNTERS
1888                 /* Increment bytes counter. */
1889                 rxq->stats.ibytes += PKT_LEN(pkt);
1890 #endif
1891                 /* Return packet. */
1892                 *(pkts++) = pkt;
1893                 pkt = NULL;
1894                 --pkts_n;
1895                 ++i;
1896 skip:
1897                 /* Align consumer index to the next stride. */
1898                 rq_ci >>= sges_n;
1899                 ++rq_ci;
1900                 rq_ci <<= sges_n;
1901         }
1902         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1903                 return 0;
1904         /* Update the consumer index. */
1905         rxq->rq_ci = rq_ci >> sges_n;
1906         rte_io_wmb();
1907         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1908         rte_io_wmb();
1909         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1910 #ifdef MLX5_PMD_SOFT_COUNTERS
1911         /* Increment packets counter. */
1912         rxq->stats.ipackets += i;
1913 #endif
1914         return i;
1915 }
1916
1917 /**
1918  * Dummy DPDK callback for TX.
1919  *
1920  * This function is used to temporarily replace the real callback during
1921  * unsafe control operations on the queue, or in case of error.
1922  *
1923  * @param dpdk_txq
1924  *   Generic pointer to TX queue structure.
1925  * @param[in] pkts
1926  *   Packets to transmit.
1927  * @param pkts_n
1928  *   Number of packets in array.
1929  *
1930  * @return
1931  *   Number of packets successfully transmitted (<= pkts_n).
1932  */
1933 uint16_t
1934 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1935 {
1936         (void)dpdk_txq;
1937         (void)pkts;
1938         (void)pkts_n;
1939         return 0;
1940 }
1941
1942 /**
1943  * Dummy DPDK callback for RX.
1944  *
1945  * This function is used to temporarily replace the real callback during
1946  * unsafe control operations on the queue, or in case of error.
1947  *
1948  * @param dpdk_rxq
1949  *   Generic pointer to RX queue structure.
1950  * @param[out] pkts
1951  *   Array to store received packets.
1952  * @param pkts_n
1953  *   Maximum number of packets in array.
1954  *
1955  * @return
1956  *   Number of packets successfully received (<= pkts_n).
1957  */
1958 uint16_t
1959 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1960 {
1961         (void)dpdk_rxq;
1962         (void)pkts;
1963         (void)pkts_n;
1964         return 0;
1965 }
1966
1967 /*
1968  * Vectorized Rx/Tx routines are not compiled in when required vector
1969  * instructions are not supported on a target architecture. The following null
1970  * stubs are needed for linkage when those are not included outside of this file
1971  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1972  */
1973
1974 uint16_t __attribute__((weak))
1975 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1976 {
1977         (void)dpdk_txq;
1978         (void)pkts;
1979         (void)pkts_n;
1980         return 0;
1981 }
1982
1983 uint16_t __attribute__((weak))
1984 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1985 {
1986         (void)dpdk_txq;
1987         (void)pkts;
1988         (void)pkts_n;
1989         return 0;
1990 }
1991
1992 uint16_t __attribute__((weak))
1993 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1994 {
1995         (void)dpdk_rxq;
1996         (void)pkts;
1997         (void)pkts_n;
1998         return 0;
1999 }
2000
2001 int __attribute__((weak))
2002 priv_check_raw_vec_tx_support(struct priv *priv)
2003 {
2004         (void)priv;
2005         return -ENOTSUP;
2006 }
2007
2008 int __attribute__((weak))
2009 priv_check_vec_tx_support(struct priv *priv)
2010 {
2011         (void)priv;
2012         return -ENOTSUP;
2013 }
2014
2015 int __attribute__((weak))
2016 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2017 {
2018         (void)rxq;
2019         return -ENOTSUP;
2020 }
2021
2022 int __attribute__((weak))
2023 priv_check_vec_rx_support(struct priv *priv)
2024 {
2025         (void)priv;
2026         return -ENOTSUP;
2027 }