drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  45
  46 static __rte_always_inline void
  47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  48                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  49
  50 static __rte_always_inline void
  51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  52
  53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  54         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  55 };
  56
  57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  59
  60 /**
  61  * Build a table to translate Rx completion flags to packet type.
  62  *
  63  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  64  */
  65 void
  66 mlx5_set_ptype_table(void)
  67 {
  68         unsigned int i;
  69         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  70
  71         /* Last entry must not be overwritten, reserved for errored packet. */
  72         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  73                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  74         /*
  75          * The index to the array should have:
  76          * bit[1:0] = l3_hdr_type
  77          * bit[4:2] = l4_hdr_type
  78          * bit[5] = ip_frag
  79          * bit[6] = tunneled
  80          * bit[7] = outer_l3_type
  81          */
  82         /* L2 */
  83         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  84         /* L3 */
  85         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_NONFRAG;
  87         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_NONFRAG;
  89         /* Fragmented */
  90         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  91                      RTE_PTYPE_L4_FRAG;
  92         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG;
  94         /* TCP */
  95         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  96                      RTE_PTYPE_L4_TCP;
  97         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP;
  99         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP;
 101         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP;
 103         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_TCP;
 105         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_TCP;
 107         /* UDP */
 108         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_UDP;
 110         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_UDP;
 112         /* Repeat with outer_l3_type being set. Just in case. */
 113         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_NONFRAG;
 115         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_NONFRAG;
 117         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_FRAG;
 119         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_FRAG;
 121         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_TCP;
 125         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_TCP;
 127         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_TCP;
 129         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_TCP;
 131         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_UDP;
 135         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         /* Tunneled - L3 */
 138         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L4_TCP;
 196         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 197                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L4_TCP;
 199         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L4_TCP;
 202         /* Tunneled - UDP */
 203         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_UDP;
 209         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_UDP;
 212         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 213                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L4_UDP;
 215 }
 216
 217 /**
 218  * Build a table to translate packet to checksum type of Verbs.
 219  */
 220 void
 221 mlx5_set_cksum_table(void)
 222 {
 223         unsigned int i;
 224         uint8_t v;
 225
 226         /*
 227          * The index should have:
 228          * bit[0] = PKT_TX_TCP_SEG
 229          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 230          * bit[4] = PKT_TX_IP_CKSUM
 231          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 232          * bit[9] = tunnel
 233          */
 234         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 235                 v = 0;
 236                 if (i & (1 << 9)) {
 237                         /* Tunneled packet. */
 238                         if (i & (1 << 8)) /* Outer IP. */
 239                                 v |= MLX5_ETH_WQE_L3_CSUM;
 240                         if (i & (1 << 4)) /* Inner IP. */
 241                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 242                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 243                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 244                 } else {
 245                         /* No tunnel. */
 246                         if (i & (1 << 4)) /* IP. */
 247                                 v |= MLX5_ETH_WQE_L3_CSUM;
 248                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 249                                 v |= MLX5_ETH_WQE_L4_CSUM;
 250                 }
 251                 mlx5_cksum_table[i] = v;
 252         }
 253 }
 254
 255 /**
 256  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 257  */
 258 void
 259 mlx5_set_swp_types_table(void)
 260 {
 261         unsigned int i;
 262         uint8_t v;
 263
 264         /*
 265          * The index should have:
 266          * bit[0:1] = PKT_TX_L4_MASK
 267          * bit[4] = PKT_TX_IPV6
 268          * bit[8] = PKT_TX_OUTER_IPV6
 269          * bit[9] = PKT_TX_OUTER_UDP
 270          */
 271         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 272                 v = 0;
 273                 if (i & (1 << 8))
 274                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 275                 if (i & (1 << 9))
 276                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 277                 if (i & (1 << 4))
 278                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 279                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 280                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 281                 mlx5_swp_types_table[i] = v;
 282         }
 283 }
 284
 285 /**
 286  * Return the size of tailroom of WQ.
 287  *
 288  * @param txq
 289  *   Pointer to TX queue structure.
 290  * @param addr
 291  *   Pointer to tail of WQ.
 292  *
 293  * @return
 294  *   Size of tailroom.
 295  */
 296 static inline size_t
 297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 298 {
 299         size_t tailroom;
 300         tailroom = (uintptr_t)(txq->wqes) +
 301                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 302                    (uintptr_t)addr;
 303         return tailroom;
 304 }
 305
 306 /**
 307  * Copy data to tailroom of circular queue.
 308  *
 309  * @param dst
 310  *   Pointer to destination.
 311  * @param src
 312  *   Pointer to source.
 313  * @param n
 314  *   Number of bytes to copy.
 315  * @param base
 316  *   Pointer to head of queue.
 317  * @param tailroom
 318  *   Size of tailroom from dst.
 319  *
 320  * @return
 321  *   Pointer after copied data.
 322  */
 323 static inline void *
 324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 325                 void *base, size_t tailroom)
 326 {
 327         void *ret;
 328
 329         if (n > tailroom) {
 330                 rte_memcpy(dst, src, tailroom);
 331                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 332                            n - tailroom);
 333                 ret = (uint8_t *)base + n - tailroom;
 334         } else {
 335                 rte_memcpy(dst, src, n);
 336                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 337         }
 338         return ret;
 339 }
 340
 341 /**
 342  * Inline TSO headers into WQE.
 343  *
 344  * @return
 345  *   0 on success, negative errno value on failure.
 346  */
 347 static int
 348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 349            uint32_t *length,
 350            uintptr_t *addr,
 351            uint16_t *pkt_inline_sz,
 352            uint8_t **raw,
 353            uint16_t *max_wqe,
 354            uint16_t *tso_segsz,
 355            uint16_t *tso_header_sz)
 356 {
 357         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 358                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 359         unsigned int copy_b;
 360         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 361         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 362                                  PKT_TX_TUNNEL_MASK);
 363         uint16_t n_wqe;
 364
 365         *tso_segsz = buf->tso_segsz;
 366         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 367         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 368                 txq->stats.oerrors++;
 369                 return -EINVAL;
 370         }
 371         if (tunneled)
 372                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 373         /* First seg must contain all TSO headers. */
 374         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 375                      *tso_header_sz > DATA_LEN(buf)) {
 376                 txq->stats.oerrors++;
 377                 return -EINVAL;
 378         }
 379         copy_b = *tso_header_sz - *pkt_inline_sz;
 380         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 381                 return -EAGAIN;
 382         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 383         if (unlikely(*max_wqe < n_wqe))
 384                 return -EINVAL;
 385         *max_wqe -= n_wqe;
 386         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 387         *length -= copy_b;
 388         *addr += copy_b;
 389         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 390         *pkt_inline_sz += copy_b;
 391         *raw += copy_b;
 392         return 0;
 393 }
 394
 395 /**
 396  * DPDK callback to check the status of a tx descriptor.
 397  *
 398  * @param tx_queue
 399  *   The tx queue.
 400  * @param[in] offset
 401  *   The index of the descriptor in the ring.
 402  *
 403  * @return
 404  *   The status of the tx descriptor.
 405  */
 406 int
 407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 408 {
 409         struct mlx5_txq_data *txq = tx_queue;
 410         uint16_t used;
 411
 412         mlx5_tx_complete(txq);
 413         used = txq->elts_head - txq->elts_tail;
 414         if (offset < used)
 415                 return RTE_ETH_TX_DESC_FULL;
 416         return RTE_ETH_TX_DESC_DONE;
 417 }
 418
 419 /**
 420  * DPDK callback to check the status of a rx descriptor.
 421  *
 422  * @param rx_queue
 423  *   The rx queue.
 424  * @param[in] offset
 425  *   The index of the descriptor in the ring.
 426  *
 427  * @return
 428  *   The status of the tx descriptor.
 429  */
 430 int
 431 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 432 {
 433         struct mlx5_rxq_data *rxq = rx_queue;
 434         struct rxq_zip *zip = &rxq->zip;
 435         volatile struct mlx5_cqe *cqe;
 436         const unsigned int cqe_n = (1 << rxq->cqe_n);
 437         const unsigned int cqe_cnt = cqe_n - 1;
 438         unsigned int cq_ci;
 439         unsigned int used;
 440
 441         /* if we are processing a compressed cqe */
 442         if (zip->ai) {
 443                 used = zip->cqe_cnt - zip->ca;
 444                 cq_ci = zip->cq_ci;
 445         } else {
 446                 used = 0;
 447                 cq_ci = rxq->cq_ci;
 448         }
 449         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 450         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 451                 int8_t op_own;
 452                 unsigned int n;
 453
 454                 op_own = cqe->op_own;
 455                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 456                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 457                 else
 458                         n = 1;
 459                 cq_ci += n;
 460                 used += n;
 461                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 462         }
 463         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 464         if (offset < used)
 465                 return RTE_ETH_RX_DESC_DONE;
 466         return RTE_ETH_RX_DESC_AVAIL;
 467 }
 468
 469 /**
 470  * DPDK callback for TX.
 471  *
 472  * @param dpdk_txq
 473  *   Generic pointer to TX queue structure.
 474  * @param[in] pkts
 475  *   Packets to transmit.
 476  * @param pkts_n
 477  *   Number of packets in array.
 478  *
 479  * @return
 480  *   Number of packets successfully transmitted (<= pkts_n).
 481  */
 482 uint16_t
 483 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 484 {
 485         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 486         uint16_t elts_head = txq->elts_head;
 487         const uint16_t elts_n = 1 << txq->elts_n;
 488         const uint16_t elts_m = elts_n - 1;
 489         unsigned int i = 0;
 490         unsigned int j = 0;
 491         unsigned int k = 0;
 492         uint16_t max_elts;
 493         uint16_t max_wqe;
 494         unsigned int comp;
 495         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 496         unsigned int segs_n = 0;
 497         const unsigned int max_inline = txq->max_inline;
 498         uint64_t addr_64;
 499
 500         if (unlikely(!pkts_n))
 501                 return 0;
 502         /* Prefetch first packet cacheline. */
 503         rte_prefetch0(*pkts);
 504         /* Start processing. */
 505         mlx5_tx_complete(txq);
 506         max_elts = (elts_n - (elts_head - txq->elts_tail));
 507         /* A CQE slot must always be available. */
 508         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 509         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 510         if (unlikely(!max_wqe))
 511                 return 0;
 512         do {
 513                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 514                 uint8_t *raw;
 515                 volatile struct mlx5_wqe_v *wqe = NULL;
 516                 volatile rte_v128u32_t *dseg = NULL;
 517                 uint32_t length;
 518                 unsigned int ds = 0;
 519                 unsigned int sg = 0; /* counter of additional segs attached. */
 520                 uintptr_t addr;
 521                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 522                 uint16_t tso_header_sz = 0;
 523                 uint16_t ehdr;
 524                 uint8_t cs_flags;
 525                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 526                 uint32_t swp_offsets = 0;
 527                 uint8_t swp_types = 0;
 528                 uint16_t tso_segsz = 0;
 529 #ifdef MLX5_PMD_SOFT_COUNTERS
 530                 uint32_t total_length = 0;
 531 #endif
 532                 int ret;
 533
 534                 segs_n = buf->nb_segs;
 535                 /*
 536                  * Make sure there is enough room to store this packet and
 537                  * that one ring entry remains unused.
 538                  */
 539                 assert(segs_n);
 540                 if (max_elts < segs_n)
 541                         break;
 542                 max_elts -= segs_n;
 543                 sg = --segs_n;
 544                 if (unlikely(--max_wqe == 0))
 545                         break;
 546                 wqe = (volatile struct mlx5_wqe_v *)
 547                         tx_mlx5_wqe(txq, txq->wqe_ci);
 548                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 549                 if (pkts_n - i > 1)
 550                         rte_prefetch0(*(pkts + 1));
 551                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 552                 length = DATA_LEN(buf);
 553                 ehdr = (((uint8_t *)addr)[1] << 8) |
 554                        ((uint8_t *)addr)[0];
 555 #ifdef MLX5_PMD_SOFT_COUNTERS
 556                 total_length = length;
 557 #endif
 558                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 559                         txq->stats.oerrors++;
 560                         break;
 561                 }
 562                 /* Update element. */
 563                 (*txq->elts)[elts_head & elts_m] = buf;
 564                 /* Prefetch next buffer data. */
 565                 if (pkts_n - i > 1)
 566                         rte_prefetch0(
 567                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 568                 cs_flags = txq_ol_cksum_to_cs(buf);
 569                 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
 570                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 571                 /* Replace the Ethernet type by the VLAN if necessary. */
 572                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 573                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 574                                                          buf->vlan_tci);
 575                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 576
 577                         addr += 2;
 578                         length -= 2;
 579                         /* Copy Destination and source mac address. */
 580                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 581                         /* Copy VLAN. */
 582                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 583                         /* Copy missing two bytes to end the DSeg. */
 584                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 585                                ((uint8_t *)addr) + len, 2);
 586                         addr += len + 2;
 587                         length -= (len + 2);
 588                 } else {
 589                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 590                                MLX5_WQE_DWORD_SIZE);
 591                         length -= pkt_inline_sz;
 592                         addr += pkt_inline_sz;
 593                 }
 594                 raw += MLX5_WQE_DWORD_SIZE;
 595                 if (tso) {
 596                         ret = inline_tso(txq, buf, &length,
 597                                          &addr, &pkt_inline_sz,
 598                                          &raw, &max_wqe,
 599                                          &tso_segsz, &tso_header_sz);
 600                         if (ret == -EINVAL) {
 601                                 break;
 602                         } else if (ret == -EAGAIN) {
 603                                 /* NOP WQE. */
 604                                 wqe->ctrl = (rte_v128u32_t){
 605                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 606                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 607                                         0,
 608                                         0,
 609                                 };
 610                                 ds = 1;
 611 #ifdef MLX5_PMD_SOFT_COUNTERS
 612                                 total_length = 0;
 613 #endif
 614                                 k++;
 615                                 goto next_wqe;
 616                         }
 617                 }
 618                 /* Inline if enough room. */
 619                 if (max_inline || tso) {
 620                         uint32_t inl = 0;
 621                         uintptr_t end = (uintptr_t)
 622                                 (((uintptr_t)txq->wqes) +
 623                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 624                         unsigned int inline_room = max_inline *
 625                                                    RTE_CACHE_LINE_SIZE -
 626                                                    (pkt_inline_sz - 2) -
 627                                                    !!tso * sizeof(inl);
 628                         uintptr_t addr_end;
 629                         unsigned int copy_b;
 630
 631 pkt_inline:
 632                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 633                                                    RTE_CACHE_LINE_SIZE);
 634                         copy_b = (addr_end > addr) ?
 635                                  RTE_MIN((addr_end - addr), length) : 0;
 636                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 637                                 /*
 638                                  * One Dseg remains in the current WQE.  To
 639                                  * keep the computation positive, it is
 640                                  * removed after the bytes to Dseg conversion.
 641                                  */
 642                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 643
 644                                 if (unlikely(max_wqe < n))
 645                                         break;
 646                                 max_wqe -= n;
 647                                 if (tso) {
 648                                         assert(inl == 0);
 649                                         inl = rte_cpu_to_be_32(copy_b |
 650                                                                MLX5_INLINE_SEG);
 651                                         rte_memcpy((void *)raw,
 652                                                    (void *)&inl, sizeof(inl));
 653                                         raw += sizeof(inl);
 654                                         pkt_inline_sz += sizeof(inl);
 655                                 }
 656                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 657                                 addr += copy_b;
 658                                 length -= copy_b;
 659                                 pkt_inline_sz += copy_b;
 660                         }
 661                         /*
 662                          * 2 DWORDs consumed by the WQE header + ETH segment +
 663                          * the size of the inline part of the packet.
 664                          */
 665                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 666                         if (length > 0) {
 667                                 if (ds % (MLX5_WQE_SIZE /
 668                                           MLX5_WQE_DWORD_SIZE) == 0) {
 669                                         if (unlikely(--max_wqe == 0))
 670                                                 break;
 671                                         dseg = (volatile rte_v128u32_t *)
 672                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 673                                                            ds / 4);
 674                                 } else {
 675                                         dseg = (volatile rte_v128u32_t *)
 676                                                 ((uintptr_t)wqe +
 677                                                  (ds * MLX5_WQE_DWORD_SIZE));
 678                                 }
 679                                 goto use_dseg;
 680                         } else if (!segs_n) {
 681                                 goto next_pkt;
 682                         } else {
 683                                 /*
 684                                  * Further inline the next segment only for
 685                                  * non-TSO packets.
 686                                  */
 687                                 if (!tso) {
 688                                         raw += copy_b;
 689                                         inline_room -= copy_b;
 690                                 } else {
 691                                         inline_room = 0;
 692                                 }
 693                                 /* Move to the next segment. */
 694                                 --segs_n;
 695                                 buf = buf->next;
 696                                 assert(buf);
 697                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 698                                 length = DATA_LEN(buf);
 699 #ifdef MLX5_PMD_SOFT_COUNTERS
 700                                 total_length += length;
 701 #endif
 702                                 (*txq->elts)[++elts_head & elts_m] = buf;
 703                                 goto pkt_inline;
 704                         }
 705                 } else {
 706                         /*
 707                          * No inline has been done in the packet, only the
 708                          * Ethernet Header as been stored.
 709                          */
 710                         dseg = (volatile rte_v128u32_t *)
 711                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 712                         ds = 3;
 713 use_dseg:
 714                         /* Add the remaining packet as a simple ds. */
 715                         addr_64 = rte_cpu_to_be_64(addr);
 716                         *dseg = (rte_v128u32_t){
 717                                 rte_cpu_to_be_32(length),
 718                                 mlx5_tx_mb2mr(txq, buf),
 719                                 addr_64,
 720                                 addr_64 >> 32,
 721                         };
 722                         ++ds;
 723                         if (!segs_n)
 724                                 goto next_pkt;
 725                 }
 726 next_seg:
 727                 assert(buf);
 728                 assert(ds);
 729                 assert(wqe);
 730                 /*
 731                  * Spill on next WQE when the current one does not have
 732                  * enough room left. Size of WQE must a be a multiple
 733                  * of data segment size.
 734                  */
 735                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 736                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 737                         if (unlikely(--max_wqe == 0))
 738                                 break;
 739                         dseg = (volatile rte_v128u32_t *)
 740                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 741                         rte_prefetch0(tx_mlx5_wqe(txq,
 742                                                   txq->wqe_ci + ds / 4 + 1));
 743                 } else {
 744                         ++dseg;
 745                 }
 746                 ++ds;
 747                 buf = buf->next;
 748                 assert(buf);
 749                 length = DATA_LEN(buf);
 750 #ifdef MLX5_PMD_SOFT_COUNTERS
 751                 total_length += length;
 752 #endif
 753                 /* Store segment information. */
 754                 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 755                 *dseg = (rte_v128u32_t){
 756                         rte_cpu_to_be_32(length),
 757                         mlx5_tx_mb2mr(txq, buf),
 758                         addr_64,
 759                         addr_64 >> 32,
 760                 };
 761                 (*txq->elts)[++elts_head & elts_m] = buf;
 762                 if (--segs_n)
 763                         goto next_seg;
 764 next_pkt:
 765                 if (ds > MLX5_DSEG_MAX) {
 766                         txq->stats.oerrors++;
 767                         break;
 768                 }
 769                 ++elts_head;
 770                 ++pkts;
 771                 ++i;
 772                 j += sg;
 773                 /* Initialize known and common part of the WQE structure. */
 774                 if (tso) {
 775                         wqe->ctrl = (rte_v128u32_t){
 776                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 777                                                  MLX5_OPCODE_TSO),
 778                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 779                                 0,
 780                                 0,
 781                         };
 782                         wqe->eseg = (rte_v128u32_t){
 783                                 swp_offsets,
 784                                 cs_flags | (swp_types << 8) |
 785                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 786                                 0,
 787                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 788                         };
 789                 } else {
 790                         wqe->ctrl = (rte_v128u32_t){
 791                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 792                                                  MLX5_OPCODE_SEND),
 793                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 794                                 0,
 795                                 0,
 796                         };
 797                         wqe->eseg = (rte_v128u32_t){
 798                                 swp_offsets,
 799                                 cs_flags | (swp_types << 8),
 800                                 0,
 801                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 802                         };
 803                 }
 804 next_wqe:
 805                 txq->wqe_ci += (ds + 3) / 4;
 806                 /* Save the last successful WQE for completion request */
 807                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 808 #ifdef MLX5_PMD_SOFT_COUNTERS
 809                 /* Increment sent bytes counter. */
 810                 txq->stats.obytes += total_length;
 811 #endif
 812         } while (i < pkts_n);
 813         /* Take a shortcut if nothing must be sent. */
 814         if (unlikely((i + k) == 0))
 815                 return 0;
 816         txq->elts_head += (i + j);
 817         /* Check whether completion threshold has been reached. */
 818         comp = txq->elts_comp + i + j + k;
 819         if (comp >= MLX5_TX_COMP_THRESH) {
 820                 /* Request completion on last WQE. */
 821                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 822                 /* Save elts_head in unused "immediate" field of WQE. */
 823                 last_wqe->ctrl3 = txq->elts_head;
 824                 txq->elts_comp = 0;
 825 #ifndef NDEBUG
 826                 ++txq->cq_pi;
 827 #endif
 828         } else {
 829                 txq->elts_comp = comp;
 830         }
 831 #ifdef MLX5_PMD_SOFT_COUNTERS
 832         /* Increment sent packets counter. */
 833         txq->stats.opackets += i;
 834 #endif
 835         /* Ring QP doorbell. */
 836         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 837         return i;
 838 }
 839
 840 /**
 841  * Open a MPW session.
 842  *
 843  * @param txq
 844  *   Pointer to TX queue structure.
 845  * @param mpw
 846  *   Pointer to MPW session structure.
 847  * @param length
 848  *   Packet length.
 849  */
 850 static inline void
 851 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 852 {
 853         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 854         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 855                 (volatile struct mlx5_wqe_data_seg (*)[])
 856                 tx_mlx5_wqe(txq, idx + 1);
 857
 858         mpw->state = MLX5_MPW_STATE_OPENED;
 859         mpw->pkts_n = 0;
 860         mpw->len = length;
 861         mpw->total_len = 0;
 862         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 863         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 864         mpw->wqe->eseg.inline_hdr_sz = 0;
 865         mpw->wqe->eseg.rsvd0 = 0;
 866         mpw->wqe->eseg.rsvd1 = 0;
 867         mpw->wqe->eseg.rsvd2 = 0;
 868         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 869                                              (txq->wqe_ci << 8) |
 870                                              MLX5_OPCODE_TSO);
 871         mpw->wqe->ctrl[2] = 0;
 872         mpw->wqe->ctrl[3] = 0;
 873         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 874                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 875         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 876                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 877         mpw->data.dseg[2] = &(*dseg)[0];
 878         mpw->data.dseg[3] = &(*dseg)[1];
 879         mpw->data.dseg[4] = &(*dseg)[2];
 880 }
 881
 882 /**
 883  * Close a MPW session.
 884  *
 885  * @param txq
 886  *   Pointer to TX queue structure.
 887  * @param mpw
 888  *   Pointer to MPW session structure.
 889  */
 890 static inline void
 891 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 892 {
 893         unsigned int num = mpw->pkts_n;
 894
 895         /*
 896          * Store size in multiple of 16 bytes. Control and Ethernet segments
 897          * count as 2.
 898          */
 899         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 900         mpw->state = MLX5_MPW_STATE_CLOSED;
 901         if (num < 3)
 902                 ++txq->wqe_ci;
 903         else
 904                 txq->wqe_ci += 2;
 905         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 906         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 907 }
 908
 909 /**
 910  * DPDK callback for TX with MPW support.
 911  *
 912  * @param dpdk_txq
 913  *   Generic pointer to TX queue structure.
 914  * @param[in] pkts
 915  *   Packets to transmit.
 916  * @param pkts_n
 917  *   Number of packets in array.
 918  *
 919  * @return
 920  *   Number of packets successfully transmitted (<= pkts_n).
 921  */
 922 uint16_t
 923 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 924 {
 925         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 926         uint16_t elts_head = txq->elts_head;
 927         const uint16_t elts_n = 1 << txq->elts_n;
 928         const uint16_t elts_m = elts_n - 1;
 929         unsigned int i = 0;
 930         unsigned int j = 0;
 931         uint16_t max_elts;
 932         uint16_t max_wqe;
 933         unsigned int comp;
 934         struct mlx5_mpw mpw = {
 935                 .state = MLX5_MPW_STATE_CLOSED,
 936         };
 937
 938         if (unlikely(!pkts_n))
 939                 return 0;
 940         /* Prefetch first packet cacheline. */
 941         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 942         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 943         /* Start processing. */
 944         mlx5_tx_complete(txq);
 945         max_elts = (elts_n - (elts_head - txq->elts_tail));
 946         /* A CQE slot must always be available. */
 947         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 948         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 949         if (unlikely(!max_wqe))
 950                 return 0;
 951         do {
 952                 struct rte_mbuf *buf = *(pkts++);
 953                 uint32_t length;
 954                 unsigned int segs_n = buf->nb_segs;
 955                 uint32_t cs_flags;
 956
 957                 /*
 958                  * Make sure there is enough room to store this packet and
 959                  * that one ring entry remains unused.
 960                  */
 961                 assert(segs_n);
 962                 if (max_elts < segs_n)
 963                         break;
 964                 /* Do not bother with large packets MPW cannot handle. */
 965                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 966                         txq->stats.oerrors++;
 967                         break;
 968                 }
 969                 max_elts -= segs_n;
 970                 --pkts_n;
 971                 cs_flags = txq_ol_cksum_to_cs(buf);
 972                 /* Retrieve packet information. */
 973                 length = PKT_LEN(buf);
 974                 assert(length);
 975                 /* Start new session if packet differs. */
 976                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 977                     ((mpw.len != length) ||
 978                      (segs_n != 1) ||
 979                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 980                         mlx5_mpw_close(txq, &mpw);
 981                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 982                         /*
 983                          * Multi-Packet WQE consumes at most two WQE.
 984                          * mlx5_mpw_new() expects to be able to use such
 985                          * resources.
 986                          */
 987                         if (unlikely(max_wqe < 2))
 988                                 break;
 989                         max_wqe -= 2;
 990                         mlx5_mpw_new(txq, &mpw, length);
 991                         mpw.wqe->eseg.cs_flags = cs_flags;
 992                 }
 993                 /* Multi-segment packets must be alone in their MPW. */
 994                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 995 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 996                 length = 0;
 997 #endif
 998                 do {
 999                         volatile struct mlx5_wqe_data_seg *dseg;
1000                         uintptr_t addr;
1001
1002                         assert(buf);
1003                         (*txq->elts)[elts_head++ & elts_m] = buf;
1004                         dseg = mpw.data.dseg[mpw.pkts_n];
1005                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1006                         *dseg = (struct mlx5_wqe_data_seg){
1007                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1008                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1009                                 .addr = rte_cpu_to_be_64(addr),
1010                         };
1011 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1012                         length += DATA_LEN(buf);
1013 #endif
1014                         buf = buf->next;
1015                         ++mpw.pkts_n;
1016                         ++j;
1017                 } while (--segs_n);
1018                 assert(length == mpw.len);
1019                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1020                         mlx5_mpw_close(txq, &mpw);
1021 #ifdef MLX5_PMD_SOFT_COUNTERS
1022                 /* Increment sent bytes counter. */
1023                 txq->stats.obytes += length;
1024 #endif
1025                 ++i;
1026         } while (pkts_n);
1027         /* Take a shortcut if nothing must be sent. */
1028         if (unlikely(i == 0))
1029                 return 0;
1030         /* Check whether completion threshold has been reached. */
1031         /* "j" includes both packets and segments. */
1032         comp = txq->elts_comp + j;
1033         if (comp >= MLX5_TX_COMP_THRESH) {
1034                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1035
1036                 /* Request completion on last WQE. */
1037                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1038                 /* Save elts_head in unused "immediate" field of WQE. */
1039                 wqe->ctrl[3] = elts_head;
1040                 txq->elts_comp = 0;
1041 #ifndef NDEBUG
1042                 ++txq->cq_pi;
1043 #endif
1044         } else {
1045                 txq->elts_comp = comp;
1046         }
1047 #ifdef MLX5_PMD_SOFT_COUNTERS
1048         /* Increment sent packets counter. */
1049         txq->stats.opackets += i;
1050 #endif
1051         /* Ring QP doorbell. */
1052         if (mpw.state == MLX5_MPW_STATE_OPENED)
1053                 mlx5_mpw_close(txq, &mpw);
1054         mlx5_tx_dbrec(txq, mpw.wqe);
1055         txq->elts_head = elts_head;
1056         return i;
1057 }
1058
1059 /**
1060  * Open a MPW inline session.
1061  *
1062  * @param txq
1063  *   Pointer to TX queue structure.
1064  * @param mpw
1065  *   Pointer to MPW session structure.
1066  * @param length
1067  *   Packet length.
1068  */
1069 static inline void
1070 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1071                     uint32_t length)
1072 {
1073         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1074         struct mlx5_wqe_inl_small *inl;
1075
1076         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1077         mpw->pkts_n = 0;
1078         mpw->len = length;
1079         mpw->total_len = 0;
1080         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1081         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1082                                              (txq->wqe_ci << 8) |
1083                                              MLX5_OPCODE_TSO);
1084         mpw->wqe->ctrl[2] = 0;
1085         mpw->wqe->ctrl[3] = 0;
1086         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1087         mpw->wqe->eseg.inline_hdr_sz = 0;
1088         mpw->wqe->eseg.cs_flags = 0;
1089         mpw->wqe->eseg.rsvd0 = 0;
1090         mpw->wqe->eseg.rsvd1 = 0;
1091         mpw->wqe->eseg.rsvd2 = 0;
1092         inl = (struct mlx5_wqe_inl_small *)
1093                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1094         mpw->data.raw = (uint8_t *)&inl->raw;
1095 }
1096
1097 /**
1098  * Close a MPW inline session.
1099  *
1100  * @param txq
1101  *   Pointer to TX queue structure.
1102  * @param mpw
1103  *   Pointer to MPW session structure.
1104  */
1105 static inline void
1106 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1107 {
1108         unsigned int size;
1109         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1110                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1111
1112         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1113         /*
1114          * Store size in multiple of 16 bytes. Control and Ethernet segments
1115          * count as 2.
1116          */
1117         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1118                                              MLX5_WQE_DS(size));
1119         mpw->state = MLX5_MPW_STATE_CLOSED;
1120         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1121         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1122 }
1123
1124 /**
1125  * DPDK callback for TX with MPW inline support.
1126  *
1127  * @param dpdk_txq
1128  *   Generic pointer to TX queue structure.
1129  * @param[in] pkts
1130  *   Packets to transmit.
1131  * @param pkts_n
1132  *   Number of packets in array.
1133  *
1134  * @return
1135  *   Number of packets successfully transmitted (<= pkts_n).
1136  */
1137 uint16_t
1138 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1139                          uint16_t pkts_n)
1140 {
1141         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1142         uint16_t elts_head = txq->elts_head;
1143         const uint16_t elts_n = 1 << txq->elts_n;
1144         const uint16_t elts_m = elts_n - 1;
1145         unsigned int i = 0;
1146         unsigned int j = 0;
1147         uint16_t max_elts;
1148         uint16_t max_wqe;
1149         unsigned int comp;
1150         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1151         struct mlx5_mpw mpw = {
1152                 .state = MLX5_MPW_STATE_CLOSED,
1153         };
1154         /*
1155          * Compute the maximum number of WQE which can be consumed by inline
1156          * code.
1157          * - 2 DSEG for:
1158          *   - 1 control segment,
1159          *   - 1 Ethernet segment,
1160          * - N Dseg from the inline request.
1161          */
1162         const unsigned int wqe_inl_n =
1163                 ((2 * MLX5_WQE_DWORD_SIZE +
1164                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1165                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1166
1167         if (unlikely(!pkts_n))
1168                 return 0;
1169         /* Prefetch first packet cacheline. */
1170         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1171         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1172         /* Start processing. */
1173         mlx5_tx_complete(txq);
1174         max_elts = (elts_n - (elts_head - txq->elts_tail));
1175         /* A CQE slot must always be available. */
1176         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1177         do {
1178                 struct rte_mbuf *buf = *(pkts++);
1179                 uintptr_t addr;
1180                 uint32_t length;
1181                 unsigned int segs_n = buf->nb_segs;
1182                 uint8_t cs_flags;
1183
1184                 /*
1185                  * Make sure there is enough room to store this packet and
1186                  * that one ring entry remains unused.
1187                  */
1188                 assert(segs_n);
1189                 if (max_elts < segs_n)
1190                         break;
1191                 /* Do not bother with large packets MPW cannot handle. */
1192                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1193                         txq->stats.oerrors++;
1194                         break;
1195                 }
1196                 max_elts -= segs_n;
1197                 --pkts_n;
1198                 /*
1199                  * Compute max_wqe in case less WQE were consumed in previous
1200                  * iteration.
1201                  */
1202                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1203                 cs_flags = txq_ol_cksum_to_cs(buf);
1204                 /* Retrieve packet information. */
1205                 length = PKT_LEN(buf);
1206                 /* Start new session if packet differs. */
1207                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1208                         if ((mpw.len != length) ||
1209                             (segs_n != 1) ||
1210                             (mpw.wqe->eseg.cs_flags != cs_flags))
1211                                 mlx5_mpw_close(txq, &mpw);
1212                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1213                         if ((mpw.len != length) ||
1214                             (segs_n != 1) ||
1215                             (length > inline_room) ||
1216                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1217                                 mlx5_mpw_inline_close(txq, &mpw);
1218                                 inline_room =
1219                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1220                         }
1221                 }
1222                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1223                         if ((segs_n != 1) ||
1224                             (length > inline_room)) {
1225                                 /*
1226                                  * Multi-Packet WQE consumes at most two WQE.
1227                                  * mlx5_mpw_new() expects to be able to use
1228                                  * such resources.
1229                                  */
1230                                 if (unlikely(max_wqe < 2))
1231                                         break;
1232                                 max_wqe -= 2;
1233                                 mlx5_mpw_new(txq, &mpw, length);
1234                                 mpw.wqe->eseg.cs_flags = cs_flags;
1235                         } else {
1236                                 if (unlikely(max_wqe < wqe_inl_n))
1237                                         break;
1238                                 max_wqe -= wqe_inl_n;
1239                                 mlx5_mpw_inline_new(txq, &mpw, length);
1240                                 mpw.wqe->eseg.cs_flags = cs_flags;
1241                         }
1242                 }
1243                 /* Multi-segment packets must be alone in their MPW. */
1244                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1245                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1246                         assert(inline_room ==
1247                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1248 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1249                         length = 0;
1250 #endif
1251                         do {
1252                                 volatile struct mlx5_wqe_data_seg *dseg;
1253
1254                                 assert(buf);
1255                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1256                                 dseg = mpw.data.dseg[mpw.pkts_n];
1257                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1258                                 *dseg = (struct mlx5_wqe_data_seg){
1259                                         .byte_count =
1260                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1261                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1262                                         .addr = rte_cpu_to_be_64(addr),
1263                                 };
1264 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1265                                 length += DATA_LEN(buf);
1266 #endif
1267                                 buf = buf->next;
1268                                 ++mpw.pkts_n;
1269                                 ++j;
1270                         } while (--segs_n);
1271                         assert(length == mpw.len);
1272                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1273                                 mlx5_mpw_close(txq, &mpw);
1274                 } else {
1275                         unsigned int max;
1276
1277                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1278                         assert(length <= inline_room);
1279                         assert(length == DATA_LEN(buf));
1280                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1281                         (*txq->elts)[elts_head++ & elts_m] = buf;
1282                         /* Maximum number of bytes before wrapping. */
1283                         max = ((((uintptr_t)(txq->wqes)) +
1284                                 (1 << txq->wqe_n) *
1285                                 MLX5_WQE_SIZE) -
1286                                (uintptr_t)mpw.data.raw);
1287                         if (length > max) {
1288                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1289                                            (void *)addr,
1290                                            max);
1291                                 mpw.data.raw = (volatile void *)txq->wqes;
1292                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1293                                            (void *)(addr + max),
1294                                            length - max);
1295                                 mpw.data.raw += length - max;
1296                         } else {
1297                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1298                                            (void *)addr,
1299                                            length);
1300
1301                                 if (length == max)
1302                                         mpw.data.raw =
1303                                                 (volatile void *)txq->wqes;
1304                                 else
1305                                         mpw.data.raw += length;
1306                         }
1307                         ++mpw.pkts_n;
1308                         mpw.total_len += length;
1309                         ++j;
1310                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1311                                 mlx5_mpw_inline_close(txq, &mpw);
1312                                 inline_room =
1313                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1314                         } else {
1315                                 inline_room -= length;
1316                         }
1317                 }
1318 #ifdef MLX5_PMD_SOFT_COUNTERS
1319                 /* Increment sent bytes counter. */
1320                 txq->stats.obytes += length;
1321 #endif
1322                 ++i;
1323         } while (pkts_n);
1324         /* Take a shortcut if nothing must be sent. */
1325         if (unlikely(i == 0))
1326                 return 0;
1327         /* Check whether completion threshold has been reached. */
1328         /* "j" includes both packets and segments. */
1329         comp = txq->elts_comp + j;
1330         if (comp >= MLX5_TX_COMP_THRESH) {
1331                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1332
1333                 /* Request completion on last WQE. */
1334                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1335                 /* Save elts_head in unused "immediate" field of WQE. */
1336                 wqe->ctrl[3] = elts_head;
1337                 txq->elts_comp = 0;
1338 #ifndef NDEBUG
1339                 ++txq->cq_pi;
1340 #endif
1341         } else {
1342                 txq->elts_comp = comp;
1343         }
1344 #ifdef MLX5_PMD_SOFT_COUNTERS
1345         /* Increment sent packets counter. */
1346         txq->stats.opackets += i;
1347 #endif
1348         /* Ring QP doorbell. */
1349         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1350                 mlx5_mpw_inline_close(txq, &mpw);
1351         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1352                 mlx5_mpw_close(txq, &mpw);
1353         mlx5_tx_dbrec(txq, mpw.wqe);
1354         txq->elts_head = elts_head;
1355         return i;
1356 }
1357
1358 /**
1359  * Open an Enhanced MPW session.
1360  *
1361  * @param txq
1362  *   Pointer to TX queue structure.
1363  * @param mpw
1364  *   Pointer to MPW session structure.
1365  * @param length
1366  *   Packet length.
1367  */
1368 static inline void
1369 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1370 {
1371         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1372
1373         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1374         mpw->pkts_n = 0;
1375         mpw->total_len = sizeof(struct mlx5_wqe);
1376         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1377         mpw->wqe->ctrl[0] =
1378                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1379                                  (txq->wqe_ci << 8) |
1380                                  MLX5_OPCODE_ENHANCED_MPSW);
1381         mpw->wqe->ctrl[2] = 0;
1382         mpw->wqe->ctrl[3] = 0;
1383         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1384         if (unlikely(padding)) {
1385                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1386
1387                 /* Pad the first 2 DWORDs with zero-length inline header. */
1388                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1389                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1390                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1391                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1392                 /* Start from the next WQEBB. */
1393                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1394         } else {
1395                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1396         }
1397 }
1398
1399 /**
1400  * Close an Enhanced MPW session.
1401  *
1402  * @param txq
1403  *   Pointer to TX queue structure.
1404  * @param mpw
1405  *   Pointer to MPW session structure.
1406  *
1407  * @return
1408  *   Number of consumed WQEs.
1409  */
1410 static inline uint16_t
1411 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1412 {
1413         uint16_t ret;
1414
1415         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1416          * count as 2.
1417          */
1418         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1419                                              MLX5_WQE_DS(mpw->total_len));
1420         mpw->state = MLX5_MPW_STATE_CLOSED;
1421         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1422         txq->wqe_ci += ret;
1423         return ret;
1424 }
1425
1426 /**
1427  * TX with Enhanced MPW support.
1428  *
1429  * @param txq
1430  *   Pointer to TX queue structure.
1431  * @param[in] pkts
1432  *   Packets to transmit.
1433  * @param pkts_n
1434  *   Number of packets in array.
1435  *
1436  * @return
1437  *   Number of packets successfully transmitted (<= pkts_n).
1438  */
1439 static inline uint16_t
1440 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1441                uint16_t pkts_n)
1442 {
1443         uint16_t elts_head = txq->elts_head;
1444         const uint16_t elts_n = 1 << txq->elts_n;
1445         const uint16_t elts_m = elts_n - 1;
1446         unsigned int i = 0;
1447         unsigned int j = 0;
1448         uint16_t max_elts;
1449         uint16_t max_wqe;
1450         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1451         unsigned int mpw_room = 0;
1452         unsigned int inl_pad = 0;
1453         uint32_t inl_hdr;
1454         uint64_t addr_64;
1455         struct mlx5_mpw mpw = {
1456                 .state = MLX5_MPW_STATE_CLOSED,
1457         };
1458
1459         if (unlikely(!pkts_n))
1460                 return 0;
1461         /* Start processing. */
1462         mlx5_tx_complete(txq);
1463         max_elts = (elts_n - (elts_head - txq->elts_tail));
1464         /* A CQE slot must always be available. */
1465         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1466         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1467         if (unlikely(!max_wqe))
1468                 return 0;
1469         do {
1470                 struct rte_mbuf *buf = *(pkts++);
1471                 uintptr_t addr;
1472                 unsigned int do_inline = 0; /* Whether inline is possible. */
1473                 uint32_t length;
1474                 uint8_t cs_flags;
1475
1476                 /* Multi-segmented packet is handled in slow-path outside. */
1477                 assert(NB_SEGS(buf) == 1);
1478                 /* Make sure there is enough room to store this packet. */
1479                 if (max_elts - j == 0)
1480                         break;
1481                 cs_flags = txq_ol_cksum_to_cs(buf);
1482                 /* Retrieve packet information. */
1483                 length = PKT_LEN(buf);
1484                 /* Start new session if:
1485                  * - multi-segment packet
1486                  * - no space left even for a dseg
1487                  * - next packet can be inlined with a new WQE
1488                  * - cs_flag differs
1489                  */
1490                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1491                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1492                              mpw_room) ||
1493                             (length <= txq->inline_max_packet_sz &&
1494                              inl_pad + sizeof(inl_hdr) + length >
1495                              mpw_room) ||
1496                             (mpw.wqe->eseg.cs_flags != cs_flags))
1497                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1498                 }
1499                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1500                         /* In Enhanced MPW, inline as much as the budget is
1501                          * allowed. The remaining space is to be filled with
1502                          * dsegs. If the title WQEBB isn't padded, it will have
1503                          * 2 dsegs there.
1504                          */
1505                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1506                                            (max_inline ? max_inline :
1507                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1508                                            MLX5_WQE_SIZE);
1509                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1510                                 break;
1511                         /* Don't pad the title WQEBB to not waste WQ. */
1512                         mlx5_empw_new(txq, &mpw, 0);
1513                         mpw_room -= mpw.total_len;
1514                         inl_pad = 0;
1515                         do_inline = length <= txq->inline_max_packet_sz &&
1516                                     sizeof(inl_hdr) + length <= mpw_room &&
1517                                     !txq->mpw_hdr_dseg;
1518                         mpw.wqe->eseg.cs_flags = cs_flags;
1519                 } else {
1520                         /* Evaluate whether the next packet can be inlined.
1521                          * Inlininig is possible when:
1522                          * - length is less than configured value
1523                          * - length fits for remaining space
1524                          * - not required to fill the title WQEBB with dsegs
1525                          */
1526                         do_inline =
1527                                 length <= txq->inline_max_packet_sz &&
1528                                 inl_pad + sizeof(inl_hdr) + length <=
1529                                  mpw_room &&
1530                                 (!txq->mpw_hdr_dseg ||
1531                                  mpw.total_len >= MLX5_WQE_SIZE);
1532                 }
1533                 if (max_inline && do_inline) {
1534                         /* Inline packet into WQE. */
1535                         unsigned int max;
1536
1537                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1538                         assert(length == DATA_LEN(buf));
1539                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1540                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1541                         mpw.data.raw = (volatile void *)
1542                                 ((uintptr_t)mpw.data.raw + inl_pad);
1543                         max = tx_mlx5_wq_tailroom(txq,
1544                                         (void *)(uintptr_t)mpw.data.raw);
1545                         /* Copy inline header. */
1546                         mpw.data.raw = (volatile void *)
1547                                 mlx5_copy_to_wq(
1548                                           (void *)(uintptr_t)mpw.data.raw,
1549                                           &inl_hdr,
1550                                           sizeof(inl_hdr),
1551                                           (void *)(uintptr_t)txq->wqes,
1552                                           max);
1553                         max = tx_mlx5_wq_tailroom(txq,
1554                                         (void *)(uintptr_t)mpw.data.raw);
1555                         /* Copy packet data. */
1556                         mpw.data.raw = (volatile void *)
1557                                 mlx5_copy_to_wq(
1558                                           (void *)(uintptr_t)mpw.data.raw,
1559                                           (void *)addr,
1560                                           length,
1561                                           (void *)(uintptr_t)txq->wqes,
1562                                           max);
1563                         ++mpw.pkts_n;
1564                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1565                         /* No need to get completion as the entire packet is
1566                          * copied to WQ. Free the buf right away.
1567                          */
1568                         rte_pktmbuf_free_seg(buf);
1569                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1570                         /* Add pad in the next packet if any. */
1571                         inl_pad = (((uintptr_t)mpw.data.raw +
1572                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1573                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1574                                   (uintptr_t)mpw.data.raw;
1575                 } else {
1576                         /* No inline. Load a dseg of packet pointer. */
1577                         volatile rte_v128u32_t *dseg;
1578
1579                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1580                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1581                         assert(length == DATA_LEN(buf));
1582                         if (!tx_mlx5_wq_tailroom(txq,
1583                                         (void *)((uintptr_t)mpw.data.raw
1584                                                 + inl_pad)))
1585                                 dseg = (volatile void *)txq->wqes;
1586                         else
1587                                 dseg = (volatile void *)
1588                                         ((uintptr_t)mpw.data.raw +
1589                                          inl_pad);
1590                         (*txq->elts)[elts_head++ & elts_m] = buf;
1591                         addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1592                                                                     uintptr_t));
1593                         *dseg = (rte_v128u32_t) {
1594                                 rte_cpu_to_be_32(length),
1595                                 mlx5_tx_mb2mr(txq, buf),
1596                                 addr_64,
1597                                 addr_64 >> 32,
1598                         };
1599                         mpw.data.raw = (volatile void *)(dseg + 1);
1600                         mpw.total_len += (inl_pad + sizeof(*dseg));
1601                         ++j;
1602                         ++mpw.pkts_n;
1603                         mpw_room -= (inl_pad + sizeof(*dseg));
1604                         inl_pad = 0;
1605                 }
1606 #ifdef MLX5_PMD_SOFT_COUNTERS
1607                 /* Increment sent bytes counter. */
1608                 txq->stats.obytes += length;
1609 #endif
1610                 ++i;
1611         } while (i < pkts_n);
1612         /* Take a shortcut if nothing must be sent. */
1613         if (unlikely(i == 0))
1614                 return 0;
1615         /* Check whether completion threshold has been reached. */
1616         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1617                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1618                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1619                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1620
1621                 /* Request completion on last WQE. */
1622                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1623                 /* Save elts_head in unused "immediate" field of WQE. */
1624                 wqe->ctrl[3] = elts_head;
1625                 txq->elts_comp = 0;
1626                 txq->mpw_comp = txq->wqe_ci;
1627 #ifndef NDEBUG
1628                 ++txq->cq_pi;
1629 #endif
1630         } else {
1631                 txq->elts_comp += j;
1632         }
1633 #ifdef MLX5_PMD_SOFT_COUNTERS
1634         /* Increment sent packets counter. */
1635         txq->stats.opackets += i;
1636 #endif
1637         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1638                 mlx5_empw_close(txq, &mpw);
1639         /* Ring QP doorbell. */
1640         mlx5_tx_dbrec(txq, mpw.wqe);
1641         txq->elts_head = elts_head;
1642         return i;
1643 }
1644
1645 /**
1646  * DPDK callback for TX with Enhanced MPW support.
1647  *
1648  * @param dpdk_txq
1649  *   Generic pointer to TX queue structure.
1650  * @param[in] pkts
1651  *   Packets to transmit.
1652  * @param pkts_n
1653  *   Number of packets in array.
1654  *
1655  * @return
1656  *   Number of packets successfully transmitted (<= pkts_n).
1657  */
1658 uint16_t
1659 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1660 {
1661         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1662         uint16_t nb_tx = 0;
1663
1664         while (pkts_n > nb_tx) {
1665                 uint16_t n;
1666                 uint16_t ret;
1667
1668                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1669                 if (n) {
1670                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1671                         if (!ret)
1672                                 break;
1673                         nb_tx += ret;
1674                 }
1675                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1676                 if (n) {
1677                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1678                         if (!ret)
1679                                 break;
1680                         nb_tx += ret;
1681                 }
1682         }
1683         return nb_tx;
1684 }
1685
1686 /**
1687  * Translate RX completion flags to packet type.
1688  *
1689  * @param[in] rxq
1690  *   Pointer to RX queue structure.
1691  * @param[in] cqe
1692  *   Pointer to CQE.
1693  *
1694  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1695  *
1696  * @return
1697  *   Packet type for struct rte_mbuf.
1698  */
1699 static inline uint32_t
1700 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1701 {
1702         uint8_t idx;
1703         uint8_t pinfo = cqe->pkt_info;
1704         uint16_t ptype = cqe->hdr_type_etc;
1705
1706         /*
1707          * The index to the array should have:
1708          * bit[1:0] = l3_hdr_type
1709          * bit[4:2] = l4_hdr_type
1710          * bit[5] = ip_frag
1711          * bit[6] = tunneled
1712          * bit[7] = outer_l3_type
1713          */
1714         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1715         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1716 }
1717
1718 /**
1719  * Get size of the next packet for a given CQE. For compressed CQEs, the
1720  * consumer index is updated only once all packets of the current one have
1721  * been processed.
1722  *
1723  * @param rxq
1724  *   Pointer to RX queue.
1725  * @param cqe
1726  *   CQE to process.
1727  * @param[out] mcqe
1728  *   Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1729  *   written.
1730  *
1731  * @return
1732  *   Packet size in bytes (0 if there is none), -1 in case of completion
1733  *   with error.
1734  */
1735 static inline int
1736 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1737                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1738 {
1739         struct rxq_zip *zip = &rxq->zip;
1740         uint16_t cqe_n = cqe_cnt + 1;
1741         int len = 0;
1742         uint16_t idx, end;
1743
1744         /* Process compressed data in the CQE and mini arrays. */
1745         if (zip->ai) {
1746                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1747                         (volatile struct mlx5_mini_cqe8 (*)[8])
1748                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1749
1750                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1751                 *mcqe = &(*mc)[zip->ai & 7];
1752                 if ((++zip->ai & 7) == 0) {
1753                         /* Invalidate consumed CQEs */
1754                         idx = zip->ca;
1755                         end = zip->na;
1756                         while (idx != end) {
1757                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1758                                         MLX5_CQE_INVALIDATE;
1759                                 ++idx;
1760                         }
1761                         /*
1762                          * Increment consumer index to skip the number of
1763                          * CQEs consumed. Hardware leaves holes in the CQ
1764                          * ring for software use.
1765                          */
1766                         zip->ca = zip->na;
1767                         zip->na += 8;
1768                 }
1769                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1770                         /* Invalidate the rest */
1771                         idx = zip->ca;
1772                         end = zip->cq_ci;
1773
1774                         while (idx != end) {
1775                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1776                                         MLX5_CQE_INVALIDATE;
1777                                 ++idx;
1778                         }
1779                         rxq->cq_ci = zip->cq_ci;
1780                         zip->ai = 0;
1781                 }
1782         /* No compressed data, get next CQE and verify if it is compressed. */
1783         } else {
1784                 int ret;
1785                 int8_t op_own;
1786
1787                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1788                 if (unlikely(ret == 1))
1789                         return 0;
1790                 ++rxq->cq_ci;
1791                 op_own = cqe->op_own;
1792                 rte_cio_rmb();
1793                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1794                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1795                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1796                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1797                                                           cqe_cnt].pkt_info);
1798
1799                         /* Fix endianness. */
1800                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1801                         /*
1802                          * Current mini array position is the one returned by
1803                          * check_cqe64().
1804                          *
1805                          * If completion comprises several mini arrays, as a
1806                          * special case the second one is located 7 CQEs after
1807                          * the initial CQE instead of 8 for subsequent ones.
1808                          */
1809                         zip->ca = rxq->cq_ci;
1810                         zip->na = zip->ca + 7;
1811                         /* Compute the next non compressed CQE. */
1812                         --rxq->cq_ci;
1813                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1814                         /* Get packet size to return. */
1815                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1816                         *mcqe = &(*mc)[0];
1817                         zip->ai = 1;
1818                         /* Prefetch all the entries to be invalidated */
1819                         idx = zip->ca;
1820                         end = zip->cq_ci;
1821                         while (idx != end) {
1822                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1823                                 ++idx;
1824                         }
1825                 } else {
1826                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1827                 }
1828                 /* Error while receiving packet. */
1829                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1830                         return -1;
1831         }
1832         return len;
1833 }
1834
1835 /**
1836  * Translate RX completion flags to offload flags.
1837  *
1838  * @param[in] cqe
1839  *   Pointer to CQE.
1840  *
1841  * @return
1842  *   Offload flags (ol_flags) for struct rte_mbuf.
1843  */
1844 static inline uint32_t
1845 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1846 {
1847         uint32_t ol_flags = 0;
1848         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1849
1850         ol_flags =
1851                 TRANSPOSE(flags,
1852                           MLX5_CQE_RX_L3_HDR_VALID,
1853                           PKT_RX_IP_CKSUM_GOOD) |
1854                 TRANSPOSE(flags,
1855                           MLX5_CQE_RX_L4_HDR_VALID,
1856                           PKT_RX_L4_CKSUM_GOOD);
1857         return ol_flags;
1858 }
1859
1860 /**
1861  * Fill in mbuf fields from RX completion flags.
1862  * Note that pkt->ol_flags should be initialized outside of this function.
1863  *
1864  * @param rxq
1865  *   Pointer to RX queue.
1866  * @param pkt
1867  *   mbuf to fill.
1868  * @param cqe
1869  *   CQE to process.
1870  * @param rss_hash_res
1871  *   Packet RSS Hash result.
1872  */
1873 static inline void
1874 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1875                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1876 {
1877         /* Update packet information. */
1878         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1879         if (rss_hash_res && rxq->rss_hash) {
1880                 pkt->hash.rss = rss_hash_res;
1881                 pkt->ol_flags |= PKT_RX_RSS_HASH;
1882         }
1883         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1884                 pkt->ol_flags |= PKT_RX_FDIR;
1885                 if (cqe->sop_drop_qpn !=
1886                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1887                         uint32_t mark = cqe->sop_drop_qpn;
1888
1889                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1890                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1891                 }
1892         }
1893         if (rxq->csum)
1894                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1895         if (rxq->vlan_strip &&
1896             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1897                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1898                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1899         }
1900         if (rxq->hw_timestamp) {
1901                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1902                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1903         }
1904 }
1905
1906 /**
1907  * DPDK callback for RX.
1908  *
1909  * @param dpdk_rxq
1910  *   Generic pointer to RX queue structure.
1911  * @param[out] pkts
1912  *   Array to store received packets.
1913  * @param pkts_n
1914  *   Maximum number of packets in array.
1915  *
1916  * @return
1917  *   Number of packets successfully received (<= pkts_n).
1918  */
1919 uint16_t
1920 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1921 {
1922         struct mlx5_rxq_data *rxq = dpdk_rxq;
1923         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1924         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1925         const unsigned int sges_n = rxq->sges_n;
1926         struct rte_mbuf *pkt = NULL;
1927         struct rte_mbuf *seg = NULL;
1928         volatile struct mlx5_cqe *cqe =
1929                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1930         unsigned int i = 0;
1931         unsigned int rq_ci = rxq->rq_ci << sges_n;
1932         int len = 0; /* keep its value across iterations. */
1933
1934         while (pkts_n) {
1935                 unsigned int idx = rq_ci & wqe_cnt;
1936                 volatile struct mlx5_wqe_data_seg *wqe =
1937                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1938                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1939                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1940                 uint32_t rss_hash_res;
1941
1942                 if (pkt)
1943                         NEXT(seg) = rep;
1944                 seg = rep;
1945                 rte_prefetch0(seg);
1946                 rte_prefetch0(cqe);
1947                 rte_prefetch0(wqe);
1948                 rep = rte_mbuf_raw_alloc(rxq->mp);
1949                 if (unlikely(rep == NULL)) {
1950                         ++rxq->stats.rx_nombuf;
1951                         if (!pkt) {
1952                                 /*
1953                                  * no buffers before we even started,
1954                                  * bail out silently.
1955                                  */
1956                                 break;
1957                         }
1958                         while (pkt != seg) {
1959                                 assert(pkt != (*rxq->elts)[idx]);
1960                                 rep = NEXT(pkt);
1961                                 NEXT(pkt) = NULL;
1962                                 NB_SEGS(pkt) = 1;
1963                                 rte_mbuf_raw_free(pkt);
1964                                 pkt = rep;
1965                         }
1966                         break;
1967                 }
1968                 if (!pkt) {
1969                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1970                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1971                         if (!len) {
1972                                 rte_mbuf_raw_free(rep);
1973                                 break;
1974                         }
1975                         if (unlikely(len == -1)) {
1976                                 /* RX error, packet is likely too large. */
1977                                 rte_mbuf_raw_free(rep);
1978                                 ++rxq->stats.idropped;
1979                                 goto skip;
1980                         }
1981                         pkt = seg;
1982                         assert(len >= (rxq->crc_present << 2));
1983                         pkt->ol_flags = 0;
1984                         /* If compressed, take hash result from mini-CQE. */
1985                         rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1986                                                         cqe->rx_hash_res :
1987                                                         mcqe->rx_hash_result);
1988                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1989                         if (rxq->crc_present)
1990                                 len -= ETHER_CRC_LEN;
1991                         PKT_LEN(pkt) = len;
1992                 }
1993                 DATA_LEN(rep) = DATA_LEN(seg);
1994                 PKT_LEN(rep) = PKT_LEN(seg);
1995                 SET_DATA_OFF(rep, DATA_OFF(seg));
1996                 PORT(rep) = PORT(seg);
1997                 (*rxq->elts)[idx] = rep;
1998                 /*
1999                  * Fill NIC descriptor with the new buffer.  The lkey and size
2000                  * of the buffers are already known, only the buffer address
2001                  * changes.
2002                  */
2003                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2004                 /* If there's only one MR, no need to replace LKey in WQE. */
2005                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2006                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2007                 if (len > DATA_LEN(seg)) {
2008                         len -= DATA_LEN(seg);
2009                         ++NB_SEGS(pkt);
2010                         ++rq_ci;
2011                         continue;
2012                 }
2013                 DATA_LEN(seg) = len;
2014 #ifdef MLX5_PMD_SOFT_COUNTERS
2015                 /* Increment bytes counter. */
2016                 rxq->stats.ibytes += PKT_LEN(pkt);
2017 #endif
2018                 /* Return packet. */
2019                 *(pkts++) = pkt;
2020                 pkt = NULL;
2021                 --pkts_n;
2022                 ++i;
2023 skip:
2024                 /* Align consumer index to the next stride. */
2025                 rq_ci >>= sges_n;
2026                 ++rq_ci;
2027                 rq_ci <<= sges_n;
2028         }
2029         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2030                 return 0;
2031         /* Update the consumer index. */
2032         rxq->rq_ci = rq_ci >> sges_n;
2033         rte_cio_wmb();
2034         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2035         rte_cio_wmb();
2036         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2037 #ifdef MLX5_PMD_SOFT_COUNTERS
2038         /* Increment packets counter. */
2039         rxq->stats.ipackets += i;
2040 #endif
2041         return i;
2042 }
2043
2044 void
2045 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2046 {
2047         struct mlx5_mprq_buf *buf = opaque;
2048
2049         if (rte_atomic16_read(&buf->refcnt) == 1) {
2050                 rte_mempool_put(buf->mp, buf);
2051         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2052                 rte_atomic16_set(&buf->refcnt, 1);
2053                 rte_mempool_put(buf->mp, buf);
2054         }
2055 }
2056
2057 void
2058 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2059 {
2060         mlx5_mprq_buf_free_cb(NULL, buf);
2061 }
2062
2063 static inline void
2064 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2065 {
2066         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2067         volatile struct mlx5_wqe_data_seg *wqe =
2068                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2069         void *addr;
2070
2071         assert(rep != NULL);
2072         /* Replace MPRQ buf. */
2073         (*rxq->mprq_bufs)[rq_idx] = rep;
2074         /* Replace WQE. */
2075         addr = mlx5_mprq_buf_addr(rep);
2076         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2077         /* If there's only one MR, no need to replace LKey in WQE. */
2078         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2079                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2080         /* Stash a mbuf for next replacement. */
2081         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2082                 rxq->mprq_repl = rep;
2083         else
2084                 rxq->mprq_repl = NULL;
2085 }
2086
2087 /**
2088  * DPDK callback for RX with Multi-Packet RQ support.
2089  *
2090  * @param dpdk_rxq
2091  *   Generic pointer to RX queue structure.
2092  * @param[out] pkts
2093  *   Array to store received packets.
2094  * @param pkts_n
2095  *   Maximum number of packets in array.
2096  *
2097  * @return
2098  *   Number of packets successfully received (<= pkts_n).
2099  */
2100 uint16_t
2101 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2102 {
2103         struct mlx5_rxq_data *rxq = dpdk_rxq;
2104         const unsigned int strd_n = 1 << rxq->strd_num_n;
2105         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2106         const unsigned int strd_shift =
2107                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2108         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2109         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2110         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2111         unsigned int i = 0;
2112         uint16_t rq_ci = rxq->rq_ci;
2113         uint16_t consumed_strd = rxq->consumed_strd;
2114         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2115
2116         while (i < pkts_n) {
2117                 struct rte_mbuf *pkt;
2118                 void *addr;
2119                 int ret;
2120                 unsigned int len;
2121                 uint16_t strd_cnt;
2122                 uint16_t strd_idx;
2123                 uint32_t offset;
2124                 uint32_t byte_cnt;
2125                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2126                 uint32_t rss_hash_res = 0;
2127
2128                 if (consumed_strd == strd_n) {
2129                         /* Replace WQE only if the buffer is still in use. */
2130                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2131                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2132                                 /* Release the old buffer. */
2133                                 mlx5_mprq_buf_free(buf);
2134                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2135                                 struct mlx5_mprq_buf *rep;
2136
2137                                 /*
2138                                  * Currently, the MPRQ mempool is out of buffer
2139                                  * and doing memcpy regardless of the size of Rx
2140                                  * packet. Retry allocation to get back to
2141                                  * normal.
2142                                  */
2143                                 if (!rte_mempool_get(rxq->mprq_mp,
2144                                                      (void **)&rep))
2145                                         rxq->mprq_repl = rep;
2146                         }
2147                         /* Advance to the next WQE. */
2148                         consumed_strd = 0;
2149                         ++rq_ci;
2150                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2151                 }
2152                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2153                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2154                 if (!ret)
2155                         break;
2156                 if (unlikely(ret == -1)) {
2157                         /* RX error, packet is likely too large. */
2158                         ++rxq->stats.idropped;
2159                         continue;
2160                 }
2161                 byte_cnt = ret;
2162                 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2163                            MLX5_MPRQ_STRIDE_NUM_SHIFT;
2164                 assert(strd_cnt);
2165                 consumed_strd += strd_cnt;
2166                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2167                         continue;
2168                 if (mcqe == NULL) {
2169                         rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2170                         strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2171                 } else {
2172                         /* mini-CQE for MPRQ doesn't have hash result. */
2173                         strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2174                 }
2175                 assert(strd_idx < strd_n);
2176                 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2177                 /*
2178                  * Currently configured to receive a packet per a stride. But if
2179                  * MTU is adjusted through kernel interface, device could
2180                  * consume multiple strides without raising an error. In this
2181                  * case, the packet should be dropped because it is bigger than
2182                  * the max_rx_pkt_len.
2183                  */
2184                 if (unlikely(strd_cnt > 1)) {
2185                         ++rxq->stats.idropped;
2186                         continue;
2187                 }
2188                 pkt = rte_pktmbuf_alloc(rxq->mp);
2189                 if (unlikely(pkt == NULL)) {
2190                         ++rxq->stats.rx_nombuf;
2191                         break;
2192                 }
2193                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2194                 assert((int)len >= (rxq->crc_present << 2));
2195                 if (rxq->crc_present)
2196                         len -= ETHER_CRC_LEN;
2197                 offset = strd_idx * strd_sz + strd_shift;
2198                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2199                 /* Initialize the offload flag. */
2200                 pkt->ol_flags = 0;
2201                 /*
2202                  * Memcpy packets to the target mbuf if:
2203                  * - The size of packet is smaller than mprq_max_memcpy_len.
2204                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2205                  */
2206                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2207                         /*
2208                          * When memcpy'ing packet due to out-of-buffer, the
2209                          * packet must be smaller than the target mbuf.
2210                          */
2211                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2212                                 rte_pktmbuf_free_seg(pkt);
2213                                 ++rxq->stats.idropped;
2214                                 continue;
2215                         }
2216                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2217                 } else {
2218                         rte_iova_t buf_iova;
2219                         struct rte_mbuf_ext_shared_info *shinfo;
2220                         uint16_t buf_len = strd_cnt * strd_sz;
2221
2222                         /* Increment the refcnt of the whole chunk. */
2223                         rte_atomic16_add_return(&buf->refcnt, 1);
2224                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2225                                strd_n + 1);
2226                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2227                         /*
2228                          * MLX5 device doesn't use iova but it is necessary in a
2229                          * case where the Rx packet is transmitted via a
2230                          * different PMD.
2231                          */
2232                         buf_iova = rte_mempool_virt2iova(buf) +
2233                                    RTE_PTR_DIFF(addr, buf);
2234                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2235                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2236                         /*
2237                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2238                          * attaching the stride to mbuf and more offload flags
2239                          * will be added below by calling rxq_cq_to_mbuf().
2240                          * Other fields will be overwritten.
2241                          */
2242                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2243                                                   shinfo);
2244                         rte_pktmbuf_reset_headroom(pkt);
2245                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2246                         /*
2247                          * Prevent potential overflow due to MTU change through
2248                          * kernel interface.
2249                          */
2250                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2251                                 rte_pktmbuf_free_seg(pkt);
2252                                 ++rxq->stats.idropped;
2253                                 continue;
2254                         }
2255                 }
2256                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2257                 PKT_LEN(pkt) = len;
2258                 DATA_LEN(pkt) = len;
2259                 PORT(pkt) = rxq->port_id;
2260 #ifdef MLX5_PMD_SOFT_COUNTERS
2261                 /* Increment bytes counter. */
2262                 rxq->stats.ibytes += PKT_LEN(pkt);
2263 #endif
2264                 /* Return packet. */
2265                 *(pkts++) = pkt;
2266                 ++i;
2267         }
2268         /* Update the consumer indexes. */
2269         rxq->consumed_strd = consumed_strd;
2270         rte_cio_wmb();
2271         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2272         if (rq_ci != rxq->rq_ci) {
2273                 rxq->rq_ci = rq_ci;
2274                 rte_cio_wmb();
2275                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2276         }
2277 #ifdef MLX5_PMD_SOFT_COUNTERS
2278         /* Increment packets counter. */
2279         rxq->stats.ipackets += i;
2280 #endif
2281         return i;
2282 }
2283
2284 /**
2285  * Dummy DPDK callback for TX.
2286  *
2287  * This function is used to temporarily replace the real callback during
2288  * unsafe control operations on the queue, or in case of error.
2289  *
2290  * @param dpdk_txq
2291  *   Generic pointer to TX queue structure.
2292  * @param[in] pkts
2293  *   Packets to transmit.
2294  * @param pkts_n
2295  *   Number of packets in array.
2296  *
2297  * @return
2298  *   Number of packets successfully transmitted (<= pkts_n).
2299  */
2300 uint16_t
2301 removed_tx_burst(void *dpdk_txq __rte_unused,
2302                  struct rte_mbuf **pkts __rte_unused,
2303                  uint16_t pkts_n __rte_unused)
2304 {
2305         return 0;
2306 }
2307
2308 /**
2309  * Dummy DPDK callback for RX.
2310  *
2311  * This function is used to temporarily replace the real callback during
2312  * unsafe control operations on the queue, or in case of error.
2313  *
2314  * @param dpdk_rxq
2315  *   Generic pointer to RX queue structure.
2316  * @param[out] pkts
2317  *   Array to store received packets.
2318  * @param pkts_n
2319  *   Maximum number of packets in array.
2320  *
2321  * @return
2322  *   Number of packets successfully received (<= pkts_n).
2323  */
2324 uint16_t
2325 removed_rx_burst(void *dpdk_txq __rte_unused,
2326                  struct rte_mbuf **pkts __rte_unused,
2327                  uint16_t pkts_n __rte_unused)
2328 {
2329         return 0;
2330 }
2331
2332 /*
2333  * Vectorized Rx/Tx routines are not compiled in when required vector
2334  * instructions are not supported on a target architecture. The following null
2335  * stubs are needed for linkage when those are not included outside of this file
2336  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2337  */
2338
2339 uint16_t __attribute__((weak))
2340 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2341                       struct rte_mbuf **pkts __rte_unused,
2342                       uint16_t pkts_n __rte_unused)
2343 {
2344         return 0;
2345 }
2346
2347 uint16_t __attribute__((weak))
2348 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2349                   struct rte_mbuf **pkts __rte_unused,
2350                   uint16_t pkts_n __rte_unused)
2351 {
2352         return 0;
2353 }
2354
2355 uint16_t __attribute__((weak))
2356 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2357                   struct rte_mbuf **pkts __rte_unused,
2358                   uint16_t pkts_n __rte_unused)
2359 {
2360         return 0;
2361 }
2362
2363 int __attribute__((weak))
2364 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2365 {
2366         return -ENOTSUP;
2367 }
2368
2369 int __attribute__((weak))
2370 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2371 {
2372         return -ENOTSUP;
2373 }
2374
2375 int __attribute__((weak))
2376 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2377 {
2378         return -ENOTSUP;
2379 }
2380
2381 int __attribute__((weak))
2382 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2383 {
2384         return -ENOTSUP;
2385 }