drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci)
  75           __attribute__((always_inline));
  76
  77 static inline void
  78 txq_complete(struct txq *txq) __attribute__((always_inline));
  79
  80 static inline uint32_t
  81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
  82         __attribute__((always_inline));
  83
  84 static inline void
  85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
  86         __attribute__((always_inline));
  87
  88 static inline uint32_t
  89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
  90         __attribute__((always_inline));
  91
  92 static inline int
  93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  94                  uint16_t cqe_cnt, uint32_t *rss_hash)
  95                  __attribute__((always_inline));
  96
  97 static inline uint32_t
  98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
  99                    __attribute__((always_inline));
 100
 101 #ifndef NDEBUG
 102
 103 /**
 104  * Verify or set magic value in CQE.
 105  *
 106  * @param cqe
 107  *   Pointer to CQE.
 108  *
 109  * @return
 110  *   0 the first time.
 111  */
 112 static inline int
 113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 114 {
 115         static const uint8_t magic[] = "seen";
 116         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 117         int ret = 1;
 118         unsigned int i;
 119
 120         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 121                 if (!ret || (*buf)[i] != magic[i]) {
 122                         ret = 0;
 123                         (*buf)[i] = magic[i];
 124                 }
 125         return ret;
 126 }
 127
 128 #endif /* NDEBUG */
 129
 130 /**
 131  * Check whether CQE is valid.
 132  *
 133  * @param cqe
 134  *   Pointer to CQE.
 135  * @param cqes_n
 136  *   Size of completion queue.
 137  * @param ci
 138  *   Consumer index.
 139  *
 140  * @return
 141  *   0 on success, 1 on failure.
 142  */
 143 static inline int
 144 check_cqe(volatile struct mlx5_cqe *cqe,
 145           unsigned int cqes_n, const uint16_t ci)
 146 {
 147         uint16_t idx = ci & cqes_n;
 148         uint8_t op_own = cqe->op_own;
 149         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 150         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 151
 152         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 153                 return 1; /* No CQE. */
 154 #ifndef NDEBUG
 155         if ((op_code == MLX5_CQE_RESP_ERR) ||
 156             (op_code == MLX5_CQE_REQ_ERR)) {
 157                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 158                 uint8_t syndrome = err_cqe->syndrome;
 159
 160                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 161                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 162                         return 0;
 163                 if (!check_cqe_seen(cqe))
 164                         ERROR("unexpected CQE error %u (0x%02x)"
 165                               " syndrome 0x%02x",
 166                               op_code, op_code, syndrome);
 167                 return 1;
 168         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 169                    (op_code != MLX5_CQE_REQ)) {
 170                 if (!check_cqe_seen(cqe))
 171                         ERROR("unexpected CQE opcode %u (0x%02x)",
 172                               op_code, op_code);
 173                 return 1;
 174         }
 175 #endif /* NDEBUG */
 176         return 0;
 177 }
 178
 179 /**
 180  * Return the address of the WQE.
 181  *
 182  * @param txq
 183  *   Pointer to TX queue structure.
 184  * @param  wqe_ci
 185  *   WQE consumer index.
 186  *
 187  * @return
 188  *   WQE address.
 189  */
 190 static inline uintptr_t *
 191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 192 {
 193         ci &= ((1 << txq->wqe_n) - 1);
 194         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 195 }
 196
 197 /**
 198  * Return the size of tailroom of WQ.
 199  *
 200  * @param txq
 201  *   Pointer to TX queue structure.
 202  * @param addr
 203  *   Pointer to tail of WQ.
 204  *
 205  * @return
 206  *   Size of tailroom.
 207  */
 208 static inline size_t
 209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 210 {
 211         size_t tailroom;
 212         tailroom = (uintptr_t)(txq->wqes) +
 213                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 214                    (uintptr_t)addr;
 215         return tailroom;
 216 }
 217
 218 /**
 219  * Copy data to tailroom of circular queue.
 220  *
 221  * @param dst
 222  *   Pointer to destination.
 223  * @param src
 224  *   Pointer to source.
 225  * @param n
 226  *   Number of bytes to copy.
 227  * @param base
 228  *   Pointer to head of queue.
 229  * @param tailroom
 230  *   Size of tailroom from dst.
 231  *
 232  * @return
 233  *   Pointer after copied data.
 234  */
 235 static inline void *
 236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 237                 void *base, size_t tailroom)
 238 {
 239         void *ret;
 240
 241         if (n > tailroom) {
 242                 rte_memcpy(dst, src, tailroom);
 243                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 244                            n - tailroom);
 245                 ret = (uint8_t *)base + n - tailroom;
 246         } else {
 247                 rte_memcpy(dst, src, n);
 248                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 249         }
 250         return ret;
 251 }
 252
 253 /**
 254  * Manage TX completions.
 255  *
 256  * When sending a burst, mlx5_tx_burst() posts several WRs.
 257  *
 258  * @param txq
 259  *   Pointer to TX queue structure.
 260  */
 261 static inline void
 262 txq_complete(struct txq *txq)
 263 {
 264         const unsigned int elts_n = 1 << txq->elts_n;
 265         const unsigned int cqe_n = 1 << txq->cqe_n;
 266         const unsigned int cqe_cnt = cqe_n - 1;
 267         uint16_t elts_free = txq->elts_tail;
 268         uint16_t elts_tail;
 269         uint16_t cq_ci = txq->cq_ci;
 270         volatile struct mlx5_cqe *cqe = NULL;
 271         volatile struct mlx5_wqe_ctrl *ctrl;
 272
 273         do {
 274                 volatile struct mlx5_cqe *tmp;
 275
 276                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 277                 if (check_cqe(tmp, cqe_n, cq_ci))
 278                         break;
 279                 cqe = tmp;
 280 #ifndef NDEBUG
 281                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 282                         if (!check_cqe_seen(cqe))
 283                                 ERROR("unexpected compressed CQE, TX stopped");
 284                         return;
 285                 }
 286                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 287                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 288                         if (!check_cqe_seen(cqe))
 289                                 ERROR("unexpected error CQE, TX stopped");
 290                         return;
 291                 }
 292 #endif /* NDEBUG */
 293                 ++cq_ci;
 294         } while (1);
 295         if (unlikely(cqe == NULL))
 296                 return;
 297         txq->wqe_pi = ntohs(cqe->wqe_counter);
 298         ctrl = (volatile struct mlx5_wqe_ctrl *)
 299                 tx_mlx5_wqe(txq, txq->wqe_pi);
 300         elts_tail = ctrl->ctrl3;
 301         assert(elts_tail < (1 << txq->wqe_n));
 302         /* Free buffers. */
 303         while (elts_free != elts_tail) {
 304                 struct rte_mbuf *elt = (*txq->elts)[elts_free];
 305                 unsigned int elts_free_next =
 306                         (elts_free + 1) & (elts_n - 1);
 307                 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
 308
 309 #ifndef NDEBUG
 310                 /* Poisoning. */
 311                 memset(&(*txq->elts)[elts_free],
 312                        0x66,
 313                        sizeof((*txq->elts)[elts_free]));
 314 #endif
 315                 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
 316                 /* Only one segment needs to be freed. */
 317                 rte_pktmbuf_free_seg(elt);
 318                 elts_free = elts_free_next;
 319         }
 320         txq->cq_ci = cq_ci;
 321         txq->elts_tail = elts_tail;
 322         /* Update the consumer index. */
 323         rte_wmb();
 324         *txq->cq_db = htonl(cq_ci);
 325 }
 326
 327 /**
 328  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 329  * the cloned mbuf is allocated is returned instead.
 330  *
 331  * @param buf
 332  *   Pointer to mbuf.
 333  *
 334  * @return
 335  *   Memory pool where data is located for given mbuf.
 336  */
 337 static struct rte_mempool *
 338 txq_mb2mp(struct rte_mbuf *buf)
 339 {
 340         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 341                 return rte_mbuf_from_indirect(buf)->pool;
 342         return buf->pool;
 343 }
 344
 345 /**
 346  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 347  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 348  * remove an entry first.
 349  *
 350  * @param txq
 351  *   Pointer to TX queue structure.
 352  * @param[in] mp
 353  *   Memory Pool for which a Memory Region lkey must be returned.
 354  *
 355  * @return
 356  *   mr->lkey on success, (uint32_t)-1 on failure.
 357  */
 358 static inline uint32_t
 359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 360 {
 361         unsigned int i;
 362         uint32_t lkey = (uint32_t)-1;
 363
 364         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 365                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 366                         /* Unknown MP, add a new MR for it. */
 367                         break;
 368                 }
 369                 if (txq->mp2mr[i].mp == mp) {
 370                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 371                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 372                                txq->mp2mr[i].lkey);
 373                         lkey = txq->mp2mr[i].lkey;
 374                         break;
 375                 }
 376         }
 377         if (unlikely(lkey == (uint32_t)-1))
 378                 lkey = txq_mp2mr_reg(txq, mp, i);
 379         return lkey;
 380 }
 381
 382 /**
 383  * Ring TX queue doorbell.
 384  *
 385  * @param txq
 386  *   Pointer to TX queue structure.
 387  * @param wqe
 388  *   Pointer to the last WQE posted in the NIC.
 389  */
 390 static inline void
 391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 392 {
 393         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 394         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 395
 396         rte_wmb();
 397         *txq->qp_db = htonl(txq->wqe_ci);
 398         /* Ensure ordering between DB record and BF copy. */
 399         rte_wmb();
 400         *dst = *src;
 401 }
 402
 403 /**
 404  * DPDK callback to check the status of a tx descriptor.
 405  *
 406  * @param tx_queue
 407  *   The tx queue.
 408  * @param[in] offset
 409  *   The index of the descriptor in the ring.
 410  *
 411  * @return
 412  *   The status of the tx descriptor.
 413  */
 414 int
 415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 416 {
 417         struct txq *txq = tx_queue;
 418         const unsigned int elts_n = 1 << txq->elts_n;
 419         const unsigned int elts_cnt = elts_n - 1;
 420         unsigned int used;
 421
 422         txq_complete(txq);
 423         used = (txq->elts_head - txq->elts_tail) & elts_cnt;
 424         if (offset < used)
 425                 return RTE_ETH_TX_DESC_FULL;
 426         return RTE_ETH_TX_DESC_DONE;
 427 }
 428
 429 /**
 430  * DPDK callback to check the status of a rx descriptor.
 431  *
 432  * @param rx_queue
 433  *   The rx queue.
 434  * @param[in] offset
 435  *   The index of the descriptor in the ring.
 436  *
 437  * @return
 438  *   The status of the tx descriptor.
 439  */
 440 int
 441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 442 {
 443         struct rxq *rxq = rx_queue;
 444         struct rxq_zip *zip = &rxq->zip;
 445         volatile struct mlx5_cqe *cqe;
 446         const unsigned int cqe_n = (1 << rxq->cqe_n);
 447         const unsigned int cqe_cnt = cqe_n - 1;
 448         unsigned int cq_ci;
 449         unsigned int used;
 450
 451         /* if we are processing a compressed cqe */
 452         if (zip->ai) {
 453                 used = zip->cqe_cnt - zip->ca;
 454                 cq_ci = zip->cq_ci;
 455         } else {
 456                 used = 0;
 457                 cq_ci = rxq->cq_ci;
 458         }
 459         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 461                 int8_t op_own;
 462                 unsigned int n;
 463
 464                 op_own = cqe->op_own;
 465                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 466                         n = ntohl(cqe->byte_cnt);
 467                 else
 468                         n = 1;
 469                 cq_ci += n;
 470                 used += n;
 471                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 472         }
 473         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 474         if (offset < used)
 475                 return RTE_ETH_RX_DESC_DONE;
 476         return RTE_ETH_RX_DESC_AVAIL;
 477 }
 478
 479 /**
 480  * DPDK callback for TX.
 481  *
 482  * @param dpdk_txq
 483  *   Generic pointer to TX queue structure.
 484  * @param[in] pkts
 485  *   Packets to transmit.
 486  * @param pkts_n
 487  *   Number of packets in array.
 488  *
 489  * @return
 490  *   Number of packets successfully transmitted (<= pkts_n).
 491  */
 492 uint16_t
 493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 494 {
 495         struct txq *txq = (struct txq *)dpdk_txq;
 496         uint16_t elts_head = txq->elts_head;
 497         const unsigned int elts_n = 1 << txq->elts_n;
 498         unsigned int i = 0;
 499         unsigned int j = 0;
 500         unsigned int k = 0;
 501         unsigned int max;
 502         uint16_t max_wqe;
 503         unsigned int comp;
 504         volatile struct mlx5_wqe_v *wqe = NULL;
 505         unsigned int segs_n = 0;
 506         struct rte_mbuf *buf = NULL;
 507         uint8_t *raw;
 508
 509         if (unlikely(!pkts_n))
 510                 return 0;
 511         /* Prefetch first packet cacheline. */
 512         rte_prefetch0(*pkts);
 513         /* Start processing. */
 514         txq_complete(txq);
 515         max = (elts_n - (elts_head - txq->elts_tail));
 516         if (max > elts_n)
 517                 max -= elts_n;
 518         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 519         if (unlikely(!max_wqe))
 520                 return 0;
 521         do {
 522                 volatile rte_v128u32_t *dseg = NULL;
 523                 uint32_t length;
 524                 unsigned int ds = 0;
 525                 uintptr_t addr;
 526                 uint64_t naddr;
 527                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 528                 uint16_t tso_header_sz = 0;
 529                 uint16_t ehdr;
 530                 uint8_t cs_flags = 0;
 531                 uint64_t tso = 0;
 532 #ifdef MLX5_PMD_SOFT_COUNTERS
 533                 uint32_t total_length = 0;
 534 #endif
 535
 536                 /* first_seg */
 537                 buf = *(pkts++);
 538                 segs_n = buf->nb_segs;
 539                 /*
 540                  * Make sure there is enough room to store this packet and
 541                  * that one ring entry remains unused.
 542                  */
 543                 assert(segs_n);
 544                 if (max < segs_n + 1)
 545                         break;
 546                 max -= segs_n;
 547                 --segs_n;
 548                 if (!segs_n)
 549                         --pkts_n;
 550                 if (unlikely(--max_wqe == 0))
 551                         break;
 552                 wqe = (volatile struct mlx5_wqe_v *)
 553                         tx_mlx5_wqe(txq, txq->wqe_ci);
 554                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 555                 if (pkts_n > 1)
 556                         rte_prefetch0(*pkts);
 557                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 558                 length = DATA_LEN(buf);
 559                 ehdr = (((uint8_t *)addr)[1] << 8) |
 560                        ((uint8_t *)addr)[0];
 561 #ifdef MLX5_PMD_SOFT_COUNTERS
 562                 total_length = length;
 563 #endif
 564                 assert(length >= MLX5_WQE_DWORD_SIZE);
 565                 /* Update element. */
 566                 (*txq->elts)[elts_head] = buf;
 567                 elts_head = (elts_head + 1) & (elts_n - 1);
 568                 /* Prefetch next buffer data. */
 569                 if (pkts_n > 1) {
 570                         volatile void *pkt_addr;
 571
 572                         pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
 573                         rte_prefetch0(pkt_addr);
 574                 }
 575                 /* Should we enable HW CKSUM offload */
 576                 if (buf->ol_flags &
 577                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 578                         const uint64_t is_tunneled = buf->ol_flags &
 579                                                      (PKT_TX_TUNNEL_GRE |
 580                                                       PKT_TX_TUNNEL_VXLAN);
 581
 582                         if (is_tunneled && txq->tunnel_en) {
 583                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 584                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 585                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 586                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 587                         } else {
 588                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 589                                            MLX5_ETH_WQE_L4_CSUM;
 590                         }
 591                 }
 592                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 593                 /* Replace the Ethernet type by the VLAN if necessary. */
 594                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 595                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 596                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 597
 598                         addr += 2;
 599                         length -= 2;
 600                         /* Copy Destination and source mac address. */
 601                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 602                         /* Copy VLAN. */
 603                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 604                         /* Copy missing two bytes to end the DSeg. */
 605                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 606                                ((uint8_t *)addr) + len, 2);
 607                         addr += len + 2;
 608                         length -= (len + 2);
 609                 } else {
 610                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 611                                MLX5_WQE_DWORD_SIZE);
 612                         length -= pkt_inline_sz;
 613                         addr += pkt_inline_sz;
 614                 }
 615                 if (txq->tso_en) {
 616                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 617                         if (tso) {
 618                                 uintptr_t end = (uintptr_t)
 619                                                 (((uintptr_t)txq->wqes) +
 620                                                 (1 << txq->wqe_n) *
 621                                                 MLX5_WQE_SIZE);
 622                                 unsigned int copy_b;
 623                                 uint8_t vlan_sz = (buf->ol_flags &
 624                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 625                                 const uint64_t is_tunneled =
 626                                                         buf->ol_flags &
 627                                                         (PKT_TX_TUNNEL_GRE |
 628                                                          PKT_TX_TUNNEL_VXLAN);
 629
 630                                 tso_header_sz = buf->l2_len + vlan_sz +
 631                                                 buf->l3_len + buf->l4_len;
 632
 633                                 if (is_tunneled && txq->tunnel_en) {
 634                                         tso_header_sz += buf->outer_l2_len +
 635                                                          buf->outer_l3_len;
 636                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 637                                 } else {
 638                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 639                                 }
 640                                 if (unlikely(tso_header_sz >
 641                                              MLX5_MAX_TSO_HEADER))
 642                                         break;
 643                                 copy_b = tso_header_sz - pkt_inline_sz;
 644                                 /* First seg must contain all headers. */
 645                                 assert(copy_b <= length);
 646                                 raw += MLX5_WQE_DWORD_SIZE;
 647                                 if (copy_b &&
 648                                    ((end - (uintptr_t)raw) > copy_b)) {
 649                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 650                                                       1 + 3) / 4;
 651
 652                                         if (unlikely(max_wqe < n))
 653                                                 break;
 654                                         max_wqe -= n;
 655                                         rte_memcpy((void *)raw,
 656                                                    (void *)addr, copy_b);
 657                                         addr += copy_b;
 658                                         length -= copy_b;
 659                                         pkt_inline_sz += copy_b;
 660                                         /*
 661                                          * Another DWORD will be added
 662                                          * in the inline part.
 663                                          */
 664                                         raw += MLX5_WQE_DS(copy_b) *
 665                                                MLX5_WQE_DWORD_SIZE -
 666                                                MLX5_WQE_DWORD_SIZE;
 667                                 } else {
 668                                         /* NOP WQE. */
 669                                         wqe->ctrl = (rte_v128u32_t){
 670                                                      htonl(txq->wqe_ci << 8),
 671                                                      htonl(txq->qp_num_8s | 1),
 672                                                      0,
 673                                                      0,
 674                                         };
 675                                         ds = 1;
 676                                         total_length = 0;
 677                                         pkts--;
 678                                         pkts_n++;
 679                                         elts_head = (elts_head - 1) &
 680                                                     (elts_n - 1);
 681                                         k++;
 682                                         goto next_wqe;
 683                                 }
 684                         }
 685                 }
 686                 /* Inline if enough room. */
 687                 if (txq->inline_en || tso) {
 688                         uintptr_t end = (uintptr_t)
 689                                 (((uintptr_t)txq->wqes) +
 690                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 691                         unsigned int max_inline = txq->max_inline *
 692                                                   RTE_CACHE_LINE_SIZE -
 693                                                   (pkt_inline_sz - 2);
 694                         uintptr_t addr_end = (addr + max_inline) &
 695                                              ~(RTE_CACHE_LINE_SIZE - 1);
 696                         unsigned int copy_b = (addr_end > addr) ?
 697                                 RTE_MIN((addr_end - addr), length) :
 698                                 0;
 699
 700                         raw += MLX5_WQE_DWORD_SIZE;
 701                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 702                                 /*
 703                                  * One Dseg remains in the current WQE.  To
 704                                  * keep the computation positive, it is
 705                                  * removed after the bytes to Dseg conversion.
 706                                  */
 707                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 708
 709                                 if (unlikely(max_wqe < n))
 710                                         break;
 711                                 max_wqe -= n;
 712                                 if (tso) {
 713                                         uint32_t inl =
 714                                                 htonl(copy_b | MLX5_INLINE_SEG);
 715
 716                                         pkt_inline_sz =
 717                                                 MLX5_WQE_DS(tso_header_sz) *
 718                                                 MLX5_WQE_DWORD_SIZE;
 719                                         rte_memcpy((void *)raw,
 720                                                    (void *)&inl, sizeof(inl));
 721                                         raw += sizeof(inl);
 722                                         pkt_inline_sz += sizeof(inl);
 723                                 }
 724                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 725                                 addr += copy_b;
 726                                 length -= copy_b;
 727                                 pkt_inline_sz += copy_b;
 728                         }
 729                         /*
 730                          * 2 DWORDs consumed by the WQE header + ETH segment +
 731                          * the size of the inline part of the packet.
 732                          */
 733                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 734                         if (length > 0) {
 735                                 if (ds % (MLX5_WQE_SIZE /
 736                                           MLX5_WQE_DWORD_SIZE) == 0) {
 737                                         if (unlikely(--max_wqe == 0))
 738                                                 break;
 739                                         dseg = (volatile rte_v128u32_t *)
 740                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 741                                                            ds / 4);
 742                                 } else {
 743                                         dseg = (volatile rte_v128u32_t *)
 744                                                 ((uintptr_t)wqe +
 745                                                  (ds * MLX5_WQE_DWORD_SIZE));
 746                                 }
 747                                 goto use_dseg;
 748                         } else if (!segs_n) {
 749                                 goto next_pkt;
 750                         } else {
 751                                 /* dseg will be advance as part of next_seg */
 752                                 dseg = (volatile rte_v128u32_t *)
 753                                         ((uintptr_t)wqe +
 754                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 755                                 goto next_seg;
 756                         }
 757                 } else {
 758                         /*
 759                          * No inline has been done in the packet, only the
 760                          * Ethernet Header as been stored.
 761                          */
 762                         dseg = (volatile rte_v128u32_t *)
 763                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 764                         ds = 3;
 765 use_dseg:
 766                         /* Add the remaining packet as a simple ds. */
 767                         naddr = htonll(addr);
 768                         *dseg = (rte_v128u32_t){
 769                                 htonl(length),
 770                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 771                                 naddr,
 772                                 naddr >> 32,
 773                         };
 774                         ++ds;
 775                         if (!segs_n)
 776                                 goto next_pkt;
 777                 }
 778 next_seg:
 779                 assert(buf);
 780                 assert(ds);
 781                 assert(wqe);
 782                 /*
 783                  * Spill on next WQE when the current one does not have
 784                  * enough room left. Size of WQE must a be a multiple
 785                  * of data segment size.
 786                  */
 787                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 788                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 789                         if (unlikely(--max_wqe == 0))
 790                                 break;
 791                         dseg = (volatile rte_v128u32_t *)
 792                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 793                         rte_prefetch0(tx_mlx5_wqe(txq,
 794                                                   txq->wqe_ci + ds / 4 + 1));
 795                 } else {
 796                         ++dseg;
 797                 }
 798                 ++ds;
 799                 buf = buf->next;
 800                 assert(buf);
 801                 length = DATA_LEN(buf);
 802 #ifdef MLX5_PMD_SOFT_COUNTERS
 803                 total_length += length;
 804 #endif
 805                 /* Store segment information. */
 806                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 807                 *dseg = (rte_v128u32_t){
 808                         htonl(length),
 809                         txq_mp2mr(txq, txq_mb2mp(buf)),
 810                         naddr,
 811                         naddr >> 32,
 812                 };
 813                 (*txq->elts)[elts_head] = buf;
 814                 elts_head = (elts_head + 1) & (elts_n - 1);
 815                 ++j;
 816                 --segs_n;
 817                 if (segs_n)
 818                         goto next_seg;
 819                 else
 820                         --pkts_n;
 821 next_pkt:
 822                 ++i;
 823                 /* Initialize known and common part of the WQE structure. */
 824                 if (tso) {
 825                         wqe->ctrl = (rte_v128u32_t){
 826                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 827                                 htonl(txq->qp_num_8s | ds),
 828                                 0,
 829                                 0,
 830                         };
 831                         wqe->eseg = (rte_v128u32_t){
 832                                 0,
 833                                 cs_flags | (htons(buf->tso_segsz) << 16),
 834                                 0,
 835                                 (ehdr << 16) | htons(tso_header_sz),
 836                         };
 837                 } else {
 838                         wqe->ctrl = (rte_v128u32_t){
 839                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 840                                 htonl(txq->qp_num_8s | ds),
 841                                 0,
 842                                 0,
 843                         };
 844                         wqe->eseg = (rte_v128u32_t){
 845                                 0,
 846                                 cs_flags,
 847                                 0,
 848                                 (ehdr << 16) | htons(pkt_inline_sz),
 849                         };
 850                 }
 851 next_wqe:
 852                 txq->wqe_ci += (ds + 3) / 4;
 853 #ifdef MLX5_PMD_SOFT_COUNTERS
 854                 /* Increment sent bytes counter. */
 855                 txq->stats.obytes += total_length;
 856 #endif
 857         } while (pkts_n);
 858         /* Take a shortcut if nothing must be sent. */
 859         if (unlikely((i + k) == 0))
 860                 return 0;
 861         /* Check whether completion threshold has been reached. */
 862         comp = txq->elts_comp + i + j + k;
 863         if (comp >= MLX5_TX_COMP_THRESH) {
 864                 volatile struct mlx5_wqe_ctrl *w =
 865                         (volatile struct mlx5_wqe_ctrl *)wqe;
 866
 867                 /* Request completion on last WQE. */
 868                 w->ctrl2 = htonl(8);
 869                 /* Save elts_head in unused "immediate" field of WQE. */
 870                 w->ctrl3 = elts_head;
 871                 txq->elts_comp = 0;
 872         } else {
 873                 txq->elts_comp = comp;
 874         }
 875 #ifdef MLX5_PMD_SOFT_COUNTERS
 876         /* Increment sent packets counter. */
 877         txq->stats.opackets += i;
 878 #endif
 879         /* Ring QP doorbell. */
 880         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
 881         txq->elts_head = elts_head;
 882         return i;
 883 }
 884
 885 /**
 886  * Open a MPW session.
 887  *
 888  * @param txq
 889  *   Pointer to TX queue structure.
 890  * @param mpw
 891  *   Pointer to MPW session structure.
 892  * @param length
 893  *   Packet length.
 894  */
 895 static inline void
 896 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 897 {
 898         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 899         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 900                 (volatile struct mlx5_wqe_data_seg (*)[])
 901                 tx_mlx5_wqe(txq, idx + 1);
 902
 903         mpw->state = MLX5_MPW_STATE_OPENED;
 904         mpw->pkts_n = 0;
 905         mpw->len = length;
 906         mpw->total_len = 0;
 907         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 908         mpw->wqe->eseg.mss = htons(length);
 909         mpw->wqe->eseg.inline_hdr_sz = 0;
 910         mpw->wqe->eseg.rsvd0 = 0;
 911         mpw->wqe->eseg.rsvd1 = 0;
 912         mpw->wqe->eseg.rsvd2 = 0;
 913         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 914                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 915         mpw->wqe->ctrl[2] = 0;
 916         mpw->wqe->ctrl[3] = 0;
 917         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 918                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 919         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 920                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 921         mpw->data.dseg[2] = &(*dseg)[0];
 922         mpw->data.dseg[3] = &(*dseg)[1];
 923         mpw->data.dseg[4] = &(*dseg)[2];
 924 }
 925
 926 /**
 927  * Close a MPW session.
 928  *
 929  * @param txq
 930  *   Pointer to TX queue structure.
 931  * @param mpw
 932  *   Pointer to MPW session structure.
 933  */
 934 static inline void
 935 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 936 {
 937         unsigned int num = mpw->pkts_n;
 938
 939         /*
 940          * Store size in multiple of 16 bytes. Control and Ethernet segments
 941          * count as 2.
 942          */
 943         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 944         mpw->state = MLX5_MPW_STATE_CLOSED;
 945         if (num < 3)
 946                 ++txq->wqe_ci;
 947         else
 948                 txq->wqe_ci += 2;
 949         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 950         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 951 }
 952
 953 /**
 954  * DPDK callback for TX with MPW support.
 955  *
 956  * @param dpdk_txq
 957  *   Generic pointer to TX queue structure.
 958  * @param[in] pkts
 959  *   Packets to transmit.
 960  * @param pkts_n
 961  *   Number of packets in array.
 962  *
 963  * @return
 964  *   Number of packets successfully transmitted (<= pkts_n).
 965  */
 966 uint16_t
 967 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 968 {
 969         struct txq *txq = (struct txq *)dpdk_txq;
 970         uint16_t elts_head = txq->elts_head;
 971         const unsigned int elts_n = 1 << txq->elts_n;
 972         unsigned int i = 0;
 973         unsigned int j = 0;
 974         unsigned int max;
 975         uint16_t max_wqe;
 976         unsigned int comp;
 977         struct mlx5_mpw mpw = {
 978                 .state = MLX5_MPW_STATE_CLOSED,
 979         };
 980
 981         if (unlikely(!pkts_n))
 982                 return 0;
 983         /* Prefetch first packet cacheline. */
 984         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 985         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 986         /* Start processing. */
 987         txq_complete(txq);
 988         max = (elts_n - (elts_head - txq->elts_tail));
 989         if (max > elts_n)
 990                 max -= elts_n;
 991         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 992         if (unlikely(!max_wqe))
 993                 return 0;
 994         do {
 995                 struct rte_mbuf *buf = *(pkts++);
 996                 unsigned int elts_head_next;
 997                 uint32_t length;
 998                 unsigned int segs_n = buf->nb_segs;
 999                 uint32_t cs_flags = 0;
1000
1001                 /*
1002                  * Make sure there is enough room to store this packet and
1003                  * that one ring entry remains unused.
1004                  */
1005                 assert(segs_n);
1006                 if (max < segs_n + 1)
1007                         break;
1008                 /* Do not bother with large packets MPW cannot handle. */
1009                 if (segs_n > MLX5_MPW_DSEG_MAX)
1010                         break;
1011                 max -= segs_n;
1012                 --pkts_n;
1013                 /* Should we enable HW CKSUM offload */
1014                 if (buf->ol_flags &
1015                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1016                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1017                 /* Retrieve packet information. */
1018                 length = PKT_LEN(buf);
1019                 assert(length);
1020                 /* Start new session if packet differs. */
1021                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1022                     ((mpw.len != length) ||
1023                      (segs_n != 1) ||
1024                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1025                         mlx5_mpw_close(txq, &mpw);
1026                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1027                         /*
1028                          * Multi-Packet WQE consumes at most two WQE.
1029                          * mlx5_mpw_new() expects to be able to use such
1030                          * resources.
1031                          */
1032                         if (unlikely(max_wqe < 2))
1033                                 break;
1034                         max_wqe -= 2;
1035                         mlx5_mpw_new(txq, &mpw, length);
1036                         mpw.wqe->eseg.cs_flags = cs_flags;
1037                 }
1038                 /* Multi-segment packets must be alone in their MPW. */
1039                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1040 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1041                 length = 0;
1042 #endif
1043                 do {
1044                         volatile struct mlx5_wqe_data_seg *dseg;
1045                         uintptr_t addr;
1046
1047                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1048                         assert(buf);
1049                         (*txq->elts)[elts_head] = buf;
1050                         dseg = mpw.data.dseg[mpw.pkts_n];
1051                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1052                         *dseg = (struct mlx5_wqe_data_seg){
1053                                 .byte_count = htonl(DATA_LEN(buf)),
1054                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1055                                 .addr = htonll(addr),
1056                         };
1057                         elts_head = elts_head_next;
1058 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1059                         length += DATA_LEN(buf);
1060 #endif
1061                         buf = buf->next;
1062                         ++mpw.pkts_n;
1063                         ++j;
1064                 } while (--segs_n);
1065                 assert(length == mpw.len);
1066                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1067                         mlx5_mpw_close(txq, &mpw);
1068                 elts_head = elts_head_next;
1069 #ifdef MLX5_PMD_SOFT_COUNTERS
1070                 /* Increment sent bytes counter. */
1071                 txq->stats.obytes += length;
1072 #endif
1073                 ++i;
1074         } while (pkts_n);
1075         /* Take a shortcut if nothing must be sent. */
1076         if (unlikely(i == 0))
1077                 return 0;
1078         /* Check whether completion threshold has been reached. */
1079         /* "j" includes both packets and segments. */
1080         comp = txq->elts_comp + j;
1081         if (comp >= MLX5_TX_COMP_THRESH) {
1082                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1083
1084                 /* Request completion on last WQE. */
1085                 wqe->ctrl[2] = htonl(8);
1086                 /* Save elts_head in unused "immediate" field of WQE. */
1087                 wqe->ctrl[3] = elts_head;
1088                 txq->elts_comp = 0;
1089         } else {
1090                 txq->elts_comp = comp;
1091         }
1092 #ifdef MLX5_PMD_SOFT_COUNTERS
1093         /* Increment sent packets counter. */
1094         txq->stats.opackets += i;
1095 #endif
1096         /* Ring QP doorbell. */
1097         if (mpw.state == MLX5_MPW_STATE_OPENED)
1098                 mlx5_mpw_close(txq, &mpw);
1099         mlx5_tx_dbrec(txq, mpw.wqe);
1100         txq->elts_head = elts_head;
1101         return i;
1102 }
1103
1104 /**
1105  * Open a MPW inline session.
1106  *
1107  * @param txq
1108  *   Pointer to TX queue structure.
1109  * @param mpw
1110  *   Pointer to MPW session structure.
1111  * @param length
1112  *   Packet length.
1113  */
1114 static inline void
1115 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1116 {
1117         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1118         struct mlx5_wqe_inl_small *inl;
1119
1120         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1121         mpw->pkts_n = 0;
1122         mpw->len = length;
1123         mpw->total_len = 0;
1124         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1125         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1126                                   (txq->wqe_ci << 8) |
1127                                   MLX5_OPCODE_TSO);
1128         mpw->wqe->ctrl[2] = 0;
1129         mpw->wqe->ctrl[3] = 0;
1130         mpw->wqe->eseg.mss = htons(length);
1131         mpw->wqe->eseg.inline_hdr_sz = 0;
1132         mpw->wqe->eseg.cs_flags = 0;
1133         mpw->wqe->eseg.rsvd0 = 0;
1134         mpw->wqe->eseg.rsvd1 = 0;
1135         mpw->wqe->eseg.rsvd2 = 0;
1136         inl = (struct mlx5_wqe_inl_small *)
1137                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1138         mpw->data.raw = (uint8_t *)&inl->raw;
1139 }
1140
1141 /**
1142  * Close a MPW inline session.
1143  *
1144  * @param txq
1145  *   Pointer to TX queue structure.
1146  * @param mpw
1147  *   Pointer to MPW session structure.
1148  */
1149 static inline void
1150 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1151 {
1152         unsigned int size;
1153         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1154                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1155
1156         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1157         /*
1158          * Store size in multiple of 16 bytes. Control and Ethernet segments
1159          * count as 2.
1160          */
1161         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1162         mpw->state = MLX5_MPW_STATE_CLOSED;
1163         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1164         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1165 }
1166
1167 /**
1168  * DPDK callback for TX with MPW inline support.
1169  *
1170  * @param dpdk_txq
1171  *   Generic pointer to TX queue structure.
1172  * @param[in] pkts
1173  *   Packets to transmit.
1174  * @param pkts_n
1175  *   Number of packets in array.
1176  *
1177  * @return
1178  *   Number of packets successfully transmitted (<= pkts_n).
1179  */
1180 uint16_t
1181 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1182                          uint16_t pkts_n)
1183 {
1184         struct txq *txq = (struct txq *)dpdk_txq;
1185         uint16_t elts_head = txq->elts_head;
1186         const unsigned int elts_n = 1 << txq->elts_n;
1187         unsigned int i = 0;
1188         unsigned int j = 0;
1189         unsigned int max;
1190         uint16_t max_wqe;
1191         unsigned int comp;
1192         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1193         struct mlx5_mpw mpw = {
1194                 .state = MLX5_MPW_STATE_CLOSED,
1195         };
1196         /*
1197          * Compute the maximum number of WQE which can be consumed by inline
1198          * code.
1199          * - 2 DSEG for:
1200          *   - 1 control segment,
1201          *   - 1 Ethernet segment,
1202          * - N Dseg from the inline request.
1203          */
1204         const unsigned int wqe_inl_n =
1205                 ((2 * MLX5_WQE_DWORD_SIZE +
1206                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1207                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1208
1209         if (unlikely(!pkts_n))
1210                 return 0;
1211         /* Prefetch first packet cacheline. */
1212         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1213         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1214         /* Start processing. */
1215         txq_complete(txq);
1216         max = (elts_n - (elts_head - txq->elts_tail));
1217         if (max > elts_n)
1218                 max -= elts_n;
1219         do {
1220                 struct rte_mbuf *buf = *(pkts++);
1221                 unsigned int elts_head_next;
1222                 uintptr_t addr;
1223                 uint32_t length;
1224                 unsigned int segs_n = buf->nb_segs;
1225                 uint32_t cs_flags = 0;
1226
1227                 /*
1228                  * Make sure there is enough room to store this packet and
1229                  * that one ring entry remains unused.
1230                  */
1231                 assert(segs_n);
1232                 if (max < segs_n + 1)
1233                         break;
1234                 /* Do not bother with large packets MPW cannot handle. */
1235                 if (segs_n > MLX5_MPW_DSEG_MAX)
1236                         break;
1237                 max -= segs_n;
1238                 --pkts_n;
1239                 /*
1240                  * Compute max_wqe in case less WQE were consumed in previous
1241                  * iteration.
1242                  */
1243                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1244                 /* Should we enable HW CKSUM offload */
1245                 if (buf->ol_flags &
1246                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1247                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1248                 /* Retrieve packet information. */
1249                 length = PKT_LEN(buf);
1250                 /* Start new session if packet differs. */
1251                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1252                         if ((mpw.len != length) ||
1253                             (segs_n != 1) ||
1254                             (mpw.wqe->eseg.cs_flags != cs_flags))
1255                                 mlx5_mpw_close(txq, &mpw);
1256                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1257                         if ((mpw.len != length) ||
1258                             (segs_n != 1) ||
1259                             (length > inline_room) ||
1260                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1261                                 mlx5_mpw_inline_close(txq, &mpw);
1262                                 inline_room =
1263                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1264                         }
1265                 }
1266                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1267                         if ((segs_n != 1) ||
1268                             (length > inline_room)) {
1269                                 /*
1270                                  * Multi-Packet WQE consumes at most two WQE.
1271                                  * mlx5_mpw_new() expects to be able to use
1272                                  * such resources.
1273                                  */
1274                                 if (unlikely(max_wqe < 2))
1275                                         break;
1276                                 max_wqe -= 2;
1277                                 mlx5_mpw_new(txq, &mpw, length);
1278                                 mpw.wqe->eseg.cs_flags = cs_flags;
1279                         } else {
1280                                 if (unlikely(max_wqe < wqe_inl_n))
1281                                         break;
1282                                 max_wqe -= wqe_inl_n;
1283                                 mlx5_mpw_inline_new(txq, &mpw, length);
1284                                 mpw.wqe->eseg.cs_flags = cs_flags;
1285                         }
1286                 }
1287                 /* Multi-segment packets must be alone in their MPW. */
1288                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1289                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1290                         assert(inline_room ==
1291                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1292 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1293                         length = 0;
1294 #endif
1295                         do {
1296                                 volatile struct mlx5_wqe_data_seg *dseg;
1297
1298                                 elts_head_next =
1299                                         (elts_head + 1) & (elts_n - 1);
1300                                 assert(buf);
1301                                 (*txq->elts)[elts_head] = buf;
1302                                 dseg = mpw.data.dseg[mpw.pkts_n];
1303                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1304                                 *dseg = (struct mlx5_wqe_data_seg){
1305                                         .byte_count = htonl(DATA_LEN(buf)),
1306                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1307                                         .addr = htonll(addr),
1308                                 };
1309                                 elts_head = elts_head_next;
1310 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1311                                 length += DATA_LEN(buf);
1312 #endif
1313                                 buf = buf->next;
1314                                 ++mpw.pkts_n;
1315                                 ++j;
1316                         } while (--segs_n);
1317                         assert(length == mpw.len);
1318                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1319                                 mlx5_mpw_close(txq, &mpw);
1320                 } else {
1321                         unsigned int max;
1322
1323                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1324                         assert(length <= inline_room);
1325                         assert(length == DATA_LEN(buf));
1326                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1327                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1328                         (*txq->elts)[elts_head] = buf;
1329                         /* Maximum number of bytes before wrapping. */
1330                         max = ((((uintptr_t)(txq->wqes)) +
1331                                 (1 << txq->wqe_n) *
1332                                 MLX5_WQE_SIZE) -
1333                                (uintptr_t)mpw.data.raw);
1334                         if (length > max) {
1335                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1336                                            (void *)addr,
1337                                            max);
1338                                 mpw.data.raw = (volatile void *)txq->wqes;
1339                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1340                                            (void *)(addr + max),
1341                                            length - max);
1342                                 mpw.data.raw += length - max;
1343                         } else {
1344                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1345                                            (void *)addr,
1346                                            length);
1347
1348                                 if (length == max)
1349                                         mpw.data.raw =
1350                                                 (volatile void *)txq->wqes;
1351                                 else
1352                                         mpw.data.raw += length;
1353                         }
1354                         ++mpw.pkts_n;
1355                         mpw.total_len += length;
1356                         ++j;
1357                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1358                                 mlx5_mpw_inline_close(txq, &mpw);
1359                                 inline_room =
1360                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1361                         } else {
1362                                 inline_room -= length;
1363                         }
1364                 }
1365                 elts_head = elts_head_next;
1366 #ifdef MLX5_PMD_SOFT_COUNTERS
1367                 /* Increment sent bytes counter. */
1368                 txq->stats.obytes += length;
1369 #endif
1370                 ++i;
1371         } while (pkts_n);
1372         /* Take a shortcut if nothing must be sent. */
1373         if (unlikely(i == 0))
1374                 return 0;
1375         /* Check whether completion threshold has been reached. */
1376         /* "j" includes both packets and segments. */
1377         comp = txq->elts_comp + j;
1378         if (comp >= MLX5_TX_COMP_THRESH) {
1379                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1380
1381                 /* Request completion on last WQE. */
1382                 wqe->ctrl[2] = htonl(8);
1383                 /* Save elts_head in unused "immediate" field of WQE. */
1384                 wqe->ctrl[3] = elts_head;
1385                 txq->elts_comp = 0;
1386         } else {
1387                 txq->elts_comp = comp;
1388         }
1389 #ifdef MLX5_PMD_SOFT_COUNTERS
1390         /* Increment sent packets counter. */
1391         txq->stats.opackets += i;
1392 #endif
1393         /* Ring QP doorbell. */
1394         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1395                 mlx5_mpw_inline_close(txq, &mpw);
1396         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1397                 mlx5_mpw_close(txq, &mpw);
1398         mlx5_tx_dbrec(txq, mpw.wqe);
1399         txq->elts_head = elts_head;
1400         return i;
1401 }
1402
1403 /**
1404  * Open an Enhanced MPW session.
1405  *
1406  * @param txq
1407  *   Pointer to TX queue structure.
1408  * @param mpw
1409  *   Pointer to MPW session structure.
1410  * @param length
1411  *   Packet length.
1412  */
1413 static inline void
1414 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1415 {
1416         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1417
1418         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1419         mpw->pkts_n = 0;
1420         mpw->total_len = sizeof(struct mlx5_wqe);
1421         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1422         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1423                                   (txq->wqe_ci << 8) |
1424                                   MLX5_OPCODE_ENHANCED_MPSW);
1425         mpw->wqe->ctrl[2] = 0;
1426         mpw->wqe->ctrl[3] = 0;
1427         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1428         if (unlikely(padding)) {
1429                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1430
1431                 /* Pad the first 2 DWORDs with zero-length inline header. */
1432                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1433                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1434                         htonl(MLX5_INLINE_SEG);
1435                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1436                 /* Start from the next WQEBB. */
1437                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1438         } else {
1439                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1440         }
1441 }
1442
1443 /**
1444  * Close an Enhanced MPW session.
1445  *
1446  * @param txq
1447  *   Pointer to TX queue structure.
1448  * @param mpw
1449  *   Pointer to MPW session structure.
1450  *
1451  * @return
1452  *   Number of consumed WQEs.
1453  */
1454 static inline uint16_t
1455 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1456 {
1457         uint16_t ret;
1458
1459         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1460          * count as 2.
1461          */
1462         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1463         mpw->state = MLX5_MPW_STATE_CLOSED;
1464         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1465         txq->wqe_ci += ret;
1466         return ret;
1467 }
1468
1469 /**
1470  * DPDK callback for TX with Enhanced MPW support.
1471  *
1472  * @param dpdk_txq
1473  *   Generic pointer to TX queue structure.
1474  * @param[in] pkts
1475  *   Packets to transmit.
1476  * @param pkts_n
1477  *   Number of packets in array.
1478  *
1479  * @return
1480  *   Number of packets successfully transmitted (<= pkts_n).
1481  */
1482 uint16_t
1483 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1484 {
1485         struct txq *txq = (struct txq *)dpdk_txq;
1486         uint16_t elts_head = txq->elts_head;
1487         const unsigned int elts_n = 1 << txq->elts_n;
1488         unsigned int i = 0;
1489         unsigned int j = 0;
1490         unsigned int max_elts;
1491         uint16_t max_wqe;
1492         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1493         unsigned int mpw_room = 0;
1494         unsigned int inl_pad = 0;
1495         uint32_t inl_hdr;
1496         struct mlx5_mpw mpw = {
1497                 .state = MLX5_MPW_STATE_CLOSED,
1498         };
1499
1500         if (unlikely(!pkts_n))
1501                 return 0;
1502         /* Start processing. */
1503         txq_complete(txq);
1504         max_elts = (elts_n - (elts_head - txq->elts_tail));
1505         if (max_elts > elts_n)
1506                 max_elts -= elts_n;
1507         /* A CQE slot must always be available. */
1508         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1509         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1510         if (unlikely(!max_wqe))
1511                 return 0;
1512         do {
1513                 struct rte_mbuf *buf = *(pkts++);
1514                 unsigned int elts_head_next;
1515                 uintptr_t addr;
1516                 uint64_t naddr;
1517                 unsigned int n;
1518                 unsigned int do_inline = 0; /* Whether inline is possible. */
1519                 uint32_t length;
1520                 unsigned int segs_n = buf->nb_segs;
1521                 uint32_t cs_flags = 0;
1522
1523                 /*
1524                  * Make sure there is enough room to store this packet and
1525                  * that one ring entry remains unused.
1526                  */
1527                 assert(segs_n);
1528                 if (max_elts - j < segs_n + 1)
1529                         break;
1530                 /* Do not bother with large packets MPW cannot handle. */
1531                 if (segs_n > MLX5_MPW_DSEG_MAX)
1532                         break;
1533                 /* Should we enable HW CKSUM offload. */
1534                 if (buf->ol_flags &
1535                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1536                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1537                 /* Retrieve packet information. */
1538                 length = PKT_LEN(buf);
1539                 /* Start new session if:
1540                  * - multi-segment packet
1541                  * - no space left even for a dseg
1542                  * - next packet can be inlined with a new WQE
1543                  * - cs_flag differs
1544                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1545                  * segmented packet.
1546                  */
1547                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1548                         if ((segs_n != 1) ||
1549                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1550                               mpw_room) ||
1551                             (length <= txq->inline_max_packet_sz &&
1552                              inl_pad + sizeof(inl_hdr) + length >
1553                               mpw_room) ||
1554                             (mpw.wqe->eseg.cs_flags != cs_flags))
1555                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1556                 }
1557                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1558                         if (unlikely(segs_n != 1)) {
1559                                 /* Fall back to legacy MPW.
1560                                  * A MPW session consumes 2 WQEs at most to
1561                                  * include MLX5_MPW_DSEG_MAX pointers.
1562                                  */
1563                                 if (unlikely(max_wqe < 2))
1564                                         break;
1565                                 mlx5_mpw_new(txq, &mpw, length);
1566                         } else {
1567                                 /* In Enhanced MPW, inline as much as the budget
1568                                  * is allowed. The remaining space is to be
1569                                  * filled with dsegs. If the title WQEBB isn't
1570                                  * padded, it will have 2 dsegs there.
1571                                  */
1572                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1573                                             (max_inline ? max_inline :
1574                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1575                                             MLX5_WQE_SIZE);
1576                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1577                                               mpw_room))
1578                                         break;
1579                                 /* Don't pad the title WQEBB to not waste WQ. */
1580                                 mlx5_empw_new(txq, &mpw, 0);
1581                                 mpw_room -= mpw.total_len;
1582                                 inl_pad = 0;
1583                                 do_inline =
1584                                         length <= txq->inline_max_packet_sz &&
1585                                         sizeof(inl_hdr) + length <= mpw_room &&
1586                                         !txq->mpw_hdr_dseg;
1587                         }
1588                         mpw.wqe->eseg.cs_flags = cs_flags;
1589                 } else {
1590                         /* Evaluate whether the next packet can be inlined.
1591                          * Inlininig is possible when:
1592                          * - length is less than configured value
1593                          * - length fits for remaining space
1594                          * - not required to fill the title WQEBB with dsegs
1595                          */
1596                         do_inline =
1597                                 length <= txq->inline_max_packet_sz &&
1598                                 inl_pad + sizeof(inl_hdr) + length <=
1599                                  mpw_room &&
1600                                 (!txq->mpw_hdr_dseg ||
1601                                  mpw.total_len >= MLX5_WQE_SIZE);
1602                 }
1603                 /* Multi-segment packets must be alone in their MPW. */
1604                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1605                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1606 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1607                         length = 0;
1608 #endif
1609                         do {
1610                                 volatile struct mlx5_wqe_data_seg *dseg;
1611
1612                                 elts_head_next =
1613                                         (elts_head + 1) & (elts_n - 1);
1614                                 assert(buf);
1615                                 (*txq->elts)[elts_head] = buf;
1616                                 dseg = mpw.data.dseg[mpw.pkts_n];
1617                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1618                                 *dseg = (struct mlx5_wqe_data_seg){
1619                                         .byte_count = htonl(DATA_LEN(buf)),
1620                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1621                                         .addr = htonll(addr),
1622                                 };
1623                                 elts_head = elts_head_next;
1624 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1625                                 length += DATA_LEN(buf);
1626 #endif
1627                                 buf = buf->next;
1628                                 ++j;
1629                                 ++mpw.pkts_n;
1630                         } while (--segs_n);
1631                         /* A multi-segmented packet takes one MPW session.
1632                          * TODO: Pack more multi-segmented packets if possible.
1633                          */
1634                         mlx5_mpw_close(txq, &mpw);
1635                         if (mpw.pkts_n < 3)
1636                                 max_wqe--;
1637                         else
1638                                 max_wqe -= 2;
1639                 } else if (do_inline) {
1640                         /* Inline packet into WQE. */
1641                         unsigned int max;
1642
1643                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1644                         assert(length == DATA_LEN(buf));
1645                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1646                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1647                         mpw.data.raw = (volatile void *)
1648                                 ((uintptr_t)mpw.data.raw + inl_pad);
1649                         max = tx_mlx5_wq_tailroom(txq,
1650                                         (void *)(uintptr_t)mpw.data.raw);
1651                         /* Copy inline header. */
1652                         mpw.data.raw = (volatile void *)
1653                                 mlx5_copy_to_wq(
1654                                           (void *)(uintptr_t)mpw.data.raw,
1655                                           &inl_hdr,
1656                                           sizeof(inl_hdr),
1657                                           (void *)(uintptr_t)txq->wqes,
1658                                           max);
1659                         max = tx_mlx5_wq_tailroom(txq,
1660                                         (void *)(uintptr_t)mpw.data.raw);
1661                         /* Copy packet data. */
1662                         mpw.data.raw = (volatile void *)
1663                                 mlx5_copy_to_wq(
1664                                           (void *)(uintptr_t)mpw.data.raw,
1665                                           (void *)addr,
1666                                           length,
1667                                           (void *)(uintptr_t)txq->wqes,
1668                                           max);
1669                         ++mpw.pkts_n;
1670                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1671                         /* No need to get completion as the entire packet is
1672                          * copied to WQ. Free the buf right away.
1673                          */
1674                         elts_head_next = elts_head;
1675                         rte_pktmbuf_free_seg(buf);
1676                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1677                         /* Add pad in the next packet if any. */
1678                         inl_pad = (((uintptr_t)mpw.data.raw +
1679                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1680                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1681                                   (uintptr_t)mpw.data.raw;
1682                 } else {
1683                         /* No inline. Load a dseg of packet pointer. */
1684                         volatile rte_v128u32_t *dseg;
1685
1686                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1687                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1688                         assert(length == DATA_LEN(buf));
1689                         if (!tx_mlx5_wq_tailroom(txq,
1690                                         (void *)((uintptr_t)mpw.data.raw
1691                                                 + inl_pad)))
1692                                 dseg = (volatile void *)txq->wqes;
1693                         else
1694                                 dseg = (volatile void *)
1695                                         ((uintptr_t)mpw.data.raw +
1696                                          inl_pad);
1697                         elts_head_next = (elts_head + 1) & (elts_n - 1);
1698                         (*txq->elts)[elts_head] = buf;
1699                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1700                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1701                                 rte_prefetch2((void *)(addr +
1702                                                 n * RTE_CACHE_LINE_SIZE));
1703                         naddr = htonll(addr);
1704                         *dseg = (rte_v128u32_t) {
1705                                 htonl(length),
1706                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1707                                 naddr,
1708                                 naddr >> 32,
1709                         };
1710                         mpw.data.raw = (volatile void *)(dseg + 1);
1711                         mpw.total_len += (inl_pad + sizeof(*dseg));
1712                         ++j;
1713                         ++mpw.pkts_n;
1714                         mpw_room -= (inl_pad + sizeof(*dseg));
1715                         inl_pad = 0;
1716                 }
1717                 elts_head = elts_head_next;
1718 #ifdef MLX5_PMD_SOFT_COUNTERS
1719                 /* Increment sent bytes counter. */
1720                 txq->stats.obytes += length;
1721 #endif
1722                 ++i;
1723         } while (i < pkts_n);
1724         /* Take a shortcut if nothing must be sent. */
1725         if (unlikely(i == 0))
1726                 return 0;
1727         /* Check whether completion threshold has been reached. */
1728         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1729                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1730                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1731                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1732
1733                 /* Request completion on last WQE. */
1734                 wqe->ctrl[2] = htonl(8);
1735                 /* Save elts_head in unused "immediate" field of WQE. */
1736                 wqe->ctrl[3] = elts_head;
1737                 txq->elts_comp = 0;
1738                 txq->mpw_comp = txq->wqe_ci;
1739                 txq->cq_pi++;
1740         } else {
1741                 txq->elts_comp += j;
1742         }
1743 #ifdef MLX5_PMD_SOFT_COUNTERS
1744         /* Increment sent packets counter. */
1745         txq->stats.opackets += i;
1746 #endif
1747         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1748                 mlx5_empw_close(txq, &mpw);
1749         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1750                 mlx5_mpw_close(txq, &mpw);
1751         /* Ring QP doorbell. */
1752         mlx5_tx_dbrec(txq, mpw.wqe);
1753         txq->elts_head = elts_head;
1754         return i;
1755 }
1756
1757 /**
1758  * Translate RX completion flags to packet type.
1759  *
1760  * @param[in] cqe
1761  *   Pointer to CQE.
1762  *
1763  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1764  *
1765  * @return
1766  *   Packet type for struct rte_mbuf.
1767  */
1768 static inline uint32_t
1769 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1770 {
1771         uint32_t pkt_type;
1772         uint16_t flags = ntohs(cqe->hdr_type_etc);
1773
1774         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1775                 pkt_type =
1776                         TRANSPOSE(flags,
1777                                   MLX5_CQE_RX_IPV4_PACKET,
1778                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1779                         TRANSPOSE(flags,
1780                                   MLX5_CQE_RX_IPV6_PACKET,
1781                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1782                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1783                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1784                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1785         } else {
1786                 pkt_type =
1787                         TRANSPOSE(flags,
1788                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1789                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1790                         TRANSPOSE(flags,
1791                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1792                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1793         }
1794         return pkt_type;
1795 }
1796
1797 /**
1798  * Get size of the next packet for a given CQE. For compressed CQEs, the
1799  * consumer index is updated only once all packets of the current one have
1800  * been processed.
1801  *
1802  * @param rxq
1803  *   Pointer to RX queue.
1804  * @param cqe
1805  *   CQE to process.
1806  * @param[out] rss_hash
1807  *   Packet RSS Hash result.
1808  *
1809  * @return
1810  *   Packet size in bytes (0 if there is none), -1 in case of completion
1811  *   with error.
1812  */
1813 static inline int
1814 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1815                  uint16_t cqe_cnt, uint32_t *rss_hash)
1816 {
1817         struct rxq_zip *zip = &rxq->zip;
1818         uint16_t cqe_n = cqe_cnt + 1;
1819         int len = 0;
1820         uint16_t idx, end;
1821
1822         /* Process compressed data in the CQE and mini arrays. */
1823         if (zip->ai) {
1824                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1825                         (volatile struct mlx5_mini_cqe8 (*)[8])
1826                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1827
1828                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1829                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1830                 if ((++zip->ai & 7) == 0) {
1831                         /* Invalidate consumed CQEs */
1832                         idx = zip->ca;
1833                         end = zip->na;
1834                         while (idx != end) {
1835                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1836                                         MLX5_CQE_INVALIDATE;
1837                                 ++idx;
1838                         }
1839                         /*
1840                          * Increment consumer index to skip the number of
1841                          * CQEs consumed. Hardware leaves holes in the CQ
1842                          * ring for software use.
1843                          */
1844                         zip->ca = zip->na;
1845                         zip->na += 8;
1846                 }
1847                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1848                         /* Invalidate the rest */
1849                         idx = zip->ca;
1850                         end = zip->cq_ci;
1851
1852                         while (idx != end) {
1853                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1854                                         MLX5_CQE_INVALIDATE;
1855                                 ++idx;
1856                         }
1857                         rxq->cq_ci = zip->cq_ci;
1858                         zip->ai = 0;
1859                 }
1860         /* No compressed data, get next CQE and verify if it is compressed. */
1861         } else {
1862                 int ret;
1863                 int8_t op_own;
1864
1865                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1866                 if (unlikely(ret == 1))
1867                         return 0;
1868                 ++rxq->cq_ci;
1869                 op_own = cqe->op_own;
1870                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1871                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1872                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1873                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1874                                                           cqe_cnt]);
1875
1876                         /* Fix endianness. */
1877                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1878                         /*
1879                          * Current mini array position is the one returned by
1880                          * check_cqe64().
1881                          *
1882                          * If completion comprises several mini arrays, as a
1883                          * special case the second one is located 7 CQEs after
1884                          * the initial CQE instead of 8 for subsequent ones.
1885                          */
1886                         zip->ca = rxq->cq_ci;
1887                         zip->na = zip->ca + 7;
1888                         /* Compute the next non compressed CQE. */
1889                         --rxq->cq_ci;
1890                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1891                         /* Get packet size to return. */
1892                         len = ntohl((*mc)[0].byte_cnt);
1893                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1894                         zip->ai = 1;
1895                         /* Prefetch all the entries to be invalidated */
1896                         idx = zip->ca;
1897                         end = zip->cq_ci;
1898                         while (idx != end) {
1899                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1900                                 ++idx;
1901                         }
1902                 } else {
1903                         len = ntohl(cqe->byte_cnt);
1904                         *rss_hash = ntohl(cqe->rx_hash_res);
1905                 }
1906                 /* Error while receiving packet. */
1907                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1908                         return -1;
1909         }
1910         return len;
1911 }
1912
1913 /**
1914  * Translate RX completion flags to offload flags.
1915  *
1916  * @param[in] rxq
1917  *   Pointer to RX queue structure.
1918  * @param[in] cqe
1919  *   Pointer to CQE.
1920  *
1921  * @return
1922  *   Offload flags (ol_flags) for struct rte_mbuf.
1923  */
1924 static inline uint32_t
1925 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1926 {
1927         uint32_t ol_flags = 0;
1928         uint16_t flags = ntohs(cqe->hdr_type_etc);
1929
1930         ol_flags =
1931                 TRANSPOSE(flags,
1932                           MLX5_CQE_RX_L3_HDR_VALID,
1933                           PKT_RX_IP_CKSUM_GOOD) |
1934                 TRANSPOSE(flags,
1935                           MLX5_CQE_RX_L4_HDR_VALID,
1936                           PKT_RX_L4_CKSUM_GOOD);
1937         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1938                 ol_flags |=
1939                         TRANSPOSE(flags,
1940                                   MLX5_CQE_RX_L3_HDR_VALID,
1941                                   PKT_RX_IP_CKSUM_GOOD) |
1942                         TRANSPOSE(flags,
1943                                   MLX5_CQE_RX_L4_HDR_VALID,
1944                                   PKT_RX_L4_CKSUM_GOOD);
1945         return ol_flags;
1946 }
1947
1948 /**
1949  * DPDK callback for RX.
1950  *
1951  * @param dpdk_rxq
1952  *   Generic pointer to RX queue structure.
1953  * @param[out] pkts
1954  *   Array to store received packets.
1955  * @param pkts_n
1956  *   Maximum number of packets in array.
1957  *
1958  * @return
1959  *   Number of packets successfully received (<= pkts_n).
1960  */
1961 uint16_t
1962 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1963 {
1964         struct rxq *rxq = dpdk_rxq;
1965         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1966         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1967         const unsigned int sges_n = rxq->sges_n;
1968         struct rte_mbuf *pkt = NULL;
1969         struct rte_mbuf *seg = NULL;
1970         volatile struct mlx5_cqe *cqe =
1971                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1972         unsigned int i = 0;
1973         unsigned int rq_ci = rxq->rq_ci << sges_n;
1974         int len; /* keep its value across iterations. */
1975
1976         while (pkts_n) {
1977                 unsigned int idx = rq_ci & wqe_cnt;
1978                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1979                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1980                 uint32_t rss_hash_res = 0;
1981
1982                 if (pkt)
1983                         NEXT(seg) = rep;
1984                 seg = rep;
1985                 rte_prefetch0(seg);
1986                 rte_prefetch0(cqe);
1987                 rte_prefetch0(wqe);
1988                 rep = rte_mbuf_raw_alloc(rxq->mp);
1989                 if (unlikely(rep == NULL)) {
1990                         ++rxq->stats.rx_nombuf;
1991                         if (!pkt) {
1992                                 /*
1993                                  * no buffers before we even started,
1994                                  * bail out silently.
1995                                  */
1996                                 break;
1997                         }
1998                         while (pkt != seg) {
1999                                 assert(pkt != (*rxq->elts)[idx]);
2000                                 rep = NEXT(pkt);
2001                                 rte_mbuf_refcnt_set(pkt, 0);
2002                                 __rte_mbuf_raw_free(pkt);
2003                                 pkt = rep;
2004                         }
2005                         break;
2006                 }
2007                 if (!pkt) {
2008                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2009                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2010                                                &rss_hash_res);
2011                         if (!len) {
2012                                 rte_mbuf_refcnt_set(rep, 0);
2013                                 __rte_mbuf_raw_free(rep);
2014                                 break;
2015                         }
2016                         if (unlikely(len == -1)) {
2017                                 /* RX error, packet is likely too large. */
2018                                 rte_mbuf_refcnt_set(rep, 0);
2019                                 __rte_mbuf_raw_free(rep);
2020                                 ++rxq->stats.idropped;
2021                                 goto skip;
2022                         }
2023                         pkt = seg;
2024                         assert(len >= (rxq->crc_present << 2));
2025                         /* Update packet information. */
2026                         pkt->packet_type = 0;
2027                         pkt->ol_flags = 0;
2028                         if (rss_hash_res && rxq->rss_hash) {
2029                                 pkt->hash.rss = rss_hash_res;
2030                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2031                         }
2032                         if (rxq->mark && (cqe->sop_drop_qpn !=
2033                                           htonl(MLX5_FLOW_MARK_INVALID))) {
2034                                 pkt->ol_flags |= PKT_RX_FDIR;
2035                                 if (cqe->sop_drop_qpn !=
2036                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2037                                         uint32_t mark = cqe->sop_drop_qpn;
2038
2039                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2040                                         pkt->hash.fdir.hi =
2041                                                 mlx5_flow_mark_get(mark);
2042                                 }
2043                         }
2044                         if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
2045                             rxq->crc_present) {
2046                                 if (rxq->csum) {
2047                                         pkt->packet_type =
2048                                                 rxq_cq_to_pkt_type(cqe);
2049                                         pkt->ol_flags |=
2050                                                 rxq_cq_to_ol_flags(rxq, cqe);
2051                                 }
2052                                 if (ntohs(cqe->hdr_type_etc) &
2053                                     MLX5_CQE_VLAN_STRIPPED) {
2054                                         pkt->ol_flags |= PKT_RX_VLAN_PKT |
2055                                                 PKT_RX_VLAN_STRIPPED;
2056                                         pkt->vlan_tci = ntohs(cqe->vlan_info);
2057                                 }
2058                                 if (rxq->crc_present)
2059                                         len -= ETHER_CRC_LEN;
2060                         }
2061                         PKT_LEN(pkt) = len;
2062                 }
2063                 DATA_LEN(rep) = DATA_LEN(seg);
2064                 PKT_LEN(rep) = PKT_LEN(seg);
2065                 SET_DATA_OFF(rep, DATA_OFF(seg));
2066                 NB_SEGS(rep) = NB_SEGS(seg);
2067                 PORT(rep) = PORT(seg);
2068                 NEXT(rep) = NULL;
2069                 (*rxq->elts)[idx] = rep;
2070                 /*
2071                  * Fill NIC descriptor with the new buffer.  The lkey and size
2072                  * of the buffers are already known, only the buffer address
2073                  * changes.
2074                  */
2075                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2076                 if (len > DATA_LEN(seg)) {
2077                         len -= DATA_LEN(seg);
2078                         ++NB_SEGS(pkt);
2079                         ++rq_ci;
2080                         continue;
2081                 }
2082                 DATA_LEN(seg) = len;
2083 #ifdef MLX5_PMD_SOFT_COUNTERS
2084                 /* Increment bytes counter. */
2085                 rxq->stats.ibytes += PKT_LEN(pkt);
2086 #endif
2087                 /* Return packet. */
2088                 *(pkts++) = pkt;
2089                 pkt = NULL;
2090                 --pkts_n;
2091                 ++i;
2092 skip:
2093                 /* Align consumer index to the next stride. */
2094                 rq_ci >>= sges_n;
2095                 ++rq_ci;
2096                 rq_ci <<= sges_n;
2097         }
2098         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2099                 return 0;
2100         /* Update the consumer index. */
2101         rxq->rq_ci = rq_ci >> sges_n;
2102         rte_wmb();
2103         *rxq->cq_db = htonl(rxq->cq_ci);
2104         rte_wmb();
2105         *rxq->rq_db = htonl(rxq->rq_ci);
2106 #ifdef MLX5_PMD_SOFT_COUNTERS
2107         /* Increment packets counter. */
2108         rxq->stats.ipackets += i;
2109 #endif
2110         return i;
2111 }
2112
2113 /**
2114  * Dummy DPDK callback for TX.
2115  *
2116  * This function is used to temporarily replace the real callback during
2117  * unsafe control operations on the queue, or in case of error.
2118  *
2119  * @param dpdk_txq
2120  *   Generic pointer to TX queue structure.
2121  * @param[in] pkts
2122  *   Packets to transmit.
2123  * @param pkts_n
2124  *   Number of packets in array.
2125  *
2126  * @return
2127  *   Number of packets successfully transmitted (<= pkts_n).
2128  */
2129 uint16_t
2130 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2131 {
2132         (void)dpdk_txq;
2133         (void)pkts;
2134         (void)pkts_n;
2135         return 0;
2136 }
2137
2138 /**
2139  * Dummy DPDK callback for RX.
2140  *
2141  * This function is used to temporarily replace the real callback during
2142  * unsafe control operations on the queue, or in case of error.
2143  *
2144  * @param dpdk_rxq
2145  *   Generic pointer to RX queue structure.
2146  * @param[out] pkts
2147  *   Array to store received packets.
2148  * @param pkts_n
2149  *   Maximum number of packets in array.
2150  *
2151  * @return
2152  *   Number of packets successfully received (<= pkts_n).
2153  */
2154 uint16_t
2155 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2156 {
2157         (void)dpdk_rxq;
2158         (void)pkts;
2159         (void)pkts_n;
2160         return 0;
2161 }
2162
2163 /**
2164  * DPDK callback for rx queue interrupt enable.
2165  *
2166  * @param dev
2167  *   Pointer to Ethernet device structure.
2168  * @param rx_queue_id
2169  *   RX queue number
2170  *
2171  * @return
2172  *   0 on success, negative on failure.
2173  */
2174 int
2175 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2176 {
2177 #ifdef HAVE_UPDATE_CQ_CI
2178         struct priv *priv = mlx5_get_priv(dev);
2179         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2180         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2181         struct ibv_cq *cq = rxq_ctrl->cq;
2182         uint16_t ci = rxq->cq_ci;
2183         int ret = 0;
2184
2185         ibv_mlx5_exp_update_cq_ci(cq, ci);
2186         ret = ibv_req_notify_cq(cq, 0);
2187 #else
2188         int ret = -1;
2189         (void)dev;
2190         (void)rx_queue_id;
2191 #endif
2192         if (ret)
2193                 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2194         return ret;
2195 }
2196
2197 /**
2198  * DPDK callback for rx queue interrupt disable.
2199  *
2200  * @param dev
2201  *   Pointer to Ethernet device structure.
2202  * @param rx_queue_id
2203  *   RX queue number
2204  *
2205  * @return
2206  *   0 on success, negative on failure.
2207  */
2208 int
2209 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2210 {
2211 #ifdef HAVE_UPDATE_CQ_CI
2212         struct priv *priv = mlx5_get_priv(dev);
2213         struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2214         struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2215         struct ibv_cq *cq = rxq_ctrl->cq;
2216         struct ibv_cq *ev_cq;
2217         void *ev_ctx;
2218         int ret = 0;
2219
2220         ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2221         if (ret || ev_cq != cq)
2222                 ret = -1;
2223         else
2224                 ibv_ack_cq_events(cq, 1);
2225 #else
2226         int ret = -1;
2227         (void)dev;
2228         (void)rx_queue_id;
2229 #endif
2230         if (ret)
2231                 WARN("unable to disable interrupt on rx queue %d",
2232                      rx_queue_id);
2233         return ret;
2234 }