drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, uint32_t *rss_hash);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  45
  46 static __rte_always_inline void
  47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  48                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  49
  50 static __rte_always_inline void
  51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  52
  53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  54         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  55 };
  56
  57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  59
  60 /**
  61  * Build a table to translate Rx completion flags to packet type.
  62  *
  63  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  64  */
  65 void
  66 mlx5_set_ptype_table(void)
  67 {
  68         unsigned int i;
  69         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  70
  71         /* Last entry must not be overwritten, reserved for errored packet. */
  72         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  73                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  74         /*
  75          * The index to the array should have:
  76          * bit[1:0] = l3_hdr_type
  77          * bit[4:2] = l4_hdr_type
  78          * bit[5] = ip_frag
  79          * bit[6] = tunneled
  80          * bit[7] = outer_l3_type
  81          */
  82         /* L2 */
  83         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  84         /* L3 */
  85         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_NONFRAG;
  87         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_NONFRAG;
  89         /* Fragmented */
  90         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  91                      RTE_PTYPE_L4_FRAG;
  92         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  93                      RTE_PTYPE_L4_FRAG;
  94         /* TCP */
  95         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  96                      RTE_PTYPE_L4_TCP;
  97         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  98                      RTE_PTYPE_L4_TCP;
  99         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 100                      RTE_PTYPE_L4_TCP;
 101         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 102                      RTE_PTYPE_L4_TCP;
 103         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_TCP;
 105         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_TCP;
 107         /* UDP */
 108         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 109                      RTE_PTYPE_L4_UDP;
 110         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 111                      RTE_PTYPE_L4_UDP;
 112         /* Repeat with outer_l3_type being set. Just in case. */
 113         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_NONFRAG;
 115         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_NONFRAG;
 117         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_FRAG;
 119         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_FRAG;
 121         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_TCP;
 125         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_TCP;
 127         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 128                      RTE_PTYPE_L4_TCP;
 129         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 130                      RTE_PTYPE_L4_TCP;
 131         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_L4_TCP;
 133         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 134                      RTE_PTYPE_L4_UDP;
 135         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 136                      RTE_PTYPE_L4_UDP;
 137         /* Tunneled - L3 */
 138         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 139         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 140                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L4_NONFRAG;
 142         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L4_NONFRAG;
 145         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 146         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 147                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L4_NONFRAG;
 149         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 150                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L4_NONFRAG;
 152         /* Tunneled - Fragmented */
 153         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 154                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L4_FRAG;
 156         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 157                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L4_FRAG;
 159         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 160                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L4_FRAG;
 162         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 163                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L4_FRAG;
 165         /* Tunneled - TCP */
 166         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 191                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L4_TCP;
 193         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 194                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L4_TCP;
 196         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 197                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L4_TCP;
 199         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 200                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L4_TCP;
 202         /* Tunneled - UDP */
 203         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 204                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L4_UDP;
 206         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 207                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L4_UDP;
 209         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 210                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L4_UDP;
 212         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 213                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L4_UDP;
 215 }
 216
 217 /**
 218  * Build a table to translate packet to checksum type of Verbs.
 219  */
 220 void
 221 mlx5_set_cksum_table(void)
 222 {
 223         unsigned int i;
 224         uint8_t v;
 225
 226         /*
 227          * The index should have:
 228          * bit[0] = PKT_TX_TCP_SEG
 229          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 230          * bit[4] = PKT_TX_IP_CKSUM
 231          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 232          * bit[9] = tunnel
 233          */
 234         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 235                 v = 0;
 236                 if (i & (1 << 9)) {
 237                         /* Tunneled packet. */
 238                         if (i & (1 << 8)) /* Outer IP. */
 239                                 v |= MLX5_ETH_WQE_L3_CSUM;
 240                         if (i & (1 << 4)) /* Inner IP. */
 241                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 242                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 243                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 244                 } else {
 245                         /* No tunnel. */
 246                         if (i & (1 << 4)) /* IP. */
 247                                 v |= MLX5_ETH_WQE_L3_CSUM;
 248                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 249                                 v |= MLX5_ETH_WQE_L4_CSUM;
 250                 }
 251                 mlx5_cksum_table[i] = v;
 252         }
 253 }
 254
 255 /**
 256  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 257  */
 258 void
 259 mlx5_set_swp_types_table(void)
 260 {
 261         unsigned int i;
 262         uint8_t v;
 263
 264         /*
 265          * The index should have:
 266          * bit[0:1] = PKT_TX_L4_MASK
 267          * bit[4] = PKT_TX_IPV6
 268          * bit[8] = PKT_TX_OUTER_IPV6
 269          * bit[9] = PKT_TX_OUTER_UDP
 270          */
 271         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 272                 v = 0;
 273                 if (i & (1 << 8))
 274                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 275                 if (i & (1 << 9))
 276                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 277                 if (i & (1 << 4))
 278                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 279                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 280                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 281                 mlx5_swp_types_table[i] = v;
 282         }
 283 }
 284
 285 /**
 286  * Return the size of tailroom of WQ.
 287  *
 288  * @param txq
 289  *   Pointer to TX queue structure.
 290  * @param addr
 291  *   Pointer to tail of WQ.
 292  *
 293  * @return
 294  *   Size of tailroom.
 295  */
 296 static inline size_t
 297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 298 {
 299         size_t tailroom;
 300         tailroom = (uintptr_t)(txq->wqes) +
 301                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 302                    (uintptr_t)addr;
 303         return tailroom;
 304 }
 305
 306 /**
 307  * Copy data to tailroom of circular queue.
 308  *
 309  * @param dst
 310  *   Pointer to destination.
 311  * @param src
 312  *   Pointer to source.
 313  * @param n
 314  *   Number of bytes to copy.
 315  * @param base
 316  *   Pointer to head of queue.
 317  * @param tailroom
 318  *   Size of tailroom from dst.
 319  *
 320  * @return
 321  *   Pointer after copied data.
 322  */
 323 static inline void *
 324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 325                 void *base, size_t tailroom)
 326 {
 327         void *ret;
 328
 329         if (n > tailroom) {
 330                 rte_memcpy(dst, src, tailroom);
 331                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 332                            n - tailroom);
 333                 ret = (uint8_t *)base + n - tailroom;
 334         } else {
 335                 rte_memcpy(dst, src, n);
 336                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 337         }
 338         return ret;
 339 }
 340
 341 /**
 342  * Inline TSO headers into WQE.
 343  *
 344  * @return
 345  *   0 on success, negative errno value on failure.
 346  */
 347 static int
 348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 349            uint32_t *length,
 350            uintptr_t *addr,
 351            uint16_t *pkt_inline_sz,
 352            uint8_t **raw,
 353            uint16_t *max_wqe,
 354            uint16_t *tso_segsz,
 355            uint16_t *tso_header_sz)
 356 {
 357         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 358                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 359         unsigned int copy_b;
 360         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 361         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 362                                  PKT_TX_TUNNEL_MASK);
 363         uint16_t n_wqe;
 364
 365         *tso_segsz = buf->tso_segsz;
 366         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 367         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 368                 txq->stats.oerrors++;
 369                 return -EINVAL;
 370         }
 371         if (tunneled)
 372                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 373         /* First seg must contain all TSO headers. */
 374         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 375                      *tso_header_sz > DATA_LEN(buf)) {
 376                 txq->stats.oerrors++;
 377                 return -EINVAL;
 378         }
 379         copy_b = *tso_header_sz - *pkt_inline_sz;
 380         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 381                 return -EAGAIN;
 382         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 383         if (unlikely(*max_wqe < n_wqe))
 384                 return -EINVAL;
 385         *max_wqe -= n_wqe;
 386         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 387         *length -= copy_b;
 388         *addr += copy_b;
 389         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 390         *pkt_inline_sz += copy_b;
 391         *raw += copy_b;
 392         return 0;
 393 }
 394
 395 /**
 396  * DPDK callback to check the status of a tx descriptor.
 397  *
 398  * @param tx_queue
 399  *   The tx queue.
 400  * @param[in] offset
 401  *   The index of the descriptor in the ring.
 402  *
 403  * @return
 404  *   The status of the tx descriptor.
 405  */
 406 int
 407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 408 {
 409         struct mlx5_txq_data *txq = tx_queue;
 410         uint16_t used;
 411
 412         mlx5_tx_complete(txq);
 413         used = txq->elts_head - txq->elts_tail;
 414         if (offset < used)
 415                 return RTE_ETH_TX_DESC_FULL;
 416         return RTE_ETH_TX_DESC_DONE;
 417 }
 418
 419 /**
 420  * DPDK callback to check the status of a rx descriptor.
 421  *
 422  * @param rx_queue
 423  *   The rx queue.
 424  * @param[in] offset
 425  *   The index of the descriptor in the ring.
 426  *
 427  * @return
 428  *   The status of the tx descriptor.
 429  */
 430 int
 431 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 432 {
 433         struct mlx5_rxq_data *rxq = rx_queue;
 434         struct rxq_zip *zip = &rxq->zip;
 435         volatile struct mlx5_cqe *cqe;
 436         const unsigned int cqe_n = (1 << rxq->cqe_n);
 437         const unsigned int cqe_cnt = cqe_n - 1;
 438         unsigned int cq_ci;
 439         unsigned int used;
 440
 441         /* if we are processing a compressed cqe */
 442         if (zip->ai) {
 443                 used = zip->cqe_cnt - zip->ca;
 444                 cq_ci = zip->cq_ci;
 445         } else {
 446                 used = 0;
 447                 cq_ci = rxq->cq_ci;
 448         }
 449         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 450         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 451                 int8_t op_own;
 452                 unsigned int n;
 453
 454                 op_own = cqe->op_own;
 455                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 456                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 457                 else
 458                         n = 1;
 459                 cq_ci += n;
 460                 used += n;
 461                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 462         }
 463         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 464         if (offset < used)
 465                 return RTE_ETH_RX_DESC_DONE;
 466         return RTE_ETH_RX_DESC_AVAIL;
 467 }
 468
 469 /**
 470  * DPDK callback for TX.
 471  *
 472  * @param dpdk_txq
 473  *   Generic pointer to TX queue structure.
 474  * @param[in] pkts
 475  *   Packets to transmit.
 476  * @param pkts_n
 477  *   Number of packets in array.
 478  *
 479  * @return
 480  *   Number of packets successfully transmitted (<= pkts_n).
 481  */
 482 uint16_t
 483 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 484 {
 485         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 486         uint16_t elts_head = txq->elts_head;
 487         const uint16_t elts_n = 1 << txq->elts_n;
 488         const uint16_t elts_m = elts_n - 1;
 489         unsigned int i = 0;
 490         unsigned int j = 0;
 491         unsigned int k = 0;
 492         uint16_t max_elts;
 493         uint16_t max_wqe;
 494         unsigned int comp;
 495         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 496         unsigned int segs_n = 0;
 497         const unsigned int max_inline = txq->max_inline;
 498
 499         if (unlikely(!pkts_n))
 500                 return 0;
 501         /* Prefetch first packet cacheline. */
 502         rte_prefetch0(*pkts);
 503         /* Start processing. */
 504         mlx5_tx_complete(txq);
 505         max_elts = (elts_n - (elts_head - txq->elts_tail));
 506         /* A CQE slot must always be available. */
 507         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 508         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 509         if (unlikely(!max_wqe))
 510                 return 0;
 511         do {
 512                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 513                 uint8_t *raw;
 514                 volatile struct mlx5_wqe_v *wqe = NULL;
 515                 volatile rte_v128u32_t *dseg = NULL;
 516                 uint32_t length;
 517                 unsigned int ds = 0;
 518                 unsigned int sg = 0; /* counter of additional segs attached. */
 519                 uintptr_t addr;
 520                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 521                 uint16_t tso_header_sz = 0;
 522                 uint16_t ehdr;
 523                 uint8_t cs_flags;
 524                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 525                 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
 526                 uint32_t swp_offsets = 0;
 527                 uint8_t swp_types = 0;
 528                 uint16_t tso_segsz = 0;
 529 #ifdef MLX5_PMD_SOFT_COUNTERS
 530                 uint32_t total_length = 0;
 531 #endif
 532                 int ret;
 533
 534                 segs_n = buf->nb_segs;
 535                 /*
 536                  * Make sure there is enough room to store this packet and
 537                  * that one ring entry remains unused.
 538                  */
 539                 assert(segs_n);
 540                 if (max_elts < segs_n)
 541                         break;
 542                 max_elts -= segs_n;
 543                 sg = --segs_n;
 544                 if (unlikely(--max_wqe == 0))
 545                         break;
 546                 wqe = (volatile struct mlx5_wqe_v *)
 547                         tx_mlx5_wqe(txq, txq->wqe_ci);
 548                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 549                 if (pkts_n - i > 1)
 550                         rte_prefetch0(*(pkts + 1));
 551                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 552                 length = DATA_LEN(buf);
 553                 ehdr = (((uint8_t *)addr)[1] << 8) |
 554                        ((uint8_t *)addr)[0];
 555 #ifdef MLX5_PMD_SOFT_COUNTERS
 556                 total_length = length;
 557 #endif
 558                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 559                         txq->stats.oerrors++;
 560                         break;
 561                 }
 562                 /* Update element. */
 563                 (*txq->elts)[elts_head & elts_m] = buf;
 564                 /* Prefetch next buffer data. */
 565                 if (pkts_n - i > 1)
 566                         rte_prefetch0(
 567                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 568                 cs_flags = txq_ol_cksum_to_cs(buf);
 569                 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
 570                                 (uint8_t *)&swp_offsets, &swp_types);
 571                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 572                 /* Replace the Ethernet type by the VLAN if necessary. */
 573                 if (is_vlan) {
 574                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 575                                                          buf->vlan_tci);
 576                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 577
 578                         addr += 2;
 579                         length -= 2;
 580                         /* Copy Destination and source mac address. */
 581                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 582                         /* Copy VLAN. */
 583                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 584                         /* Copy missing two bytes to end the DSeg. */
 585                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 586                                ((uint8_t *)addr) + len, 2);
 587                         addr += len + 2;
 588                         length -= (len + 2);
 589                 } else {
 590                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 591                                MLX5_WQE_DWORD_SIZE);
 592                         length -= pkt_inline_sz;
 593                         addr += pkt_inline_sz;
 594                 }
 595                 raw += MLX5_WQE_DWORD_SIZE;
 596                 if (tso) {
 597                         ret = inline_tso(txq, buf, &length,
 598                                          &addr, &pkt_inline_sz,
 599                                          &raw, &max_wqe,
 600                                          &tso_segsz, &tso_header_sz);
 601                         if (ret == -EINVAL) {
 602                                 break;
 603                         } else if (ret == -EAGAIN) {
 604                                 /* NOP WQE. */
 605                                 wqe->ctrl = (rte_v128u32_t){
 606                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 607                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 608                                         0,
 609                                         0,
 610                                 };
 611                                 ds = 1;
 612 #ifdef MLX5_PMD_SOFT_COUNTERS
 613                                 total_length = 0;
 614 #endif
 615                                 k++;
 616                                 goto next_wqe;
 617                         }
 618                 }
 619                 /* Inline if enough room. */
 620                 if (max_inline || tso) {
 621                         uint32_t inl = 0;
 622                         uintptr_t end = (uintptr_t)
 623                                 (((uintptr_t)txq->wqes) +
 624                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 625                         unsigned int inline_room = max_inline *
 626                                                    RTE_CACHE_LINE_SIZE -
 627                                                    (pkt_inline_sz - 2) -
 628                                                    !!tso * sizeof(inl);
 629                         uintptr_t addr_end;
 630                         unsigned int copy_b;
 631
 632 pkt_inline:
 633                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 634                                                    RTE_CACHE_LINE_SIZE);
 635                         copy_b = (addr_end > addr) ?
 636                                  RTE_MIN((addr_end - addr), length) : 0;
 637                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 638                                 /*
 639                                  * One Dseg remains in the current WQE.  To
 640                                  * keep the computation positive, it is
 641                                  * removed after the bytes to Dseg conversion.
 642                                  */
 643                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 644
 645                                 if (unlikely(max_wqe < n))
 646                                         break;
 647                                 max_wqe -= n;
 648                                 if (tso && !inl) {
 649                                         inl = rte_cpu_to_be_32(copy_b |
 650                                                                MLX5_INLINE_SEG);
 651                                         rte_memcpy((void *)raw,
 652                                                    (void *)&inl, sizeof(inl));
 653                                         raw += sizeof(inl);
 654                                         pkt_inline_sz += sizeof(inl);
 655                                 }
 656                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 657                                 addr += copy_b;
 658                                 length -= copy_b;
 659                                 pkt_inline_sz += copy_b;
 660                         }
 661                         /*
 662                          * 2 DWORDs consumed by the WQE header + ETH segment +
 663                          * the size of the inline part of the packet.
 664                          */
 665                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 666                         if (length > 0) {
 667                                 if (ds % (MLX5_WQE_SIZE /
 668                                           MLX5_WQE_DWORD_SIZE) == 0) {
 669                                         if (unlikely(--max_wqe == 0))
 670                                                 break;
 671                                         dseg = (volatile rte_v128u32_t *)
 672                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 673                                                            ds / 4);
 674                                 } else {
 675                                         dseg = (volatile rte_v128u32_t *)
 676                                                 ((uintptr_t)wqe +
 677                                                  (ds * MLX5_WQE_DWORD_SIZE));
 678                                 }
 679                                 goto use_dseg;
 680                         } else if (!segs_n) {
 681                                 goto next_pkt;
 682                         } else {
 683                                 raw += copy_b;
 684                                 inline_room -= copy_b;
 685                                 --segs_n;
 686                                 buf = buf->next;
 687                                 assert(buf);
 688                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 689                                 length = DATA_LEN(buf);
 690 #ifdef MLX5_PMD_SOFT_COUNTERS
 691                                 total_length += length;
 692 #endif
 693                                 (*txq->elts)[++elts_head & elts_m] = buf;
 694                                 goto pkt_inline;
 695                         }
 696                 } else {
 697                         /*
 698                          * No inline has been done in the packet, only the
 699                          * Ethernet Header as been stored.
 700                          */
 701                         dseg = (volatile rte_v128u32_t *)
 702                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 703                         ds = 3;
 704 use_dseg:
 705                         /* Add the remaining packet as a simple ds. */
 706                         addr = rte_cpu_to_be_64(addr);
 707                         *dseg = (rte_v128u32_t){
 708                                 rte_cpu_to_be_32(length),
 709                                 mlx5_tx_mb2mr(txq, buf),
 710                                 addr,
 711                                 addr >> 32,
 712                         };
 713                         ++ds;
 714                         if (!segs_n)
 715                                 goto next_pkt;
 716                 }
 717 next_seg:
 718                 assert(buf);
 719                 assert(ds);
 720                 assert(wqe);
 721                 /*
 722                  * Spill on next WQE when the current one does not have
 723                  * enough room left. Size of WQE must a be a multiple
 724                  * of data segment size.
 725                  */
 726                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 727                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 728                         if (unlikely(--max_wqe == 0))
 729                                 break;
 730                         dseg = (volatile rte_v128u32_t *)
 731                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 732                         rte_prefetch0(tx_mlx5_wqe(txq,
 733                                                   txq->wqe_ci + ds / 4 + 1));
 734                 } else {
 735                         ++dseg;
 736                 }
 737                 ++ds;
 738                 buf = buf->next;
 739                 assert(buf);
 740                 length = DATA_LEN(buf);
 741 #ifdef MLX5_PMD_SOFT_COUNTERS
 742                 total_length += length;
 743 #endif
 744                 /* Store segment information. */
 745                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 746                 *dseg = (rte_v128u32_t){
 747                         rte_cpu_to_be_32(length),
 748                         mlx5_tx_mb2mr(txq, buf),
 749                         addr,
 750                         addr >> 32,
 751                 };
 752                 (*txq->elts)[++elts_head & elts_m] = buf;
 753                 if (--segs_n)
 754                         goto next_seg;
 755 next_pkt:
 756                 if (ds > MLX5_DSEG_MAX) {
 757                         txq->stats.oerrors++;
 758                         break;
 759                 }
 760                 ++elts_head;
 761                 ++pkts;
 762                 ++i;
 763                 j += sg;
 764                 /* Initialize known and common part of the WQE structure. */
 765                 if (tso) {
 766                         wqe->ctrl = (rte_v128u32_t){
 767                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 768                                                  MLX5_OPCODE_TSO),
 769                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 770                                 0,
 771                                 0,
 772                         };
 773                         wqe->eseg = (rte_v128u32_t){
 774                                 swp_offsets,
 775                                 cs_flags | (swp_types << 8) |
 776                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 777                                 0,
 778                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 779                         };
 780                 } else {
 781                         wqe->ctrl = (rte_v128u32_t){
 782                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 783                                                  MLX5_OPCODE_SEND),
 784                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 785                                 0,
 786                                 0,
 787                         };
 788                         wqe->eseg = (rte_v128u32_t){
 789                                 swp_offsets,
 790                                 cs_flags | (swp_types << 8),
 791                                 0,
 792                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 793                         };
 794                 }
 795 next_wqe:
 796                 txq->wqe_ci += (ds + 3) / 4;
 797                 /* Save the last successful WQE for completion request */
 798                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 799 #ifdef MLX5_PMD_SOFT_COUNTERS
 800                 /* Increment sent bytes counter. */
 801                 txq->stats.obytes += total_length;
 802 #endif
 803         } while (i < pkts_n);
 804         /* Take a shortcut if nothing must be sent. */
 805         if (unlikely((i + k) == 0))
 806                 return 0;
 807         txq->elts_head += (i + j);
 808         /* Check whether completion threshold has been reached. */
 809         comp = txq->elts_comp + i + j + k;
 810         if (comp >= MLX5_TX_COMP_THRESH) {
 811                 /* Request completion on last WQE. */
 812                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 813                 /* Save elts_head in unused "immediate" field of WQE. */
 814                 last_wqe->ctrl3 = txq->elts_head;
 815                 txq->elts_comp = 0;
 816 #ifndef NDEBUG
 817                 ++txq->cq_pi;
 818 #endif
 819         } else {
 820                 txq->elts_comp = comp;
 821         }
 822 #ifdef MLX5_PMD_SOFT_COUNTERS
 823         /* Increment sent packets counter. */
 824         txq->stats.opackets += i;
 825 #endif
 826         /* Ring QP doorbell. */
 827         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 828         return i;
 829 }
 830
 831 /**
 832  * Open a MPW session.
 833  *
 834  * @param txq
 835  *   Pointer to TX queue structure.
 836  * @param mpw
 837  *   Pointer to MPW session structure.
 838  * @param length
 839  *   Packet length.
 840  */
 841 static inline void
 842 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 843 {
 844         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 845         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 846                 (volatile struct mlx5_wqe_data_seg (*)[])
 847                 tx_mlx5_wqe(txq, idx + 1);
 848
 849         mpw->state = MLX5_MPW_STATE_OPENED;
 850         mpw->pkts_n = 0;
 851         mpw->len = length;
 852         mpw->total_len = 0;
 853         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 854         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 855         mpw->wqe->eseg.inline_hdr_sz = 0;
 856         mpw->wqe->eseg.rsvd0 = 0;
 857         mpw->wqe->eseg.rsvd1 = 0;
 858         mpw->wqe->eseg.rsvd2 = 0;
 859         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 860                                              (txq->wqe_ci << 8) |
 861                                              MLX5_OPCODE_TSO);
 862         mpw->wqe->ctrl[2] = 0;
 863         mpw->wqe->ctrl[3] = 0;
 864         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 865                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 866         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 867                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 868         mpw->data.dseg[2] = &(*dseg)[0];
 869         mpw->data.dseg[3] = &(*dseg)[1];
 870         mpw->data.dseg[4] = &(*dseg)[2];
 871 }
 872
 873 /**
 874  * Close a MPW session.
 875  *
 876  * @param txq
 877  *   Pointer to TX queue structure.
 878  * @param mpw
 879  *   Pointer to MPW session structure.
 880  */
 881 static inline void
 882 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 883 {
 884         unsigned int num = mpw->pkts_n;
 885
 886         /*
 887          * Store size in multiple of 16 bytes. Control and Ethernet segments
 888          * count as 2.
 889          */
 890         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 891         mpw->state = MLX5_MPW_STATE_CLOSED;
 892         if (num < 3)
 893                 ++txq->wqe_ci;
 894         else
 895                 txq->wqe_ci += 2;
 896         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 897         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 898 }
 899
 900 /**
 901  * DPDK callback for TX with MPW support.
 902  *
 903  * @param dpdk_txq
 904  *   Generic pointer to TX queue structure.
 905  * @param[in] pkts
 906  *   Packets to transmit.
 907  * @param pkts_n
 908  *   Number of packets in array.
 909  *
 910  * @return
 911  *   Number of packets successfully transmitted (<= pkts_n).
 912  */
 913 uint16_t
 914 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 915 {
 916         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 917         uint16_t elts_head = txq->elts_head;
 918         const uint16_t elts_n = 1 << txq->elts_n;
 919         const uint16_t elts_m = elts_n - 1;
 920         unsigned int i = 0;
 921         unsigned int j = 0;
 922         uint16_t max_elts;
 923         uint16_t max_wqe;
 924         unsigned int comp;
 925         struct mlx5_mpw mpw = {
 926                 .state = MLX5_MPW_STATE_CLOSED,
 927         };
 928
 929         if (unlikely(!pkts_n))
 930                 return 0;
 931         /* Prefetch first packet cacheline. */
 932         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 933         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 934         /* Start processing. */
 935         mlx5_tx_complete(txq);
 936         max_elts = (elts_n - (elts_head - txq->elts_tail));
 937         /* A CQE slot must always be available. */
 938         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 939         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 940         if (unlikely(!max_wqe))
 941                 return 0;
 942         do {
 943                 struct rte_mbuf *buf = *(pkts++);
 944                 uint32_t length;
 945                 unsigned int segs_n = buf->nb_segs;
 946                 uint32_t cs_flags;
 947
 948                 /*
 949                  * Make sure there is enough room to store this packet and
 950                  * that one ring entry remains unused.
 951                  */
 952                 assert(segs_n);
 953                 if (max_elts < segs_n)
 954                         break;
 955                 /* Do not bother with large packets MPW cannot handle. */
 956                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 957                         txq->stats.oerrors++;
 958                         break;
 959                 }
 960                 max_elts -= segs_n;
 961                 --pkts_n;
 962                 cs_flags = txq_ol_cksum_to_cs(buf);
 963                 /* Retrieve packet information. */
 964                 length = PKT_LEN(buf);
 965                 assert(length);
 966                 /* Start new session if packet differs. */
 967                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 968                     ((mpw.len != length) ||
 969                      (segs_n != 1) ||
 970                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 971                         mlx5_mpw_close(txq, &mpw);
 972                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 973                         /*
 974                          * Multi-Packet WQE consumes at most two WQE.
 975                          * mlx5_mpw_new() expects to be able to use such
 976                          * resources.
 977                          */
 978                         if (unlikely(max_wqe < 2))
 979                                 break;
 980                         max_wqe -= 2;
 981                         mlx5_mpw_new(txq, &mpw, length);
 982                         mpw.wqe->eseg.cs_flags = cs_flags;
 983                 }
 984                 /* Multi-segment packets must be alone in their MPW. */
 985                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 986 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 987                 length = 0;
 988 #endif
 989                 do {
 990                         volatile struct mlx5_wqe_data_seg *dseg;
 991                         uintptr_t addr;
 992
 993                         assert(buf);
 994                         (*txq->elts)[elts_head++ & elts_m] = buf;
 995                         dseg = mpw.data.dseg[mpw.pkts_n];
 996                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 997                         *dseg = (struct mlx5_wqe_data_seg){
 998                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 999                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1000                                 .addr = rte_cpu_to_be_64(addr),
1001                         };
1002 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1003                         length += DATA_LEN(buf);
1004 #endif
1005                         buf = buf->next;
1006                         ++mpw.pkts_n;
1007                         ++j;
1008                 } while (--segs_n);
1009                 assert(length == mpw.len);
1010                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1011                         mlx5_mpw_close(txq, &mpw);
1012 #ifdef MLX5_PMD_SOFT_COUNTERS
1013                 /* Increment sent bytes counter. */
1014                 txq->stats.obytes += length;
1015 #endif
1016                 ++i;
1017         } while (pkts_n);
1018         /* Take a shortcut if nothing must be sent. */
1019         if (unlikely(i == 0))
1020                 return 0;
1021         /* Check whether completion threshold has been reached. */
1022         /* "j" includes both packets and segments. */
1023         comp = txq->elts_comp + j;
1024         if (comp >= MLX5_TX_COMP_THRESH) {
1025                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1026
1027                 /* Request completion on last WQE. */
1028                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1029                 /* Save elts_head in unused "immediate" field of WQE. */
1030                 wqe->ctrl[3] = elts_head;
1031                 txq->elts_comp = 0;
1032 #ifndef NDEBUG
1033                 ++txq->cq_pi;
1034 #endif
1035         } else {
1036                 txq->elts_comp = comp;
1037         }
1038 #ifdef MLX5_PMD_SOFT_COUNTERS
1039         /* Increment sent packets counter. */
1040         txq->stats.opackets += i;
1041 #endif
1042         /* Ring QP doorbell. */
1043         if (mpw.state == MLX5_MPW_STATE_OPENED)
1044                 mlx5_mpw_close(txq, &mpw);
1045         mlx5_tx_dbrec(txq, mpw.wqe);
1046         txq->elts_head = elts_head;
1047         return i;
1048 }
1049
1050 /**
1051  * Open a MPW inline session.
1052  *
1053  * @param txq
1054  *   Pointer to TX queue structure.
1055  * @param mpw
1056  *   Pointer to MPW session structure.
1057  * @param length
1058  *   Packet length.
1059  */
1060 static inline void
1061 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1062                     uint32_t length)
1063 {
1064         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1065         struct mlx5_wqe_inl_small *inl;
1066
1067         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1068         mpw->pkts_n = 0;
1069         mpw->len = length;
1070         mpw->total_len = 0;
1071         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1072         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1073                                              (txq->wqe_ci << 8) |
1074                                              MLX5_OPCODE_TSO);
1075         mpw->wqe->ctrl[2] = 0;
1076         mpw->wqe->ctrl[3] = 0;
1077         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1078         mpw->wqe->eseg.inline_hdr_sz = 0;
1079         mpw->wqe->eseg.cs_flags = 0;
1080         mpw->wqe->eseg.rsvd0 = 0;
1081         mpw->wqe->eseg.rsvd1 = 0;
1082         mpw->wqe->eseg.rsvd2 = 0;
1083         inl = (struct mlx5_wqe_inl_small *)
1084                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1085         mpw->data.raw = (uint8_t *)&inl->raw;
1086 }
1087
1088 /**
1089  * Close a MPW inline session.
1090  *
1091  * @param txq
1092  *   Pointer to TX queue structure.
1093  * @param mpw
1094  *   Pointer to MPW session structure.
1095  */
1096 static inline void
1097 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1098 {
1099         unsigned int size;
1100         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1101                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1102
1103         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1104         /*
1105          * Store size in multiple of 16 bytes. Control and Ethernet segments
1106          * count as 2.
1107          */
1108         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1109                                              MLX5_WQE_DS(size));
1110         mpw->state = MLX5_MPW_STATE_CLOSED;
1111         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1112         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1113 }
1114
1115 /**
1116  * DPDK callback for TX with MPW inline support.
1117  *
1118  * @param dpdk_txq
1119  *   Generic pointer to TX queue structure.
1120  * @param[in] pkts
1121  *   Packets to transmit.
1122  * @param pkts_n
1123  *   Number of packets in array.
1124  *
1125  * @return
1126  *   Number of packets successfully transmitted (<= pkts_n).
1127  */
1128 uint16_t
1129 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1130                          uint16_t pkts_n)
1131 {
1132         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1133         uint16_t elts_head = txq->elts_head;
1134         const uint16_t elts_n = 1 << txq->elts_n;
1135         const uint16_t elts_m = elts_n - 1;
1136         unsigned int i = 0;
1137         unsigned int j = 0;
1138         uint16_t max_elts;
1139         uint16_t max_wqe;
1140         unsigned int comp;
1141         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1142         struct mlx5_mpw mpw = {
1143                 .state = MLX5_MPW_STATE_CLOSED,
1144         };
1145         /*
1146          * Compute the maximum number of WQE which can be consumed by inline
1147          * code.
1148          * - 2 DSEG for:
1149          *   - 1 control segment,
1150          *   - 1 Ethernet segment,
1151          * - N Dseg from the inline request.
1152          */
1153         const unsigned int wqe_inl_n =
1154                 ((2 * MLX5_WQE_DWORD_SIZE +
1155                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1156                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1157
1158         if (unlikely(!pkts_n))
1159                 return 0;
1160         /* Prefetch first packet cacheline. */
1161         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1162         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1163         /* Start processing. */
1164         mlx5_tx_complete(txq);
1165         max_elts = (elts_n - (elts_head - txq->elts_tail));
1166         /* A CQE slot must always be available. */
1167         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1168         do {
1169                 struct rte_mbuf *buf = *(pkts++);
1170                 uintptr_t addr;
1171                 uint32_t length;
1172                 unsigned int segs_n = buf->nb_segs;
1173                 uint8_t cs_flags;
1174
1175                 /*
1176                  * Make sure there is enough room to store this packet and
1177                  * that one ring entry remains unused.
1178                  */
1179                 assert(segs_n);
1180                 if (max_elts < segs_n)
1181                         break;
1182                 /* Do not bother with large packets MPW cannot handle. */
1183                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1184                         txq->stats.oerrors++;
1185                         break;
1186                 }
1187                 max_elts -= segs_n;
1188                 --pkts_n;
1189                 /*
1190                  * Compute max_wqe in case less WQE were consumed in previous
1191                  * iteration.
1192                  */
1193                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1194                 cs_flags = txq_ol_cksum_to_cs(buf);
1195                 /* Retrieve packet information. */
1196                 length = PKT_LEN(buf);
1197                 /* Start new session if packet differs. */
1198                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1199                         if ((mpw.len != length) ||
1200                             (segs_n != 1) ||
1201                             (mpw.wqe->eseg.cs_flags != cs_flags))
1202                                 mlx5_mpw_close(txq, &mpw);
1203                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1204                         if ((mpw.len != length) ||
1205                             (segs_n != 1) ||
1206                             (length > inline_room) ||
1207                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1208                                 mlx5_mpw_inline_close(txq, &mpw);
1209                                 inline_room =
1210                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1211                         }
1212                 }
1213                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1214                         if ((segs_n != 1) ||
1215                             (length > inline_room)) {
1216                                 /*
1217                                  * Multi-Packet WQE consumes at most two WQE.
1218                                  * mlx5_mpw_new() expects to be able to use
1219                                  * such resources.
1220                                  */
1221                                 if (unlikely(max_wqe < 2))
1222                                         break;
1223                                 max_wqe -= 2;
1224                                 mlx5_mpw_new(txq, &mpw, length);
1225                                 mpw.wqe->eseg.cs_flags = cs_flags;
1226                         } else {
1227                                 if (unlikely(max_wqe < wqe_inl_n))
1228                                         break;
1229                                 max_wqe -= wqe_inl_n;
1230                                 mlx5_mpw_inline_new(txq, &mpw, length);
1231                                 mpw.wqe->eseg.cs_flags = cs_flags;
1232                         }
1233                 }
1234                 /* Multi-segment packets must be alone in their MPW. */
1235                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1236                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1237                         assert(inline_room ==
1238                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1239 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1240                         length = 0;
1241 #endif
1242                         do {
1243                                 volatile struct mlx5_wqe_data_seg *dseg;
1244
1245                                 assert(buf);
1246                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1247                                 dseg = mpw.data.dseg[mpw.pkts_n];
1248                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1249                                 *dseg = (struct mlx5_wqe_data_seg){
1250                                         .byte_count =
1251                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1252                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1253                                         .addr = rte_cpu_to_be_64(addr),
1254                                 };
1255 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1256                                 length += DATA_LEN(buf);
1257 #endif
1258                                 buf = buf->next;
1259                                 ++mpw.pkts_n;
1260                                 ++j;
1261                         } while (--segs_n);
1262                         assert(length == mpw.len);
1263                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1264                                 mlx5_mpw_close(txq, &mpw);
1265                 } else {
1266                         unsigned int max;
1267
1268                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1269                         assert(length <= inline_room);
1270                         assert(length == DATA_LEN(buf));
1271                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1272                         (*txq->elts)[elts_head++ & elts_m] = buf;
1273                         /* Maximum number of bytes before wrapping. */
1274                         max = ((((uintptr_t)(txq->wqes)) +
1275                                 (1 << txq->wqe_n) *
1276                                 MLX5_WQE_SIZE) -
1277                                (uintptr_t)mpw.data.raw);
1278                         if (length > max) {
1279                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1280                                            (void *)addr,
1281                                            max);
1282                                 mpw.data.raw = (volatile void *)txq->wqes;
1283                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1284                                            (void *)(addr + max),
1285                                            length - max);
1286                                 mpw.data.raw += length - max;
1287                         } else {
1288                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1289                                            (void *)addr,
1290                                            length);
1291
1292                                 if (length == max)
1293                                         mpw.data.raw =
1294                                                 (volatile void *)txq->wqes;
1295                                 else
1296                                         mpw.data.raw += length;
1297                         }
1298                         ++mpw.pkts_n;
1299                         mpw.total_len += length;
1300                         ++j;
1301                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1302                                 mlx5_mpw_inline_close(txq, &mpw);
1303                                 inline_room =
1304                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1305                         } else {
1306                                 inline_room -= length;
1307                         }
1308                 }
1309 #ifdef MLX5_PMD_SOFT_COUNTERS
1310                 /* Increment sent bytes counter. */
1311                 txq->stats.obytes += length;
1312 #endif
1313                 ++i;
1314         } while (pkts_n);
1315         /* Take a shortcut if nothing must be sent. */
1316         if (unlikely(i == 0))
1317                 return 0;
1318         /* Check whether completion threshold has been reached. */
1319         /* "j" includes both packets and segments. */
1320         comp = txq->elts_comp + j;
1321         if (comp >= MLX5_TX_COMP_THRESH) {
1322                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1323
1324                 /* Request completion on last WQE. */
1325                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1326                 /* Save elts_head in unused "immediate" field of WQE. */
1327                 wqe->ctrl[3] = elts_head;
1328                 txq->elts_comp = 0;
1329 #ifndef NDEBUG
1330                 ++txq->cq_pi;
1331 #endif
1332         } else {
1333                 txq->elts_comp = comp;
1334         }
1335 #ifdef MLX5_PMD_SOFT_COUNTERS
1336         /* Increment sent packets counter. */
1337         txq->stats.opackets += i;
1338 #endif
1339         /* Ring QP doorbell. */
1340         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1341                 mlx5_mpw_inline_close(txq, &mpw);
1342         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1343                 mlx5_mpw_close(txq, &mpw);
1344         mlx5_tx_dbrec(txq, mpw.wqe);
1345         txq->elts_head = elts_head;
1346         return i;
1347 }
1348
1349 /**
1350  * Open an Enhanced MPW session.
1351  *
1352  * @param txq
1353  *   Pointer to TX queue structure.
1354  * @param mpw
1355  *   Pointer to MPW session structure.
1356  * @param length
1357  *   Packet length.
1358  */
1359 static inline void
1360 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1361 {
1362         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1363
1364         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1365         mpw->pkts_n = 0;
1366         mpw->total_len = sizeof(struct mlx5_wqe);
1367         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1368         mpw->wqe->ctrl[0] =
1369                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1370                                  (txq->wqe_ci << 8) |
1371                                  MLX5_OPCODE_ENHANCED_MPSW);
1372         mpw->wqe->ctrl[2] = 0;
1373         mpw->wqe->ctrl[3] = 0;
1374         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1375         if (unlikely(padding)) {
1376                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1377
1378                 /* Pad the first 2 DWORDs with zero-length inline header. */
1379                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1380                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1381                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1382                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1383                 /* Start from the next WQEBB. */
1384                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1385         } else {
1386                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1387         }
1388 }
1389
1390 /**
1391  * Close an Enhanced MPW session.
1392  *
1393  * @param txq
1394  *   Pointer to TX queue structure.
1395  * @param mpw
1396  *   Pointer to MPW session structure.
1397  *
1398  * @return
1399  *   Number of consumed WQEs.
1400  */
1401 static inline uint16_t
1402 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1403 {
1404         uint16_t ret;
1405
1406         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1407          * count as 2.
1408          */
1409         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1410                                              MLX5_WQE_DS(mpw->total_len));
1411         mpw->state = MLX5_MPW_STATE_CLOSED;
1412         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1413         txq->wqe_ci += ret;
1414         return ret;
1415 }
1416
1417 /**
1418  * TX with Enhanced MPW support.
1419  *
1420  * @param txq
1421  *   Pointer to TX queue structure.
1422  * @param[in] pkts
1423  *   Packets to transmit.
1424  * @param pkts_n
1425  *   Number of packets in array.
1426  *
1427  * @return
1428  *   Number of packets successfully transmitted (<= pkts_n).
1429  */
1430 static inline uint16_t
1431 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1432                uint16_t pkts_n)
1433 {
1434         uint16_t elts_head = txq->elts_head;
1435         const uint16_t elts_n = 1 << txq->elts_n;
1436         const uint16_t elts_m = elts_n - 1;
1437         unsigned int i = 0;
1438         unsigned int j = 0;
1439         uint16_t max_elts;
1440         uint16_t max_wqe;
1441         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1442         unsigned int mpw_room = 0;
1443         unsigned int inl_pad = 0;
1444         uint32_t inl_hdr;
1445         struct mlx5_mpw mpw = {
1446                 .state = MLX5_MPW_STATE_CLOSED,
1447         };
1448
1449         if (unlikely(!pkts_n))
1450                 return 0;
1451         /* Start processing. */
1452         mlx5_tx_complete(txq);
1453         max_elts = (elts_n - (elts_head - txq->elts_tail));
1454         /* A CQE slot must always be available. */
1455         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1456         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1457         if (unlikely(!max_wqe))
1458                 return 0;
1459         do {
1460                 struct rte_mbuf *buf = *(pkts++);
1461                 uintptr_t addr;
1462                 unsigned int do_inline = 0; /* Whether inline is possible. */
1463                 uint32_t length;
1464                 uint8_t cs_flags;
1465
1466                 /* Multi-segmented packet is handled in slow-path outside. */
1467                 assert(NB_SEGS(buf) == 1);
1468                 /* Make sure there is enough room to store this packet. */
1469                 if (max_elts - j == 0)
1470                         break;
1471                 cs_flags = txq_ol_cksum_to_cs(buf);
1472                 /* Retrieve packet information. */
1473                 length = PKT_LEN(buf);
1474                 /* Start new session if:
1475                  * - multi-segment packet
1476                  * - no space left even for a dseg
1477                  * - next packet can be inlined with a new WQE
1478                  * - cs_flag differs
1479                  */
1480                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1481                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1482                              mpw_room) ||
1483                             (length <= txq->inline_max_packet_sz &&
1484                              inl_pad + sizeof(inl_hdr) + length >
1485                              mpw_room) ||
1486                             (mpw.wqe->eseg.cs_flags != cs_flags))
1487                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1488                 }
1489                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1490                         /* In Enhanced MPW, inline as much as the budget is
1491                          * allowed. The remaining space is to be filled with
1492                          * dsegs. If the title WQEBB isn't padded, it will have
1493                          * 2 dsegs there.
1494                          */
1495                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1496                                            (max_inline ? max_inline :
1497                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1498                                            MLX5_WQE_SIZE);
1499                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1500                                 break;
1501                         /* Don't pad the title WQEBB to not waste WQ. */
1502                         mlx5_empw_new(txq, &mpw, 0);
1503                         mpw_room -= mpw.total_len;
1504                         inl_pad = 0;
1505                         do_inline = length <= txq->inline_max_packet_sz &&
1506                                     sizeof(inl_hdr) + length <= mpw_room &&
1507                                     !txq->mpw_hdr_dseg;
1508                         mpw.wqe->eseg.cs_flags = cs_flags;
1509                 } else {
1510                         /* Evaluate whether the next packet can be inlined.
1511                          * Inlininig is possible when:
1512                          * - length is less than configured value
1513                          * - length fits for remaining space
1514                          * - not required to fill the title WQEBB with dsegs
1515                          */
1516                         do_inline =
1517                                 length <= txq->inline_max_packet_sz &&
1518                                 inl_pad + sizeof(inl_hdr) + length <=
1519                                  mpw_room &&
1520                                 (!txq->mpw_hdr_dseg ||
1521                                  mpw.total_len >= MLX5_WQE_SIZE);
1522                 }
1523                 if (max_inline && do_inline) {
1524                         /* Inline packet into WQE. */
1525                         unsigned int max;
1526
1527                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1528                         assert(length == DATA_LEN(buf));
1529                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1530                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1531                         mpw.data.raw = (volatile void *)
1532                                 ((uintptr_t)mpw.data.raw + inl_pad);
1533                         max = tx_mlx5_wq_tailroom(txq,
1534                                         (void *)(uintptr_t)mpw.data.raw);
1535                         /* Copy inline header. */
1536                         mpw.data.raw = (volatile void *)
1537                                 mlx5_copy_to_wq(
1538                                           (void *)(uintptr_t)mpw.data.raw,
1539                                           &inl_hdr,
1540                                           sizeof(inl_hdr),
1541                                           (void *)(uintptr_t)txq->wqes,
1542                                           max);
1543                         max = tx_mlx5_wq_tailroom(txq,
1544                                         (void *)(uintptr_t)mpw.data.raw);
1545                         /* Copy packet data. */
1546                         mpw.data.raw = (volatile void *)
1547                                 mlx5_copy_to_wq(
1548                                           (void *)(uintptr_t)mpw.data.raw,
1549                                           (void *)addr,
1550                                           length,
1551                                           (void *)(uintptr_t)txq->wqes,
1552                                           max);
1553                         ++mpw.pkts_n;
1554                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1555                         /* No need to get completion as the entire packet is
1556                          * copied to WQ. Free the buf right away.
1557                          */
1558                         rte_pktmbuf_free_seg(buf);
1559                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1560                         /* Add pad in the next packet if any. */
1561                         inl_pad = (((uintptr_t)mpw.data.raw +
1562                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1563                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1564                                   (uintptr_t)mpw.data.raw;
1565                 } else {
1566                         /* No inline. Load a dseg of packet pointer. */
1567                         volatile rte_v128u32_t *dseg;
1568
1569                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1570                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1571                         assert(length == DATA_LEN(buf));
1572                         if (!tx_mlx5_wq_tailroom(txq,
1573                                         (void *)((uintptr_t)mpw.data.raw
1574                                                 + inl_pad)))
1575                                 dseg = (volatile void *)txq->wqes;
1576                         else
1577                                 dseg = (volatile void *)
1578                                         ((uintptr_t)mpw.data.raw +
1579                                          inl_pad);
1580                         (*txq->elts)[elts_head++ & elts_m] = buf;
1581                         addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1582                                                                  uintptr_t));
1583                         *dseg = (rte_v128u32_t) {
1584                                 rte_cpu_to_be_32(length),
1585                                 mlx5_tx_mb2mr(txq, buf),
1586                                 addr,
1587                                 addr >> 32,
1588                         };
1589                         mpw.data.raw = (volatile void *)(dseg + 1);
1590                         mpw.total_len += (inl_pad + sizeof(*dseg));
1591                         ++j;
1592                         ++mpw.pkts_n;
1593                         mpw_room -= (inl_pad + sizeof(*dseg));
1594                         inl_pad = 0;
1595                 }
1596 #ifdef MLX5_PMD_SOFT_COUNTERS
1597                 /* Increment sent bytes counter. */
1598                 txq->stats.obytes += length;
1599 #endif
1600                 ++i;
1601         } while (i < pkts_n);
1602         /* Take a shortcut if nothing must be sent. */
1603         if (unlikely(i == 0))
1604                 return 0;
1605         /* Check whether completion threshold has been reached. */
1606         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1607                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1608                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1609                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1610
1611                 /* Request completion on last WQE. */
1612                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1613                 /* Save elts_head in unused "immediate" field of WQE. */
1614                 wqe->ctrl[3] = elts_head;
1615                 txq->elts_comp = 0;
1616                 txq->mpw_comp = txq->wqe_ci;
1617 #ifndef NDEBUG
1618                 ++txq->cq_pi;
1619 #endif
1620         } else {
1621                 txq->elts_comp += j;
1622         }
1623 #ifdef MLX5_PMD_SOFT_COUNTERS
1624         /* Increment sent packets counter. */
1625         txq->stats.opackets += i;
1626 #endif
1627         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1628                 mlx5_empw_close(txq, &mpw);
1629         /* Ring QP doorbell. */
1630         mlx5_tx_dbrec(txq, mpw.wqe);
1631         txq->elts_head = elts_head;
1632         return i;
1633 }
1634
1635 /**
1636  * DPDK callback for TX with Enhanced MPW support.
1637  *
1638  * @param dpdk_txq
1639  *   Generic pointer to TX queue structure.
1640  * @param[in] pkts
1641  *   Packets to transmit.
1642  * @param pkts_n
1643  *   Number of packets in array.
1644  *
1645  * @return
1646  *   Number of packets successfully transmitted (<= pkts_n).
1647  */
1648 uint16_t
1649 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1650 {
1651         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1652         uint16_t nb_tx = 0;
1653
1654         while (pkts_n > nb_tx) {
1655                 uint16_t n;
1656                 uint16_t ret;
1657
1658                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1659                 if (n) {
1660                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1661                         if (!ret)
1662                                 break;
1663                         nb_tx += ret;
1664                 }
1665                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1666                 if (n) {
1667                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1668                         if (!ret)
1669                                 break;
1670                         nb_tx += ret;
1671                 }
1672         }
1673         return nb_tx;
1674 }
1675
1676 /**
1677  * Translate RX completion flags to packet type.
1678  *
1679  * @param[in] rxq
1680  *   Pointer to RX queue structure.
1681  * @param[in] cqe
1682  *   Pointer to CQE.
1683  *
1684  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1685  *
1686  * @return
1687  *   Packet type for struct rte_mbuf.
1688  */
1689 static inline uint32_t
1690 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1691 {
1692         uint8_t idx;
1693         uint8_t pinfo = cqe->pkt_info;
1694         uint16_t ptype = cqe->hdr_type_etc;
1695
1696         /*
1697          * The index to the array should have:
1698          * bit[1:0] = l3_hdr_type
1699          * bit[4:2] = l4_hdr_type
1700          * bit[5] = ip_frag
1701          * bit[6] = tunneled
1702          * bit[7] = outer_l3_type
1703          */
1704         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1705         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1706 }
1707
1708 /**
1709  * Get size of the next packet for a given CQE. For compressed CQEs, the
1710  * consumer index is updated only once all packets of the current one have
1711  * been processed.
1712  *
1713  * @param rxq
1714  *   Pointer to RX queue.
1715  * @param cqe
1716  *   CQE to process.
1717  * @param[out] rss_hash
1718  *   Packet RSS Hash result.
1719  *
1720  * @return
1721  *   Packet size in bytes (0 if there is none), -1 in case of completion
1722  *   with error.
1723  */
1724 static inline int
1725 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1726                  uint16_t cqe_cnt, uint32_t *rss_hash)
1727 {
1728         struct rxq_zip *zip = &rxq->zip;
1729         uint16_t cqe_n = cqe_cnt + 1;
1730         int len = 0;
1731         uint16_t idx, end;
1732
1733         /* Process compressed data in the CQE and mini arrays. */
1734         if (zip->ai) {
1735                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1736                         (volatile struct mlx5_mini_cqe8 (*)[8])
1737                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1738
1739                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1740                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1741                 if ((++zip->ai & 7) == 0) {
1742                         /* Invalidate consumed CQEs */
1743                         idx = zip->ca;
1744                         end = zip->na;
1745                         while (idx != end) {
1746                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1747                                         MLX5_CQE_INVALIDATE;
1748                                 ++idx;
1749                         }
1750                         /*
1751                          * Increment consumer index to skip the number of
1752                          * CQEs consumed. Hardware leaves holes in the CQ
1753                          * ring for software use.
1754                          */
1755                         zip->ca = zip->na;
1756                         zip->na += 8;
1757                 }
1758                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1759                         /* Invalidate the rest */
1760                         idx = zip->ca;
1761                         end = zip->cq_ci;
1762
1763                         while (idx != end) {
1764                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1765                                         MLX5_CQE_INVALIDATE;
1766                                 ++idx;
1767                         }
1768                         rxq->cq_ci = zip->cq_ci;
1769                         zip->ai = 0;
1770                 }
1771         /* No compressed data, get next CQE and verify if it is compressed. */
1772         } else {
1773                 int ret;
1774                 int8_t op_own;
1775
1776                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1777                 if (unlikely(ret == 1))
1778                         return 0;
1779                 ++rxq->cq_ci;
1780                 op_own = cqe->op_own;
1781                 rte_cio_rmb();
1782                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1783                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1784                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1785                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1786                                                           cqe_cnt].pkt_info);
1787
1788                         /* Fix endianness. */
1789                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1790                         /*
1791                          * Current mini array position is the one returned by
1792                          * check_cqe64().
1793                          *
1794                          * If completion comprises several mini arrays, as a
1795                          * special case the second one is located 7 CQEs after
1796                          * the initial CQE instead of 8 for subsequent ones.
1797                          */
1798                         zip->ca = rxq->cq_ci;
1799                         zip->na = zip->ca + 7;
1800                         /* Compute the next non compressed CQE. */
1801                         --rxq->cq_ci;
1802                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1803                         /* Get packet size to return. */
1804                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1805                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1806                         zip->ai = 1;
1807                         /* Prefetch all the entries to be invalidated */
1808                         idx = zip->ca;
1809                         end = zip->cq_ci;
1810                         while (idx != end) {
1811                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1812                                 ++idx;
1813                         }
1814                 } else {
1815                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1816                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1817                 }
1818                 /* Error while receiving packet. */
1819                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1820                         return -1;
1821         }
1822         return len;
1823 }
1824
1825 /**
1826  * Translate RX completion flags to offload flags.
1827  *
1828  * @param[in] cqe
1829  *   Pointer to CQE.
1830  *
1831  * @return
1832  *   Offload flags (ol_flags) for struct rte_mbuf.
1833  */
1834 static inline uint32_t
1835 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1836 {
1837         uint32_t ol_flags = 0;
1838         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1839
1840         ol_flags =
1841                 TRANSPOSE(flags,
1842                           MLX5_CQE_RX_L3_HDR_VALID,
1843                           PKT_RX_IP_CKSUM_GOOD) |
1844                 TRANSPOSE(flags,
1845                           MLX5_CQE_RX_L4_HDR_VALID,
1846                           PKT_RX_L4_CKSUM_GOOD);
1847         return ol_flags;
1848 }
1849
1850 /**
1851  * Fill in mbuf fields from RX completion flags.
1852  * Note that pkt->ol_flags should be initialized outside of this function.
1853  *
1854  * @param rxq
1855  *   Pointer to RX queue.
1856  * @param pkt
1857  *   mbuf to fill.
1858  * @param cqe
1859  *   CQE to process.
1860  * @param rss_hash_res
1861  *   Packet RSS Hash result.
1862  */
1863 static inline void
1864 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1865                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1866 {
1867         /* Update packet information. */
1868         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1869         if (rss_hash_res && rxq->rss_hash) {
1870                 pkt->hash.rss = rss_hash_res;
1871                 pkt->ol_flags |= PKT_RX_RSS_HASH;
1872         }
1873         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1874                 pkt->ol_flags |= PKT_RX_FDIR;
1875                 if (cqe->sop_drop_qpn !=
1876                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1877                         uint32_t mark = cqe->sop_drop_qpn;
1878
1879                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1880                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1881                 }
1882         }
1883         if (rxq->csum)
1884                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1885         if (rxq->vlan_strip &&
1886             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1887                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1888                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1889         }
1890         if (rxq->hw_timestamp) {
1891                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1892                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1893         }
1894 }
1895
1896 /**
1897  * DPDK callback for RX.
1898  *
1899  * @param dpdk_rxq
1900  *   Generic pointer to RX queue structure.
1901  * @param[out] pkts
1902  *   Array to store received packets.
1903  * @param pkts_n
1904  *   Maximum number of packets in array.
1905  *
1906  * @return
1907  *   Number of packets successfully received (<= pkts_n).
1908  */
1909 uint16_t
1910 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1911 {
1912         struct mlx5_rxq_data *rxq = dpdk_rxq;
1913         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1914         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1915         const unsigned int sges_n = rxq->sges_n;
1916         struct rte_mbuf *pkt = NULL;
1917         struct rte_mbuf *seg = NULL;
1918         volatile struct mlx5_cqe *cqe =
1919                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1920         unsigned int i = 0;
1921         unsigned int rq_ci = rxq->rq_ci << sges_n;
1922         int len = 0; /* keep its value across iterations. */
1923
1924         while (pkts_n) {
1925                 unsigned int idx = rq_ci & wqe_cnt;
1926                 volatile struct mlx5_wqe_data_seg *wqe =
1927                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1928                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1929                 uint32_t rss_hash_res = 0;
1930
1931                 if (pkt)
1932                         NEXT(seg) = rep;
1933                 seg = rep;
1934                 rte_prefetch0(seg);
1935                 rte_prefetch0(cqe);
1936                 rte_prefetch0(wqe);
1937                 rep = rte_mbuf_raw_alloc(rxq->mp);
1938                 if (unlikely(rep == NULL)) {
1939                         ++rxq->stats.rx_nombuf;
1940                         if (!pkt) {
1941                                 /*
1942                                  * no buffers before we even started,
1943                                  * bail out silently.
1944                                  */
1945                                 break;
1946                         }
1947                         while (pkt != seg) {
1948                                 assert(pkt != (*rxq->elts)[idx]);
1949                                 rep = NEXT(pkt);
1950                                 NEXT(pkt) = NULL;
1951                                 NB_SEGS(pkt) = 1;
1952                                 rte_mbuf_raw_free(pkt);
1953                                 pkt = rep;
1954                         }
1955                         break;
1956                 }
1957                 if (!pkt) {
1958                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1959                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1960                                                &rss_hash_res);
1961                         if (!len) {
1962                                 rte_mbuf_raw_free(rep);
1963                                 break;
1964                         }
1965                         if (unlikely(len == -1)) {
1966                                 /* RX error, packet is likely too large. */
1967                                 rte_mbuf_raw_free(rep);
1968                                 ++rxq->stats.idropped;
1969                                 goto skip;
1970                         }
1971                         pkt = seg;
1972                         assert(len >= (rxq->crc_present << 2));
1973                         pkt->ol_flags = 0;
1974                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1975                         if (rxq->crc_present)
1976                                 len -= ETHER_CRC_LEN;
1977                         PKT_LEN(pkt) = len;
1978                 }
1979                 DATA_LEN(rep) = DATA_LEN(seg);
1980                 PKT_LEN(rep) = PKT_LEN(seg);
1981                 SET_DATA_OFF(rep, DATA_OFF(seg));
1982                 PORT(rep) = PORT(seg);
1983                 (*rxq->elts)[idx] = rep;
1984                 /*
1985                  * Fill NIC descriptor with the new buffer.  The lkey and size
1986                  * of the buffers are already known, only the buffer address
1987                  * changes.
1988                  */
1989                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1990                 /* If there's only one MR, no need to replace LKey in WQE. */
1991                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1992                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1993                 if (len > DATA_LEN(seg)) {
1994                         len -= DATA_LEN(seg);
1995                         ++NB_SEGS(pkt);
1996                         ++rq_ci;
1997                         continue;
1998                 }
1999                 DATA_LEN(seg) = len;
2000 #ifdef MLX5_PMD_SOFT_COUNTERS
2001                 /* Increment bytes counter. */
2002                 rxq->stats.ibytes += PKT_LEN(pkt);
2003 #endif
2004                 /* Return packet. */
2005                 *(pkts++) = pkt;
2006                 pkt = NULL;
2007                 --pkts_n;
2008                 ++i;
2009 skip:
2010                 /* Align consumer index to the next stride. */
2011                 rq_ci >>= sges_n;
2012                 ++rq_ci;
2013                 rq_ci <<= sges_n;
2014         }
2015         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2016                 return 0;
2017         /* Update the consumer index. */
2018         rxq->rq_ci = rq_ci >> sges_n;
2019         rte_cio_wmb();
2020         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2021         rte_cio_wmb();
2022         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2023 #ifdef MLX5_PMD_SOFT_COUNTERS
2024         /* Increment packets counter. */
2025         rxq->stats.ipackets += i;
2026 #endif
2027         return i;
2028 }
2029
2030 void
2031 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2032 {
2033         struct mlx5_mprq_buf *buf = opaque;
2034
2035         if (rte_atomic16_read(&buf->refcnt) == 1) {
2036                 rte_mempool_put(buf->mp, buf);
2037         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2038                 rte_atomic16_set(&buf->refcnt, 1);
2039                 rte_mempool_put(buf->mp, buf);
2040         }
2041 }
2042
2043 void
2044 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2045 {
2046         mlx5_mprq_buf_free_cb(NULL, buf);
2047 }
2048
2049 static inline void
2050 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2051 {
2052         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2053         volatile struct mlx5_wqe_data_seg *wqe =
2054                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2055         void *addr;
2056
2057         assert(rep != NULL);
2058         /* Replace MPRQ buf. */
2059         (*rxq->mprq_bufs)[rq_idx] = rep;
2060         /* Replace WQE. */
2061         addr = mlx5_mprq_buf_addr(rep);
2062         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2063         /* If there's only one MR, no need to replace LKey in WQE. */
2064         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2065                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2066         /* Stash a mbuf for next replacement. */
2067         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2068                 rxq->mprq_repl = rep;
2069         else
2070                 rxq->mprq_repl = NULL;
2071 }
2072
2073 /**
2074  * DPDK callback for RX with Multi-Packet RQ support.
2075  *
2076  * @param dpdk_rxq
2077  *   Generic pointer to RX queue structure.
2078  * @param[out] pkts
2079  *   Array to store received packets.
2080  * @param pkts_n
2081  *   Maximum number of packets in array.
2082  *
2083  * @return
2084  *   Number of packets successfully received (<= pkts_n).
2085  */
2086 uint16_t
2087 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2088 {
2089         struct mlx5_rxq_data *rxq = dpdk_rxq;
2090         const unsigned int strd_n = 1 << rxq->strd_num_n;
2091         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2092         const unsigned int strd_shift =
2093                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2094         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2095         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2096         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2097         unsigned int i = 0;
2098         uint16_t rq_ci = rxq->rq_ci;
2099         uint16_t strd_idx = rxq->strd_ci;
2100         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2101
2102         while (i < pkts_n) {
2103                 struct rte_mbuf *pkt;
2104                 void *addr;
2105                 int ret;
2106                 unsigned int len;
2107                 uint16_t consumed_strd;
2108                 uint32_t offset;
2109                 uint32_t byte_cnt;
2110                 uint32_t rss_hash_res = 0;
2111
2112                 if (strd_idx == strd_n) {
2113                         /* Replace WQE only if the buffer is still in use. */
2114                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2115                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2116                                 /* Release the old buffer. */
2117                                 mlx5_mprq_buf_free(buf);
2118                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2119                                 struct mlx5_mprq_buf *rep;
2120
2121                                 /*
2122                                  * Currently, the MPRQ mempool is out of buffer
2123                                  * and doing memcpy regardless of the size of Rx
2124                                  * packet. Retry allocation to get back to
2125                                  * normal.
2126                                  */
2127                                 if (!rte_mempool_get(rxq->mprq_mp,
2128                                                      (void **)&rep))
2129                                         rxq->mprq_repl = rep;
2130                         }
2131                         /* Advance to the next WQE. */
2132                         strd_idx = 0;
2133                         ++rq_ci;
2134                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2135                 }
2136                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2137                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &rss_hash_res);
2138                 if (!ret)
2139                         break;
2140                 if (unlikely(ret == -1)) {
2141                         /* RX error, packet is likely too large. */
2142                         ++rxq->stats.idropped;
2143                         continue;
2144                 }
2145                 byte_cnt = ret;
2146                 consumed_strd = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2147                                 MLX5_MPRQ_STRIDE_NUM_SHIFT;
2148                 assert(consumed_strd);
2149                 /* Calculate offset before adding up stride index. */
2150                 offset = strd_idx * strd_sz + strd_shift;
2151                 strd_idx += consumed_strd;
2152                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2153                         continue;
2154                 /*
2155                  * Currently configured to receive a packet per a stride. But if
2156                  * MTU is adjusted through kernel interface, device could
2157                  * consume multiple strides without raising an error. In this
2158                  * case, the packet should be dropped because it is bigger than
2159                  * the max_rx_pkt_len.
2160                  */
2161                 if (unlikely(consumed_strd > 1)) {
2162                         ++rxq->stats.idropped;
2163                         continue;
2164                 }
2165                 pkt = rte_pktmbuf_alloc(rxq->mp);
2166                 if (unlikely(pkt == NULL)) {
2167                         ++rxq->stats.rx_nombuf;
2168                         break;
2169                 }
2170                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2171                 assert((int)len >= (rxq->crc_present << 2));
2172                 if (rxq->crc_present)
2173                         len -= ETHER_CRC_LEN;
2174                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2175                 /* Initialize the offload flag. */
2176                 pkt->ol_flags = 0;
2177                 /*
2178                  * Memcpy packets to the target mbuf if:
2179                  * - The size of packet is smaller than mprq_max_memcpy_len.
2180                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2181                  */
2182                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2183                         /*
2184                          * When memcpy'ing packet due to out-of-buffer, the
2185                          * packet must be smaller than the target mbuf.
2186                          */
2187                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2188                                 rte_pktmbuf_free_seg(pkt);
2189                                 ++rxq->stats.idropped;
2190                                 continue;
2191                         }
2192                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2193                 } else {
2194                         rte_iova_t buf_iova;
2195                         struct rte_mbuf_ext_shared_info *shinfo;
2196                         uint16_t buf_len = consumed_strd * strd_sz;
2197
2198                         /* Increment the refcnt of the whole chunk. */
2199                         rte_atomic16_add_return(&buf->refcnt, 1);
2200                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2201                                strd_n + 1);
2202                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2203                         /*
2204                          * MLX5 device doesn't use iova but it is necessary in a
2205                          * case where the Rx packet is transmitted via a
2206                          * different PMD.
2207                          */
2208                         buf_iova = rte_mempool_virt2iova(buf) +
2209                                    RTE_PTR_DIFF(addr, buf);
2210                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2211                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2212                         /*
2213                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2214                          * attaching the stride to mbuf and more offload flags
2215                          * will be added below by calling rxq_cq_to_mbuf().
2216                          * Other fields will be overwritten.
2217                          */
2218                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2219                                                   shinfo);
2220                         rte_pktmbuf_reset_headroom(pkt);
2221                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2222                         /*
2223                          * Prevent potential overflow due to MTU change through
2224                          * kernel interface.
2225                          */
2226                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2227                                 rte_pktmbuf_free_seg(pkt);
2228                                 ++rxq->stats.idropped;
2229                                 continue;
2230                         }
2231                 }
2232                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2233                 PKT_LEN(pkt) = len;
2234                 DATA_LEN(pkt) = len;
2235                 PORT(pkt) = rxq->port_id;
2236 #ifdef MLX5_PMD_SOFT_COUNTERS
2237                 /* Increment bytes counter. */
2238                 rxq->stats.ibytes += PKT_LEN(pkt);
2239 #endif
2240                 /* Return packet. */
2241                 *(pkts++) = pkt;
2242                 ++i;
2243         }
2244         /* Update the consumer indexes. */
2245         rxq->strd_ci = strd_idx;
2246         rte_io_wmb();
2247         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2248         if (rq_ci != rxq->rq_ci) {
2249                 rxq->rq_ci = rq_ci;
2250                 rte_io_wmb();
2251                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2252         }
2253 #ifdef MLX5_PMD_SOFT_COUNTERS
2254         /* Increment packets counter. */
2255         rxq->stats.ipackets += i;
2256 #endif
2257         return i;
2258 }
2259
2260 /**
2261  * Dummy DPDK callback for TX.
2262  *
2263  * This function is used to temporarily replace the real callback during
2264  * unsafe control operations on the queue, or in case of error.
2265  *
2266  * @param dpdk_txq
2267  *   Generic pointer to TX queue structure.
2268  * @param[in] pkts
2269  *   Packets to transmit.
2270  * @param pkts_n
2271  *   Number of packets in array.
2272  *
2273  * @return
2274  *   Number of packets successfully transmitted (<= pkts_n).
2275  */
2276 uint16_t
2277 removed_tx_burst(void *dpdk_txq __rte_unused,
2278                  struct rte_mbuf **pkts __rte_unused,
2279                  uint16_t pkts_n __rte_unused)
2280 {
2281         return 0;
2282 }
2283
2284 /**
2285  * Dummy DPDK callback for RX.
2286  *
2287  * This function is used to temporarily replace the real callback during
2288  * unsafe control operations on the queue, or in case of error.
2289  *
2290  * @param dpdk_rxq
2291  *   Generic pointer to RX queue structure.
2292  * @param[out] pkts
2293  *   Array to store received packets.
2294  * @param pkts_n
2295  *   Maximum number of packets in array.
2296  *
2297  * @return
2298  *   Number of packets successfully received (<= pkts_n).
2299  */
2300 uint16_t
2301 removed_rx_burst(void *dpdk_txq __rte_unused,
2302                  struct rte_mbuf **pkts __rte_unused,
2303                  uint16_t pkts_n __rte_unused)
2304 {
2305         return 0;
2306 }
2307
2308 /*
2309  * Vectorized Rx/Tx routines are not compiled in when required vector
2310  * instructions are not supported on a target architecture. The following null
2311  * stubs are needed for linkage when those are not included outside of this file
2312  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2313  */
2314
2315 uint16_t __attribute__((weak))
2316 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2317                       struct rte_mbuf **pkts __rte_unused,
2318                       uint16_t pkts_n __rte_unused)
2319 {
2320         return 0;
2321 }
2322
2323 uint16_t __attribute__((weak))
2324 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2325                   struct rte_mbuf **pkts __rte_unused,
2326                   uint16_t pkts_n __rte_unused)
2327 {
2328         return 0;
2329 }
2330
2331 uint16_t __attribute__((weak))
2332 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2333                   struct rte_mbuf **pkts __rte_unused,
2334                   uint16_t pkts_n __rte_unused)
2335 {
2336         return 0;
2337 }
2338
2339 int __attribute__((weak))
2340 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2341 {
2342         return -ENOTSUP;
2343 }
2344
2345 int __attribute__((weak))
2346 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2347 {
2348         return -ENOTSUP;
2349 }
2350
2351 int __attribute__((weak))
2352 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2353 {
2354         return -ENOTSUP;
2355 }
2356
2357 int __attribute__((weak))
2358 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2359 {
2360         return -ENOTSUP;
2361 }