drivers/net/mlx5/mlx5_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright 2015 6WIND S.A.
   5  *   Copyright 2015 Mellanox.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of 6WIND S.A. nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <assert.h>
  35 #include <stdint.h>
  36 #include <string.h>
  37 #include <stdlib.h>
  38
  39 /* Verbs header. */
  40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  41 #ifdef PEDANTIC
  42 #pragma GCC diagnostic ignored "-Wpedantic"
  43 #endif
  44 #include <infiniband/verbs.h>
  45 #include <infiniband/mlx5_hw.h>
  46 #include <infiniband/arch.h>
  47 #ifdef PEDANTIC
  48 #pragma GCC diagnostic error "-Wpedantic"
  49 #endif
  50
  51 /* DPDK headers don't like -pedantic. */
  52 #ifdef PEDANTIC
  53 #pragma GCC diagnostic ignored "-Wpedantic"
  54 #endif
  55 #include <rte_mbuf.h>
  56 #include <rte_mempool.h>
  57 #include <rte_prefetch.h>
  58 #include <rte_common.h>
  59 #include <rte_branch_prediction.h>
  60 #include <rte_ether.h>
  61 #ifdef PEDANTIC
  62 #pragma GCC diagnostic error "-Wpedantic"
  63 #endif
  64
  65 #include "mlx5.h"
  66 #include "mlx5_utils.h"
  67 #include "mlx5_rxtx.h"
  68 #include "mlx5_autoconf.h"
  69 #include "mlx5_defs.h"
  70 #include "mlx5_prm.h"
  71
  72 static __rte_always_inline int
  73 check_cqe(volatile struct mlx5_cqe *cqe,
  74           unsigned int cqes_n, const uint16_t ci);
  75
  76 static __rte_always_inline void
  77 txq_complete(struct txq *txq);
  78
  79 static __rte_always_inline uint32_t
  80 txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
  81
  82 static __rte_always_inline void
  83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
  84
  85 static __rte_always_inline uint32_t
  86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  87
  88 static __rte_always_inline int
  89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
  90                  uint16_t cqe_cnt, uint32_t *rss_hash);
  91
  92 static __rte_always_inline uint32_t
  93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
  94
  95 #ifndef NDEBUG
  96
  97 /**
  98  * Verify or set magic value in CQE.
  99  *
 100  * @param cqe
 101  *   Pointer to CQE.
 102  *
 103  * @return
 104  *   0 the first time.
 105  */
 106 static inline int
 107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
 108 {
 109         static const uint8_t magic[] = "seen";
 110         volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
 111         int ret = 1;
 112         unsigned int i;
 113
 114         for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
 115                 if (!ret || (*buf)[i] != magic[i]) {
 116                         ret = 0;
 117                         (*buf)[i] = magic[i];
 118                 }
 119         return ret;
 120 }
 121
 122 #endif /* NDEBUG */
 123
 124 /**
 125  * Check whether CQE is valid.
 126  *
 127  * @param cqe
 128  *   Pointer to CQE.
 129  * @param cqes_n
 130  *   Size of completion queue.
 131  * @param ci
 132  *   Consumer index.
 133  *
 134  * @return
 135  *   0 on success, 1 on failure.
 136  */
 137 static inline int
 138 check_cqe(volatile struct mlx5_cqe *cqe,
 139           unsigned int cqes_n, const uint16_t ci)
 140 {
 141         uint16_t idx = ci & cqes_n;
 142         uint8_t op_own = cqe->op_own;
 143         uint8_t op_owner = MLX5_CQE_OWNER(op_own);
 144         uint8_t op_code = MLX5_CQE_OPCODE(op_own);
 145
 146         if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
 147                 return 1; /* No CQE. */
 148 #ifndef NDEBUG
 149         if ((op_code == MLX5_CQE_RESP_ERR) ||
 150             (op_code == MLX5_CQE_REQ_ERR)) {
 151                 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
 152                 uint8_t syndrome = err_cqe->syndrome;
 153
 154                 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
 155                     (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
 156                         return 0;
 157                 if (!check_cqe_seen(cqe))
 158                         ERROR("unexpected CQE error %u (0x%02x)"
 159                               " syndrome 0x%02x",
 160                               op_code, op_code, syndrome);
 161                 return 1;
 162         } else if ((op_code != MLX5_CQE_RESP_SEND) &&
 163                    (op_code != MLX5_CQE_REQ)) {
 164                 if (!check_cqe_seen(cqe))
 165                         ERROR("unexpected CQE opcode %u (0x%02x)",
 166                               op_code, op_code);
 167                 return 1;
 168         }
 169 #endif /* NDEBUG */
 170         return 0;
 171 }
 172
 173 /**
 174  * Return the address of the WQE.
 175  *
 176  * @param txq
 177  *   Pointer to TX queue structure.
 178  * @param  wqe_ci
 179  *   WQE consumer index.
 180  *
 181  * @return
 182  *   WQE address.
 183  */
 184 static inline uintptr_t *
 185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
 186 {
 187         ci &= ((1 << txq->wqe_n) - 1);
 188         return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
 189 }
 190
 191 /**
 192  * Return the size of tailroom of WQ.
 193  *
 194  * @param txq
 195  *   Pointer to TX queue structure.
 196  * @param addr
 197  *   Pointer to tail of WQ.
 198  *
 199  * @return
 200  *   Size of tailroom.
 201  */
 202 static inline size_t
 203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
 204 {
 205         size_t tailroom;
 206         tailroom = (uintptr_t)(txq->wqes) +
 207                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 208                    (uintptr_t)addr;
 209         return tailroom;
 210 }
 211
 212 /**
 213  * Copy data to tailroom of circular queue.
 214  *
 215  * @param dst
 216  *   Pointer to destination.
 217  * @param src
 218  *   Pointer to source.
 219  * @param n
 220  *   Number of bytes to copy.
 221  * @param base
 222  *   Pointer to head of queue.
 223  * @param tailroom
 224  *   Size of tailroom from dst.
 225  *
 226  * @return
 227  *   Pointer after copied data.
 228  */
 229 static inline void *
 230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 231                 void *base, size_t tailroom)
 232 {
 233         void *ret;
 234
 235         if (n > tailroom) {
 236                 rte_memcpy(dst, src, tailroom);
 237                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 238                            n - tailroom);
 239                 ret = (uint8_t *)base + n - tailroom;
 240         } else {
 241                 rte_memcpy(dst, src, n);
 242                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 243         }
 244         return ret;
 245 }
 246
 247 /**
 248  * Manage TX completions.
 249  *
 250  * When sending a burst, mlx5_tx_burst() posts several WRs.
 251  *
 252  * @param txq
 253  *   Pointer to TX queue structure.
 254  */
 255 static inline void
 256 txq_complete(struct txq *txq)
 257 {
 258         const uint16_t elts_n = 1 << txq->elts_n;
 259         const uint16_t elts_m = elts_n - 1;
 260         const unsigned int cqe_n = 1 << txq->cqe_n;
 261         const unsigned int cqe_cnt = cqe_n - 1;
 262         uint16_t elts_free = txq->elts_tail;
 263         uint16_t elts_tail;
 264         uint16_t cq_ci = txq->cq_ci;
 265         volatile struct mlx5_cqe *cqe = NULL;
 266         volatile struct mlx5_wqe_ctrl *ctrl;
 267         struct rte_mbuf *m, *free[elts_n];
 268         struct rte_mempool *pool = NULL;
 269         unsigned int blk_n = 0;
 270
 271         do {
 272                 volatile struct mlx5_cqe *tmp;
 273
 274                 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
 275                 if (check_cqe(tmp, cqe_n, cq_ci))
 276                         break;
 277                 cqe = tmp;
 278 #ifndef NDEBUG
 279                 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
 280                         if (!check_cqe_seen(cqe))
 281                                 ERROR("unexpected compressed CQE, TX stopped");
 282                         return;
 283                 }
 284                 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
 285                     (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
 286                         if (!check_cqe_seen(cqe))
 287                                 ERROR("unexpected error CQE, TX stopped");
 288                         return;
 289                 }
 290 #endif /* NDEBUG */
 291                 ++cq_ci;
 292         } while (1);
 293         if (unlikely(cqe == NULL))
 294                 return;
 295         txq->wqe_pi = ntohs(cqe->wqe_counter);
 296         ctrl = (volatile struct mlx5_wqe_ctrl *)
 297                 tx_mlx5_wqe(txq, txq->wqe_pi);
 298         elts_tail = ctrl->ctrl3;
 299         assert((elts_tail & elts_m) < (1 << txq->wqe_n));
 300         /* Free buffers. */
 301         while (elts_free != elts_tail) {
 302                 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
 303                 if (likely(m != NULL)) {
 304                         if (likely(m->pool == pool)) {
 305                                 free[blk_n++] = m;
 306                         } else {
 307                                 if (likely(pool != NULL))
 308                                         rte_mempool_put_bulk(pool,
 309                                                              (void *)free,
 310                                                              blk_n);
 311                                 free[0] = m;
 312                                 pool = m->pool;
 313                                 blk_n = 1;
 314                         }
 315                 }
 316         }
 317         if (blk_n)
 318                 rte_mempool_put_bulk(pool, (void *)free, blk_n);
 319 #ifndef NDEBUG
 320         elts_free = txq->elts_tail;
 321         /* Poisoning. */
 322         while (elts_free != elts_tail) {
 323                 memset(&(*txq->elts)[elts_free & elts_m],
 324                        0x66,
 325                        sizeof((*txq->elts)[elts_free & elts_m]));
 326                 ++elts_free;
 327         }
 328 #endif
 329         txq->cq_ci = cq_ci;
 330         txq->elts_tail = elts_tail;
 331         /* Update the consumer index. */
 332         rte_wmb();
 333         *txq->cq_db = htonl(cq_ci);
 334 }
 335
 336 /**
 337  * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
 338  * the cloned mbuf is allocated is returned instead.
 339  *
 340  * @param buf
 341  *   Pointer to mbuf.
 342  *
 343  * @return
 344  *   Memory pool where data is located for given mbuf.
 345  */
 346 static struct rte_mempool *
 347 txq_mb2mp(struct rte_mbuf *buf)
 348 {
 349         if (unlikely(RTE_MBUF_INDIRECT(buf)))
 350                 return rte_mbuf_from_indirect(buf)->pool;
 351         return buf->pool;
 352 }
 353
 354 /**
 355  * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
 356  * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
 357  * remove an entry first.
 358  *
 359  * @param txq
 360  *   Pointer to TX queue structure.
 361  * @param[in] mp
 362  *   Memory Pool for which a Memory Region lkey must be returned.
 363  *
 364  * @return
 365  *   mr->lkey on success, (uint32_t)-1 on failure.
 366  */
 367 static inline uint32_t
 368 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
 369 {
 370         unsigned int i;
 371         uint32_t lkey = (uint32_t)-1;
 372
 373         for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
 374                 if (unlikely(txq->mp2mr[i].mp == NULL)) {
 375                         /* Unknown MP, add a new MR for it. */
 376                         break;
 377                 }
 378                 if (txq->mp2mr[i].mp == mp) {
 379                         assert(txq->mp2mr[i].lkey != (uint32_t)-1);
 380                         assert(htonl(txq->mp2mr[i].mr->lkey) ==
 381                                txq->mp2mr[i].lkey);
 382                         lkey = txq->mp2mr[i].lkey;
 383                         break;
 384                 }
 385         }
 386         if (unlikely(lkey == (uint32_t)-1))
 387                 lkey = txq_mp2mr_reg(txq, mp, i);
 388         return lkey;
 389 }
 390
 391 /**
 392  * Ring TX queue doorbell.
 393  *
 394  * @param txq
 395  *   Pointer to TX queue structure.
 396  * @param wqe
 397  *   Pointer to the last WQE posted in the NIC.
 398  */
 399 static inline void
 400 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
 401 {
 402         uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
 403         volatile uint64_t *src = ((volatile uint64_t *)wqe);
 404
 405         rte_wmb();
 406         *txq->qp_db = htonl(txq->wqe_ci);
 407         /* Ensure ordering between DB record and BF copy. */
 408         rte_wmb();
 409         *dst = *src;
 410 }
 411
 412 /**
 413  * DPDK callback to check the status of a tx descriptor.
 414  *
 415  * @param tx_queue
 416  *   The tx queue.
 417  * @param[in] offset
 418  *   The index of the descriptor in the ring.
 419  *
 420  * @return
 421  *   The status of the tx descriptor.
 422  */
 423 int
 424 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 425 {
 426         struct txq *txq = tx_queue;
 427         uint16_t used;
 428
 429         txq_complete(txq);
 430         used = txq->elts_head - txq->elts_tail;
 431         if (offset < used)
 432                 return RTE_ETH_TX_DESC_FULL;
 433         return RTE_ETH_TX_DESC_DONE;
 434 }
 435
 436 /**
 437  * DPDK callback to check the status of a rx descriptor.
 438  *
 439  * @param rx_queue
 440  *   The rx queue.
 441  * @param[in] offset
 442  *   The index of the descriptor in the ring.
 443  *
 444  * @return
 445  *   The status of the tx descriptor.
 446  */
 447 int
 448 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 449 {
 450         struct rxq *rxq = rx_queue;
 451         struct rxq_zip *zip = &rxq->zip;
 452         volatile struct mlx5_cqe *cqe;
 453         const unsigned int cqe_n = (1 << rxq->cqe_n);
 454         const unsigned int cqe_cnt = cqe_n - 1;
 455         unsigned int cq_ci;
 456         unsigned int used;
 457
 458         /* if we are processing a compressed cqe */
 459         if (zip->ai) {
 460                 used = zip->cqe_cnt - zip->ca;
 461                 cq_ci = zip->cq_ci;
 462         } else {
 463                 used = 0;
 464                 cq_ci = rxq->cq_ci;
 465         }
 466         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 467         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 468                 int8_t op_own;
 469                 unsigned int n;
 470
 471                 op_own = cqe->op_own;
 472                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 473                         n = ntohl(cqe->byte_cnt);
 474                 else
 475                         n = 1;
 476                 cq_ci += n;
 477                 used += n;
 478                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 479         }
 480         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 481         if (offset < used)
 482                 return RTE_ETH_RX_DESC_DONE;
 483         return RTE_ETH_RX_DESC_AVAIL;
 484 }
 485
 486 /**
 487  * DPDK callback for TX.
 488  *
 489  * @param dpdk_txq
 490  *   Generic pointer to TX queue structure.
 491  * @param[in] pkts
 492  *   Packets to transmit.
 493  * @param pkts_n
 494  *   Number of packets in array.
 495  *
 496  * @return
 497  *   Number of packets successfully transmitted (<= pkts_n).
 498  */
 499 uint16_t
 500 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 501 {
 502         struct txq *txq = (struct txq *)dpdk_txq;
 503         uint16_t elts_head = txq->elts_head;
 504         const uint16_t elts_n = 1 << txq->elts_n;
 505         const uint16_t elts_m = elts_n - 1;
 506         unsigned int i = 0;
 507         unsigned int j = 0;
 508         unsigned int k = 0;
 509         uint16_t max_elts;
 510         unsigned int max_inline = txq->max_inline;
 511         const unsigned int inline_en = !!max_inline && txq->inline_en;
 512         uint16_t max_wqe;
 513         unsigned int comp;
 514         volatile struct mlx5_wqe_v *wqe = NULL;
 515         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 516         unsigned int segs_n = 0;
 517         struct rte_mbuf *buf = NULL;
 518         uint8_t *raw;
 519
 520         if (unlikely(!pkts_n))
 521                 return 0;
 522         /* Prefetch first packet cacheline. */
 523         rte_prefetch0(*pkts);
 524         /* Start processing. */
 525         txq_complete(txq);
 526         max_elts = (elts_n - (elts_head - txq->elts_tail));
 527         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 528         if (unlikely(!max_wqe))
 529                 return 0;
 530         do {
 531                 volatile rte_v128u32_t *dseg = NULL;
 532                 uint32_t length;
 533                 unsigned int ds = 0;
 534                 unsigned int sg = 0; /* counter of additional segs attached. */
 535                 uintptr_t addr;
 536                 uint64_t naddr;
 537                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 538                 uint16_t tso_header_sz = 0;
 539                 uint16_t ehdr;
 540                 uint8_t cs_flags = 0;
 541                 uint64_t tso = 0;
 542                 uint16_t tso_segsz = 0;
 543 #ifdef MLX5_PMD_SOFT_COUNTERS
 544                 uint32_t total_length = 0;
 545 #endif
 546
 547                 /* first_seg */
 548                 buf = *pkts;
 549                 segs_n = buf->nb_segs;
 550                 /*
 551                  * Make sure there is enough room to store this packet and
 552                  * that one ring entry remains unused.
 553                  */
 554                 assert(segs_n);
 555                 if (max_elts < segs_n)
 556                         break;
 557                 max_elts -= segs_n;
 558                 --segs_n;
 559                 if (unlikely(--max_wqe == 0))
 560                         break;
 561                 wqe = (volatile struct mlx5_wqe_v *)
 562                         tx_mlx5_wqe(txq, txq->wqe_ci);
 563                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 564                 if (pkts_n - i > 1)
 565                         rte_prefetch0(*(pkts + 1));
 566                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 567                 length = DATA_LEN(buf);
 568                 ehdr = (((uint8_t *)addr)[1] << 8) |
 569                        ((uint8_t *)addr)[0];
 570 #ifdef MLX5_PMD_SOFT_COUNTERS
 571                 total_length = length;
 572 #endif
 573                 if (length < (MLX5_WQE_DWORD_SIZE + 2))
 574                         break;
 575                 /* Update element. */
 576                 (*txq->elts)[elts_head & elts_m] = buf;
 577                 /* Prefetch next buffer data. */
 578                 if (pkts_n - i > 1)
 579                         rte_prefetch0(
 580                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 581                 /* Should we enable HW CKSUM offload */
 582                 if (buf->ol_flags &
 583                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
 584                         const uint64_t is_tunneled = buf->ol_flags &
 585                                                      (PKT_TX_TUNNEL_GRE |
 586                                                       PKT_TX_TUNNEL_VXLAN);
 587
 588                         if (is_tunneled && txq->tunnel_en) {
 589                                 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
 590                                            MLX5_ETH_WQE_L4_INNER_CSUM;
 591                                 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
 592                                         cs_flags |= MLX5_ETH_WQE_L3_CSUM;
 593                         } else {
 594                                 cs_flags = MLX5_ETH_WQE_L3_CSUM |
 595                                            MLX5_ETH_WQE_L4_CSUM;
 596                         }
 597                 }
 598                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 599                 /* Replace the Ethernet type by the VLAN if necessary. */
 600                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 601                         uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
 602                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 603
 604                         addr += 2;
 605                         length -= 2;
 606                         /* Copy Destination and source mac address. */
 607                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 608                         /* Copy VLAN. */
 609                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 610                         /* Copy missing two bytes to end the DSeg. */
 611                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 612                                ((uint8_t *)addr) + len, 2);
 613                         addr += len + 2;
 614                         length -= (len + 2);
 615                 } else {
 616                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 617                                MLX5_WQE_DWORD_SIZE);
 618                         length -= pkt_inline_sz;
 619                         addr += pkt_inline_sz;
 620                 }
 621                 if (txq->tso_en) {
 622                         tso = buf->ol_flags & PKT_TX_TCP_SEG;
 623                         if (tso) {
 624                                 uintptr_t end = (uintptr_t)
 625                                                 (((uintptr_t)txq->wqes) +
 626                                                 (1 << txq->wqe_n) *
 627                                                 MLX5_WQE_SIZE);
 628                                 unsigned int copy_b;
 629                                 uint8_t vlan_sz = (buf->ol_flags &
 630                                                   PKT_TX_VLAN_PKT) ? 4 : 0;
 631                                 const uint64_t is_tunneled =
 632                                                         buf->ol_flags &
 633                                                         (PKT_TX_TUNNEL_GRE |
 634                                                          PKT_TX_TUNNEL_VXLAN);
 635
 636                                 tso_header_sz = buf->l2_len + vlan_sz +
 637                                                 buf->l3_len + buf->l4_len;
 638                                 tso_segsz = buf->tso_segsz;
 639
 640                                 if (is_tunneled && txq->tunnel_en) {
 641                                         tso_header_sz += buf->outer_l2_len +
 642                                                          buf->outer_l3_len;
 643                                         cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 644                                 } else {
 645                                         cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 646                                 }
 647                                 if (unlikely(tso_header_sz >
 648                                              MLX5_MAX_TSO_HEADER))
 649                                         break;
 650                                 copy_b = tso_header_sz - pkt_inline_sz;
 651                                 /* First seg must contain all headers. */
 652                                 assert(copy_b <= length);
 653                                 raw += MLX5_WQE_DWORD_SIZE;
 654                                 if (copy_b &&
 655                                    ((end - (uintptr_t)raw) > copy_b)) {
 656                                         uint16_t n = (MLX5_WQE_DS(copy_b) -
 657                                                       1 + 3) / 4;
 658
 659                                         if (unlikely(max_wqe < n))
 660                                                 break;
 661                                         max_wqe -= n;
 662                                         rte_memcpy((void *)raw,
 663                                                    (void *)addr, copy_b);
 664                                         addr += copy_b;
 665                                         length -= copy_b;
 666                                         pkt_inline_sz += copy_b;
 667                                         /*
 668                                          * Another DWORD will be added
 669                                          * in the inline part.
 670                                          */
 671                                         raw += MLX5_WQE_DS(copy_b) *
 672                                                MLX5_WQE_DWORD_SIZE -
 673                                                MLX5_WQE_DWORD_SIZE;
 674                                 } else {
 675                                         /* NOP WQE. */
 676                                         wqe->ctrl = (rte_v128u32_t){
 677                                                      htonl(txq->wqe_ci << 8),
 678                                                      htonl(txq->qp_num_8s | 1),
 679                                                      0,
 680                                                      0,
 681                                         };
 682                                         ds = 1;
 683                                         total_length = 0;
 684                                         k++;
 685                                         goto next_wqe;
 686                                 }
 687                         }
 688                 }
 689                 /* Inline if enough room. */
 690                 if (inline_en || tso) {
 691                         uintptr_t end = (uintptr_t)
 692                                 (((uintptr_t)txq->wqes) +
 693                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 694                         unsigned int inline_room = max_inline *
 695                                                    RTE_CACHE_LINE_SIZE -
 696                                                    (pkt_inline_sz - 2);
 697                         uintptr_t addr_end = (addr + inline_room) &
 698                                              ~(RTE_CACHE_LINE_SIZE - 1);
 699                         unsigned int copy_b = (addr_end > addr) ?
 700                                 RTE_MIN((addr_end - addr), length) :
 701                                 0;
 702
 703                         raw += MLX5_WQE_DWORD_SIZE;
 704                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 705                                 /*
 706                                  * One Dseg remains in the current WQE.  To
 707                                  * keep the computation positive, it is
 708                                  * removed after the bytes to Dseg conversion.
 709                                  */
 710                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 711
 712                                 if (unlikely(max_wqe < n))
 713                                         break;
 714                                 max_wqe -= n;
 715                                 if (tso) {
 716                                         uint32_t inl =
 717                                                 htonl(copy_b | MLX5_INLINE_SEG);
 718
 719                                         pkt_inline_sz =
 720                                                 MLX5_WQE_DS(tso_header_sz) *
 721                                                 MLX5_WQE_DWORD_SIZE;
 722                                         rte_memcpy((void *)raw,
 723                                                    (void *)&inl, sizeof(inl));
 724                                         raw += sizeof(inl);
 725                                         pkt_inline_sz += sizeof(inl);
 726                                 }
 727                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 728                                 addr += copy_b;
 729                                 length -= copy_b;
 730                                 pkt_inline_sz += copy_b;
 731                         }
 732                         /*
 733                          * 2 DWORDs consumed by the WQE header + ETH segment +
 734                          * the size of the inline part of the packet.
 735                          */
 736                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 737                         if (length > 0) {
 738                                 if (ds % (MLX5_WQE_SIZE /
 739                                           MLX5_WQE_DWORD_SIZE) == 0) {
 740                                         if (unlikely(--max_wqe == 0))
 741                                                 break;
 742                                         dseg = (volatile rte_v128u32_t *)
 743                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 744                                                            ds / 4);
 745                                 } else {
 746                                         dseg = (volatile rte_v128u32_t *)
 747                                                 ((uintptr_t)wqe +
 748                                                  (ds * MLX5_WQE_DWORD_SIZE));
 749                                 }
 750                                 goto use_dseg;
 751                         } else if (!segs_n) {
 752                                 goto next_pkt;
 753                         } else {
 754                                 /* dseg will be advance as part of next_seg */
 755                                 dseg = (volatile rte_v128u32_t *)
 756                                         ((uintptr_t)wqe +
 757                                          ((ds - 1) * MLX5_WQE_DWORD_SIZE));
 758                                 goto next_seg;
 759                         }
 760                 } else {
 761                         /*
 762                          * No inline has been done in the packet, only the
 763                          * Ethernet Header as been stored.
 764                          */
 765                         dseg = (volatile rte_v128u32_t *)
 766                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 767                         ds = 3;
 768 use_dseg:
 769                         /* Add the remaining packet as a simple ds. */
 770                         naddr = htonll(addr);
 771                         *dseg = (rte_v128u32_t){
 772                                 htonl(length),
 773                                 txq_mp2mr(txq, txq_mb2mp(buf)),
 774                                 naddr,
 775                                 naddr >> 32,
 776                         };
 777                         ++ds;
 778                         if (!segs_n)
 779                                 goto next_pkt;
 780                 }
 781 next_seg:
 782                 assert(buf);
 783                 assert(ds);
 784                 assert(wqe);
 785                 /*
 786                  * Spill on next WQE when the current one does not have
 787                  * enough room left. Size of WQE must a be a multiple
 788                  * of data segment size.
 789                  */
 790                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 791                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 792                         if (unlikely(--max_wqe == 0))
 793                                 break;
 794                         dseg = (volatile rte_v128u32_t *)
 795                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 796                         rte_prefetch0(tx_mlx5_wqe(txq,
 797                                                   txq->wqe_ci + ds / 4 + 1));
 798                 } else {
 799                         ++dseg;
 800                 }
 801                 ++ds;
 802                 buf = buf->next;
 803                 assert(buf);
 804                 length = DATA_LEN(buf);
 805 #ifdef MLX5_PMD_SOFT_COUNTERS
 806                 total_length += length;
 807 #endif
 808                 /* Store segment information. */
 809                 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
 810                 *dseg = (rte_v128u32_t){
 811                         htonl(length),
 812                         txq_mp2mr(txq, txq_mb2mp(buf)),
 813                         naddr,
 814                         naddr >> 32,
 815                 };
 816                 (*txq->elts)[++elts_head & elts_m] = buf;
 817                 ++sg;
 818                 /* Advance counter only if all segs are successfully posted. */
 819                 if (sg < segs_n)
 820                         goto next_seg;
 821                 else
 822                         j += sg;
 823 next_pkt:
 824                 ++elts_head;
 825                 ++pkts;
 826                 ++i;
 827                 /* Initialize known and common part of the WQE structure. */
 828                 if (tso) {
 829                         wqe->ctrl = (rte_v128u32_t){
 830                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
 831                                 htonl(txq->qp_num_8s | ds),
 832                                 0,
 833                                 0,
 834                         };
 835                         wqe->eseg = (rte_v128u32_t){
 836                                 0,
 837                                 cs_flags | (htons(tso_segsz) << 16),
 838                                 0,
 839                                 (ehdr << 16) | htons(tso_header_sz),
 840                         };
 841                 } else {
 842                         wqe->ctrl = (rte_v128u32_t){
 843                                 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
 844                                 htonl(txq->qp_num_8s | ds),
 845                                 0,
 846                                 0,
 847                         };
 848                         wqe->eseg = (rte_v128u32_t){
 849                                 0,
 850                                 cs_flags,
 851                                 0,
 852                                 (ehdr << 16) | htons(pkt_inline_sz),
 853                         };
 854                 }
 855 next_wqe:
 856                 txq->wqe_ci += (ds + 3) / 4;
 857                 /* Save the last successful WQE for completion request */
 858                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 859 #ifdef MLX5_PMD_SOFT_COUNTERS
 860                 /* Increment sent bytes counter. */
 861                 txq->stats.obytes += total_length;
 862 #endif
 863         } while (i < pkts_n);
 864         /* Take a shortcut if nothing must be sent. */
 865         if (unlikely((i + k) == 0))
 866                 return 0;
 867         txq->elts_head += (i + j);
 868         /* Check whether completion threshold has been reached. */
 869         comp = txq->elts_comp + i + j + k;
 870         if (comp >= MLX5_TX_COMP_THRESH) {
 871                 /* Request completion on last WQE. */
 872                 last_wqe->ctrl2 = htonl(8);
 873                 /* Save elts_head in unused "immediate" field of WQE. */
 874                 last_wqe->ctrl3 = txq->elts_head;
 875                 txq->elts_comp = 0;
 876         } else {
 877                 txq->elts_comp = comp;
 878         }
 879 #ifdef MLX5_PMD_SOFT_COUNTERS
 880         /* Increment sent packets counter. */
 881         txq->stats.opackets += i;
 882 #endif
 883         /* Ring QP doorbell. */
 884         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 885         return i;
 886 }
 887
 888 /**
 889  * Open a MPW session.
 890  *
 891  * @param txq
 892  *   Pointer to TX queue structure.
 893  * @param mpw
 894  *   Pointer to MPW session structure.
 895  * @param length
 896  *   Packet length.
 897  */
 898 static inline void
 899 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
 900 {
 901         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 902         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 903                 (volatile struct mlx5_wqe_data_seg (*)[])
 904                 tx_mlx5_wqe(txq, idx + 1);
 905
 906         mpw->state = MLX5_MPW_STATE_OPENED;
 907         mpw->pkts_n = 0;
 908         mpw->len = length;
 909         mpw->total_len = 0;
 910         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 911         mpw->wqe->eseg.mss = htons(length);
 912         mpw->wqe->eseg.inline_hdr_sz = 0;
 913         mpw->wqe->eseg.rsvd0 = 0;
 914         mpw->wqe->eseg.rsvd1 = 0;
 915         mpw->wqe->eseg.rsvd2 = 0;
 916         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
 917                                   (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
 918         mpw->wqe->ctrl[2] = 0;
 919         mpw->wqe->ctrl[3] = 0;
 920         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 921                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 922         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 923                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 924         mpw->data.dseg[2] = &(*dseg)[0];
 925         mpw->data.dseg[3] = &(*dseg)[1];
 926         mpw->data.dseg[4] = &(*dseg)[2];
 927 }
 928
 929 /**
 930  * Close a MPW session.
 931  *
 932  * @param txq
 933  *   Pointer to TX queue structure.
 934  * @param mpw
 935  *   Pointer to MPW session structure.
 936  */
 937 static inline void
 938 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
 939 {
 940         unsigned int num = mpw->pkts_n;
 941
 942         /*
 943          * Store size in multiple of 16 bytes. Control and Ethernet segments
 944          * count as 2.
 945          */
 946         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
 947         mpw->state = MLX5_MPW_STATE_CLOSED;
 948         if (num < 3)
 949                 ++txq->wqe_ci;
 950         else
 951                 txq->wqe_ci += 2;
 952         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 953         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 954 }
 955
 956 /**
 957  * DPDK callback for TX with MPW support.
 958  *
 959  * @param dpdk_txq
 960  *   Generic pointer to TX queue structure.
 961  * @param[in] pkts
 962  *   Packets to transmit.
 963  * @param pkts_n
 964  *   Number of packets in array.
 965  *
 966  * @return
 967  *   Number of packets successfully transmitted (<= pkts_n).
 968  */
 969 uint16_t
 970 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 971 {
 972         struct txq *txq = (struct txq *)dpdk_txq;
 973         uint16_t elts_head = txq->elts_head;
 974         const uint16_t elts_n = 1 << txq->elts_n;
 975         const uint16_t elts_m = elts_n - 1;
 976         unsigned int i = 0;
 977         unsigned int j = 0;
 978         uint16_t max_elts;
 979         uint16_t max_wqe;
 980         unsigned int comp;
 981         struct mlx5_mpw mpw = {
 982                 .state = MLX5_MPW_STATE_CLOSED,
 983         };
 984
 985         if (unlikely(!pkts_n))
 986                 return 0;
 987         /* Prefetch first packet cacheline. */
 988         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 989         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 990         /* Start processing. */
 991         txq_complete(txq);
 992         max_elts = (elts_n - (elts_head - txq->elts_tail));
 993         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 994         if (unlikely(!max_wqe))
 995                 return 0;
 996         do {
 997                 struct rte_mbuf *buf = *(pkts++);
 998                 uint32_t length;
 999                 unsigned int segs_n = buf->nb_segs;
1000                 uint32_t cs_flags = 0;
1001
1002                 /*
1003                  * Make sure there is enough room to store this packet and
1004                  * that one ring entry remains unused.
1005                  */
1006                 assert(segs_n);
1007                 if (max_elts < segs_n)
1008                         break;
1009                 /* Do not bother with large packets MPW cannot handle. */
1010                 if (segs_n > MLX5_MPW_DSEG_MAX)
1011                         break;
1012                 max_elts -= segs_n;
1013                 --pkts_n;
1014                 /* Should we enable HW CKSUM offload */
1015                 if (buf->ol_flags &
1016                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1017                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1018                 /* Retrieve packet information. */
1019                 length = PKT_LEN(buf);
1020                 assert(length);
1021                 /* Start new session if packet differs. */
1022                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1023                     ((mpw.len != length) ||
1024                      (segs_n != 1) ||
1025                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1026                         mlx5_mpw_close(txq, &mpw);
1027                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1028                         /*
1029                          * Multi-Packet WQE consumes at most two WQE.
1030                          * mlx5_mpw_new() expects to be able to use such
1031                          * resources.
1032                          */
1033                         if (unlikely(max_wqe < 2))
1034                                 break;
1035                         max_wqe -= 2;
1036                         mlx5_mpw_new(txq, &mpw, length);
1037                         mpw.wqe->eseg.cs_flags = cs_flags;
1038                 }
1039                 /* Multi-segment packets must be alone in their MPW. */
1040                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1041 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1042                 length = 0;
1043 #endif
1044                 do {
1045                         volatile struct mlx5_wqe_data_seg *dseg;
1046                         uintptr_t addr;
1047
1048                         assert(buf);
1049                         (*txq->elts)[elts_head++ & elts_m] = buf;
1050                         dseg = mpw.data.dseg[mpw.pkts_n];
1051                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1052                         *dseg = (struct mlx5_wqe_data_seg){
1053                                 .byte_count = htonl(DATA_LEN(buf)),
1054                                 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1055                                 .addr = htonll(addr),
1056                         };
1057 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1058                         length += DATA_LEN(buf);
1059 #endif
1060                         buf = buf->next;
1061                         ++mpw.pkts_n;
1062                         ++j;
1063                 } while (--segs_n);
1064                 assert(length == mpw.len);
1065                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1066                         mlx5_mpw_close(txq, &mpw);
1067 #ifdef MLX5_PMD_SOFT_COUNTERS
1068                 /* Increment sent bytes counter. */
1069                 txq->stats.obytes += length;
1070 #endif
1071                 ++i;
1072         } while (pkts_n);
1073         /* Take a shortcut if nothing must be sent. */
1074         if (unlikely(i == 0))
1075                 return 0;
1076         /* Check whether completion threshold has been reached. */
1077         /* "j" includes both packets and segments. */
1078         comp = txq->elts_comp + j;
1079         if (comp >= MLX5_TX_COMP_THRESH) {
1080                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1081
1082                 /* Request completion on last WQE. */
1083                 wqe->ctrl[2] = htonl(8);
1084                 /* Save elts_head in unused "immediate" field of WQE. */
1085                 wqe->ctrl[3] = elts_head;
1086                 txq->elts_comp = 0;
1087         } else {
1088                 txq->elts_comp = comp;
1089         }
1090 #ifdef MLX5_PMD_SOFT_COUNTERS
1091         /* Increment sent packets counter. */
1092         txq->stats.opackets += i;
1093 #endif
1094         /* Ring QP doorbell. */
1095         if (mpw.state == MLX5_MPW_STATE_OPENED)
1096                 mlx5_mpw_close(txq, &mpw);
1097         mlx5_tx_dbrec(txq, mpw.wqe);
1098         txq->elts_head = elts_head;
1099         return i;
1100 }
1101
1102 /**
1103  * Open a MPW inline session.
1104  *
1105  * @param txq
1106  *   Pointer to TX queue structure.
1107  * @param mpw
1108  *   Pointer to MPW session structure.
1109  * @param length
1110  *   Packet length.
1111  */
1112 static inline void
1113 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1114 {
1115         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1116         struct mlx5_wqe_inl_small *inl;
1117
1118         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1119         mpw->pkts_n = 0;
1120         mpw->len = length;
1121         mpw->total_len = 0;
1122         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1123         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1124                                   (txq->wqe_ci << 8) |
1125                                   MLX5_OPCODE_TSO);
1126         mpw->wqe->ctrl[2] = 0;
1127         mpw->wqe->ctrl[3] = 0;
1128         mpw->wqe->eseg.mss = htons(length);
1129         mpw->wqe->eseg.inline_hdr_sz = 0;
1130         mpw->wqe->eseg.cs_flags = 0;
1131         mpw->wqe->eseg.rsvd0 = 0;
1132         mpw->wqe->eseg.rsvd1 = 0;
1133         mpw->wqe->eseg.rsvd2 = 0;
1134         inl = (struct mlx5_wqe_inl_small *)
1135                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1136         mpw->data.raw = (uint8_t *)&inl->raw;
1137 }
1138
1139 /**
1140  * Close a MPW inline session.
1141  *
1142  * @param txq
1143  *   Pointer to TX queue structure.
1144  * @param mpw
1145  *   Pointer to MPW session structure.
1146  */
1147 static inline void
1148 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1149 {
1150         unsigned int size;
1151         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1152                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1153
1154         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1155         /*
1156          * Store size in multiple of 16 bytes. Control and Ethernet segments
1157          * count as 2.
1158          */
1159         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1160         mpw->state = MLX5_MPW_STATE_CLOSED;
1161         inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1162         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1163 }
1164
1165 /**
1166  * DPDK callback for TX with MPW inline support.
1167  *
1168  * @param dpdk_txq
1169  *   Generic pointer to TX queue structure.
1170  * @param[in] pkts
1171  *   Packets to transmit.
1172  * @param pkts_n
1173  *   Number of packets in array.
1174  *
1175  * @return
1176  *   Number of packets successfully transmitted (<= pkts_n).
1177  */
1178 uint16_t
1179 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1180                          uint16_t pkts_n)
1181 {
1182         struct txq *txq = (struct txq *)dpdk_txq;
1183         uint16_t elts_head = txq->elts_head;
1184         const uint16_t elts_n = 1 << txq->elts_n;
1185         const uint16_t elts_m = elts_n - 1;
1186         unsigned int i = 0;
1187         unsigned int j = 0;
1188         uint16_t max_elts;
1189         uint16_t max_wqe;
1190         unsigned int comp;
1191         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1192         struct mlx5_mpw mpw = {
1193                 .state = MLX5_MPW_STATE_CLOSED,
1194         };
1195         /*
1196          * Compute the maximum number of WQE which can be consumed by inline
1197          * code.
1198          * - 2 DSEG for:
1199          *   - 1 control segment,
1200          *   - 1 Ethernet segment,
1201          * - N Dseg from the inline request.
1202          */
1203         const unsigned int wqe_inl_n =
1204                 ((2 * MLX5_WQE_DWORD_SIZE +
1205                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1206                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1207
1208         if (unlikely(!pkts_n))
1209                 return 0;
1210         /* Prefetch first packet cacheline. */
1211         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1212         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1213         /* Start processing. */
1214         txq_complete(txq);
1215         max_elts = (elts_n - (elts_head - txq->elts_tail));
1216         do {
1217                 struct rte_mbuf *buf = *(pkts++);
1218                 uintptr_t addr;
1219                 uint32_t length;
1220                 unsigned int segs_n = buf->nb_segs;
1221                 uint32_t cs_flags = 0;
1222
1223                 /*
1224                  * Make sure there is enough room to store this packet and
1225                  * that one ring entry remains unused.
1226                  */
1227                 assert(segs_n);
1228                 if (max_elts < segs_n)
1229                         break;
1230                 /* Do not bother with large packets MPW cannot handle. */
1231                 if (segs_n > MLX5_MPW_DSEG_MAX)
1232                         break;
1233                 max_elts -= segs_n;
1234                 --pkts_n;
1235                 /*
1236                  * Compute max_wqe in case less WQE were consumed in previous
1237                  * iteration.
1238                  */
1239                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1240                 /* Should we enable HW CKSUM offload */
1241                 if (buf->ol_flags &
1242                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1243                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1244                 /* Retrieve packet information. */
1245                 length = PKT_LEN(buf);
1246                 /* Start new session if packet differs. */
1247                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1248                         if ((mpw.len != length) ||
1249                             (segs_n != 1) ||
1250                             (mpw.wqe->eseg.cs_flags != cs_flags))
1251                                 mlx5_mpw_close(txq, &mpw);
1252                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1253                         if ((mpw.len != length) ||
1254                             (segs_n != 1) ||
1255                             (length > inline_room) ||
1256                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1257                                 mlx5_mpw_inline_close(txq, &mpw);
1258                                 inline_room =
1259                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1260                         }
1261                 }
1262                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1263                         if ((segs_n != 1) ||
1264                             (length > inline_room)) {
1265                                 /*
1266                                  * Multi-Packet WQE consumes at most two WQE.
1267                                  * mlx5_mpw_new() expects to be able to use
1268                                  * such resources.
1269                                  */
1270                                 if (unlikely(max_wqe < 2))
1271                                         break;
1272                                 max_wqe -= 2;
1273                                 mlx5_mpw_new(txq, &mpw, length);
1274                                 mpw.wqe->eseg.cs_flags = cs_flags;
1275                         } else {
1276                                 if (unlikely(max_wqe < wqe_inl_n))
1277                                         break;
1278                                 max_wqe -= wqe_inl_n;
1279                                 mlx5_mpw_inline_new(txq, &mpw, length);
1280                                 mpw.wqe->eseg.cs_flags = cs_flags;
1281                         }
1282                 }
1283                 /* Multi-segment packets must be alone in their MPW. */
1284                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1285                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1286                         assert(inline_room ==
1287                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1288 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1289                         length = 0;
1290 #endif
1291                         do {
1292                                 volatile struct mlx5_wqe_data_seg *dseg;
1293
1294                                 assert(buf);
1295                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1296                                 dseg = mpw.data.dseg[mpw.pkts_n];
1297                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1298                                 *dseg = (struct mlx5_wqe_data_seg){
1299                                         .byte_count = htonl(DATA_LEN(buf)),
1300                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1301                                         .addr = htonll(addr),
1302                                 };
1303 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1304                                 length += DATA_LEN(buf);
1305 #endif
1306                                 buf = buf->next;
1307                                 ++mpw.pkts_n;
1308                                 ++j;
1309                         } while (--segs_n);
1310                         assert(length == mpw.len);
1311                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1312                                 mlx5_mpw_close(txq, &mpw);
1313                 } else {
1314                         unsigned int max;
1315
1316                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1317                         assert(length <= inline_room);
1318                         assert(length == DATA_LEN(buf));
1319                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1320                         (*txq->elts)[elts_head++ & elts_m] = buf;
1321                         /* Maximum number of bytes before wrapping. */
1322                         max = ((((uintptr_t)(txq->wqes)) +
1323                                 (1 << txq->wqe_n) *
1324                                 MLX5_WQE_SIZE) -
1325                                (uintptr_t)mpw.data.raw);
1326                         if (length > max) {
1327                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1328                                            (void *)addr,
1329                                            max);
1330                                 mpw.data.raw = (volatile void *)txq->wqes;
1331                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1332                                            (void *)(addr + max),
1333                                            length - max);
1334                                 mpw.data.raw += length - max;
1335                         } else {
1336                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1337                                            (void *)addr,
1338                                            length);
1339
1340                                 if (length == max)
1341                                         mpw.data.raw =
1342                                                 (volatile void *)txq->wqes;
1343                                 else
1344                                         mpw.data.raw += length;
1345                         }
1346                         ++mpw.pkts_n;
1347                         mpw.total_len += length;
1348                         ++j;
1349                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1350                                 mlx5_mpw_inline_close(txq, &mpw);
1351                                 inline_room =
1352                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1353                         } else {
1354                                 inline_room -= length;
1355                         }
1356                 }
1357 #ifdef MLX5_PMD_SOFT_COUNTERS
1358                 /* Increment sent bytes counter. */
1359                 txq->stats.obytes += length;
1360 #endif
1361                 ++i;
1362         } while (pkts_n);
1363         /* Take a shortcut if nothing must be sent. */
1364         if (unlikely(i == 0))
1365                 return 0;
1366         /* Check whether completion threshold has been reached. */
1367         /* "j" includes both packets and segments. */
1368         comp = txq->elts_comp + j;
1369         if (comp >= MLX5_TX_COMP_THRESH) {
1370                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1371
1372                 /* Request completion on last WQE. */
1373                 wqe->ctrl[2] = htonl(8);
1374                 /* Save elts_head in unused "immediate" field of WQE. */
1375                 wqe->ctrl[3] = elts_head;
1376                 txq->elts_comp = 0;
1377         } else {
1378                 txq->elts_comp = comp;
1379         }
1380 #ifdef MLX5_PMD_SOFT_COUNTERS
1381         /* Increment sent packets counter. */
1382         txq->stats.opackets += i;
1383 #endif
1384         /* Ring QP doorbell. */
1385         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1386                 mlx5_mpw_inline_close(txq, &mpw);
1387         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1388                 mlx5_mpw_close(txq, &mpw);
1389         mlx5_tx_dbrec(txq, mpw.wqe);
1390         txq->elts_head = elts_head;
1391         return i;
1392 }
1393
1394 /**
1395  * Open an Enhanced MPW session.
1396  *
1397  * @param txq
1398  *   Pointer to TX queue structure.
1399  * @param mpw
1400  *   Pointer to MPW session structure.
1401  * @param length
1402  *   Packet length.
1403  */
1404 static inline void
1405 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1406 {
1407         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1408
1409         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1410         mpw->pkts_n = 0;
1411         mpw->total_len = sizeof(struct mlx5_wqe);
1412         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1413         mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1414                                   (txq->wqe_ci << 8) |
1415                                   MLX5_OPCODE_ENHANCED_MPSW);
1416         mpw->wqe->ctrl[2] = 0;
1417         mpw->wqe->ctrl[3] = 0;
1418         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1419         if (unlikely(padding)) {
1420                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1421
1422                 /* Pad the first 2 DWORDs with zero-length inline header. */
1423                 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1424                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1425                         htonl(MLX5_INLINE_SEG);
1426                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1427                 /* Start from the next WQEBB. */
1428                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1429         } else {
1430                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1431         }
1432 }
1433
1434 /**
1435  * Close an Enhanced MPW session.
1436  *
1437  * @param txq
1438  *   Pointer to TX queue structure.
1439  * @param mpw
1440  *   Pointer to MPW session structure.
1441  *
1442  * @return
1443  *   Number of consumed WQEs.
1444  */
1445 static inline uint16_t
1446 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1447 {
1448         uint16_t ret;
1449
1450         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1451          * count as 2.
1452          */
1453         mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1454         mpw->state = MLX5_MPW_STATE_CLOSED;
1455         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1456         txq->wqe_ci += ret;
1457         return ret;
1458 }
1459
1460 /**
1461  * DPDK callback for TX with Enhanced MPW support.
1462  *
1463  * @param dpdk_txq
1464  *   Generic pointer to TX queue structure.
1465  * @param[in] pkts
1466  *   Packets to transmit.
1467  * @param pkts_n
1468  *   Number of packets in array.
1469  *
1470  * @return
1471  *   Number of packets successfully transmitted (<= pkts_n).
1472  */
1473 uint16_t
1474 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1475 {
1476         struct txq *txq = (struct txq *)dpdk_txq;
1477         uint16_t elts_head = txq->elts_head;
1478         const uint16_t elts_n = 1 << txq->elts_n;
1479         const uint16_t elts_m = elts_n - 1;
1480         unsigned int i = 0;
1481         unsigned int j = 0;
1482         uint16_t max_elts;
1483         uint16_t max_wqe;
1484         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1485         unsigned int mpw_room = 0;
1486         unsigned int inl_pad = 0;
1487         uint32_t inl_hdr;
1488         struct mlx5_mpw mpw = {
1489                 .state = MLX5_MPW_STATE_CLOSED,
1490         };
1491
1492         if (unlikely(!pkts_n))
1493                 return 0;
1494         /* Start processing. */
1495         txq_complete(txq);
1496         max_elts = (elts_n - (elts_head - txq->elts_tail));
1497         /* A CQE slot must always be available. */
1498         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1499         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1500         if (unlikely(!max_wqe))
1501                 return 0;
1502         do {
1503                 struct rte_mbuf *buf = *(pkts++);
1504                 uintptr_t addr;
1505                 uint64_t naddr;
1506                 unsigned int n;
1507                 unsigned int do_inline = 0; /* Whether inline is possible. */
1508                 uint32_t length;
1509                 unsigned int segs_n = buf->nb_segs;
1510                 uint32_t cs_flags = 0;
1511
1512                 /*
1513                  * Make sure there is enough room to store this packet and
1514                  * that one ring entry remains unused.
1515                  */
1516                 assert(segs_n);
1517                 if (max_elts - j < segs_n)
1518                         break;
1519                 /* Do not bother with large packets MPW cannot handle. */
1520                 if (segs_n > MLX5_MPW_DSEG_MAX)
1521                         break;
1522                 /* Should we enable HW CKSUM offload. */
1523                 if (buf->ol_flags &
1524                     (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1525                         cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1526                 /* Retrieve packet information. */
1527                 length = PKT_LEN(buf);
1528                 /* Start new session if:
1529                  * - multi-segment packet
1530                  * - no space left even for a dseg
1531                  * - next packet can be inlined with a new WQE
1532                  * - cs_flag differs
1533                  * It can't be MLX5_MPW_STATE_OPENED as always have a single
1534                  * segmented packet.
1535                  */
1536                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1537                         if ((segs_n != 1) ||
1538                             (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1539                               mpw_room) ||
1540                             (length <= txq->inline_max_packet_sz &&
1541                              inl_pad + sizeof(inl_hdr) + length >
1542                               mpw_room) ||
1543                             (mpw.wqe->eseg.cs_flags != cs_flags))
1544                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1545                 }
1546                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1547                         if (unlikely(segs_n != 1)) {
1548                                 /* Fall back to legacy MPW.
1549                                  * A MPW session consumes 2 WQEs at most to
1550                                  * include MLX5_MPW_DSEG_MAX pointers.
1551                                  */
1552                                 if (unlikely(max_wqe < 2))
1553                                         break;
1554                                 mlx5_mpw_new(txq, &mpw, length);
1555                         } else {
1556                                 /* In Enhanced MPW, inline as much as the budget
1557                                  * is allowed. The remaining space is to be
1558                                  * filled with dsegs. If the title WQEBB isn't
1559                                  * padded, it will have 2 dsegs there.
1560                                  */
1561                                 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1562                                             (max_inline ? max_inline :
1563                                              pkts_n * MLX5_WQE_DWORD_SIZE) +
1564                                             MLX5_WQE_SIZE);
1565                                 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1566                                               mpw_room))
1567                                         break;
1568                                 /* Don't pad the title WQEBB to not waste WQ. */
1569                                 mlx5_empw_new(txq, &mpw, 0);
1570                                 mpw_room -= mpw.total_len;
1571                                 inl_pad = 0;
1572                                 do_inline =
1573                                         length <= txq->inline_max_packet_sz &&
1574                                         sizeof(inl_hdr) + length <= mpw_room &&
1575                                         !txq->mpw_hdr_dseg;
1576                         }
1577                         mpw.wqe->eseg.cs_flags = cs_flags;
1578                 } else {
1579                         /* Evaluate whether the next packet can be inlined.
1580                          * Inlininig is possible when:
1581                          * - length is less than configured value
1582                          * - length fits for remaining space
1583                          * - not required to fill the title WQEBB with dsegs
1584                          */
1585                         do_inline =
1586                                 length <= txq->inline_max_packet_sz &&
1587                                 inl_pad + sizeof(inl_hdr) + length <=
1588                                  mpw_room &&
1589                                 (!txq->mpw_hdr_dseg ||
1590                                  mpw.total_len >= MLX5_WQE_SIZE);
1591                 }
1592                 /* Multi-segment packets must be alone in their MPW. */
1593                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1594                 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1595 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1596                         length = 0;
1597 #endif
1598                         do {
1599                                 volatile struct mlx5_wqe_data_seg *dseg;
1600
1601                                 assert(buf);
1602                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1603                                 dseg = mpw.data.dseg[mpw.pkts_n];
1604                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1605                                 *dseg = (struct mlx5_wqe_data_seg){
1606                                         .byte_count = htonl(DATA_LEN(buf)),
1607                                         .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1608                                         .addr = htonll(addr),
1609                                 };
1610 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1611                                 length += DATA_LEN(buf);
1612 #endif
1613                                 buf = buf->next;
1614                                 ++j;
1615                                 ++mpw.pkts_n;
1616                         } while (--segs_n);
1617                         /* A multi-segmented packet takes one MPW session.
1618                          * TODO: Pack more multi-segmented packets if possible.
1619                          */
1620                         mlx5_mpw_close(txq, &mpw);
1621                         if (mpw.pkts_n < 3)
1622                                 max_wqe--;
1623                         else
1624                                 max_wqe -= 2;
1625                 } else if (do_inline) {
1626                         /* Inline packet into WQE. */
1627                         unsigned int max;
1628
1629                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1630                         assert(length == DATA_LEN(buf));
1631                         inl_hdr = htonl(length | MLX5_INLINE_SEG);
1632                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1633                         mpw.data.raw = (volatile void *)
1634                                 ((uintptr_t)mpw.data.raw + inl_pad);
1635                         max = tx_mlx5_wq_tailroom(txq,
1636                                         (void *)(uintptr_t)mpw.data.raw);
1637                         /* Copy inline header. */
1638                         mpw.data.raw = (volatile void *)
1639                                 mlx5_copy_to_wq(
1640                                           (void *)(uintptr_t)mpw.data.raw,
1641                                           &inl_hdr,
1642                                           sizeof(inl_hdr),
1643                                           (void *)(uintptr_t)txq->wqes,
1644                                           max);
1645                         max = tx_mlx5_wq_tailroom(txq,
1646                                         (void *)(uintptr_t)mpw.data.raw);
1647                         /* Copy packet data. */
1648                         mpw.data.raw = (volatile void *)
1649                                 mlx5_copy_to_wq(
1650                                           (void *)(uintptr_t)mpw.data.raw,
1651                                           (void *)addr,
1652                                           length,
1653                                           (void *)(uintptr_t)txq->wqes,
1654                                           max);
1655                         ++mpw.pkts_n;
1656                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1657                         /* No need to get completion as the entire packet is
1658                          * copied to WQ. Free the buf right away.
1659                          */
1660                         rte_pktmbuf_free_seg(buf);
1661                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1662                         /* Add pad in the next packet if any. */
1663                         inl_pad = (((uintptr_t)mpw.data.raw +
1664                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1665                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1666                                   (uintptr_t)mpw.data.raw;
1667                 } else {
1668                         /* No inline. Load a dseg of packet pointer. */
1669                         volatile rte_v128u32_t *dseg;
1670
1671                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1672                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1673                         assert(length == DATA_LEN(buf));
1674                         if (!tx_mlx5_wq_tailroom(txq,
1675                                         (void *)((uintptr_t)mpw.data.raw
1676                                                 + inl_pad)))
1677                                 dseg = (volatile void *)txq->wqes;
1678                         else
1679                                 dseg = (volatile void *)
1680                                         ((uintptr_t)mpw.data.raw +
1681                                          inl_pad);
1682                         (*txq->elts)[elts_head++ & elts_m] = buf;
1683                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1684                         for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1685                                 rte_prefetch2((void *)(addr +
1686                                                 n * RTE_CACHE_LINE_SIZE));
1687                         naddr = htonll(addr);
1688                         *dseg = (rte_v128u32_t) {
1689                                 htonl(length),
1690                                 txq_mp2mr(txq, txq_mb2mp(buf)),
1691                                 naddr,
1692                                 naddr >> 32,
1693                         };
1694                         mpw.data.raw = (volatile void *)(dseg + 1);
1695                         mpw.total_len += (inl_pad + sizeof(*dseg));
1696                         ++j;
1697                         ++mpw.pkts_n;
1698                         mpw_room -= (inl_pad + sizeof(*dseg));
1699                         inl_pad = 0;
1700                 }
1701 #ifdef MLX5_PMD_SOFT_COUNTERS
1702                 /* Increment sent bytes counter. */
1703                 txq->stats.obytes += length;
1704 #endif
1705                 ++i;
1706         } while (i < pkts_n);
1707         /* Take a shortcut if nothing must be sent. */
1708         if (unlikely(i == 0))
1709                 return 0;
1710         /* Check whether completion threshold has been reached. */
1711         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1712                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1713                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1714                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1715
1716                 /* Request completion on last WQE. */
1717                 wqe->ctrl[2] = htonl(8);
1718                 /* Save elts_head in unused "immediate" field of WQE. */
1719                 wqe->ctrl[3] = elts_head;
1720                 txq->elts_comp = 0;
1721                 txq->mpw_comp = txq->wqe_ci;
1722                 txq->cq_pi++;
1723         } else {
1724                 txq->elts_comp += j;
1725         }
1726 #ifdef MLX5_PMD_SOFT_COUNTERS
1727         /* Increment sent packets counter. */
1728         txq->stats.opackets += i;
1729 #endif
1730         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1731                 mlx5_empw_close(txq, &mpw);
1732         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1733                 mlx5_mpw_close(txq, &mpw);
1734         /* Ring QP doorbell. */
1735         mlx5_tx_dbrec(txq, mpw.wqe);
1736         txq->elts_head = elts_head;
1737         return i;
1738 }
1739
1740 /**
1741  * Translate RX completion flags to packet type.
1742  *
1743  * @param[in] cqe
1744  *   Pointer to CQE.
1745  *
1746  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1747  *
1748  * @return
1749  *   Packet type for struct rte_mbuf.
1750  */
1751 static inline uint32_t
1752 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1753 {
1754         uint32_t pkt_type;
1755         uint16_t flags = ntohs(cqe->hdr_type_etc);
1756
1757         if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1758                 pkt_type =
1759                         TRANSPOSE(flags,
1760                                   MLX5_CQE_RX_IPV4_PACKET,
1761                                   RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1762                         TRANSPOSE(flags,
1763                                   MLX5_CQE_RX_IPV6_PACKET,
1764                                   RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1765                 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1766                              RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1767                              RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1768         } else {
1769                 pkt_type =
1770                         TRANSPOSE(flags,
1771                                   MLX5_CQE_L3_HDR_TYPE_IPV6,
1772                                   RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1773                         TRANSPOSE(flags,
1774                                   MLX5_CQE_L3_HDR_TYPE_IPV4,
1775                                   RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1776         }
1777         return pkt_type;
1778 }
1779
1780 /**
1781  * Get size of the next packet for a given CQE. For compressed CQEs, the
1782  * consumer index is updated only once all packets of the current one have
1783  * been processed.
1784  *
1785  * @param rxq
1786  *   Pointer to RX queue.
1787  * @param cqe
1788  *   CQE to process.
1789  * @param[out] rss_hash
1790  *   Packet RSS Hash result.
1791  *
1792  * @return
1793  *   Packet size in bytes (0 if there is none), -1 in case of completion
1794  *   with error.
1795  */
1796 static inline int
1797 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1798                  uint16_t cqe_cnt, uint32_t *rss_hash)
1799 {
1800         struct rxq_zip *zip = &rxq->zip;
1801         uint16_t cqe_n = cqe_cnt + 1;
1802         int len = 0;
1803         uint16_t idx, end;
1804
1805         /* Process compressed data in the CQE and mini arrays. */
1806         if (zip->ai) {
1807                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1808                         (volatile struct mlx5_mini_cqe8 (*)[8])
1809                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1810
1811                 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1812                 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1813                 if ((++zip->ai & 7) == 0) {
1814                         /* Invalidate consumed CQEs */
1815                         idx = zip->ca;
1816                         end = zip->na;
1817                         while (idx != end) {
1818                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1819                                         MLX5_CQE_INVALIDATE;
1820                                 ++idx;
1821                         }
1822                         /*
1823                          * Increment consumer index to skip the number of
1824                          * CQEs consumed. Hardware leaves holes in the CQ
1825                          * ring for software use.
1826                          */
1827                         zip->ca = zip->na;
1828                         zip->na += 8;
1829                 }
1830                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1831                         /* Invalidate the rest */
1832                         idx = zip->ca;
1833                         end = zip->cq_ci;
1834
1835                         while (idx != end) {
1836                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1837                                         MLX5_CQE_INVALIDATE;
1838                                 ++idx;
1839                         }
1840                         rxq->cq_ci = zip->cq_ci;
1841                         zip->ai = 0;
1842                 }
1843         /* No compressed data, get next CQE and verify if it is compressed. */
1844         } else {
1845                 int ret;
1846                 int8_t op_own;
1847
1848                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1849                 if (unlikely(ret == 1))
1850                         return 0;
1851                 ++rxq->cq_ci;
1852                 op_own = cqe->op_own;
1853                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1854                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1855                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1856                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1857                                                           cqe_cnt]);
1858
1859                         /* Fix endianness. */
1860                         zip->cqe_cnt = ntohl(cqe->byte_cnt);
1861                         /*
1862                          * Current mini array position is the one returned by
1863                          * check_cqe64().
1864                          *
1865                          * If completion comprises several mini arrays, as a
1866                          * special case the second one is located 7 CQEs after
1867                          * the initial CQE instead of 8 for subsequent ones.
1868                          */
1869                         zip->ca = rxq->cq_ci;
1870                         zip->na = zip->ca + 7;
1871                         /* Compute the next non compressed CQE. */
1872                         --rxq->cq_ci;
1873                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1874                         /* Get packet size to return. */
1875                         len = ntohl((*mc)[0].byte_cnt);
1876                         *rss_hash = ntohl((*mc)[0].rx_hash_result);
1877                         zip->ai = 1;
1878                         /* Prefetch all the entries to be invalidated */
1879                         idx = zip->ca;
1880                         end = zip->cq_ci;
1881                         while (idx != end) {
1882                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1883                                 ++idx;
1884                         }
1885                 } else {
1886                         len = ntohl(cqe->byte_cnt);
1887                         *rss_hash = ntohl(cqe->rx_hash_res);
1888                 }
1889                 /* Error while receiving packet. */
1890                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1891                         return -1;
1892         }
1893         return len;
1894 }
1895
1896 /**
1897  * Translate RX completion flags to offload flags.
1898  *
1899  * @param[in] rxq
1900  *   Pointer to RX queue structure.
1901  * @param[in] cqe
1902  *   Pointer to CQE.
1903  *
1904  * @return
1905  *   Offload flags (ol_flags) for struct rte_mbuf.
1906  */
1907 static inline uint32_t
1908 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1909 {
1910         uint32_t ol_flags = 0;
1911         uint16_t flags = ntohs(cqe->hdr_type_etc);
1912
1913         ol_flags =
1914                 TRANSPOSE(flags,
1915                           MLX5_CQE_RX_L3_HDR_VALID,
1916                           PKT_RX_IP_CKSUM_GOOD) |
1917                 TRANSPOSE(flags,
1918                           MLX5_CQE_RX_L4_HDR_VALID,
1919                           PKT_RX_L4_CKSUM_GOOD);
1920         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1921                 ol_flags |=
1922                         TRANSPOSE(flags,
1923                                   MLX5_CQE_RX_L3_HDR_VALID,
1924                                   PKT_RX_IP_CKSUM_GOOD) |
1925                         TRANSPOSE(flags,
1926                                   MLX5_CQE_RX_L4_HDR_VALID,
1927                                   PKT_RX_L4_CKSUM_GOOD);
1928         return ol_flags;
1929 }
1930
1931 /**
1932  * DPDK callback for RX.
1933  *
1934  * @param dpdk_rxq
1935  *   Generic pointer to RX queue structure.
1936  * @param[out] pkts
1937  *   Array to store received packets.
1938  * @param pkts_n
1939  *   Maximum number of packets in array.
1940  *
1941  * @return
1942  *   Number of packets successfully received (<= pkts_n).
1943  */
1944 uint16_t
1945 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1946 {
1947         struct rxq *rxq = dpdk_rxq;
1948         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1949         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1950         const unsigned int sges_n = rxq->sges_n;
1951         struct rte_mbuf *pkt = NULL;
1952         struct rte_mbuf *seg = NULL;
1953         volatile struct mlx5_cqe *cqe =
1954                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1955         unsigned int i = 0;
1956         unsigned int rq_ci = rxq->rq_ci << sges_n;
1957         int len = 0; /* keep its value across iterations. */
1958
1959         while (pkts_n) {
1960                 unsigned int idx = rq_ci & wqe_cnt;
1961                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1962                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1963                 uint32_t rss_hash_res = 0;
1964
1965                 if (pkt)
1966                         NEXT(seg) = rep;
1967                 seg = rep;
1968                 rte_prefetch0(seg);
1969                 rte_prefetch0(cqe);
1970                 rte_prefetch0(wqe);
1971                 rep = rte_mbuf_raw_alloc(rxq->mp);
1972                 if (unlikely(rep == NULL)) {
1973                         ++rxq->stats.rx_nombuf;
1974                         if (!pkt) {
1975                                 /*
1976                                  * no buffers before we even started,
1977                                  * bail out silently.
1978                                  */
1979                                 break;
1980                         }
1981                         while (pkt != seg) {
1982                                 assert(pkt != (*rxq->elts)[idx]);
1983                                 rep = NEXT(pkt);
1984                                 NEXT(pkt) = NULL;
1985                                 NB_SEGS(pkt) = 1;
1986                                 rte_mbuf_raw_free(pkt);
1987                                 pkt = rep;
1988                         }
1989                         break;
1990                 }
1991                 if (!pkt) {
1992                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1993                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1994                                                &rss_hash_res);
1995                         if (!len) {
1996                                 rte_mbuf_raw_free(rep);
1997                                 break;
1998                         }
1999                         if (unlikely(len == -1)) {
2000                                 /* RX error, packet is likely too large. */
2001                                 rte_mbuf_raw_free(rep);
2002                                 ++rxq->stats.idropped;
2003                                 goto skip;
2004                         }
2005                         pkt = seg;
2006                         assert(len >= (rxq->crc_present << 2));
2007                         /* Update packet information. */
2008                         pkt->packet_type = 0;
2009                         pkt->ol_flags = 0;
2010                         if (rss_hash_res && rxq->rss_hash) {
2011                                 pkt->hash.rss = rss_hash_res;
2012                                 pkt->ol_flags = PKT_RX_RSS_HASH;
2013                         }
2014                         if (rxq->mark &&
2015                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2016                                 pkt->ol_flags |= PKT_RX_FDIR;
2017                                 if (cqe->sop_drop_qpn !=
2018                                     htonl(MLX5_FLOW_MARK_DEFAULT)) {
2019                                         uint32_t mark = cqe->sop_drop_qpn;
2020
2021                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2022                                         pkt->hash.fdir.hi =
2023                                                 mlx5_flow_mark_get(mark);
2024                                 }
2025                         }
2026                         if (rxq->csum | rxq->csum_l2tun) {
2027                                 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2028                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2029                         }
2030                         if (rxq->vlan_strip &&
2031                             (cqe->hdr_type_etc &
2032                              htons(MLX5_CQE_VLAN_STRIPPED))) {
2033                                 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2034                                         PKT_RX_VLAN_STRIPPED;
2035                                 pkt->vlan_tci = ntohs(cqe->vlan_info);
2036                         }
2037                         if (rxq->crc_present)
2038                                 len -= ETHER_CRC_LEN;
2039                         PKT_LEN(pkt) = len;
2040                 }
2041                 DATA_LEN(rep) = DATA_LEN(seg);
2042                 PKT_LEN(rep) = PKT_LEN(seg);
2043                 SET_DATA_OFF(rep, DATA_OFF(seg));
2044                 PORT(rep) = PORT(seg);
2045                 (*rxq->elts)[idx] = rep;
2046                 /*
2047                  * Fill NIC descriptor with the new buffer.  The lkey and size
2048                  * of the buffers are already known, only the buffer address
2049                  * changes.
2050                  */
2051                 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2052                 if (len > DATA_LEN(seg)) {
2053                         len -= DATA_LEN(seg);
2054                         ++NB_SEGS(pkt);
2055                         ++rq_ci;
2056                         continue;
2057                 }
2058                 DATA_LEN(seg) = len;
2059 #ifdef MLX5_PMD_SOFT_COUNTERS
2060                 /* Increment bytes counter. */
2061                 rxq->stats.ibytes += PKT_LEN(pkt);
2062 #endif
2063                 /* Return packet. */
2064                 *(pkts++) = pkt;
2065                 pkt = NULL;
2066                 --pkts_n;
2067                 ++i;
2068 skip:
2069                 /* Align consumer index to the next stride. */
2070                 rq_ci >>= sges_n;
2071                 ++rq_ci;
2072                 rq_ci <<= sges_n;
2073         }
2074         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2075                 return 0;
2076         /* Update the consumer index. */
2077         rxq->rq_ci = rq_ci >> sges_n;
2078         rte_wmb();
2079         *rxq->cq_db = htonl(rxq->cq_ci);
2080         rte_wmb();
2081         *rxq->rq_db = htonl(rxq->rq_ci);
2082 #ifdef MLX5_PMD_SOFT_COUNTERS
2083         /* Increment packets counter. */
2084         rxq->stats.ipackets += i;
2085 #endif
2086         return i;
2087 }
2088
2089 /**
2090  * Dummy DPDK callback for TX.
2091  *
2092  * This function is used to temporarily replace the real callback during
2093  * unsafe control operations on the queue, or in case of error.
2094  *
2095  * @param dpdk_txq
2096  *   Generic pointer to TX queue structure.
2097  * @param[in] pkts
2098  *   Packets to transmit.
2099  * @param pkts_n
2100  *   Number of packets in array.
2101  *
2102  * @return
2103  *   Number of packets successfully transmitted (<= pkts_n).
2104  */
2105 uint16_t
2106 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2107 {
2108         (void)dpdk_txq;
2109         (void)pkts;
2110         (void)pkts_n;
2111         return 0;
2112 }
2113
2114 /**
2115  * Dummy DPDK callback for RX.
2116  *
2117  * This function is used to temporarily replace the real callback during
2118  * unsafe control operations on the queue, or in case of error.
2119  *
2120  * @param dpdk_rxq
2121  *   Generic pointer to RX queue structure.
2122  * @param[out] pkts
2123  *   Array to store received packets.
2124  * @param pkts_n
2125  *   Maximum number of packets in array.
2126  *
2127  * @return
2128  *   Number of packets successfully received (<= pkts_n).
2129  */
2130 uint16_t
2131 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2132 {
2133         (void)dpdk_rxq;
2134         (void)pkts;
2135         (void)pkts_n;
2136         return 0;
2137 }